W78LE51C中文资料_数据手册_规格书

W78LE51C/W78L051C

8-BIT MICROCONTROLLER

Table of Contents-

1.

GENERAL DESCRIPTION ......................................................................................................... 2

FEATURES................................................................................................................................. 2

PIN CONFIGURATIONS ............................................................................................................ 3

PIN DESCRIPTION..................................................................................................................... 4

FUNCTIONAL DESCRIPTION ................................................................................................... 5

ON-CHIP FLASH EPROM CHARACTERISTICS..................................................................... 10

SECURITY BITS....................................................................................................................... 10

ABSOLUTE MAXIMUM RATINGS ........................................................................................... 11

DC CHARACTERISTICS.......................................................................................................... 12

AC CHARACTERISTICS.......................................................................................................... 14

TIMING WAVEFORMS............................................................................................................. 17

TYPICAL APPLICATION CIRCUITS ........................................................................................ 19

PACKAGE DIMENSIONS......................................................................................................... 21

REVISION HISTORY................................................................................................................ 23

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

Publication Release Date: December 4, 2006

- 1 -

Revision A3

W78LE51C/W78L051C

1. GENERAL DESCRIPTION

The W78L051C is an 8-bit microcontroller which can accommodate a wide supply voltage range with

low power consumption. The instruction set for the W78L051C is fully compatible with the standard

8051. The W78L051C contains an 4K bytes Flash EPROM; a 128 bytes RAM; four 8-bit bi-directional

and bit-addressable I/O ports; an additional 4-bit I/O port P4; two 16-bit timer/counters; a hardware

watchdog timer and a serial port. These peripherals are supported by seven sources two-level

interrupt capability. To facilitate programming and verification, the Flash EPROM inside the

W78L051C allows the program memory to be programmed and read electronically. Once the code is

confirmed, the user can protect the code for security.

The W78L051C microcontroller has two power reduction modes, idle mode and power-down mode,

both of which are software selectable. The idle mode turns off the processor clock but allows for

continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power

consumption. The external clock can be stopped at any time and in any state without affecting the

processor.

2. FEATURES

•

Fully static design 8-bit CMOS microcontroller

Wide supply voltage of 2.4V to 5.5V

128 bytes of on-chip scratchpad RAM

4 KB electrically erasable/programmable Flash EPROM

64 KB program memory address space

64 KB data memory address space

Four 8-bit bi-directional ports

•

One extra 4-bit bit-addressable I/O port, additional INT2 / INT3

(available on 44-pin PLCC/QFP package)

•

Two 16-bit timer/counters

One full duplex serial port (UART)

Watchdog Timer

seven sources, two-level interrupt capability

EMI reduction mode

Built-in power management

Code protection mechanism

Packages:

− Lead Free (RoHS) DIP 40: W78L051C24DL

− Lead Free (RoHS) PLCC 44: W78L051C24PL

− Lead Free (RoHS) PQFP 44: W78L051C24FL

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W78LE51C/W78L051C

3. PIN CONFIGURATIONS

Publication Release Date: December 4, 2006

Revision A3

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W78LE51C/W78L051C

4. PIN DESCRIPTION

SYMBOL

DESCRIPTIONS

EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of

external ROM. It should be kept high to access internal ROM. The ROM address and

EA

data will not be presented on the bus if EA pin is high and the program counter is

within on-chip ROM area.

PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0

address/ data bus during fetch and MOVC operations. When internal ROM access is

PSEN

performed, no PSEN strobe signal outputs from this pin.

ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates

the address from the data on Port 0.

ALE

RESET: A high on this pin for two machine cycles while the oscillator is running resets

the device.

RST

CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external

clock.

XTAL1

XTAL2

VSS

CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.

GROUND: Ground potential

VDD

POWER SUPPLY: Supply voltage for operation.

PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order

address/data bus during accesses to external memory. The Port 0 is also an open-

drain port and external pull-ups need to be connected while in programming.

P0.0−P0.7

PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate

functions which are described below:

P1.0−P1.7

P2.0−P2.7

T2(P1.0): Timer/Counter 2 external count input

T2EX(P1.1): Timer/Counter 2 Reload/Capture control

PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides

the upper address bits for accesses to external memory.

PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate

functions, which are described below:

RXD(P3.0) : Serial Port receiver input

TXD(P3.1) : Serial Port transmitter output

INT0 (P3.2) : External Interrupt 0

P3.0−P3.7

P4.0−P4.3

INT1(P3.3) : External Interrupt 1

T0(P3.4) : Timer 0 External Input

T1(P3.5) : Timer 1 External Input

WR(P3.6) :External Data Memory Write Strobe

RD(P3.7) : External Data Memory Read Strobe

PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative

function pins. It can be used as general I/O port or external interrupt input sources

(INT2 /INT3 ).

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W78LE51C/W78L051C

5. FUNCTIONAL DESCRIPTION

The W78L051C architecture consists of a core controller surrounded by various registers, five general

purpose I/O ports, 128 bytes of RAM, two timer/counters, and a serial port. The processor supports

111 different opcodes and references both a 64K program address space and a 64K data storage

space.

New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt

INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:

1. INT2 / INT3

Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external

interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are

determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is

bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To

set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,

"SETB 0C2H" sets the EX2 bit of XICON.

XICON - external interrupt control (C0H)

PX3

EX3

IE3

IT3

PX2

EX2

IE2

IT2

PX3: External interrupt 3 priority high if set

EX3: External interrupt 3 enable if set

IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced

IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software

PX2: External interrupt 2 priority high if set

EX2: External interrupt 2 enable if set

IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced

IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Eight-source interrupt informations:

POLLING

SEQUENCE WITHIN

PRIORITY LEVEL

ENABLE

REQUIRED

SETTINGS

VECTOR

ADDRESS

INTERRUPT TYPE

EDGE/LEVEL

INTERRUPT SOURCE

External Interrupt 0

Timer/Counter 0

External Interrupt 1

Timer/Counter 1

Serial Port

03H

0BH

13H

1BH

23H

33H

3BH

0 (highest)

IE.0

IE.1

TCON.0

1

-

2

IE.2

TCON.2

3

IE.3

-

4

5

IE.4

-

External Interrupt 2

External Interrupt 3

XICON.2

XICON.6

XICON.0

XICON.3

6 (lowest)

Publication Release Date: December 4, 2006

Revision A3

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W78LE51C/W78L051C

2. PORT4

Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port

address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are

alternative function pins. It can be used as general I/O pins or external interrupt input sources (INT2 ,

INT3 ).

Example:

P4

REG 0D8H

P4, #0AH

A, P4

P4.#00000001B ; Set P4.0 to be high state

P4.#11111110B ; Clear P4.0 to be low state.

MOV

ORL

ANL

; Output data "A" through P4.0−P4.3.

; Read P4 status to Accumulator.

3. Reduce EMI Emission

Because of on-chip Flash EPROM, when a program is running in internal ROM space, the ALE will be

unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it

is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which

is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external

ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it

has been completely accessed or the program returns to internal ROM code space. The AO bit in the

AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation

circuitry, W78L051C allows user to diminish the gain of on-chip oscillator amplifiers by using

programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be

decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a

half of gain may effect to external crystal operating improperly at high frequency above 20 MHz. The

value of R and C1, C2 may need some adjustment while running at lower gain.

***AUXR - Auxiliary register (8EH)

-

AO

AO: Turn off ALE output.

4. Power-off Flag

***PCON - Power control (87H)

-

GF1

GF0

PD

IDL

-

POF

POF:

Power off flag. Bit is set by hardware when power on reset. It can be cleared by software

to determine chip reset is a warm boot or cold boot.

GF1, GF0: These two bits are general-purpose flag bits for the user.

PD:

IDL:

Power down mode bit. Set it to enter power down mode.

Idle mode bit. Set it to enter idle mode.

The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can

be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.

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W78LE51C/W78L051C

Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a

system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the

system clock. The divider output is selectable and determines the time-out interval. When the time-out

occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a

system monitor. This is important in real-time control applications. In case of power glitches or electro-

magnetic interference, the processor may begin to execute errant code. If this is left unchecked the

entire system may crash. The watchdog time-out selection will result in different time-out values

depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software

should restart the Watchdog timer to put it into a known state. The control bits that support the

Watchdog timer are discussed below.

Watchdog Timer Control Register

Bit:

7

6

5

4

-

3

-

2

1

0

ENW CLRW WIDL

Mnemonic: WDTC

PS2

PS1

PS0

Address: 8FH

ENW : Enable watch-dog if set.

CLRW: Clear watch-dog timer and prescaler if set. This flag will be cleared automatically

WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled

under IDLE mode. Default is cleared.

PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2−0 as follows:

PS2 PS1 PS0

PRESCALER SELECT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

256

The time-out period is obtained using the following equation:

1

× 2¹⁴×PRESCALER×1000×12 mS

OSC

Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6

(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next

instruction cycle. The Watchdog timer is cleared on reset.

Publication Release Date: December 4, 2006

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Revision A3

W78LE51C/W78L051C

ENW

WIDL

IDLE

EXTERNAL

RESET

INTERNAL

RESET

14-BIT TIMER

CLEAR

PRESCALER

OSC

1/12

CLRW

Watchdog Timer Block Diagram

Typical Watch-Dog time-out period when OSC = 20 MHz

PS2 PS1 PS0

WATCHDOG TIME-OUT PERIOD

19.66 mS

0

1

0

1

0

1

0

1

0

1

0

1

0

1

39.32 mS

78.64 mS

157.28 mS

314.57mS

629.14 mS

1.25 S

2.50 S

Clock

The W78L051C is designed to be used with either a crystal oscillator or an external clock. Internally,

the clock is divided by two before it is used. This makes the W78L051C relatively insensitive to duty

cycle variations in the clock. The W78L051C incorporates a built-in crystal oscillator. To make the

oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load

capacitor must be connected from each pin to ground. An external clock source should be connected

to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as

required by the crystal oscillator.

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W78LE51C/W78L051C

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal

clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The

processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this

mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is

by a reset.

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two

machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to

deglitch the reset line when the W78L051C is used with an external RC network. The reset logic also

has a special glitch removal circuit that ignores glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit

4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

Publication Release Date: December 4, 2006

- 9 -

Revision A3

W78LE51C/W78L051C

6. ON-CHIP FLASH EPROM CHARACTERISTICS

7. SECURITY BITS

During the on-chip Flash EPROM operation mode, the Flash EPROM can be programmed and

verified repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be

protected. The protection of Flash EPROM and those operations on it are described below. The

W78L051C has a Special Setting Register, the Security Register, which can not be accessed in

normal mode. The Security register can only be accessed from the Flash EPROM operation mode.

Those bits of the Security Registers can not be changed once they have been programmed from high

to low. They can only be reset through erase-all operation. The Security Register is addressed in the

Flash EPROM operation mode by address #0FFFFh.

D7 D6 D5 D4 D3 D2 D1 D0

Security Bits

0000h

0FFFh

4KB Flash EPROM

Program Memory

Reserved B2 B1 B0

B7

B0 : Lock bit, logic 0 : active

B1 : MOVC inhibit,

logic 0 : the MOVC instruction in external memory

cannot access the code in internal memory.

logic 1 : no restriction.

Reserved

B2 : Encryption

logic 0 : the encryption logic enable

logic 1 : the encryption logic disable

B7 : Osillator Control

logic 0 : 1/2 gain

logic 1 : Full gain

Security Register

0FFFFh

Default 1 for all security bits.

Reserved bits must be kept in logic 1.

Special Setting Register

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W78LE51C/W78L051C

Lock bit

This bit is used to protect the customer's program code in the W78L051C. It may be set after the

programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the

Flash EPROM data and Special Setting Registers can not be accessed again.

MOVC Inhibit

This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC

instruction in external program memory from reading the internal program code. When this bit is set to

logic 0, a MOVC instruction in external program memory space will be able to access code only in the

external memory, not in the internal memory. A MOVC instruction in internal program memory space

will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,

there are no restrictions on the MOVC instruction.

Encryption

This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is

enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will

reset this bit.

8. ABSOLUTE MAXIMUM RATINGS

PARAMETER

DC Power Supply

SYMBOL

VDD−VSS

VIN

MIN.

-0.3

MAX.

+7.0

UNIT

V

Input Voltage

VSS -0.3

0

VDD +0.3

70

V

Operating Temperature

Storage Temperature

TA

°C

TST

-55

+150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

Publication Release Date: December 4, 2006

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Revision A3

W78LE51C/W78L051C

9. DC CHARACTERISTICS

VSS = 0V, TA = 25° C, unless otherwise specified.

SPECIFICATION

PARAMETER

Operating Voltage

Operating Current

SYM.

VDD

IDD

UNIT

TEST CONDITIONS

MIN.

MAX.

5.5

20

3

2.4

V

-

mA

μA

No load VDD = 5.5V

No load VDD = 2.4V

6

VDD = 5.5V, FOSC = 20 MHz

VDD = 2.4V, FOSC = 12 MHz

VDD = 5.5V, FOSC = 20 MHz

Idle Current

IIDLE

1.5

50

20

Power Down Current

IPWDN

VDD = 2.4V, FOSC = 12 MHz

VDD = 5.5V

μA

Input Current

P1, P2, P3, P4

Input Current

RST

IIN1

IIN2

-50

-10

+10

+300

+10

μA

VIN = 0V or VDD

VDD = 5.5V

0 < VIN < VDD

Input Leakage Current

VDD = 5.5V

ILK

0V < VIN < VDD

P0, EA

Logic 1 to 0 Transition

Current

VDD = 5.5V

VIN = 2.0V

ITL [*4]

-500

-

μA

P1, P2, P3, P4

Input Low Voltage

P0, P1, P2, P3, P4,

EA

0

0.8

0.5

V

VDD = 4.5V

VDD = 2.4V

VIL1

Input Low Voltage

RST[*1]

0

0.8

0.3

0.8

0.6

V

VDD = 4.5V

VDD = 2.4V

VDD = 4.5V

VDD = 2.4V

VIL2

VIL3

Input Low Voltage

XTAL1 [*3]

VDD

+0.2

Input High Voltage

2.4

1.4

3.5

1.7

3.5

1.6

V

VDD = 5.5V

VDD = 2.4V

VDD = 5.5V

VDD = 2.4V

VDD = 5.5V

VDD = 2.4V

VIH1

VIH2

VIH3

VDD

+0.2

P0, P1, P2, P3, P4,EA

Input High Voltage

RST[*1]

VDD

+0.2

VDD

+0.2

VDD

+0.2

Input High Voltage

XTAL1 [*3]

VDD

+0.2

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W78LE51C/W78L051C

DC Characteristics, continued

SPECIFICATION

PARAMETER

SYM.

VOL1

VOL2

ISK1

UNIT

TEST CONDITIONS

MIN.

MAX.

0.45

0.25

0.45

Output Low Voltage

P1, P2, P3, P4

-

V

VDD = 4.5V, IOL = +2 mA

VDD = 2.4V, IOL = +1 mA

VDD = 4.5V, IOL = +4 mA

Output Low Voltage

-

0.25

V

VDD = 2.4V, IOL = +2 mA

P0, ALE, PSEN [*2]

Sink Current

4

1.8

8

12

5.4

16

mA

VDD = 4.5V, Vin = 0.45V

VDD = 2.4V, Vin = 0.45V

VDD = 4.5V, Vin = 0.45V

P1, P2, P3, P4

Sink Current

ISK2

4.5

2.4

1.4

2.4

1.4

9

-

mA

V

VDD = 2.4V, Vin = 0.45V

P0, ALE, PSEN

Output High Voltage

P1, P2, P3, P4

VDD = 4.5V, IOH = -100 μA

VDD = 2.4V, IOH = -8 μA

VDD = 4.5V, IOH = -400 μA

VOH1

VOH2

ISR1

-

V

Output High Voltage

-

V

-

V

VDD = 2.4V, IOH = -200 μA

VDD = 4.5V, Vin = 2.4V

VDD = 2.4V, Vin = 1.4V

VDD = 4.5V, Vin = 2.4V

VDD = 2.4V, Vin = 1.4V

P0, ALE, PSEN [*2]

Source Current

P1, P2, P3, P4

-100

-20

-8

-250

-50

μA

mA

Source Current

-14

ISR2

-1.9

-3.8

mA

P0, ALE, PSEN

Notes:

*1. RST pin is a Schmitt trigger input.

*2. P0, ALE and /PSEN are tested in the external access mode.

*3. XTAL1 is a CMOS input.

*4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0.

Publication Release Date: December 4, 2006

Revision A3

- 13 -

W78LE51C/W78L051C

10. AC CHARACTERISTICS

The AC specifications are a function of the particular process used to manufacture the part, the ratings

of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications

can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually

experience less than a ±20 nS variation. The numbers below represent the performance expected

from a 0.6micron CMOS process when using 2 and 4 mA output buffers.

Clock Input Waveform

XTAL1

T_CH

T_CL

F_OP,

T_CP

PARAMETER

Operating Speed

SYMBOL

FOP

MIN.

0

TYP.

MAX.

UNIT

MHz

nS

NOTES

-

20

-

1

2

3

Clock Period

Clock High

Clock Low

TCP

50

25

TCH

-

nS

TCL

-

nS

Notes:

1. The clock may be stopped indefinitely in either state.

2. The TCP specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

Program Fetch Cycle

PARAMETER

SYMBOL

TAAS

MIN.

TYP.

MAX.

UNIT

nS

NOTES

Address Valid to ALE Low

Address Hold from ALE Low

-

4

1, 4

4

1 TCP -Δ

-

TAAH

nS

TAPL

TPDA

TPDH

TPDZ

TALW

TPSW

nS

ALE Low to PSEN Low

-

2 TCP

nS

2

3

PSEN Low to Data Valid

Data Hold after PSEN High

Data Float after PSEN High

ALE Pulse Width

0

-

1 TCP

0

-

1 TCP

2 TCP

3 TCP

-

4

2 TCP -Δ

3 TCP -Δ

PSEN Pulse Width

Notes:

1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 TCP.

3. Data have been latched internally prior to PSEN going high.

4. "Δ" (due to buffer driving delay and wire loading) is 20 nS.

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W78LE51C/W78L051C

Data Read Cycle

PARAMETER

SYMBOL

TDAR

MIN.

TYP.

MAX.

3 TCP +Δ

4 TCP

2 TCP

-

UNIT

nS

NOTES

1, 2

1

-

3 TCP -Δ

ALE Low to RD Low

RD Low to Data Valid

Data Hold from RD High

Data Float from RD High

RD Pulse Width

TDDA

-

nS

TDDH

0

-

nS

TDDZ

nS

TDRD

6 TCP

nS

2

6 TCP -Δ

Notes:

1. Data memory access time is 8 TCP.

2. "Δ" (due to buffer driving delay and wire loading) is 20 nS.

Data Write Cycle

PARAMETER

ALE Low to WR Low

Data Valid to WR Low

Data Hold from WR High

WR Pulse Width

SYMBOL

MIN.

TYP.

MAX.

UNIT

nS

TDAW

TDAD

TDWD

TDWR

-

3 TCP -Δ

1 TCP -Δ

6 TCP -Δ

3 TCP +Δ

-

nS

6 TCP

nS

Note: "Δ" (due to buffer driving delay and wire loading) is 20 nS.

Port Access Cycle

PARAMETER

Port Input Setup to ALE Low

Port Input Hold from ALE Low

Port Output to ALE

SYMBOL

TPDS

MIN.

1 TCP

0

TYP.

MAX.

UNIT

nS

-

TPDH

nS

TPDA

1 TCP

nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

Publication Release Date: December 4, 2006

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Revision A3

W78LE51C/W78L051C

Program Operation

PARAMETER

SYMBOL

TVPS

TDS

MIN.

2.0

0

TYP.

MAX.

UNIT

μS

VPP Setup Time

Data Setup Time

Data Hold Time

-

TDH

-

Address Setup Time

Address Hold Time

TAS

-

TAH

-

TPWP

TOCS

TOCH

TOES

290

2.0

300

310

CE Program Pulse Width for Program Operation

OECTRL Setup Time

-

OECTRL Hold Time

OE Setup Time

TDFP

TOEV

0

-

130

150

nS

OE High to Output Float

Data Valid from OE

Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status,

and the PSEN pin must pull in VIH status.

- 16 -

W78LE51C/W78L051C

11. TIMING WAVEFORMS

Program Fetch Cycle

S1

S2

S3

S4

S5

S6

S1

S2

S3

S4

S5

S6

XTAL1

ALE

T_ALW

T_APL

PSEN

T_PSW

T_AAS

PORT 2

PORT 0

T_PDA

T_AAH

T_PDH,T_PDZ

A0-A7

Code

A0-A7

Code

Data

A0-A7

Data Read Cycle

S4

S5

S6

S1

S2

S3

S4

S5

S6

S1

S2

S3

XTAL1

ALE

PSEN

PORT 2

A8-A15

DATA

A0-A7

PORT 0

RD

T_DAR

T_DDA

T_DDH,T_DDZ

T_DRD

Publication Release Date: December 4, 2006

Revision A3

- 17 -

W78LE51C/W78L051C

Data Write Cycle

S4

S5

S6

S1

S2

S3

S4

S5

S6

S1

S2

S3

XTAL1

ALE

PSEN

A8-A15

PORT 2

PORT 0

WR

A0-A7

DATA OUT

T

DWD

T

DAD

T

DWR

DAW

Port Access Cycle

S5

S6

S1

XTAL1

ALE

T_PDS

T_PDH

T_PDA

PORT

DATA OUT

INPUT

SAMPLE

- 18 -

W78LE51C/W78L051C

12. TYPICAL APPLICATION CIRCUITS

Expanded External Program Memory and Crystal

V

DD

V

DD

31

19

AD0

39

AD0

3

4

7

8

11

12

13

15

16

17

18

19

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

2

5

A0

A1

A2

A3

A4

A0

A1

A2

A3

A4

A5

A6

A7

A8 25

A9 24

A10

A11

A12

A13

A14

A15

10

9

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

A0

O0

O1

O2

O3

O4

O5

O6

O7

EA

38 AD1

37 AD2

36 AD3

AD1

AD2

AD3

A1

6

8

A2

XTAL1

9

12

15 A5

16

19

10 u

7

A3

AD4

AD5

AD6

AD7

35

34

33

32

AD4 13

14

AD6 17

AD7 18

6

A4

R

18

9

AD5

5

XTAL2

RST

A5

CRYSTAL

A6

A7

4

A6

3

A7

8.2 K

A8

1

GND

A8

A9

21

22

23

24

25

26

27

28

OC

G

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

A9

C1

C2

21

23

2

26

27

1

11

A10

A11

A12

A13

A14

A15

INT0

12

13

14

15

A10

A11

A12

A13

A14

A15

INT1

T0

T1

74373

1

2

3

4

5

6

7

8

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

GND

20

22

CE

OE

RD

WR

PSEN

ALE

TXD

17

16

29

30

11

10

27512

RXD

W78LE51C/W78L051C

Figure A

CRYSTAL

16 MHz

20 MHz

C1

C2

R

-

30P

15P

30P

15P

-

Above table shows the reference values for crystal applications (full gain).

Note: C1, C2, R components refer to Figure A.

Publication Release Date: December 4, 2006

Revision A3

- 19 -

W78LE51C/W78L051C

Expanded External Data Memory and Oscillator

V

DD

V

DD

31

19

AD0

AD1

AD2

AD3

AD4

AD5 14

AD6 17

AD7 18

3

4

7

8

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

A0

A1

A2

A3

A4

A5

A6

A7

10

9

11

12

13

15

16

17

18

19

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

A0

A1

A2

A3

39 AD0

AD1

2

5

6

9

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

D0

D1

D2

D3

D4

D5

D6

D7

EA

38

8

37 AD2

36 AD3

XTAL1

OSCILLATOR

10 u

7

13

AD4

AD5

35

34

6

12 A4

15 A5

18

9

5

XTAL2

33 AD6

32 AD7

A6

4

16

19 A7

8.2 K

3

A8 25

A9 24

RST

INT0

GND

1

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

21

A8

A9

OC

G

11

21

23

2

A10

A11

A12

22

23

24

25

26

27

28

A10

A11

A12

A13

12

13

14

15

A10

A11

A12

A13

A14

74373

INT1

T0

T1

A13 26

1

A14

GND

CE

20

22

27

1

2

3

4

5

6

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

OE

RD

17

16

29

30

11

10

WR

20256

PSEN

ALE

TXD

RXD

7

8

W78LE51C/W78L051C

Figure B

- 20 -

W78LE51C/W78L051C

13. PACKAGE DIMENSIONS

40-pin DIP

Dimension in inch Dimension in mm

Symbol

Min. Nom. Max. Min. Nom. Max.

5.334

0.210

A

B

c

D

E

e

L

a

0.010

0.150 0.155 0.160

0.254

3.81

1

2

3.937 4.064

0.016 0.018

0.406 0.457 0.559

1.219 1.27 1.372

0.203 0.254 0.356

0.022

0.054

0.050

0.010

2.055

0.048

0.008

1

0.014

D

2.070

52.58

15.494

13.97

2.794

3.556

15

52.20

15.24

40

21

0.610

0.590 0.600

14.986

13.72 13.84

0.540

0.545 0.550

1

0.110

0.090 0.100

2.286

3.048

0

2.54

0.120 0.130 0.140

15

3.302

1

E

0

0.630 0.650 0.670 16.00 16.51 17.01

0.090

e

S

A

2.286

1

20

Notes:

E

1. Dimension D Max. & S include mold flash or

tie bar burrs.

S

c

2. Dimension E1 does not include interlead flash.

3. Dimension D & E1 include mold mismatch and

are determined at the mold parting line.

A²

A

L

Base Plane

1

A

.

Seating Plane

4. Dimension B1 does not include dambar

protrusion/intrusion.

B

e₁

e_A

5. Controlling dimension: Inches.

6. General appearance spec. should be based on

final visual inspection spec.

a

B ₁

44-pin PLCC

H _D

D

1

6

44

40

Dimension in inch Dimension in mm

Min. Nom. Max. Min. Nom. Max.

Symbol

7

39

0.185

4.699

A

A₂

b ₁

b

0.020

0.508

1

0.145 0.150 0.155 3.683 3.81 3.937

0.026 0.028

0.016 0.018

0.032 0.66

0.406

0.813

0.559

0.356

0.711

0.457

0.022

H_E

GE

E

0.008 0.010 0.014 0.203 0.254

c

16.46 16.59 16.71

1.27 BSC

0.648 0.653 0.658

D

E

e

0.648 0.653

0.658

0.050 BSC

0.590

0.680

14.99 15.49 16.00

17.27 17.53 17.78

17

29

0.610

0.630

G_D

0.610 0.630

0.690 0.700

G

H

E

D

E

18

28

c

H

L

y

0.090 0.100

2.54 2.794

0.10

0.110 2.296

0.004

L

Notes:

A²

A

1. Dimension D & E do not include interlead

flash.

2. Dimension b1 does not include dambar

protrusion/intrusion.

θ

e

b

A¹

3. Controlling dimension: Inches

4. General appearance spec. should be based

on final visual inspection spec.

b ¹

Seating Plane

y

G _D

Publication Release Date: December 4, 2006

Revision A3

- 21 -

W78LE51C/W78L051C

44-pin PQFP

H _D

D

Dimension in inch

Dimension in mm

Symbol

A

Min. Nom. Max. Min. Nom. Max.

34

44

---

0.5

0.002

0.01

0.02

0.25

2.05

0.05

1.90

1

A

0.075 0.081 0.087

2.20

0.45

A₂

b

c

D

E

e

33

1

0.01

0.014

0.006

0.394

0.031

0.25

0.018

0.010

0.398

0.036

0.530

0.35

0.101 0.152 0.254

0.004

0.390

10.00

0.80

9.9

10.1

0.390

0.025

E

H^E

0.952

13.45

0.95

0.635

12.95

0.65

0.510 0.520

13.2

0.8

H

D

E

0.520 0.530

0.025 0.031

0.510

H

L

y

11

0.037

0.051 0.063 0.075 1.295

1.6

1.905

0.08

7

1

0.003

7

12

22

e

b

θ

0

Notes:

1. Dimension D & E do not include interlead

flash.

c

2. Dimension b does not include dambar

protrusion/intrusion.

3. Controlling dimension: Millimeter

4. General appearance spec. should be based

on final visual inspection spec.

A

A₂

A₁

θ

L

See Detail F

y

Seating Plane

L

1

Detail F

- 22 -

W78LE51C/W78L051C

14. REVISION HISTORY

VERSION

DATE

PAGE

REASONS FOR CHANGE

A1

May 19, 2005

Initial Issued

Remove block diagram

A2

A3

October 2, 2006

Change operating frequency into 20MHz

Remove all Leaded package parts

December 4, 2006

2

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

Publication Release Date: December 4, 2006

- 23 -

Revision A3

型号	制造商	描述	价格	文档
W78LE51C-24	WINBOND	Microcontroller, 8-Bit, FLASH, 8051 CPU, 20MHz, CMOS, PDIP40, DIP-40	获取价格
W78LE51CF-24	WINBOND	Microcontroller, 8-Bit, FLASH, 8051 CPU, 20MHz, CMOS, PQFP44, PLASTIC, QFP-44	获取价格
W78LE51CP-24	WINBOND	Microcontroller, 8-Bit, FLASH, 8051 CPU, 20MHz, CMOS, PQCC44, PLASTIC, LCC-44	获取价格
W78LE51F-24	WINBOND	8-BIT MTP MICROCONTROLLER	获取价格
W78LE51P-24	WINBOND	8-BIT MTP MICROCONTROLLER	获取价格
W78LE51_06	WINBOND	8-BIT MICROCONTROLLER	获取价格
W78LE52	WINBOND	8-BIT MTP MICROCONTROLLER	获取价格
W78LE52-24	WINBOND	8-BIT MTP MICROCONTROLLER	获取价格
W78LE52C	WINBOND	8-BIT MICROCONTROLLER	获取价格
W78LE52C-24	WINBOND	Microcontroller, 8-Bit, FLASH, 8051 CPU, 20MHz, CMOS, PDIP40, DIP-40	获取价格

W78LE51C

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