W79E342 [WINBOND]
Preliminary W79E342 datasheet v0.6; 初步W79E342数据手册V0.6
| 型号： | W79E342 |
| 厂家： | 
WINBOND |
| 描述： | Preliminary W79E342 datasheet v0.6 |
| 文件： | 总89页 (文件大小：1431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY W79E342 DATA SHEET
8-BIT MICROCONTROLLER
Table of Contents-
1
2
3
GENERAL DESCRIPTION ......................................................................................................................4
FEATURES.................................................................................................................................................4
PARTS INFORMATION LIST..................................................................................................................5
LEAD FREE (ROHS) PARTS INFORMATION LIST.......................................................................................5
PIN CONFIGURATION.............................................................................................................................6
PIN DESCRIPTIONS.................................................................................................................................7
FUNCTIONAL DESCRIPTION................................................................................................................9
3.1
4
5
6
6.1
6.2
6.3
6.4
6.5
6.6
ON-CHIP FLASH EPROM ........................................................................................................................9
I/O PORTS ................................................................................................................................................9
TIMERS......................................................................................................................................................9
INTERRUPTS..............................................................................................................................................9
DATA POINTERS .......................................................................................................................................9
ARCHITECTURE.......................................................................................................................................10
6.6.1
6.6.2
ALU ................................................................................................................................................10
Accumulator..................................................................................................................................10
B Register......................................................................................................................................10
Program Status Word:.................................................................................................................10
Scratch-pad RAM.........................................................................................................................10
Stack Pointer.................................................................................................................................10
6.6.3
6.6.4
6.6.5
6.6.6
6.7
POWER MANAGEMENT ...........................................................................................................................10
7
MEMORY ORGANIZATION...................................................................................................................11
7.1
7.2
7.3
7.4
PROGRAM MEMORY (ON-CHIP FLASH)...................................................................................................11
DATA FLASH MEMORY............................................................................................................................11
DATA MEMORY (ACCESSED BY MOVX)................................................................................................11
SCRATCH-PAD RAM AND REGISTER MAP .............................................................................................11
7.4.1
7.4.2
7.4.3
Working Registers........................................................................................................................13
Bit addressable Locations...........................................................................................................14
Stack ..............................................................................................................................................14
8
9
SPECIAL FUNCTION REGISTERS .....................................................................................................15
INSTRUCTION SET................................................................................................................................35
INSTRUCTION TIMING..............................................................................................................................42
POWER MANAGEMENT.......................................................................................................................45
9.1
10
10.1 IDLE MODE..............................................................................................................................................45
10.2 POWER DOWN MODE .............................................................................................................................45
11
RESET CONDITIONS.............................................................................................................................46
11.1 SOURCES OF RESET ...............................................................................................................................46
11.1.1 External Reset ..............................................................................................................................47
11.1.2 Power-On Reset (POR)...............................................................................................................47
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11.1.3 Watchdog Timer Reset................................................................................................................47
11.2 RESET STATE .........................................................................................................................................48
12
INTERRUPTS...........................................................................................................................................49
12.1 INTERRUPT SOURCES.............................................................................................................................49
12.2 PRIORITY LEVEL STRUCTURE ................................................................................................................50
12.3 RESPONSE TIME.....................................................................................................................................51
12.4 INTERRUPT INPUTS.................................................................................................................................52
13
PROGRAMMABLE TIMERS/COUNTERS..........................................................................................54
13.1 TIMER/COUNTERS 0 & 1.........................................................................................................................54
13.1.1 Time-Base Selection....................................................................................................................54
13.1.2 Mode 0...........................................................................................................................................54
13.1.3 Mode 1...........................................................................................................................................55
13.1.4 Mode 2...........................................................................................................................................55
13.1.5 Mode 3...........................................................................................................................................56
14
15
NVM MEMORY ........................................................................................................................................57
WATCHDOG TIMER...............................................................................................................................58
15.1 WATCHDOG CONTROL ....................................................................................................................59
15.2 CLOCK CONTROL OF WATCHDOG ....................................................................................................59
16
TIME ACCESS PROCTECTION...........................................................................................................61
KEYBOARD INTERRUPT (KBI)...........................................................................................................63
I/O PORT CONFIGURATION................................................................................................................64
17
18
18.1 QUASI-BIDIRECTIONAL OUTPUT CONFIGURATION.................................................................................64
18.2 OPEN DRAIN OUTPUT CONFIGURATION.................................................................................................65
18.3 PUSH-PULL OUTPUT CONFIGURATION ..................................................................................................66
18.4 INPUT ONLY CONFIGURATION ................................................................................................................66
19
OSCILLATOR ..........................................................................................................................................67
19.1 ON-CHIP RC OSCILLATOR OPTION .......................................................................................................67
19.2 EXTERNAL CLOCK INPUT OPTION ..........................................................................................................67
19.3 CPU CLOCK RATE SELECT ....................................................................................................................67
19.4 CLOCK SOURCE CONTROL.....................................................................................................................68
20
21
BUZZER OUTPUT...................................................................................................................................69
POWER MONITORING FUNCTION.....................................................................................................72
21.1 POWER ON DETECT ...............................................................................................................................72
21.2 BROWNOUT DETECT...............................................................................................................................72
22
ANALOG-TO-DIGITAL CONVERTER.................................................................................................73
22.1 ADC RESOLUTION AND ANALOG SUPPLY: ............................................................................................74
23
24
ICP (IN-CIRCUIT PROGRAM) FLASH PROGRAM ..........................................................................76
CONFIG BITS...........................................................................................................................................77
24.1 CONFIG0 ..............................................................................................................................................77
24.2 CONFIG1 ..............................................................................................................................................78
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25
ELECTRICAL CHARACTERISTICS....................................................................................................79
25.1 ABSOLUTE MAXIMUM RATINGS ..............................................................................................................79
25.2 DC ELECTRICAL CHARACTERISTICS...........................................................................................80
25.3 THE ADC CONVERTER DC ELECTRICAL CHARACTERISTICS ....................................................83
25.4 AC ELECTRICAL CHARACTERISTICS...........................................................................................83
25.5 EXTERNAL CLOCK CHARACTERISTICS ......................................................................................84
25.6 AC SPECIFICATION ...........................................................................................................................85
25.7 TYPICAL APPLICATION CIRCUITS.................................................................................................85
26
PACKAGE DIMENSIONS......................................................................................................................86
26.1 16-PIN SOP............................................................................................................................................86
26.2 16-PIN DIP..............................................................................................................................................87
27
REVISION HISTORY ..............................................................................................................................88
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PRELIMINARY W79E342 DATA SHEET
1
GENERAL DESCRIPTION
The W79E342 series are an 8-bit 4T-8051 microcontroller which has Flash EPROM which is
programmable by ICP (In Circuit Program) or by hardware writer. The instruction set of the W79E342
series are fully compatible with the standard 8052. The W79E342 series contain 2K bytes of main
Flash EPROM; 128 bytes of RAM; two 16-bit timer/counters; 5 KBI inputs; 4-channel multiplexed 10-bit
A/D convert. The W79E342 series supports 128 bytes NVM Data Flash EPROM. These peripherals
are supported by 8 sources four-level interrupt capability. To facilitate programming and verification,
the Flash EPROM inside the W79E342 series allow the program memory to be programmed and read
electronically. Once the code is confirmed, the user can protect the code for security. This product
series consist of on-chip internal oscillator that runs at 455KHz to provide better power saving.
2
z
z
z
FEATURES
Fully static design 8-bit 4T-8051 CMOS microcontroller up to 8MHz when VDD=2.4V to 5.5V.
Instruction-set compatible with MSC-51.
CPU clock source configurable by option bit and software:
External oscillator: upto 8MHz.
External crystal: 4MHz~8MHz or 32KHz ~1MHz, selectable by option bit.
On-chip oscillator: 455KHz with ±2% accuracy, at fixed voltage and temperature condition.
CPU clock source from external or on-chip oscillator is selectable by software.
z
z
z
z
z
z
z
z
z
z
2K bytes of AP Flash EPROM, with ICP and external writer programmable mode.
128 bytes of on-chip RAM.
128 bytes NVM Data Flash EPROM.
Up to 14 I/O pins.
Eight interrupts source with four levels of priority.
The 4 outputs mode and TTL/Schmitt trigger selectable Port.
Four-channel multiplexed with 10-bits A/D converter.
Low Voltage Detect interrupt and reset.
Two 16-bit timer/counters.
Programmable Watchdog Timer (clock source supported by internal 20KHz RC oscillator and
upto 8MHz external crystal, selectable by option bit).
z
z
z
z
Five-keypad interrupt inputs.
Internal square wave generator for buzzer.
LED drive capability (20mA) on all port pins. Sink 20mA; Drive: -15~-20mA @push-pull mode.
Development Tools:
ICP(In Circuit Programming) writer
z
Packages:
- Lead Free (RoHS) DIP 16:
- Lead Free (RoHS) SOP 16:
W79E342ASK
W79E342ASG
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PRELIMINARY W79E342 DATA SHEET
3
PARTS INFORMATION LIST
3.1 Lead Free (RoHS) Parts information list
EPROM
FLASH SIZE
NVM FLASH
EPROM
PART NO.
RAM
PACKAGE
REMARK
W79E342ASG
W79E342ASK
2K
2K
128B
128B
128B
128B
SOP 16
DIP 16
Table 3-1: Lead Free (RoHS) Parts information list
Publication Release Date: April 08, 2008
Revision A6
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PRELIMINARY W79E342 DATA SHEET
4
PIN CONFIGURATION
Figure 4-1: Pin Configuration
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PRELIMINARY W79E342 DATA SHEET
5
PIN DESCRIPTIONS
Symbol
VDD
Alternate Alternate Alternate
Function 1 Function 2 Function 3 Function 4
(ICP mode)
Alternate
Type Descriptions
P
POWER SUPPLY: Supply
voltage for operation.
GROUND: Ground potential.
Port0:
VSS
P0.3
P0.4
P0.5
P0.6
P0.7
P
AD0
AD1
AD2
AD3
/KB3
/KB4
/KB5
/KB6
/KB7
I/O
I/O
I/O
I/O
I/O
Support 4 output modes and
TTL/Schmitt trigger.
Data
Clock
Multifunction pins for T1, AD0-3,
/KB3-7, Data and Clock (for
ICP).
T1
T0
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
BUZ
I/O
I/O
I/O
I/O
I/O
I
Port1:
Support 4 output modes and
TTL/Schmitt trigger (except for
P1.5 input only).
/INT0
/INT1
Multifunction pins for /RST, T0,
/INT0-1, BUZ, STADC, and HV
(for ICP).
STADC
RST
HV
P1.6
P2.0
I/O
I/O
XTAL2/CLKOUT
CRYSTAL2: This is the crystal
oscillator output. It is the
inversion of XTAL1. Also a
configurable i/o pin.
When operating as i/o, it
supports 4 output modes and
TTL/Schmitt trigger.
P2.1
XTAL1
I/O
CRYSTAL1: This is the crystal
oscillator input. This pin may be
driven by an external clock or
configurable i/o pin.
When operating as i/o, it
supports 4 output modes and
TTL/Schmitt trigger.
* TYPE: P: power, I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open-drain.
Table 5-1: Pin Descriptions
Note:
1. On power-on-reset, all port pins will be tri-stated.
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PRELIMINARY W79E342 DATA SHEET
2. After power-on-reset, all port pins state will follow CONFIG0.PRHI bit definition.
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PRELIMINARY W79E342 DATA SHEET
6
FUNCTIONAL DESCRIPTION
The W79E342 series architecture consist of a 4T 8051 core controller surrounded by various registers,
2K bytes Flash EPROM, 128 bytes of RAM, up to 14 general purpose I/O ports, two timer/counters, 5
KBI inputs, 4-channel multiplexed with 10-bit ADC analog input, Flash EPROM program by Writer and
ICP. W79E342 series supports 128 bytes NVM Data Flash EPROM.
6.1 On-Chip Flash EPROM
The W79E342 series include one 2K bytes of main Flash EPROM for application program. A Writer or
ICP programming board is required to program the Flash EPROM or NVM Data Flash EPROM.
This ICP (In-Circuit Programming) feature makes the job easy and efficient when the application’s
firmware needs to be updated frequently. In some applications, the in-circuit programming feature
makes it possible for the end-user to easily update the system firmware without opening the chassis.
6.2 I/O Ports
The W79E342 series have up to 14 I/O pins using on-chip oscillator & /RST is input only by reset
options. All ports can be used as four outputs mode when it may set by PxM1.y and PxM2.y SFR’s
registers, it has strong pull-ups and pull-downs, and does not need any external pull-ups. Otherwise it
can be used as general I/O port as open drain circuit. All ports can be used bi-directional and these are
as I/O ports. These ports are not true I/O, but rather are pseudo-I/O ports. This is because these ports
have strong pull-downs and weak pull-ups.
6.3 Timers
The W79E342 series have two 16-bit timers that are functionally and similar to the timers of the 8052
family. When used as timers, the user has a choice of 12 or 4 clocks per count that emulates the timing
of the original 8052.
6.4 Interrupts
The Interrupt structure in the W79E342 series is slightly different from that of the standard 8052. Due
to the presence of additional features and peripherals, the number of interrupt sources and vectors has
been increased.
6.5 Data Pointers
The data pointer of W79E342 series is same as standard 8052 that has 16-bit Data Pointer (DPTR).
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6.6 Architecture
The W79E342 series are based on the standard 8052 device. It is built around an 8-bit ALU that uses
internal registers for temporary storage and control of the peripheral devices. It can execute the
standard 8052 instruction set.
6.6.1 ALU
The ALU is the heart of the W79E342 series. It is responsible for the arithmetic and logical functions. It
is also used in decision making, in case of jump instructions, and is also used in calculating jump
addresses. The user cannot directly use the ALU, but the Instruction Decoder reads the op-code,
decodes it, and sequences the data through the ALU and its associated registers to generate the
required result. The ALU mainly uses the ACC which is a special function register (SFR) on the chip.
Another SFR, namely B register is also used in Multiply and Divide instructions. The ALU generates
several status signals which are stored in the Program Status Word register (PSW).
6.6.2 Accumulator
The Accumulator (ACC) is the primary register used in arithmetic, logical and data transfer operations
in the W79E342 series. Since the Accumulator is directly accessible by the CPU, most of the high
speed instructions make use of the ACC as one argument.
6.6.3 B Register
This is an 8-bit register that is used as the second argument in the MUL and DIV instructions. For all
other instructions it can be used simply as a general purpose register.
6.6.4 Program Status Word:
This is an 8-bit SFR that is used to store the status bits of the ALU. It holds the Carry flag, the Auxiliary
Carry flag, General purpose flags, the Register Bank Select, the Overflow flag, and the Parity flag.
6.6.5 Scratch-pad RAM
The W79E342 series have a 128 bytes on-chip scratch-pad RAM. These can be used by the user for
temporary storage during program execution. A certain section of this RAM is bit addressable, and can
be directly addressed for this purpose.
6.6.6 Stack Pointer
The W79E342 series have an 8-bit Stack Pointer which points to the top of the Stack. This stack
resides in the Scratch Pad RAM in the W79E342 series. Hence the size of the stack is limited by the
size of this RAM.
6.7 Power Management
Power Management like the standard 8052, the W79E342 series also have the IDLE and POWER
DOWN modes of operation. In the IDLE mode, the clock to the CPU is stopped while the timers, serial
ports and interrupt block continue to operate. In the POWER DOWN mode, all clocks are stopped and
the chip operation is completely stopped. This is the lowest power consumption state.
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PRELIMINARY W79E342 DATA SHEET
7
MEMORY ORGANIZATION
The W79E342 series separate the memory into two separate sections, the Program Memory and the
Data Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory
is used to store data or for memory mapped devices.
Figure 7-1: Memory map
7.1 Program Memory (on-chip Flash)
The Program Memory on the W79E342 series can be up to 2K bytes long. All instructions are fetched
for execution from this memory area. The MOVC instruction can also access this memory region.
7.2 Data Flash Memory
For W79E342 series, NVM Data Memory of Flash EPROM is fixed at 128 bytes long with page size 16
bytes.
7.3 Data Memory (Accessed by MOVX)
Not available in this product series.
7.4 Scratch-pad RAM and Register Map
As mentioned before the W79E342 series have separate Program and Data Memory areas. The on-
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PRELIMINARY W79E342 DATA SHEET
chip 128 bytes scratch pad RAM is in addition to the external memory. There are also several Special
Function Registers (SFRs) which can be accessed by software. The SFRs can be accessed only by
direct addressing, while the on-chip RAM can be accessed by either direct or indirect addressing.
Figure 7-2: RAM and SFR memory map
Since the scratch-pad RAM is only 128 bytes it can be used only when data contents are small. There
are several other special purpose areas within the scratch-pad RAM. These are described as follows.
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PRELIMINARY W79E342 DATA SHEET
FFH
Indirect RAM
80H
7FH
Direct RAM
30H
2FH 7F 7E 7D 7C 7B 7A 79
2EH 77 76 75 74 73 72 71
2DH 6F 6E 6D 6C 6B 6A 69
2CH 67 66 65 64 63 62 61
2BH 5F 5E 5D 5C 5B 5A 59
2AH 57 56 55 54 53 52 51
29H 4F 4E 4D 4C 4B 4A 49
41
78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
28H 47
46
45
44
43
42
27H 3F 3E 3D 3C 3B 3A 39
26H 34 33
25H 2F 2E 2D 2C 2B 2A 29
24H 27 26 25 24 23 22 21
23H 1F 1E 1D 1C 1B 1A 19
22H 17 16 15 14 13 12 11
21H 0F 0E 0D 0C 0B 0A 09
37
36
35
32
31
20H 07
1FH
06
05
04
03
02
01
Bank 3
18H
17H
Bank 2
Bank 1
Bank 0
10H
0FH
08H
07H
00H
Figure 7-3: Scratch pad RAM
7.4.1 Working Registers
There are four sets of working registers, each consisting of eight 8-bit registers. These are termed as
Banks 0, 1, 2, and 3. Individual registers within these banks can be directly accessed by separate
instructions. These individual registers are named as R0, R1, R2, R3, R4, R5, R6 and R7. However, at
one time the W79E342 series can work with only one particular bank. The bank selection is done by
setting RS1-RS0 bits in the PSW. The R0 and R1 registers are used to store the address for indirect
accessing.
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PRELIMINARY W79E342 DATA SHEET
7.4.2 Bit addressable Locations
The Scratch-pad RAM area from location 20h to 2Fh is byte as well as bit addressable. This means
that a bit in this area can be individually addressed. In addition some of the SFRs are also bit
addressable. The instruction decoder is able to distinguish a bit access from a byte access by the type
of the instruction itself. In the SFR area, any existing SFR whose address ends in a 0 or 8 is bit
addressable.
7.4.3 Stack
The scratch-pad RAM can be used for the stack. This area is selected by the Stack Pointer (SP), which
stores the address of the top of the stack. Whenever a jump, call or interrupt is invoked the return
address is placed on the stack. There is no restriction as to where the stack can begin in the RAM. By
default however, the Stack Pointer contains 07h at reset. The user can then change this to any value
desired. The SP will point to the last used value. Therefore, the SP will be incremented and then
address saved onto the stack. Conversely, while popping from the stack the contents will be read first,
and then the SP is decreased.
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PRELIMINARY W79E342 DATA SHEET
8
SPECIAL FUNCTION REGISTERS
The W79E342 series uses Special Function Registers (SFRs) to control and monitor peripherals and
their Modes. The SFRs reside in the register locations 80-FFh and are accessed by direct addressing
only. Some of the SFRs are bit addressable. This is very useful in cases where users wish to modify a
particular bit without changing the others. The SFRs that are bit addressable are those whose
addresses end in 0 or 8. The W79E342 series contain all the SFRs present in the standard 8052.
However some additional SFRs are added. In some cases the unused bits in the original 8052, have
been given new functions. The list of the SFRs is as follows.
F8
IP1
BUZCON
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
B
EIE
PADIDS
IP1H
ACC
ADCCON
ADCH
ADCCON1
WDCON
PSW
NVMCON
NVMDAT
TA
NVMADDRL
IP0
P0M1
KBI
P0M2
P1M1
P1M2
P2M1
P2M2
IP0H
IE
A0
P2
AUXR1
98
90
88
80
P1
TCON
P0
DIVM
TH1
TMOD
SP
TL0
TL1
TH0
CKCON
CKCON1
PCON
DPL
DPH
Table 8-1: Special Function Register Location Table
Note: 1. The SFRs in the column with dark borders are bit-addressable
2. The table is condensed with eight locations per row. Empty locations indicate that these are no registers at these
addresses. When a bit or register is not implemented, it will read high.
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PRELIMINARY W79E342 DATA SHEET
SYMBOL
DEFINITION
ADDR MSB
ESS
BIT_ADDRESS, SYMBOL
LSB RESET
BUZCON
IP1
Buzzer control register
Interrupt priority 1
F9H
F8H
BUZDIV.7 BUZDIV.6 BUZDIV.5 BUZDIV.4 BUZDIV.3 BUZDIV.2 BUZDIV.1 BUZDIV.0 00000000B
(FF)
-
(FE)
-
(FD)
-
(FC)
PWDI
(FB)
-
(FA)
-
(F9)
PKB
(F8)
-
xxx0xx0xB
IP1H
Interrupt high priority 1
F7H
F6H
-
-
-
PWDIH
-
-
PKBH
-
-
xxx0xx0xB
x0000xxxB
PADIDS
Port ADC Digital Input Disable
-
PADIDS.6 PADIDS.5 PADIDS.4 PADIDS.3 -
-
B
B register
F0H
E8H
(F7)
(F6)
(F5)
(F4)
(F3)
(F2)
(F1)
(F0)
00000000B
xxx0xx0xB
EIE
Interrupt enable 1
(EF)
-
(EE)
-
(ED)
-
(EC)
EWDI
(EB)
-
(EA)
-
(E9)
EKB
(E8)
-
ADCCON1
ADCH
ADC control register 1
E3H
ADCLK.1 ADCLK.0
-
-
-
-
-
-
00xxxxxxB
00000000B
00000000B
00000000B
ADC converter result high register E2H
ADC.9
ADC.1
(E7)
ADC.8
ADC.0
(E6)
ADC.7
ADCEX
(E5)
ADC.6
ADCI
(E4)
ADC.5
ADCS
(E3)
ADC.4
RCCLK
(E2)
ADC.3
AADR1
(E1)
ADC.2
AADR0
(E0)
ADCCON
ACC
ADC control register
Accumulator
E1H
E0H
D8H
WDCON
Watch-Dog control
(DF)
WDRUN
(DE)
-
(DD)
WD1
(DC)
WD0
(DB)
WDIF
(DA)
WTRF
(D9)
(D8)
External
reset:
EWRST WDCLR
0x00 0000B
Watchdog
reset:
0x00 0100B
Power on
reset
0x000000B
PSW
Program status word
D0H
CFH
(D7)
CY
(D6)
AC
(D5)
F0
(D4)
RS1
(D3)
RS0
(D2)
OV
(D1)
F1
(D0)
P
00000000B
NVMDATA
NVMCON
TA
NVM Data
00000000B
00000000B
11111111B
NVM Control
CEH EER
EWR
TA.6
-
-
-
-
-
-
Timed Access Protection
C7H
C6H
TA.7
-
TA.5
TA.4
TA.3
TA.2
TA.1
TA.0
NVMADDRL NVM low byte address
NVMADD NVMADD NVMADD NVMADD NVMADD NVMADD NVMADD 00000000B
R.6
R.5
R.4
R.3
R.2
R.1
R.0
IP0
Interrupt priority
B8H
(BF)
-
(BE)
PADC
(BD)
PBO
(BC)
-
(BB)
PT1
(BA)
PX1
(B9)
PT0
(B8)
PX0
x00x0000B
IP0H
P2M2
P2M1
P1M2
P1M1
P0M2
P0M1
IE
Interrupt high priority
Port 2 output mode 2
Port 2 output mode 1
Port 1 output mode 2
Port 1 output mode 1
Port 0 output mode 2
Port 0 output mode 1
Interrupt enable
B7H
B6H
B5H
B4H
B3H
B2H
B1H
A8H
-
PADCH PBOH
-
PT1H
-
PX1H
PT0H
P2M2.1
P2M1.1
P1M2.1
P1M1.1
-
PX0H
P2M2.0
P2M1.0
P1M2.0
P1M1.0
-
x00x0000B
xxxxxx00B
00000000B
x0x00000B
x0x00000B
00000xxxB
00000xxxB
000x0000B
-
-
-
-
-
P2S
P1S
P0S
ENCLK
P1M2.4
P1M1.4
P0M2.4
P0M1.4
T1OE
P1M2.3
P1M1.3
P0M2.3
P0M1.3
T0OE
-
P1M2.6
P1M1.6
P0M2.6
P0M1.6
-
P1M2.2
-
-
P1M1.2
P0M2.7
P0M1.7
P0M2.5
P0M1.5
-
-
-
-
(AF)
EA
(AE)
EADC
(AD)
EBO
(AC)
-
(AB)
ET1
(AA)
EX1
(A9)
ET0
(A8)
EX0
AUXR1
KBI
AUX function register
Keyboard Interrupt
Port 2
A2H
A1H
A0H
KBF
BOD
BOI
LPBOV
KBI.4
SRST
KBI.3
ADCEN
-
BUZE
-
-
-
000x000xB
00000xxxB
xxxxxx11B
KBI.7
KBI.6
KBI.5
P2
(A7)
-
(A6)
-
(A5)
-
(A4)
-
(A3)
-
(A2)
-
(A1)
XTAL1
(A0)
XTAL2
CLKOUT
DIVM
P1
uC clock divide register
Port 1
95H
90H
00000000B
x1111111B
(97)
-
(96)
-
(95)
/RST
VPP
(94)
/INT1
STADC
(93)
/INT0
(92)
T0
(91)
(90)
Buz
CKCON1
Clock control 1
8FH
-
-
-
-
-
CLKSRC. CLKSRC. All reset:
1
0
-
Bit1-0 =
CONFIG0.1-
0
CKCON
TH1
Clock control
Timer high 1
Timer high 0
Timer low 1
Timer low 0
Timer mode
Timer control
8EH
8DH
8CH
8BH
8AH
89H
88H
-
-
-
T1M
T0M
-
-
xxx00xxxB
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
TH0
TL1
TL0
TMOD
TCON
GATE
(8F)
C/T
M1
M0
GATE
(8B)
C/T
M1
M0
(8E)
(8D)
(8C)
(8A)
(89)
(88)
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PRELIMINARY W79E342 DATA SHEET
TF1
-
TR1
-
TF0
TR0
IE1
IT1
IE0
PD
IT0
IDL
PCON
DPH
DPL
SP
Power control
Data pointer high
Data pointer low
Stack pointer
Port 0
87H
83H
82H
81H
80H
BOF
POR
GF1
GF0
xxxx0000B
00000000B
00000000B
00000111B
11111xxxB
P0
(87)
T1
(86)
AD3
(85)
AD2
(84)
AD1
(83)
AD0
(82)
-
(81)
-
(80)
-
Table 8-2: Special Function Registers
Publication Release Date: April 08, 2008
Revision A6
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PRELIMINARY W79E342 DATA SHEET
PORT 0
Bit:
7
6
5
4
3
2
-
1
-
0
-
P0.7
P0.6
P0.5
P0.4
P0.3
Mnemonic: P0
Address: 80h
P0.7-0.3: General purpose Input/Output port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is read. These alternate
functions are described below:
BIT NAME FUNCTION
7
6
P0.7
P0.6
P0.5
P0.4
P0.3
-
Timer 1 pin or KB7 pin of keypad input by alternative.
AD3 or KB6 pin of keypad input by alternative.
AD2 or KB5 pin of keypad input by alternative.
AD1 or KB4 pin of keypad input by alternative.
AD0 or KB3 pin of keypad input by alternative.
Reserved.
5
4
3
2-0
Note: During power-on-reset, the port pins are tri-stated. After power-on-reset, the value of the port is set by CONFIG0.PRHI bit.
The default setting for CONFIG0.PRHI =1 which the alternative function output is turned on upon reset. If CONFIG0.PRHI is set
to 0, the user has to write a 1 to port SFR to turn on the alternative function output.
STACK POINTER
Bit:
7
6
5
4
3
2
1
0
SP.7
SP.6
SP.5
SP.4
SP.3
SP.2
SP.1
SP.0
Mnemonic: SP
BIT NAME FUNCTION
Address: 81h
7-0 SP.[7:0] The Stack Pointer stores the Scratch-pad RAM address where the stack begins. In
other words it always points to the top of the stack.
DATA POINTER LOW
Bit:
7
6
5
4
3
2
1
0
DPL.7
DPL.6
DPL.5
DPL.4
DPL.3
DPL.2
DPL.1
DPL.0
Mnemonic: DPL
BIT NAME
Address: 82h
FUNCTION
7-0 DPL.[7:0] This is the low byte of the standard 8052 16-bit data pointer.
DATA POINTER HIGH
Bit:
7
6
5
4
3
2
1
0
DPH.7
DPH.6
DPH.5
DPH.4
DPH.3
DPH.2
DPH.1
DPH.0
Mnemonic: DPH
BIT NAME
Address: 83h
FUNCTION
7-0 DPH.[7:0] This is the high byte of the standard 8052 16-bit data pointer.
This is the high byte of the DPTR 16-bit data pointer.
POWER CONTROL
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PRELIMINARY W79E342 DATA SHEET
Bit:
7
-
6
-
5
4
3
2
1
0
BOF
POR
GF1
GF0
PD
IDL
Mnemonic: PCON
BIT NAME FUNCTION
Address: 87h
7
6
-
-
Reserved.
Reserved.
0: Cleared by software.
5
4
BOF
POR
1: Set automatically when a brownout reset or interrupt has occurred. Also set at
power on.
0: Cleared by software.
1: Set automatically when a power-on reset has occurred.
3
2
GF1
GF0
General purpose user flags.
General purpose user flags.
1: The CPU goes into the POWER DOWN mode. In this mode, all the clocks are
stopped and program execution is frozen.
1
0
PD
1: The CPU goes into the IDLE mode. In this mode, the clocks CPU clock stopped,
so program execution is frozen. But the clock to the serial, timer and interrupt
blocks is not stopped, and these blocks continue operating.
IDL
TIMER CONTROL
Bit:
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Mnemonic: TCON
BIT NAME FUNCTION
Address: 88h
7
TF1
Timer 1 Overflow Flag. This bit is set when Timer 1 overflows. It is cleared
automatically when the program does a timer 1 interrupt service routine. Software
can also set or clear this bit.
6
5
TR1
TF0
Timer 1 Run Control. This bit is set or cleared by software to turn timer/counter on or
off.
Timer 0 Overflow Flag. This bit is set when Timer 0 overflows. It is cleared
automatically when the program does a timer 0 interrupt service routine. Software
can also set or clear this bit.
4
3
TR0
IE1
Timer 0 Run Control. This bit is set or cleared by software to turn timer/counter on or
off.
Interrupt 1 Edge Detect Flag: Set by hardware when an edge/level is detected on
INT1
. This bit is cleared by hardware when the service routine is vectored to only if
the interrupt was edge triggered. Otherwise it follows the inverse of the pin.
2
1
IT1
IE0
Interrupt 1 Type Control. Set/cleared by software to specify falling edge/ low level
triggered external inputs.
Interrupt 0 Edge Detect Flag. Set by hardware when an edge/level is detected on
Publication Release Date: April 08, 2008
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Revision A6
PRELIMINARY W79E342 DATA SHEET
INT0
. This bit is cleared by hardware when the service routine is vectored to only if
the interrupt was edge triggered. Otherwise it follows the inverse of the pin.
0
IT0
Interrupt 0 Type Control: Set/cleared by software to specify falling edge/ low level
triggered external inputs.
TIMER MODE CONTROL
Bit:
7
6
5
4
3
2
1
0
GATE
M1
M0
GATE
M1
M0
C/ T
C/ T
TIMER1
TIMER0
Mnemonic: TMOD
BIT NAME FUNCTION
Address: 89h
Gating control: When this bit is set, Timer/counter 1 is enabled only while the INT1
GATE
7
pin is high and the TR1 control bit is set. When cleared, the INT1 pin has no effect,
and Timer 1 is enabled whenever TR1 control bit is set.
Timer or Counter Select: When clear, Timer 1 is incremented by the internal clock.
When set, the timer counts falling edges on the T1 pin.
6
C/T
M1
M0
Timer 1 mode select bit 1. See table below.
Timer 1 mode select bit 0. See table below.
5
4
Gating control: When this bit is set, Timer/counter 0 is enabled only while the INT0
GATE
3
pin is high and the TR0 control bit is set. When cleared, the INT0 pin has no effect,
and Timer 0 is enabled whenever TR0 control bit is set.
Timer or Counter Select: When clear, Timer 0 is incremented by the internal clock.
When set, the timer counts falling edges on the T0 pin.
2
C/T
M1
M0
Timer 0 mode select bit 1. See table below.
Timer 0 mode select bit 0. See table below.
1
0
M1, M0: Mode Select bits:
MODE
M1 M0
0
0
Mode 0: 13-bits timer/counter; THx 8 bits and TLx 5 bits which serve as pre-
scalar.
0
1
1
1
0
1
Mode 1: 16-bit timer/counter, no pre-scale.
Mode 2: 8-bit timer/counter with auto-reload from THx.
Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer0
control bits. TH0 is an 8-bit timer only controlled by Timer1 control bits.
(Timer 1) Timer/Counter 1 is stopped.
TIMER 0 LSB
Bit:
7
6
5
4
3
2
1
0
TL0.7
TL0.6
TL0.5
TL0.4
TL0.3
TL0.2
TL0.1
TL0.0
Mnemonic: TL0
BIT NAME
Address: 8Ah
FUNCTION
7-0 TL0.[7:0] Timer 0 LSB.
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PRELIMINARY W79E342 DATA SHEET
TIMER 1 LSB
Bit:
7
6
5
4
3
2
1
0
TL1.7
TL1.6
TL1.5
TL1.4
TL1.3
TL1.2
TL1.1
TL1.0
Mnemonic: TL1
BIT NAME
Address: 8Bh
FUNCTION
7-0 TL1.[7:0] Timer 1 LSB.
TIMER 0 MSB
Bit:
7
6
5
4
3
2
1
0
TH0.7
TH0.6
TH0.5
TH0.4
TH0.3
TH0.2
TH0.1
TH0.0
Mnemonic: TH0
BIT NAME
Address: 8Ch
FUNCTION
7-0 TH0.[7:0] Timer 0 MSB.
TIMER 1 MSB
Bit:
7
6
5
4
3
2
1
0
TH1.7
TH1.6
TH1.5
TH1.4
TH1.3
TH1.2
TH1.1
TH1.0
Mnemonic: TH1
BIT NAME
Address: 8Dh
FUNCTION
7-0 TH1.[7:0] Timer 1 MSB.
CLOCK CONTROL
Bit:
7
-
6
-
5
-
4
3
2
-
1
-
0
-
T1M
T0M
Mnemonic: CKCON
Address: 8Eh
BIT
NAME FUNCTION
-
Reserved.
Timer 1 clock select:
7-5
T1M
0: Timer 1 uses a divide by 12 clocks.
1: Timer 1 uses a divide by 4 clocks.
4
Timer 0 clock select:
T0M
-
0: Timer 0 uses a divide by 12 clocks.
1: Timer 0 uses a divide by 4 clocks.
3
Reserved.
2-0
CLOCK CONTROL 1
Bit:
7
-
6
-
5
-
4
-
3
-
2
-
1
0
CLKSRC.
1
CLKSRC.
0
Publication Release Date: April 08, 2008
Revision A6
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PRELIMINARY W79E342 DATA SHEET
Mnemonic: CKCON1
Address: 8Fh
BIT
NAME FUNCTION
-
Reserved.
7-2
Clock source selectors (TA protected bits):
00: 4MHz to 8MHz external crystal.
01: Internal 455KHz RC oscillator.
10: 32KHz to 1MHz external crystal.
11: External oscillator in XTAL1.
CLKSRC.[
1:0]
1-0
Note that upon power-on-reset, the content of CONFIG0.1-0 will map to these bits.
However, user is able to re-configure these CLKSRC bits after reset. These bits
will have priority over CONFIG0.Fosc1 and Fosc0 bits.
PORT 1
Bit:
7
-
6
5
4
3
2
1
0
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Mnemonic: P1
Address: 90h
P1.6-0: General purpose Input/Output port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is read. These alternate
functions are described below:
BIT
7
NAME
-
FUNCTION
6
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Dedicated GPIO pin (for 16L package only).
/RST Pin or VPP pin by alternative.
INT1 interrupt or STADC pin by alternative.
INT0 interrupt.
5
4
3
2
Timer 0.
1
Dedicated GPIO pin.
0
Buz pin by alternative.
Note: During power-on-reset, the port pins are tri-stated. After power-on-reset, the value of the port is set by CONFIG0.PRHI bit.
The default setting for CONFIG0.PRHI =1 which the alternative function output is turned on upon reset. If CONFIG0.PRHI is set
to 0, the user has to write a 1 to port SFR to turn on the alternative function output.
DIVIDER CLOCK
Bit:
7
6
5
4
3
2
1
0
DIVM.7
DIVM.6
DIVM.5
DIVM.4
DIVM.3
DIVM.2
DIVM.1
DIVM.0
Mnemonic: DIVM
BIT NAME
Address: 95h
FUNCTION
7-0 DIVM.[7:0] The DIVM register is clock divider of uC. Refer OSCILLATOR chapter.
PORT 2
Bit:
7
-
6
-
5
-
4
-
3
-
2
-
1
0
P2.1
P2.0
Mnemonic: P2
Address: A0h
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PRELIMINARY W79E342 DATA SHEET
BIT
7-2
1
NAME
-
FUNCTION
Reserved
P2.1
P2.0
XTAL1 clock input pin.
XTAL2 or CLKOUT pin by alternative.
0
Note: During power-on-reset, the port pins are tri-stated. After power-on-reset, the value of the port is set by CONFIG0.PRHI bit.
The default setting for CONFIG0.PRHI =1 which the alternative function output is turned on upon reset. If CONFIG0.PRHI is set
to 0, the user has to write a 1 to port SFR to turn on the alternative function output.
KEYBOARD INTERRUPT
Bit:
7
6
5
4
3
2
-
1
-
0
-
KBI.7
KBI.6
KBI.5
KBI.4
KBI.3
Mnemonic: KBI
Address: A1h
BIT
7
NAME
KBI.7
KBI.6
KBI.5
KBI.4
KBI.3
-
FUNCTION
1: Enable P0.7 as a cause of a Keyboard interrupt.
1: Enable P0.6 as a cause of a Keyboard interrupt.
1: Enable P0.5 as a cause of a Keyboard interrupt.
1: Enable P0.4 as a cause of a Keyboard interrupt.
6
5
4
3
1: Enable P0.3 as a cause of a Keyboard interrupt (for 16L package only).
Reserved.
2-0
AUX FUNCTION REGISTER 1
Bit:
7
6
5
4
3
2
1
0
-
KBF
BOD
BOI
LPBOV
SRST
ADCEN
BUZE
Mnemonic: AUXR1
Address: A2h
BIT
NAME
FUNCTION
Keyboard Interrupt Flag:
7
KBF
1: When any pin of port 0 that is enabled for the Keyboard Interrupt function goes
low. Must be cleared by software.
Brown Out Disable:
6
5
BOD
BOI
0: Enable Brownout Detect function.
1: Disable Brownout Detect function and save power.
Brown Out Interrupt:
0: Disable Brownout Detect Interrupt function and it will cause chip reset when
BOF is set.
1: This prevents Brownout Detection from causing a chip reset and allows the
Brownout Detect function to be used as an interrupt.
Low Power Brown Out Detect control:
0: When BOD is enable, the Brown Out detect is always turned on by normal run
or Power Down mode.
4
LPBOV
1: When BOD is enable, the Brown Out detect circuit is turned on by Power
Publication Release Date: April 08, 2008
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Revision A6
PRELIMINARY W79E342 DATA SHEET
Down mode. This control can help save 15/16 of the Brownout circuit power.
When uC is in Power Down mode, the BOD will enable internal RC OSC
(455KHZ)
Software reset:
3
2
SRST
1: reset the chip as if a hardware reset occurred.
ADCEN
0: Disable ADC circuit.
1: Enable ADC circuit.
Square-wave enable bit:
1
0
BUZE
-
When set, the square wave is output to the BUZ (P1.0) pin.
Reserved.
INTERRUPT ENABLE
Bit:
7
6
5
4
-
3
2
1
0
EA
EADC
EBO
ET1
EX1
ET0
EX0
Mnemonic: IE
Address: A8h
BIT
7
NAME
FUNCTION
EA
Global enable. Enable/Disable all interrupts.
Enable ADC interrupt.
6
EADC
EBO
-
5
Enable Brown Out interrupt.
Reserved.
4
3
ET1
EX1
ET0
EX0
Enable Timer 1 interrupt.
Enable external interrupt 1.
Enable Timer 0 interrupt.
Enable external interrupt 0.
2
1
0
PORT 0 OUTPUT MODE 1
Bit:
7
6
5
4
3
2
-
1
-
0
-
P0M1.7
P0M1.6
P0M1.5
P0M1.4
P0M1.3
Mnemonic: P0M1
BIT NAME
7-3 P0M1.[7:3] To control the output configuration of P0 bits [7:3].
2-0 Reserved.
PORT 0 OUTPUT MODE 2
Address: B1h
FUNCTION
-
Bit:
7
6
5
4
3
2
-
1
-
0
-
P0M2.7
P0M2.6
P0M2.5
P0M2.4
P0M2.3
Mnemonic: P0M2
BIT NAME
7-3 P0M2.[7:3] To control the output configuration of P0 bits [7:3]
2-0 Reserved.
Address: B2h
FUNCTION
-
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PRELIMINARY W79E342 DATA SHEET
PORT 1 OUTPUT MODE 1
Bit:
7
-
6
5
-
4
3
2
1
0
P1M1.6
P1M1.4
P1M1.3
P1M1.2
P1M1.1
P1M1.0
Mnemonic: P1M1
Address: B3h
BIT
7
NAME
FUNCTION
-
Reserved.
6
P1M1.6
-
To control the output configuration of P1.6.
Reserved.
5
4-0 P1M1.4-0
To control the output configuration of P1.4-1.0.
PORT 1 OUTPUT MODE 2
Bit:
7
-
6
5
-
4
3
2
1
0
P1M2.6
P1M2.4
P1M2.3
P1M2.2
P1M2.1
P1M2.0
Mnemonic: P1M2
Address: B4h
BIT
7
NAME
FUNCTION
-
Reserved.
6
P1M2.6
-
To control the output configuration of P1.6.
Reserved.
5
4-0 P1M2.[4:0] To control the output configuration of P1 bits [4:0]
PORT 2 OUTPUT MODE 1
Bit:
7
6
5
4
3
2
1
0
P2S
P1S
P0S
ENCLK
T1OE
T0OE
P2M1.1
P2M1.0
Mnemonic: P2M1
BIT NAME FUNCTION
Address: B5h
7
6
5
P2S
P1S
P0S
0: Disable Schmitt trigger inputs on port 2 and enable TTL inputs on port 2.
1: Enables Schmitt trigger inputs on Port 2.
0: Disable Schmitt trigger inputs on port 1 and enable TTL inputs on port 1.
1: Enables Schmitt trigger inputs on Port 1.
0: Disable Schmitt trigger inputs on port 0 and enable TTL inputs on port 0
1: Enables Schmitt trigger inputs on Port 0.
4
3
ENCLK 1: Enabled clock output to XTAL2 pin (P2.0).
T1OE
1: The P0.7 pin is toggled whenever Timer 1 overflows. The output frequency is
therefore one half of the Timer 1 overflow rate.
2
1
T0OE
1: The P1.2 pin is toggled whenever Timer 0 overflows. The output frequency is
therefore one half of the Timer 0 overflow rate.
P2M1.1 To control the output configuration of P2.1.
Publication Release Date: April 08, 2008
Revision A6
- 25 -
PRELIMINARY W79E342 DATA SHEET
0
P2M1.0 To control the output configuration of P2.0.
PORT 2 OUTPUT MODE 2
Bit:
7
-
6
-
5
-
4
-
3
-
2
-
1
0
P2M2.1
P2M2.0
Mnemonic: P2M2
Address: B6h
BIT
NAME
FUNCTION
Reserved.
7-2
-
1-0 P2M2.[1:0] To control the output configuration of P2 bits [1:0]
Port Output Configuration Settings:
PXM1.Y
PXM2.Y
PORT INPUT/OUTPUT MODE
Quasi-bidirectional
0
0
1
0
1
0
Push-Pull
Input Only (High Impedance)
P2M1.PxS=0, TTL input
P2M1.PxS=1, Schmitt input
1
1
Open Drain
INTERRUPT HIGH PRIORITY
Bit:
7
-
6
5
4
-
3
2
1
0
PADCH
PBOH
PT1H
PX1H
PT0H
PX0H
Mnemonic: IP0H
Address: B7h
BIT
7
NAME
FUNCTION
-
This bit is un-implemented and will read high.
1: To set interrupt high priority of ADC is highest priority level.
6
PADCH
PBOH
-
5
1: To set interrupt high priority of Brown Out Detector is highest priority level.
Reserved.
4
3
PT1H
PX1H
PT0H
PX0H
1: To set interrupt high priority of Timer 1 is highest priority level.
1: To set interrupt high priority of External interrupt 1 is highest priority level.
1: To set interrupt high priority of Timer 0 is highest priority level.
1: To set interrupt high priority of External interrupt 0 is highest priority level.
2
1
0
INTERRUPT PRIORITY 0
Bit:
7
-
6
5
4
-
3
2
1
0
PADC
PBO
PT1
PX1
PT0
PX0
Mnemonic: IP
Address: B8h
BIT
7
NAME
FUNCTION
This bit is un-implemented and will read high.
1: To set interrupt priority of ADC is higher priority level.
-
6
PADC
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PRELIMINARY W79E342 DATA SHEET
5
4
3
2
1
0
PBO
-
1: To set interrupt priority of Brown Out Detector is higher priority level.
Reserved.
PT1
PX1
PT0
PX0
1: To set interrupt priority of Timer 1 is higher priority level.
1: To set interrupt priority of External interrupt 1 is higher priority level.
1: To set interrupt priority of Timer 0 is higher priority level.
1: To set interrupt priority of External interrupt 0 is higher priority level.
NVM LOW BYTE ADDRESS
Bit:
7
-
6
5
4
3
2
1
0
NVMADD
R.6
NVMADD
R.5
NVMADD
R.4
NVMADD
R.3
NVMADD
R.2
NVMADD
R.1
NVMADD
R.0
Mnemonic: NVMADDRL
Address: C6h
BIT
NAME
FUNCTION
Please Keep it at 0.
7
-
6~0 NVMADDR.[6:0] The NVM low byte address:
The register indicates NVM data memory of low byte address on On-Chip
code memory space.
TIMED ACCESS
Bit:
7
6
5
4
3
2
1
0
TA.7
TA.6
TA.5
TA.4
TA.3
TA.2
TA.1
TA.0
Mnemonic: TA
Address: C7h
BIT
NAME
FUNCTION
7-0 TA.[7:0]
The Timed Access register:
The Timed Access register controls the access to protected bits. To access
protected bits, the user must first write AAH to the TA. This must be immediately
followed by a write of 55H to TA. Now a window is opened in the protected bits
for three machine cycles, during which the user can write to these bits.
NVM CONTROL
Bit:
7
6
5
-
4
-
3
-
2
-
1
-
0
-
EER
EWR
Mnemonic: NVMCON
Address: CEh
BIT
NAME
FUNCTION
NVM page(n) erase bit:
0: Without erase NVM page(n).
7
EER
1: Set this bit to erase page(n) of NVM. The NVM has 8 pages and each page
have 16 bytes data memory. Initiate page select by programming NVMADDL
registers, which will automaticly enable page area. When user set this bit, the
page erase process will begin and program counter will halt at this instruction.
After the erase process is completed, program counter will continue executing
Publication Release Date: April 08, 2008
- 27 -
Revision A6
PRELIMINARY W79E342 DATA SHEET
next instruction.
6
EWR
NVM data write bit:
0: Without write NVM data.
1: Set this bit to write NVM bytes and program counter will halt at this instruction.
After write is finished, program counter will kept next instruction then executed.
5-0
-
Reserved
NVM DATA
Bit:
7
6
5
4
3
2
1
0
NVMDAT. NVMDAT. NVMDAT. NVMDAT. NVMDAT
NVMDAT. NVMDAT. NVMDAT.
7
6
5
4
3
2
1
0
Mnemonic: NVMDATA
BIT NAME
Address: CFh
FUNCTION
7~0 NVMDAT.[7:0] The NVM data write register. The read NVM data is by MOVC instruction.
PROGRAM STATUS WORD
Bit:
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
Mnemonic: PSW
Address: D0h
BIT
NAME
CY
FUNCTION
7
Carry flag:
Set for an arithmetic operation which results in a carry being generated from the
ALU. It is also used as the accumulator for the bit operations.
6
5
AC
F0
Auxiliary carry:
Set when the previous operation resulted in a carry from the high order nibble.
User flag 0:
The General purpose flag that can be set or cleared by the user.
4~3 RS1~RS0 Register bank select bits.
2
OV
Overflow flag:
Set when a carry was generated from the seventh bit but not from the 8th bit as
a result of the previous operation, or vice-versa.
1
0
F1
P
User Flag 1:
The General purpose flag that can be set or cleared by the user software.
Parity flag:
Set/cleared by hardware to indicate odd/even number of 1's in the accumulator.
RS.1-0: Register Bank Selection Bits:
RS1
RS0
REGISTER BANK
ADDRESS
00-07h
0
0
1
1
0
1
0
1
0
1
2
3
08-0Fh
10-17h
18-1Fh
- 28 -
PRELIMINARY W79E342 DATA SHEET
WATCHDOG CONTROL
Bit:
7
6
-
5
4
3
2
1
0
WDRUN
WD1
WD0
WDIF
WTRF
EWRST
WDCLR
Mnemonic: WDCON
Address: D8h
BIT
NAME
FUNCTION
7
WDRUN
0: The Watchdog is stopped.
1: The Watchdog is running.
6
5
4
-
Reserved.
WD1
WD0
Watchdog Timer Time-out Select bits. These bits determine the time-out period
of the watchdog timer. The reset time-out period is 512 clocks longer than the
watchdog time-out.
WD1 WD0 Interrupt time-out
Reset time-out
26 + 512
0
0
1
1
0
1
0
1
26
29
213
215
29 + 512
213 + 512
215 + 512
3
2
WDIF
Watchdog Timer Interrupt Flag
0: If the interrupt is not enabled, then this bit indicates that the time-out period
has elapsed. This bit must be cleared by software.
1: If the watchdog interrupt is enabled, hardware will set this bit to indicate that
the watchdog interrupt has occurred.
WTRF
Watchdog Timer Reset Flag
1: Hardware will set this bit when the watchdog timer causes a reset. Software
can read it but must clear it manually. A power-fail reset will also clear the
bit. This bit helps software in determining the cause of a reset. If EWRST =
0, the watchdog timer will have no affect on this bit.
1
0
EWRST
WDCLR
0: Disable Watchdog Timer Reset.
1: Enable Watchdog Timer Reset.
Reset Watchdog Timer
This bit helps in putting the watchdog timer into a know state. It also helps in
resetting the watchdog timer before a time-out occurs. Failing to set the
EWRST before time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512
clocks after that a watchdog timer reset will be generated if EWRST is set. This
bit is self-clearing by hardware.
The WDCON SFR is set to 0x000000B on a reset. WTRF (WDCON.2) is set to a 1 on a Watchdog
timer reset, but to a 0 on power on/down resets. WTRF (WDCON.2) is not altered by an external reset.
EWRST (WDCON.1) is set to 0 on a Power-on reset, reset pin reset, and Watch Dog Timer reset.
All the bits in this SFR have unrestricted read access. WDRUN, WD0, WD1, EWRST, WDIF and
WDCLR require Timed Access procedure to write. The remaining bits have unrestricted write
accesses. Please refer TA register description.
Publication Release Date: April 08, 2008
- 29 -
Revision A6
PRELIMINARY W79E342 DATA SHEET
TA
REG
C7H
D8H
WDCON
MOV
MOV
SETB
ORL
REG
TA, #AAH
TA, #55H
WDCON.0
; To access protected bits
; Reset watchdog timer
WDCON, #00110000B
TA, #AAH
; Select 26 bits watchdog timer
MOV
MOV
ORL
TA, #55H
WDCON, #00000010B
; Enable watchdog reset
ACCUMULATOR
Bit:
7
6
5
4
3
2
1
0
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
Mnemonic: ACC
BIT NAME
Address: E0h
FUNCTION
7-0 ACC.[7:0] The A or ACC register is the standard 8052 accumulator
ADC CONTROL REGISTER
Bit:
7
6
5
4
3
2
1
0
ADC.1
ADC.0
ADCEX
ADCI
ADCS
RCCLK
AADR1
AADR0
Mnemonic: ADCCON
BIT NAME FUNCTION
7-6 ADC.1-0
Address: E1h
2 LSB of 10-bit A/D conversion result.
Enable STADC-triggered conversion
5
ADCEX
0: Conversion can only be started by software (i.e., by setting ADCS).
1: Conversion can be started by software or by a rising edge on STADC (pin
P1.4).
4
3
ADCI
ADC Interrupt flag:
This flag is set when the result of an A/D conversion is ready. This generates an
ADC interrupt, if it is enabled. The flag may be cleared by the ISR. While this flag
is 1, the ADC cannot start a new conversion. ADCI can not be set by software.
ADCS
ADC Start and Status: Set this bit to start an A/D conversion. It may also be set
by STADC if ADCEX is 1. This signal remains high while the ADC is busy and is
reset right after ADCI is set.
Note:
1.
It is recommended to clear ADCI before ADCS is set. However, if ADCI is
cleared and ADCS is set at the same time, a new A/D conversion may start
on the same channel.
2.
3.
Software clearing of ADCS will abort conversion in progress.
ADC cannot start a new conversion while ADCS is high.
2
RCCLK
0: The CPU clock is used as ADC clock source.
1: The internal RC 455KHz clock is used as ADC clock source.
Note:
- 30 -
PRELIMINARY W79E342 DATA SHEET
1. This bit can only be set/cleared when ADCEN=0.
2. The ADC clock source will goes through pre-scalar of /1, /2, /4 or /8,
selectable by ADCLK bits (SFR ADCCON1.6-7).
1
0
AADR1
AADR0
The ADC input select. See table below.
The ADC input select. See table below.
The ADCI and ADCS control the ADC conversion as below:
ADCI
ADCS
ADC STATUS
0
0
1
1
0
1
0
1
ADC not busy; A conversion can be started.
ADC busy; Start of a new conversion is blocked.
Conversion completed; Start of a new conversion requires ADCI = 0.
This is an internal temporary state that user can ignore it.
AADR1, AADR0: ADC Analog Input Channel select bits:
AADR1
AADR0
SELECTED ANALOG INPUT CHANNEL
AD0 (P0.3)
AD1 (P0.4)
AD2 (P0.5)
AD3 (P0.6)
0
0
1
1
0
1
0
1
(These bits can only be changed when ADCI and ADCS are both zero.)
ADC CONVERTER RESULT HIGH REGISTER
Bit:
7
6
5
4
3
2
1
0
ADC.9
ADC.8
ADC.7
ADC.6
ADC.5
ADC.4
ADC.3
ADC.2
Mnemonic: ADCH
BIT NAME
Address: E2h
FUNCTION
7-0 ADC.[9:2] 8 MSB of 10-bit A/D conversion result.
ADC CONTROL REGISTER 1
Bit:
7
6
5
-
4
-
3
-
2
-
1
-
0
-
ADCLK.1
ADCLK.0
Mnemonic: ADCCON1
BIT NAME
Address: E3h
FUNCTION
Publication Release Date: April 08, 2008
Revision A6
- 31 -
PRELIMINARY W79E342 DATA SHEET
7-6 ADCLK.1~0 ADC Clock Prescaler:
The 10-bit ADC needs a clock to drive the converting and the clock frequency
need to be within 200KHz to 5MHz. ADCLK[1:0] controls the frequency of the
clock to ADC block as below table.
ADCLK.1
ADCLK.0
ADC Clock Frequency
ADCCLK/1 (default)
ADCCLK/2
0
0
1
1
0
1
0
1
ADCCLK/4
ADCCLK/8
Note: User required to clear ADCEN (ADCEN = 0) when re-configure the ADC
clock prescaler.
5-0
-
Reserved.
INTERRUPT ENABLE REGISTER 1
Bit:
7
-
6
-
5
-
4
3
-
2
-
1
0
-
EWDI
EKB
Mnemonic: EIE
Address: E8h
BIT
7-5
4
NAME
FUNCTION
Reserved.
-
EWDI
0: Disable Watchdog Timer Interrupt.
1: Enable Watchdog Timer Interrupt.
3-2
1
-
Reserved.
EKB
0: Disable Keypad Interrupt.
1: Enable Keypad Interrupt.
0
-
Reserved.
B REGISTER
Bit:
7
6
5
4
3
2
1
0
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
Mnemonic: B
Address: F0h
BIT
NAME
FUNCTION
7-0 B.[7:0]
The B register is the standard 8052 register that serves as a second accumulator.
PORT ADC DIGITAL INPUT DISABLE
Bit:
7
6
5
4
3
2
-
1
-
0
-
PADIDS.6 PADIDS.5 PADIDS.4 PADIDS.3
-
Mnemonic: PADIDS
Address: F6h
BIT
NAME
FUNCTION
7
-
Reserved.
- 32 -
PRELIMINARY W79E342 DATA SHEET
P0.6 digital input disable bit.
6
5
4
PADIDS.6 0: Default (With digital/analog input).
1: Disable Digital Input of ADC Input Channel 3.
P0.5 digital input disable bit.
PADIDS.5 0: Default (With digital/analog input).
1: Disable Digital Input of ADC Input Channel 2.
P0.4 digital input disable bit.
PADIDS.4 0: Default (With digital/analog input).
1: Disable Digital Input of ADC Input Channel 1.
P0.3 digital input disable bit.
3
PADIDS.3 0: Default (With digital/analog input).
1: Disable Digital Input of ADC Input Channel 0.
2-0
-
Reserved.
INTERRUPT HIGH PRIORITY 1
Bit:
7
-
6
-
5
-
4
3
-
2
-
1
0
PWDIH
PKBH
-
Mnemonic: IP1H
Address: F7h
BIT
7-5
4
NAME
FUNCTION
Reserved.
-
PWDIH
1: To set interrupt high priority of Watchdog is highest priority level.
3-2
1
-
Reserved.
PKBH
-
1: To set interrupt high priority of Keypad is highest priority level.
Reserved.
0
EXTENDED INTERRUPT PRIORITY
Bit:
7
-
6
-
5
-
4
3
-
2
-
1
0
PWDI
PKB
-
Mnemonic: IP1
Address: F8h
BIT
7-5
4
NAME
FUNCTION
Reserved.
-
PWDI
1: To set interrupt priority of Watchdog is higher priority level.
3-2
1
-
Reserved.
PKB
-
1: To set interrupt priority of Keypad is higher priority level.
Reserved.
0
BUZZER CONTROL REGISTER
Bit:
7
6
5
4
3
2
1
0
BUZDIV.7 BUZDIV.6 BUZDIV.5 BUZDIV.4 BUZDIV.3 BUZDIV.2 BUZDIV.1 BUZDIV.0
Publication Release Date: April 08, 2008
- 33 -
Revision A6
PRELIMINARY W79E342 DATA SHEET
Mnemonic: BUZCON
BIT NAME FUNCTION
7-0 BUZDIV
Address: F9h
Buzzer division select bits:
These bits are division selector. User may configure these bits to further divide
the cpu clock in order to generate the desired buzzer output frequency.
The following shows the equation for the buzzer output rate;
Fbuz = Fcpu x 1/[(16)x(BUZDIV + 1)]
- 34 -
PRELIMINARY W79E342 DATA SHEET
9
INSTRUCTION SET
The W79E342 series execute all the instructions of the standard 8052 family. The operations of these
instructions, as well as their effects on flag and status bits, are exactly the same. However, the timing
of these instructions is different in two ways. Firstly, the machine cycle is four clock periods, while the
standard-8051/52 machine cycle is twelve clock periods. Secondly, it can fetch only once per machine
cycle (i.e., four clocks per fetch), while the standard 8051/52 can fetch twice per machine cycle (i.e.,
six clocks per fetch).
The timing differences create an advantage for the W79E342 series. There is only one fetch per
machine cycle, so the number of machine cycles is usually equal to the number of operands in the
instruction. (Jumps and calls do require an additional cycle to calculate the new address.) As a result,
the W79E342 series reduces the number of dummy fetches and wasted cycles, and therefore
improves overall efficiency, compared to the standard 8051/52.
Op-code
HEX Code
Bytes
W79E342
series
Machine
Cycle
W79E342
series
Clock
8032
Clock
cycles
W79E342
series vs. 8032
Speed Ratio
cycles
NOP
00
28
29
2A
2B
2C
2D
2E
2F
26
27
25
24
38
39
3A
3B
3C
3D
3E
3F
36
37
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
4
4
4
8
8
4
4
4
4
4
4
4
4
4
4
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
3
ADD A, R0
ADD A, R1
ADD A, R2
ADD A, R3
ADD A, R4
ADD A, R5
ADD A, R6
ADD A, R7
ADD A, @R0
ADD A, @R1
ADD A, direct
ADD A, #data
ADDC A, R0
ADDC A, R1
ADDC A, R2
ADDC A, R3
ADDC A, R4
ADDC A, R5
ADDC A, R6
ADDC A, R7
ADDC A, @R0
ADDC A, @R1
3
3
3
3
3
3
3
3
3
3
1.5
1.5
3
3
3
3
3
3
3
3
3
3
Publication Release Date: April 08, 2008
Revision A6
- 35 -
PRELIMINARY W79E342 DATA SHEET
ADDC A, direct
ADDC A, #data
SUBB A, R0
SUBB A, R1
SUBB A, R2
SUBB A, R3
SUBB A, R4
SUBB A, R5
SUBB A, R6
SUBB A, R7
SUBB A, @R0
SUBB A, @R1
SUBB A, direct
SUBB A, #data
INC A
35
34
98
99
9A
9B
9C
9D
9E
9F
96
97
95
94
04
08
09
0A
0B
0C
0D
0E
0F
06
07
05
A3
14
18
19
1A
1B
1C
1D
1E
1F
16
17
15
2
2
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
2
8
8
4
4
4
4
4
4
4
4
4
4
8
8
4
4
4
4
4
4
4
4
4
4
4
8
8
4
4
4
4
4
4
4
4
4
4
4
8
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
24
12
12
12
12
12
12
12
12
12
12
12
12
1.5
1.5
3
3
3
3
3
3
3
3
3
3
1.5
1.5
3
INC R0
3
INC R1
3
INC R2
3
INC R3
3
INC R4
3
INC R5
3
INC R6
3
INC R7
3
INC @R0
INC @R1
INC direct
INC DPTR
DEC A
3
3
1.5
3
3
DEC R0
3
DEC R1
3
DEC R2
3
DEC R3
3
DEC R4
3
DEC R5
3
DEC R6
3
DEC R7
3
DEC @R0
DEC @R1
DEC direct
3
3
1.5
- 36 -
PRELIMINARY W79E342 DATA SHEET
DEC DPTR
MUL AB
A5
A4
84
D4
58
59
5A
5B
5C
5D
5E
5F
56
57
55
54
52
53
48
49
4A
4B
4C
4D
4E
4F
46
47
45
44
42
43
68
69
6A
6B
6C
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
3
1
1
1
1
1
1
1
1
1
1
2
2
2
3
1
1
1
1
1
2
5
5
1
1
1
1
1
1
1
1
1
1
1
2
2
2
3
1
1
1
1
1
1
1
1
1
1
2
2
2
3
1
1
1
1
1
8
24
48
48
12
12
12
12
12
12
12
12
12
12
12
12
12
12
24
12
12
12
12
12
12
12
12
12
12
12
12
12
24
12
12
12
12
12
3
20
20
4
2.4
2.4
3
DIV AB
DA A
ANL A, R0
ANL A, R1
ANL A, R2
ANL A, R3
ANL A, R4
ANL A, R5
ANL A, R6
ANL A, R7
ANL A, @R0
ANL A, @R1
ANL A, direct
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, R0
ORL A, R1
ORL A, R2
ORL A, R3
ORL A, R4
ORL A, R5
ORL A, R6
ORL A, R7
ORL A, @R0
ORL A, @R1
ORL A, direct
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, R0
XRL A, R1
XRL A, R2
XRL A, R3
XRL A, R4
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
8
1.5
1.5
1.5
2
8
8
12
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
8
1.5
1.5
1.5
2
8
8
12
4
3
4
3
4
3
4
3
4
3
Publication Release Date: April 08, 2008
Revision A6
- 37 -
PRELIMINARY W79E342 DATA SHEET
XRL A, R5
XRL A, R6
XRL A, R7
XRL A, @R0
XRL A, @R1
XRL A, direct
XRL A, #data
XRL direct, A
XRL direct, #data
CLR A
6D
6E
6F
66
67
65
64
62
63
E4
F4
23
33
03
13
C4
E8
E9
EA
EB
EC
ED
EE
EF
E6
E7
E5
74
F8
F9
FA
FB
FC
FD
FE
FF
A8
A9
AA
1
1
1
1
1
2
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
2
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
2
2
2
4
4
4
4
4
8
8
8
12
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8
8
4
4
4
4
4
4
4
4
8
8
8
12
12
12
12
12
12
12
12
24
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
3
3
3
3
3
1.5
1.5
1.5
2
3
CPL A
3
RL A
3
RLC A
3
RR A
3
RRC A
3
SWAP A
3
MOV A, R0
MOV A, R1
MOV A, R2
MOV A, R3
MOV A, R4
MOV A, R5
MOV A, R6
MOV A, R7
MOV A, @R0
MOV A, @R1
MOV A, direct
MOV A, #data
MOV R0, A
MOV R1, A
MOV R2, A
MOV R3, A
MOV R4, A
MOV R5, A
MOV R6, A
MOV R7, A
MOV R0, direct
MOV R1, direct
MOV R2, direct
3
3
3
3
3
3
3
3
3
3
1.5
1.5
3
3
3
3
3
3
3
3
1.5
1.5
1.5
- 38 -
PRELIMINARY W79E342 DATA SHEET
MOV R3, direct
MOV R4, direct
MOV R5, direct
MOV R6, direct
MOV R7, direct
MOV R0, #data
MOV R1, #data
MOV R2, #data
MOV R3, #data
MOV R4, #data
MOV R5, #data
MOV R6, #data
MOV R7, #data
MOV @R0, A
AB
AC
AD
AE
AF
78
79
7A
7B
7C
7D
7E
7F
F6
F7
A6
A7
76
77
F5
88
89
8A
8B
8C
8D
8E
8F
86
87
85
75
90
93
83
E2
E3
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
1
1
1
1
2
8
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
24
24
24
24
24
24
24
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
3
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
1
4
MOV @R1, A
1
4
3
MOV @R0, direct
MOV @R1, direct
MOV @R0, #data
MOV @R1, #data
MOV direct, A
2
8
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2
2
8
2
8
2
8
2
8
MOV direct, R0
MOV direct, R1
MOV direct, R2
MOV direct, R3
MOV direct, R4
MOV direct, R5
MOV direct, R6
MOV direct, R7
MOV direct, @R0
MOV direct, @R1
MOV direct, direct
MOV direct, #data
MOV DPTR, #data 16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @R0
MOVX A, @R1
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
3
12
3
12
2
3
12
2
2
8
3
2
8
3
2 - 9
2 - 9
8 - 36
8 - 36
3 - 0.66
3 - 0.66
Publication Release Date: April 08, 2008
Revision A6
- 39 -
PRELIMINARY W79E342 DATA SHEET
MOVX A, @DPTR
MOVX @R0, A
MOVX @R1, A
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, R0
XCH A, R1
XCH A, R2
XCH A, R3
XCH A, R4
XCH A, R5
XCH A, R6
XCH A, R7
XCH A, @R0
XCH A, @R1
XCHD A, @R0
XCHD A, @R1
XCH A, direct
CLR C
E0
F2
F3
F0
C0
D0
C8
C9
CA
CB
CC
CD
CE
CF
C6
C7
D6
D7
C5
C3
C2
D3
D2
B3
B2
82
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1
2
1
2
2
2
2
2
2
2
2
2 - 9
2 - 9
2 - 9
2 - 9
2
8 - 36
24
24
24
24
24
24
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
24
24
24
24
12
24
24
3 - 0.66
8 - 36
3 - 0.66
8 - 36
3 - 0.66
8 - 36
8
3 - 0.66
3
2
8
3
1
4
3
1
4
3
1
4
3
1
4
3
1
4
3
1
4
3
1
4
3
1
4
3
1
4
3
1
4
3
1
4
3
1
4
3
2
8
1.5
3
1
4
CLR bit
2
8
1.5
3
SETB C
1
4
SETB bit
2
8
1.5
3
CPL C
1
4
CPL bit
2
8
1.5
3
ANL C, bit
2
8
ANL C, /bit
ORL C, bit
B0
72
2
6
3
2
8
3
ORL C, /bit
MOV C, bit
MOV bit, C
ACALL addr11
A0
A2
92
2
6
3
2
8
1.5
3
2
8
71, 91, B1,
11, 31, 51,
D1, F1
3
12
2
LCALL addr16
RET
12
22
32
3
1
1
2
4
2
2
3
16
8
24
24
24
24
1.5
3
RETI
8
3
AJMP ADDR11
01, 21, 41,
61, 81, A1,
C1, E1
12
2
LJMP addr16
02
3
4
16
24
1.5
- 40 -
PRELIMINARY W79E342 DATA SHEET
JMP @A+DPTR
SJMP rel
73
1
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
3
2
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
4
6
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
3
80
12
12
12
12
12
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
12
12
12
12
12
12
12
12
16
2
JZ rel
60
2
JNZ rel
70
2
JC rel
40
2
JNC rel
50
2
JB bit, rel
20
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2
JNB bit, rel
30
JBC bit, rel
10
CJNE A, direct, rel
CJNE A, #data, rel
CJNE @R0, #data, rel
CJNE @R1, #data, rel
CJNE R0, #data, rel
CJNE R1, #data, rel
CJNE R2, #data, rel
CJNE R3, #data, rel
CJNE R4, #data, rel
CJNE R5, #data, rel
CJNE R6, #data, rel
CJNE R7, #data, rel
DJNZ R0, rel
B5
B4
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
D8
D9
DD
DA
DB
DC
DE
DF
D5
DJNZ R1, rel
2
DJNZ R5, rel
2
DJNZ R2, rel
2
DJNZ R3, rel
2
DJNZ R4, rel
2
DJNZ R6, rel
2
DJNZ R7, rel
2
DJNZ direct, rel
1.5
Table 9-1: Instruction Set for W79E342
Publication Release Date: April 08, 2008
Revision A6
- 41 -
PRELIMINARY W79E342 DATA SHEET
9.1 Instruction Timing
This section is important because some applications use software instructions to generate timing
delays. It also provides more information about timing differences between the W79E342 series and
the standard 8051/52.
In W79E342 series, each machine cycle is four clock periods long. Each clock period is called a state,
and each machine cycle consists of four states: C1, C2 C3 and C4, in order. Both clock edges are
used for internal timing, so the duty cycle of the clock should be as close to 50% as possible to avoid
timing conflicts.
The W79E342 series does one op-code fetch per machine cycle, so, in most instructions, the number
of machine cycles required is equal to the number of bytes in the instruction. There are 256 available
op-codes. 128 of them are single-cycle instructions, so many op-codes are executed in just four clocks
period. Some of the other op-codes are two-cycle instructions, and most of these have two-byte op-
codes. However, there are some instructions that have one-byte instructions yet take two cycles to
execute. One important example is the MOVX instruction.
In the standard 8052, the MOVX instruction is always two machine cycles long. However, in the
W79E342 series each machine cycle is made of only 4 clock periods compared to the 12 clock periods
for the standard 8052. Therefore, even though the number of categories has increased, each
instruction is at least 1.5 to 3 times faster than the standard 8052 in terms of clock periods.
Single Cycle
C4
C1
C2
C3
CPU CLK
ALE
PSEN
A7-0
Data_ in D7-0
AD<7:0>
Address A15-8
Address <15:0>
Figure 9-1: Single Cycle Instruction Timing
- 42 -
PRELIMINARY W79E342 DATA SHEET
Operand Fetch
Instruction Fetch
C1
C2
C3
C4
C1
C2
C3
C4
CPU CLK
ALE
PSEN
PC
OP-CODE
PC+1
OPERAND
AD<7:0>
Address A15-8
Address A15-8
Address<15:0>
Figure 9-2: Two Cycles Instruction Timing
Instruction Fetch
Operand Fetch
Operand Fetch
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
CPU CLK
ALE
PSEN
A7-0
OP-CODE
A7-0
OPERAND
A7-0
OPERAND
AD<7:0>
Address<15:0>
Address A15-8
Address A15-8
Address A15-8
Figure 9-3: Three Cycles Instruction Timing
Publication Release Date: April 08, 2008
Revision A6
- 43 -
PRELIMINARY W79E342 DATA SHEET
Instruction Fetch
Operand Fetch
C1 C2 C3
Operand Fetch
Operand Fetch
C1 C2 C3 C4
C1
C2
C3
C4
C4
C1
C2
C3
C4
CPU CLK
ALE
PSEN
OP-CODE
A7-0
A7-0
AD<7:0>
A7-0
OPERAND
OPERAND
A7-0
OPERAND
Address<15:0>
Address A15-8
Address A15-8
Address A15-8
Address A15-8
Figure 9-4: Four Cycles Instruction Timing
Operand Fetch
Instruction Fetch
Operand Fetch
Operand Fetch
Operand Fetch
C1
C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CPU CLK
ALE
PSEN
OPERAND
AD<7:0>
OP-CODE
OPERAND
OPERAND
OPERAND
A7-0
A7-0
A7-0
A7-0
A7-0
Address<15:0>
Address A15-8
Address A15-8
Address A15-8
Address A15-8
Address A15-8
Figure 9-5: Five Cycles Instruction Timing
- 44 -
PRELIMINARY W79E342 DATA SHEET
10 POWER MANAGEMENT
The W79E342 series has several features that help the user to control the power consumption of the
device. These modes are discussed in the next two sections.
10.1 Idle Mode
The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the
idle bit is the last instruction that will be executed before the device goes into Idle Mode. In the Idle
mode, the clock to the CPU is halted, but not to the Interrupt, Timer and Watchdog timer blocks. This
forces the CPU state to be frozen; the Program counter, the Stack Pointer, the Program Status Word,
the Accumulator and the other registers hold their contents. The port pins hold the logical states they
had at the time Idle was activated. The Idle mode can be terminated in two ways. Since the interrupt
controller is still active, the activation of any enabled interrupt can wake up the processor. This will
automatically clear the Idle bit, terminate the Idle mode, and the Interrupt Service Routine (ISR) will be
executed. After the ISR, execution of the program will continue from the instruction which put the
device into Idle Mode.
The Idle mode can also be exited by activating the reset. The device can put into reset either by
applying a low on the external /RST pin, a Power on reset condition or a Watchdog timer reset. The
external reset pin has to be held low for at least two machine cycles i.e. 8 clock periods to be
recognized as a valid reset. In the reset condition the program counter is reset to 0000h and all the
SFRs are set to the reset condition. Since the clock is already running there is no delay and execution
starts immediately. In the Idle mode, the Watchdog timer continues to run, and if enabled, a time-out
will cause a watchdog timer interrupt which will wake up the device. The software must reset the
Watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-out.
When the W79E342 series are exiting from an Idle Mode with a reset, the instruction following the one
which put the device into Idle Mode is not executed. So there is no danger of unexpected writes.
10.2 Power Down Mode
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does
this will be the last instruction to be executed before the device goes into Power Down mode. In the
Power Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely
stopped and the power consumption is reduced to the lowest possible value. The port pins output the
values held by their respective SFRs.
The W79E342 series will exit the Power Down mode with a reset or by an external interrupt pin
enabled as level detected. An external reset can be used to exit the Power down state. The low on
/RST pin terminates the Power Down mode, and restarts the clock. The program execution will restart
from 0000h. In the Power down mode, the clock is stopped, so the Watchdog timer cannot be used to
provide the reset to exit Power down mode when its clock source is external OSC or crystal.
The sources that can wake up from the power down mode are external interrupts, keyboard interrupt
(KBI), brownout reset (BOR), watchdog timer interrupt (if WDTCK = 0) and ADC. Note that for ADC
waking up from powerdown, the device need to run on internal rc and software perform start ADC prior
to powerdown.
The W79E342 series can be waken up from the Power Down mode by forcing an external interrupt pin
activation, provided the corresponding interrupt is enabled, while the global enable (EA) bit is set. If
these conditions are met, then either a low-level or a falling-edge at external interrupt pin will re-start
the oscillator. The device will then execute the interrupt service routine for the corresponding external
interrupt. After the interrupt service routine is completed, the program execution returns to the
instruction after one which put the device into Power Down mode and continues from there. During
Power down mode, if AUXR1.LPBOV = 1 and AUXR1.BOD = 0, the internal RC clock will be enabled
and hence save power.
Publication Release Date: April 08, 2008
- 45 -
Revision A6
PRELIMINARY W79E342 DATA SHEET
11 RESET CONDITIONS
The user has several hardware related options for placing the W79E342 series into reset condition. In
general, most register bits go to their reset value irrespective of the reset condition, but there are a few
flags whose state depends on the source of reset. The user can use these flags to determine the
cause of reset using software.
11.1 Sources of reset
Figure 11-1: Reset and Vdd monitor timing diagram, disable /RST pin.
- 46 -
PRELIMINARY W79E342 DATA SHEET
Figure 11-2: Reset and Vdd monitor timing diagram, enable /RST pin.
11.1.1 External Reset
The device samples the /RST pin every machine cycle during state C4. The /RST pin must be held low
for at least two machine cycles before the reset circuitry applies an internal reset signal. Thus, this
reset is a synchronous operation and requires the clock to be running.
The device remains in the reset state as long as /RST is low and remains low up to two machine
cycles after /RST is deactivated. Then, the device begins program execution at 0000h. There are no
flags associated with the external reset, but, since the other two reset sources do have flags, the
external reset is the cause if those flags are clear.
11.1.2 Power-On Reset (POR)
When the power supply rises to proper level, the device performs a power-on reset and sets the POR
flag. The software should clear the POR flag, or it will be difficult to determine the source of future
resets. During power-on-reset, all port pins will be tri-stated. After power-on-reset, the port pins state
will determined by PRHI value.
11.1.3 Watchdog Timer Reset
The Watchdog Timer is a free-running timer with programmable time-out intervals. The program must
clear the Watchdog Timer before the time-out interval is reached to restart the count. If the time-out
interval is reached, an interrupt flag is set. 512 clocks later, if the Watchdog Reset is enabled and the
Watchdog Timer has not been cleared, the Watchdog Timer generates a reset. The reset condition is
Publication Release Date: April 08, 2008
47 -
Revision A6
PRELIMINARY W79E342 DATA SHEET
maintained by the hardware for two machine cycles, and the WTRF bit in WDCON is set. Afterwards,
the device begins program execution at 0000h.
11.2 Reset State
When the device is reset, most registers return to their initial state. The Watchdog Timer is disabled if
the reset source was a power-on reset. The port registers are set to FFh, which puts most of the port
pins in a high state. The Program Counter is set to 0000h, and the stack pointer is reset to 07h. After
this, the device remains in the reset state as long as the reset conditions are satisfied.
Reset does not affect the on-chip RAM, however, so RAM is preserved as long as VDD remains above
approximately 2V, the minimum operating voltage for the RAM. If VDD falls below 2V, the RAM
contents are also lost. In either case, the stack pointer is always reset, so the stack contents are lost.
The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset. The
WDCON SFR is set to a 0x00 0000B on the reset. WTRF (WDCON.2) is set to a 1 on a Watchdog
timer reset, but to a 0 on power on/down resets. WTRF (WDCON.2) is not altered by external reset.
EWRST (WDCON.1) is cleared by any reset. Software or any reset will clear WDIF (WDCON.3) bit.
Some of the bits in the WDCON SFR (WDRUN, WDCLR, EWRST, WDIF, WD0 and WD1) have un-
restricted read access which required Timed Access procedure to write. The remaining bits have
unrestricted write accesses. Please refer TA register description.
For all SFR reset state values, please refer to Table 8-2: Special Function Registers.
- 48 -
PRELIMINARY W79E342 DATA SHEET
12 INTERRUPTS
The W79E342 series have four priority level interrupts structure with 8 interrupt sources. Each of the
interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the
interrupts can be globally enabled or disabled.
12.1 Interrupt Sources
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, programmable
through bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to
generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine
cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected
and the interrupts request flag IEx in TCON is set. The flag bit requests the interrupt. Since the
external interrupts are sampled every machine cycle, they have to be held high or low for at least one
complete machine cycle. The IEx flag is automatically cleared when the service routine is called. If the
level triggered mode is selected, then the requesting source has to hold the pin low till the interrupt is
serviced. The IEx flag will not be cleared by the hardware on entering the service routine. If the
interrupt continues to be held low even after the service routine is completed, then the processor may
acknowledge another interrupt request from the same source.
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the
overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware
when the timer interrupt is serviced.
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the time-
out count is reached, the Watchdog Timer interrupt flag WDIF (WDCON.3) is set. If the interrupt is
enabled by the enable bit EIE.4, then an interrupt will occur.
The ADC can generate interrupt after finished ADC converter. There is one interrupt source, which is
obtained by the ADCI bit in the ADCCON SFR. This bit is not automatically cleared by the hardware,
and the user will have to clear this bit using software.
Keyboard interrupt is generated when any of the keypad connected to P0 (P0.3-P0.7) pins is pressed.
Each keypad interrupt can be individually enabled or disabled. User will have to software clear the flag
bit.
Brownout detect can cause brownout flag, BOF, to be asserted if power voltage drop below brownout
voltage level. Interrupt will occur if BOI (AUXR1.5), EBO (IE.5) and global interrupt enable are set.
All the bits that generate interrupts can be set or reset by software, and thereby software initiated
interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or
clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to disable
all interrupts.
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled
interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will
execute an internally generated LCALL instruction which will vector the process to the appropriate
interrupt vector address. The conditions for generating the LCALL are;
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being execute.
3. The current instruction does not involve a write to IE, EIE, IP0, IP0H, IP1 or IPH1 registers and is
not a RETI.
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is
repeated every machine cycle, with the interrupts sampled in the same machine cycle. If an interrupt
flag is active in one cycle but not responded to, and is not active when the above conditions are met,
the denied interrupt will not be serviced. This means that active interrupts are not remembered; every
Publication Release Date: April 08, 2008
- 49 -
Revision A6
PRELIMINARY W79E342 DATA SHEET
polling cycle is new.
The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate
service routine. This may or may not clear the flag which caused the interrupt. In case of Timer
interrupts, the TF0 or TF1 flags are cleared by hardware whenever the processor vectors to the
appropriate timer service routine. In case of external interrupt, INT0 and INT1, the flags are cleared
only if they are edge triggered. In case of Serial interrupts, the flags are not cleared by hardware. The
Watchdog timer interrupt flag WDIF has to be cleared by software. The hardware LCALL behaves
exactly like the software LCALL instruction. This instruction saves the Program Counter contents onto
the Stack, but does not save the Program Status Word PSW. The PC is reloaded with the vector
address of that interrupt which caused the LCALL. These address of vector for the different sources
are as follows:
VECTOR LOCATIONS FOR INTERRUPT SOURCES
VECTOR
ADDRESS
VECTOR
ADDRESS
SOURCE
SOURCE
External Interrupt 0
0003h
0013h
0023h
0033h
0043h
0053h
0063h
0073h
Timer 0 Overflow
000Bh
001Bh
002Bh
003Bh
004Bh
005Bh
006Bh
007Bh
External Interrupt 1
Timer 1 Overflow
-
Brownout Interrupt
-
KBI Interrupt
-
-
Watchdog Timer
ADC Interrupt
-
-
-
-
Table 12-1: Vector locations for interrupt sources
Execution continues from the vectored address till an RETI instruction is executed. On execution of the
RETI instruction the processor pops the Stack and loads the PC with the contents at the top of the
stack. The user must take care that the status of the stack is restored to what it was after the hardware
LCALL, if the execution is return to the interrupted program. The processor does not notice anything if
the stack contents are modified and will proceed with execution from the address put back into PC.
Note that a RET instruction would perform exactly the same process as a RETI instruction, but it would
not inform the Interrupt Controller that the interrupt service routine is completed, and would leave the
controller still thinking that the service routine is underway.
12.2 Priority Level Structure
The W79E342 series uses a four priority level interrupt structure (highest, high, low and lowest) and
supports up to 8 interrupt sources. The interrupt sources can be individually set to either high or low
levels. Naturally, a higher priority interrupt cannot be interrupted by a lower priority interrupt. However
there exists a pre-defined hierarchy amongst the interrupts themselves. This hierarchy comes into play
when the interrupt controller has to resolve simultaneous requests having the same priority level. This
hierarchy is defined as table below. This allows great flexibility in controlling and handling many
interrupt sources.
Priority Bits Interrupt Priority Level
IPXH IPX
0
0
Level 0 (lowest priority)
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0
1
1
1
0
1
Level 1
Level 2
Level 3 (highest priority)
Table 12-2: Four-level interrupt priority
Each interrupt source can be individually programmed to one of four priority levels by setting or
clearing bits in the IP0, IP0H, IP1, and IP1H registers. An interrupt service routine in progress can be
interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The
highest priority interrupt service cannot be interrupted by any other interrupt source. So, if two requests
of different priority levels are received simultaneously, the request of higher priority level is serviced.
If requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. This is called the arbitration ranking. Note that the arbitration
ranking is only used to resolve simultaneous requests of the same priority level.
As below Table summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits,
arbitration ranking, and whether each interrupt may wake up the CPU from Power Down mode.
Source
Flag
Vector
Interrupt
Interrupt
Priority
Arbitration
Ranking
Power
Down
Wakeup
Flag
cleared by
address
Enable Bits
Hardware,
Follow the
inverse of pin
External
Interrupt 0
IE0
0003H
002BH
EX0 (IE0.0)
EBO (IE.5)
IP0H.0, IP0.0
IP0H.5, IP0.5
1(highest)
Yes
Brownout Detect BOF
2
3
Yes
Software
Software
Watchdog Timer WDIF 0053H
EWDI (EIE.4) IP1H.4, IP1.4
Yes(1)
Hardware,
software
Timer 0 Interrupt TF0
ADC Converter ADCI
000BH
005BH
ET0 (IE.1)
EAD (IE.6)
IP0H.1, IP0.1
IP0H.6, IP0.6
4
5
No
Yes(1)
Hardware
Hardware,
Follow the
inverse of pin
External
IE1
0013H
EX1 (IE.2)
IP0H.2, IP0.2
6
Yes
Interrupt 1
KBI Interrupt
KBF
003BH
001BH
EKB (EIE.1)
ET1 (IE.3)
IP1H.1, IP1.1
IP0H.3, IP0.3
7
8
Yes
No
Software
Hardware,
software
Timer 1 Interrupt TF1
Note: 1. The Watchdog Timer and ADC Converter can wake up Power Down Mode when its clock source is from internal RC.
Table 12-3: Vector location for Interrupt sources and power down wakeup
12.3 Response Time
The response time for each interrupt source depends on several factors, such as the nature of the
interrupt and the instruction underway. In the case of external interrupts INT0 and INT1 , they are
sampled at C3 of every machine cycle and then their corresponding interrupt flags IEx will be set or
reset. The Timer 0 and 1 overflow flags are set at C3 of the machine cycle in which overflow has
occurred. These flag values are polled only in the next machine cycle. If a request is active and all
three conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes
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four machine cycles to be completed. Thus there is a minimum time of five machine cycles between
the interrupt flag being set and the interrupt service routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
service routine currently being executed. If the polling cycle is not the last machine cycle of the
instruction being executed, then an additional delay is introduced. The maximum response time (if no
other interrupt is in service) occurs if the W79E342 series are performing a write to IE, EIE, IP0, IP0H,
IP1 or IP1H and then executes a MUL or DIV instruction. From the time an interrupt source is
activated, the longest reaction time is 12 machine cycles. This includes 1 machine cycle to detect the
interrupt, 2 machine cycles to complete the IE, EIE, IP0, IP0H, IP1 or IP1H access, 5 machine cycles
to complete the MUL or DIV instruction and 4 machine cycles to complete the hardware LCALL to the
interrupt vector location.
Thus in a single-interrupt system the interrupt response time will always be more than 5 machine
cycles and not more than 12 machine cycles. The maximum latency of 12 machine cycles is 48 clock
cycles. Note that in the standard 8051 the maximum latency is 8 machine cycles which equals 96
machine cycles. This is a 50% reduction in terms of clock periods.
12.4 Interrupt Inputs
The W79E342 series have total 8 interrupt sources with two individual interrupt inputs sources. They
are IE0, IE1, BOF, KBF, WDT, TF0, TF1 and ADC. Two interrupt inputs are identical to those present
on the standard 80C51 microcontroller as show in below figures.
If an external interrupt is enabled when the W79E342 series are put into Power Down or Idle mode, the
interrupt will cause the processor to wake up and resume operation.
Figure 12-1: Interrupt Sources that can wake up from Power Down Mode
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Figure 12-2: Interrupt Sources that cannot wake up from Power-down Mode
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13 PROGRAMMABLE TIMERS/COUNTERS
The W79E342 series have two 16-bit programmable timer/counters and one programmable Watchdog
Timer. The Watchdog Timer is operationally quite different from the other two timers. Its’ timer/counters
have additional timer 0 or timer 1 overflow toggle output enable feature as compare to conventional
timer/counters. This timer overflow toggle output can be configured to automatically toggle T0 or T1 pin
output whenever a timer overflow occurs.
13.1 Timer/Counters 0 & 1
The W79E342 series have two 16-bit Timer/Counters. Each of these Timer/Counters has two 8 bit
registers which form the 16 bit counting register. For Timer/Counter 0 they are TH0, the upper 8 bits
register, and TL0, the lower 8 bit register. Similarly Timer/Counter 1 has two 8 bit registers, TH1 and
TL1. The two can be configured to operate either as timers, counting machine cycles or as counters
counting external inputs.
When configured as a "Timer", the timer counts clock cycles. The timer clock can be programmed to
be thought of as 1/12 of the system clock or 1/4 of the system clock. In the "Counter" mode, the
register is incremented on the falling edge of the external input pin, T0 for Timer 0, and T1 for Timer 1.
The T0 and T1 inputs are sampled in every machine cycle at C4. If the sampled value is high in one
machine cycle and low in the next, then a valid high to low transition on the pin is recognized and the
count register is incremented. Since it takes two machine cycles to recognize a negative transition on
the pin, the maximum rate at which counting will take place is 1/8 of the master clock frequency. In
either the "Timer" or "Counter" mode, the count register will be updated at C3. Therefore, in the "Timer"
mode, the recognized negative transition on pin T0 and T1 can cause the count register value to be
updated only in the machine cycle following the one in which the negative edge was detected.
The "Timer" or "Counter" function is selected by the "C/T " bit in the TMOD Special Function Register.
Each Timer/Counter has one selection bit for its own; bit 2 of TMOD selects the function for
Timer/Counter 0 and bit 6 of TMOD selects the function for Timer/Counter 1. In addition each
Timer/Counter can be set to operate in any one of four possible modes. The mode selection is done by
bits M0 and M1 in the TMOD SFR.
13.1.1 Time-Base Selection
The W79E342 series can operate like the standard 8051/52 family, counting at the rate of 1/12 of the
clock speed, or in turbo mode, counting at the rate of 1/4 clock speed. The speed is controlled by the
T0M and T1M bits in CKCON, and the default value is zero, which uses the standard 8051/52 speed.
13.1.2 Mode 0
In Mode 0, the timer/counter is a 13-bit counter. The 13-bit counter consists of THx (8 MSB) and the
five lower bits of TLx (5 LSB). The upper three bits of TLx are ignored. The timer/counter is enabled
when TRx is set and either GATE is 0 or INTx is 1. When C/T is 0, the timer/counter counts clock
cycles; when C/T is 1, it counts falling edges on T0 (P1.2 for Timer 0) or T1 (P0.7 for Timer 1). For
clock cycles, the time base may be 1/12 or 1/4 clock speed, and the falling edge of the clock
increments the counter. When the 13-bit value moves from 1FFFh to 0000h, the timer overflow flag
TFx is set, and an interrupt occurs if enabled. This is illustrated in next figure below.
In “Timer” mode, if output toggled enable bit of P2M1.T0OE or P2M1.T1OE is enable, T0 or T1 output
pin will toggle whenever a timer overflow occurs.
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Figure 13-1: Timer/Counters 0 & 1 in Mode 0
13.1.3 Mode 1
Mode 1 is similar to Mode 0 except that the counting register forms a 16-bit counter, rather than a 13-
bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs when the timer
moves from a count of FFFFh to 0000h. The timer overflow flag TFx of the relevant timer is set and if
enabled an interrupt will occur. The selection of the time-base in the timer mode is similar to that in
Mode 0. The gate function operates similarly to that in Mode 0.
Figure 13-2: Timer/Counters 0 & 1 in Mode 1
13.1.4 Mode 2
In Mode 2, the timer/counter is in the Auto Reload Mode. In this mode, TLx acts as 8-bit count register,
while THx holds the reload value. When the TLx register overflows from FFh to 00h, the TFx bit in
TCON is set and TLx is reloaded with the contents of THx, and the counting process continues from
here. The reload operation leaves the contents of the THx register unchanged. Counting is enabled by
the TRx bit and proper setting of GATE and INTx pins. As in the other two modes 0 and 1 mode 2
allows counting of either clock cycles (clock/12 or clock/4) or pulses on pin Tn.
In “Timer” mode, if output toggled enable bit of P2M1.T0OE or P2M1.T1OE is enable, T0 or T1 output
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pin will toggle whenever a timer overflow occurs.
Figure 13-3: Timer/Counter 0 & 1 in Mode 2
13.1.5 Mode 3
Mode 3 has different operating methods for the two timer/counters. For timer/counter 1, mode 3 simply
freezes the counter. Timer/Counter 0, however, configures TL0 and TH0 as two separate 8 bit count
registers in this mode. The logic for this mode is shown in the figure. TL0 uses the Timer/Counter 0
control bits C/T , GATE, TR0, INT0 and TF0. The TL0 can be used to count clock cycles (clock/12 or
clock/4) or 1-to-0 transitions on pin T0 as determined by C/T (TMOD.2). TH0 is forced as a clock cycle
counter (clock/12 or clock/4) and takes over the use of TR1 and TF1 from Timer/Counter 1. Mode 3 is
used in cases where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 can still be used
in Modes 0, 1 and 2, but its flexibility is somewhat limited. While its basic functionality is maintained, it
no longer has control over its overflow flag TF1 and the enable bit TR1. Timer 1 can still be used as a
timer/counter and retains the use of GATE and INT1 pin. In this condition it can be turned on and off by
switching it out of and into its own Mode 3. It can also be used as a baud rate generator for the serial
port.
In “Timer” mode, if output toggled enable bit of P2M1.T0OE or P2M1.T1OE is enable, T0 or T1 output
pin will toggle whenever a timer overflow occurs.
T0M=CKCON.3
(T1M=CKCON.4)
1/4
1
C/T=TMOD.2
Fcpu
0
0
TL0
1/12
0
7
Interrupt
T0OE
TF0
TF1
1
T0=P1.2
TR0=TCON.4
GATE=TMOD.3
INT0=P1.3
P1.2
TH0
0
7
Interrupt
T1OE
TR1=TCON.6
P0.7
Figure 13-4: Timer/Counter Mode 3
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14 NVM MEMORY
The W79E342 series has NVM data memory of 128 bytes of 8 pages and each page of 16 bytes.
The NVM memory can be read/write by customer program to access. Read NVM data is by MOVC
A,@A+DPTR instruction, and write data is by SFR of NVMADDRL, NVMDAT and NVMCON. Before
write data to NVM memory, the page must be erased by providing page address on NVMADDRL,
which address of On-Chip Code Memory space will decode, then set EER of NVMCON.7. This will
automatically hold fetch program code and PC Counter, and execute page erase. After finished, this bit
will be cleared by hardware. The erase time is ~ 5ms.
For writing data to NVM memory, user must set address and data NVMADDRL and NVMDAT, then set
EWR of NVMCON.6 to initiate nvm data write. The uC will hold program code and PC Counter, and
then write data to mapping address. Upon write completion, the EWR bit will be cleared by hardware,
the uC will continue execute next instruction. The program time is ~50us.
Figure 14-1: Memory map
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15 WATCHDOG TIMER
The Watchdog Timer is a free-running Timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs a flag is set, which can cause an interrupt if enabled, and a system reset can also be caused if
it is enabled. The interrupt will occur if the individual interrupt enable and the global enable are set. The
interrupt and reset functions are independent of each other and may be used separately or together
depending on the user’s software.
Time-Out
00 Selector
20KHz
15-bits Counter
(WDCON.3)
WDIF
internal RC
Oscillator
/Enable
0
5
Interrupt
(CONFIG0.7)
WDTCK
01
6
8
EWDI
(EIE.4)
MUX
10
11
(WDCON.2)
WTRF
9
12
14
Fcpu
WDRUN
(WDCON.7)
13
512 clock
delay
Reset
WDCLR
WD1,WD0
(Reset Watchdog) (WDCON.5~4)
(WDCON.0)
EWRST
(WDCON.1)
Figure 15-1: Watchdog Timer
The Watchdog Timer should first be restarted by using WDCLR. This ensures that the timer starts from
a known state. The WDCLR bit is used to restart the Watchdog Timer. This bit is self clearing, i.e. after
writing a 1 to this bit the software will automatically clear it. The Watchdog Timer will now count clock
cycles. The time-out interval is selected by the two bits WD1 and WD0 (WDCON.5 and WDCON.4).
When the selected time-out occurs, the Watchdog interrupt flag WDIF (WDCON.3) is set. After the
time-out has occurred, the Watchdog Timer waits for an additional 512 clock cycles. If the Watchdog
Reset EWRST (WDCON.1) is enabled, then 512 clocks after the time-out, if there is no WDCLR, a
system reset due to Watchdog Timer will occur. This will last for two machine cycles, and the
Watchdog Timer reset flag WTRF (WDCON.2) will be set. This indicates to the software that the
Watchdog was the cause of the reset.
When used as a simple timer, the reset and interrupt functions are disabled. The timer will set the
WDIF flag each time the timer completes the selected time interval. The WDIF flag is polled to detect a
time-out and the WDCLR allows software to restart the timer. The Watchdog Timer can also be used
as a very long timer. The interrupt feature is enabled in this case. Every time the time-out occurs an
interrupt will occur if the global interrupt enable EA is set.
The main use of the Watchdog Timer is as a system monitor. This is important in real-time control
applications. In case of some power glitches or electro-magnetic interference, the processor may begin
to execute errant code. If this is left unchecked the entire system may crash. Using the watchdog timer
interrupt during software development will allow the user to select ideal watchdog reset locations. The
code is first written without the watchdog interrupt or reset. Then the Watchdog interrupt is enabled to
identify code locations where interrupt occurs. The user can now insert instructions to reset the
Watchdog Timer, which will allow the code to run without any Watchdog Timer interrupts. Now the
Watchdog Timer reset is enabled and the Watchdog interrupt may be disabled. If any errant code is
executed now, then the reset Watchdog Timer instructions will not be executed at the required instants
and Watchdog reset will occur.
The Watchdog Timer time-out selection will result in different time-out values depending on the clock
speed. The reset, when enabled, will occur when 512 clocks after time-out has occurred.
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WD1
WD0
Interrupt Reset
Number of Time
time-out
Clocks
@ 20 KHz
time-out
26 + 512
29 + 512
213 + 512
215 + 512
0
0
1
1
0
1
0
1
26
29
213
215
64
3.2 mS
512
25.6 mS
409.6 mS
1638.4 mS
8192
32768
Table 15-1: Time-out values for the Watchdog Timer
The Watchdog Timer will be disabled by a power-on/fail reset. The Watchdog Timer reset does not
disable the Watchdog Timer, but will restart it. In general, software should restart the timer to put it into
a known state. The control bits that support the Watchdog Timer are discussed below.
15.1 WATCHDOG CONTROL
WDIF: WDCON.3 - Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the
Watchdog Timer. If the Watchdog interrupt is enabled (EIE.4), then an interrupt will occur (if the global
interrupt enable is set and other interrupt requirements are met). Software or any reset can clear this
bit.
WTRF: WDCON.2 - Watchdog Timer Reset flag. This bit is set whenever a watchdog reset occurs.
This bit is useful for determined the cause of a reset. Software must read it, and clear it manually. A
Power-fail reset will clear this bit. If EWRST = 0, then this bit will not be affected by the Watchdog
Timer.
EWRST: WDCON.1 - Enable Watchdog Timer Reset. This bit when set to 1 will enable the Watchdog
Timer reset function. Setting this bit to 0 will disable the Watchdog Timer reset function, but will leave
the timer running.
WDCLR: WDCON.0 - Reset Watchdog Timer. This bit is used to clear the Watchdog Timer and to
restart it. This bit is self-clearing, so after the software writes 1 to it the hardware will automatically
clear it. If the Watchdog Timer reset is enabled, then the WDCLR has to be set by the user within 512
clocks of the time-out. If this is not done then a Watchdog Timer reset will occur.
15.2 CLOCK CONTROL of Watchdog
WD1, WD0: WDCON.5, WDCON.4 - Watchdog Timer Mode select bits. These two bits select the time-
out interval for the watchdog timer. The reset time is 512 clocks longer than the interrupt time-out
value.
The default Watchdog time-out is 26 clocks, which is the shortest time-out period. The WDRUN, WD0,
WD1, EWRST, WDIF and WDCLR bits are protected by the Timed Access procedure. This prevents
software from accidentally enabling or disabling the watchdog timer. More importantly, it makes it
highly improbable that errant code can enable or disable the Watchdog Timer.
The WDTCK bit is located at bit 7 of CONFIG0 register. This bit is user to configure the clock source of
watchdog timer either it is from the internal RC or from the uC clock.
When WDTCK bit is cleared and 20KHz clock is used to run the watchdog timer, there is a chance that
the watchdog timer would hang as the counter does not increment. This problem arises when the
watchdog is set to run, (WDCON.7, WDRUN), the WDCLR bit (WDCON.0) is set to clear the watchdog
timer and the next instruction is to set the PCON register for CPU to go into idle or power-down state.
The reason this happens because the setting/clearing of WDCLR bit and the watchdog counter are
running on different clock domains, CPU clock and internal RC clock respectively. When WDCLR bit is
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set, to reset it, the counter must be non-zero. Since the counter is running off a much slower clock, the
counter may not have time to increment before the CPU clock halts as it entered the idle/power-down
mode. This results in the WDCLR bit is always set & the watchdog counter remaining at zero. The
solution to this problem is to monitor the WDCLR bit, ensuring that it’s cleared before issue the
instruction for the CPU to go into idle/power-down mode.
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16 TIME ACCESS PROCTECTION
The W79E342 series have a new feature, like the Watchdog Timer which is a crucial to proper
operation of the system. If left unprotected, errant code may write to the Watchdog control bits
resulting in incorrect operation and loss of control. In order to prevent this, the W79E342 series have a
protection scheme which controls the write access to critical bits. This protection scheme is done using
a timed access.
In this method, the bits which are to be protected have a timed write enable window. A write is
successful only if this window is active, otherwise the write will be discarded. This write enable window
is open for 3 machine cycles if certain conditions are met. After 3 machine cycles, this window
automatically closes. The window is opened by writing AAh and immediately 55h to the Timed Access
(TA) SFR. This SFR is located at address C7h. The suggested code for opening the timed access
window is;
TA
REG
MOV
MOV
0C7h
; Define new register TA, @0C7h
TA, #0AAh
TA, #055h
When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine
cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the
first write (AAh), then the timed access window is opened. It remains open for 3 machine cycles, during
which the user may write to the protected bits. Once the window closes the procedure must be
repeated to access the other protected bits.
Examples of Timed Assessing are shown below.
Example 1: Valid access
MOV
TA, #0AAh
; 3 M/C Note: M/C = Machine Cycles
MOV
TA, #055h
; 3 M/C
; 3 M/C
MOV
WDCON, #00h
Example 2: Valid access
MOV
TA, #0AAh
TA, #055h
; 3 M/C
; 3 M/C
; 1 M/C
; 2 M/C
MOV
NOP
SETB
EWRST
Example 3: Valid access
MOV
MOV
ORL
TA, #0AAh
; 3 M/C
; 3 M/C
; 3M/C
TA, #055h
WDCON, #00000010B
Example 4: Invalid access
MOV
MOV
NOP
NOP
CLR
TA, #0AAh
; 3 M/C
; 3 M/C
; 1 M/C
; 1 M/C
; 2 M/C
TA, #055h
EWT
Example 5: Invalid Access
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MOV
NOP
MOV
SETB
TA, #0AAh
; 3 M/C
; 1 M/C
; 3 M/C
; 2 M/C
TA, #055h
EWT
In the first three examples, the writing to the protected bits is done before the 3 machine cycles window
closes. In Example 4, however, the writing to the protected bit occurs after the window has closed, and
so there is effectively no change in the status of the protected bit. In Example 5, the second write to TA
occurs 4 machine cycles after the first write, therefore the timed access window is not opened at all,
and the write to the protected bit fails.
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17 KEYBOARD INTERRUPT (KBI)
The W79E342 series are provided 5 keyboard interrupt function to detect keypad status which key is
acted, and allow a single interrupt to be generated when any key is pressed on a keyboard or keypad
connected to specific pins of the W79E342 series, as shown below Figure. This interrupt may be used
to wake up the CPU from Idle or Power Down modes, after chip is in Power Down or Idle Mode.
Keyboard function is supported through Port 0 (P0.3-P0.7). It can allow any or all supported pins of
Port 0 to be enabled to cause this interrupt. Port pins are enabled by the setting of bits of KBI3 ~ KBI7
in the KBI register, as shown below Figure. The Keyboard Interrupt Flag (KBF) in the AUXR1 register
is set when any enabled pin is pulled low while the KBI interrupt function is active, and the low pulse
must be more than 1 machine cycle, an interrupt will be generated if it has been enabled. The KBF bit
set by hardware and must be cleared by software. In order to determine which key was pressed, the
KBI will allow the interrupt service routine to poll port 0.
Figure 17-1: Keyboard Interrupt
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18 I/O PORT CONFIGURATION
The W79E342 series have three I/O ports, port 0, port 1 and port 2. All pins of I/O ports can be
configured to one of four types by software except P1.5 is only input pin. When P1.5 is configured
reset pin by RPD=0 in the CONFIG 1 register, the W79E342 series can support 11 pins by use Crystal.
If used on-chip RC oscillator the P1.5 is configured input pin, the W79E342 series can be supported up
to 14 pins. The I/O ports configuration setting as below table.
PXM1.Y
PXM2.Y
PORT INPUT/OUTPUT MODE
Quasi-bidirectional
Push-Pull
0
0
1
0
1
0
Input Only (High Impedance)
P2M1.PxS=0, TTL input
P2M1.PxS=1, Schmitt input
1
1
Open Drain
Table 18-1: I/O port Configuration Table
All port pins can be determined to high or low after reset by configure PRHI bit in the CONFIG0
register. During power-on-reset, all port pins will be tri-stated. After reset, these pins are in quasi-
bidirectional mode. The port pin of P1.5 only is a Schmitt trigger input.
Enabled toggle outputs from Timer 0 and Timer 1 by T0OE and T1OE on P2M1 register, the output
frequency of Timer 0 or Timer 1 is by Timer overflow.
Each I/O port of the W79E342 series may be selected to use TTL level inputs or Schmitt inputs by
P(n)S bit on P2M1 register, where n is 0, 1 or 2. When P(n)S is set to 1, Ports are selected Schmitt
trigger inputs on Port(n). The P2.0 (XTAL2) can be configured clock output when used on-chip RC or
external Oscillator is clock source, and the frequency of clock output is divided by 4 on on-chip RC
clock or external Oscillator.
Note: During power-on-reset, all port pins will be tri-stated.
18.1 Quasi-Bidirectional Output Configuration
After chip was power on or reset, the all ports output are this mode, and output is common with the
8051. This mode can be used as both an input and output without the need to reconfigure the port.
When the pin is pulled low, it is driven strongly and able to sink a fairly large current. These features
are somewhat similar to an open drain output except that there are three pull-up transistors in the
quasi-bidirectional output that serve different purposes.
This mode has three pull-up resisters that are “strong” pull-up, “weak” pull-up and “very weak” pull-up.
The “strong” pull-up is used fast transition from logic “0” change to logic “1”, and it is fast latch and
transition. When port pins is occur from logic “0” to logic “1”, the strong pull-up will quickly turn on two
CPU clocks to pull high then turn off.
The “weak” pull-up is turned on when the input port pin is logic “1” level or itself is logic “1”, and it
provides the most source current for a quasi-bidirectional pin that output is “1” or port latch is logic “0”’.
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The “very weak” pull-up is turned on when the port latch is logic “1”. If port latch is logic “0”, it will be
turned off. The very weak pull-up is support a very small current that will pull the pin high if it is left
floating. And the quasi-bidirectional port configuration is shown as below figure.
If port pin is low, it can drives large sink current for output, and it is similar with push-pull and open
drain on sink current output.
Figure 18-1: Quasi-Bidirectional Output
18.2 Open Drain Output Configuration
To configure this mode is turned off all pull-ups. If used similar as a logic output, the port must has an
external pull-up resister. The open drain port configuration is shown as below.
Port Pin
Port Latch
Data
N
Input Data
Figure 18-2: Open Drain Output
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18.3 Push-Pull Output Configuration
The push-pull output mode has two strong pull-up and pull-down structure that support large source
and sink current output. It removes “weak” pull-up and “very weak” pull-up resister and remain “strong
pull-up resister on quasi-bidirectional output mode. The “strong” pull-up is always turns on when port
latch is logic “1” to support source current. The push-pull port configuration is shown in below Figure.
Figure 18-3: Push-Pull Output
18.4 Input Only Configuration
By configure this mode, the ports are only digital input and disable digital output. The W79E342 series
can select input pin to Schmitt trigger or TTL level input by PxM1.y and PxM2.y registers.
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19 OSCILLATOR
The W79E342 series provides three oscillator input option. These are configured at CONFIG register
(CONFIG0) that include On-Chip RC Oscillator Option, External Clock Input Option and Crystal
Oscillator Input Option. The Crystal Oscillator Input frequency may be supported are 32KHz to 1MHz,
and 4MHz to 8MHz, and without capacitor or resister.
Figure 19-1: Oscillator
19.1 On-Chip RC Oscillator Option
The On-Chip RC Oscillator is fixed at 455KHz +/- 2% frequency to support clock source. When
FOSC1, FOSC0 = 01b, the On-Chip RC Oscillator is enabled. A clock output on P2.0 (XTAL2) may be
enabled when On-Chip RC oscillator is used.
19.2 External Clock Input Option
The clock source pin (XTAL1) is from External Clock Input by FOSC1, FOSC0 = 11b, and frequency
range is form 0Hz up to 8MHz. A clock output on P2.0 (XTAL2) may be enabled when External Clock
Input is used.
The W79E342 series supports a clock output function when either the on-chip RC oscillator or the
external clock input options is selected. This allows external devices to synchronize to the W79E342
serial. When enabled, via the ENCLK bit in the P2M1 register, the clock output appears on the
XTAL2/CLKOUT pin whenever the on-chip oscillator is running, including in Idle Mode. The frequency
of the clock output is 1/4 of the CPU clock rate. If the clock output is not needed in Idle Mode, it may be
turned off prior to entering Idle mode, saving additional power. The clock output may also be enabled
when the external clock input option is selected.
19.3 CPU Clock Rate select
The CPU clock of W79E342 series may be selected by the DIVM register. If DIVM = 00H, the CPU
clock is running at 4 CPU clock pre machine cycle, and without any division from source clock (Fosc).
When the DIVM register is set to N value, the CPU clock is divided by 2(DVIM+1), so CPU clock
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PRELIMINARY W79E342 DATA SHEET
frequency division is from 4 to 512. The user may use this feature to set CPU at a lower speed rate for
reducing power consumption. This is very similar to the situation when CPU has entered Idle mode. In
addition this frequency division function affect all peripheral timings as they are all sourcing from the
CPU clock(Fcpu).
19.4 Clock Source Control
The W79E342 series has added CKCON1 SFR that allows user application to control clock source
above. The SFR consists of clock source selection bits (CLKSRC.1-0), where user can switch the
clock source. For precaution reason, these SFR bits are TA protected. For information related to TA,
please refer to section TIME ACCESS PROCTECTION.
With this clock source control, this device support clock switching from external rc to internal rc or
internal rc to external rc by user application. However, for clock switching from internal rc to external rc,
the device requires some amount of warm-up period for external rc to be stable. Duration of the warm-
up period differs for different clock source conditions (see table below). During this warm-up period, the
core clock is halted.
Clock Source
Warm-up period (due to power-on-
reset and clock switching) [unit: clocks]
External Crystal (4MHz-8MHz)
Internal RC (455KHz)
65538
4
External Crystal ( 32KHz-1MHz)
External Oscillator
4098
258
Table 19-1: Warm-up period
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20 BUZZER OUTPUT
The W79E342 series support square wave output capability. The square wave is output through P1.0
(BUZ) pin. The square wave can be enabled through bit BUZE (SFR AUXR1.1). Depending on Fcpu
clock input to the buzzer output block, user is able to control the output frequency by configure the 8-bit
Divider through BUZDIV bits in BUZCON SFR. The following shows the block diagram of square wave
output generator.
P1.0
BUZ pin
(P1.0)
Fcpu clock
1
0
1/16
8-bit Divider
Buz Output
8
1
BUZDIV.7-0
BUZE, buzzer enable bit
BUZE
Figure 20-1: Square wave output
Buzzer output frequency equation:
Fbuz = Fcpu x 1/[16x(BUZDIV+1)]
The following table tabulates examples of the BUZDIV setting needed in order to generate buzzer
output at rate close to 2KHz and 4KHz, for each cpu clock frequency.
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Frequency, Fcpu (Hz)
Division
/16
1
455000
28437
4000000
250000
6000000
375000
8000000
5000000
.
4
5
6
7
4062.429
8
9
10
11
12
13
14
15
16
17
18
19
64
.
2031.214
3906.25
96
.
3906.25
128
.
1953.125
3906.25
192
256
1953.125
1953.125
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For supporting active low buzzer, this buzzer output is implemented with an off-state of high. The
following pseudo code shows the operating procedure when working with active high and low buzzer;
(Assume PRHI=1):
1) During power on, P1.0/BUZ will be high;
<For active high buzzer>
Clear SFR P1.0
; user has to take care to output this pin low
; at the top of s/w code to avoid initial beep sound.
<For active low buzzer>
No action needed.
2) To turn-on buzzer;
<For active high buzzer>
Set BUZE bit
Set SFR P1.0 bit
<For active low buzzer>
Set BUZE bit
; to push out the buzout.
3) To turn-off buzzer;
<For active high buzzer>
Clear SFR P1.0
; user has to take care to output this pin low.
Clear BUZE bit
<For active low buzzer>
Set BUZE bit
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21 POWER MONITORING FUNCTION
Power-On Detect and Brownout are two additional power monitoring functions implemented in
W79E342 series to prevent incorrect operation during power up and power drop or loss.
21.1 Power On Detect
The Power–On Detect function is a designed to detect power up after power voltage reaches to a level
where Brownout Detect can work. After power on detect, the POR (PCON.4) will be set to “1” to
indicate an initial power up condition. The POR flag will be cleared by software.
21.2 Brownout Detect
The Brownout Detect function is detect power voltage is drops to brownout voltage level, and allows
preventing some process work or indicate power warming. The W79E342 series have two brownout
voltage levels to select by BOV (CONFIG0.4). If BOV =0 that brownout voltage level is 3.8V, If BOV =
1 that brownout voltage level is 2.5V. When the Brownout voltage is drop to select level, the brownout
detector will detect and keeps this active until VDD is returns to above brownout Detect voltage. The
Brownout Detect block is as follow.
Figure 21-1: Brownout Detect Block
When Brownout Detect is enabled by BOD (AUXR1.6), the BOF (PCON.5) flag will be set and
brownout reset will occur. If BOI (AUXR1.5) is set to “1”, the brownout detect will cause interrupt via
the EA (IE.7) and EBO (IE.5) bits is set. BOF is cleared by software.
In order to guarantee a correct detection of Brownout, The VDD fail time must be slower than
50mV/us, and rise time is slower than 2mV/us to ensure a proper reset.
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22 ANALOG-TO-DIGITAL CONVERTER
The ADC contains a DAC which converts the contents of a successive approximation register to a
voltage (VDAC) which is compared to the analog input voltage (Vin). The output of the comparator is
fed to the successive approximation control logic which controls the successive approximation register.
A conversion is initiated by setting ADCS in the ADCCON register. There are two triggering methods
by ADC to start conversion, either by purely software start or external pin STADC triggering.
The software start mode is used to trigger ADC conversion regardless of ADCCON.5 (ADCEX) bit is
set or cleared. A conversion will start simply by setting the ADCCON.3 (ADCS) bit. As for the external
STADC pin triggering mode, ADCCON.5 (ADCEX) bit has to be set and a rise edge pulse has to apply
to STADC pin to trigger the ADC conversion. For the rising edge triggering method, a minimum of at
least 2 machine cycles symmetrical pulse is required.
The low-to-high transition of STADC is recognized at the end of a machine cycle, and the conversion
commences at the beginning of the next cycle. When a conversion is initiated by software, the
conversion starts at the beginning of the machine cycle which follows the instruction that sets ADCS.
ADCS is actually implemented with tpw flip-flops: a command flip-flop which is affected by set
operations, and a status flag which is accessed during read operations.
The next two machine cycles are used to initiate the converter. At the end of the first cycle, the ADCS
status flag is set end a value of “1” will be returned if the ADCS flag is read while the conversion is in
progress. Sampling of the analog input commences at the end of the second cycle.
During the next eight machine cycles, the voltage at the previously selected pin of one of analog input
pin is sampled, and this input voltage should be stable in order to obtain a useful sample. In any event,
the input voltage slew rate must be less than 10V/ms in order to prevent an undefined result.
The successive approximation control logic first sets the most significant bit and clears all other bits in
the successive approximation register (10 0000 0000b). The output of the DAC (50% full scale) is
compared to the input voltage Vin. If the input voltage is greater than VDAC, then the bit remains set;
otherwise if is cleared.
The successive approximation control logic now sets the next most significant bit (11 0000 0000b or 01
0000 0000b, depending on the previous result), and the VDAC is compared to Vin again. If the input
voltage is greater then VDAC, then the bit remains set; otherwise it is cleared. This process is repeated
until all ten bits have been tested, at which stage the result of the conversion is held in the successive
approximation register. The conversion takes four machine cycles per bit.
The end of the 10-bit conversion is flagged by control bit ADCCON.4 (ADCI). The upper 8 bits of the
result are held in special function register ADCH, and the two remaining bits are held in ADCCON.7
(ADC.1) and ADCCON.6 (ADC.0). The user may ignore the two least significant bits in ADCCON and
use the ADC as an 8-bit converter (8 upper bits in ADCH). In any event, the total actual conversion
time is 52 ADC clock cycles. ADCI will be set and the ADCS status flag will be reset 52 cycles after the
ADCS is set. Control bits ADCCON.0 and ADCCON.1 are used to control an analog multiplexer which
selects one of 4 analog channels. An ADC conversion in progress is unaffected by an external or
software ADC start. The result of a completed conversion remains unaffected provided ADCI = logic 1;
a new ADC conversion already in progress is aborted when the idle or power down mode is entered.
The result of a completed conversion (ADCI = logic 1) remains unaffected when entering the idle
mode.
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Figure 22-1: Successive Approximation ADC
22.1 ADC Resolution and Analog Supply:
The ADC circuit has its own supply pins (AVDD and AVSS) and one pins (Vref+) connected to each
end of the DAC’s resistance-ladder that the AVDD and Vref+ are connected to VDD and AVSS is
connected to VSS. The ladder has 1023 equally spaced taps, separated by a resistance of “R”. The
first tap is located 0.5×R above AVSS, and the last tap is located 0.5×R below Vref+. This gives a total
ladder resistance of 1024×R. This structure ensures that the DAC is monotonic and results in a
symmetrical quantization error.
For input voltages between VSS and [(Vref+) + ½ LSB], the 10-bit result of an A/D conversion will be
0000000000B = 000H. For input voltages between [(Vref+) – 3/2 LSB] and Vref+, the result of a
conversion will be 1111111111B = 3FFH. Vref+ and AVSS may be between AVDD + 0.2V and VSS –
0.2 V. Vref+ should be positive with respect to VSS, and the input voltage (Vin) should be between
Vref+ and VSS.
The result can always be calculated from the following formula:
Vin
Vin
Result = 1024 ×
or Result = 1024 ×
Vref +
VDD
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Figure 22-2: The ADC Block Diagram
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23 ICP (IN-CIRCUIT PROGRAM) FLASH PROGRAM
The contexts of flash in W79E342 series are empty by default. At the first use, you must program the
flash EPROM by external Writer device or by ICP (In-Circuit Program) tool.
Note:
1.
2.
3.
When use ICP to upgrade code, the P1.5, P0.4 and P0.5 must be taken within design system board.
After program finished by ICP, to suggest system power must power off and remove ICP connector then power on.
It is recommended that user performs erase function and programming configure bits continuously without any
interruption.
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24 CONFIG BITS
The W79E342 has two CONFIG bits (CONFIG0 located at FB00h, CONFIG1 located at FB01h) that
must be defined at power up and can not be set the program after start of execution. Those features
are configured through the use of two flash EPROM bytes, and the flash EPROM can be programmed
and verified repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be
protected. The protection of flash EPROM (CONFIG1) and those operations on it are described below.
The data of these bytes may be read by the MOVX instruction at the addresses.
24.1 CONFIG0
Figure 24-1: Config0 register bits
Bit
7
Name Function
WDTCK Watchdog Timer Clock Select bit:
0: The internal 20KHz RC oscillator clock is for Watchdog Timer clock used.
1: The uC clock is for Watchdog Timer clock used.
6
5
4
RPD
PRHI
BOV
Reset Pin Disable bit:
0: Enable Reset function of Pin 1.5.
1: Disable Reset function of Pin 1.5, and it to be used as an input port pin.
Port Reset High or Low bit:
0: Port reset to low state.
1: Port reset to high state.
Brownout Voltage Select bit:
0: Brownout detect voltage is 3.8V.
1: Brownout detect voltage is 2.5V.
3
2
-
Reserved.
BPFR
Bypass Clock Filter.
0: Disable Clock Filter.
1: Enable Clock Filter.
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1
0
Fosc1
Fosc0
CPU Oscillator Type Select bit 1.
CPU Oscillator Type Select bit 0.
Oscillator Configuration bits:
Fosc1
Fosc0
OSC source
0
0
0
1
4MHz ~ 8MHz crystal
Internal 455KHz RC
Oscillator
1
1
0
1
32KHz-1MHz crystal
External Oscillator in XTAL1
24.2 CONFIG1
Figure 24-2: Config1 register bits
C7: 2K byte Flash EPROM Lock bit
This bit is used to protect the customer’s program code. It may be set after the programmer finishes
the programming and verifies sequence. Once this bit is set to logic 0, both the Flash EPROM data
and CONFIG Registers can not be accessed again.
C6: 128 byte NVM Data Lock bit
This bit is used to protect the customer’s 128 bytes of data code. It may be set after the programmer
finishes the programming and verifies sequence. Once this bit is set to logic 0, both the 128 bytes of
Flash EPROM data and CONFIG Registers can not be accessed again.
Bit 7 Bit 6 Function Description
1
1
Both security of 2KB program code and 128 Bytes data area are not locked. They can
be erased, programmed or read by Writer or ICP.
0
1
The 2KB program code area is locked. It can’t be read by Writer or ICP. The 128 Bytes
data area can be program or read. The bank erase is invalid.
1
0
0
0
Not supported.
Both security of 2KB program code and 128 Bytes data area are locked. They can’t be
read by Writer or ICP.
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25 ELECTRICAL CHARACTERISTICS
25.1 Absolute Maximum Ratings
SYMBOL
DC Power Supply
Input Voltage
PARAMETER
CONDITION
-0.3
RATING
+7.0
UNIT
V
VDD−VSS
VIN
VSS-0.3
-40
VDD+0.3
+85
V
Operating Temperature
Storage Temperature
TA
°C
°C
Tst
-55
+150
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
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25.2 DC ELECTRICAL CHARACTERISTICS
(VDD−VSS = 2.4~5V±10%, TA = -40~85°C, Fosc = 8MHz, unless otherwise
specified.
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD=4.5V ~ 5.5V @ 8MHz
VDD=2.4V ~ 5.5V @ 455KHz
Operating Voltage (455KHz)
2.4
5.5
V
IDD1
IDD2
No load, /RST = VSS, VDD =
5.0V, BOR disabled.
Operating Current (455KHz)
mA
No load, /RST = VDD, VDD =
5.0V, BOR disabled, RUN NOP
0.54
7.2
No load, /RST = VDD, VDD =
5.0V, BOR enabled, RUN NOP
No load, /RST = VDD, VDD =
5.0V, ADC enabled, BOR
disabled, RUN NOP
No load, /RST = VDD, VDD =
5.0V, ADC enabled, BOR
enabled, RUN NOP
IDD3
IDD4
No load, /RST = VSS, VDD =
3.0V, BOR disabled.
No load, /RST = VDD, VDD =
3.0V, BOR disabled, RUN NOP
No load, /RST = VDD, VDD =
3.0V, BOR enabled, RUN NOP
No load, /RST = VDD, VDD =
3.0V, ADC enabled, BOR
disabled, RUN NOP
No load, /RST = VDD, VDD =
3.0V, ADC enabled, BOR
enabled, RUN NOP
IDD5
IDD6
No load, /RST = VSS, VDD =
5.0V, BOR disabled.
Operating Current (8MHz)
No load, /RST = VDD, VDD =
5.0V, BOR disabled, RUN NOP
4.8
No load, /RST = VDD, VDD =
5.0V, BOR enabled, RUN NOP
10.4
No load, /RST = VDD, VDD =
5.0V, ADC enabled, BOR
disabled, RUN NOP
No load, /RST = VDD, VDD =
5.0V, ADC enabled, BOR
enabled, RUN NOP
IDD7
IDD8
No load, /RST = VSS, VDD =
3.0V, BOR disabled.
No load, /RST = VDD, VDD =
3.0V, BOR disabled, RUN NOP
No load, /RST = VDD, VDD =
3.0V, BOR enabled, RUN NOP
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PRELIMINARY W79E342 DATA SHEET
No load, /RST = VDD, VDD =
3.0V, ADC enabled, BOR
disabled, RUN NOP
No load, /RST = VDD, VDD =
3.0V, ADC enabled, BOR
enabled, RUN NOP
Idle Current (455KHz)
1.26
0. 25
0.9
mA
mA
mA
No load, RST = VDD, VDD =
5.0V
No load, RST = VDD, VDD =
5.0V, BOR disabled.
No load, RST = VDD, VDD =
3.0V
0.10
3.15
2.1
mA
mA
mA
No load, RST = VDD, VDD =
3.0V, BOR disabled.
Idle Current (8MHz)
Power Down Current
No load, RST = VDD, VDD =
5.0V
No load, RST = VDD, VDD =
5.0V, BOR disabled.
0.1
0.1
1
5
uA
uA
TA=25℃
TA=-45~80℃
Input / Output
V
DD = 5.5V, VIN = 0V or
Input Current P0, P1, P2
IIN1
IIN2
ILK
-50
-55
-
-45
-
+10
-30
μA
μA
μA
μA
VIN=VDD
Input Current P1.5(RST pin)[1]
V
DD = 5.5V, VIN = 0.45V
VDD = 5.5V, 0<VIN<VDD
VDD = 5.5V, VIN<2.0V
Input Leakage Current P0,
P1, P2 (Open Drain)
-10
+10
-500
-450
-200
-246
[*3]
ITL
-
Logic 1 to 0 Transition
Current P0, P1, P2
-93
0
-
-
-
-56
1.0
0.6
Vdd=2.4 Vin = 1.3v
VDD = 4.5V
Input Low Voltage P0, P1, P2
(TTL input)
VIL1
VIH1
VIL3
VIH3
V
V
V
V
0
VDD = 2.4V
VDD
+0.2
2.0
1.5
-
-
VDD = 5.5V
Input High Voltage P0, P1, P2
(TTL input)
VDD
+0.2
VDD =2.4V
VDD = 4.5V
Input Low Voltage XTAL1[*2]
0
0
-
-
0.8
0.4
VDD = 3.0V
VDD
+0.2
3.5
2.4
-
-
VDD = 5.5V
VDD = 3.0V
Input High Voltage XTAL1[*2]
VDD
+0.2
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Negative going threshold
(Schmitt input)
VILS
VIHS
-0.5
-
-
0.3VDD
V
V
Positive going threshold
(Schmitt input)
0.7VDD
VDD+0.5
Hysteresis voltage
VHY
ISR1
0.2VDD
-26
V
-16
-5
-36
-11
mA
mA
VDD = 4.5V, VS = 2.4V
DD =2.4V, VS = 2.0V
Source Current P0, P1, P2
(PUSH-PULL Mode)
-7.9
V
-150
-39
13
-210
-53
-360
-69
24
VDD = 4.5V, VS = 2.4V
VDD =2.4V, VS = 2.0V
VDD = 4.5V, VS = 0.45V
μA
μA
Source Current P0, P1, P2
(Quasi-bidirectional Mode)
ISR2
Sink Current P0, P1, P2
18.5
15
mA
ISK2
(Quasi-bidirectional and
PUSH-PULL Mode)
9
21
VDD = 2.4V, VS = 0.45V
V
DD = 4.5V, IOL = 50 mAVDD
=
-
0.5
VV
Output Low Voltage P0, P1,
P2 (Quasi-bidirectional and
PUSH-PULL Mode)
4.5V, IOL = 20 mA
VOL1
VOH1
VOH2
-
0.5
0.1
3.7
2.4
0.9
0.4
-
V
V
V
VDD = 4.5V, IOL = 20 mA
VDD = 2.4V, IOL = 3.2 mA
VDD = 4.5V, IOH = -100μA
-
2.4
1.9
Output High Voltage P0, P1,
P2 (Quasi-bidirectional Mode)
-
V
DD = 2.4V, IOH = -30μA
DD = 4.5V, IOH = -50mA VDD
V
3.4
-
VV
V
= 4.5V, IOH = -16mA
Output High Voltage P0, P1,
P2 (PUSH-PULL Mode)
2.4
1.9
2.4
3.5
3.4
2.4
-
-
-
VDD = 4.5V, IOH = -16mA
VDD = 2.4V, IOH = -3.2mA
Brownout voltage with BOV=1 VBO2.5
Brownout voltage with BOV=0 VBO3.8
2.7
4
V
V
-
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25.3 The ADC Converter DC ELECTRICAL CHARACTERISTICS
(VDD−VSS = 3.0~5V, TA = -40~85°C, Fosc = 4MHz, unless otherwise specified.)
PARAMETER
SYMBOL
SPECIFICATION
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
Analog input
AVin
VSS-0.2
200KHz
VDD+0.2
5MHz
ADC clock
ADCCLK
-
Hz
ADC block circuit
input clock
1
Conversion time
Differential non-linearity
Integral non-linearity
Offset error
tC
52tADC
us
DNL
INL
Ofe
Ge
-1
-2
-1
-1
-3
-
-
-
-
-
+1
+2
+1
+1
+3
LSB
LSB
LSB
%
Gain error
Absolute voltage error
Ae
LSB
Notes:
1. tADC: The period time of ADC input clock.
25.4 AC ELECTRICAL CHARACTERISTICS
(VDD−VSS = 2.7~5V, TA = -40~85°C.)
Parameter
Specification
Test Conditions
Min.
-2
Typ.
Max.
Unit
%
Vdd=5V,room temperature
On-chip RC oscillator calibration
(Fosc = 455KHz)
2
7
-7
%
-45~85℃
On-chip RC oscillator calibration
(Fosc = 20KHz)
-50
100
%
Wakeup time for power-on-reset
and clock switching:
65538
4
o External crystal
clks
o Internal RC (455KHz)
o 32KHz-1MHz external crystal
o External oscillator
4098
258
Vdd rise rate
Vdd fail rate
2
mS/uV
mS/uV
mS
50
30
70
Erase time
Whole chip
byte
Programming time
uS
Publication Release Date: April 08, 2008
Revision A6
- 83 -
PRELIMINARY W79E342 DATA SHEET
tCLCL
tCLCH
tCLCX
tCHCL
tCHCX
Note: Duty cycle is 50%.
25.5 EXTERNAL CLOCK CHARACTERISTICS
PARAMETER
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
SYMBOL
tCHCX
MIN.
12.5
12.5
-
TYP.
MAX.
UNITS
nS
NOTES
-
-
-
-
-
tCLCX
-
nS
tCLCH
10
10
nS
tCHCL
-
nS
- 84 -
PRELIMINARY W79E342 DATA SHEET
25.6 AC SPECIFICATION
VARIABLE CLOCK MIN. VARIABLE CLOCK MAX.
PARAMETER
SYMBOL
UNITS
Oscillator Frequency
1/tCLCL
0
8
MHz
25.7 TYPICAL APPLICATION CIRCUITS
CRYSTAL
4MHz ~ 8MHz
1MHz
CONFIG0.FOSC1 CONFIG0.FOSC0
C1
without
TBD
C2
without
TBD
R
0
1
1
1
0
0
0
0
without
TBD
TBD
TBD
TBD
455KHz
TBD
TBD
TBD
32.768KHz
The above table shows the reference values for crystal applications.
Publication Release Date: April 08, 008
RevisiA6
- 85 -
PRELIMINARY W79E342 DATA SHEET
26 PACKAGE DIMENSIONS
26.1 16-pin SOP
Figure 26-1: 16-pin SOP 300mil
- 86 -
PRELIMINARY W79E342 DATA SHEET
26.2 16-pin DIP
A
Figure 26-2: 16-pin DIP 300mil
Publication Release Date: April 08, 2008
- 87 -
Revision A6
PRELIMINARY W79E342 DATA SHEET
27 REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
Novemver
12, 2007
A1
-
Initial Issued
Do not disclose CBOD description.
27, 84
January 8,
2008
A2
A3
4, 33,
64, 65,
66, 83
1. Changed WDT to run on 20KHz when WDTCK = 0.
2. Changed WDT clock dividers.
February 18
88
1. Added 20KHz on-chip rc oscillator to AC Electrical
Characteristic table.
98
2. Added 32.768KHz, 455KHz and 1MHz to Typical Application
Circuit table.
74, 91
3. Updated Oscillator figure, Warm-up period. Changed “External
Crystal 455KHz” to “External Crystal 32KHz-1MHz”.
4. Added reset and vdd monitor timing diagrams.
51
88
5. Added operating current if ADC is enabled for 3V, 5V at 8MHz
and 455KHz.
A4
February 27
6. Added power consumption current when brownout enabled for
3V and 5V, at 8MHz and 455MHz, in DC Electrical Table.
88
4
7. Re-phrased feature list for external oscillator and crystal.
93
8. Added columns Fosc0 and Fosc1 to typical application circuit
table.
88
9. Removed HS0 from DC Electrical Table.
10. Updated new Winbond logo.
All
All
6
82
90
1. Updated Winbond header.
2. Changed to W79E342 part number.
3. Removed 14 pins package.
4. Removed HS1 from config register.
5. Renamed SA8207 to W79E342.
A5
A6
March 28
April 08
All
All
86
1.
2.
3.
Removed NVMADDRH register
Revised NVMADDRL register
Add SOP16 package dimension.
- 88 -
PRELIMINARY W79E342 DATA SHEET
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation wherein personal injury, death or severe property or
environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
2727 North First Street, San Jose,
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
200336 China
CA 95134, U.S.A.
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 1-408-9436666
FAX: 1-408-5441798
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: 81-45-4781881
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
Publication Release Date: April 08, 2008
Revision A6
- 89 -
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