W81281 [WINBOND]
USB Keyboard/ Device Controller; USB键盘/设备控制器
| 型号： | W81281 |
| 厂家： | 
WINBOND |
| 描述： | USB Keyboard/ Device Controller |
| 文件： | 总38页 (文件大小：356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W81281
USB Keyboard/
Device Controller
W81281
W81281 Data Sheet Revision History
Pages
Dates
Version Version
on Web
Main Contents
1
2
09/01/1997
0.50
First published.
All
12/16/1997
7/12/1999
0.51
0.6
Update Features
Update registers description
3
4
5
6
7
8
9
10
11
Please note that all data and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result
in personal injury. Winbond customers using or selling these products for use in
such applications do so at their own risk and agree to fully indemnify Winbond for
any damages resulting from such improper use or sales.
Publication Release Date: July 1999
- I -
Revision 0.60
W81281
Preliminary
TABLE OF CONTENT
1.
2.
3
GENERAL DESCRIPTION................................................................................................................1
FEATURES .........................................................................................................................................2
BLOCK DIAGRAM .............................................................................................................................3
PIN CONFIGURATION ......................................................................................................................4
PIN DESCRIPTION ............................................................................................................................6
4.
5.
...........................................................................................................................................6
.........................................................................................................................................8
5.1
5.2
5.3
40 PIN DIP
28-PIN SOP
48-PIN LQFP
......................................................................................................................................9
6 FUNCTIONAL DESCRIPTION...............................................................................................................11
IRST
F
N
I F
IRST UT TORAGE
O
RGANIZATION
(FIFO'S) O
....................................................................11
6.1
S
6.1.1
INTERFACE TO THE MICROCONTROLLER:
.......................................................................11
EGISTER ESCRITPION
......................................................................................................................12
........................................................................................................................12
.......................................................................................................................13
6.2
6.2.1
6.2.2
R
D
Status Registers
Control Registers
ESET
R
.................................................................................................................................................15
6.3
6.3.1
6.3.2
External Reset (Hardware Reset)
Warm Reset (Software Reset)
............................................................................................16
.................................................................................................16
.................................................................................................................................16
USB SUSPEND
..................................................................................................................................16
USB RESUME:
6.4
6.5
7.
PROGRAMMING NOTES: ..............................................................................................................17
ONTROL EGISTERS CCESS
...........................................................................................................17
:
7.1
7.2
7.3
7.4
7.5
C
S
R
A
TATUS EGISTERS CCESS
..............................................................................................................17
:
R
A
S
FIFO A
CCESS
.................................................................................................................................17
:
ET TALL FOR NDPOINT
........................................................................................................17
0 - 4 :
S
S
S
E
ET ULL ATA FOR
RANSACTION OF
IN T EP 0 :
................................................................................18
N
D
8.
ELECTRICAL CHARACTERISTICS & CAPACITANCE..............................................................19
USB KEYBOARD SAMPLE APPLICATION .................................................................................22
PACKAGE DIMENSIONS................................................................................................................24
9.
10.
APPENDIX A: WINBOND( W81281-004) DEFAULT MATRIX CODE.................................................28
II
Publication Release Date: July 1999
Revision 0.60
W81281
USB Keyboard/ Device Controller
1.
GENERAL DESCRIPTION
W81281 is a low cost, high integration single-chip microcontroller with Universal Serial Bus (USB) interface
for keyboard application, it includes the core of Winbond 8-bit microprocessor W78C52 which works on
6MHz. It implements a standard PC keyboard and enables connection to host system through low-speed
(1.5Mhz) USB connection . It complies with USB Specification Revision 1.0 and HID Class Definition
Revision 1.0.
For Keyboard application, W81281 supports an 18 X 8 keyboard scan matrix, which allows suspend wake
up, and also provides a port for PS/2 mouse. It consists of an 8051 compatible CPU core, a 6K-byte ROM,
a 256-byte SRAM, and three 16-bit programmable timers.
W81281 supports one device address and five endpoints, one bi-directional endpoint for Control transfer
and four unidirectional endpoints for Interrupt IN transfer. Through modification of firmware of W78C52, it
can be used for multifunction device design, such as USB-IR receiver and any Slow-Speed (1.5Mhz) USB
peripheral device controller.
Publication Release Date: July 1999
- 1 -
Revision 0.60
W81281
Preliminary
2.
FEATURES
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Fully compliant with USB spec. Rev.1.0 and HID Class Rev. 1.0
Supporting one device address and five endpoints (one Control transfer, four Interrupt transfer)
Implementing USB keyboard with PS/2 mouse connection
Microsoft Intellimouse(3D mouse) Supported
Supporting 8-bit sense (row) input with wake up interrupt on falling edge, internal pull-ups
Supporting 18-bit drive (column) output, open drain with pull-ups
8-bit 8051 compatible CPU core
6K-byte ROM
256-byte SRAM
3 direct drive LED outputs with internal series resisters
Supporting warm reset
Built-in low voltage reset and EFT/ESD protection circuit
Built-in Watch-Dog Timer for device recovery
Support Win98 system control function
µ
Support suspend/wake-up function, suspend current under 500 A
Internal 3.3V regulator supported
40-pin DIP, 28-pin SOP and 48-pin LQFP packages
5V CMOS Device
2
Publication Release Date: July 1999
Revision 0.60
Preliminary
3
Winbond USB Keyboard/HID Controller
Winbond USB Keyboard/HID Controller
(W81281)
IDSEL(P30)
LED0-2(P33-P35)
(x3)
RST
P02SO*
INT
USB
Transceiver
USB SIE
D-
XFRI
8052
Micro
.
.
.
(x18)
D+
Endpoints
Processor
P1SI*
Power Down
Control
VSS
VBUS
5V to 3.3V
Conversion
Clock
Generator
Watch Dog
Timer
(x8)
EFT, LVRST
VDD
*P02SO: P00-P07,P20-P27,SCO16,SCO17
*P1SI:P10-P17
X2
X1
PSCL
(P32) (P31)
PSDA
External Clock Circuit
Publication Release Date:
1999
60
W81281
Preliminary
4.
PIN CONFIGURATION
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSS
D+
D-
SO17
SO16
2
3
SO00/P00
SO01/P01
SO02/P02
SO03/P03
SI4/P14
4
VDD3
5
SI0/P10
SI1/P11
SI2/P12
SI3/P13
SO04/P04
SO05/P05
6
7
8
SI5/P15
SI6/P16
SI7/P17
9
10
11
12
13
14
15
16
17
18
19
20
SO015/P27
SO014/P26
SO013/P25
SO012/P24
SO011/P23
SO010/P22
SO06/P06
SO07/P07
IDSEL/P30
LED0/P33
PSCLK/P32
PSDA/P31
LED1/P34
LED2/P35
RESET
SO09/P21
SO08/P20
VDD
X2
X1
40-PIN DIP
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AD00
AD01
AD02
AD03
WK0
WK1
WK2
WK3
NC
VSS
VSS
D+
D -
VDD3
AD04
AD05
AD06
AD07
XALE
XWR
XRD
RESET
X2
9
10
11
12
13
14
NC
XMODE
XINT
VDD
X1
28-PIN SOP
4
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
36
25
24
37
SO01/P02
NC
SO09/P21
SO08/P20
SO00/P00
SO16
VDD
X1
SO17
EESCL
VID1
X2
W81281D
RESET
VID0
EESDA
LED2/P35
LED1/P34
PSDA/P31
PSCLK/P32
LED0/P33
VSS
VSS
D+
D-
48
13
1
12
48-pin LQFP
5
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
5.
PIN DESCRIPTION
40 PIN DIP
5.1
PIN NO.
NAME
TYPE
POWER
I/O
DESCRIPTION
1
VSS
D+
Ground
2
USB signal (+)
USB signal (-)
3
D-
I/O
4
VDD3
POWER
I/O
DC power 3.3V output
5
SI0/P10
µ
Keyboard scan Input 0 / Internal C IO port 1.0
6
SI1/P11
I/O
Keyboard scan Input 1 / Internal µC IO port 1.1
7
SI2/P12
I/O
µ
Keyboard scan Input 2 / Internal C IO port 1.2
8
SI3/P13
I/O
µ
Keyboard scan Input 3 / Internal C IO port 1.3
9
SO04/P04
SO05/P05
SO06/P06
SO07/P07
IDSEL/P30
LED0/P33
PSCLK/P32
PSDA/P31
LED1/P34
LED2/P35
RESET
I/O
µ
Keyboard scan Output 04 / Internal C IO port 0.4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O
µ
Keyboard scan Output 05 / Internal C IO port 0.5
I/O
µ
Keyboard scan Output 06 / Internal C IO port 0.6
I/O
µ
Keyboard scan Output 07 / Internal C IO port 0.7
I/O
Vendor ID selection / Internal µC IO port 3.0
I/O
µ
Num. Lock LED / Internal C IO port 3.3
I/O
µ
PS/2 mouse clock pin / Internal C IO port 3.2
I/O
µ
PS/2 mouse data pin / Internal C IO port 3.1
I/O
µ
Caps Lock LED / Internal C IO port 3.4
I/O
µ
Scroll Lock LED / Internal C IO port 3.5
INPUT
Chip reset pin
X2
OUTPUT Clock output
X1
INPUT
POWER
I/O
Clock input
VDD power
VDD
SO08/P20
SO09/P21
SO10/P22
SO11/P23
SO12/P24
SO13/P25
µ
Keyboard scan Output 08 / Internal C IO port 2.0
I/O
µ
Keyboard scan Output 09 / Internal C IO port 2.1
I/O
µ
Keyboard scan Output 10 / Internal C IO port 2.2
I/O
Keyboard scan Output 11 / Internal µC IO port 2.3
I/O
µ
Keyboard scan Output 12 / Internal C IO port 2.4
I/O
µ
Keyboard scan Output 13 / Internal C IO port 2.5
6
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
5.1 40-PIN DIP, continued
PIN NO.
29
NAME
TYPE
I/O
DESCRIPTION
Keyboard scan Output 14 / Internal µC IO port 2.6
SO14/P26
SO15/P27
SI7/P17
30
I/O
µ
Keyboard scan Output 15 / Internal C IO port 2.7
31
I/O
µ
Keyboard scan Input 7 / Internal C IO port 1.7
32
SI6/P16
I/O
µ
Keyboard scan Input 6 / Internal C IO port 1.6
33
SI5/P15
I/O
µ
Keyboard scan Input 5 / Internal C IO port 1.5
34
SI4/P14
I/O
µ
Keyboard scan Input 4 / Internal C IO port 1.4
35
SO03/P03
SO02/P02
SO01/P01
SO00/P00
SO16
I/O
µ
Keyboard scan Output 03 / Internal C IO port 0.3
36
I/O
µ
Keyboard scan Output 02 / Internal C IO port 0.2
37
I/O
Keyboard scan Output 01 / Internal µC IO port 0.1
38
I/O
µ
Keyboard scan Output 00 / Internal C IO port 0.0
39
OUTPUT
OUTPUT
Keyboard scan Output 16
Keyboard scan Output 17
40
SO17
7
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
5.2
28-PIN SOP
NAME
PIN NO.
TYPE
POWER
POWER
I/O
DESCRIPTION
1
VSS
VSS
D+
Ground
2
Ground
USB signal (+)
USB signal (-)
3
4
D-
I/O
DC power 3.3V output
5
VDD3
AD04
AD05
AD06
AD07
XALE
XWR
XRD
RESET
X2
POWER
I/O
6
µ
µ
µ
µ
µ
µ
µ
C Interface AD04 (Address/Data 04)
C Interface AD05 (Address/Data 05)
C Interface AD06 (Address/Data 06)
C Interface AD07 (Address/Data 07)
C Interface ALE (Address Latch Enable)
C Interface WR (Data Write)
7
I/O
8
I/O
9
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O
I/O
I/O
C Interface RD (Data Read)
Chip reset pin
Clock output
Clock input
VDD power
INPUT
OUTPUT
INPUT
POWER
I/O
X1
VDD
XINT
XMODE
NC
µ
C Interface INT (Interrupt)
I/O
Controller mode setting, it should be kept high
Not Used
I/O
NC
I/O
Not Used
WK3
WK2
WK1
WK0
AD03
AD02
AD01
AD00
INPUT
INPUT
INPUT
INPUT
I/O
Wakeup pin, Active low and keep more than 100ns
Wakeup pin, Active low and keep more than 100ns
Wakeup pin, Active low and keep more than 100ns
Wakeup pin, Active low and keep more than 100ns
µ
µ
µ
µ
C Interface AD03 (Address/Data 03)
C Interface AD02 (Address/Data 02)
C Interface AD01 (Address/Data 01)
C Interface AD00 (Address/Data 00)
I/O
I/O
I/O
8
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
5.3
48-PIN LQFP
NAME
PIN NO.
TYPE
POWER
I/O
DESCRIPTION
DC power 3.3V output
Keyboard scan Input 0 / Internal C IO port 1.0
1
VDD3
2
SI0/P10
SI1/P11
SI2/P12
SI3/P13
NC
µ
3
I/O
µ
Keyboard scan Input 1 / Internal C IO port 1.1
4
I/O
µ
Keyboard scan Input 2 / Internal C IO port 1.2
5
I/O
µ
Keyboard scan Input 3 / Internal C IO port 1.3
6
none
I/O
Not Used
7
SO04/P04
SO05/P05
SO06/P06
SO07/P07
IDSEL/P30
NC
µ
Keyboard scan Output 04 / Internal C IO port 0.4
8
I/O
µ
Keyboard scan Output 05 / Internal C IO port 0.5
9
I/O
µ
Keyboard scan Output 06 / Internal C IO port 0.6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
I/O
µ
Keyboard scan Output 07 / Internal C IO port 0.7
I/O
µ
Vendor ID selection / Internal C IO port 3.0
none
I/O
Not Used
LED0/P33
PSCLK/P32
PSDA/P31
LED1/P34
LED2/P35
RESET
µ
Num. Lock LED / Internal C IO port 3.3
I/O
µ
PS/2 mouse clock pin / Internal C IO port 3.2
I/O
µ
PS/2 mouse data pin / Internal C IO port 3.1
I/O
µ
Caps Lock LED / Internal C IO port 3.4
I/O
µ
Scroll Lock LED / Internal C IO port 3.5
INPUT
Chip reset pin
X2
OUTPUT Clock output
X1
INPUT
POWER
I/O
Clock input
VDD power
VDD
SO08/P20
SO09/P21
NC
µ
Keyboard scan Output 08 / Internal C IO port 2.0
I/O
µ
Keyboard scan Output 09 / Internal C IO port 2.1
none
I/O
Not Used
SO10/P22
SO11/P23
SO12/P24
SO13/P25
SO14/P26
SO15/P27
µ
Keyboard scan Output 10 / Internal C IO port 2.2
I/O
µ
Keyboard scan Output 11 / Internal C IO port 2.3
I/O
µ
Keyboard scan Output 12 / Internal C IO port 2.4
I/O
µ
Keyboard scan Output 13 / Internal C IO port 2.5
I/O
µ
Keyboard scan Output 14 / Internal C IO port 2.6
I/O
µ
Keyboard scan Output 15 / Internal C IO port 2.7
9
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
5.3 48-PIN LQFP, continued
PIN NO.
31
NAME
TYPE
I/O
DESCRIPTION
SI7/P17
SI6/P16
SI5/P15
SI4/P14
SO03/P03
SO02/P02
SO01/P01
SO00/P00
SO16
µ
Keyboard scan Input 7 / Internal C IO port 1.7
32
I/O
µ
Keyboard scan Input 6 / Internal C IO port 1.6
33
I/O
µ
Keyboard scan Input 5 / Internal C IO port 1.5
34
I/O
µ
Keyboard scan Input 4 / Internal C IO port 1.4
35
I/O
µ
Keyboard scan Output 03 / Internal C IO port 0.3
36
I/O
µ
Keyboard scan Output 02 / Internal C IO port 0.2
37
I/O
µ
Keyboard scan Output 01 / Internal C IO port 0.1
38
I/O
µ
Keyboard scan Output 00 / Internal C IO port 0.0
39
OUTPUT Keyboard scan Output 16
40
SO17
OUTPUT Keyboard scan Output 17
41
EESCL
VID1
OUTPUT Clock pin of External serial EEPROM
42
INPUT
INPUT
I/O
Vendor ID selection 1
Vendor ID selection 0
Data pin of External serial EEPROM
Ground
43
VID0
44
EESDA
VSS
45
POWER
POWER
I/O
46
VSS
Ground
47
D+
USB signal (+)
48
D-
I/O
USB signal (-)
10
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
6
FUNCTIONAL DESCRIPTION
6.1
First In First Out Storage (FIFO'S) Organization
The W81281 has six FIFO's, one for receiving and five for transmitting.
FIFO or
SRAM
SIZE (Byte )
NOTES
8
8
8
8
8
8
Endpt 0
Receiving
Data received on upstream port which contains the correct address
and pids will be stored here for the CPU core to read.
Endpt 0
Transmitting
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
Endpt 1
Transmitting
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
Endpt 2
Transmitting
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
Endpt 3
Transmitting
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
Endpt 4
Transmitting
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
6.1.1 INTERFACE TO THE MICROCONTROLLER:
The FIFOs communicate with the CPU core by address 06H 0f External DATA Memory Access of CPU
during IP.6 = "1".The FIFO access steps are firstly set IP.6 = "1" in CPU core. Secondly, CPU core selects
FIFO to access by setting the followed bits in control register 2 :
EP0_RD_EN : read "IN" FIFO of Endpoint 0 ( EP0 ).
EP0_WR_EN : write "OUT" FIFO of Endpoint 0 ( EP0 ).
EP1_WR_EN : write "OUT" FIFO of Endpoint 1 ( EP1 ).
EP2_WR_EN : write "OUT" FIFO of Endpoint 2 ( EP2 ).
EP3_WR_EN : write "OUT" FIFO of Endpoint 3 ( EP3 ).
EP4_WR_EN : write "OUT" FIFO of Endpoint 4 ( EP4 ).
Then access FIFO by address 06H of External DATA Memory Access of CPU. For detailed programming
steps, refer to section 7.3 Programming Note.
11
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
6.2
Register Descritpion
The CPU core accesses registers by External DATA Memory Access during IP.6 = "1"‘1’
6.2.1 Status Registers
CPU core can set "High" at USB_EventINT_EN bit of control register 4 to enable interrupt of USB events to
INT0. When interrupt comes, CPU reads status register 0 and 1 to check which event occurs. ( refer to
section 7.2 for accessing Status Registers )
Status Register 0: Address = 00H (Interrupt Event Flags)
BIT
SYMBOL
DESCRIPTION
7
NAK_EP0_IN
NAK occurs from EP0 for IN Transaction. ( only valid during
NakEP0In_INT_EN = 1 in Control Register 3 )
6
5
4
3
2
1
0
ACK_EP0_SETUP ACK occurs from EP0 for SETUP Transaction
ACK_EP0_OUT
ACK_EP0_IN
ACK_EP1_IN
ACK_EP2_IN
ACK_EP3_IN
ACK_EP4_IN
ACK occurs from EP0 for OUT Transaction
ACK occurs from EP0 for IN Transaction
ACK occurs from EP1 for IN Transaction
ACK occurs from EP2 for IN Transaction
ACK occurs from EP3 for IN Transaction
ACK occurs from EP4 for IN Transaction
Status Register 1: Address = 01H (Interrupt Event Flags)
BIT
7-6
5
SYMBOL
VID[1:0]
Reserved
EP0OutNullData receiving Null Data at EP0 during OUT Transaction
DESCRIPTION
Keyboard Scan Matrix Selection.
must ignore this value.
4
3
Suspend_In
USB_Reset
Resume_In
Reserved
Suspend Mode active ( no traffic on USB Bus > 3 mS )
receiving Reset command from USB Bus
receiving Resume command from USB Bus
must ignore this value
2
1
0
12
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
Status Register 2: Address = 07H (Data Byte Count of EP0 IN FIFO)
BIT
7-4
3-0
SYMBOL
Reserved
DataLength_CNT[3:0]
DESCRIPTION
must ignore those values
Number of Data byte for EP0 FIFO ( receiving Data from USB Bus
)
6.2.2 Control Registers
( All registers are set to 00h at power up.)( refer to section 7.1 for accessing Control Registers )
Control Register 0: Address = 02H (Endpoint Enable Control)
BIT
7-5
4
SYMBOL
Reserved
DESCRIPTION
must keep bits = “0”
USB_Speed
set igh” for Full Speed; set "Low" for Low Speed
set "High" to enable Endpoint 1
3
2
1
0
EP1_EN
EP2_EN
EP3_EN
EP4_EN
set "High" to enable Endpoint 2
set "High" to enable Endpoint 3
set "High" to enable Endpoint 4
Control Register 1: Address = 03H (Device Address Setting)
BIT
7
SYMBOL
DESCRIPTION
Bus_Connection
connect up stream port on USB Bus after chip initialization done
6-0
Device_Address[6:0] Setup Device Address
Control Register 2: Address = 04H (FIFO Access Control)
BIT
7
SYMBOL
Reserved
Set_Stall
DESCRIPTION
must keep bit = "0".
6
Set Stall for EP 0 -4 ( refer to section 7.4 for programming )
13
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
5
4
EP0_RD_EN
EP0_WR_EN
Set "High" before reading IN FIFO of EP0 (receiving Data from USB Bus )
Set "High" before writting OUT FIFO of EP0 (transmitting Data to USB Bus
)
3
2
1
EP1_WR_EN
EP2_WR_EN
EP3_WR_EN
EP4_WR_EN
Set "High" before writting OUT FIFO of EP1 (transmitting Data to USB Bus
)
Set "High" before writting OUT FIFO of EP2 (transmitting Data to USB Bus
)
Set "High" before writting OUT FIFO of EP3 (transmitting Data to USB Bus
)
0
Set "High" before writting OUT FIFO of EP4 (transmitting Data to USB Bus
)
Control Register 3: Address = 05H (USB Event Control)
BIT
7
SYMBOL
Reserved
NakEP0In_INT_EN Enable interrupt event when NAK comes from EP0 for IN Transaction
DESCRIPTION
must keep bit = "0"
6
5
Set_EP0NullData
set Null Data for IN Transaction of EP 0 ( refer to section 7.5 for
programming )
4
3
Warm_Reset
Resume_Out
Active Warm Reset
Send Resume command (K-state) to USB Bus ( Set_Suspend should
be “1” )
2
1
Set_Suspend
Read_Event
Set suspend mode active
Set "High" during reading Status Registers ( refer to section 7.2 for
programming )
0
Set_EP0_Nak
Set "High" for responsing Nak when IN/OUT Transaction of EP0 come
14
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
Control Register 4: Address = 08H (Interrupt Enable Control)
BIT
7-4
3
SYMBOL
Reserved
DESCRIPTION
must keep bits = "0"
Remote_Wakeup_EN
USB_EventINT_EN
SCANOUT[17]
for Remote Wakeup Enable from Keystroke or Mouse moving
for USB event interrupt enable
2
1
output port value of port SO17
0
SCANOUT[16]
output port value of port SO16
Control Register 5: Address = 09H (CPU Reset Control)
BIT
7-2
1
SYMBOL
Reserved
UC_WarmReset_EN
DESCRIPTION
must keep bit = "0"
set "High" for reseting CPU when Warm_Reset = "1"
0
DisconUSB_Bus_Disable set "High" keeping device conecting with USB Bus during
software or hardware reset
set ow” disconnecting with USB Bus during software or
hardware reset
Control Register 6: Address = 0EH (Watch Dog Timer Reset)
BIT
SYMBOL
DESCRIPTION
7-0
Reset_WDT
Clear WDT = 00H when set Reset_WDT = AAH
6.3
Reset
The W81281 supports three types of reset. During a reset, all registers of the CPU core and USB return to
their default status, and USB device address is set to zero.
15
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
6.3.1 External Reset (Hardware Reset)
As in 8051 series controller, the external RESET signal is sampled at S5P2. To take effect, it must be held
high at least two machine cycles while the oscillator is running.
An internal trigger circuit in the reset line is used to deglitch the reset line. The reset logic also has a special
glitch remocal circuit that ignores glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON(with exception of bit 4) to
00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
6.3.2 Warm Reset (Software Reset)
W81281 provides a warm reset by setting "High" at Warm_Reset bit of control register 3.
The W81281 handles the USB reset function independently from the CPU core. If a Single Ended Zero
(SE0) is detected on the upstream port for greater then 2.5us, then the interrupt is enabled. The CPU core
read flag from USB_Reset bit of status register 1 then CPU
- to reset the device address to 0, and enter the default state. No any reset timing occurs.
or
- to set "High" at Warm_Reset bit of control register
6.3.3 WDT Reset (Hardware Reset)
There is a Watch Dog Timer installed in W81C281. CPU should periodically clear WDT to 00H by setting
Reset_WDT=AAH before WDT time out. If CPU hangs WDT will time-out and cause hardware reset.
6.4
USB SUSPEND
If there is no upstream activity for 3 msec then the Suspend_In flag is set and the interrupt enabled. When
Suspend_In flag is read, CPU core actives power down mode for W81281 go into suspend
6.5
USB RESUME:
The suspend state can be exit by a 'resume'. The resume can occur by three methods.
•
The host can send a resume to all ports by placing a 0 (K state) on the bus. The W81281 sees the
resume, , and enables the interrupt. In this case, the CPU core does not have to perform any functions.
•
•
The host can reset the bus.
When any falling edge is detected on CPU port1(keystrokes). The CPU core will exit from power down
mode and initiate a resume by setting Resume_Out in the Control Register 3 which will cause a K state
to be sent. To un-resume, the CPU core must clear the Resume_Out bit in the Control Register 3.
16
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
7.
PROGRAMMING NOTES:
The W81281 uses reserved bit of the Interrupt Priority Register IP.6 as a pre-decoding bit to implement a
alternative register and FIFO by External Data Memory Access of CPU core. Programming functions
described as below:
7.1
7.2
Control Registers Access:
Step 1: set IP.6 = 1
Step 2: access Control Register (by MOVX Instruction)
Step 3: set IP.6 = 0
Status Registers Access:
Step 1: set IP.6 = 1
Step 2 : set Read_Event = 1 in Control Register 3 ( by MOVX Instruction )
step 3 : access Status Registers ( by MOVX Instruction )
step 4 : set IP.6 = 0
7.3
FIFOs Access :
step 1 : set IP.6 = 1
step 2 : set EP0_RD_EN/EPX_WR_EN = 1 ( X : 0 - 4) (by MOVX Instruction )
step 3 : access FIFO by address 06H of MOVX Instruction
step 4 : set EP0_RD_EN/EPX_WR_EN = 0 ( X : 0 - 4) (by MOVX Instruction )
step 5 : set IP.6 = 0
7.4
Set Stall for Endpoint 0 - 4 :
step 1 : set IP.6 = 1
step 2 : set Set_Stall = 1 (by MOVX Instruction )
step 3 : set EP0_RD_EN/EPX_WR_EN = 1 ( X : 0 - 4) (by MOVX Instruction )
step 4 : set EP0_RD_EN/EPX_WR_EN = 0 ( X : 0 - 4) (by MOVX Instruction )
step 5 : set Set_Stall = 0 (by MOVX Instruction )
step 6 : set IP.6 = 0
Note : 1. EP0_RD_EN = 1 for OUT Transaction of EP0.
17
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
2. EP0_WR_EN = 1 for IN Transaction of EP0.
7.5
Set Null Data for IN Transaction of EP 0 :
step 1 : set IP.6 = 1
step 2 : set Set_EP0NullData = 1 (by MOVX Instruction )
step 3 : set EP0_WR_EN = 1 (by MOVX Instruction )
step 4 : set EP0_WR_EN = 0 (by MOVX Instruction )
step 5 : set Set_EP0NullData = 0 (by MOVX Instruction )
step 6 : set IP.6 = 0
18
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
8.
ELECTRICAL CHARACTERISTICS & CAPACITANCE
¢ J
¢ J
(Ta = 0 to + 70 , VDD = +5V 5% )
SYMBOL
VDD
VIL
DESCRIPTION
Power Support
MIN.
TYP.
MAX.
5.5
UNIT
V
NOTE
4.0
5.0
Input Low Voltage (except RESET)
Input Low Voltage (RESET)
0.8
V
VIL1
0.6
V
VIH1
VIH2
VOH
VOL
Input High Voltage (except RESET)
Input High Voltage (RESET)
2.0
3.5
V
V
Output High Voltage (except D+/D-)
Output Low Voltage (except D+/D-)
2.4
V
IOH=-4mA
IOL= 4mA
0.4
-10
V
IOFL
Output Leakage Current (High-Z
state)
10
10
uA
IIH
IIL
Input Leakage Current
-10
-10
uA
uA
VDD=5.5V
VIN=VDD
VDD=5.5V
VIN=VSS
Input Leakage Current
10
19
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
Symbol
Conditions
Min
Max
Unit
D+/D- Leakage Current:
Hi-Z State Data Line Leakage
D+/D- Input Levels:
ILO
0 V < VIN < 3.3V
-10
+10
µ
A
Differential Input Sensitivity
Differential Common Mode Range
Single Endge Receiver Threshold
D+/D- Output Levels:
Static Output Low
VDI
VCM
VSE
0.2
0.8
0.8
V
(D+)-(D-)
Includes VDI range
2.5
2.0
V
V
VOL
VOH
0.3
3.6
V
V
Ω
RL of 1.5k to 3.6V
Static Output High
2.8
Ω
RL of 1.5k to GND
D+/D- Capacitance:
Transceiver Capacitance
D+/D- Driver Characteristics:
Transition Time:
CIN
Pin to GND
20
pF
Rise Time
ns
ns
%
V
TR
TF
CL=50pF/350pF
CL=50pF/350pF
(TR / TF)
75
75
80
1.3
300
300
125
2.0
Fall Time
Rise / Fall Time Matching
Output Signal Crossover Voltage
D+/D- Data Source Timings:
Low Speed Data Rate
TRFM
VCRS
TDRATE Ave.Bit Rate
1.4775 1.5225 Mbs
1
(1.5Mb/s .5%)
Source Differential Driver Jitter
To Next Transition
95
150
1.50
100
ns
ns
TDJ1
TDJ2
-95
-150
1.25
-40
For Paired Transitions
Source EOP Width
TEOPT
TDEOP
µ
s
Differential to EOP Transition Skew
D+/D- Data Receiver Timings:
Receiver Data Jitter Tolerance
To Next Transition
ns
75
45
ns
ns
ns
TDJR1
TDJR2
TLST
-75
-45
For Paired Transitions
Receiver SE0 Tolerance during
Differential Transition
210
20
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
EOP Width at receiver
Must reject as EOP
Must accept as EOP
ns
ns
TEORP1
TEOPR2
330
675
21
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
9.
USB KEYBOARD SAMPLE APPLICATION
1. For 40 pin DIP package
W81281 USB Keyboard Reference
VCC
U1
+
VCC
C6
10u
5
6
7
22
4
1
ScanIn0
ScanIn1
ScanIn2
ScanIn3
ScanIn4
ScanIn5
ScanIn6
ScanIn7
SI0
SI1
SI2
SI3
SI4
SI5
SI6
SI7
VDD
VDD3
VSS
R6
R7
30
30
U-
U+
8
34
33
32
31
19
RESET
R1
7.5K
RESET
21
20
X1
X2
X1
X2
VCC
38
37
36
35
9
10
11
12
USB1
USB-CONN
ScanOut0
ScanOut1
ScanOut2
ScanOut3
ScanOut4
ScanOut5
ScanOut6
ScanOut7
SO0
SO1
SO2
SO3
SO4
SO5
SO6
SO7
13
IDSEL
IDSEL
L7 FB
1
2
3
L8 FB
L1 FB
L2 FB
14
17
18
LED0
LED1
LED2
LED0
LED1
LED2
+
C5
10u
4
C4
0.1u
6
5
23
24
25
26
27
28
29
30
3
2
D-
D+
ScanOut8
ScanOut9
SO8
SO9
D-
D+
ScanOut10
ScanOut11
ScanOut12
ScanOut13
ScanOut14
ScanOut15
SO10
SO11
SO12
SO13
SO14
SO15
16
15
PSDA
PSCLK
PSDA
PSCLK
39
40
ScanOut16
ScanOut17
SO16
SO17
VCC
W81281
L3
VCC
FB
CapsLoc
PSDA
L4
L5
JP4
1
2
3
4
5
6
ScrollLoc
D3
FB
FB
NumLoc
D1
D2
PSCLK
R
an
100ohm
be short
while
not used
L6
PS/2 MOUSE
FB
C7
47p
C1
47p
R2
100
R3
100
R4
100
LED0
LED1
LED2
VCC
+
C2
C8
10u
X1
JP1
JUMPER
JP2
JUMPER
JP3
RESET
30p
C3
X1
6MHZ Crystal / Resonator
JUMPER
Only one
Jumper
can be
short
R5
3.3K
X2
30p
or all
IDSEL
22
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
For 48 pin LQFP package reference circuit
W81281 (48pin LQFP) USB Keyboard Reference Schematic
VCC
CapsLock
VCC
L3
NumLock
D1
D2
D3
FB
ScrollLock
VCC
R
100ohm can
be short
while Jumper
not used
L4
L5
JP4
PSDA
U1
1
2
3
4
5
6
+
C6
2
3
4
21
1
45
46
10u
FB
FB
ScanIn0
ScanIn1
ScanIn2
ScanIn3
ScanIn4
ScanIn5
ScanIn6
ScanIn7
SI0
SI1
SI2
SI3
SI4
SI5
SI6
SI7
VDD
VDD3
VSS
R2
R3
R4
PSCLK
100
100
100
L6
5
VSS
34
33
32
31
FB
18
RESET
RESET
PS/2 MOUSE
20
19
X1
X2
X1
X2
C7
C1
38
37
36
35
7
8
9
10
LED0
LED1
LED2
ScanOut0
ScanOut1
ScanOut2
ScanOut3
ScanOut4
ScanOut5
ScanOut6
ScanOut7
SO0
SO1
SO2
SO3
SO4
SO5
SO6
SO7
47p
47p
11
43
42
IDSEL
VID0
VID1
IDSEL
VID0
VID1
13
16
17
LED0
LED1
LED2
LED0
LED1
LED2
Option
22
23
25
26
27
28
29
30
48
47
D-
D+
ScanOut8
ScanOut9
SO8
SO9
D-
D+
JP1
JP2
JP3
ScanOut10
ScanOut11
ScanOut12
ScanOut13
ScanOut14
ScanOut15
SO10
SO11
SO12
SO13
SO14
SO15
14
15
41
44
PSCLK
PSDA
EESCL
EESDA
VCC
PSCLK
PSDA
EESCL
EESDA
JUMPER JUMPER JUMPER
U2
Only one
Jumper
can be
short
or all open
EESDA
EESCL
5
4
3
2
1
SDA
SCL
RC
VSS
A2
6
7
8
6
12
24
NC
NC
NC
A1
39
40
ScanOut16
ScanOut17
SO16
SO17
VCC
A0
IDSEL
24LC04B
W81C281-48
JP4
VID0
JUMPER
VCC
JP5
VID1
R6
R7
30
30
U-
U+
JUMPER
VCC
R1
7.5K
C2
VCC
USB1
+
C8
X1
X2
USB-CONN
FB
FB
10u
L7
L8
L1
L2
30p
1
2
3
4
RESET
X1
6M
+
C5
C3
inbond
C4
R5
10u
FB
FB
0.1u
3.3K
WINBOND ELECTRONICS CORP.
30p
Title
W81281 USB Keyboard Reference Schematic
Size
B
Document Number
281DEMO4.SCH
Rev
1.3
Date:
Monday, January 25, 1999
Sheet
1
of
1
23
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
10.
PACKAGE DIMENSIONS
40-pin DIP
Dimension in mm
Dimension in inches
Symbol
Min. Nom. Max. Min. Nom. Max.
5.33
0.210
A
0.010
0.150
0.016
0.048
0.008
0.25
3.81
0.41
1.22
0.20
A1
0.155
0.018
0.050
0.010
2.055
0.160
0.022
0.054
0.014
2.070
0.610
3.94
0.46
4.06
0.56
A
B
B
c
2
1.27
1.37
1
0.36
0.25
52.58
15.49
13.97
2.79
52.20
15.24
13.84
2.54
D
E
E1
D
0.590
0.540
0.090
0.600
0.545
0.100
14.99
13.72
2.29
40
21
0.550
0.110
e
1
3.05
0
0.120
0
0.130
0.140
15
3.30
3.56
15
L
a
1
E
17.02
0.630 0.650
0.670
0.090
16.00
16.51
e
S
A
2.29
Notes:
1. Dimensions D Max & S include mold flash or
tie bar burrs.
1
20
E
S
2. Dimension E1 does not include interlead flash.
3. Dimensions D & E1 include mold mismatch and
c
Base Plane
2
A
A
L
.
are determined at the mold parting line.
4. Dimension B1 does not include dambar
A1
Seating Plane
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
B
e
1
eA
a
B 1
28-pin SOP
15
c
28
Control demensions are in milme
DIMENSION IN MM
SYMBOL
DIMENSION IN INCH
MIN.
MAX.
2.65
MIN.
MAX.
2.35
0.093
0.104
0.012
0.020
A
E
HE
0.10
0.33
0.23
A1
0.004
0.013
0.30
0.51
b
c
0.32
0.009
0.291
0.013
0.299
7.40
E
D
7.60
L
17.70
18.10
0.697
0.713
1
14
e
0.050 BSC
1.27 BSC
D
O
0.25
H
10.65
0.10
10.00
0.394
0.419
0.004
E
Y
L
A
0.40
0
1.27
8
0.016
0
0.050
8
Y
θ
SEATING PLANE
e
GAUGE PLANE
A1
b
24
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
48-pin LQFP
H
D
D
25
36
Dimension in inch
Dimension in mm
Symbol
A
Min. Nom. Max. Min. Nom. Max.
1.60
---
---
---
0.05
1.35
0.15
1.45
1
A
24
37
1.40
0.20
---
2
A
0.17
0.09
0.27
0.20
b
c
E
E
7.00
7.00
H
D
E
e
0.50
9.00
9.00
D
H
H
L
L
y
48
13
E
0.45
0.75
0.60
1.00
0.08
3.5
1
---
0
---
7
1
12
e
b
0
Notes:
c
1. Dimensions D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
2
A
A
A
1
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
See Detail F
L
y
Seating Plane
L 1
Detail F
Headquarters
No. 4, Creation Rd. III
Science-Based Industrial Park
Hsinchu, Taiwan
TEL: 886-35-770066
FAX: 886-35-789467
Winbond Electronics
(North America) Corp.
2730 Orchard Parkway
San Jose, CA 95134 U.S.A.
TEL: 1-408-9436666
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
TEL: 852-27516023-7
FAX: 852-27552064
FAX: 1-408-9436668
www: http://www.winbond.com.tw/
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
TLX: 16485 WINTPE
25
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
26
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
27
Publication Release Date: July 1999
Revision 0.60
W81281
W81281 USB Keyboard Reference
VCC
Preliminary
10u
U1
+
VCC
C6
5
6
7
22
4
1
ScanIn0
ScanIn1
ScanIn2
ScanIn3
ScanIn4
ScanIn5
ScanIn6
ScanIn7
SI0
SI1
SI2
SI3
SI4
SI5
SI6
SI7
VDD
VDD3
VSS
R6
R7
30
30
U-
U+
8
34
33
32
31
19
RESET
R1
7.5K
RESET
21
20
X1
X2
X1
X2
VCC
38
37
36
35
9
10
11
12
USB1
ScanOut0
ScanOut1
SO0
SO1
SO2
SO3
SO4
SO5
SO6
SO7
W812U8S1B-CO(NN48pin LQFP) USB Keyboard Reference Schematic
13
IDSEL
IDSEL
L7 FB
1
2
3
4
ScanOut2
ScanOut3
ScanOut4
ScanOut5
ScanOut6
ScanOut7
L8 FB
L1 FB
L2 FB
14
17
18
LED0
LED1
LED2
VCC
LED0
LED1
LED2
+
C5
10u
C4
0.1u
6
5
CapsLock
23
24
25
26
27
28
29
30
3
D-
D2D+
ScanOut8
VCC
ScanOut9
SO8
SO9
D-
D+
L3
2
NumLock
D1
D3
FB
ScanOut10
ScanOut11
ScanOut12
ScanOut13
ScanOut14
ScanOut15
SO10
SO11
SO12
SO13
SO14
SO15
ScrollLock
16
15
PSDA
PSCLK
VCC
PSDA
P1S0C0oLhmKcan
be short
R
while Jumper
not used
L4
L5
JP4
PSDA
U1
1
2
3
4
5
6
+
39
40
C6
ScanOut16
ScanOut17
SO16
SO17
2
3
4
21
1
45
46
10u
FB
FB
ScanIn0
ScanIn1
ScanIn2
ScanIn3
ScanIn4
ScanIn5
ScanIn6
ScanIn7
SI0
SI1
SI2
SI3
SI4
SI5
SI6
SI7
VDD
VDD3
VSS
R2
R3
R4
PSCLK
100
100
100
VCC
L6
5
VSS
W81281
34
33
32
31
FB
18
RESET
RESET
PS/2 MOUSE
20
19
X1
X2
L3
FB
X1
X2
C7
C1
VCC
38
37
36
LED0
ScanOut0
ScanOut1
ScanOut2
ScanOut3
ScanOut4
ScanOut5
ScanOut6
ScanOut7
SO0
SO1
47p
47p
11
43
42
IDSEL
VID0
VID1
IDSEL
VID0
VID1
CapsLoc
PSDASO2
L4
JP4
35
LED1
SO3
7
SO4
8
13
16
17
LED0
LED1
LED2
1
2
3
4
5
6
ScrollLoc
D3
SO5
SO6
LED0
FB
9
LED2
D2
NumLoc
LED1
D1
PS1C0 LK
SO7
L5 LED2
Option
22
48
47
D-
D+
ScanOut8
ScanOut9
SO8
23
D-
D+
FB
SO9
25
JP1
JP2
JP3
ScanOut10
ScanOut11
ScanOut12
ScanOut13
ScanOut14
ScanOut15
SO10
26
14
15
41
44
PSCLK
PSDA
EESCL
EESDA
VCC
SO11
27
PSCLK
PSDA
L6
R 100ohm
PS/2 MOUSE
EESDA
SO12
28
JUMPER JUMPER JUMPER
be short
while
an
U2
FB
SO13
29
EESCL
Only one
Jumper
can be
short
or all open
5
4
3
2
1
C7
C1
SO14
30
EESDA
SDA
VSS
A2
6
7
8
EESCL
not used
Jumper
R2
100
R3
100
R4
100
SO15
39
SCL
RC
47p
47p
6
NC
NC
NC
A1
12
24
ScanOut16
ScanOut17
SO16
40
VCC
A0
SO17
IDSEL
24LC04B
W81C281-48
LED0
LED1
LED2
VCC
JP4
VID0
JUMPER
VCC
+
C2
C8
10u
JP5
X1
VID1
JP3
JP1
JUMPER
JP2
R6
R7
30
30
U-
U+
RESET
30p
JUMPER
VCC
R1
X1
6MHZ Crystal / Resonator
JUMPER
JUMPER
7.5K
Only one
Jumper
can be
short
R5
3.3K
C3
VCC
C2
X2
USB1
+
C8
X1
USB-CONN
FB
FB
10u
30p
L7
L8
L1
L2
30p
or all
IDSEL
1
2
3
4
RESET
X1
6M
+
C5
C3
inbond
C4
R5
X2
10u
FB
FB
0.1u
3.3K
WINBOND ELECTRONICS CORP.
30p
Title
W81281 USB Keyboard Reference Schematic
Size
B
Document Number
281DEMO4.SCH
Rev
1.3
Date:
Monday, January 25, 1999
Sheet
1
of
1
APPENDIX A: WINBOND( W81281-004) DEFAULT MATRIX CODE
0000
0801
PID: (with PS/2 mouse) PID:
0802
(without PS/2 mouse)
VID:
101(AT)/102(Europe+Macro)(+Fn)/103(Korean)(Brazillian)/106(Japan.)+Windows 95 keys compatible
28
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
NOTE 1: The contents in the table are hexadecimal HID codes and function descriptor.
2: Six are scan-in lines, Sox are scan-out lines.
3: The three ACPI power management keys for Windows 98 are Power (SI4-SO12), Sleep (SI5-
SO13) and Wakeup (SI1-SO12).
Multimedia Buttons & Reserved Buttons (W81281-004)
HID Code
E8
Functions (ref. Qtronix)
Play/Pause
E9
Stop/Eject
Rewind
EA
EB
Forward
EC
Record
ED
Volume+
EE
Volume-
EF
Mute
F0
WWW
F1
Previous
Next
F2
F3
Stop
F4
Search
F5
Scroll-Up
Scroll-Down
Menu
F6
F7
F8
Suspend
F9
Coffee
FA
Xfer
FB
Calculator
Reserved (OnN-oPwower)
Reserved (OnN-oSwleep)
Reserved (OnN-oWwakeup)
Reserved
FC
FD
FE
FF
Publication Release Date: July 1999
Revision 0.60
30
W81281
Preliminary
Winbond USB Product Roadmap
W81182
Legacy HUB
W81C180
4 pot HUB
W81181D
4 pot HUB
HUB
W81C280
USB K/B
W81281
USB 8052
W81282
HUB+K/B
K/B
2Q/99
3Q/99
4Q/99
1Q/2K
2H/98 1Q/99
Winbond USB Product Brief
• W81C180: USB 4 Port Hub Controller
• W81181D: High Integrated USB 4 Port Hub Controller
• W81182:USB Legacy Hub, Translate EPP, Serial, PS/2
to USB Connection, Including 4 port USB Hub
• W81C280: USB K/B Controller
• W81281: High Integrated USB+8052 Controller or
USB K/B Controller
• W81282:USB 4 Port Hub + K/B Controller
Publication Release Date: July 1999
Revision 0.60
33
W81281
Preliminary
Headquarters
No. 4, Creation Rd. III
Science-Based Industrial Park
Hsinchu, Taiwan
TEL: 886-35-770066
FAX: 886-35-789467
www: http://www.winbond.com.tw/
Winbond Electronics
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
TEL: 852-27516023-7
FAX: 852-27552064
(North America) Corp.
2730 Orchard Parkway
San Jose, CA 95134 U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade
marks of products and companies mentioned in this data sheet belong to their respective owners.
34
Publication Release Date: July 1999
Revision 0.60
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
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