W83627UHG [WINBOND]
WINBOND LPC I/O; WINBOND LPC I / O
| 型号： | W83627UHG |
| 厂家： | 
WINBOND |
| 描述： | WINBOND LPC I/O |
| 文件： | 总241页 (文件大小：1798K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W83627UHG
WINBOND LPC I/O
Date: May/25/2007 Revision: 1.0
W83627UHG
W83627UHG Data Sheet Revision History
WEB
VERSION
PAGES
DATES
VERSION
MAIN CONTENTS
1
2
NA
9/14/2006
0.5
NA
For Customer reference. (PRELIMINARY)
1. Remove the section of AT Interface in
Chapter 9 Floppy Disk Controller.
2. Remove sections 8.4 and 8.5 (EXTFDD and
EXT2FDD).
3. Remove section 9.6 (OnNow / Security
Keyboard and Mouse Wake-Up).
NA
11/29/2006
0.6
NA
4. Update “S5COLD State” to “S5 State”.
5. Update
Characteristic.
6. Update the description of CRF0.
“VDD”
to
“5VCC”
in
DC
1.
2.
Substitute “TControl” with “TBase”
Modify the pin descriptions of INDEX#, SOUTF,
TRAK0#,
HEFRAS,
WP#,
PENKBC,
RDATA#,
VIN0
DSKCHG#,
VIN2,
~
CPUVCORE, VREF, PLED and PSOUT#
3.
4.
5.
6.
Revise the pin name of Pin 52 to PFDCUART
Modify the IO type of Pin 90, 92 and 77.
Update Figure 7-4 and 7-8
Modify section 7.3.1, 7.5, 7.7.2, 7.7.3, 7.7.4 and
18.2
3
NA
05/25/2007
1.0
NA
7.
8.
9.
Modify Chapter 13 Power Management Event
Add section 13.4 PWROK Generation
Remove Configuration Register CR[24h], bit 0;
CR[26h], bit 7 and Logical Device A, CR[E4h],
bit 4
10. Modify Logical Device A, CR[E6h], bit 3 and bit
5; Logical Device C, CR[E5h], bit 0
11. Re-define the strapping function of pin 122.
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Publication Release Date: May 25, 2007
-I-
Revision 1.0
W83627UHG
Table of Contents -
1.
2.
3.
4.
5.
GENERAL DESCRIPTION ......................................................................................................... 1
FEATURES................................................................................................................................. 2
BLOCK DIAGRAM ...................................................................................................................... 5
PIN LAYOUT............................................................................................................................... 6
PIN DESCRIPTION..................................................................................................................... 7
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
LPC Interface.................................................................................................................. 8
FDC Interface.................................................................................................................. 8
Multi-Mode Parallel Port ............................................................................................... 10
Serial Port & Infrared Port Interface.............................................................................. 12
KBC Interface................................................................................................................ 17
Hardware Monitor Interface .......................................................................................... 17
PECI Interface............................................................................................................... 18
SST Interface................................................................................................................ 18
Advanced Configuration and Power Interface.............................................................. 18
5.10 General Purpose I/O Port ............................................................................................. 19
5.10.1 GPIO Power Source.....................................................................................................19
5.10.2 GPIO-1 Interface ..........................................................................................................19
5.10.3 GPIO-2 Interface ..........................................................................................................19
5.10.4 GPIO-3 Interface ..........................................................................................................19
5.10.5 GPIO-4 Interface ..........................................................................................................19
5.10.6 GPIO-5 Interface ..........................................................................................................20
5.10.7 GPIO-6 Interface ..........................................................................................................20
5.10.8 WDTO# and SUSLED Pins ..........................................................................................20
5.11 POWER PINS............................................................................................................... 20
6.
7.
CONFIGURATION REGISTER ACCESS PROTOCOL ........................................................... 21
6.1
Configuration Sequence ............................................................................................... 23
6.1.1 Enter the Extended Function Mode ................................................................................23
6.1.2 Configure the Configuration Registers............................................................................24
6.1.3 Exit the Extended Function Mode...................................................................................24
6.1.4 Software Programming Example....................................................................................24
HARDWARE MONITOR ........................................................................................................... 26
7.1
7.2
General Description...................................................................................................... 26
Access Interfaces.......................................................................................................... 26
7.2.1 LPC Interface .................................................................................................................27
7.2.2 I2C Interface....................................................................................................................29
Analog Inputs................................................................................................................ 31
7.3.1 Voltages Over 2.048 V or Less Than 0 V .......................................................................32
7.3.2 Voltage Detection ...........................................................................................................32
7.3.3 Temperature Sensing.....................................................................................................33
SST Command Summary............................................................................................. 35
7.4.1 Command Summary.......................................................................................................36
7.3
7.4
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W83627UHG
7.4.2 Combination Sensor Data Format ..................................................................................37
PECI.............................................................................................................................. 38
Fan Speed Measurement and Control ......................................................................... 40
7.6.1 Fan Speed Measurement...............................................................................................40
7.6.2 Fan Speed Control .........................................................................................................41
7.6.3 SMART FANTM Control...................................................................................................42
Interrupt Detection ........................................................................................................ 49
7.7.1 SMI# Interrupt Mode.......................................................................................................49
7.7.2 OVT# Interrupt Mode......................................................................................................52
7.7.3 Caseopen Detection.......................................................................................................53
7.7.4 BEEP Alarm Function.....................................................................................................54
7.5
7.6
7.7
8.
HARDWARE MONITOR REGISTER SET................................................................................ 55
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Address Port (Port x5h) ................................................................................................ 55
Data Port (Port x6h)...................................................................................................... 55
SYSFANOUT PWM Output Frequency Configuration Register - Index 00h (Bank 0) . 56
SYSFANOUT Output Value Select Register - Index 01h (Bank 0) .............................. 56
CPUFANOUT PWM Output Frequency Configuration Register - Index 02h (Bank 0). 57
CPUFANOUT Output Value Select Register - Index 03h (Bank 0).............................. 57
FAN Configuration Register I - Index 04h (Bank 0)...................................................... 58
SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register - Index 05h
(Bank 0)..................................................................................................................................... 58
8.9 CPUTIN Target Temperature Register/ CPUFANIN Target Speed Register - Index 06h
(Bank 0)..................................................................................................................................... 59
8.10 Tolerance of Target Temperature or Target Speed Register - Index 07h (Bank 0) ..... 59
8.11 SYSFANOUT Stop Value Register - Index 08h (Bank 0)............................................. 59
8.12 CPUFANOUT Stop Value Register - Index 09h (Bank 0)............................................. 60
8.13 SYSFANOUT Start-up Value Register - Index 0Ah (Bank 0)....................................... 60
8.14 CPUFANOUT Start-up Value Register - Index 0Bh (Bank 0)....................................... 60
8.15 SYSFANOUT Stop Time Register - Index 0Ch (Bank 0).............................................. 61
8.16 CPUFANOUT Stop Time Register - Index 0Dh (Bank 0)............................................. 61
8.17 Fan Output Step Down Time Register - Index 0Eh (Bank 0) ....................................... 61
8.18 Fan Output Step Up Time Register - Index 0Fh (Bank 0) ............................................ 62
8.19 Reserved Registers - Index 10h (Bank 0) .................................................................... 62
8.20 Reserved Registers - Index 11h (Bank 0) .................................................................... 62
8.21 FAN Configuration Register II - Index 12h (Bank 0)..................................................... 62
8.22 Reserved Registers - Index 13h (Bank 0) .................................................................... 63
8.23 Reserved Registers - Index 14h (Bank 0) .................................................................... 63
8.24 Reserved Registers - Index 15h (Bank 0) .................................................................... 63
8.25 Reserved Registers - Index 16h (Bank 0) .................................................................... 63
8.26 Reserved Registers - Index 17h (Bank 0) .................................................................... 63
8.27 OVT# Configuration Register - Index 18h (Bank 0)...................................................... 63
8.28 Reserved Registers - Index 19h ~ 1Fh (Bank 0).......................................................... 64
8.29 Value RAM ⎯ Index 20h ~ 3Fh (Bank 0) ..................................................................... 64
Publication Release Date: May 25, 2007
-III-
Revision 1.0
W83627UHG
8.30 Configuration Register - Index 40h (Bank 0) ................................................................ 65
8.31 Interrupt Status Register 1 - Index 41h (Bank 0).......................................................... 66
8.32 Interrupt Status Register 2 - Index 42h (Bank 0).......................................................... 66
8.33 SMI# Mask Register 1 - Index 43h (Bank 0)................................................................. 67
8.34 SMI# Mask Register 2 - Index 44h (Bank 0)................................................................. 67
8.35 Reserved Register - Index 45h (Bank 0) .................................................................... 68
8.36 SMI# Mask Register 3 - Index 46h (Bank 0)................................................................. 68
8.37 Fan Divisor Register I - Index 47h (Bank 0) ................................................................. 68
8.38 Serial Bus Address Register - Index 48h (Bank 0)....................................................... 68
8.39 CPUFANOUT monitor Temperature source select register - Index 49h (Bank 0) ....... 69
8.40 SYSFANOUT monitor Temperature source select register - Index 4Ah (Bank 0) ....... 70
8.41 Fan Divisor Register II - Index 4Bh (Bank 0)................................................................ 70
8.42 SMI#/OVT# Control Register - Index 4Ch (Bank 0)...................................................... 71
8.43 FAN IN/OUT Control Register - Index 4Dh (Bank 0).................................................... 72
8.44 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (Bank 0) .................................. 72
8.45 Winbond Vendor ID Register - Index 4Fh (Bank 0)...................................................... 73
8.46 Reserved Register - Index 50h ~ 55h (Bank 0)............................................................ 73
8.47 BEEP Control Register 1 - Index 56h (Bank 0) ............................................................ 73
8.48 BEEP Control Register 2 - Index 57h (Bank 0) ............................................................ 74
8.49 Chip ID - Index 58h (Bank 0) ........................................................................................ 75
8.50 Diode Selection Register - Index 59h (Bank 0) ............................................................ 75
8.51 Reserved Register - Index 5Ah ~ 5Ch (Bank 0)........................................................... 75
8.52 VBAT Monitor Control Register - Index 5Dh (Bank 0).................................................. 75
8.53 Critical Temperature enable register - Index 5Eh (Bank 0).......................................... 76
8.54 Reserved Register - Index 5Fh (Bank 0)...................................................................... 77
8.55 Reserved Registers - Index 60h (Bank 0) .................................................................... 77
8.56 Reserved Registers - Index 61h (Bank 0) .................................................................... 77
8.57 Reserved Registers - Index 62h (Bank 0) .................................................................... 77
8.58 Reserved Registers - Index 63h (Bank 0) .................................................................... 77
8.59 Reserved Registers - Index 64h (Bank 0) .................................................................... 77
8.60 Reserved Registers - Index 65h (Bank 0) .................................................................... 77
8.61 Reserved Registers - Index 66h (Bank 0) .................................................................... 77
8.62 CPUFANOUT Maximum Output Value Register - Index 67h (Bank 0) ........................ 77
8.63 CPUFANOUT Output Step Value Register - Index 68h (Bank 0)................................. 78
8.64 Reserved Registers - Index 69h (Bank 0) .................................................................... 78
8.65 Reserved Registers - Index 6Ah (Bank 0).................................................................... 78
8.66 SYSFANOUT Critical Temperature register - Index 6Bh (Bank 0)............................... 78
8.67 CPUFANOUT Critical Temperature register - Index 6Ch (Bank 0) .............................. 78
8.68 Reserved Registers - Index 6Dh (Bank 0).................................................................... 79
8.69 Reserved Registers - Index 6Eh (Bank 0).................................................................... 79
8.70 CPUTIN/PECI Temperature (High Byte) Register - Index 50h (Bank 1)...................... 79
8.71 CPUTIN/PECI Temperature (Low Byte) Register - Index 51h (Bank 1)....................... 79
8.72 CPUTIN Configuration Register - Index 52h (Bank 1).................................................. 80
-IV-
W83627UHG
8.73 CPUTIN Hysteresis (High Byte) Register - Index 53h (Bank 1) ................................... 80
8.74 CPUTIN Hysteresis (Low Byte) Register - Index 54h (Bank 1).................................... 80
8.75 CPUTIN Over-temperature (High Byte) Register - Index 55h (Bank1)......................... 81
8.76 CPUTIN Over-temperature (Low Byte) Register - Index 56h (Bank 1) ........................ 81
8.77 SYSTIN/CPUTIN/PECI Temperature (High Byte) Register - Index 50h (Bank 2)........ 81
8.78 SYSTIN/CPUTIN/PECI Temperature (Low Byte) Register – Index 51h (Bank 2)........ 82
8.79 Reserved Registers – Index 52h (Bank 2).................................................................... 82
8.80 Reserved Registers – Index 53h (Bank 2).................................................................... 82
8.81 Reserved Registers – Index 54h (Bank 2).................................................................... 82
8.82 Reserved Registers – Index 55h (Bank 2).................................................................... 82
8.83 Reserved Registers – Index 56h (Bank 2).................................................................... 82
8.84 Interrupt Status Register 3 – Index 50h (Bank 4) ......................................................... 82
8.85 SMI# Mask Register 4 – Index 51h (Bank 4)................................................................ 83
8.86 Reserved Register - Index 52h (Bank 4) ...................................................................... 83
8.87 BEEP Control Register 3 - Index 53h (Bank 4) ............................................................ 83
8.88 SYSTIN Temperature Sensor Offset Register - Index 54h (Bank 4)............................ 84
8.89 CPUTIN Temperature Sensor Offset Register - Index 55h (Bank 4) ........................... 84
8.90 Reserved Registers - Index 56h (Bank 4) .................................................................... 84
8.91 Reserved Register - Index 57h-58h (Bank 4)............................................................... 84
8.92 Real Time Hardware Status Register I - Index 59h (Bank 4) ....................................... 84
8.93 Real Time Hardware Status Register II - Index 5Ah (Bank 4)...................................... 85
8.94 Real Time Hardware Status Register III - Index 5Bh (Bank 4)..................................... 86
8.95 Reserved Register - Index 5Ch - 5Fh (Bank 4) ............................................................ 87
8.96 Value RAM 2 ⎯ Index 50h-59h (Bank 5) ..................................................................... 87
8.97 Reserved Register - Index 50h - 57h (Bank 6)............................................................. 87
FLOPPY DISK CONTROLLER................................................................................................. 88
9.
9.1
FDC Functional Description.......................................................................................... 88
9.1.1 FIFO (Data) ....................................................................................................................88
Data Separator.............................................................................................................. 89
9.2.1 Write Precompensation ..................................................................................................89
9.2.2 Perpendicular Recording Mode......................................................................................89
9.2.3 FDC Core .......................................................................................................................90
9.2.4 FDC Commands.............................................................................................................90
Register Descriptions.................................................................................................... 98
9.3.1 Status Register A (SA Register) (Read base address + 0).............................................98
9.3.2 Status Register B (SB Register) (Read base address + 1)...........................................100
9.3.3 Digital Output Register (DO Register) (Write base address + 2) ..................................101
9.3.4 Tape Drive Register (TD Register) (Read base address + 3).......................................101
9.3.5 Main Status Register (MS Register) (Read base address + 4).....................................102
9.3.6 Data Rate Register (DR Register) (Write base address + 4)........................................103
9.3.7 FIFO Register (R/W base address + 5)........................................................................105
9.3.8 Digital Input Register (DI Register) (Read base address + 7).......................................107
9.2
9.3
Publication Release Date: May 25, 2007
-V-
Revision 1.0
W83627UHG
9.3.9 Configuration Control Register (CC Register) (Write base address + 7) ......................109
UART PORT ........................................................................................................................... 110
10.
10.1 Universal Asynchronous Receiver/Transmitter (UART A, B, C, D, E, F) ................... 110
10.2 Register Address ........................................................................................................ 110
10.2.1 UART Control Register (UCR) (Read/Write) ..............................................................110
10.2.2 UART Status Register (USR) (Read/Write)................................................................113
10.2.3 Handshake Control Register (HCR) (Read/Write) ......................................................114
10.2.4 Handshake Status Register (HSR) (Read/Write)........................................................114
10.2.5 This register is used to control the FIFO functions of the UART.................................115
10.2.6 Interrupt Status Register (ISR) (Read only)................................................................116
10.2.7 Interrupt Control Register (ICR) (Read/Write) ............................................................117
PARALLEL PORT................................................................................................................... 118
11.
11.1 Printer Interface Logic................................................................................................. 118
11.2 Enhanced Parallel Port (EPP) .................................................................................... 118
11.2.1 Data Port (Data Swapper) ..........................................................................................119
11.2.2 Printer Status Buffer ...................................................................................................119
11.2.3 Printer Control Latch and Printer Control Swapper.....................................................120
11.2.4 EPP Address Port.......................................................................................................121
11.2.5 EPP Data Port 0-3......................................................................................................121
11.2.6 EPP Pin Descriptions .................................................................................................122
11.2.7 EPP Operation ...........................................................................................................122
11.3 Extended Capabilities Parallel (ECP) Port ................................................................. 123
11.3.1 ECP Register and Bit Map..........................................................................................124
11.3.2 Data and ecpAFifo Port ..............................................................................................125
11.3.3 Device Status Register (DSR) ....................................................................................125
11.3.4 Device Control Register (DCR) ..................................................................................125
11.3.5 CFIFO (Parallel Port Data FIFO) Mode = 010 ............................................................126
11.3.6 ECPDFIFO (ECP Data FIFO) Mode = 011.................................................................126
11.3.7 TFIFO (Test FIFO Mode) Mode = 110........................................................................126
11.3.8 CNFGA (Configuration Register A) Mode = 111.........................................................126
11.3.9 CNFGB (Configuration Register B) Mode = 111.........................................................127
11.3.10 ECR (Extended Control Register) Mode = all...........................................................127
11.3.11 ECP Pin Descriptions ...............................................................................................129
11.3.12 ECP Operation .........................................................................................................130
11.3.13 DMA Transfers .........................................................................................................131
11.3.14 Programmed I/O (NON-DMA) Mode.........................................................................131
KEYBOARD CONTROLLER................................................................................................... 132
12.
12.1 Output Buffer............................................................................................................... 132
12.2 Input Buffer ................................................................................................................. 132
12.3 Status Register ........................................................................................................... 133
12.4 Commands.................................................................................................................. 134
12.5 Hardware GATEA20/Keyboard Reset Control Logic.................................................. 135
12.5.1 KB Control Register (Logic Device 5, CR-F0) ............................................................135
12.5.2 Port 92 Control Register (Default Value = 0x24) ........................................................137
-VI-
W83627UHG
13.
POWER MANAGEMENT EVENT........................................................................................... 138
13.1 Power Control Logic ................................................................................................... 138
13.1.1 PSON# Logic..............................................................................................................139
13.1.2 AC Power Failure Resume.........................................................................................140
13.2 Wake Up the System by Keyboard and Mouse.......................................................... 141
13.2.1 Waken up by Keyboard events...................................................................................141
13.2.2 Waken up by Mouse events .......................................................................................142
13.3 Resume Reset Logic .................................................................................................. 142
13.4 PWROK Generation ................................................................................................... 143
14.
SERIALIZED IRQ.................................................................................................................... 145
14.1 Start Frame................................................................................................................. 145
14.2 IRQ/Data Frame.......................................................................................................... 146
14.3 Stop Frame ................................................................................................................. 147
WATCHDOG TIMER............................................................................................................... 148
GENERAL PURPOSE I/O....................................................................................................... 149
16.1 GPIO Architecture....................................................................................................... 149
16.2 Access Channels........................................................................................................ 149
CONFIGURATION REGISTER............................................................................................... 151
17.1 Chip (Global) Control Register.................................................................................... 151
17.2 Logical Device 0 (FDC)............................................................................................... 157
17.3 Logical Device 1 (Parallel Port) .................................................................................. 161
17.4 Logical Device 2 (UART A)......................................................................................... 162
17.5 Logical Device 3 (UART B)......................................................................................... 163
17.6 Logical Device 5 (Keyboard Controller)...................................................................... 165
17.7 Logical Device 6 (UART C)......................................................................................... 167
17.8 Logical Device 7 (GPIO3, GPIO4).............................................................................. 168
17.9 Logical Device 8 (WDTO#, PLED, GPIO5, 6 & GPIO Base Address) ....................... 170
17.10 Logical Device 9 (GPIO1, GPIO2 and SUSLED)...................................................... 174
17.11 Logical Device A (ACPI)............................................................................................ 176
17.12 Logical Device B (Hardware Monitor) ....................................................................... 184
17.13 Logical Device C (PECI, SST)................................................................................... 185
17.14 Logical Device D (UART D)....................................................................................... 191
17.15 Logical Device E (UART E)....................................................................................... 192
17.16 Logical Device F (UART F) ....................................................................................... 193
SPECIFICATIONS .................................................................................................................. 194
15.
16.
17.
18.
18.1 Absolute Maximum Ratings........................................................................................ 194
18.2 DC CHARACTERISTICS............................................................................................ 194
18.3 AC CHARACTERISTICS............................................................................................ 199
18.3.1 Power On / Off Timing................................................................................................199
18.3.2 AC Power Failure Resume Timing .............................................................................200
18.3.3 Clock Input Timing......................................................................................................205
18.3.4 PECI and SST Timing ................................................................................................206
Publication Release Date: May 25, 2007
-VII-
Revision 1.0
W83627UHG
18.3.5 SMBus Timing............................................................................................................207
18.3.6 Floppy Disk Drive Timing............................................................................................207
18.3.7 UART/Parallel Port .....................................................................................................209
18.3.8 Parallel Port Mode Parameters ..................................................................................211
18.3.9 Parallel Port................................................................................................................212
18.3.10 KBC Timing Parameters...........................................................................................221
18.3.11 GPIO Timing Parameters .........................................................................................224
18.4 LRESET Timing .......................................................................................................... 225
TOP MARKING SPECIFICATION .......................................................................................... 226
PACKAGE SPECIFICATION.................................................................................................. 227
19.
20.
APPENDIX – ABBREVIATIONS ......................................................................................................... 228
-VIII-
W83627UHG
List of Figures -
Figure 3-1 W83627UHG Block Diagram........................................................................................... 5
Figure 4-1 W83627UHG Pin Layout ................................................................................................. 6
Figure 6-1 Structure of the Configuration Register ......................................................................... 21
Figure 6-2 Configuration Register................................................................................................... 23
Figure 7-1 LPC Bus’ Reads from / Writes to Internal Registers...................................................... 28
Figure 7-2 Serial Bus Write to Internal Address Register Followed by the Data Byte.................... 29
Figure 7-3 Serial Bus Read from Internal Address Register........................................................... 30
Figure 7-4 Analog Inputs and Application Circuit of the W83627UHG ........................................... 31
Figure 7-5 Monitoring Temperature from Thermistor...................................................................... 33
Figure 7-6 Monitoring Temperature from Thermal Diode (Voltage Mode)...................................... 34
Figure 7-7 Monitoring Temperature from Thermal Diode ............................................................... 35
Figure 7-8 PECI Illustration............................................................................................................. 39
Figure 7-9 FANOUT and Corresponding Temperature Sensors in SMART FANTMI ...................... 42
Figure 7-10 Mechanism of Thermal CruiseTM Mode (PWM Duty Cycle) ........................................ 43
Figure 7-11 Mechanism of Thermal CruiseTM Mode (DC Output Voltage) ..................................... 43
Figure 7-12 Mechanism of Fan Speed CruiseTM Mode................................................................... 44
Figure 7-13 FANOUT and Corresponding Temperature Sensor in SMART FANTM III ................... 45
Figure 7-14 Setting of SMART FANTM III......................................................................................... 46
Figure 7-15 SMART FANTM III Mechanism (Current Temp. > Target Temp. + Tol.)....................... 47
Figure 7-16 SMART FANTM III Mechanism (Current Temp. < Target Temp. – Tol.)....................... 48
Figure 7-17 SMI Mode of Voltage and Fan Inputs.......................................................................... 49
Figure 7-18 SMI Mode of SYSTIN I ................................................................................................ 50
Figure 7-19 SMI Mode of SYSTIN II ............................................................................................... 51
Figure 7-20 SMI Mode of CPUTIN.................................................................................................. 52
Figure 7-21 OVT# Modes of Temperature Inputs........................................................................... 53
Figure 7-22 Caseopen Mechanism................................................................................................. 54
Figure 12-1 Keyboard and Mouse Interface.................................................................................. 132
Figure 13-1 Power Control Mechanism......................................................................................... 139
Figure 13-2 Power Sequence from S5 to S0, then back to S5. .................................................... 139
Figure 13-3 Mechanism of Resume Reset Logic.......................................................................... 143
Figure 14-1 Start Frame Timing with Source Sampled A Low Pulse on IRQ1 ............................. 145
Figure 14-2 Stop Frame Timing with Host Using 17 SERIRQ Sampling Period........................... 147
Publication Release Date: May 25, 2007
-IX-
Revision 1.0
W83627UHG
List of Tables-
Table 6-1 Devices of I/O Base Address.......................................................................................... 22
Table 6-2 Chip (Global) Control Registers...................................................................................... 25
Table 7-1 Temperature Data Format .............................................................................................. 33
Table 7-2 SST Command Summary............................................................................................... 36
Table 7-3 Typical Temperature Values........................................................................................... 37
Table 7-4 Fan Divisor Definition...................................................................................................... 40
Table 7-5 Divisor, RPM, and Count Relation .................................................................................. 40
Table 7-6 Display Registers – at SMART FANTM I Mode................................................................ 44
Table 7-7 Relative Registers – at Thermal Cruise Mode................................................................ 45
Table 7-8 Relative Registers – at Speed Cruise Mode................................................................... 45
Table 7-9 Display Register – at SMART FANTMIII Mode ................................................................ 48
Table 7-10 Relative Register – at SMART FANTMIII Control Mode................................................. 49
Table 9-1 The Delays of the FIFO................................................................................................... 88
Table 9-2 FDC Registers................................................................................................................. 98
Table 10-1 Register Summary for UART ...................................................................................... 112
Table 11-1 Pin Descriptions for SPP, EPP, and ECP Modes....................................................... 118
Table 11-2 EPP Register Addresses ............................................................................................ 118
Table 11-3 Address and Bit Map for SPP and EPP Modes.......................................................... 119
Table 11-4 ECP Mode Description................................................................................................ 123
Table 11-5 ECP Register Addresses ............................................................................................ 124
Table 11-6 Bit Map of the ECP Registers ..................................................................................... 124
Table 12-1 Bit Map of Status Register .......................................................................................... 133
Table 12-2 KBC Command Sets................................................................................................... 134
Table 13-1 Bit Map of Logical Device A, CR[E4h], Bits [6:5] ........................................................ 140
Table 13-2 Definitions of Mouse Wake-Up Events ....................................................................... 142
Table 13-3 Timing and Voltage Parameters of RSMRST#........................................................... 143
Table 14-1 SERIRQ Sampling Periods......................................................................................... 146
Table 16-1 Relative Control Registers of GPIO 25, 26 and 27 that Support Wake-Up Function . 149
Table 16-2 GPIO Register Addresses........................................................................................... 150
-X-
W83627UHG
1. GENERAL DESCRIPTION
The W83627UHG is a member of Winbond's Super I/O product line. This family features the LPC (Low
Pin Count) interface. This interface is more economical than its ISA counterpart because it has
approximately forty pins fewer, yet still provides as great performance. In addition, the improvement
allows even more efficient operation of software, BIOS and device drivers.
In addition to providing an LPC interface for I/O, the W83627UHG monitors several critical parameters
in PC hardware, including power supply voltages, fan speeds, and temperatures. In terms of
temperature monitoring, the W83627UHG adopts the Current Mode (dual current source) approach.
The W83627UHG also supports the Smart Fan control system, including “SMART FANTM I and SMART
FANTM III, which makes the system more stable and user-friendly.
The W83627UHG supports four -- 360K, 720K, 1.2M, 1.44M, or 2.88M -- disk drives and data transfer
rates of 250 Kb/s, 300 Kb/s, 500 Kb/s, 1 Mb/s, and 2 Mb/s. The disk drive adapter supports the
functions of floppy disk drive controller (compatible with the industry standard 82077/ 765), data
separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive
interface control logic, and interrupt and DMA logic. Such a wide range of functions integrated into one
W83627UHG greatly reduces the number of required components to interface with floppy disk drives.
The W83627UHG provides six high-speed serial communication ports (UARTs), one of which provides
IR functions IrDA 1.0 (SIR for 1.152K bps). Each UART includes a 16-byte send/receive FIFO, a
programmable baud rate generator, complete modem-control capability, and a processor interrupt
system. All of the UARTs support legacy speeds up to 115.2K bps as well as higher baud rates of
230K, 460K, or 921K bps to support higher speed modems.
The W83627UHG supports the PC-compatible printer port (SPP), the bi-directional printer port (BPP),
the enhanced parallel port (EPP) and the extended capabilities port (ECP).
The W83627UHG provides flexible I/O control functions through a set of 45 general purpose I/O
(GPIO) ports. These GPIO ports may serve as simple I/O ports or may be individually configured to
provide alternative functions.
The W83627UHG supports the SST (Simple Serial Transport) interface and Intel® PECI (Platform
Environment Control Interface).
The W83627UHG fully complies with the Microsoft© PC98 and PC99 Hardware Design Guide and
meets the requirements of ACPI.
The configuration registers inside the W83627UHG support mode selection, function enable and
disable, and power-down selection. Furthermore, the configurable PnP features are compatible with
the plug-and-play feature in Windows 95/98/2000/XPTM, making the allocation of the system resources
more efficient than ever.
One special characteristic of the Super I/O product line is the separation of the power supply in normal
operation from that in standby operation. Please pay attention to the layout of these two power
supplies to avoid short circuits. Otherwise, the feature will not function.
Publication Release Date: May 25, 2007
-1-
Revision 1.0
W83627UHG
2. FEATURES
General
y
y
y
y
y
Meet LPC Spec. 1.01
Support LDRQ# (LPC DMA), SERIRQ (Serialized IRQ)
Integrated hardware monitor functions
Compliant with Microsoft PC2000/PC2001 Hardware Design Guide
Support DPM (Device Power Management), ACPI (Advanced Configuration and Power
Interface)
y
y
Programmable configuration settings
Single 24- or 48-MHz clock input
FDC
y
y
y
y
y
y
y
y
Variable write pre-compensation with track-selection capability
Support vertical recording format
DMA-enable logic
16-byte data FIFOs
Support floppy disk drives and tape drives
Detect all overrun and underrun conditions
Built-in address mark detection circuit to simplify the read electronics
FDD anti-virus functions with software write protect and FDD-write enable signal (write data
signal forced to be inactive)
y
y
y
y
y
Support 3.5-inch or 5.25-inch floppy disk drives
Compatible with industry standard 82077
360K / 720K / 1.2M / 1.44M / 2.88M formats
250K, 300K, 500K, 1M, 2M bps data transfer rate
Support 3-mode FDD and its Windows driver
UART
y
y
Six high-speed, 16550-compatible UARTs with 16-byte send / receive FIFOs
Fully programmable serial-interface characteristics:
--- 5, 6, 7 or 8-bit characters
--- Even, odd or no parity bit generation/detection
--- 1, 1.5 or 2 stop-bit generation
y
Internal diagnostic capabilities:
--- Loop-back controls for communications link fault isolation
--- Break, parity, overrun, framing error simulation
y
y
Programmable baud rate generator allows division of clock source by any value from 1 to
16
(2 -1)
Maximum baud rate for clock source 14.769 MHz is up to 921K bps. The baud rate at 24 MHz
is 1.5M bps.
-2-
W83627UHG
Parallel Port
y
y
y
y
y
Compatible with IBM parallel port
Support PS/2-compatible bi-directional parallel port
Support Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification
Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification
Enhanced printer port back-drive current protection
Keyboard Controller
•
•
•
•
•
•
•
•
•
•
•
8042-based keyboard controller
Support Phoenix MultiKey/42TM firmware
Asynchronous Access to two data registers and one status register
Software-compatible with 8042
Support PS/2 mouse
Support port 92
Support both interrupt and polling modes
Fast Gate A20 and Hardware Keyboard Reset
8-bit timer / counter
Support binary and BCD arithmetic
6, 8, 12, or 16 MHz operating frequency
Hardware Monitor Functions
•
Smart Fan control system, supporting the functions of SMART FANTM I - “Thermal CruiseTM”
and “Fan Speed CruiseTM” modes and SMART FANTM III functions
•
Programmable threshold temperature to speed fan fully while current temperature exceeds
this temperature during Thermal CruiseTM mode
•
•
•
•
•
•
•
•
•
•
Two thermal inputs from optionally-remote thermistors or thermal diode output
Support Current Mode (dual current source) temperature sensing method
Eight voltage inputs (CPUVCORE, VIN[0..2] and 5VCC, AVCC , 5VSB, VBAT)
Two fan-speed monitoring inputs
Two fan-speed controls
Dual mode for fan control (PWM and DC)
Built-in case open detection circuit
Programmable hysteresis and setting points for all monitored items
Over-temperature indicator output
Issue SMI#, OVT# to activate system protection
Publication Release Date: May 25, 2007
-3-
Revision 1.0
W83627UHG
•
•
Winbond Hardware DoctorTM Support
Provide I2C interface to read / write registers
Infrared
•
•
Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps
General Purpose I/O Ports
•
•
45 programmable general purpose I/O ports
GP25, GP26 and GP27 can distinguish whether the input pins have any transitions by reading
the registers and all of the 3 GPIOs also can assert PSOUT# or PME# to wake up the system
if each them has any transition.
OnNow Functions
y
y
y
Keyboard Wake-Up by programmable keys
Mouse Wake-Up by programmable buttons
On Now Wake-Up from all of the ACPI sleeping states (S1-S5)
Simple Serial Transport™ Interface
y
y
SST temperature and voltage Combination Sensor command support
Support SST 0.9 Specification
PECI Interface
y
y
y
PECI Host
Support PECI 1.0 Specification
Support 4 CPU addresses and 2 domains per CPU address
Package
y
y
128-pin QFP
Pb-free / RoHS
-4-
W83627UHG
3. BLOCK DIAGRAM
LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ
LPC
Interface
Floppy drive
interface signals
General
-purpose
GPIO
PECI
FDC
I/O pins
PECI
UART
interface
Serial port A, B,C,D,E,F
interface signals
A, B,C, D, E, F
SST
interface
SST
HM
IRRX
IRTX
IR
Hardware monitor
channel and Vref
Printer port
interface signals
PRT
Keyboard/Mouse
data and clock
KBC
ACPI
Figure 3-1 W83627UHG Block Diagram
Publication Release Date: May 25, 2007
Revision 1.0
-5-
W83627UHG
4. PIN LAYOUT
64
SUSLED
KDAT
KCLK
5VSB
GP27
KBRST
GA20M
RIA#
DCDA#
VSS
CPUTIN
SYSTIN
AGND
GP22
GP21/BEEP
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
VBAT
5VCC
Vtt
VSB
VSB
AVCC
GP20/PLED
CTSC#/GP37
DSRC#/GP36
RTSC#/GP35
DTRC#/GP34
SINC/GP33
SOUTC/GP32
DCDC#/GP31
RIC#/GP30
SOUTA(PENKBC)
SINA
DTRA# (PFDCUART)
RTSA# (HEFRAS)
DSRA#
CTSA#
5VCC
STB#
AFD#
ERR#
INIT#
SLIN#
PD0
PD1
PD2
W83627UHG
CTSD#/GP47
DSRD#/GP46
(FAN_SET) RTSD#/GP45
DTRD#/GP44
SIND/GP43
(GPI_MUL) SOUTD/GP42
DCDD#/GP41
RID#/GP40
CTSE#/GP57
DSRE#/GP56
RTSE#/GP55
DTRE#/GP54
5VCC
PD3
Figure 4-1 W83627UHG Pin Layout
-6-
W83627UHG
5. PIN DESCRIPTION
Note: Please refer to Section 18.2 DC CHARACTERISTICS for details.
AOUT
AIN
- Analog output pin
- Analog input pin
I/O12tp3
- 3.3-V, TTL-level, bi-directional pin with 12mA source-sink capability
I/O12ts
- TTL-level Schmitt-trigger bi-directional pin with 12mA source-sink capability
- TTL-level, bi-directional pin and open-drain output with 12mA sink capability
I/OD12t
I/OD16ts
I/OD12ts
I/OD12tsu
- TTL-level Schmitt-trigger bi-directional pin and open-drain output with 16mA sink capability
- TTL-level Schmitt-trigger bi-directional pin and open-drain output with 12mA sink capability
- TTL-level, bi-directional, Schmitt-trigger pin with internal pull-up resistor
. Open-drain output with 12-mA sink capability.
I/Ov3
I/Ov4
INts
- Bi-direction pin with source capability of 6 mA and sink capability of 1 mA
- Bi-direction pin with source capability of 6 mA and sink capability of 1 mA
- TTL-level Schmitt-trigger input pin
INtsu
INtsp3
INt
- TTL-level Schmitt-trigger input pin with internal pull-up resistor
- 3.3-V, TTL-level Schmitt-trigger input pin
- TTL-level input pin
INtu
- TTL-level input pin with internal pull-up resistor
- CMOS-level input pin with internal pull-down resistor
- 3.3-V, output pin with 12mA source-sink capability
- Open-drain output pin with 12mA sink capability
- Open-drain output pin with 24mA sink capability
- Output pin with 8mA source-sink capability
- Output pin with 12mA source-sink capability
- Output pin with 24mA source-sink capability
INcd
O12p3
OD12
OD24
O8
O12
O24
Publication Release Date: May 25, 2007
Revision 1.0
-7-
W83627UHG
5.1 LPC Interface
SYMBOL
PIN
I/O
DESCRIPTION
System clock input, either 24MHz or 48MHz. The actual
frequency must be specified in register. The default value is
48MHz.
INt
CLKIN
19
OD12
INtsp3
PME#
PCICLK
LDRQ#
SERIRQ
86
21
22
23
Generated PME event.
PCI-clock 33-MHz input.
Encoded DMA Request signal.
Serialized IRQ input / output.
O12p3
I/O12tp3
24-
27
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
LAD[3:0]
LFRAME#
LRESET#
I/O12tp3
INtsp3
Indicates the start of a new cycle or the termination of a broken
cycle.
29
30
Reset signal. It can be connected to the PCIRST# signal on the
host.
INtsp3
5.2 FDC Interface
SYMBOL
PIN
I/O
DESCRIPTION
OD24
DRVDEN0
Drive Density Select bit 0.
Clear To Send. It is the modem control input. The function of
these pins can be tested by reading bit 4 of the handshake
status register.
5
INt
CTSF#
This Schmitt-trigger input from the disk drive is active-low when
the head is positioned over the beginning of a track marked by
an index hole. This input pin needs to connect a pulled-up 1-
KΩ resistor to 5V for Floppy Drive compatibility.
INtsu
INDEX#
6
I/OD12ts
OD24
INt
GP64
MOA#
DSRF#
General purpose I/O port 6 bit 4.
Motor A On. When set to 0, this pin enables disk drive A. This is
an open-drain output.
7
8
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
Drive Select A. When set to 0, this pin enables disk drive A. This
is an open-drain output.
OD24
O24
DSA#
UART F Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
RTSF#
-8-
W83627UHG
FDC Interface, continued
SYMBOL
PIN
I/O
DESCRIPTION
Direction of the head step motor. An open-drain output.
Logic 1 = outward motion
OD24
DIR#
9
Logic 0 = inward motion
UART F Data Terminal Ready. An active low signal informs the
modem or data set that the controller is ready to communicate.
O24
OD24
INt
DTRF#
STEP#
SINF
Step output pulses. This active-low open-drain output produces
a pulse to move the head to another track.
10
Serial Input. This pin is used to receive serial data through the
communication link.
Write data. This logic-low open-drain writes pre-compensation
serial data to the selected FDD. An open-drain output.
OD24
WD#
11
13
UART F Serial Output. This pin is used to transmit serial data out
to the communication link.
O24
OD24
INt
SOUTF
WE#
Write enable. An open-drain output.
Data Carrier Detect. An active low signal indicates the modem
or data set has detected a data carrier.
DCDF#
Track 0. This Schmitt-trigger input from the disk drive is active-
low when the head is positioned over the outermost track. This
input pin needs to connect a pulled-up 1-KΩ resistor to 5V for
Floppy Drive compatibility.
INtsu
I/OD12ts
INtsu
TRAK0#
GP63
WP#
14
General purpose I/O port 6 bit 3.
Write Protected. This active-low Schmitt input from the disk drive
indicates that the diskette is write-protected. This input pin needs
to connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive
compatibility.
15
16
I/OD12ts
GP62
General purpose I/O port 6 bit 2.
The read-data input signal from the FDD. This input pin needs to
connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive
compatibility.
INtsu
RDATA#
GP61
I/OD12ts
General purpose I/O port 6 bit 1.
Publication Release Date: May 25, 2007
-9-
Revision 1.0
W83627UHG
FDC Interface, continued
SYMBOL
PIN
I/O
DESCRIPTION
Head Select. This open-drain output determines which disk
drive head is active.
OD24
HEAD#
Logic 1 = side 0
Logic 0 = side 1
17
Ring Indicator. An active low signal indicates that a ring signal is
being received from the modem or data set.
INt
RIF#
Diskette Change. This signal is active-low at power-on and
whenever the diskette is removed. This input pin needs to
connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive
compatibility.
INtsu
DSKCHG#
GP60
18
I/OD12ts
General purpose I/O port 6 bit 0.
5.3 Multi-Mode Parallel Port
SYMBOL
PIN
I/O
DESCRIPTION
PRINTER MODE:
An active-high input on this pin indicates that the printer is selected.
See the description of the parallel port for the definition of this pin in
ECP and EPP modes.
SLCT
31
INts
PRINTER MODE:
An active-high input on this pin indicates that the printer has detected
the end of the paper. See the description of the parallel port for the
definition of this pin in ECP and EPP modes.
PE
32
33
34
INts
INts
INts
PRINTER MODE:
An active-high input indicates that the printer is not ready to receive
data. See the description of the parallel port for the definition of this
pin in ECP and EPP modes.
BUSY
ACK#
PRINTER MODE: ACK#
An active-low input on this pin indicates that the printer has received
data and is ready to accept more data. See the description of the
parallel port for the definition of this pin in ECP and EPP modes.
PRINTER MODE: ERR#
An active-low input on this pin indicates that the printer has
encountered an error. See the description of the parallel port for the
definition of this pin in ECP and EPP modes.
ERR#
SLIN#
45
43
INts
PRINTER MODE: SLIN#
OD12
Output line for detection of printer selection. See the description of
the parallel port for the definition of this pin in ECP and EPP modes.
-10-
W83627UHG
Multi-Mode Parallel Port, continued
SYMBOL
PIN
I/O
DESCRIPTION
PRINTER MODE: INIT#
OD12
INIT#
44
Output line for the printer initialization. See the description of the
parallel port for the definition of this pin in ECP and EPP modes.
PRINTER MODE: AFD#
An active-low output from this pin causes the printer to auto feed a
line after a line is printed. See the description of the parallel port for
the definition of this pin in ECP and EPP modes.
OD12
OD12
AFD#
STB#
46
47
PRINTER MODE: STB#
An active-low output is used to latch the parallel data into the printer.
See the description of the parallel port for the definition of this pin in
ECP and EPP modes.
PRINTER MODE: PD0
I/O12ts
I/O12ts
I/O12ts
I/O12ts
I/O12ts
I/O12ts
I/O12ts
I/O12ts
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
42
41
40
39
38
37
36
35
Parallel port data bus bit 0. See the description of the parallel port for
the definition of this pin in ECP and EPP modes.
PRINTER MODE: PD1
Parallel port data bus bit 1. See the description of the parallel port for
the definition of this pin in ECP and EPP modes.
PRINTER MODE: PD2
Parallel port data bus bit 2. See the description of the parallel port for
the definition of this pin in ECP and EPP modes.
PRINTER MODE: PD3
Parallel port data bus bit 3. See the description of the parallel port for
the definition of this pin in ECP and EPP modes.
PRINTER MODE: PD4
Parallel port data bus bit 4. See the description of the parallel port for
the definition of this pin in ECP and EPP modes.
PRINTER MODE: PD5
Parallel port data bus bit 5. See the description of the parallel port
for the definition of this pin in ECP and EPP modes.
PRINTER MODE: PD6
Parallel port data bus bit 6. See the description of the parallel port for
the definition of this pin in ECP and EPP modes.
PRINTER MODE: PD7
Parallel port data bus bit 7. See the description of the parallel port for
the definition of this pin in ECP and EPP modes.
Publication Release Date: May 25, 2007
-11-
Revision 1.0
W83627UHG
5.4 Serial Port & Infrared Port Interface
SYMBOL
PIN
I/O
DESCRIPTION
Clear To Send. This is the modem-control input. The function of
these pins can be tested by reading bit 4 of the handshake status
register.
INt
CTSA#
49
Clear To Send. This is the modem-control input. The function of
these pins can be tested by reading bit 4 of the handshake status
register.
INt
I/OD12t
INt
CTSB#
GP17
78
General-purpose I/O port 1 bit 7.
Clear To Send. This is the modem-control input. The function of
these pins can be tested by reading bit 4 of the handshake status
register.
CTSC#
GP37
109
117
125
I/OD12t
INt
General-purpose I/O port 3 bit 7.
Clear To Send. This is the modem-control input. The function of
these pins can be tested by reading bit 4 of the handshake status
register.
CTSD#
GP47
I/OD12t
INt
General-purpose I/O port 4 bit 7.
Clear To Send. This is the modem-control input. The function of
these pins can be tested by reading bit 4 of the handshake status
register.
CTSE#
GP57
I/OD12t
INt
General-purpose I/O port 5 bit 7.
Clear To Send. This is the modem-control input. The function of
these pins can be tested by reading bit 4 of the handshake status
register.
CTSF#
DRVDEN0
DSRA#
5
OD24
INt
Drive Density Select bit 0.
Data Set Ready. An active-low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
50
79
Data Set Ready. An active-low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
INt
I/OD12t
INt
DSRB#
GP16
General-purpose I/O port 1 bit 6.
Data Set Ready. An active-low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
DSRC#
GP36
110
118
I/OD12t
INt
General-purpose I/O port 3 bit 6.
Data Set Ready. An active-low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
DSRD#
GP46
I/OD12t
General-purpose I/O port 4 bit 6.
-12-
W83627UHG
Serial Port & Infrared Port Interface, continued
SYMBOL
DSRE#
GP56
PIN
I/O
DESCRIPTION
Data Set Ready. An active-low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
IN
t
126
I/OD12t
INt
General-purpose I/O port 5 bit 6.
Data Set Ready. An active-low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
DSRF#
7
Motor A On. When set to 0, this pin enables disk drive 0. This is
an open drain output.
OD24
O8
MOA#
UART A Request To Send. An active-low signal informs the
modem or data set that the controller is ready to send data.
RTSA#
During power-on reset, this pin is pulled down internally and is
defined as HEFRAS, which provides the power-on value for
CR26 bit 6 (HEFRAS). The PCB layout should reserve space for
a 1-kΩ resistor to pull down this pin so as to ensure the selection
of I/O port’s configuration address to 2EH, and a 1-kΩ resistor is
recommended to pull it up if 4EH is selected as I/O port′s
configuration address.
51
HEFRAS
INcd
UART B Request To Send. An active-low signal informs the
modem or data set that the controller is ready to send data.
O8
I/OD8
O8
RTSB#
GP15
80
General-purpose I/O port 1 bit 5.
UART C Request To Send. An active-low signal informs the
modem or data set that the controller is ready to send data.
RTSC#
GP35
111
I/OD8
O8
General-purpose I/O port 3 bit 5.
UART D Request To Send. An active-low signal informs the
modem or data set that the controller is ready to send data.
RTSD#
Determines the initial FAN speed. Power-on configuration for 2
fan speeds, 50% or 100%. During power-on reset, this pin needs
a pulled-up or a pull-down resistor to decide whether the fan
speed is 50% or 100%.
119
INcd
FAN_SET
I/OD8
O12
GP45
RTSE#
GP55
General-purpose I/O port 4 bit 5.
UART E Request To Send. An active-low signal informs the
modem or data set that the controller is ready to send data.
127
8
I/OD12t
O24
General-purpose I/O port 5 bit 5.
UART F Request To Send. An active-low signal informs the
modem or data set that the controller is ready to send data.
RTSF
Drive Select A. When set to 0, this pin enables disk drive A. This
is an open drain output.
OD24
DSA#
Publication Release Date: May 25, 2007
-13-
Revision 1.0
W83627UHG
Serial Port & Infrared Port Interface, continued
SYMBOL
PIN
I/O
DESCRIPTION
UART A Data Terminal Ready. An active-low signal informs the
modem or data set that the controller is ready to communicate.
O8
DTRA#
During power-on reset, this pin is pulled down internally and is
defined as FDC enable, which provides the power-on value for
CR24 bit 1. A 1 kΩ is reserved to pull down and a 1 kΩ resistor
is recommended if intends to pull-up to enable UART F.
52
PFDCUART
INcd
UART B Data Terminal Ready. An active-low signal informs the
modem or data set that the controller is ready to communicate.
O8
I/OD12t
O8
DTRB#
GP14
81
General-purpose I/O port 1 bit 4.
UART C Data Terminal Ready. An active-low signal informs the
modem or data set that the controller is ready to communicate.
DTRC#
GP34
112
120
128
I/OD12t
O8
General-purpose I/O port 3 bit 4.
UART D Data Terminal Ready. An active-low signal informs the
modem or data set that the controller is ready to communicate.
DTRD#
GP44
I/OD8t
O8
General-purpose I/O port 4 bit 4.
UART E Data Terminal Ready. An active-low signal informs the
modem or data set that the controller is ready to communicate.
DTRE#
GP54
I/OD12t
O24
General-purpose I/O port 5 bit 4.
UART F Data Terminal Ready. An active-low signal informs the
modem or data set that the controller is ready to communicate.
DTRF#
9
Direction of the head step motor. An open drain output.
Logic 1 = outward motion
OD24
INt
DIR#
Logic 0 = inward motion
Serial Input. This pin is used to receive serial data through the
communication link.
SINA
SINB
53
82
Serial Input. This pin is used to receive serial data through the
communication link.
INt
IRRX
GP13
IR Receiver input.
I/OD12t
INt
General-purpose I/O port 1 bit 3.
Serial Input. This pin is used to receive serial data through the
communication link.
SINC
GP33
SIND
GP43
113
121
I/OD12t
INt
General-purpose I/O port 3 bit 3.
Serial Input. This pin is used to receive serial data through the
communication link.
I/OD12t
General-purpose I/O port 4 bit 3.
-14-
W83627UHG
Serial Port & Infrared Port Interface, continued
SYMBOL
SINE
PIN
I/O
DESCRIPTION
Serial Input. This pin is used to receive serial data through the
communication link.
INt
1
I/OD12t
INt
GP53
General-purpose I/O port 5 bit 3.
Serial Input. This pin is used to receive serial data through the
communication link.
SINF
10
54
Step output pulses. This active low open drain output produces a
pulse to move the head to another track.
OD24
O8
STEP#
SOUTA
UART A Serial Output. This pin is used to transmit serial data out
to the communication link.
During power on reset, this pin is pulled down internally and is
defined as PENKBC, and the power-on values are shown at
CR24 bit 2. The PCB layout should reserve space for a 1-kΩ
resistor to pull down this pin to ensure the disabling of KBC, and
a 1-kΩ resistor is recommended to pull the pin up If wish to
enable KBC.
PENKBC
SOUTB
INcd
UART B Serial Output. This pin is used to transmit serial data out
to the communication link.
O8
83
IRTX
IR Transmitter output.
I/OD8
O8
GP12
General-purpose I/O port 1 bit 2.
UART C Serial Output. This pin is used to transmit serial data out
to the communication link.
SOUTC
GP32
114
I/OD8
O8
General-purpose I/O port 3 bit 2.
UART D Serial Output. This pin is used to transmit serial data out
to the communication link.
SOUTD
Determines PIN 107 and 108 multi-function select. During power-
on reset, this pin is pulled down internally and is defined as
BEEP function and power LED enable. A 1 kΩ is reserved to pull
down and a 1 kΩ resistor is recommended if intending to pull up
to enable GPIO output.
122
GPI_MUL
INcd
I/OD8
O8
GP42
SOUTE
GP52
General-purpose I/O port 4 bit 2.
UART E Serial Output. This pin is used to transmit serial data out
to the communication link.
2
I/OD8
O24
General-purpose I/O port 5 bit 2.
UART F Serial Output. This pin is used to transmit serial data out
to the communication link.
SOUTF
11
Write data. This logic low open drain writes pre-compensation
serial data to the selected FDD. An open drain output.
OD24
WD#
Publication Release Date: May 25, 2007
-15-
Revision 1.0
W83627UHG
Serial Port & Infrared Port Interface, continued
SYMBOL
PIN
I/O
DESCRIPTION
Data Carrier Detect. An active-low signal indicates the modem or
data set has detected a data carrier.
INt
DCDA#
56
Data Carrier Detect. An active-low signal indicates the modem or
data set has detected a data carrier.
INt
I/OD12t
INt
DCDB#
GP11
84
General-purpose I/O port 1 bit 1.
Data Carrier Detect. An active-low signal indicates the modem or
data set has detected a data carrier.
DCDC#
GP31
115
I/OD12t
INt
General-purpose I/O port 3 bit 1.
Data Carrier Detect. An active-low signal indicates the modem or
data set has detected a data carrier.
DCDD#
GP41
123
3
I/OD12t
General-purpose I/O port 4 bit 1.
Data Carrier Detect. An active-low signal indicates the modem or
data set has detected a data carrier.
INt
I/OD12t
INt
DCDE#
GP51
DCDF#
WE#
General-purpose I/O port 5 bit 1.
Data Carrier Detect. An active-low signal indicates the modem or
data set has detected a data carrier.
13
57
85
OD24
INt
Write enable. An open drain output.
Ring Indicator. An active-low signal indicates that a ring signal is
being received from the modem or data set.
RIA#
Ring Indicator. An active-low signal indicates that a ring signal is
being received from the modem or data set.
INt
I/OD12t
INt
RIB#
GP10
RIC#
GP30
RID#
GP40
RIE#
GP50
RIF#
General-purpose I/O port 1 bit 0.
Ring Indicator. An active-low signal indicates that a ring signal is
being received from the modem or data set.
116
124
4
I/OD12t
INt
General-purpose I/O port 3 bit 0.
Ring Indicator. An active-low signal indicates that a ring signal is
being received from the modem or data set.
I/OD12t
INt
General-purpose I/O port 4 bit 0.
Ring Indicator. An active-low signal indicates that a ring signal is
being received from the modem or data set.
I/OD12t
INt
General-purpose I/O port 5 bit 0.
Ring Indicator. An active-low signal indicates that a ring signal is
being received from the modem or data set.
Head select. This open drain output determines which disk drive
17
head is active.
Logic 1 = side 0
Logic 0 = side 1
OD24
HEAD#
-16-
W83627UHG
5.5 KBC Interface
SYMBOL
GA20M
KBRST
KCLK
PIN
58
I/O
O12
DESCRIPTION
Gate A20 output. This pin is high after system reset. (KBC P21)
Keyboard reset. This pin is high after system reset. (KBC P20)
Keyboard Clock.
59
O12
I/OD16ts
62
I/OD16ts
I/OD16ts
I/OD16ts
Keyboard Data.
KDAT
MCLK
MDAT
63
65
66
PS2 Mouse Clock.
PS2 Mouse Data.
5.6 Hardware Monitor Interface
SYMBOL
BEEP
PIN
I/O
DESCRIPTION
Beep function for hardware monitor. This pin is low after
system reset.
OD12
107
I/OD12t General-purpose I/O port 2 bit 1.
GP21
CASE OPEN Detection. An active-low input from an external
device when the case is open. This signal can be latched if pin
VBAT is connected to the battery, even if the W83627UHG is
turned off.
INt
CASEOPEN#
76
Pull up a 2-MΩ resistor to VBAT is recommended if useless.
Analog Inputs for voltage measurement (Range: 0 to 2.048 V)
Analog Inputs for voltage measurement (Range: 0 to 2.048 V).
Analog Inputs for voltage measurement (Range: 0 to 2.048 V)
Analog Inputs for voltage measurement (Range: 0 to 2.048 V)
Reference Voltage (2.048 V)
VIN2
VIN1
98
99
AIN
AIN
VIN0
100
101
102
AIN
CPUVCORE
VREF
AIN
AOUT
Temperature sensor 2 input. It is used for CPU temperature
sensing.
CPUTIN
SYSTIN
103
104
AIN
AIN
Temperature sensor 1 input. It is used for system temperature
sensing.
Over temperature Shutdown Output. This pin indicates the
temperature is over the temperature limit. (Default after
LRESET#)
OVT#
SMI#
95
OD12
System Management Interrupt channel output.
CPUFANIN
SYSFANIN
91
93
I/O12ts
0 to +5 V amplitude fan tachometer input.
Publication Release Date: May 25, 2007
-17-
Revision 1.0
W83627UHG
Hardware Monitor Interface, continued
SYMBOL
PIN
I/O
DESCRIPTION
DC/PWM fan output control.
O12
CPUFANOUT
SYSFANOUT
90
92
OD12
AOUT
CPUFANOUT and SYSFANOUT are default PWM mode.
OD12
PLED
GP20
Power LED output. This pin is tri-stated as default.
General-purpose I/O port 2 bit 0.
108
I/OD12t
5.7 PECI Interface
SYMBOL
PIN
I/O
DESCRIPTION
PECI
88
I/OV3
INTEL® CPU PECI interface. Connect to CPU.
Vtt
89
Power
INTEL® CPU Vtt Power.
5.8 SST Interface
SYMBOL
PIN
87
I/O
DESCRIPTION
SST
I/OV4
Simple Serial Transport (SST) Interface.
5.9 Advanced Configuration and Power Interface
SYMBOL
PIN
I/O
DESCRIPTION
PSIN#
68
INtu
Panel Switch Input. This pin is active-low.
Panel Switch Output. This signal is used to wake-up the
system from S3/S5 state.
OD12
OD12
PSOUT#
67
RSMRST#
SUSB#
PSON#
PWROK
SCL
75
73
72
71
Resume reset signal output.
INt
System S3 state input.
OD12
Power Supply on-off Output.
OD12
This pin generates the PWROK signal while 5VCC comes in.
Serial Bus clock.
INts
70
69
I/OD12ts
GP25
General-purpose I/O port 2 bit 5.
Serial bus bi-directional Data.
General-purpose I/O port 2 bit 6.
I/OD12t
I/OD12t
SDA
GP26
-18-
W83627UHG
5.10 General Purpose I/O Port
5.10.1
GPIO Power Source
SYMBOL
GPIO port 1
POWER SOURCE
5VSB
5VSB
5VCC
5VCC
5VCC
5VCC
GPIO port 2
GPIO port 3
GPIO port 4
GPIO port 5
GPIO port 6 (Bit 0-4)
5.10.2
GPIO-1 Interface
See 5.4 Serial Port & Infrared Port Interface
5.10.3
SYMBOL
GP20
GPIO-2 Interface
PIN
I/O
DESCRIPTION
General-purpose I/O port 2 bit 0.
I/OD12t
108
OD12
PLED
GP21
Power LED output. This pin is tri-stated as default..
General-purpose I/O port 2 bit 1.
I/OD12t
107
Beep function for hardware monitor. This pin is low after
system reset.
OD12
BEEP
I/OD12t
I/OD12t
I/OD12t
I/OD12ts
General-purpose I/O port 2 bit 2.
GP22
GP23
GP24
GP25
SCL
106
96
General-purpose I/O port 2 bit 3.
General-purpose I/O port 2 bit 4.
General-purpose I/O port 2 bit 5.
94
70
INts
Serial Bus clock.
I/OD12t
General-purpose I/O port 2 bit 6.
GP26
SDA
69
58
I/OD12t
I/OD12t
Serial bus bi-directional data.
General-purpose I/O port 2 bit 7.
GP27
5.10.4
GPIO-3 Interface
See 5.4 Serial Port & Infrared Port Interface
5.10.5
GPIO-4 Interface
See 5.4 Serial Port & Infrared Port Interface
Publication Release Date: May 25, 2007
Revision 1.0
-19-
W83627UHG
5.10.6
GPIO-5 Interface
See 5.4 Serial Port & Infrared Port Interface
5.10.7
GPIO-6 Interface
See 5.2 FDC Interface
5.10.8
WDTO# and SUSLED Pins
SYMBOL
PIN
77
I/O
DESCRIPTION
Watchdog timer output signal.
OD12
WDTO#
OD12
SUSLED
64
Suspend-LED output signal. This pin is low as default.
5.11 POWER PINS
SYMBOL
PIN
DESCRIPTION
5VSB
61
+5 V stand-by power supply for the digital circuit.
VBAT
74
+3 V on-board battery for the digital circuit.
5VCC
3VCC
AVCC
12,48
28
+5 V power supply for the digital circuit.
+3.3V power supply for driving 3V on the host interface.
Analog +5 V power input. Internally supply to all analog circuits.
97
Analog ground. The ground reference for all analog input.
Internally connected to all analog circuits.
AGND
105
VSS
Vtt
20,55
89
Ground.
INTEL® CPU Vtt power.
-20-
W83627UHG
6. CONFIGURATION REGISTER ACCESS PROTOCOL
The W83627UHG uses Super I/O protocol to access configuration registers to set up different types of
configurations. The W83627UHG has totally fifteen Logical Devices (from Logical Device 0 to Logical
Device F with the exception of Logical Device 4 for backward compatibility) corresponding to fifteen
individual functions: FDC (Logical Device 0), Parallel Port (Logical Device 1), UARTA (Logical Device
2), UARTB (Logical Device 3), Keyboard Controller (Logical Device 5), UARTC (Logical Device 6),
GPIO3, 4 (Logical Device 7), WDTO# & PLED and GPIO5, 6 (Logical Device 8), GPIO1, 2 and
SUSLED (Logical Device 9), ACPI (Logical Device A), Hardware Monitor (Logical Device B), PECI &
SST (Logical Device C), UARTD (Logical Device D), UARTE(Logical Device E), and UARTF (Logical
Device F). Each Logical Device has its own configuration registers (above CR30). The host can
access those registers by writing an appropriate Logical Device Number into the Logical Device select
register at CR7.
Logical Device No.
Logical Device
Control
Logical Device
One Per
Configuration
Logical Device
#0
#1
#2
#F
Figure 6-1 Structure of the Configuration Register
Publication Release Date: May 25, 2007
Revision 1.0
-21-
W83627UHG
Table 6-1 Devices of I/O Base Address
LOGICAL DEVICE
NUMBER
I/O BASE
ADDRESS
DEFAULT
VALUE
FUNCTION
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
FDC
100h ~ FF8h
100h ~ FF8h
100h ~ FF8h
100h ~ FF8h
3F0h
378h
3F8h
2F8h
Parallel Port
UART A
UART B
Reserved
Keyboard Controller
UART C
100h ~ FF8h
100h ~ FF8h
100h ~ FF8h
Reserved
60h/64h
3E0h
GPIO 3, 4
-
WDTO# & PLED, and GPIO 5, 6
GPIO 1, 2
-
Reserved
-
ACPI
Reserved
-
Hardware Monitor
PECI & SST
UART C
100h ~ FF8h
Reserved
-
-
100h ~ FF8h
100h ~ FF8h
100h ~ FF8h
2E0h
3E8h
2E8h
UART D
UART E
-22-
W83627UHG
6.1 Configuration Sequence
Power-on Reset
Any other I/O transition cycle
Wait for key string
I/O Write to 2Eh
N
Is the data
“87h”?
Y
Any other I/O transition cycle
Check Pass key
I/O Write to 2Eh
N
Is the data
“87h”?
Y
Extended Function
Mode
Figure 6-2 Configuration Register
To program the W83627UHG configuration registers, the following configuration procedures must be
followed in sequence:
(1). Enter the Extended Function Mode.
(2). Configure the configuration registers.
(3). Exit the Extended Function Mode.
6.1.1
Enter the Extended Function Mode
To place the chip into the Extended Function Mode, two successive writes of 0x87 must be applied to
Extended Function Enable Registers (EFERs, i.e. 2Eh or 4Eh).
Publication Release Date: May 25, 2007
-23-
Revision 1.0
W83627UHG
6.1.2
Configure the Configuration Registers
The chip selects the Logical Device and activates the desired Logical Devices through Extended
Function Index Register (EFIR) and Extended Function Data Register (EFDR). The EFIR is located at
the same address as the EFER, and the EFDR is located at address (EFIR+1).
First, write the Logical Device Number (i.e. 0x07) to the EFIR and then write the number of the desired
Logical Device to the EFDR. If accessing the Chip (Global) Control Registers, this step is not required.
Secondly, write the address of the desired configuration register within the Logical Device to the EFIR
and then write (or read) the desired configuration register through the EFDR.
6.1.3
Exit the Extended Function Mode
To exit the Extended Function Mode, writing 0xAA to the EFER is required. Once the chip exits the
Extended Function Mode, it is in the normal running mode and is ready to enter the configuration
mode.
6.1.4
Software Programming Example
The following example is written in Intel 8086 assembly language. It assumes that the EFER is located
at 2Eh, so the EFIR is located at 2Eh and the EFDR is located at 2Fh. If the HEFRAS (CR26 bit 6) is
set, 2Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh.
;-----------------------------------------------------
; Enter the Extended Function Mode
;-----------------------------------------------------
MOV DX, 2EH
MOV AL, 87H
OUT DX, AL
OUT DX, AL
;-----------------------------------------------------------------------------
; Configure Logical Device 1, Configuration Register CRF0
;-----------------------------------------------------------------------------
MOV DX, 2EH
MOV AL, 07H
OUT DX, AL
MOV DX, 2FH
MOV AL, 01H
OUT DX, AL
;
; point to Logical Device Number Reg.
; select Logical Device 1
MOV DX, 2EH
MOV AL, F0H
OUT DX, AL
MOV DX, 2FH
MOV AL, 3CH
OUT DX, AL
; select CRF0
; update CRF0 with value 3CH
-24-
W83627UHG
;------------------------------------------
; Exit the Extended Function Mode
;------------------------------------------
MOV DX, 2EH
MOV AL, AAH
OUT DX, AL
Table 6-2 Chip (Global) Control Registers
INDEX
02h
07h
20h
21h
22h
23h
24h
25h
R/W
Write Only
R/W
DEFAULT VALUE
DESCRIPTION
Software Reset
Logical Device
Chip ID, MSB
00h
A2h
Read Only
Read Only
R/W
3xh
Chip ID, LSB
FFh
Device Power Down
Device Power Down
Global Option
R/W
F0h
R/W
0100_0ss0b
00h
R/W
Interface Tri-state
Enable
26h
27h
28h
29h
R/W
0s000000b
Reserved
00h
Global Option
R/W
R/W
Global Option
00h
Multi-function Pin
Selection
2Ah
2Bh
2Ch
R/W
00h
I2C Pin Select
Reserved
02h
R/W
R/W
Multi-function Pin
Selection
2Dh
00h
GPIO2 Input Detected
Type
2Eh
2Fh
R/W
R/W
00h
00h
Reserved
Reserved
S: Strapping; x: chip version.
Publication Release Date: May 25, 2007
Revision 1.0
-25-
W83627UHG
7. HARDWARE MONITOR
7.1 General Description
The W83627UHG monitors several critical parameters in PC hardware, including power supply
voltages, fan speeds, and temperatures, all of which are very important for a high-end computer
system to work stably and properly. In addition, proprietary hardware reduces the amount of
programming and processor intervention to control cooling fan speeds, minimizing ambient noise and
maximizing system temperature and reliability.
The W83627UHG can simultaneously monitor all of the following inputs:
•
Eight analog voltage inputs (four internal voltages VBAT, 5VSB, 5VCC and AVCC power; four
external voltage inputs)
•
•
Two fan tachometer inputs
Two remote temperatures, using either a thermistor or the CPU thermal diode (voltage or
current mode measurement method)
•
One case-open detection signal.
These inputs are converted to digital values using the integrated, eight-bit analog-to-digital converter
(ADC).
In response to these inputs, the W83627UHG can generate the following outputs:
•
•
•
•
Two PWM (pulse width modulation) or DC fan outputs for the fan speed control
Beep tone output for warnings
SMI#
OVT# signals for system protection events
The W83627UHG provides hardware access to all monitored parameters through the LPC or I2C
interface and software access through application software, such as Winbond’s Hardware DoctorTM, or
BIOS. In addition, the W83627UHG can generate pop-up warnings or beep tones when a parameter
goes outside of a user-specified range.
The rest of this section introduces the various features of the W83627UHG hardware-monitor
capability. These features are divided into the following sections:
•
•
•
•
•
•
•
Access Interfaces
Analog Inputs
Fan Speed Measurement and Control
Smart Fan Control
SMI# Interrupt Mode
OVT# Interrupt Mode
Registers and Value RAM
7.2 Access Interfaces
The W83627UHG provides two interfaces, LPC and I2C, for the microprocessor to read or write the
internal registers of the hardware monitor.
-26-
W83627UHG
7.2.1
LPC Interface
The internal registers of the hardware monitor block are accessible through two separate methods on
the LPC bus. The first set of registers, which primarily enables the block and sets its address in the
CPU I/O address space are accessed by the Super I/O protocol described in Chapter 6 at address
2Eh/2Fh or 4Eh/4Fh. The bulk of the functionality and internal registers of this block are accessed
from an index/data pair of CPU I/O addresses. The standard locations are usually 295h/296h and are
set by CR60 and CR61 accessed using the Super I/O protocol as described in Chapter 6.
Due to the number of internal registers, it is necessary to separate the register sets into “banks”
specified by register 4Eh. The structure of the internal registers is shown in the following figure.
Publication Release Date: May 25, 2007
-27-
Revision 1.0
W83627UHG
Smart Fan Configuration
Registers
00h-1Fh
Monitor Value Registers
20h~3Fh
BANK 0
FANOUT Critical
Temperature
6Bh~6Eh
Configuration Register
40h
BANK 1
Interrupt Status Registers
41h, 42h
CPUTIN Temperature
Control/Stauts Registers
50h~56h
SMI# Mask Registers
43h, 44h, 46h
Fan Divisor Register I
47h
LPC
Bus
Serial Bus Address
48h
BANK 4
Interrupt Status & SMI#
Mask Registers
50h~51h
Port 5h
FANOUTs Source Select Register
49h, 4Ah
Index
Register
BANK 4
Beep Control Registers
53h
Fan Divisor Register II
4Bh
SMI#/OVT# Control Register
4Ch
BANK 4
Temperature Offset
Fan IN /OUT Control Register
4Dh
Registers
54h~56h
Bank Select for 50h~5Fh
Registers
4Eh
BANK 4
Real Time Status
Registers
Port 6h
Winbond Vendor ID
4Fh
59h~5Bh
Data
Register
BANK 0
BEEP Control Registers
56h~57h
BANK 5
Monitor Value Registers
50h~5Ch
BANK 0
Chip ID Register
58h
BANK 0
Temperature Sensor Type
Configuration &
Fan Divisor Registers
59h,5Dh
BANK 0
Cirtical Tempature and
Curren mode enable
5Eh
BANK 0
Smart Fan Configuration
Registers
60h~6Ah
Figure 7-1 LPC Bus’ Reads from / Writes to Internal Registers
-28-
W83627UHG
7.2.2
I2C Interface
The I2C interface is a second, parallel port into the internal registers of the hardware monitor function
block. The interface is totally compatible with the industry-standard I2C specification, allowing external
components that are also compatible to read the internal registers of the W83627UHG hardware
monitor and control fan speeds. The address of the I2C peripheral is set by the register located at
index 48h (which is accessed by the index/data pair at I/O address typically at 295h/296h).
The two timing diagrams below illustrate how to use the I2C interface to write to an internal register
and how to read the value in an internal register, respectively.
(a) Serial bus write to internal address register followed by the data byte
0
7
8
0
7
8
SCL
SDA
0
1
0
1
1
0
1
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Start By
Master
Ack
by
627UHG
Ack
by
627UHG
Frame 1
Serial Bus Address Byte
Frame 2
Internal Index Register Byte
0
7
8
SCL (Continued)
SDA (Continued)
D7
D6
D5
D4
D3
D2
D1
D0
AAckck
byby
768247RUHG
Stop
by
Master
Frame 3
Data Byte
Figure 7-2 Serial Bus Write to Internal Address Register Followed by the Data Byte
Publication Release Date: May 25, 2007
Revision 1.0
-29-
W83627UHG
(b) Serial bus read from a register
0
7
8
0
7
8
SCL
SDA
0
1
0
1
1
0
1
R/W
D7 D6
D5 D4 D3 D2
Frame 2
D1 D0
Start By
Master
Ack
by
Ack
by
627UHG
Frame 1
627UHG
Serial Bus Address Byte
Internal Index Register Byte
0
8
0
0
7
0
7
8
1
0
1
1
0
1
R/W
D7 D6
D5 D4 D3 D2
D1 D0
Ack
by
Master
Ack
by
627UHG
Stop by
Master
Frame 3
Serial Bus Address Byte
Repeat
Frame 4
Data Byte
start
by
Master
0
Figure 7-3 Serial Bus Read from Internal Address Register
-30-
W83627UHG
7.3 Analog Inputs
The eight analog inputs of the hardware monitor block connect to an 8-bit Analog to Digital Converter
(ADC) and consist of four general-purpose inputs connected to external device pins (CPUVCORE,
VIN0 – VIN2) and four internal signals connected to the power supplies (AVCC, VBAT, 5VSB and
5VCC). All inputs are limited to a maximum voltage of 2.048V due to an internal setting of 8mV LSB
(256 steps x 8mV = 2.048V). All inputs to the ADC must limit the maximum voltage by using a voltage
divider. The power supplies have internal resistors, while the external pins require outside limiting
resistors as described below.
Pin 97
AVCC
Pin 74
VBAT
Power Inputs
Pin 61
5VSB
Pin 12
5VCC
Pin 101
CPUVCORE
R1
VIN0
Pin 100
V0
R2
Positive Voltage Input
8-bit ADC
with
8mV LSB
Pin 99
Pin 98
VIN1
R3
VIN2
Negative Voltage Input
V2
R4
R
THM
10K@25 C, beta=3435K
R
10K, 1%
VREF
Pin 102
R
15K, 1%
CPUTIN
SYSTIN
Pin 103
Pin 104
CPUD+
CAP,2200p
Pin 105
AGND
CPUD-
(AGND)
Figure 7-4 Analog Inputs and Application Circuit of the W83627UHG
As illustrated in the figure above, other connections may require some external circuits. The rest of
this section provides more information about voltages outside the range of the 8-bit ADC, CPU Vcore
voltage detection, and temperature measurement
Publication Release Date: May 25, 2007
-31-
Revision 1.0
W83627UHG
7.3.1
Voltages Over 2.048 V or Less Than 0 V
Input voltages greater than 2.048 V should be reduced by an external resistor divider to keep the input
voltages in the proper range. For example, input voltage V0 (+12 V) should be reduced before it is
connected to VIN0 according to the following equation:
R2
VIN0 = V ×
0
R1 + R2
R1 and R2 can be set to 150 KΩ and 10 KΩ, respectively, to reduce V0 from +12 V to less than 2.048
V.
The W83627UHG uses the same approach. Pins 12 and 97 provide two functions. One, these pins
are connected to 5VCC at +5 V to supply internal (digital / analog) power to the W83627UHG. Two,
these pins monitor 5VCC. The W83627UHG has two internal, 80-KΩ and 20-KΩ, serial resistors that
reduce the ADC-input voltage to 1 V.
20KΩ
80KΩ + 20KΩ
Vin = 5VCC ×
≅ 1V , where 5VCC is set to 5V
Pin 61 is implemented likewise to monitor its +5 V stand-by power supply.
Pin 74 also has two internal, 20-KΩ serial resistors that reduce the ADC-input voltage to 1.65 V.
20KΩ
20KΩ + 20KΩ
Vin =VBAT ×
≅ 1.65V , where VBAT is set to 3.3V
The CPUVCORE pin feeds directly into the ADC with no voltage divider since the nominal voltage on
this pin is only 1.2V.
Negative voltages are handled similarly, though the equation looks a little more complicated. For
example, negative voltage V2 (-5V) can be reduced according to the following equation:
R4
VIN2 = (V2 − 2.048)×
+ 2.048,whereV 2 = −5
4
R
3
+ R
R3 and R4 can be set to 120 KΩ and 10 KΩ, respectively, to reduce negative input voltage V2 from – 5
V to less than 2.048 V. Note that R4 is referenced to VREF, or 2.048V instead of 0V to allow for more
dynamic range. This is simply good analog practice to yield the most precise measurements.
Both of these solutions are illustrated in the figure above.
7.3.2
Voltage Detection
The data format for voltage detection is an eight-bit value, and each unit represents an interval of 8
mV.
Detected Voltage = Reading * 0.008 V
If the source voltage was reduced by a voltage divider, the detected voltage value must be scaled
up accordingly.
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W83627UHG
The voltage values can be read at Hardware Monitor Register Bank 0, Index 20h to 25h.
7.3.3 Temperature Sensing
The data format for sensor SYSTIN is 8-bit, two's-complement, and the data format for sensors
CPUTIN is 9-bit, two's-complement. This is illustrated in the table below.
Table 7-1 Temperature Data Format
8-BIT DIGITAL OUTPUT
8-BIT BINARY 8-BIT HEX
0111,1101 7Dh
9-BIT DIGITAL OUTPUT
9-BIT BINARY 9-BIT HEX
TEMPERATURE
+125°C
+25°C
+1°C
0,1111,1010
0,0011,0010
0,0000,0010
0,0000,0001
0,0000,0000
1,1111,1111
1,1111,1110
1,1100,1110
1,1001,0010
0FAh
032h
002h
001h
000h
1FFh
1FFh
1CEh
192h
0001,1001
0000,0001
-
19h
01h
+0.5°C
+0°C
-
-
0000,0000
-
00h
-0.5°C
-1°C
1111,1111
1110,0111
1100,1001
FFh
E7h
C9h
-25°C
-55°C
Eight-bit temperature data is read from Index 27h. For nine-bit temperature data, the 8 MSB are read
from Bank1 Index 50h,and the LSB is read from Bank1 Index 51h, bit 7.
There are two sources of temperature data: external thermistors or thermal diodes.
7.3.3.1
Monitor Temperature from Thermistor
External thermistors should have a β value of 3435K and a resistance of 10 KΩ at 25°C. As illustrated
in the schematic below, the thermistor is connected in series with a 10-KΩ resistor and then connects
to VREF (pin 102). The configuration registers to select a themistor temperature sensor and the
measurement method are found at Bank 0, Index 59h, 5Dh, and 5Eh.
R
RTHM
10K, 1%
10K@25°C, beta=3435K
VREF Pin 102
CPUTIN Pin 103
W83627UHG
SYSTIN Pin 104
Figure 7-5 Monitoring Temperature from Thermistor
Publication Release Date: May 25, 2007
Revision 1.0
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W83627UHG
7.3.3.2
Monitor Temperature from Thermal Diode (Voltage Mode)
The thermal diode D- pin is connected to AGND (pin 105), and the D+ pin is connected to the
temperature sensor pin in the W83627UHG. A 15-KΩ resistor is connected to VREF to supply the bias
current for the diode, and the 2200-pF, bypass capacitor is added to filter high-frequency noise. The
configuration registers to select a thermal diode temperature sensor and the measurement method are
found at Bank 0, Index 59h, 5Dh, and 5Eh.
VREF
R= 15K, 1%
W83627UHG
CPUTIN
(SYSTIN)
D+
D-
Thermal
Diode
C= 2200pF
AGND
Figure 7-6 Monitoring Temperature from Thermal Diode (Voltage Mode)
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W83627UHG
7.3.3.3
Monitor Temperature from Thermal Diode (Current Mode)
The W83627UHG also can measure diode temperature by current mode and the circuit is shown in
the following figure.
W83627UHG
CPUTIN
(SYSTIN)
D+
D-
Thermal
Diode
C= 2200pF
AGND
Figure 7-7 Monitoring Temperature from Thermal Diode
The pin of processor D- is connected to AGND (pin 105) and the pin D+ is connected to temperature
sensor pin in W83627UHG. A bypass capacitor C=2200pF should be added to filter the high
frequency noise. The configuration registers to select a thermal diode temperature sensor and the
measurement method are found at Bank 0, Index 59h, 5Dh, and 5Eh.
7.4 SST Command Summary
The W83627UHG can act as an SST peripheral or slave and output the results of the Analog to Digital
Converter onto the SST bus. SST is a new, popular standard to communicate temperature and
voltage information from around the PC motherboard to report on the status of the system and control
cooling fans and other safety mechanisms.
SST is a self-clocked, one-wire bus for data transfer. The bus requires no additional control lines. In
addition, SST also includes variable data transfer rate established with every message. Therefore, it is
comparatively flexible. The W83627UHG has a programmable SST address defined at Logical Device
C CR[F1h]. The default address is 0x48h which is within the range of 0x48h-0x4ah defined in the SST
specification.
Since the same, integrated Analog to Digital Converter is used, all the features and restrictions of use
remain the same. The reference voltage is integrated and fixed with the 8-bit ADC, yielding a
maximum voltage on each of 2.048V and an LSB of 8mV. As discussed in the previous section 7.3,
voltage scaling using resistive dividers may be necessary to keep external voltages within the
maximum input voltage range. The power supply pins have integrated resistive dividers.
Publication Release Date: May 25, 2007
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Revision 1.0
W83627UHG
7.4.1
Command Summary
The W83627UHG supports SST commands as shown in the following table:
Table 7-2 SST Command Summary
COMMAND
DESCRIPTION
ResetDevice()
This command is used to recover from serious
hardware or bus error.
GetDIB()
Support 8-byte and 16-byte read length
GetIntTemp()
Returns the 20byte temperature data values for
pin SYSTIN (Pin 104)
GetExtTemp()
GetAllTemps()
GetVolt12V()
Returns the 2-byte temperature data values for
pin CPUTIN (Pin 103)
Returns the 4-byte temperature data values for
both SYSTIN and CPUTIN
Returns the 2-byte voltage data values for pin
VIN0 (Pin 100). This pin should be connected to
+12V power through scaling resistors. Please
refer to section 7.4.2.2
GetVolt5V()
Returns the 2-byte voltage data values for pin
5VCC (Pin 12, 48). This pin should be
connected to +5V power directly. Please refer to
section 7.4.2.2
GetVolt3p3V()
GetVolt2p5V()
GetVoltVccp()
Returns the 2-byte voltage data values for pin
VIN1 (Pin 99). This pin should be connected to
+3.3V power through scaling resistors. Please
refer to section 7.4.2.2
Returns the 2-byte voltage data values for pin
VIN2 (Pin 98). This pin should be connected to
+2.5V power through scaling resistors. Please
refer to section 7.4.2.2
Returns the 2-byte voltage data values of
CPUVCORE (Pin 101). This pin should be
connected to CPU power supply directly. The
CPU power supply voltage must not be higher
than 2.048 volt
GetAllVoltages()
Returns a 10-byte voltage data value containing
all the above listed five (5) voltages
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W83627UHG
7.4.2
Combination Sensor Data Format
Temperature Data Format
7.4.2.1
The W83627UHG temperature data format of both CPUTIN and SYSTIN is 16-bit two’s-complement
binary value. It represents multiple of 1/64°C in the temperature reading.
Table 1 shows some typical temperature values in 16-bit two’s complement format.
Table 7-3 Typical Temperature Values
TEMPERATURE
16-BIT DIGITAL OUTPUT (2’S COMPLEMENT)
16-BIT BINARY
16-BIT HEX
1400h
+80°C
+79.5°C
+1°C
0001 0100 0000 0000
0001 0011 1110 0000
0000 0000 0100 0000
0000 0000 0000 0000
1111 1111 1100 0000
1111 1110 1100 0000
13E0h
0010h
+0°C
0000h
-1°C
FFC0h
FEC0h
-5°C
7.4.2.2
Voltage Data Format
The W83627UHG can return five (5) voltage values through the SST interface. The voltage data
format is 16-bit two’s-complement binary. The relation between the 2-byte data and the monitored
voltage is listed below:
1) CPUVCORE (pin 101) = Decimal[2-byte data by GetVoltVccp() ] / 1024 volts
2) 5VCC (pin 12) = Decimal[2-byte data by GetVolt5V()] / 1024 volts
3) “+12V” = Decimal[2-byte data by GetVolt12V()] / 1024 / ((R1+R2) / R2) volts
VIN0 (pin 100) is connected as shown below:
R2
+12V
AGND
VIN0
1
1
R1
150K 1%
10K 1%
4) “+3VCC” = Decimal[2-byte data by GetVolt3p3V()] / 1024 / ((R3+R4) / R4) volts
VIN1 (pin 99) is connected as shown below:
R3
3VCC
VIN1
1
10K 1%
R4
AGND
1
10K 1%
Publication Release Date: May 25, 2007
Revision 1.0
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W83627UHG
5) “+2.5V” = Decimal[2-byte data by GetVolt2p5V()] / 1024 / ((R5+R6) / R6) volts
VIN2 (pin 98) is connected as shown below:
R5
2.5V
VIN2
1
10K 1%
R6
AGND
1
10K 1%
7.5 PECI
PECI (Platform Environment Control Interface) is a proprietary derivation of SST. It is one of the
temperature sensing methods that the W83627UHG supports. With a bandwidth ranging from 2 kbps
to 2 Mbps, PECI uses a single wire – no additional control lines needed – for self-clocking and data
transfer. By interfacing to Digital Thermal Sensor on the Intel® CPU, PECI reports a negative
temperature value relative to the processor’s temperature at which the thermal control circuit (TCC) is
activated.
To enable the PECI functionalities of the W83627UHG, BIOS/software should follow the steps below:
1. Program Logical Device C, CR[E8h] bit (1..0) for PECI speed selection to meet the bit timing limits
of CPU with PECI. “11b” is recommended to be set to the bit for better stability.
2. Program Logical Device C, CR[E5h] bit (7..4) for each PECI Agent to match the number of
domains in the processors. Setting to “1” enables the W83627UHG to issue GetTemp(0) and
GetTemp(1) commands to access the PECI temperatures of domains 0 and domain 1. Setting to “0”
enables the W83627UHG to issue GetTemp(0) command for domain 0.
3. Program Logical Device C, CR[E0h] bit (3..0) for each PECI Agent. Setting to “1” returns the PECI
temperature of domain 1 to the temperature reading register. Setting to “0” returns the PECI
temperature of domain 0 to the temperature reading register. If CR[E5h] bit 1 is set to “1”, the higher
PECI temperature of domain 0 and domain 1 is returned to the temperature reading register. See the
example below for more details about the temperature reading register(s)
4. Program Logical Device C, CR[E0h] bit (7..4) for each PECI Agent. Setting to “1” enables the
W83627UHG to access the agent. The power-on default is disabled. After an agent is enabled, the
W83627UHG issues PING and GetTemp commands to obtain the PECI temperature.
5. Since the PECI temperature is a relative value, the W83627UHG provides registers for each PECI
Agent to convert the relative value to a more traditional “absolute” format. The TBase registers
(Logical Device C, CR[E1h]~CR[E4h]) store the “base” temperature. By means of BIOS/software, the
desired base temperature can be written to these registers. Important: the value must be positive.
Otherwise abnormal temperature responses will take place. Here is an example on how to obtain
TBase value:
(1). Use a digital thermometer on the surface of the PECI processor to measure the processor body
temperature.
(2). Power up the system with the PECI processor. Run the processor to 100% loading.
(3). After the system is stable, read the PECI reading from Logical Device C, CR[E0h] ~ CR[E7h] of
selected Agents and record the value of the digital thermometer.
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W83627UHG
(4). Calculate TBase. For example, if PECI = -10 and the digital thermometer is 50’C, then TBase
could be set to 60’C. (60 – 10 = 50).
6. There are two temperature reading registers in the W83627UHG: Bank1, Index 50h & 51h, and
Bank2, Index 50h & 51h. The source of the Bank 1, Index 50h & 51h value is determined by the
value programmed into the CPUFANOUT monitor Temperature source select register (Hardware
Monitor Device, Bank 0, Index 49h, bits (2..0)). The source of Bank 2, Index 50h & 51h value is
determined by the value programmed into the SYSFANOUT monitor Temperature source select
register (Hardware Monitor Device, Bank 0, Index 4Ah, bits(7..5)).
7. The temperature values in Bank 1 and Bank 2 Index 50h & 51h are:
Bank 1, Index 50h & 51h = (TBase) + (PECI Agent relative temperature)
Bank 2, Index 50h & 51h = (TBase) + (PECI Agent relative temperature)
Example:
If the PECI relative temperature of agent 1 is -10; TBase is set to 72°C, and Bank0 Index 49h
selects PECI Agent 1 as the temperature source, the reported temperature will be 62°C (-10 + 72).
Please be noted that when the temperature source is selected as PECI temperature source,
the Bank 1 Index 50h & 51h or Bank 2 Index 50h & 51h reading does not reflect the actual
temperature of the processor.
8. In addition, each PECI Agent relative temperature can be read in Logical Device C, CR[E0h] ~
CR[E7h], as long as Logical Device C, CR[E8h] bit 3 is set to “1”. When this bit is “1”, Logical Device
C, CR[E0h] ~ CR[E7h] become “Read Only” registers.
CPU
W83627UHG
(PECI Host)
PECI
PECI
Fan Control
Figure 7-8 PECI Illustration
9. A warning flag register at Logical Device C, CR[E8h] bit (7..4) is designed for each PECI
Agent to report whether the W83627UHG (PECI host) detects the PECI client or not and whether the
PECI client returns invalid FCS values from the polling for three successive times.
Publication Release Date: May 25, 2007
-39-
Revision 1.0
W83627UHG
7.6 Fan Speed Measurement and Control
This section is divided into two parts, one to measure the speed and the other to control the speed.
7.6.1 Fan Speed Measurement
The W83627UHG can measure fan speed for fans equipped with tachometer outputs. The tachometer
signals should be set to TTL-level, and the maximum input voltage cannot exceed +5 V. If the
tachometer signal exceeds +5 V, an external trimming circuit should be added to reduce the voltage
accordingly.
The fan speed counter is read from Bank0 Index 28h, and 29h. The fan speed can then be evaluated
by the following equation:
1.35×106
Count × Divisor
RPM =
The default divisor is 2 and is specified at Bank0 Index 47h, bits 7 ~ 4; and Index 5Dh, bits 6 ~ 5.
There are three bits for each divisor, and the corresponding divisor is listed in the table below.
Table 7-4 Fan Divisor Definition
BIT 2
BIT 1
BIT 0
FAN DIVISOR
BIT 2
BIT 1
BIT 0
FAN DIVISOR
0
0
0
0
0
0
1
1
0
1
0
1
1
2
4
8
1
1
1
1
0
0
1
1
0
1
0
1
16
32
64
128
The following table provides some examples of the relationship between divisor, RPM, and count.
Table 7-5 Divisor, RPM, and Count Relation
NOMINAL
RPM
TIME PER
REVOLUTION
DIVISOR
COUNTS
70% RPM
TIME FOR 70%
1
8800
4400
2200
1100
550
6.82 ms
13.64 ms
27.27 ms
54.54 ms
109.08 ms
218.16 ms
436.32 ms
872.64 ms
153
153
153
153
153
153
153
153
6160
3080
1540
770
385
192
96
9.84 ms
19.48 ms
38.96 ms
77.92 ms
155.84 ms
311.68 ms
623.36 ms
1246.72 ms
2 (default)
4
8
16
32
64
128
275
137
68
48
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W83627UHG
7.6.2
Fan Speed Control
The W83627UHG has two output pins for fan control, each of which offers PWM duty cycle and DC
voltage to control the fan speed. The output type (PWM or DC) of each pin is configured by Bank0
Index 04h, bits 1 ~ 0.
For PWM, the duty cycle is programmed by eight-bit registers at Bank0 Index 01h and Index 03h. The
duty cycle can be calculated using the following equation:
Programmed8 - bit Register Value
Dutycycle(%) =
×100%
255
The default duty cycle is FFh, or 100%. The PWM clock frequency is programmed at Bank0 Index 00h
and Index 02h.
For DC, the W83627UHG has a six bit digital-to-analog converter (DAC) that produces 0 to 5 Volts DC.
The analog output is programmed at Bank0 Index 01h and Index 03h. The analog output can be
calculated using the following equation:
Programmed 6 - bit Register Value
= AVCC ×
`
OUTPUT Voltage (V)
64
The default value is 111111YY, or nearly 5 V, and Y is a reserved bit.
Publication Release Date: May 25, 2007
Revision 1.0
-41-
W83627UHG
7.6.3
SMART FANTM Control
The W83627UHG supports two SMART FANTM I features—Thermal CruiseTM mode and Fan Speed
CruiseTM mode—and SMART FANTM III. Each of these is discussed in the following sections. When
SMART FANTM I features are enabled, fan output starts from the previous setting in Bank0 Index 01h
and Index 03h.
There are two pairs of temperature sensors and fan outputs in SMART FANTM I, as illustrated in the
figure below.
SYSTIN
CPUTIN
PECI_Agent1
Pin 92
SYSFANOUT
PECI_Agent2
PECI_Agent3
PECI_Agent4
CPUTIN
PECI_Agent1
Pin 90
CPUFANOUT
PECI_Agent2
PECI_Agent3
PECI_Agent4
Figure 7-9 FANOUT and Corresponding Temperature Sensors in SMART FANTMI
7.6.3.1
Thermal CruiseTM Mode
Two pairs of temperature sensors and fan outputs in Thermal CruiseTM mode:
•
•
SYSTIN and the temperature sensor selected by Bank0 Index 4Ah, bits 7 ~ 5
CPUTIN and the temperature sensor selected by Bank0 Index 49h, bits 2 ~ 0
Thermal CruiseTM mode controls the fan speed to keep the temperature in a specified range. First, this
range is defined in BIOS by a temperature and the interval (e.g., 55 °C ± 3 °C). As long as the current
temperature remains below the low end of this range (i.e., 52 °C), the fan is off. Once the temperature
exceeds the low end, the fan turns on at a speed defined in BIOS (e.g., 20% output). Thermal
CruiseTM mode then controls the fan output according to the current temperature. Three conditions
may occur:
(1) If the temperature still exceeds the high end, fan output increases slowly. If the fan is operating
at full speed but the temperature still exceeds the high end, a warning message is issued to
protect the system.
(2) If the temperature falls below the high end (e.g., 58 °C) but remains above the low end (e.g.,
52 °C), fan output remains the same.
(3) If the temperature falls below the low end (e.g., 52 °C), fan output decreases slowly to zero or
to a specified “stop value”. This stop value is enabled by Bank0 Index12h, bits 5 ~ 4, and the
value itself is specified in Bank0 Index 08h and Index 09h. The fan remains at the stop value for
the period of time defined in Bank0 Index 0Ch and Index 0Dh.
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W83627UHG
In general, Thermal CruiseTM mode means
•
•
•
if the current temperature is higher than the high end, increase the fan speed;
if the current temperature is lower than the low end, decrease the fan speed;
otherwise, keep the fan speed the same.
The following figures illustrate two examples of Thermal CruiseTM mode.
Figure 7-10 Mechanism of Thermal CruiseTM Mode (PWM Duty Cycle)
Figure 7-11 Mechanism of Thermal CruiseTM Mode (DC Output Voltage)
Publication Release Date: May 25, 2007
Revision 1.0
-43-
W83627UHG
7.6.3.2
Two pairs of fan input sensors and fan outputs in Fan Speed CruiseTM mode.
Fan Speed CruiseTM Mode
•
•
SYSFANIN and SYSFANOUT
CPUFANIN and CPUFANOUT
Fan Speed CruiseTM mode keeps the fan speed in a specified range. First, this range is defined in
BIOS by a fan speed count (the amount of time between clock input signals, not the number of clock
input signals in a period of time) and an interval (e.g., 160 ± 10). As long as the fan speed count is in
the specified range, fan output remains the same. If the fan speed count is higher than the high end
(e.g., 170), fan output increases to make the count lower. If the fan speed count is lower than the low
end (e.g., 150), fan output decreases to make the count higher. One example is illustrated in this
figure.
A
C
Count
170
160
150
(%)
100
Fan
output
50
0
Figure 7-12 Mechanism of Fan Speed CruiseTM Mode
The following tables show current temperature, fan output value and the relative control registers at
Thermal CruiseTM and Fan Speed CruiseTM mode.
Table 7-6 Display Registers – at SMART FANTM I Mode
REGISTER
ADDRESS
DESCRIPTION
REGISTER NAME
ATTRIBUTE
BIT DATA
Bank1, Index
50h ,51h
Current CPU
Temperature
CPUTIN Temperature
Sensor
8 MSB, 1°C bit 7,
0.5 °C
Read only
Bank0, Index
27h
Current SYS
Temperature
SYSTIN Temperature
Sensor
Read only
8 MSB, 1°C
Current
CPUFANOUT
Output Value
Bank0, Index
03h
CPUFANOUT Output
Value Select
80h / FFh by
strapping
Bits 7-0
CPUFANOUT Value
Current
Bank0 Index
01h
SYSFANOUT Output
Value Select
80h / FFh by
strapping
Bits 7-0
SYSFANOUT Value
SYSFANOUT
Output Value
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W83627UHG
Table 7-7 Relative Registers – at Thermal CruiseTM Mode
KEEP
MIN.
FAN
SPEED
CRUISETM
MODE
START-
UP
VALUE
STEP-
DOWN
TIME
TARGET
TEMPERATURE
STOP
VALUE
STOP
TIME
STEP-
UP TIME
TOLERANCE
OUTPUT
VALUE
Bank0, 07h
Bits0-3
Bank0,
0Ah
Bank0,
08h
Bank0,
12h, Bit5
Bank0,
0Ch
SYSFANOUT
CPUFANOUT
Bank0, 05h
Bank0, 06h
Bank0,
0Eh
Bank0,
0Fh
Bank0, 07h
Bits 4-7
Bank0,
0Bh
Bank0,
09h
Bank0,
12h, Bit4
Bank0,
0Dh
Table 7-8 Relative Registers – at Speed CruiseTM Mode
THERMAL-
CRUISETM
MODE
STEP-
DOWN
TIME
KEEP MIN. FAN
OUTPUT VALUE
TARGET-SPEED
COUNT
STEP-
UP TIME
TOLERANCE
Bank0, Index 07h Bank0, Index 12h
Bits 0-3 Bit5
Bank0, Index 07h Bank0, Index 12h
Bits 4-7 Bit4
SYSFANOUT
CPUFANOUT
Bank0, Index 05h
Bank0, Index 06h
Bank0,
Index
0Eh
Bank0,
Index
0Fh
7.6.3.3
SMART FANTM III
SMART FANTM III controls the fan speed so that the temperature meets the target temperature set in
BIOS or application software. There is only one pair of fan outputs and temperature sensors in SMART
FANTM III mode.
•
CPUFANOUT and the temperature sensor selected by Bank0 Index 49h, bits 2 ~ 0
CPUTIN
PECI_Agent1
PECI_Agent2
Pin 90
PECI_Agent3
CPUFANOUT
PECI_Agent4
Figure 7-13 FANOUT and Corresponding Temperature Sensor in SMART FANTM III
The algorithm is as follows:
Publication Release Date: May 25, 2007
Revision 1.0
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W83627UHG
(1) The target temperature, temperature tolerance, maximum and minimum fan outputs and step are
set.
(2) The following figure shows the initial conditions. If the current temperature is within (Target
Temperature ± Temperature Tolerance), the fan speed remains constant.
Setting
Fan output
(DC / PWM)
Tolerance
Max. Fan Output
Min. Fan Output
Tar. - Tol.
Tar. + Tol.
Temperature
Figure 7-14 Setting of SMART FANTM III
(3) If the current temperature is higher than (Target Temperature + Temperature Tolerance), fan
speed rises one step. The step is the value in the CPUFANOUT Output Value Select Register,
Bank0, Index 03h. In addition, the target temperature shifts to (Target Temperature + Temperature
Tolerance), creating a new target temperature, named Target Temperature 1 in this figure.
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W83627UHG
Current Temp. > Target Temp. + Tol.
Fan output
(DC / PWM)
Tolerance
Max. Fan Output
Step
Fan Initial
Output Value
Min. Fan Output
Tar 1
Tar 3
Tar 2
Temperature
Tar
Tar 5
Tar 4
Figure 7-15 SMART FANTM III Mechanism (Current Temp. > Target Temp. + Tol.)
If the current temperature rises higher than (Target Temperature 1 + Temperature Tolerance), the fan
speed rises one step again, and the target temperature shifts to (Target Temperature 1 + Temperature
Tolerance), or Target Temperature 2. This process repeats whenever the current temperature is
higher than (Target Temperature X ± Temperature Tolerance) or until the fan speed reaches its
maximum speed.
(4) If the current temperature falls below (Target Temperature － Temperature Tolerance), the fan
speed falls one step. The step is the value in the CPUFANOUT Output Value Select Register,
Bank0, Index 03h. In addition, the target temperature shifts to (Target Temperature －
Temperature Tolerance), creating a new target temperature named Target Temperature 1.This is
illustrated in the figure below.
Publication Release Date: May 25, 2007
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Revision 1.0
W83627UHG
Current Temp. < Target Temp.- Tol.
Fan output
(DC / PWM)
Tolerance
Max. Fan Output
Fan Initial
Output Value
Step
Min. Fan Output
Temperature
Tar
Tar 2
Tar 3
Tar 1
Figure 7-16 SMART FANTM III Mechanism (Current Temp. < Target Temp. – Tol.)
If the current temperature falls lower than (Target Temperature 1 － Temperature Tolerance), the fan
speed is reduced one step again, and the target temperature shifts to (Target Temperature 1 －
Temperature Tolerance), or Target Temperature 2. This process repeats whenever the current
temperature is lower than (Target Temperature X － Temperature Tolerance) or until the fan speed
reaches its minimum speed.
(5) If the current temperature is always lower than (Target Temperature X － Temperature Tolerance),
the fan speed decreases slowly to zero or to a specified stop value. The stop value is enabled by
register Bank0, 12h, bit 4 and the stop value is specified in Bank0, Index 09h. The fan remains at
the stop value for the period of time defined in Bank0, Index 0Dh.
The following tables show the current temperature, fan output value and the relative control registers
at SMART FANTM III mode.
Table 7-9 Display Register – at SMART FANTMIII Mode
REGISTER
ADDRESS
DESCRIPTION
REGISTER NAME
ATTRIBUTE
BIT DATA
Bank1, Index
50h ,51h
Current CPU
Temperature
CPUTIN Temperature
Sensor
8 MSB, 1°C bit 7,
0.5 °C
Read only
Current
CPUFANOUT
Output Value
Bank0, Index
03h
CPUFANOUT Output
Value Select
80h / FFh by
strapping
Bits 7-0
CPUFANOUT Value
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W83627UHG
Table 7-10 Relative Register – at SMART FANTM III Control Mode
STOP
VALUE
(MIN. FAN
OUTPUT)
SMART FANTM III
MODE
TARGET
TEMPERATURE
MAX. FAN
OUTPUT
STOP
TIME
TOLERANCE
Bank0, Index
06h
Bank0, Index
07h, bit 4-7
Bank0,
Index 09h
Bank0, Index
67h
Bank0,
Index 0Dh
CPUFANOUT
KEEP MIN.
FAN
SMART FANTM III
MODE
STEP DOWN
TIME
STEP UP
TIME
OUTPUT STEP
OUTPUT
VALUE
Bank0, Index
68h
Bank0, Index
0Fh
Bank0,
Index 0Eh
Bank0, Index
12h, bit 4
CPUFANOUT
7.7 Interrupt Detection
7.7.1
SMI# Interrupt Mode
The SMI#/OVT# pin (pin 95) is a multi-function pin. It can be in SMI# mode or in OVT# mode by
setting Configuration Register CR[29h], bit 6 to one or zero, respectively. In SMI# mode, it can monitor
voltages, fan counts, or temperatures.
7.7.1.1
Voltage SMI# Mode
The SMI# pin can create an interrupt if a voltage exceeds a specified high limit or falls below a
specified low limit. This interrupt must be reset by reading all the interrupt status registers, or
subsequent events do not generate interrupts. This mode is illustrated in the following figure.
High limit
Fan Count limit
Low limit
SMI#
SMI#
*
*
*
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 7-17 SMI Mode of Voltage and Fan Inputs
Publication Release Date: May 25, 2007
Revision 1.0
-49-
W83627UHG
7.7.1.2
Fan SMI# Mode
The SMI# pin can create an interrupt if a fan count crosses a specified fan limit (rises above it or falls
below it). This interrupt must be reset by reading all the interrupt status registers, or subsequent
events do not generate interrupts. This mode is illustrated in the figure above.
7.7.1.3
Temperature SMI# Mode
The SMI# pin can create interrupts that depend on the temperatures measured by SYSTIN and
CPUTIN. These interrupts are divided into two parts, one for SYSTIN and the other for CPUTIN.
7.7.1.3.1
Temperature Sensor 1(SYSTIN) SMI# Interrupt
The SMI# pin has three interrupt modes with SYSTIN.
(1) Comparator Interrupt Mode
This mode is enabled by setting THYST (Temperature Hysteresis) to 127°C.
In this mode, the SMI# pin can create an interrupt as long as the current temperature exceeds TO
(Over Temperature). This interrupt can be reset by reading all the interrupt status registers, or
subsequent events do not generate interrupts. If the interrupt is reset, the SMI# pin continues to
create interrupts until the temperature goes below TO. This is illustrated in the figure below.
T
HYST
127'C
T
OI
T
OI
T
HYST
SMI#
SMI#
*
*
*
*
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 7-18 SMI Mode of SYSTIN I
(2) Two-Times Interrupt Mode
This mode is enabled by setting THYST (Temperature Hysteresis) lower than TO and setting Bank0
Index 4Ch, bit 5 to zero.
In this mode, the SMI# pin can create an interrupt when the current temperature rises above TO or
when the current temperature falls below THYST. Once the temperature rises above TO, however,
and generates an interrupt, this mode does not generate additional interrupts, even if the
temperature remains above TO, until the temperature falls below THYST. This interrupt must be
reset by reading all the interrupt status registers, or subsequent events do not generate interrupts.
This is illustrated in the figure above.
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W83627UHG
(3) One-Time Interrupt Mode
This mode is enabled by setting THYST (Temperature Hysteresis) lower than TO and setting Bank0
Index 4Ch, bit 5 to one.
In this mode, the SMI# pin can create an interrupt when the current temperature rises above TO.
Once the temperature rises above TO, however, and generates an interrupt, this mode does not
generate additional interrupts, even if the temperature remains above TO, until the temperature
falls below THYST. This interrupt must be reset by reading all the interrupt status registers, or
subsequent events do not generate interrupts. This is illustrated in the following figure.
T
OI
T
HYST
SMI#
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 7-19 SMI Mode of SYSTIN II
7.7.1.3.2
Temperature Sensor 2(CPUTIN) SMI# Interrupt
The SMI# pin has two interrupt modes with CPUTIN.
(1) Comparator Interrupt Mode
This mode is enabled by setting Bank0 Index 4Ch, bit 6, to one.
In this mode, the SMI# pin can create an interrupt when the current temperature exceeds TO
(Over Temperature) and continues to create interrupts until the temperature falls below THYST
.
This interrupt can be reset by reading all the interrupt status registers, or subsequent events do
not generate interrupts. This is illustrated in the figure below.
Publication Release Date: May 25, 2007
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Revision 1.0
W83627UHG
T
OI
T
OI
T
HYST
T
HYST
SMI#
SMI#
*
*
*
*
*
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 7-20 SMI Mode of CPUTIN
(2) Two-Times Interrupt Mode
This mode is enabled by setting Bank0 Index 4Ch, bit 6, to zero.
In this mode, the SMI# pin can create an interrupt when the current temperature rises above TO
or when the current temperature falls below THYST. Once the temperature rises above TO,
however, and generates an interrupt, this mode does not generate additional interrupts, even if
the temperature remains above TO, until the temperature falls below THYST. This interrupt must be
reset by reading all the interrupt status registers, or subsequent events do not generate interrupts.
This is illustrated in the figure above.
7.7.2
OVT# Interrupt Mode
The SMI#/OVT# pin is a multi-function pin. It can be in SMI# mode or in OVT# mode by setting
Configuration Register CR[29h], bit 6 to one or zero, respectively. In OVT# mode, it can monitor
temperatures, and it is enabled or disabled for SYSTIN and CPUTIN by Bank0 Index 18h, bit 6; and
Bank0, Index 4Ch, bit 3.
The OVT# pin has two interrupt modes, comparator and interrupt. The modes are illustrated in this
figure.
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W83627UHG
To
T
HYST
OVT#
(Comparator Mode; default)
OVT#
(Interrupt Mode)
*
*
*
*Interrupt Reset when Temperature sensor registers are read
Figure 7-21 OVT# Modes of Temperature Inputs
If Bank0, Index 18h, bit 6, and Bank2 Index 52h, bit1 are set to zero, the OVT# pin is in comparator
mode. In comparator mode, the OVT# pin can create an interrupt once the current temperature
exceeds TO and continues to create interrupts until the temperature falls below THYST. The OVT# pin is
asserted once the temperature has exceeded TO and has not yet fallen below THYST
.
If Bank0, Index 18h, bit 6, and Bank2 Index 52h, bit1 are set to one, the OVT# pin is in interrupt mode.
In interrupt mode, the OVT# pin can create an interrupt once the current temperature rises above TO
or when the temperature falls below THYST. Once the temperature rises above TO, however, and
generates an interrupt, this mode does not generate additional interrupts, even if the temperature
remains above TO, until the temperature falls below THYST. This interrupt must be reset by reading all
the interrupt status registers. The OVT# pin is asserted when an interrupt is generated and remains
asserted until the interrupt is reset.
7.7.3
Caseopen Detection
The purpose of Caseopen function is used to detect whether the computer case has been opened and
possibly tampered with. This feature must function even when there is no 5VSB power. Consequently,
the power source for the circuit is from either Pin 74 (VBAT) or Pin 61 (5VSB). 5VSB is the default
power source. If there is no 5VSB power, the power source is VBAT. This is designed to save power
consumption of the battery.
When the case is closed, CASEOPEN# (Pin 76) must be pulled high by an external 2MΩ resistor that
is connected to VBAT (Pin 74). When the case is opened, CASEOPEN# will be switched from high to
low. Meanwhile, the detection circuit inside the IC latches the signal. As a result, the interrupt status
and the real-time status can be read at the registers next time when the computer is powered. The
status will not be cleared unless Bank 0, Index 46h, bit 7, or CR[E6h] bit 5 at Logical Device A is set to
“1” first and this bit is self-cleared to “0”.
Publication Release Date: May 25, 2007
-53-
Revision 1.0
W83627UHG
CASEOPEN#
CASEOPEN
CLEAR
CASEOPEN
STATUS
Figure 7-22 Caseopen Mechanism
7.7.4
BEEP Alarm Function
The W83627UHG provides an alarm output function at the BEEP/GP21 pin. The BEEP/GP21 pin is a
multi-function pin and can be configured as BEEP output, if Logical Device B, CR[F2h], bit 1 is set to
zero.
The BEEP outputs a warning tone when one of the monitored parameters in the following events is out
of the preset range.
z
Any voltage input of the eight pins (CPUVCORE, VIN[0..2], 5VCC, AVCC , 5VSB and VBAT) is
out of the allowed range;
z
z
z
z
Any temperature input of the three pins (SYSTIN and CPUTIN) exceeds the limit;
Any fan input of the two pins (SYSFANIN and CPUFANIN) exceeds the limit;
CASEOPEN# input pin is sampled low;
User-defined bit (Bank 4, Index 53h, bit 5) is written to 1.
The BEEP alarm function is enabled or disabled by the control bit at Hardware Monitor Device, Bank 0,
Index 57h, bit 7. Also, each event has their individual enable bit at Hardware Monitor Device, Bank 0,
Index 56h bit[7:0], Index 57h bit[6:0] and Bank 4, Index 53h, bit[1:0].
BEEP/GP21 is an open-drain output pin and its default state is low. When the BEEP alarm function is
activated, this pin repeatedly outputs 600 Hz square wave for 0.5 second and 1.2 KHz square wave
for 0.5 second in turn until the enable bit or the abnormal event is cleared.
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W83627UHG
8. HARDWARE MONITOR REGISTER SET
The base address of the Address Port and Data Port is specified in registers CR[60h] and CR[61h] of
Logical Device B, the hardware monitor device. CR[60h] is the high byte, and CR[61h] is the low byte.
The Address Port and Data Port are located at the base address, plus 5h and 6h, respectively. For
example, if CR[60h] is 02h and CR[61h] is 90h, the Address Port is at 0x295h, and the Data Port is at
0x296h.
Remember that this access is from the host CPU I/O address range. To conserve space in the
crowded CPU I/O addresses, many of the hardware monitor registers are “banked” with the bank
number located at Index 4Eh. Indexes from 000h to 04Fh are “global” or accessible from all banks,
while indexes 050h to 0FFh are specific to each bank.
8.1 Address Port (Port x5h)
Attribute:
Size:
Bit 6:0 Read/Write , Bit 7: Reserved
8 bits
BIT
7
0
6
0
5
4
3
2
0
1
0
0
0
DATA
NAME
DEFAULT
0
0
0
BIT
7
DESCRIPTION
RESERVED.
6-0
READ/WRITE.
BIT
7
6
5
4
3
2
1
0
ADDRESS
DEFAULT
Reserved
0
A6
A5
A4
A3
A2
A1
A0
00h (Address Pointer)
8.2 Data Port (Port x6h)
Attribute:
Size:
Read/Write
8 bits
BIT
7
0
6
0
5
4
0
3
0
2
0
1
0
0
0
DATA
NAME
DEFAULT
0
BIT
DESCRIPTION
Data to be read from or to be written to Value RAM and Register.
7-0
Publication Release Date: May 25, 2007
Revision 1.0
-55-
W83627UHG
8.3 SYSFANOUT PWM Output Frequency Configuration Register - Index 00h
(Bank 0)
Attribute:
Size:
BIT
Read/Write
8 bits
7
6
5
0
4
0
3
2
1
1
0
0
0
PWM_CLK_SEL1
PWM_SCALE1
NAME
DEFAULT
0
0
0
The register is meaningful only when SYSFANOUT is programmed for PWM output (i.e., Bank0 Index
04h, bit 0 is 0).
BIT
DESCRIPTION
7
PWM_CLK_SEL1 (SYSFANOUT PWM Input Clock Source Select). This bit selects
clock source for PWM output frequency.
0: The clock source is 24 MHz.
1: The clock source is 180 KHz.
6-0
PWM_SCALE1 (SYSFANOUT PWM Pre-Scale Divider). The clock source for PWM
output is divided by this seven-bit value to calculate the actual PWM output frequency.
Input Clock
1
PWM output frequency =
∗
Pre_Scale Divider 256
The maximum value of the divider is 127 (7Fh), and it should not be set to 0.
8.4 SYSFANOUT Output Value Select Register - Index 01h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
3
2
1
0
SYSFANOUT Value
NAME
DEFAULT
Strap by FAN_SET (Pin 119)
FUNCTION MODE
7
6
5
4
3
2
1
0
PWM Output
(Bank 0, Index
04h, bit 0 is 0)
The PWM duty cycle is equal to this 8-bit value, divided by
255, times 100%. FFh creates a duty cycle of 100%, and 00h
creates a duty cycle of 0%.
DESCRIPTION
DEFAULT
Strap by FAN_SET (Pin 119)
DC Voltage Output
(Bank 0, Index
04h, bit 0 is 1)
SYSFANOUT voltage control. The output
voltage is calculated according to this
equation:
DESCRIPTION
DEFAULT
Reserved
FANOUT
OUTPUT Voltage = AVCC *
64
Strap by FAN_SET (Pin 119)
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W83627UHG
8.5 CPUFANOUT PWM Output Frequency Configuration Register - Index 02h
(Bank 0)
Attribute:
Size:
BIT
Read/Write
8 bits
7
6
5
0
4
0
3
2
1
1
0
0
0
PWM_CLK_SEL2
PWM_SCALE2
NAME
DEFAULT
0
0
0
The register is meaningful only when CPUFANOUT is programmed for PWM output.
BIT
DESCRIPTION
7
PWM_CLK_SEL2 (CPUFANOUT PWM Input Clock Source Select). This bit selects the
clock source for PWM output.
0: The clock source is 24 MHz.
1: The clock source is 180 KHz.
6-0
PWM_SCALE2 (CPUFANOUT PWM Pre-Scale Divider). The clock source for PWM
output is divided by this seven-bit value to calculate the actual PWM output frequency.
Input Clock
1
PWM output frequency =
∗
Pre_Scale Divider 256
The maximum value of the divider is 127 (7Fh), and it should not be set to 0.
8.6 CPUFANOUT Output Value Select Register - Index 03h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
3
2
1
0
CPUFANOUT0 Value
NAME
DEFAULT
Strap by FAN_SET (Pin 119)
FUNCTION MODE
7
6
5
4
3
2
1
0
PWM Output
(Bank 0, Index
04h, bit 1 is 0)
CPUFANOUT PWM Duty. The PWM duty cycle is equal to this
8-bit value, divided by 255, times 100%. FFh creates a duty
cycle of 100%, and creates a duty cycle of 0%.
DESCRIPTION
DEFAULT
Strap by FAN_SET (Pin 119)
DC Voltage
Output (Bank 0,
Index 04h, bit 1 is
1)
CPUFANOUT Voltage Control. The output
voltage is calculated according to this equation:
DESCRIPTION
Reserved
FANOUT
OUTPUT Voltage = AVCC *
64
DEFAULT
Strap by FAN_SET (Pin 119)
Publication Release Date: May 25, 2007
-57-
Revision 1.0
W83627UHG
8.7 FAN Configuration Register I - Index 04h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
3
2
1
0
RESERVED
CPUFANOUT_MODE SYSFAMOUT_MODE CPUFANOUT_SEL SYSFANOUT_SEL
NAME
DEFAULT
0
0
0
0
0
0
0
1
BIT
7-6
5-4
DESCRIPTION
RESERVED.
CPUFANOUT_MODE. CPUFANOUT mode control.
Bits
5 4
0 0: CPUFANOUT is in Manual Mode. (Default)
0 1: CPUFANOUT is in Thermal CruiseTM Mode.
1 0: CPUFANOUT is in Fan Speed CruiseTM Mode.
1 1: CPUFANOUT is in SMARTFANTM III Mode.
3-2
SYSFANOUT_MODE. SYSFANOUT mode control.
Bits
3 2
0 0: SYSFANOUT is as Manual Mode. (Default)
0 1: SYSFANOUT is as Thermal CruiseTM Mode.
1 0: SYSFANOUT is as Fan Speed CruiseTM Mode.
1 1: Reserved and no function.
1
0
CPUFANOUT_SEL. CPUFANOUT output selection.
0: CPUFANOUT pin produces a PWM output duty cycle. (Default)
1: CPUFANOUT pin produces DC output.
SYSFANOUT_SEL. SYSFANOUT output mode selection.
0: SYSFANOUT pin produces a PWM duty cycle output.
1: SYSFANOUT pin produces a DC output. (Default)
8.8 SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register -
Index 05h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
FUNCTION MODE
Thermal CruiseTM
7
6
5
4
3
2
0
0
1
0
0
0
0
0
DESCRIPTION
DEFAULT
Reserved SYSTIN Target Temperature
0
0
0
0
0
DESCRIPTION
DEFAULT
Fan Speed
CruiseTM
SYSFANIN Target Speed
0
0
0
0
0
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W83627UHG
8.9 CPUTIN Target Temperature Register/ CPUFANIN Target Speed Register -
Index 06h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
0
6
0
5
4
3
2
1
0
0
0
CPUTIN Target Temperature / CPUFANIN Target Speed
NAME
DEFAULT
0
0
0
0
FUNCTION MODE
7
6
5
4
3
2
1
0
Thermal CruiseTM
or SMART FANTM
III
Reserved CPUTIN Target Temperature
DESCRIPTION
DEFAULT
0
0
0
0
0
0
0
0
0
0
0
0
0
Fan Speed
CruiseTM
CPUFANIN Target Speed
DESCRIPTION
DEFAULT
0
0
0
8.10 Tolerance of Target Temperature or Target Speed Register - Index 07h (Bank
0)
Attribute:
Size:
Read/Write
8 bits
FUNCTION MODE
7
6
5
4
3
2
1
0
Thermal CruiseTM
or SMART FANTM
III
Tolerance of CPUTIN Target Tolerance of SYSTIN Target
Temperature Temperature
DESCRIPTION
DEFAULT
0
0
0
0
0
0
0
0
Fan Speed
CruiseTM
Tolerance of CPUFANIN Tolerance of SYSFANIN
Target Speed Target Speed
DESCRIPTION
DEFAULT
0
0
0
0
0
0
0
0
8.11 SYSFANOUT Stop Value Register - Index 08h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
0
6
0
5
4
3
2
0
1
0
0
1
SYSFANOUT Stop Value
NAME
DEFAULT
0
0
0
Publication Release Date: May 25, 2007
Revision 1.0
-59-
W83627UHG
In Thermal CruiseTM mode, the SYSFANOUT value decreases to this eight-bit value if the temperature
stays below the lowest temperature limit. This value should not be zero.
Please note that Stop Value does not mean that fan really stops. It means that if the temperature
keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimum
value, and this is Stop Value.
8.12 CPUFANOUT Stop Value Register - Index 09h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
0
6
0
5
4
3
2
0
1
0
0
1
CPUFANOUT Stop Value
NAME
DEFAULT
0
0
0
InThermal CruiseTM mode or SMART FANTM III mode, the CPUFANOUT value decreases to this eight-
bit value if the temperature stays below the lowest temperature limit. This value should not be zero.
Please note that Stop Value does not mean that fan really stops. It means that if the temperature
keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimum
value, and this is Stop Value.
8.13 SYSFANOUT Start-up Value Register - Index 0Ah (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
0
6
0
5
4
3
2
0
1
0
0
1
SYSFANOUT Start-up Value
NAME
DEFAULT
0
0
0
In Thermal CruiseTM mode, SYSFANOUT value increases from zero to this eight-bit register value to
provide a minimum value to turn on the fan.
8.14 CPUFANOUT Start-up Value Register - Index 0Bh (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
0
6
0
5
4
3
2
0
1
0
0
1
CPUFANOUT Start-up Value
NAME
DEFAULT
0
0
0
In Thermal Cruise TM mode, CPUFANOUT value increases from zero to this eight-bit register value to
provide a minimum value to turn on the fan.
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W83627UHG
8.15 SYSFANOUT Stop Time Register - Index 0Ch (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
0
6
0
5
4
3
2
1
1
0
0
0
SYSFANOUT Stop Time
NAME
DEFAULT
1
1
1
In Thermal Cruise TM mode, if the stop value is enabled, this register determines the amount of time it
takes the SYSFANOUT value to fall from the stop value to zero.
(1)For PWM output:
The units are intervals of 0.1 seconds. The default time is 6 seconds.
(2)For DC output:
The units are intervals of 0.4 seconds. The default time is 24 seconds.
8.16 CPUFANOUT Stop Time Register - Index 0Dh (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
0
6
0
5
4
3
2
1
1
0
0
0
CPUFANOUT Stop Time
NAME
DEFAULT
1
1
1
In Thermal CruiseTM mode or SMART FANTM III mode, this register determines the amount of time it
takes the CPUFANOUT value to fall from the stop value to zero.
(1)For PWM output:
The units are intervals of 0.1 seconds. The default time is 6 seconds.
(2)For DC output:
The units are intervals of 0.4 seconds. The default time is 24 seconds.
8.17 Fan Output Step Down Time Register - Index 0Eh (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
0
6
0
5
4
3
2
0
1
1
0
0
FANOUT Value Step Down Time
NAME
DEFAULT
0
0
1
Publication Release Date: May 25, 2007
Revision 1.0
-61-
W83627UHG
In SMART FANTM mode, this register determines the amount of time it takes FANOUT to decrease its
value by one step.
(1)For PWM output:
The units are intervals of 0.1 seconds. The default time is 1 seconds.
(2)For DC output:
The units are intervals of 0.4 seconds. The default time is 4 seconds.
8.18 Fan Output Step Up Time Register - Index 0Fh (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
0
6
0
5
4
3
2
0
1
1
0
0
FANOUT Value Step Up Time
NAME
DEFAULT
0
0
1
In SMART FANTM mode, this register determines the amount of time it takes FANOUT to increase its
value by one step.
(1)For PWM output:
The units are intervals of 0.1 second. The default time is 1 seconds.
(2)For DC output:
The units are intervals of 0.4 second. The default time is 4 seconds.
8.19 Reserved Registers - Index 10h (Bank 0)
8.20 Reserved Registers - Index 11h (Bank 0)
8.21 FAN Configuration Register II - Index 12h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
3
0
2
1
0
0
RESERVED.
SYSFANOUT_MIN_VALUE CPUFANOUT_MIN_VALUE
RESERVED
NAME
DEFAULT
0
0
0
0
0
0
BIT
7-6
5
DESCRIPTION
RESERVED.
SYSFANOUT_MIN_VALUE.
0: SYSFANOUT value decreases to zero when the temperature goes below the target
range.
1: SYSFANOUT value decreases to the value specified in Index 08h when the
temperature goes below the target range.
-62-
W83627UHG
Continued
BIT
DESCRIPTION
4
CPUFANOUT_MIN_VALUE.
0: CPUFANOUT value decreases to zero when the temperature goes below the target
range.
1: CPUFANOUT value decreases to the value specified in Index 09h when the
temperature goes below the target range.
3-0
RESERVED.
8.22 Reserved Registers - Index 13h (Bank 0)
8.23 Reserved Registers - Index 14h (Bank 0)
8.24 Reserved Registers - Index 15h (Bank 0)
8.25 Reserved Registers - Index 16h (Bank 0)
8.26 Reserved Registers - Index 17h (Bank 0)
8.27 OVT# Configuration Register - Index 18h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
3
0
2
0
1
0
1
RESERVED DIS_OVT1 RESERVED OVT1_MODE
RESERVED
NAME
DEFAULT
0
1
0
0
1
BIT
7
DESCRIPTION
RESERVED.
DIS_OVT1.
6
0: Enable SYSTIN OVT# output.
1: Disable temperature sensor SYSTIN over-temperature (OVT#) output.
5
4
RESERVED.
OVT1_MODE.
0: Compare Mode. (Default)
1: Interrupt Mode.
3-0
RESERVED.
Publication Release Date: May 25, 2007
Revision 1.0
-63-
W83627UHG
8.28 Reserved Registers - Index 19h ~ 1Fh (Bank 0)
8.29 Value RAM ⎯ Index 20h ~ 3Fh (Bank 0)
ADDRESS A6-A0
DESCRIPTION
20h
21h
22h
23h
24h
25h
26h
27h
CPUVCORE reading
VIN0 reading
AVCC reading
5VCC reading
VIN1 reading
VIN2 reading
Reserved
SYSTIN temperature sensor reading
SYSFANIN reading
28h
29h
Note: This location stores the number of counts of the internal clock per
revolution.
CPUFANIN reading
Note: This location stores the number of counts of the internal clock per
revolution.
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
Reserved
CPUVCORE High Limit
CPUVCORE Low Limit
VIN0 High Limit
VIN0 Low Limit
AVCC High Limit
AVCC Low Limit
5VCC High Limit
5VCC Low Limit
VIN1 High Limit
VIN1 Low Limit
VIN2 High Limit
VIN2 Low Limit
Reserved
Reserved
SYSTIN temperature sensor High Limit
-64-
W83627UHG
Value RAM ⎯ Index 20h ~ 3Fh (Bank 0), continued
ADDRESS A6-A0
DESCRIPTION
3Ah
SYSTIN temperature sensor Hysteresis Limit
SYSFANIN Fan Count Limit
3Bh
Note: It is the number of counts of the internal clock for the Low Limit of
the fan speed.
CPUFANIN Fan Count Limit
3Ch
Note: It is the number of counts of the internal clock for the Low Limit of
the fan speed.
3Dh
3Eh
3Fh
Reserved
Reserved
Reserved
8.30 Configuration Register - Index 40h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
0
5
4
0
3
2
1
0
INITIALIZATION
RESERVED
INT_CLEAR RESERVED SMI#ENABLE
START
NAME
DEFAULT
0
0
0
0
1
1
BIT
DESCRIPTION
7
INITIALIZATION. A one restores the power-on default values to some registers. This bit
clears itself since the power-on default value of this bit is zero.
6-4
3
RESERVED.
INT_CLEAR. A one disables the SMI# output without affecting the contents of Interrupt
Status Registers. The device will stop monitoring. It will resume upon clearing of this bit.
2
1
0
RESERVED.
SMI#ENABLE. A one enables the SMI# Interrupt output.
START. A one enables startup of monitoring operations. A zero puts the part in standby
mode.
Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an
interrupt has occurred unlike "INT_Clear'' bit.
Publication Release Date: May 25, 2007
-65-
Revision 1.0
W83627UHG
8.31 Interrupt Status Register 1 - Index 41h (Bank 0)
Attribute:
Size:
Read Only
8 bits
BIT
7
6
5
4
3
2
1
0
CPUFANIN SYSFANIN
CPUTIN
SYSTIN
5VCC
AVCC
VIN0
CPUVCORE
NAME
DEFAULT
0
0
0
0
0
0
0
0
BIT
7
DESCRIPTION
CPUFANIN. A one indicates that the fan count limit of CPUFANIN has been exceeded.
SYSFANIN. A one indicates the fan count limit of SYSFANIN has been exceeded.
CPUTIN. A one indicates the high limit of CPUTIN temperature has been exceeded.
SYSTIN. A one indicates the high limit of SYSTIN temperature has been exceeded.
5VCC. A one indicates the high or low limit of 5VCC has been exceeded.
6
5
4
3
2
AVCC (PIN 97). A one indicates the high or low limit of AVCC has been exceeded.
VIN0. A one indicates the high or low limit of VIN0 has been exceeded.
1
0
CPUVCORE. A one indicates the high or low limit of CPUVCORE has been exceeded.
8.32 Interrupt Status Register 2 - Index 42h (Bank 0)
Attribute:
Size:
Read Only
8 bits
BIT
7
6
5
4
3
2
1
0
TAR2
TAR1
RESERVED CASEOPEN RESERVED
VIN2
RESERVED
VIN1
NAME
DEFAULT
0
0
0
0
0
0
0
0
BIT
DESCRIPTION
7
TAR2. A one indicates that the CPUTIN temperature has been over the target
temperature for three minutes at full fan speed in the Thermal CruiseTM mode.
6
TAR1. A one indicates that the SYSTIN temperature has been over the target
temperature for three minutes at full fan speed in the Thermal CruiseTM mode.
5
4
3
2
1
0
RESERVED.
CASEOPEN. A one indicates that the case has been opened.
RESERVED.
VIN2. A one indicates the high or low limit of VIN2 has been exceeded.
RESERVED.
VIN1. A one indicates the high or low limit of VIN1 has been exceeded.
-66-
W83627UHG
8.33 SMI# Mask Register 1 - Index 43h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
3
2
1
0
AVCC
(PIN 97)
CPUFANIN SYSFANIN
CPUTIN
SYSTIN
5VCC
VIN0
CPUVCORE
NAME
DEFAULT
1
1
0
1
1
1
1
0
BIT
7
DESCRIPTION
CPUFANIN.
SYSFANIN.
CPUTIN.
6
5
A one disables the corresponding interrupt
4
SYSTIN.
status bit for the SMI interrupt. (See
Interrupt Status Register 1 – Index 41h
(Bank 0)).
3
5VCC.
2
AVCC (PIN 97).
VIN0.
1
0
CPUVCORE.
8.34 SMI# Mask Register 2 - Index 44h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
3
2
1
1
0
TAR1
TAR2
RESERVED CASEOPEN
RESERVED
VIN2
VIN1
NAME
DEFAULT
1
1
1
1
1
1
1
BIT
7
DESCRIPTION
TAR2
6
TAR1
A one disables the corresponding interrupt
5
RESERVED
CASEOPEN
RESERVED
VIN2
status bit for the SMI interrupt. (Please see
Interrupt Status Register 2 – Index 42h
(Bank 0)).
4
3-2
1
0
VIN1
Publication Release Date: May 25, 2007
Revision 1.0
-67-
W83627UHG
8.35 Reserved Register - Index 45h (Bank 0)
8.36 SMI# Mask Register 3 - Index 46h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
0
5
0
4
0
3
2
0
1
0
0
0
CASEOPEN
CLEAR
RESERVED
NAME
DEFAULT
0
0
BIT
DESCRIPTION
7
CASEOPEN CLEAR. Caseopen Clear Control. Write 1 to this bit will clear CASEOPEN
status. This bit will be self-cleared after an event is cleared. The function is the same as
LDA, CR[E6h] bit 5.
6-0
RESERVED.
8.37 Fan Divisor Register I - Index 47h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
3
0
2
1
0
0
1
CPUFANIN CPUFANIN
DIV_B1
SYFANIN
DIV_B1
SYSFANIN
DIV_B0
RESERVED
NAME
DIV_B0
DEFAULT
0
1
0
1
1
BIT
7
DESCRIPTION
CPUFANIN DIV_B1 (CPUFANIN Divisor).
CPUFANIN CIV_B0 (CPUFANIN Divisor).
SYSFANIN DIV_B1 (SYSFANIN Divisor).
SYSFANIN DIV_B0 (SYSFANIN Divisor).
RESERVED.
6
Please see VBAT Monitor Control
Register – Index 5Dh (Bank 0).
5
4
3-0
8.38 Serial Bus Address Register - Index 48h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
-68-
W83627UHG
BIT
7
6
0
5
1
4
0
3
2
1
1
0
0
1
RESERVED
SERIAL BUS ADDRESS
NAME
DEFAULT
0
1
BIT
7
DESCRIPTION
RESERVED (Read Only).
Serial Bus Address <7:1>.
6-0
8.39 CPUFANOUT monitor Temperature source select register - Index 49h (Bank
0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
0
3
2
1
0
CPUFANOUT
TEMP_SEL[2] TEMP_SEL[1] TEMP_SEL[0]
CPUFANOUT
CPUFANOUT
RESERVED
NAME
DEFAULT
0
0
0
0
0
0
0
BIT
7-3
2
DESCRIPTION
RESERVED.
CPUFANOUT TEMP_SEL[2].
CPUFANOUT TEMP_SEL[1].
CPUFANOUT TEMP_SEL[0].
CPUFANOUT Temperature Source Select.
Bits
2 1 0
0 0 0: Select CPUTIN as CPUFANOUT Monitor Source.
(Default)
0 0 1: Reserved.
0 1 0: Select PECI Agent 1 as CPUFANOUT monitor
source.
0 1 1: Select PECI Agent 2 as CPUFANOUT monitor
source.
1 0 0: Select PECI Agent 3 as CPUFANOUT monitor
source.
1
0
1 0 1: Select PECI Agent 4 as CPUFANOUT monitor
source.
Publication Release Date: May 25, 2007
-69-
Revision 1.0
W83627UHG
8.40 SYSFANOUT monitor Temperature source select register - Index 4Ah (Bank
0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
3
0
2
1
0
0
0
SYSFANOUT
TEMP_SEL[2] TEMP_SEL[1] TEMP_SEL[0]
SYSFANOUT
SYSFANOUT
RESERVED
NAME
DEFAULT
0
0
0
0
0
BIT
DESCRIPTION
7
SYSFANOUT TEMP_SEL[2].
SYSFANOUT TEMP_SEL[1].
SYSFANOUT TEMP_SEL[0[.
RESERVED.
SYSFANOUT Temperature Source Select.
Bits
7 6 5
0 0 0: Select SYSTIN as SYSFANOUT monitor source.
(Default)
0 0 1: Select CPUTIN as SYSFANOUT monitor source.
0 1 0: Reserved.
0 1 1: Reserved.
1 0 0: Select PECI Agent 1 as SYSFANOUT monitor
source.
1 0 1: Select PECI Agent 2 as SYSFANOUT monitor
source.
1 1 0: Select PECI Agent 3 as SYSFANOUT monitor
source.
1 1 1: Select PECI Agent 4 as SYSFANOUT monitor
source.
6
5
4-0
8.41 Fan Divisor Register II - Index 4Bh (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
1
5
0
4
0
3
0
2
1
1
0
0
0
RESERVED
ADCOVSEL
RESERVED
NAME
DEFAULT
0
-70-
W83627UHG
BIT
7-6
5-4
DESCRIPTION
RESERVED.
ADCOVSEL (A/D Converter Clock Input Select).
Bits
5 4
0 0: ADC clock select 22.5 KHz. (Default)
0 1: ADC clock select 5.6 KHz. (22.5K/4)
1 0: ADC clock select 1.4 KHz. (22.5K/16)
1 1: ADC clock select 0.35 KHz. (22.5K/64)
3-2
1-0
RESERVED. These two bits should be set to the default value 01h.
RESERVED.
8.42 SMI#/OVT# Control Register - Index 4Ch (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
3
2
1
0
T2T3_INT
MODE
RESERVED
EN_T1_ONE RESERVED DIS_OVT2
OVTPOL
RESERVED
NAME
DEFAULT
0
0
0
1
0
0
0
0
BIT
7
DESCRIPTION
RESERVED.
6
T2T3_INT MODE.
1: SMI# output type of Temperature CPUTIN is in Comparator Interrupt mode.
0: SMI# output type is in Two-time Interrupt mode. (Default)
5
EN_T1_ONE.
1: SMI# output type of temperature SYSTIN is One-time Interrupt mode.
0: SMI# output type is Two-time Interrupt mode.
4
3
RESERVED.
DIS_OVT2.
1: Disable temperature sensor CPUTIN over-temperature (OVT) output.
0: Enable CPUTIN OVT output through pin OVT#. (Default)
2
OVTPOL (Over-temperature polarity).
1: OVT# is active high.
0: OVT# is active low. (Default)
1-0
RESERVED.
Publication Release Date: May 25, 2007
Revision 1.0
-71-
W83627UHG
8.43 FAN IN/OUT Control Register - Index 4Dh (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
0
5
0
4
1
3
2
1
0
RESERVED
FANOPV2
FANINC2
FANOPV1
FANNC1
NAME
DEFAULT
1
0
1
0
1
BIT
7-4
3
DESCRIPTION
RESERVED.
FANOPV2 (CPUFANIN output value, only if bit 2 is set to zero).
1: Pin 112 (CPUFANIN) generates a logic-high signal.
0: Pin 112 generates a logic-low signal. (Default)
2
1
0
FANINC2 (CPUFANIN Input Control).
1: Pin 112 (CPUFANIN) acts as a FAN tachometer input. (Default)
0: Pin 112 acts as a FAN control signal, and the output value is set by bit 3.
FANOPV1 (SYSFANIN output value, only if bit 0 is set to zero).
1: Pin 113 (SYSFANIN) generates a logic-high signal.
0: Pin 113 generates a logic-low signal. (Default)
FANINC1 (SYSFANIN Input Control).
1: Pin 113 (SYSFANIN) acts as a FAN tachometer input. (Default)
0: Pin 113 acts as a FAN control signal, and the output value is set by bit 1.
8.44 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
0
5
4
0
3
0
2
1
0
HBACS
RESERVED
BANKSEL2 BANKSEL1 BANKSEL0
NAME
DEFAULT
1
0
0
0
0
BIT
DESCRIPTION
7
HBACS (High Byte Access).
1: Access Index 4Fh high-byte register. (Default)
0: Access Index 4Fh low-byte register.
6
5-4
3
RESERVED. This bit should not be set to zero.
RESERVED.
RESERVED. This bit should not be set to zero.
BANKSEL2.
2
Bank Select for Index Ports 0x50h~0x5Fh. The three-bit binary value
corresponds to the bank number. For example, “010” selects bank 2.
1
BANKSEL1.
BANKSEL0.
0
-72-
W83627UHG
8.45 Winbond Vendor ID Register - Index 4Fh (Bank 0)
Power on Default Value:
<15:0> = 5CA3h
Read Only
16 bits
Attribute:
Size:
BIT
15
0
14
1
13
12
1
11
1
10
1
9
0
8
0
VIDL
VIDH
NAME
DEFAULT
0
BIT
7
1
6
0
5
1
4
0
3
0
2
0
1
1
0
1
NAME
DEFAULT
BIT
15-8
7-0
DESCRIPTION
Vendor ID High-Byte, if Index 4Eh, bit7 is 1. Default 5Ch.
Vendor ID Low Byte, if Index 4Eh, bit 7 is 0. Default A3h.
8.46 Reserved Register - Index 50h ~ 55h (Bank 0)
8.47 BEEP Control Register 1 - Index 56h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
3
2
1
0
EN_
EN_
CPUTIN
_BP
EN_
SYSTIN
_BP
EN_
5VCC
_BP
EN_
AVCC
_BP
EN_
VIN0
_BP
EN_
CPUVCORE
_BP
EN_
NAME
CPUFANIN
SYSFANIN
_BP
_BP
DEFAULT
0
0
0
0
0
0
0
0
BIT
DESCRIPTION
EN_CPUFANIN_BP. BEEP output control 1: Enable BEEP output.
7
for CPUFANIN if the monitored value
exceeds the limit.
0: Disable BEEP output. (Default)
6
5
EN_SYSFANIN_BP. BEEP output control
fro SYSFANIN if the monitored value
exceeds the limit.
EN_CPUTIN_BP. BEEP output control for
temperature CPUTIN if the monitored value
exceeds the limit.
Publication Release Date: May 25, 2007
Revision 1.0
-73-
W83627UHG
Continued
BIT
DESCRIPTION
EN_SYSTIN_BP. BEEP output control for
4
temperature SYSTIN if the monitored value
exceeds the limit.
3
2
1
0
EN_5VCC_BP. BEEP output control for
5VCC if the monitored value exceeds the
limit.
EN_AVCC_BP. BEEP output control for
AVCC if the monitored value exceeds the
limit.
EN_VIN0_BP. BEEP output control for
VIN0 if the monitored value exceeds the
limit.
EN_CPUVCORE_BP. BEEP output control
for CPUVCORE if the monitored value
exceeds the limit.
8.48 BEEP Control Register 2 - Index 57h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
3
2
1
0
EN_GBP
RESERVED
EN_CASEOPEN_BP
RESERVED
EN_VIN2_BP EN_VIN1_BP
NAME
DEFAULT
1
0
0
0
0
0
0
0
BIT
DESCRIPTION
7
EN_GBP. Global BEEP Control.
1: Enable global BEEP output. (Default)
0: Disable all BEEP output.
6-5
4
RESERVED.
EN_CASEOPEN_BP. BEEP output control for CASEOPEN if the case has been opened.
1: Enable BEEP output.
0: Disable BEEP output. (Default)
3-2
1
RESERVED.
EN_VIN2_BP. BEEP output control for VIN2 if the monitored value exceeds the limit.
1: Enable BEEP output.
0: Disable BEEP output. (Default)
0
EN_VIN1_BP. BEEP output control for VIN1 if the monitored value exceeds the limit.
1: Enable BEEP output.
0: Disable BEEP output. (Default)
-74-
W83627UHG
8.49 Chip ID - Index 58h (Bank 0)
Attribute:
Size:
Read Only
8 bits
BIT
7
6
1
5
0
4
0
3
0
2
0
1
0
0
1
CHIPID
NAME
DEFAULT
1
BIT
DESCRIPTION
Winbond Chip ID Number. Default C1h.
7-0
8.50 Diode Selection Register - Index 59h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
1
5
4
3
0
2
0
1
0
0
RESERVED
SELPIIV2
SELPIIV1
RESERVED
NAME
DEFAULT
0
1
1
0
BIT
7-6
5
DESCRIPTION
RESERVED.
SELPIIV2. Diode mode selection for temperature CPUTIN, if Index 5Dh, bit 2 is set to 1.
1: CPU-compatible thermal diode.
0: Reserved.
4
SELPIIV1. Diode mode selection for temperature SYSTIN, if Index 5Dh, bit 1 is set to 1.
1: CPU-compatible thermal diode.
0: Reserved.
3-0
RESERVED.
8.51 Reserved Register - Index 5Ah ~ 5Ch (Bank 0)
8.52 VBAT Monitor Control Register - Index 5Dh (Bank 0)
Attribute:
Size:
Read/Write
8 bits
Publication Release Date: May 25, 2007
Revision 1.0
-75-
W83627UHG
BIT
7
6
5
4
3
0
2
1
0
EN_
CPUFANIN SYSFANIN
DIV_B2
RESERVED
RESERVED
DIODES2
DIODES1
NAME
DIV_B2
VBAT_MNT
DEFAULT
0
0
0
0
1
0
0
BIT
7
DESCRIPTION
RESERVED.
6
CPUFANIN DIV_B2. CPUFANIN Divisor, bit 2.
SYSFANIN DIV_B2. SYSFANIN Divisor, bit 2.
RESERVED.
5
4-3
2
DIODES2. Sensor type selection for CPUTIN.
1: Diode sensor.
0: Thermistor sensor.
1
0
DIODES1. Sensor type selection for SYSTIN.
1: Diode sensor.
0: Thermistor sensor.
EN_VBAT_MINT.
1: Enable battery voltage monitor. When this bit changes from zero to one, it takes one
monitor cycle time to update the VBAT reading value register.
0: Disable battery voltage monitor.
Fan divisor table:
BIT 2
BIT 1
BIT 0
FAN DIVISOR
BIT 2
BIT 1
BIT 0
FAN DIVISOR
0
0
0
0
0
0
1
1
0
1
0
1
1
2
4
8
1
1
1
1
0
0
1
1
0
1
0
1
16
32
64
128
8.53 Critical Temperature enable register - Index 5Eh (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
3
RESERVED
0
2
1
0
EN_CPUFAN
OUT
CRITICAL
TEMP
EN_CPUTIN
CURRENT
MODE
EN_SYSTIN
CURRENT
MODE
EN_SYSFANOUT
CRITICAL TEMP
RESERVED
RESERVED
NAME
DEFAULT
0
0
0
0
1
0
0
-76-
W83627UHG
BIT
7-6
5
DESCRIPTION
RESERVED.
EN_CPUFANOUT CRITICAL TEMP.
1: Enable CPUFANOUT critical temperature protection.
0: Disable CPUFANOUT critical temperature protection. (Default)
4
EN_SYSFANOUT CRITICAL TEMP.
1: Enable SYSFANOUT critical temperature protection.
0: Disable SYSFANOUT critical temperature protection. (Default)
3
2
RESERVED.
EN_CPUTIN CURRENT MODE. Enable CPUTIN Current Mode.
1: Temperature sensing of CPUTIN by Current Mode. (Default)
0: Temperature sensing of CPUTIN depends on setting of Index 5Dh and 59h. (Default)
1
0
EN_SYSTIN CURRENT MODE. Enable SYSTIN Current Mode.
1: Temperature sensing of SYSTIN by Current Mode.
0: Temperature sensing of SYSTIN depends on setting of Index 5Dh and 59h. (Default)
RESERVED.
8.54 Reserved Register - Index 5Fh (Bank 0)
8.55 Reserved Registers - Index 60h (Bank 0)
8.56 Reserved Registers - Index 61h (Bank 0)
8.57 Reserved Registers - Index 62h (Bank 0)
8.58 Reserved Registers - Index 63h (Bank 0)
8.59 Reserved Registers - Index 64h (Bank 0)
8.60 Reserved Registers - Index 65h (Bank 0)
8.61 Reserved Registers - Index 66h (Bank 0)
8.62 CPUFANOUT Maximum Output Value Register - Index 67h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
4
3
2
1
0
Publication Release Date: May 25, 2007
Revision 1.0
-77-
W83627UHG
BIT
7
1
6
1
5
1
4
3
2
1
1
1
0
1
CPUFANOUT Max. Value
NAME
DEFAULT
1
1
In SMART FANTM III mode, the CPUFANOUT value increases to this value. This value cannot be zero,
and it cannot be lower than the CPUFANOUT Stop value.
8.63 CPUFANOUT Output Step Value Register - Index 68h (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
0
5
0
4
3
2
0
1
0
0
1
CPUFANOUT STEP
NAME
DEFAULT
0
0
0
In SMART FANTM III mode, the CPUFANOUT value decreases or increases by this eight-bit value,
when needed.
8.64 Reserved Registers - Index 69h (Bank 0)
8.65 Reserved Registers - Index 6Ah (Bank 0)
8.66 SYSFANOUT Critical Temperature register - Index 6Bh (Bank 0)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
1
5
4
3
2
1
1
0
1
SYSFANOUT CRITICAL TEMPERATURE
NAME
DEFAULT
1
1
1
1
1
In Thermal CruiseTM mode, when SYSFANOUT critical temperature is enabled and monitor
temperature over the critical temperature then SYSFANOUT will full drive.
8.67 CPUFANOUT Critical Temperature register - Index 6Ch (Bank 0)
Attribute:
Size:
Read/Write
8 bits
-78-
W83627UHG
BIT
7
1
6
1
5
4
3
2
1
1
0
1
CPUFANOUT CRITICAL TEMPERATURE
NAME
DEFAULT
1
1
1
1
In Thermal CruiseTM mode, when CPUFANOUT critical temperature is enabled and monitor
temperature over the critical temperature then CPUFANOUT will full drive.
8.68 Reserved Registers - Index 6Dh (Bank 0)
8.69 Reserved Registers - Index 6Eh (Bank 0)
8.70 CPUTIN/PECI Temperature (High Byte) Register - Index 50h (Bank 1)
Attribute:
Size:
Read Only
8 bits
BIT
7
6
5
4
3
2
1
0
TEMP<8:1>
NAME
BIT
DESCRIPTION
7-0
TEMP<8:1>.Temperature <8:1> of the CPUTIN/PECI sensor. The nine-bit value is in
units of 0.5°C.
( See CPUFANOUT monitor Temperature source select register – Index 49h(Bank 0) )
8.71 CPUTIN/PECI Temperature (Low Byte) Register - Index 51h (Bank 1)
Attribute:
Size:
Read Only
8 bits
BIT
7
6
5
4
3
2
1
0
TEMP<0>
RESERVED
NAME
BIT
DESCRIPTION
7
TEMP<0>. Temperature <0> of the CPUTIN/PECI sensor. The nine-bit value is in units of
0.5°C.
6-0
RESERVED.
( See CPUFANOUT monitor Temperature source select register – Index 49h(Bank 0) )
Publication Release Date: May 25, 2007
Revision 1.0
-79-
W83627UHG
8.72 CPUTIN Configuration Register - Index 52h (Bank 1)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
5
0
4
0
3
0
2
1
0
RESERVED
FAULT
RESERVED
OVTMOD
STOP
NAME
DEFAULT
0
0
0
0
0
BIT
7-5
4-3
DESCRIPTION
RESERVED. These bits should be set to 0.
FAULT. Number of faults to detect before setting OVT# output. This avoids false tripping
due to noise.
2
1
RESERVED. This bit should be set to 0.
OVTMOD. OVT# mode select.
0: Compared mode. (Default)
1: Interrupt mode.
0
STOP.
0: Monitor CPUTIN.
1: Stop monitoring CPUTIN.
8.73 CPUTIN Hysteresis (High Byte) Register - Index 53h (Bank 1)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
1
5
0
4
3
1
2
0
1
1
0
1
THYST<8:1>
NAME
DEFAULT
0
0
BIT
DESCRIPTION
THYST<8:1>. Hysteresis temperature bits 8-1. The nine-bit value is in units of 0.5°C, and
7-0
the default is 75°C.
8.74 CPUTIN Hysteresis (Low Byte) Register - Index 54h (Bank 1)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
0
5
0
4
0
3
2
0
1
0
0
0
THYST<0>
RESERVED
NAME
DEFAULT
0
0
-80-
W83627UHG
BIT
7
DESCRIPTION
THYST<0>. Hysteresis temperature bit 0. The nine-bit value is in units of 0.5°C.
6-0
RESERVED.
8.75 CPUTIN Over-temperature (High Byte) Register - Index 55h (Bank1)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
1
5
0
4
1
3
0
2
0
1
0
0
0
TOVF<8:1>
NAME
DEFAULT
0
BIT
DESCRIPTION
TOVF<8:1>. Over-temperature bits 8-1. The nine-bit value is in units of 0.5°C, and the
7-0
default is 80°C.
8.76 CPUTIN Over-temperature (Low Byte) Register - Index 56h (Bank 1)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
0
5
0
4
0
3
2
0
1
0
0
0
TOVF<0>
RESERVED
NAME
DEFAULT
0
0
BIT
7
DESCRIPTION
TOVF<0>. Over-temperature bit 0. The nine-bit value is in units of 0.5°C.
6-0
RESERVED.
8.77 SYSTIN/CPUTIN/PECI Temperature (High Byte) Register - Index 50h (Bank 2)
Attribute:
Size:
Read Only
8 bits
BIT
7
6
5
4
3
2
1
0
TEMP<8:1>
NAME
BIT
DESCRIPTION
7-0
TEMP<8:1>. Temperature <8:1> of the SYSTIN/CPUTIN/PECI sensor. The nine-bit value
is in units of 0.5°C.
( See SYSFANOUT monitor Temperature source select register – Index 4Ah(Bank 0) )
Publication Release Date: May 25, 2007
Revision 1.0
-81-
W83627UHG
8.78 SYSTIN/CPUTIN/PECI Temperature (Low Byte) Register – Index 51h (Bank 2)
Attribute:
Size:
Read Only
8 bits
BIT
7
6
5
4
3
2
1
0
TEMP<0>
RESERVED
NAME
BIT
DESCRIPTION
7
TEMP<0>. Temperature <0> of the SYSTIN/CPUTIN/PECI sensor. The nine-bit value is
in units of 0.5°C.
6-0
RESERVED.
( See SYSFANOUT monitor Temperature source select register – Index 4Ah(Bank 0) )
8.79 Reserved Registers – Index 52h (Bank 2)
8.80 Reserved Registers – Index 53h (Bank 2)
8.81 Reserved Registers – Index 54h (Bank 2)
8.82 Reserved Registers – Index 55h (Bank 2)
8.83 Reserved Registers – Index 56h (Bank 2)
8.84 Interrupt Status Register 3 – Index 50h (Bank 4)
Attribute:
Size:
Read Only
8 bits
BIT
7
6
0
5
0
4
0
3
0
2
0
1
0
RESERVED
VBAT
5VSB
NAME
DEFAULT
0
0
0
BIT
7-2
1
DESCRIPTION
RESERVED.
VBAT. A one indicates the high or low limit of VBAT has been exceeded.
5VSB. A one indicates the high or low limit of 5VSB has been exceeded.
0
-82-
W83627UHG
8.85 SMI# Mask Register 4 – Index 51h (Bank 4)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
0
5
0
4
1
3
0
2
0
1
0
RESERVED
VBAT
5VSB
NAME
DEFAULT
0
1
1
BIT
7-2
1
DESCRIPTION
RESERVED.
VBAT.
A one disables the corresponding interrupt
status bit for the SMI interrupt. (Please see
Interrupt Status Register 3 – Index 50h
(Bank 4)).
0
5VSB.
8.86 Reserved Register - Index 52h (Bank 4)
8.87 BEEP Control Register 3 - Index 53h (Bank 4)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
0
5
4
0
3
2
0
1
0
EN_
EN_
EN_
RESERVED
RESERVED
NAME
USER_BP
VBAT_BP
5VSB_BP
DEFAULT
0
0
0
0
0
BIT
7-6
5
DESCRIPTION
RESERVED.
EN_USER_BP. User-defined BEEP output function.
0: Make BEEP inactive. (Default)
1: Make BEEP active.
4-2
1
RESERVED.
EN_VBAT_BP. BEEP output control for VBAT if the monitored value exceeds the limit.
1: Enable BEEP output.
0: Disable BEEP output. (Default)
0
EN_5VSB_BP. BEEP output control for 5VSB if the monitored value exceeds the limit.
1: Enable BEEP output.
0: Disable BEEP output. (Default)
Publication Release Date: May 25, 2007
-83-
Revision 1.0
W83627UHG
8.88 SYSTIN Temperature Sensor Offset Register - Index 54h (Bank 4)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
0
5
0
4
3
0
2
0
1
0
0
0
OFFSET<7:0>
NAME
DEFAULT
0
0
BIT
DESCRIPTION
7-0
SYSTIN temperature offset value. The value in this register is added to the monitored
value so that the read value will be the sum of the monitored value and this offset value.
8.89 CPUTIN Temperature Sensor Offset Register - Index 55h (Bank 4)
Attribute:
Size:
Read/Write
8 bits
BIT
7
6
0
5
0
4
3
0
2
0
1
0
0
0
OFFSET<7:0>
NAME
DEFAULT
0
0
BIT
DESCRIPTION
7-0
CPUTIN Temperature Offset Value. The value in this register will be added to the
monitored value so that the read value is the sum of the monitored value and this offset
value.
8.90 Reserved Registers - Index 56h (Bank 4)
8.91 Reserved Register - Index 57h-58h (Bank 4)
8.92 Real Time Hardware Status Register I - Index 59h (Bank 4)
Attribute:
Size:
Read Only
8 bits
BIT
7
6
5
4
3
2
1
0
CPUFANIN SYSFANIN
CPUTIN
_STS
SYSTIN
_STS
5VCC
_STS
AVCC
_STS
VIN0
CPUVCORE
_STS
NAME
_STS
_STS
_STS
DEFAULT
0
0
0
0
0
0
0
0
-84-
W83627UHG
BIT
DESCRIPTION
7
CPUFANIN_STS. CPUFANIN status.
1: Fan speed count is over the limit value.
0: Fan speed count is in the allowed range.
6
5
4
3
2
1
0
SYSFANIN_STS.
1: Fan speed count is over the limit value.
0: Fan speed count is in the allowed range.
CPUTIN_STS.
1: Temperature exceeds the over-temperature value.
0: Temperature is under the hysteresis value.
SYSTIN_STS.
1: Temperature exceeds the over-temperature value.
0: Temperature is under the hysteresis value.
5VCC_STS.
1: 5VCC voltage is over or under the allowed range.
0: 5VCC voltage is in the allowed range.
AVCC_STS.
1: AVCC voltage is over or under the allowed range.
0: AVCC voltage is in the allowed range.
VIN0_STS.
1: VIN0 voltage is over or under the allowed range.
0: VIN0 voltage is in the allowed range.
CPUVCORE_STS.
1: CPUVCORE voltage is over or under the allowed range.
0: CPUVCORE voltage is in the allowed range.
8.93 Real Time Hardware Status Register II - Index 5Ah (Bank 4)
Attribute:
Size:
Read Only
8 bits
BIT
7
6
5
4
3
0
2
1
0
0
TAR2_STS TAR1_STS RESERVED CASEOPEN_STS
RESERVED
VIN1_STS
NAME
DEFAULT
0
0
0
0
0
0
Publication Release Date: May 25, 2007
Revision 1.0
-85-
W83627UHG
BIT
DESCRIPTION
7
TAR2_STS. Smart Fan of CPUFANIN Warning Status.
1: Selected temperature has been over the target temperature for three minutes at full
speed in Thermal CruiseTM mode.
0: Selected temperature has not reached the warning range.
6
TAR1_STS. Smart Fan of SYSFANIN Warning Status.
1: SYSTIN temperature has been over the target temperature for three minutes at full
speed in Thermal CruiseTM mode.
0: SYSTIN temperature has not reached the warning range.
5
4
RESERVED.
CASEOPEN_STS. Caseopen Status.
1: Caseopen is detected and latched.
0: Caseopen is not latched.
3-1
0
RESERVED.
VIN1_STS. VIN1 Voltage Status.
1: VIN1 voltage is over or under the allowed range.
0: VIN1 voltage is in the allowed range.
8.94 Real Time Hardware Status Register III - Index 5Bh (Bank 4)
Attribute:
Size:
Read Only
8 bits
BIT
7
6
0
5
4
0
3
2
0
1
0
RESERVED
VIN2_STS
RESERVED
VBAT_STS 5VSB_STS
NAME
DEFAULT
0
0
0
0
0
BIT
7-6
5
DESCRIPTION
RESERVED.
VIN2_STS. VIN2 Voltage Status.
1: VIN2 voltage is over or under the allowed range.
0: VIN2 voltage is in the allowed range.
4-2
1
RESERVED.
VBAT_STS. VBAT Voltage Status.
1: VBAT voltage is over or under the allowed range.
0: VBAT voltage is in the allowed range.
0
5VSB_STS. 5VSB Voltage Status.
1: 5VSB voltage is over or under the allowed range.
0: 5VSB voltage is in the allowed range.
-86-
W83627UHG
8.95 Reserved Register - Index 5Ch - 5Fh (Bank 4)
8.96 Value RAM 2 ⎯ Index 50h-59h (Bank 5)
ADDRESS A6-A0
DESCRIPTION
50h
5VSB reading
VBAT reading. The reading is meaningless unless EN_VBAT_MN (Bank0
Index 5Dh, bit0) is set.
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
Reserved
Reserved
5VSB High Limit
5VSB Low Limit
VBAT High Limit
VBAT Low Limit
Reserved
Reserved
Reserved
Reserved
Reserved
8.97 Reserved Register - Index 50h - 57h (Bank 6)
Publication Release Date: May 25, 2007
Revision 1.0
-87-
W83627UHG
9. FLOPPY DISK CONTROLLER
9.1 FDC Functional Description
The floppy disk controller (FDC) of the W83627UHG integrates all of the logic required for floppy disk
control. The FDC implements a FIFO, which provides better system performance in multi-master
systems, and the digital data separator supports data rates up to 2 M bits/sec.
The FDC includes the following blocks: Precompensation, Data Rate Selection, Digital Data Separator,
FIFO, and FDC Core. The rest of this section discusses these blocks through the following topics:
FIFO, Data Separator, Write Precompensation, Perpendicular Recording mode, FDC core, FDC
commands, and FDC registers.
9.1.1
FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM
(Request for Master) and DIO (Data Input/Output) bits in the Main Status Register.
The FIFO is defaulted to disabled mode after any form of reset, which maintains PC/AT hardware
compatibility. The default values can be changed through the configure command. The advantage of
the FIFO is that it allows a larger DMA latency in the system without causing disk errors. The following
tables give several examples of the delays with the FIFO. The data are based upon the following
formula:
DELAY = THRESHOLD # × (1 / DATA RATE) * 8 - 1.5 μs
Table 9-1 The Delays of the FIFO
FIFO THRESHOLD
MAXIMUM DELAY UNTIL SERVICING AT 500K BPS
Data Rate
1 Byte
2 Byte
8 Byte
15 Byte
1 × 16 μs - 1.5 μs = 14.5 μs
2 × 16 μs - 1.5 μs = 30.5 μs
8 × 16 μs - 1.5 μs = 6.5 μs
15 × 16 μs - 1.5 μs = 238.5 μs
MAXIMUM DELAY UNTIL SERVICING AT 1M BPS
FIFO THRESHOLD
Data Rate
1 Byte
2 Byte
8 Byte
15 Byte
1 × 8 μs - 1.5 μs = 6.5 μs
2 × 8 μs - 1.5 μs = 14.5 μs
8 × 8 μs - 1.5 μs = 62.5 μs
15 × 8 μs - 1.5 μs = 118.5 μs
At the start of a command, the FIFO is always disabled, and command parameters must be sent
based upon the RQM and DIO bit settings in the Main Status Register. When the FDC enters the
command execution phase, it clears the FIFO off any data to ensure that invalid data are not
transferred.
-88-
W83627UHG
An overrun or underrun terminates the current command and data transfer. Disk writes complete the
current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the
remaining data so that the result phase may be entered.
DMA transfers are enabled by the specify command and are initiated by the FDC when the LDRQ pin
is activated during a data transfer command.
9.2 Data Separator
The function of the data separator is to lock onto incoming serial read data. When a lock is achieved,
the serial front-end logic in the chip is provided with a clock that is synchronized with the read data.
The synchronized clock, called the Data Window, is used to internally sample the serial data portion of
the bit cell, and the alternate state samples the clock portion. Serial-to-parallel conversion logic
separates the read data into clock and data bytes.
The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking.
The control logic generates RDD and RWD for every pulse input, and any data pulse input is
synchronized and then adjusted immediately by error adjustment. A digital integrator keeps track of
the speed changes in the input data stream.
9.2.1
Write Precompensation
The write precompensation logic minimizes bit shifts in the RDDATA stream from the disk drive.
Shifting of bits is a known phenomenon in magnetic media and depends on the disk media and the
floppy drive.
The FDC monitors the bit stream that is being sent to the drive. The data patterns that require
precompensation are well known, so, depending on the pattern, the bit is shifted either early or late,
relative to the surrounding bits.
9.2.2
Perpendicular Recording Mode
The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular
recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically.
This scheme packs more data bits into the same area.
FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write
perpendicular media. Some manufacturers offer drives that can read and write standard and
perpendicular media in a perpendicular media drive.
A single command puts the FDC into perpendicular mode. All other commands operate as they
normally do. Perpendicular mode requires a 1 Mbps data rate for the FDC, and, at this data rate, the
FIFO manages the host interface bottleneck due to the high speed of data transfer to and from the
disk.
Publication Release Date: May 25, 2007
-89-
Revision 1.0
W83627UHG
9.2.3
FDC Core
The W83627UHG FDC is capable of performing twenty commands. Each command is initiated by a
multi-byte transfer from the microprocessor, and the result may be a multi-byte transfer back to the
microprocessor. Each command consists of three phases: command, execution, and result.
Command
The microprocessor issues all required information to the controller to perform a specific operation.
Execution
The controller performs the specified operation.
Result
After the operation is completed, status information and other housekeeping information are provided
to the microprocessor.
The next section introduces each of the commands.
9.2.4
FDC Commands
Command Symbol Descriptions:
C:
Cylinder Number 0 - 256
D:
Data Pattern
DIR:
Step Direction
DIR = 0: step out
DIR = 1: step in
DS0:
DS1:
DTL:
EC:
Disk Drive Select 0
Disk Drive Select 1
Data Length
Enable Count
EFIFO:
EIS:
Enable FIFO
Enable Implied Seek
EOT:
FIFOTHR:
GAP:
GPL:
H:
End of Track
FIFO Threshold
Gap Length Selection
Gap Length
Head Number
HDS:
HLT:
HUT:
LOCK:
MFM:
MT:
Head Number Select
Head Load Time
Head Unload Time
Lock EFIFO, FIFOTHR, and PTRTRK bits to prevent being affected by software reset
MFM or FM Mode
Multitrack
N:
NCN:
The number of data bytes written in a sector
New Cylinder Number
-90-
W83627UHG
ND:
Non-DMA Mode
OW:
PCN:
POLL:
PRETRK:
R:
Overwritten
Present Cylinder Number
Polling Disable
Precompensation Start Track Number
Record
RCN:
R/W:
SC:
Relative Cylinder Number
Read/Write
Sectors per Cylinder
Skip deleted data address mark
Step Rate Time
Status Register 0
Status Register 1
Status Register 2
Status Register 3
SK:
SRT:
ST0:
ST1:
ST2:
ST3:
WG:
Write gate alters timing of WE
(1) Read Data
PHASE
R/W
W
D7
D6 D5 D4
D3
0
D2 D1 D0
REMARKS
Command
MT MFM SK
0
0
1
1
0
Command codes
W
0
0
0
0
HDS DS1 DS0
W
W
---------------------- C ------------------------
---------------------- H ------------------------
Sector ID information prior
to command execution
W
W
---------------------- R ------------------------
---------------------- N ------------------------
W
W
-------------------- EOT -----------------------
-------------------- GPL -----------------------
W
-------------------- DTL -----------------------
Execution
Result
Data transfer between the
FDD and system
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
Status information after
command execution
R
R
R
R
R
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Sector ID information after
command execution
Publication Release Date: May 25, 2007
Revision 1.0
-91-
W83627UHG
(2) Read Deleted Data
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
MT MFM SK
0
0
1
0
1
0
0
Command codes
W
0
0
0
HDS DS1 DS0
W
W
---------------------- C ------------------------
---------------------- H ------------------------
Sector ID information prior
to command execution
W
W
---------------------- R ------------------------
---------------------- N ------------------------
W
W
-------------------- EOT -----------------------
-------------------- GPL -----------------------
W
-------------------- DTL -----------------------
Execution
Result
Data transfer between the
FDD and system
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
Status information after
command execution
R
R
R
R
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Sector ID information after
command execution
(3) Read A Track
D7 D6 D5 D4 D3 D2 D1 D0
PHASE
R/W
REMARKS
Command
W
W
0
0
MFM
0
0
0
0
0
0
0
0
1
0
Command codes
HDS DS1 DS0
W
W
---------------------- C ------------------------
---------------------- H ------------------------
Sector ID information prior
to command execution
W
W
---------------------- R ------------------------
---------------------- N ------------------------
W
W
-------------------- EOT -----------------------
-------------------- GPL -----------------------
W
-------------------- DTL -----------------------
Execution
Data transfer between the
FDD and system; FDD
reads contents of all
cylinders from index hole to
EOT
-92-
W83627UHG
Read A Track, continued
D7 D6 D5 D4 D3 D2 D1 D0
PHASE
Result
R/W
REMARKS
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
Status information after
command execution
R
R
R
R
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Sector ID information after
command execution
(4) Read ID
PHASE
R/W
REMARKS
D7 D6 D5 D4 D3 D2 D1 D0
Command
W
W
0
0
MFM
0
0
0
0
0
1
0
0
1
0
Command codes
HDS DS1 DS0
Execution
Result
The first correct ID
information on the cylinder
is stored in the Data
Register
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
R
R
R
R
Disk status after the
command has been
completed
(5) Verify
PHASE
R/W
REMARKS
D7 D6 D5 D4 D3 D2 D1 D0
Command
W
W
W
W
W
W
W
W
MT MFM SK
EC
1
0
0
0
1
1
0
Command codes
0
0
HDS DS1 DS0
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL/SC -------------------
Sector ID information prior
to command execution
Execution
No data transfer takes
place
Publication Release Date: May 25, 2007
Revision 1.0
-93-
W83627UHG
Verify, continued
PHASE
R/W
REMARKS
D7 D6 D5 D4 D3 D2 D1 D0
Result
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
(6) Version
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command code
Command
Result
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
R
Enhanced controller
(7) Write Data
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
MT MFM
0
0
0
0
0
0
1
0
1
Command codes
W
0
0
HDS DS1 DS0
W
W
---------------------- C ------------------------
---------------------- H ------------------------
Sector ID information prior
to Command execution
W
W
---------------------- R ------------------------
---------------------- N ------------------------
W
W
-------------------- EOT -----------------------
-------------------- GPL -----------------------
W
-------------------- DTL -----------------------
Execution
Result
Data transfer between the
FDD and system
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
Status information after
Command execution
R
R
R
R
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Sector ID information after
Command execution
-94-
W83627UHG
(8) Write Deleted Data
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
MT MFM
0
0
0
0
1
0
0
1
Command codes
W
0
0
0
HDS DS1 DS0
W
W
---------------------- C ------------------------
---------------------- H ------------------------
Sector ID information prior
to command execution
W
W
---------------------- R ------------------------
---------------------- N ------------------------
W
W
W
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Execution
Result
Data transfer between the
FDD and system
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
Status information after
command execution
R
R
R
R
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Sector ID information after
command execution
(9) Format A Track
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
0
0
MFM
0
0
0
0
0
1
0
1
0
1
Command codes
W
HDS DS1 DS0
W
W
---------------------- N ------------------------
--------------------- SC -----------------------
Bytes per Sector
Sectors per Cylinder
W
W
--------------------- GPL ---------------------
---------------------- D ------------------------
Gap 3
Filler Byte
Execution
for Each
Sector:
W
W
W
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Input Sector Parameters
(Repeat)
Publication Release Date: May 25, 2007
Revision 1.0
-95-
W83627UHG
Format A Track, continued
PHASE
Result
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
Status information after
command execution
R
R
---------------- Undefined -------------------
---------------- Undefined -------------------
---------------- Undefined -------------------
---------------- Undefined -------------------
R
R
(10) Recalibrate
PHASE
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
W
0
0
0
0
0
0
0
0
0
1
1
1
Command codes
0
0
DS1 DS0
Execution
Head retracted to Track 0
Interrupt
(11) Sense Interrupt Status
PHASE
Command
Result
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
W
0
0
0
0
1
0
0
0
Command code
R
R
---------------- ST0 -------------------------
---------------- PCN -------------------------
Status information at the end
of each seek operation
(12) Specify
PHASE
R/W
D7
D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
0
0
0
0
0
0
1
1
Command codes
W
W
| ---------SRT ----------- | --------- HUT ---------- |
|------------ HLT ----------------------------------| ND
(13) Seek
PHASE
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
0
0
0
0
0
0
0
0
1
0
1
1
1
Command codes
W
W
HDS DS1 DS0
-------------------- NCN -----------------------
Execution
R
Head positioned over proper
cylinder on diskette
(14) Configure
-96-
W83627UHG
PHASE
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
Configure information
W
W
W
0
0
EIS EFIFO POLL | ------ FIFOTHR ----|
| --------------------PRETRK ----------------------- |
Execution
Internal registers written
(15) Relative Seek
PHASE
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
1
0
DIR
0
0
0
0
0
1
0
1
1
1
Command codes
W
W
HDS DS1 DS0
| -------------------- RCN ---------------------------- |
(16) Dumpreg
PHASE
Command
Result
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
W
0
0
0
0
1
1
1
0
Registers placed in FIFO
R
R
R
R
R
R
R
R
R
R
----------------------- PCN-Drive 0--------------------
----------------------- PCN-Drive 1 -------------------
----------------------- PCN-Drive 2--------------------
----------------------- PCN-Drive 3 -------------------
--------SRT ------------------ | --------- HUT --------
----------- HLT -----------------------------------| ND
------------------------ SC/EOT ----------------------
LOCK 0 D3 D2 D1 D0 GAP WG
0 EIS EFIFO POLL | ------ FIFOTHR --------
-----------------------PRETRK -------------------------
(17) Perpendicular Mode
PHASE
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
W
0
0
0
1
0
0
1
0
Command Code
OW
0
D3
D2 D1 D0 GAP WG
(18) Lock
PHASE
Command
Result
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
LOCK 0
0
0
1
0
0
1
0
0
0
0
Command Code
R
0
0
LOCK
0
(19) Sense Drive Status
Publication Release Date: May 25, 2007
Revision 1.0
-97-
W83627UHG
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
0
0
0
0
0
0
0
0
0
1
0
0
Command Code
W
0
HDS DS1 DS0
Result
R
---------------- ST3 -------------------------
Status information about
disk drive
(20) Invalid
PHASE
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
------------- Invalid Codes -----------------
Invalid codes (no operation-
FDC goes to standby state)
Result
R
-------------------- ST0 ----------------------
ST0 = 80H
9.3 Register Descriptions
There are several status, data, and control registers in the W83627UHG. These registers are defined
below, and the rest of this section provides more detail about each one of them.
Table 9-2 FDC Registers
ADDRESS
OFFSET
REGISTER
READ
WRITE
base address + 0
base address + 1
base address + 2
base address + 3
base address + 4
base address + 5
base address + 7
SA REGISTER
SB REGISTER
DO REGISTER
TD REGISTER
TD REGISTER
MS REGISTER
DR REGISTER
DT (FIFO) REGISTER
DI REGISTER
DT (FIFO) REGISTER
CC REGISTER
9.3.1
Status Register A (SA Register) (Read base address + 0)
Along with the SB register, the SA register is used to monitor several disk-interface pins in PS/2 and
Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:
BIT
7
6
5
4
3
2
1
0
INIT
PENDING
DRV 2#
STEP
TRAK0#
HEAD
INDEX#
WP#
DIR
NAME
DEFAULT
0
0
NA
1
NA
1
1
NA
BIT
DESCRIPTION
-98-
W83627UHG
BIT
7
DESCRIPTION
INIT PENDING. Indicates the value of the floppy disk interrupt output.
6
DRV2#.
0: A second drive has been installed.
1: No second drive is installed.
5
4
3
STEP. Indicates the complement of the STEP# output.
TRAK0#. Indicates the value of the TRAK# input.
HEAD. Indicates the complement of the HEAD# output.
0: Side 0.
1: Side 1.
2
1
INDEX#. Indicates the value of the INDEX# output.
WP#.
0: The disk is write-protected.
1: The disk is not write-protected.
0
DIR. Indicates the direction of head movement.
0: Outward direction.
1: Inward direction.
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
BIT
7
6
5
4
3
2
1
0
INIT
PENDING
DRQ
STEP F/F
TRAK0
HEAD#
INDEX
WP
DIR#
NAME
DEFAULT
0
0
NA
0
NA
0
0
NA
BIT
7
DESCRIPTION
INIT PENDING. Indicates the value of the floppy disk interrupt output.
DRQ. Indicates the value of the DRQ output pin.
6
5
SETP F/F. indicates the complement of latched STEP# output.
TRAK0. Indicates the complement of the TRAK0# input.
4
3
HEAD#. Indicates the value of the HEAD# output.
0: Side 1.
1: Side 0.
2
1
INDEX. Indicates the complement of the INDEX# output.
WP.
0: The disk is not write-protected.
1: The disk is write-protected.
0
DIR#. Indicates the direction of the head movement.
0: Inward direction.
1: Outward direction.
Publication Release Date: May 25, 2007
Revision 1.0
-99-
W83627UHG
9.3.2
Status Register B (SB Register) (Read base address + 1)
Along with the SA register, the SB register is used to monitor several disk interface pins in PS/2 and
Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:
BIT
7
6
5
4
3
2
1
0
Drive
SEL0
WDTA
Toggle
RDTA
Toggle
MOT EN
B
MOT EN
A
WE
NAME
DEFAULT
1
1
0
0
0
0
0
0
BIT
DESCRIPTION
7
6
5
4
3
2
1
0
1
1
Drive SEL0. Indicates the status of the DO Register, bit 0 (drive-select bit 0).
WDATA Toggle. Changes state on every rising edge of the WD# output pin.
RDATA Toggle. Changes state on every rising edge of the RDATA# output pin.
WE. Indicates the complement of the WE# output pin.
MOT EN B. Indicates the complement of the MOB# output pin.
MOT EN A. Indicates the complement of the MOA# output pin.
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
BIT
7
6
5
4
3
2
1
0
RDATA
F/F
DRV 2#
RESERVED.
DSA#
WD F/F
WE F/F
DSD#
DSC#
NAME
DEFAULT
0
1
1
0
0
0
1
1
BIT
DESCRIPTION
7
DRV 2#.
0: A second drive has been installed.
1: No second drive is installed.
6
5
4
Reserved.
DSA#. Indicates the status of the DSA# output pin.
WD F/F. Indicates the complement of the WD# output pin, which is latched on every rising
edge of the WD# output pin.
3
2
RDATA F/F. Indicates the complement of the latched RDATA# output pin.
WE F/F. Indicates the complement of the latched WE# output pin.
Reserved.
1-0
-100-
W83627UHG
9.3.3
Digital Output Register (DO Register) (Write base address + 2)
The Digital Output Register is a write-only register that controls drive motors, drive selection,
DRQ/IRQ enable, and FDC reset. All the bits in this register are cleared by the MR pin. The bit
definitions are as follows:
BIT
7
6
5
4
3
2
1
0
MOTOR
ENABLE A
DMA&INT
ENABLE
FDC
RESET
RESERVED
DRIVE SELECT
NAME
DEFAULT
0
0
0
0
0
0
0
0
BIT
7-5
4
DESCRIPTION
Reserved.
MOTOR ENABLE A. A logical 1 enables Motor A.
DMA & INT ENABLE. A logical 1 enables DRQ/IRQ.
3
2
FDC RESET. Floppy Disk Controller Reset. A logical 0 resets the FDC.
1-0
DRIVE SELECT.
Bits
1 0
0 0: Select Drive A.
0 1: Select Drive B.
1 0: Select Drive C.
1 1: Select Drive D.
9.3.4
Tape Drive Register (TD Register) (Read base address + 3)
This register is used to assign a particular drive number to the tape drive support mode of the data
separator. This register also holds the media ID, drive type, and floppy boot drive information for the
floppy disk drive.
In normal floppy mode, this register only has bits 0 and 1, and the bit definitions are as follows:
BIT
7
6
5
4
3
2
1
0
RESERVED
Tape sel 1 Tape sel 0
NAME
DEFAULT
NA
NA
NA
NA
NA
NA
0
0
BIT
7-2
1
DESCRIPTION
RESERVED.
Tape sel 1.
Tape sel 0.
0
If the three-mode FDD function is enabled (EN3MODE = 1 in LD0 CRF0, Bit 0), the bit definitions are
as follows:
Publication Release Date: May 25, 2007
-101-
Revision 1.0
W83627UHG
BIT
7
6
5
4
3
2
1
0
Floppy
Boot
Drive 1
Floppy
Boot
Drive 0
Drive
Type ID1
Drive
Type ID0
Tape Sel
1
Tape Sel
0
Media ID1
Media ID0
NAME
DEFAULT
0
0
1
1
0
0
0
0
BIT
7
DESCRIPTION
Media ID1. Read only. Reflects the value of LD0, CRF1, bit 5.
Media ID0. Read only. Reflects the value of LD0, CRF1, bit 4.
Drive Type ID1.
6
5
Reflect the bit in LD0, CRF2. Which bit is
reflected depends on the last drive selected
in the PO register.
4
Drive Type ID0.
3
2
1
Floppy Boot Drive 1. Reflects the value of LD0, CRF1, bit 7.
Floppy Boot Drive 0. Reflects the value of LD0, CRF1, bit 6.
Tape Sel 1.
Assign a logical drive number to the tape
drive. Drive 0 is not available as a tape
drive and is reserved for the floppy disk
boot drive.
0
Tape Sel 0.
TAPE SEL 1
TAPE SEL 0
DRIVE SELECTED
0
0
1
1
0
1
0
1
None
1
2
3
9.3.5
Main Status Register (MS Register) (Read base address + 4)
The Main Status Register is used to control the flow of data between the microprocessor and the
controller. The bit definitions for this register are as follows:
BIT
7
6
5
4
3
2
1
0
Non-DMA
mode
FDD 3
Busy
FDD 2
Busy
FDD 1
Busy
FDD 0
Busy
RQM
DIO
FDC Busy
NAME
DEFAULT
0
NA
NA
NA
NA
NA
NA
NA
-102-
W83627UHG
BIT
DESCRIPTION
7
Request for Master (RQM). A high on this bit indicates Data Register is ready to send or
receive data to or from the processor.
6
5
DATA INPUT/OUTPUT (DIO). If DIO = HIGH, then the transfer is from Data Register to
the processor. If DIO = LOW, the transfer is from processor to Data Register.
Non-DMA mode. The FDC is in the non-DMA mode, this bit is set only during the
execution phase in non-DMA mode.
4
3
2
1
0
FDC Busy (CB). A read or write command is in the process when CB = HIGH.
FDD 3 Busy. (D3B = 1) FDD number 3 is in the SEEK mode.
FDD 2 Busy. (D2B = 1) FDD number 2 is in the SEEK mode.
FDD 1 Busy. (D1B = 1) FDD number 1 is in the SEEK mode.
FDD 0 Busy. (D0B = 1) FDD number 0 is in the SEEK mode.
9.3.6
Data Rate Register (DR Register) (Write base address + 4)
The Data Rate Register is used to set the transfer rate and write precompensation. However, in PC-
AT and PS/2 Model 30 and PS/2 modes, the data rate is controlled by the CC register, not by the DR
register. As a result, the real data rate is determined by the most recent write to either the DR or CC
register. The bit definitions for this register are as follows:
BIT
7
6
5
4
3
2
1
0
S/W
RESET
POWER
DOWN
PRECOMP2 PRECOMP1 PRECOMP0
DRATE1
DRATE0
NAME
DEFAULT
0
0
0
0
0
0
1
0
BIT
7
DESCRIPTION
S/W RESET. The software reset bit.
6
POWER DOWN.
0: FDC in normal mode.
1: FDC in power-down mode.
5
4
0
PRECOMP 2.
Selects the value of write precompensation.
The
following
tables
values
show
for
the
every
3
2
PRECOMP 1.
PRECOMP 0.
precompensation
combination of these bits. Please see the
tables below.
Publication Release Date: May 25, 2007
Revision 1.0
-103-
W83627UHG
Continued
BIT
DESCRIPTION
1
DRATE 1.
Select the data rate of the FDC and
reduced write-current control.
Bits
1 0
0 0: 500 KB/S (MFM), 250 KB/S (FM),
RWC# = 1
0
DRATE 0.
0 1: 300 KB/S (MFM), 150 KB/S (FM),
RWC# = 0
1 0: 250 KB/S (MFM), 125 KB/S (FM),
RWC# = 0
1 1: 1 MB/S (MFM), Illegal (FM), RWC# = 1
The 2 MB/S data rate for the tape drive is only supported by setting DRATE1 and DRATE0 to 01, as
well as setting DRT1 and DRT0 (CRF4 and CRF5 for logical device 0) to 10. Please see the functional
description of CRF4 or CRF5 and the data rate table for individual data-rate settings.
PRECOMP
PRECOMPENSATION DELAY
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
250K - 1 Mbps
2 Mbps Tape drive
Default Delays
20.8 ns
Default Delays
41.67 ns
83.34 ns
41.17 ns
125.00 ns
62.5ns
166.67 ns
83.3 ns
208.33 ns
104.2 ns
250.00 ns
125.00 ns
0.00 ns (disabled)
0.00 ns (disabled)
DATA RATE
250 KB/S
300 KB/S
500 KB/S
1 MB/S
DEFAULT PRECOMPENSATION DELAYS
125 ns
125 ns
125 ns
41.67ns
20.8 ns
2 MB/S
-104-
W83627UHG
9.3.7
FIFO Register (R/W base address + 5)
The FIFO register consists of four status registers in a stack, and only one register is presented to the
data bus at a time. The FIFO register stores data, commands, and parameters, and it provides disk-
drive status information. In addition, data bytes pass through the data register to program or obtain
results after a command. In the W83627UHG, this register is disabled after reset. The FIFO can
enable it and change its values through the configure command.
BIT
7
6
5
4
3
2
1
0
EC
Equipment
Check
SE Seek
End
NR Not
Ready
HD Head
Address
IC Interrupt Code
US1, US0 Drive Select
NAME
Status Register 0 (ST0)
BIT
DESCRIPTION
7-6
IC Interrupt Code.
Bits
7 6
0 0: Normal termination of the command.
0 1: Abnormal termination of the command.
1 0: Invalid command issue.
1 1: Abnormal termination because the ready signal from FDD changed state during
command execution.
5
4
SE (Seek End).
1: Seek end.
0: Seek error.
EC (Equipment Check).
1: When a fault signal is received from the FDD or the track.
0: Signal fails to occur after 77 step pulses.
0: No error.
3
2
NR (Not Ready).
1: Drive is not ready.
0: Drive is ready.
HD Head Address. (The current head address)
1: Head selected.
0: Head selected.
1-0
US 1, US0 Drive Select.
Bits
1 0
0 0: Drive A selected.
0 1: Drive B selected.
1 0: Drive C selected.
1 1: Drive D selected.
Publication Release Date: May 25, 2007
-105-
Revision 1.0
W83627UHG
Status Register 1 (ST1)
BIT
7
6
5
4
3
2
1
0
EN
Not Used
OE
OR
Not Used
ND
NW
MAM
NAME
BIT
DESCRIPTION
7
EN (End of Track). 1 will be written to this bit if the FDC tries to access a sector beyond
the final sector or a cylinder.
6
5
Not Used. This bit is always 0.
DE (Data Error). 1 will be written to this bit if the FDC detects a CRC error in either the ID
field or the data field.
4
OR (Over Run). 1 will be written to this bit if the FDC is not served by the host system
within a certain time interval during data transfer.
3
2
Not Used. This bit is always 0.
ND (No Data). 1 will be written to this bit if the specified sector cannot be found during
execution of a read, write or verity data.
1
0
NW (Not Writable). 1 will be written to this bit if a write protect signal is detected from the
diskette drive during execution of write data.
MAM (Missing Address Mark). 1 will be written to this bit if the FDC cannot detect the
data address mark or the data address mark has been deleted.
Status Register 2 (ST2)
BIT
7
6
5
4
3
2
1
0
CM
DD
WC
SH
SN
BC
MD
NAME
BIT
7
DESCRIPTION
Not used. This bit is always 0.
6
CM (Control Mark).
1: During execution of the read data or scan command.
0: No error.
5
DD (Data error in the Data field).
1: If the FDC detects a CRC error in the data field.
0: No error.
4
3
WC (Wrong Cylinder).
1: Indicates wrong cylinder.
SH (Scan Equal Hit).
1: During execution of the Scan command, if the equal condition is satisfied.
0: No error.
2
SN (Scan Not Satisfied).
1: During execution of the Scan command.
0: No error.
-106-
W83627UHG
BIT
DESCRIPTION
1
BC (Bad Cylinder).
1: Bad Cylinder.
0: No error.
0
MD (Missing Address Mark in Data Field).
1: If FDC cannot find a data address mark (or the address mark has been deleted) when
reading data from the media.
0: No error.
Status Register 3 (ST3)
BIT
7
6
5
4
3
2
1
0
FT
WP
RY
T0
TS
HD
US1
US0
NAME
BIT
7
DESCRIPTION
FT. Fault.
6
WP. Write protected.
RY. Ready.
5
4
T0. Track 0.
3
TS. Two-side.
2
HD. Head Address.
US1. Unit Select 1.
US0. Unit Select 0.
1
0
9.3.8
Digital Input Register (DI Register) (Read base address + 7)
The Digital Input Register is an 8-bit, read-only register used for diagnostic purposes. In PC/XT or
PC/AT mode, only bit 7 is checked by the BIOS. When the register is read, bit 7 shows the
complement of DSKCHG#, while the other bits remain in tri-state. The bit definitions are as follows:
BIT
7
6
5
4
3
2
1
0
DSKCHG
RESERVED
NAME
DEFAULT
0
NA
NA
NA
NA
NA
NA
NA
BIT
7
DESCRIPTION
DSKCHG.
6-0
RESERVED. Reserved for the hard disk controller. During a read of this register, these
bits are in tri-state.
Publication Release Date: May 25, 2007
-107-
Revision 1.0
W83627UHG
In PS/2 mode, the bit definitions are as follows:
BIT
7
6
5
4
1
3
1
2
1
0
HIGH
DENS#
DSKCHG
DRATE1
DRATE0
NAME
DEFAULT
0
1
1
1
0
1
BIT
7
DESCRIPTION
DSKCHG. Indicates the complement of the DSKCHG# input.
6-3
2
Always 1 during a read.
DRATE 1.
Select the data rate of the FDC. See DR
register bits 1 and 0 (Data Rate Register
(DR Register) (Write base address + 4)) for
how the settings correspond to individual
data rates.
1
0
DRATE 0.
HIGHDENS#.
0: 500 KB/S or 1 MB/S data rate (high-density FDD).
1: 250 KB/S or 300 KB/S data rate.
In PS/2 Model 30 mode, the bit definitions are as follows:
BIT
7
6
5
4
3
2
1
0
DSKCHG#
DMAEN
NOPREC
DRATE1
DRATE0
NAME
DEFAULT
1
0
0
0
0
0
1
0
BIT
7
DESCRIPTION
DSKCHG. Indicates the status of the DSKCHG# input.
Always 0 during a read.
6-4
3
DMAEN. Indicates the value of DO register, bit 3.
2
NOPREC. Indicates the value of the NOPREC bit in the CC REGISTER.
1
DRATE 1.
Select the data rate of the FDC. See DR
register bits 1 and 0 (Data Rate Register
(DR Register) (Write base address +4)) for
how the settings correspond to individual
data rates.
0
DRATE 0.
-108-
W83627UHG
9.3.9
Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In PC/AT and PS/2 mode, the bit definitions are as
follows:
BIT
7
6
5
4
3
2
1
0
RESERVED
DRATE1
DRATE0
NAME
DEFAULT
NA
NA
NA
NAN
NA
NA
1
0
BIT
7-2
1
DESCRIPTION
RESERVED. Should be set to 0.
DRATE 1.
Select the data rate of the FDC. See DR
register bits 1 and 0 (Data Rate Register
(DR Register) (Write base address + 4) for
how the settings correspond to individual
data rates.
0
DRATE 0.
In the PS/2 Model 30 mode, the bit definitions are as follows:
BIT
7
6
5
4
3
2
1
0
RESERVED
NOPREC
DRATE1
DRATE0
NAME
DEFAULT
NA
NA
NA
NA
NA
0
1
0
BIT
7-3
2
DESCRIPTION
RESERVED. Should be set to 0.
NOPREC. Disables the precompensation function. This bit can be set by the software.
1
DRATE1.
Select the data rate of the FDC. See DR
register bits 1 and 0 (Data Rate Register
(DR Register) (Write base address + 4)) for
0
DRATE0.
how the settings correspond to individual
data rates.
Publication Release Date: May 25, 2007
-109-
Revision 1.0
W83627UHG
10. UART PORT
10.1 Universal Asynchronous Receiver/Transmitter (UART A, B, C, D, E, F)
The UARTs are used to convert parallel data into serial format for transmission and to convert serial
data into parallel format during reception. The serial data format is a start bit, followed by five to eight
data bits, a parity bit (if programmed) and one, one-and-a-half (five-bit format only) or two stop bits.
The UARTs are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the
internal transmitter logic. Provisions are also included to use this 16x clock to drive the receiver logic.
The UARTs also support the MIDI data rate. Furthermore, the UARTs also include a complete
modem control capability and 16-byte FIFOs for reception and transmission to reduce the number of
interrupts presented to the CPU.
10.2 Register Address
10.2.1
UART Control Register (UCR) (Read/Write)
The UART Control Register defines and controls the protocol for asynchronous data communications,
including data length, stop bit, parity, and baud rate selection.
BIT
7
6
5
4
3
2
1
0
BDLAB
SSE
PBFE
EPE
PBE
MSBE
DLS1
DLS0
NAME
DEFAULT
0
0
0
0
0
0
0
0
BIT
DESCRIPTION
7
BDLAB (Baud Rate Divisor Latch Access Bit). When this bit is set to logic 1, designers
can access the divisor (in 16-bit binary format) from the divisor latches of the baud-rate
generator during a read or write operation. When this bit is set to logic 0, the Receiver
Buffer Register, the Transmitter Buffer Register, and the Interrupt Control Register can be
accessed.
6
5
SSE (Set Silence Enable). A logic 1 forces the Serial Output (SOUT) to a silent state (a
logical 0). Only IRTX is affected by this bit; the transmitter is not affected.
PBFE (Parity Bit Fixed Enable). When PBE and PBFE of UCR are both set to logic 1,
(1) if EPE is logic 1, the parity bit is logical 0 when transmitting and checking;
(2) if EPE is logic 0, the parity bit is logical 1 when transmitting and checking.
4
3
EPE (Even Parity Enable). When PBE is set to logic 1, this bit counts the number of logic
1’s in the data word bits and determines the parity bit. When this bit is set to logic 1, the
parity bit is set to logic 1 if an even number of logic 1’s are sent or checked. When the bit
is set to logic 0, the parity bit is logic 1, if an odd number of logic 1’s are sent or checked.
PBE (Parity Bit Enable). When this bit is set to logic 1, the transmitter inserts a stop bit
between the last data bit and the stop bit of the SOUT, and the receiver checks the parity
bit in the same position.
-110-
W83627UHG
Continued
BIT
DESCRIPTION
2
MSBE (Multiple Stop Bit Enable). Defines the number of stop bits in each serial
character that is transmitted or received.
(1) If MSBE is set to logic 0, one stop bit is sent and checked.
(2) If MSBE is set to logic 1 and the data length is 5 bits, one-and-a-half stop bits
are sent and checked.
(3) If MSBE is set to logic 1 and the data length is 6, 7, or 8 bits, two stop bits are
sent and checked.
1
0
DLS1 (Data Length Select Bit 1). Defines the number of data bits that are sent or
checked in each serial character.
DLS0 (Data Length Select Bit 0). Defines the number of data bits that are sent or
checked in each serial character.
DLS1
DLS0
DATA LENGTH
5 bits
0
0
1
1
0
1
0
1
6 bits
7 bits
8 bits
The following table identifies the remaining UART registers. Each one is described separately in the
following sections.
Publication Release Date: May 25, 2007
-111-
Revision 1.0
W83627UHG
Table 10-1 Register Summary for UART
Bit Number
Register Address Base
0
1
2
3
4
5
6
7
+ 0
BDLAB = 0
Receiver
Buffer
Register
RBR
TBR
RX Data
Bit 0
RX Data
Bit 1
RX Data
Bit 2
RX Data
Bit 3
RX Data
Bit 4
RX Data
Bit 5
RX Data
Bit 6
RX Data
Bit 7
(Read Only)
+ 0
BDLAB = 0
Transmitter
Buffer Register
(Write Only)
TX Data
Bit 0
TX Data
Bit 1
TX Data
Bit 2
TX Data
Bit 3
TX Data
Bit 4
TX Data
Bit 5
TX Data
Bit 6
TX Data
Bit 7
+ 1
BDLAB = 0
Interrupt Control ICR
Register
RBR Data
Ready
Interrupt
Enable
TBR
Empty
Interrupt
Enable
(ETBREI)
USR
Interrupt
Enable
HSR
Interrupt
Enable
0
0
0
0
(EUSRI)
(EHSRI)
(ERDRI)
+ 2
+ 2
Interrupt Status
Register
(Read Only)
ISR
"0" if
Interrupt
Pending
Interrupt
Status
Bit (0)
Interrupt
Status
Bit (1)
Interrupt
Status
Bit (2)**
0
0
FIFOs
Enabled
**
FIFOs
Enabled
**
UART FIFO
Control
Register
UFR
FIFO
Enable
RCVR
FIFO
Reset
XMIT
FIFO
Reset
DMA
Mode
Select
Reserved
Reversed
RX
Interrupt
Active Level Active Level
RX
Interrupt
(Write Only)
(LSB)
(MSB)
+ 3
UART Control
Register
UCR
Data
Length
Select
Bit 0
Data
Length
Select
Bit 1
Multiple
Stop Bits
Enable
Parity
Bit
Enable
Even
Parity
Enable
Parity
Bit Fixed
Enable
Set
Silence
Enable
Baudrate
Divisor
Latch
Access Bit
(BDLAB)
(MSBE)
(PBE)
(EPE)
PBFE)
(SSE)
(DLS0)
(DLS1)
+ 4
+ 5
Handshake
Control
Register
HCR
USR
HSR
Data
Terminal
Ready
(DTR)
Request
to
Send
(RTS)
Loopback
RI
Input
IRQ
Enable
Internal
Loopback
Enable
0
0
0
UART Status
Register
RBR Data
Ready
(RDR)
Overrun
Error
(OER)
Parity Bit
Error
(PBER)
No Stop
Bit
Error
Silent
Byte
Detected
(SBD)
TBR
Empty
(TBRE)
TSR
Empty
(TSRE)
RX FIFO
Error
Indication
(RFEI) **
(NSER)
+ 6
+ 7
Handshake
Status Register
CTS
Toggling
(TCTS)
DSR
Toggling
(TDSR)
RI Falling
Edge
(FERI)
DCD
Toggling
(TDCD)
Clear
to Send
(CTS)
Data Set
Ready
(DSR)
Ring
Indicator
(RI)
Data Carrier
Detect
(DCD)
User Defined
Register
UDR
BLL
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
+ 0
BDLAB = 1
Baudrate
Divisor Latch
Low
Bit 0
Bit 8
Bit 1
Bit 9
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
+ 1
BDLAB = 1
Baudrate
Divisor Latch
High
BHL
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
-112-
W83627UHG
10.2.2
UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of data transfer during communication.
BIT
7
6
5
4
3
2
1
0
RF EI
TSRE
TBRE
SBD
NSER
PBER
OER
PDR
NAME
DEFAULT
0
1
1
0
0
0
0
0
BIT
DESCRIPTION
7
RF EI (RX FIFO Error Indication). In 16450 mode, this bit is always set to logical 0. in
16550 mode, this bit is set to logical 1 when there is at least one parity-bit error and no
stop0bit error or silent-byte detected in the FIFO. In 16550 mode, this bit is cleared to
logical 0 by reading from the USR if there are no remaining errors left in the FIFO.
6
5
TSRE (Transmitter Shift Register Empty). In 16450 mode, this bit is set to logical 1
when TBR and TSR are both empty. In 16550 mode, it is set to logical 1 when the
transmit FIFO and TSR are both empty. Otherwise, this bit is set to logical 0.
TBRE (Transmitter Buffer Register Empty). In 16450 mode, when a data character is
transferred from TBR to TSR, this bit is set to logical 1. If ETREI of ICR is high, and
interrupt is generated to notify the CPU to write next data. In 16550 mode, this bit is set to
logical 1 when the transmit FIFO is empty. It is set to logical 0 when the CPU writes data
into TBR or the FIFO.
4
SBD (Silent Byte Detected). This bit is set to logical 1 to indicate that received data are
kept in silent state for the time it takes to receive a full word, which includes the start bit,
data bits, parity bit, and stop bits. In 16550 mode, it indicates the same condition for the
data on the top of the FIFO. When the CPU reads USR, it sets this bit to logical 0.
3
2
1
NSER (No Stop Bit Error). This bit is set to logical 1 to indicate that the received data
have no stop bit. In 16550 mode, it indicates the same condition for the data on the top of
the FIFO. When the CPU reads USR, it sets this bit to logical 0.
PBER (Parity Bit Error). This bit is set to logical 1 to indicate that the received data has
the wrong parity bit. In 16550 mode, it indicates the same condition for the data on the top
of the FIFO. When the CPU reads USR, it sets this bit to logical 0.
OER (Overrun Error). This bit is set to logical 1 to indicate that the received data have
been overwritten by the next received data before they were read by the CPU. In 16550
mode, it indicates the same condition, instead of FIFO full. When the CPU reads USR, it
sets this bit to logical 0.
0
RDR (RBR Data Ready). This bit is set to logical 1 to indicate that the received data are
ready to be read by the CPU in the RBR or FIFO. When no data are left in the RBR or
FIFO, the bit is set to logical 0.
Publication Release Date: May 25, 2007
-113-
Revision 1.0
W83627UHG
10.2.3
Handshake Control Register (HCR) (Read/Write)
This register controls pins used with handshaking peripherals such as modems and also controls the
diagnostic mode of the UART.
BIT
7
6
5
4
3
2
1
0
INTERNAL
LOOPBACK
ENABLE
IRQ
ENABLE
LOOPBACK
RI INPUT
RTS
DTR
NAME
DEFAULT
0
0
0
0
0
0
0
0
BIT
7
DESCRIPTION
0
0
0
6
5
Internal Loopback Enable. When this bit is set to logic 1, the UART enters diagnostic
mode, as follows:
4
(1) SOUT is forced to logic 1, and SIN is isolated from the communication link.
(2) The modem output pins are set to their inactive state.
(3) The modem input pins are isolated from the communication link and connect internally
as DTR (bit 0 of HCR) →DSR#, RTS ( bit 1 of HCR) →CTS#, Loopback RI input ( bit 2 of
HCR) → RI# and IRQ enable ( bit 3 of HCR) →DCD#.
Aside from the above connections, the UART operates normally. This method allows the
CPU to test the UART in a convenient way.
3
2
1
0
IRQ Enable. The UART interrupt output is enabled by setting this bit to logic 1. In
diagnostic mode, this bit is internally connected to the modem control input DCD#.
Loopback RI Input. This bit is only used in the diagnostic mode. In diagnostic mode, this
bit is internally connected to the modem control input RI#.
RTS (Request to Send). This bit controls the RTS# output. The value of this bit is
inverted and output to RTS#.
DTR (Data Terminal Ready). This bit controls the DTR# output. The value of this bit is
inverted and output to DTR#.
10.2.4
Handshake Status Register (HSR) (Read/Write)
This register reflects the current state of four input pins used with handshake peripherals such as
modems and records changes on these pins.
BIT
7
6
5
4
3
2
1
0
DCD
RI
DSR
CTS
TDCD
FERI
TDSR
TCTS
NAME
DEFAULT
NA
NA
NA
NA
NA
NA
NA
NA
-114-
W83627UHG
BIT
DESCRIPTION
7
DCD (Data Carrier Detect). This bit is the inverse of the DCD# input and is equivalent to
bit 3 of HCR in Loopback mode.
6
5
4
3
2
1
0
RI (Ring Indicator). This bit is the inverse of the RI# input and is equivalent to bit 2 of
HCR in Loopback mode.
DSR (Data Set Ready). This bit is the inverse of the DSR# input and is equivalent to bit 0
of HCR in Loopback mode.
CTS (Clear to Send). This bit is the inverse of the CTS# input and is equivalent to bit 1 of
HCR in Loopback mode.
TDCD (DCD# Toggling). This bit indicates that the state of the DCD# pin has changed
after HSR is read by the CPU.
FERI (RI Falling Edge). This bit indicates that the RI# pin has changed from low to high
after HSR is read by the CPU.
TDSR (DSR# Toggling). This bit indicates that the state of the DSR# pin has changed
after HSR is read by the CPU.
TCTS (CTS# Toggling). This bit indicates that the state of the CTS# pin has changed
after HSR is read by the CPU.
10.2.5
This register is used to control the FIFO functions of the UART
BIT
7
6
5
4
3
2
1
0
DMA
MODE
SELECT
RECEIVER
FIFO
RESET
TRANSMITTER
FIFO RESET
FIFO
ENABLE
MSB
LSB
RESERVED
NAME
DEFAULT
0
0
NA
NA
0
0
0
0
BIT
DESCRIPTION
7
MSB (RX Interrupt Active Level).
LSB (RX Interrupt Active Level).
RESERVED.
These two bits are used to set the active
level of the receiver FIFO interrupt. The
active level is the number of bytes that
must be in the receiver FIFO to generate
an interrupt.
6
5-4
3
DMS MODE SELECT. When this bit is set to logic 1, DMA mode changes from mode 0 to
mode 1 if UFR bit 0 = 1.
2
1
0
TRANSMITTER FIFO RESET. Setting this bit to logic 1 resets the TX FIFO counter logic
to its initial state. This bit is automatically cleared afterwards.
RECEIVER FIFO RESET. Setting this bit to logic 1 resets the RX FIFO counter logic to its
initial state. This bit is automatically cleared afterwards.
FIFO ENABLE. This bit enables 16550 (FIFO) mode. This bit should be set to logic 1
before other UFR bits are programmed.
Publication Release Date: May 25, 2007
-115-
Revision 1.0
W83627UHG
BIT 7
BIT 6
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
0
0
1
1
0
1
0
1
01
04
08
14
10.2.6
Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status.
BIT
7
6
5
4
3
2
1
0
INTERRUPT INTERRUPT INTERRUPT
0 IF
FIFOS ENABLED
STATUS
BIT 2
STATUS
BIT 1
STATUS
BIT 0
INTERRUPT
PENDING
NAME
DEFAULT
0
0
0
0
0
0
0
1
BIT
7-6
5
DESCRIPTION
FIFOS ENABLED. Set to logical 1 when UFR, bit 0 = 1.
0
0
4
3
INTERRUPT STATUS BIT 2. In 16450 mode, this bit is logical 0. In 16550 mode, bits 3
and 2 are set to logical 1 when a time-out interrupt is pending. Please see the table
below.
2
1
0
INTERRUPT STATUS BIT 1.
These two bits identify the priority level of
the pending interrupt, as shown in the table
below.
INTERRUPT STATUS BIT 0.
0 IF INTERRUPT PENDING. This bit is logic 1 if there is no interrupt pending. If one of
the interrupt sources has occurred, this bit is set to logical 0.
ISR
INTERRUPT SET AND FUNCTION
Bit Bit Bit Bit Interrupt
Interrupt Type
Interrupt Source
Clear Interrupt
3
2
1
0
priority
0
0
0
1
0
1
1
0
-
-
No Interrupt pending
-
First
UART Receive
Status
1. OER = 1 2. PBER =1
3. NSER = 1 4. SBD = 1
Read USR
0
1
0
0
Second
RBR Data Ready
1. RBR data ready
1. Read RBR
2. FIFO interrupt active level
reached
2. Read RBR until FIFO
data under active level
-116-
W83627UHG
Continued
ISR
INTERRUPT SET AND FUNCTION
Bit Bit Bit Bit Interrupt
Interrupt Type
Interrupt Source
Clear Interrupt
3
2
1
0
priority
1
1
0
0
Second
FIFO Data Timeout
TBR Empty
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
Read RBR
0
0
0
0
1
0
0
0
Third
TBR empty
1. Write data into TBR
2. Read ISR (if priority is
third)
Fourth
Handshake status
1. TCTS = 1 2. TDSR = 1
3. FERI = 1 4. TDCD = 1
Read HSR
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
10.2.7
Interrupt Control Register (ICR) (Read/Write)
This 8-bit register enables and disables the five types of controller interrupts separately. A selected
interrupt can be enabled by setting the appropriate bit to logical 1. The interrupt system can be totally
disabled by setting bits 0 through 3 to logical 0.
BIT
7
6
5
4
3
2
1
0
EHSRI
EUSRI
ETBREI
ERDRI
NAME
DEFAULT
0
0
0
0
0
0
0
0
BIT
DESCRIPTION
7
6
5
4
3
0
0
0
0
EHSRI (Handshake Status Interrupt Enable). Set this bit to logical 1 to enable the
handshake status register interrupt.
2
1
0
EUSRI (UART Receive Status Interrupt Enable). Set this bit to logical 1 to enable the
UART status register interrupt.
ETBREI (TBR Empty Interrupt Enable). Set this bit to logical 1 to enable the TBR empty
interrupt.
ERDRI (RBR Data Ready Interrupt Enable). Set this bit to logical 1 to enable the RBR
data ready interrupt.
Publication Release Date: May 25, 2007
-117-
Revision 1.0
W83627UHG
11. PARALLEL PORT
11.1 Printer Interface Logic
The W83627UHG parallel port can be attached to devices that accept eight bits of parallel data at
standard TTL level. The W83627UHG supports the IBM XT/AT compatible parallel port (SPP), the bi-
directional parallel port (BPP), the Enhanced Parallel Port (EPP), and the Extended Capabilities
Parallel Port (ECP).
The following tables show the pin definitions for different modes of the parallel port.
Table 11-1 Pin Descriptions for SPP, EPP, and ECP Modes
HOST
PIN NUMBER
PIN ATTRIBUTE
SPP
EPP
ECP
CONNECTOR
OF W83627UHG
1
36
O
I/O
I
Nstb
PD<7:0>
nACK
BUSY
PE
nWrite
PD<7:0>
Intr
nSTB, HostClk2
PD<7:0>
nACK, PeriphClk2
BUSY, PeriphAck2
PEerror, nAckReverse2
SLCT, Xflag2
2-9
10
11
12
13
14
15
16
17
31-26, 24-23
22
21
19
18
35
34
33
32
I
nWait
PE
I
I
SLCT
Nafd
Select
nDStrb
nError
nInit
O
I
nAFD, HostAck2
nERR
Ninit
nFault1, nPeriphRequest2
nINIT1, nReverseRqst2
nSLIN1, ECPMode2
O
O
nSLIN
nAStrb
Notes:
n<name > : Active Low
1. Compatible Mode
2. High Speed Mode
3. For more information, refer to the IEEE 1284 standard.
11.2 Enhanced Parallel Port (EPP)
The following table lists the registers used in the EPP mode, and identifies the bit map of the parallel
port and EPP registers. Some registers are also used in other modes.
Table 11-2 EPP Register Addresses
A2
0
A1
0
A0
0
REGISTER
NOTE
Data pot (R/W)
1
1
1
1
2
0
0
1
Printer status buffer (Read)
Printer control latch (Write)
Printer control swapper (Read)
EPP address port (R/W)
0
1
0
0
1
0
0
1
1
-118-
W83627UHG
EPP Register Addresses, continued
1
1
1
1
0
0
1
1
0
1
0
1
EPP data port 0 (R/W)
EPP data port 1 (R/W)
EPP data port 2 (R/W)
EPP data port 2 (R/W)
2
2
2
2
Notes:
1. These registers are available in all modes.
2. These registers are available only in EPP mode.
Table 11-3 Address and Bit Map for SPP and EPP Modes
REGISTER
7
PD7
BUSY#
1
6
PD6
ACK#
1
5
4
PD4
SLCT
IRQEN
IRQ
3
PD3
2
1
PD1
0
PD0
Data Port (R/W)
PD5
PE
PD2
1
Status Buffer (Read)
Control Swapper (Read)
Control Latch (Write)
EPP Address Port (R/W)
EPP Data Port 0 (R/W)
EPP Data Port 1 (R/W)
EPP Data Port 2 (R/W)
EPP Data Port 3 (R/W)
ERROR#
SLIN
SLIN
PD3
1
TMOUT
STROBE#
STROBE#
PD0
1
INIT#
INIT#
PD2
PD2
PD2
PD2
PD2
AUTOFD#
AUTOFD#
PD1
1
1
DIR
PD5
PD5
PD5
PD5
PD5
PD7
PD7
PD7
PD7
PD7
PD6
PD6
PD6
PD6
PD6
PD4
PD4
PD4
PD4
PD4
PD3
PD1
PD0
PD3
PD1
PD0
PD3
PD1
PD0
PD3
PD1
PD0
Each register (or pair of registers, in some cases) is discussed below.
11.2.1
Data Port (Data Swapper)
The CPU reads the contents of the printer's data latch by reading the data port.
11.2.2
Printer Status Buffer
The CPU reads the printer status by reading the printer status buffer. The bit definitions are as follows:
BIT
7
6
5
4
3
2
1
1
1
0
BUSY#
ACK#
PE
SLCT
ERROR#
TMOUT
NAME
DEFAULT
NA
NA
NA
NA
NA
0
Publication Release Date: May 25, 2007
Revision 1.0
-119-
W83627UHG
BIT
DESCRIPTION
7
BUSY#. This signal is active during data entry, when the printer is off-line during printing,
when the print head is changing position, or during an error state. When this signal is
active, the printer is busy and cannot accept data.
6
ACK#. This bit represents the current state of the printer’s ACK# signal. A logical 0
means the printer has received a character and is ready to accept another. Normally, this
signal is active for approximately 5 μs before BUSY# stops.
5
4
3
2
1
0
PE. A logical 1 means the printer has detected the end of paper.
SLCT. A logical 1 means the printer is selected.
ERROR#. A logical 0 means the printer has encountered an error condition.
1
1
TMOUT. This bit is only valid in EPP mode. A logical 1 indicates that a 10-μs time-out has
occurred on the EPP bus; a logical 0 means hat no time-out error has occurred. Writing a
logical 1 to this bit clears the time-out status bit; writing a logical 0 has no effect.
11.2.3
Printer Control Latch and Printer Control Swapper
The CPU reads the contents of the printer control latch by reading the printer control swapper. The bit
definitions are as follows:
BIT
7
6
5
4
3
2
1
0
DIR
IRQ ENABLE
SLCT IN
INIT#
AUTO FD
STROBE
NAME
DEFAULT
1
1
NA
0
NA
NA
NA
NA
BIT
7-6
5
DESCRIPTION
These two bits are always read as logical 1 and can be written.
DIR (Direction Control Bit). When this bit is logical 1, the parallel port is in the input mode
(read). When it is logical 0, the parallel port is in the output mode (write). This bit can be
read and written. In SPP mode, this bit is invalid and fixed at zero.
4
IRQ ENABLE. A logical 1 allows an interrupt to occur when ACK# changes from low to
high.
3
2
1
0
SLCT IN. a logical 1 selects the printer.
INIT#. A logical 0 starts the printer (50 microsecond pulse, minimum).
AUTO FD. A logical 1 causes the printer to line-feed after a line is printed.
STROBE. A logical 1 generates an active-high pulse for a minimum of 0.5 μs to clock
data into the printer. Valid data must be presented for a minimum of 0.5 μs before and
after the strobe pulse.
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11.2.4
EPP Address Port
The address port is available only in EPP mode. Bit definitions are as follows:
BIT
7
6
5
4
3
2
1
0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
NAME
The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write
operation. The leading edge of IOW# causes an EPP address write cycle to be performed, and the
trailing edge of IOW# latches the data for the duration of the EPP write cycle.
PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address
read cycle to be performed and the data to be output to the host CPU.
11.2.5
EPP Data Port 0-3
These four registers are available only in EPP mode. The bit definitions for each data port are the
same and as follows:
BIT
7
6
5
4
3
2
1
0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
NAME
When any EPP data port is accessed, the contents of DB0-DB7 are buffered (non-inverting) and
output to ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP data
write cycle to be performed and the trailing edge of IOW# latches the data for the duration of the EPP
write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read
cycle to be performed and the data to be output to the host CPU.
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11.2.6
EPP Pin Descriptions
EPP NAME
TYPE
EPP DESCRIPTION
Denotes read or write operation for address or data.
Bi-directional EPP address and data bus.
NWrite
PD<7:0>
Intr
O
I/O
I
Used by peripheral devices to interrupt the host.
NWait
Inactivated to acknowledge that data transfer is complete. Activated to
indicate that the device is ready for the next transfer.
I
PE
I
I
Paper end; same as SPP mode.
Select
NDStrb
Nerror
Ninits
Printer-select status; same as SPP mode.
This signal is active low. It denotes a data read or write operation.
Error; same as SPP mode.
O
I
This signal is active low. When it is active, the EPP device is reset to its
initial operating mode.
O
O
NAStrb
This signal is active low. It denotes an address read or write operation.
11.2.7
EPP Operation
When EPP mode is selected, the PDx bus is in standard or bi-directional mode when no EPP read,
write, or address cycle is being executed. In this situation, all output signals are set by the SPP
Control Port and the direction is controlled by DIR of the Control Port.
A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 μS have
elapsed from the start of the EPP cycle to the time WAIT# is deasserted. The current EPP cycle is
aborted when a time-out occurs. The time-out condition is indicated in status bit 0.
The EPP operates on a two-phase cycle. First, the host selects the register within the device for
subsequent operations. Second, the host performs a series of read and/or write byte operations to the
selected register. Four operations are supported on the EPP: Address Write, Data Write, Address
Read, and Data Read. All operations on the EPP device are performed asynchronously.
11.2.7.1 EPP Version 1.9 Operation
The EPP read/write operation can be completed under the following conditions:
a. If nWait is active low, the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or write cycle
(nWrite active low, nDStrb/nAStrb active low) starts, proceeds normally, and is completed when nWait
goes inactive high.
b. If nWait is inactive high, the read/write cycle cannot start. It must wait until nWait changes to active
low, at which time it starts is as described above.
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11.2.7.2 EPP Version 1.7 Operation
The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the
read/write cycle starts, however, it does not finish until nWait changes from active low to inactive high.
11.3 Extended Capabilities Parallel (ECP) Port
This port is software- and hardware-compatible with existing parallel ports, so the W83627UHG
parallel port may be used in standard printer mode if ECP is not required. It provides an automatic
high burst-bandwidth channel that supports DMA for ECP in both the forward (host-to-peripheral) and
reverse (peripheral-to-host) directions.
Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth
requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the
standard parallel port to improve compatibility mode transfer speed.
The ECP port hardware supports run-length-encoded (RLE) decompression.
Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates
how many times the next byte is to be repeated. RLE compression is required; the hardware support
is optional.
For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA
Interface Standard.
The W83627UHG ECP supports the following modes.
Table 11-4 ECP Mode Description
MODE
000
001
010
011
100
101
110
111
DESCRIPTION
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
ECP Parallel Port mode
EPP mode (If this option is enabled in the CRF0h to select ECP/EPP mode)
Reserved
Test mode
Configuration mode
The mode selection bits are bits 7-5 of the Extended Control Register.
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Revision 1.0
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11.3.1
ECP Register and Bit Map
The next two tables list the registers used in ECP mode and provide a bit map of the parallel port and
ECP registers.
Table 11-5 ECP Register Addresses
NAME
data
ADDRESS
Base+000h
Base+000h
Base+001h
Base+002h
Base+400h
Base+400h
Base+400h
Base+400h
Base+401h
Base+402h
I/O
R/W
R/W
R
ECP MODES
000-001
011
FUNCTION
Data Register
ecpAFifo
dsr
ECP FIFO (Address)
Status Register
All
dcr
R/W
R/W
R/W
R/W
R
All
Control Register
cFifo
010
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
ecpDFifo
tFifo
011
110
cnfgA
cnfgB
ecr
111
Configuration Register A
Configuration Register B
Extended Control Register
R/W
R/W
111
All
Note: The base addresses are specified by CR60 and 61, which are determined by configuration register or hardware setting.
Table 11-6 Bit Map of the ECP Registers
D7
PD7
D6
D5
D4
D3
D2
D1
D0
NOTE
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Data
ecpAFifo
Dsr
Address or RLE field
Addr/RLE
nBusy
1
2
1
1
2
2
2
nAck
1
PError
Select
nFault
1
1
1
Directio
ackIntEn
SelectIn
nInit
Autofd
strobe
Dcr
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
cFifo
ecpFifo
tFifo
0
0
0
1
1
1
0
1
0
1
0
1
0
1
cnfgA
cnfgB
Ecr
compress
MODE
intrValue
nErrIntrEn
dmaEn
serviceIntr
full
empty
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16-byte FIFO.
Each register (or pair of registers, in some cases) is discussed below.
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11.3.2
Data and ecpAFifo Port
Modes 000 (SPP) and 001 (PS/2) (Data Port)
During a write operation, the Data Register latches the contents of the data bus on the rising edge of
the input, and the contents of this register are output to PD0-PD7. During a read operation, ports PD0-
PD7 are read and output to the host. The bit definitions are as follows:
BIT
7
6
5
4
3
2
1
0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
NAME
Mode 011 (ECP FIFO-Address/RLE)
A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The
hardware at the ECP port transmits this byte to the peripheral automatically. This operation is defined
only for the forward direction. The bit definitions are as follows:
BIT
7
6
5
4
3
2
1
0
Address/RLE
Address or RLE
NAME
11.3.3
Device Status Register (DSR)
These bits are logical 0 during a read of the Printer Status Register. The bits of this status register are
defined as follows:
BIT
7
6
5
4
3
2
1
0
nBusy
nAck
PError
Select
nFault
1
1
1
NAME
BIT
7
DESCRIPTION
nBusy. This bit reflects the complement of the Busy input.
nAck. This bit reflects the nAck input.
6
5
PError. This bit reflects the PError input.
Select. This bit reflects the Select input.
nFault. This bit reflects the nFault input.
4
3
2-0
These three bits are not implemented and are always logical 1 during a read.
11.3.4
Device Control Register (DCR)
The bit definitions are as follows:
BIT
7
1
6
1
5
4
3
2
1
0
Director
ackInEn
SelectIn
nInit
Autofd
Strobe
NAME
DEFAULT
NA
NA
NA
NA
NA
NA
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BIT
DESCRIPTION
7-6
These two bits are always read as logical 1 and cannot be written.
Director. If the mode is 000 or 010, this bit has no effect and the direction is always out.
In other modes,
0: The parallel port is in the output mode.
1: The parallel port is in the input mode.
5
ackInEn (Interrupt Request Enable). When this bit is set to logical 1, it enables interrupt
requests from the parallel port to the CPU on the low-to-high transition on ACK#.
4
3
SelectIn. This bit is inverted and output to the SLIN# output.
0: The printer is not selected.
1: The printer is selected.
2
1
0
nInit. This bit is output to the INIT# output.
Autofd. This bit is inverted and output to the AFD# output.
Strobe. This bit is inverted and output to the STB# output.
11.3.5
CFIFO (Parallel Port Data FIFO) Mode = 010
This mode is defined only for the forward direction. Bytes written or DMAed to this FIFO are
transmitted by a hardware handshake to the peripheral using the standard parallel port protocol.
Transfers to the FIFO are byte-aligned.
11.3.6
ECPDFIFO (ECP Data FIFO) Mode = 011
When the direction bit is 0, bytes written or DMAed to this FIFO are transmitted by a hardware
handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte-
aligned.
When the direction bit is 1, data bytes from the peripheral are read via automatic hardware handshake
from ECP into this FIFO. Reads or DMAs from the FIFO return bytes of ECP data to the system.
11.3.7
TFIFO (Test FIFO Mode) Mode = 110
Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in
the tFIFO is not transmitted to the parallel port lines. However, data in the tFIFO may be displayed on
the parallel port data lines.
11.3.8
CNFGA (Configuration Register A) Mode = 111
This register is a read-only register. When it is read, 10H is returned. This indicates that this is an 8-bit
implementation.
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11.3.9
CNFGB (Configuration Register B) Mode = 111
The bit definitions are as follows:
BIT
7
6
5
4
3
2
1
1
1
0
1
COMPRESS
intrVALUE
IRQx2
IRQx1
IRQx0
NAME
DEFAULT
0
0
0
0
0
BIT
DESCRIPTION
7
Compress. This bit is read-only. It is logical 0 during a read, which means that this chip
does not support hardware RLE compression.
6
5
intrValue. Returns the value on the ISA IRQ line to determine possible conflicts.
IRQx2.
Reflects the IRQ resource assigned for ECP port.
cnfgB[5:3]
IRQ resource
000
Reflects other IRQ resources selected by PnP
register (default)
4
3
IRQx1.
IRQx0.
001
010
011
100
101
110
111
IRQ7
IRQ9
IRQ10
IRQ11
IRQ14
IRQ15
IRQ5
2-0
These three bits are logical 1 during a read and can be written.
11.3.10 ECR (Extended Control Register) Mode = all
This register controls the extended ECP parallel port functions. The bit definitions are follows:
BIT
7
6
5
4
3
2
1
0
MODE
MODE
MODE
nErrIntrEn
dmaEn
ServiceIntr
Full
Empty
NAME
DEFAULT
0
0
0
1
0
1
0
1
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Revision 1.0
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BIT
DESCRIPTION
Mode. Read/Write. These bits select the mode.
7-5
000
001
Standard Parallel Port (SPP) mode. The FIFO is reset in this mode.
PS/2 Parallel Port mode. This is the same as SPP mode except that
direction may be used to tri-state the data lines. Furthermore, reading the
data register returns the value on the data lines, not the value in the data
register.
010
011
Parallel Port FIFO mode. This is the same as SPP mode except that bytes
are written or DMAed to the FIFO. FIFO data are automatically transmitted
using the standard parallel port protocol. This mode is useful only when
direction is 0.
ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes
placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a
single FIFO and automatically transmitted to the peripheral using the ECP
Protocol. When the direction is 1 (reverse direction), bytes are moved from
the ECP parallel port and packed into bytes in the ecpDFifo.
100
101
110
EPP Mode. EPP mode is activated if the EPP mode is selected.
Reserved.
Test Mode. The FIFO may be written and read in this mode, but the data is
not transmitted on the parallel port.
111
Configuration Mode. The confgA and confgB registers are accessible at
0x400 and 0x401 in this mode.
4
nErrIntrEn. Read/Write (Valid only in ECP Mode)
0: Enables the interrupt generated on the falling edge of nFault. This prevents interrupts
from being lost in the time between the read of the ECR and the write of the ECR.
1: Disables the interrupt generated on the asserting edge of nFault.
3
2
dmaEn. Read/Write.
0: Disable DMA unconditionally.
1: Enable DMA.
serviceIntr. Read/Write.
0: Enable one of the following cases of interrupts. When one of the serviced interrupts
occurs, this bit is set to logical 1 by the hardware. This bit must be reset to logical 0 to
re-enable the interrupts.
(a) dmaEn = 1: During DMA, this bit is set to logical 1 when terminal count is reached.
(b) dmaEn = 0, direction = 0: This bit is set to logical 1 whenever there are writeIntr
threshold or more bytes free in the FIFO.
(c) dmaEn = 0, direction = 1: This bit is set to logical 1 whenever there are readIntr
threshold or more valid bytes to be read from the FIFO.
1: Disable DMA and all of the service interrupts. Writing a logical 1 to this bit does not
cause an interrupt.
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Continued
BIT
DESCRIPTION
1
Full. Read Only.
0: The FIFO has at least one free byte.
1: The FIFO is completely full; it cannot accept another byte.
0
Empty. Read Only.
0: The FIFO contains at least one byte of data.
1: The FIFO is completely empty.
11.3.11 ECP Pin Descriptions
NAME
TYPE
DESCRIPTION
NStrobe (HostClk)
This pin loads data or address into the slave on its asserting edge
during write operations. This signal handshakes with Busy.
O
I/O
I
PD<7:0>
These signals contain address, data or RLE data.
nAck (PeriphClk)
This signal indicates valid data driven by the peripheral when
asserted. This signal handshakes with nAutoFd in reverse.
Busy (PeriphAck)
This signal deasserts to indicate that the peripheral can accept
data. In the reverse direction, it indicates whether the data lines
contain ECP command information or data. Normal data are
transferred when Busy (PeriphAck) is high, and an 8-bit command
is transferred when it is low.
I
PError (nAckReverse)
This signal is used to acknowledge a change in the direction of the
transfer (asserted = forward). The peripheral drives this signal low
to acknowledge nReverseRequest. The host relies upon
nAckReverse to determine when it is permitted to drive the data
bus.
I
I
Select (Xflag)
Indicates printer on-line.
NautoFd (HostAck)
Requests a byte of data from the peripheral when it is asserted. In
the forward direction, this signal indicates whether the data lines
contain ECP address or data. Normal data are transferred when
nAutoFd (HostAck) is high, and an 8-bit command is transferred
when it is low.
O
nFault
(nPeriphReuqest)
Generates an error interrupt when it is asserted. This signal is valid
only in the forward direction. The peripheral is permitted (but not
required) to drive this pin low to request a reverse transfer during
ECP mode.
I
nInit
This signal sets the transfer direction (asserted = reverse,
deasserted = forward). This pin is driven low to place the channel
in the reverse direction.
(nReverseRequest)
O
O
nSelectIn (ECPMode)
This signal is always deasserted in ECP mode.
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11.3.12 ECP Operation
The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol
before ECP operation. After negotiation, it is necessary to initialize some of the port bits.
(a) Set direction = 0, enabling the drivers.
(b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state.
(c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state.
(d) Set mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo,
respectively.
11.3.12.1 Mode Switching
The software must handle P1284 negotiation and all operations prior to a data transfer in SPP or PS/2
modes (000 or 001). The hardware provides an automatic control line handshake, moving data
between the FIFO and the ECP port, only in the data transfer phase (mode 011 or 010).
If the port is in mode 000 or 001, it may switch to any other mode. If the port is not in mode 000 or 001,
it can only be switched into mode 000 or 001. The direction can only be changed in mode 001.
In extended forward mode, the software should wait for the FIFO to be empty before switching back to
mode 000 or 001. In ECP reverse mode, the software should wait for all the data to be read from the
FIFO before changing back to mode 000 or 001.
11.3.12.2 Command/Data
ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction, normal
data are transferred when HostAck is high, and an 8-bit command is transferred when HostAck is low.
The most significant bits of the command indicate whether it is a run-length count (for compression) or
a channel address.
In the reverse direction, normal data are transferred when PeriphAck is high, and an 8-bit command is
transferred when PeriphAck is low. The most significant bit of the command is always zero.
11.3.12.3 Data Compression
The W83627UHG hardware supports RLE decompression and can transfer compressed data to a
peripheral. Odd (RLE) compression is not supported in the hardware, however. In order to transfer
data in ECP mode, the compression count is written to ecpAFifo and the data byte is written to
ecpDFifo.
11.3.12.4 FIFO Operation
The FIFO threshold is set in CR5. All data transferred to or from the parallel port can proceed in DMA
or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used in Parallel
Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled.
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11.3.13 DMA Transfers
DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. DMA uses the standard PC DMA
services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA
empties or fills the FIFO using the appropriate direction and mode. When the terminal count in the
DMA controller is reached, an interrupt is generated, and serviceIntr is asserted, which will disable the
DMA.
11.3.14 Programmed I/O (NON-DMA) Mode
The ECP and parallel port FIFOs can also be operated using interrupt-driven, programmed I/O.
Programmed I/O transfers are
1. To the ecpDFifo at 400H and ecpAFifo at 000H
2. From the ecpDFifo located at 400H
3. To / from the tFifo at 400H.
The host must set dmaEn and serviceIntr to 0 and also must set the direction and state accordingly in
the programmed I/O transfers.
The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The
programmed I/O empties or fills the FIFO using the appropriate direction and mode.
Publication Release Date: May 25, 2007
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12. KEYBOARD CONTROLLER
The W83627UHG KBC (8042 with licensed KB BIOS) circuit is designed to provide the functions
®-
needed to interface a CPU with a keyboard and/or a PS/2 mouse and can be used with IBM
compatible personal computers or PS/2-based systems. The controller receives serial data from the
keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte
of data in its output buffer. Then, the controller asserts an interrupt to the system when data are
placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data
transmissions. No transmission should be sent to the keyboard or PS/2 mouse until an
acknowledgement is received for the previous data byte.
P24
P25
P21
P20
KIRQ
MIRQ
GATEA20
KBRST
KINH
P17
KDAT
KCLK
P27
P10
P26
8042
T0
GP I/O PINS
Multiplex I/O PINS
MCLK
MDAT
P23
T1
P12~P16
P22
P11
Figure 12-1 Keyboard and Mouse Interface
12.1 Output Buffer
The output buffer is an 8-bit, read-only register at I/O address 60H (Default, PnP programmable I/O
address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan
code (from the keyboard) and required command bytes to the system. The output buffer can only be
read when the output buffer full bit in the register (in the status register) is logical 1.
12.2 Input Buffer
The input buffer is an 8-bit, write-only register at I/O address 60h or 64h (Default, PnP programmable
I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60h sets a flag to
indicate a data write; writing to address 64h sets a flag to indicate a command write. Data written to
I/O address 60h is sent to the keyboard (unless the keyboard controller is expecting a data byte)
through the controller's input buffer only if the input buffer full bit (in the status register) is logical 0.
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12.3 Status Register
The status register is an 8-bit, read-only register at I/O address 64H (Default, PnP programmable I/O
address LD5-CR62 and LD5-CR63) that holds information about the status of the keyboard controller
and interface. It may be read at any time.
Table 12-1 Bit Map of Status Register
BIT
BIT FUNCTION
DESCRIPTION
0: Output buffer empty
1: Output buffer full
0
Output Buffer Full
0: Input buffer empty
1: Input buffer full
1
2
Input Buffer Full
System Flag
This bit may be set to 0 or 1 by writing to the system flag bit in the
command byte of the keyboard controller. It defaults to 0 after a
power-on reset.
0: Data byte
1: Command byte
3
4
5
6
7
Command/Data
Inhibit Switch
0: Keyboard is inhibited
1: Keyboard is not inhibited
Auxiliary Device
Output Buffer
0: Auxiliary device output buffer empty
1: Auxiliary device output buffer full
General Purpose
Time-out
0: No time-out error
1: Time-out error
0: Odd parity
1: Even parity (error)
Parity Error
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W83627UHG
12.4 Commands
Table 12-2 KBC Command Sets
COMMAND
20h
FUNCTION
Read Command Byte of Keyboard Controller
Write Command Byte of Keyboard Controller
60h
BIT
BIT DEFINITION
7
6
Reserved
IBM Keyboard Translate Mode
Disable Auxiliary Device
Disable Keyboard
5
4
3
2
1
Reserve
System Flag
Enable Auxiliary Interrupt
Enable Keyboard Interrupt
0
A4h
Test Password
Returns 0Fah if Password is loaded
Returns 0F1h if Password is not loaded
Load Password
Load Password until a logical 0 is received from the system
Enable Password
A5h
A6h
Enable the checking of keystrokes for a match with the password
Disable Auxiliary Device Interface
A7h
A8h
A9h
Enable Auxiliary Device Interface
Interface Test
BIT
BIT DEFINITION
No Error Detected
00
01
Auxiliary Device "Clock" line is stuck low
Auxiliary Device "Clock" line is stuck high
Auxiliary Device "Data" line is stuck low
02
03
04
Auxiliary Device "Data" line is stuck low
AAh
Self-test
Returns 055h if self-test succeeds
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W83627UHG
KBC Command Sets, continued
COMMAND
FUNCTION
ABh
Interface Test
BIT DEFINITION
No Error Detected
BIT
00
01
Keyboard "Clock" line is stuck low
02
03
04
Keyboard "Clock" line is stuck high
Keyboard "Data" line is stuck low
Keyboard "Data" line is stuck high
ADh
AEh
C0h
C1h
C2h
D0h
D1h
D2h
D3h
D4h
E0h
FXh
Disable Keyboard Interface
Enable Keyboard Interface
Read Input Port (P1) and send data to the system
Continuously puts the lower four bits of Port1 into the STATUS register
Continuously puts the upper four bits of Port1 into the STATUS register
Send Port 2 value to the system
Only set / reset GateA20 line based on system data bit 1
Send data back to the system as if it came from the Keyboard
Send data back to the system as if it came from Auxiliary Device
Output next received byte of data from system to Auxiliary Device
Reports the status of the test inputs
Pulse only RC (the reset line) low for 6μs if the Command byte is even
12.5 Hardware GATEA20/Keyboard Reset Control Logic
The KBC includes hardware control logic to speed-up GATEA20 and KBRESET. This control logic is
controlled by LD5-CRF0 as follows:
12.5.1
KB Control Register (Logic Device 5, CR-F0)
BIT
7
6
5
4
3
0
2
1
0
KCLKS1
KCLKS0
RESERVED
P92EN
HGA20
HKBRST
NAME
DEFAULT
1
0
0
0
0
0
0
Publication Release Date: May 25, 2007
Revision 1.0
-135-
W83627UHG
BIT
DESCRIPTION
7
KCLKS1.
KCLKS0.
Select the KBC clock rate.
Bits
7 6
0 0: KBC clock input is 6 MHz.
0 1: KBC clock input is 8 MHz.
1 0: KBC clock input is 12 MHz.
1 1: KBC clock input is 16 MHz.
6
5-3
2
RESERVED.
P92EN (Port 92 Enable).
1: Enables Port 92 to control GATEA20 and KBRESET.
0: Disables Port 92 functions.
1
0
HGA20 (Hardware GATEA 20).
1: Selects hardware GATE A20 control logic to control GATE A20 signal.
0: Disables GATEA20 control logic functions.
HKBRST (Hardware Keyboard Reset).
1: Selects hardware KB RESET control logic to control KBRESET signal.
0: Disables hardware KB RESET control logic function.
When the KBC receives data that follows a "D1" command, the hardware control logic sets or clears
GATE A20 according to received data bit 1. Similarly, the hardware control logic sets or clears
KBRESET depending on received data bit 0. When the KBC receives an "FE" command, the
KBRESET is pulse low for 6 μs (Min.) with a 14 μs (Min.) delay.
GATE A20 and KBRESET are controlled by either software or hardware logic, and they are mutually
exclusive. Then, GATE A20 and KBRESET are merged with Port92 when the P92EN bit is set.
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W83627UHG
12.5.2
Port 92 Control Register (Default Value = 0x24)
BIT
7
6
5
4
3
2
1
0
RES. (0)
RES. (1)
RES. (0)
RES. (1)
SGA20
PLKBRST
NAME
DEFAULT
0
0
1
0
0
1
0
0
BIT
7-6
5
DESCRIPTION
RES. (0)
RES. (1)
RES. (0)
RES. (1)
4-3
2
1
SGA20 (Special GATE A20 Control)
1: Drives GATE A20 signal to high.
0: Drives GATE A20 signal to low.
0
PLKBRST (Pulled-low KBRESET). A logical 1 on this bit causes KBRESET to drive low
for 6 μS(Min.) with a 14 μS(Min.) delay. Before issuing another keyboard-reset command,
the bit must be cleared.
Publication Release Date: May 25, 2007
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Revision 1.0
W83627UHG
13. POWER MANAGEMENT EVENT
The PME# (pin 86) signal is connected to the South Bridge and is used to wake up the system from
S1 ~ S5 sleeping states.
One control bit and four registers in the W83627UHG are associated with the PME function. The
control bit is at Logical Device A, CR[F2h], bit[0] and is for enabling or disabling the PME function. If
this bit is set to “0”, the W83627UHG won’t output any PME signal when any of the wake-up events
has occurred and is enabled. The four registers are divided into PME status registers and PME
interrupt registers of wake-up events Note.1
1) The PME status registers of wake-up event:
.
-
-
-
At Logical Device A, CR[F3h] and CR[F4h]
Each wake-up event has its own status
The PME status should be cleared by writing a “1” before enabling its corresponding bit in
the PME interrupt registers
2) The PME interrupt registers of wake-up event:
-
-
At Logical Device A, CR[F6h] and CR[F7h]
Each wake-up event can be enabled / disabled individually to generate a PME# signal
Note.1 PME wake-up events that the W83627UHG supports include:
z
z
z
z
z
z
z
z
z
z
z
z
z
Mouse IRQ event
Keyboard IRQ event
Printer IRQ event
Floppy IRQ event
UART A IRQ event
UART B IRQ event
UART C IRQ event
UART D IRQ event
UART E IRQ event
UART F IRQ event
Hardware Monitor IRQ event
WDTO# event
RIB (UARTB Ring Indicator) event
13.1 Power Control Logic
This chapter describes how the W83627UHG implements its ACPI function via these power control
pins: PSIN# (Pin 68), PSOUT# (Pin 67), SUSB# (i.e. SLP_S3#; Pin 73) and PSON# (Pin 72). The
following figure illustrates the relationships.
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W83627UHG
PSON#
53VSB/VBAT
53VCC
PSON#
PWRBTN#
PSOUT#
PSIN#
VCC ON
Power
W83627UHG
Supply
South Bridge
IOCLK
48 / 24 MHz
SUSB#
SLP_S3#
Figure 13-1 Power Control Mechanism
13.1.1
PSON# Logic
13.1.1.1 Normal Operation
The PSOUT# signal will be asserted low if the PSIN# signal is asserted low. The PSOUT# signal is
held low for as long as the PSIN# is held low. The South Bridge controls the SUSB# signal through the
PSOUT# signal. The PSON# is directly connected to the power supply to turn on or off the power.
Figure 13-2 shows the power on and off sequences.
The ACPI state changes from S5 to S0, then to S5
PSON#
SUSB# (Intel Chipset)
SUSB# (Other Chipset)
PSOUT#
PSIN#
5VSB
S0 State
S5 State
S5 State
Figure 13-2 Power Sequence from S5 to S0, then back to S5.
Publication Release Date: May 25, 2007
Revision 1.0
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W83627UHG
13.1.2
AC Power Failure Resume
By definition, AC power failure means that the standby power is removed. The power failure resume
control logic of the W83627UHG is used to recover the system to a pre-defined state after AC power
failure. Two control bits at Logical Device A, CR[E4h], bits[6:5] indicate the pre-defined state. The
definition of these two bits is listed in the following table:
Table 13-1 Bit Map of Logical Device A, CR[E4h], bits [6:5]
LOGICAL DEVICE A, CR[E4H],
BITS[6:5]
DEFINITION
00
01
System always turns off when it returns from AC power failure
System always turns on when it returns from AC power failure
System turns off / on when it returns from power failure
depending on the state before the power failure. (Please see
Note 1)
10
11
User defines the state before the power failure. (The previous
state is set at CRE6[4]. Please see Note 2)
Note1. The W83627UHG detects the state before power failure (on or off) through the SUSB# signal and
the 5VCC power. The relation is illustrated in the following two figures.
5VCC
SUSB#
The previous state is “on”, if 5VCC falls to 3.75V and SUSB# keeps at 2.0V.
5VCC
SUSB#
The previous state is “off”, if 5VCC falls to 3.75V and SUSB# keeps at 0.8V.
Note 2.
Logical Device A, CR[E6h]
bit [4]
Definition
0
1
User defines the state to be “on”
User defines the state to be “off”
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W83627UHG
To ensure that VCC does not fall faster than VSB in various ATX Power Supplies, the W83627UHG
adds the option of “user define mode” for the pre-defined state before AC power failure. BIOS can set
the pre-defined state to be “On” or “Off”. According to this setting, the system is returned to the pre-
defined state after the AC power recovery.
13.2 Wake Up the System by Keyboard and Mouse
The W83627UHG generates a low pulse through the PSOUT# pin to wake up the system when it
detects a key code pressed or mouse button clicked. The following sections describe how the
W83627UHG works.
13.2.1
Waken up by Keyboard events
The keyboard Wake-Up function is enabled by setting Logical Device A, CR[E0h], bit 6 to “1”.
There are two keyboard events that can be used for the wake-up
1) Any key – Set bit 0 at Logical Device A, CR[E0h] to “1” (Default).
2) Specific keys (Password) - Set bit 0 at Logical Device A, CR[E0h] to “0”.
Three sets of specific key combinations are stored at Logical Device A. CR[E1h] is an index register to
indicate which byte of key code storage (0x00h ~ 0x0Eh, 0x30h ~ 0x3Eh, 0x40h ~ 0x4Eh) is going to
be read or written through CR[E2h]. According to IBM 101/102 keyboard specification, a complete key
code contains a 1-byte make code and a 2-byte break code. For example, the make code of “0” is
0x45h, and the corresponding break code is 0xF0h, 0x45h.
The approach to implement Keyboard Password Wake-Up Function is to fill key codes into the
password storage. Assume that we want to set “012” as the password. The storage should be filled as
below. Please note that index 0x09h ~ 0x0Eh must be filled as 0x00h since the password has only
three numbers.
Index(CRE1)Æ
Data(CRE2)Æ
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
1E F0 1E 16 F0 16 45 F0 45 00 00 00 00 00 00
First-pressed key “0”
Second-pressed key “1”
Third-pressed key “2”
Publication Release Date: May 25, 2007
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Revision 1.0
W83627UHG
13.2.2
Waken up by Mouse events
The mouse Wake-Up function is enabled by setting Logical Device A, CR[E0h], bit 5 to “1”.
The following specific mouse events can be used for the wake-up:
z
z
z
z
z
z
Any button clicked or any movement
One click of the left or the right button
One click of the left button
One click of the right button
Two clicks of the left button
Two clicks of the right button.
Three control bits (ENMDAT_UP, MSRKEY, MSXKEY) define the combinations of the mouse wake-up
events. Please see the following table for the details.
Table 13-2 Definitions of Mouse Wake-Up Events
MSXKEY
ENMDAT_UP
MSRKEY
(LOGICAL
DEVICE A,
CR[E0H], BIT 1)
WAKE-UP EVENT
(LOGICAL DEVICE A, (LOGICAL DEVICE A,
CR[E6H], BIT 7)
CR[E0H], BIT 4)
Any button clicked or any
movement.
1
1
x
x
1
0
One click of the left or right
button.
0
0
0
0
0
1
0
1
1
1
0
0
One click of the left button.
One click of the right button.
Two clicks of the left button.
Two clicks of the right button.
13.3 Resume Reset Logic
The RSMRST# (Pin 75) signal is a reset output and is used as the 5VSB power on reset signal for the
South Bridge.
When the W83627UHG detects the 5VSB voltage rises to “V1”, it then starts a delay – “t1” before the
rising edge of RSMRST# asserting. If the 5VSB voltage falls below “V2”, the RSMRST# de-asserts
immediately.
Timing and voltage parameters are shown in Figure 13-3 and Table 13-3.
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W83627UHG
t1
RSMRST#
V1
V2
5VSB
Figure 13-3 Mechanism of Resume Reset Logic
Table 13-3 Timing and Voltage Parameters of RSMRST#
NAME
PARAMETER
MIN.
-
MAX.
4.3
-
UNIT
V
V1
V2
t1
5VSB Valid Voltage
5VSB Ineffective Voltage
2.6
100
V
Valid 5VSB to RSMRST# inactive
200
mS
13.4 PWROK Generation
The PWROK (Pin 71) signal is an output and is used as both the 5VCC and 3VCC power-on reset
signal.
When the W83627UHG detects both of the 5VCC and 3VCC voltages rise to “V3” and “V5”, it then
starts a delay – “t2” before the rising edge of PWROK assertion. If both of the 5VCC and 3VCC
voltages fall below “V4” and “V6”, the PWROK de-asserts immediately.
Timing and the voltage parameters are shown in Figure 13-4 and Table 13-4.
Figure 13-4 PWROK Generation Mechanism
t2
PWROK
V3
V4
V6
5VCC
3VCC
V5
Publication Release Date: May 25, 2007
Revision 1.0
-143-
W83627UHG
Table 13-4 Timing and the Voltage Parameters of PWROK
NAME
PARAMETER
5VCC Valid Voltage
MIN.
-
MAX.
4.3
-
UNIT
V
V3
5VCC Ineffective Voltage
2.6
-
V
V4
V5
V6
t2
3VCC Valid Voltage
2.9
V
3VCC Ineffective Voltage
2.1
300
V
Valid 5VCC and 3VCC to PWROK active
500
mS
Originally, the t2 timing is between 300 mS to 500 mS, but it can be changed to 200 mS to 300 mS by
programming Logical Device A, CR[E6h], bit 3 to “1”. Furthermore, the W83627UHG provides four
different extra delay time of PWROK for various demands. The four extra delay time are designed at
Logical Device A, CR[E6h], bits 2~1. The following table shows the definitions of Logical Device A,
CR[E6h] bits 3 ~1.
LOGICAL DEVICE A,
DEFINITION
CR[E6H] BIT
PWROK_DEL (first stage) (VSB)
Set the delay time when rising from PWROK_LP to PWROK_ST.
3
0: 300 ~ 500 mS.
1: 200 ~ 300 mS.
PWROK_DEL (VSB)
Set the delay time when rising from PWROK_ST to PWROK.
2~1
00: No delay time.
10: 96 ms
01: Delay 32 ms
11: Delay 250 ms
For example, if Logical Device A, CR[E6h] bit 2 is set to “0” and bits 2~1 are set to “10”, the range of t2
timing is from 396(300 + 96) mS to 596(500 + 96) mS.
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W83627UHG
14. SERIALIZED IRQ
The W83627UHG supports a serialized IRQ scheme. This allows a signal line to be used to report the
parallel interrupt requests. Since more than one device may need to share the signal serial SERIRQ
signal, an open drain signal scheme is employed. The clock source is the PCI clock. The serialized
interrupt is transferred on the SERIRQ signal, one cycle consisting of three frames types: the Start
Frame, the IRQ/Data Frame, and the Stop Frame.
14.1 Start Frame
There are two modes of operation for the SERIRQ Start Frame: the Quiet mode and the Continuous
mode.
In the Quiet mode, the W83627UHG drives the SERIRQ signal active low for one clock, and then tri-
states it. This brings all the state machines of the W83627UHG from idle to active states. The host
controller (the South Bridge) then takes over driving SERIRQ signal low in the next clock and
continues driving the SERIRQ low for programmable 3 to 7 clock periods. This makes the total number
of clocks low 4 to 8 clock periods. After these clocks, the host controller drives the SERIRQ high for
one clock and then tri-states it.
In the Continuous mode, the START Frame can only be initiated by the host controller to update the
information of the IRQ/Data Frame. The host controller drives the SERIRQ signal low for 4 to 8 clock
periods. Upon a reset, the SERIRQ signal is defaulted to the Continuous mode for the host controller
to initiate the first Start Frame.
Please see the diagram below for more details.
IRQ1 FRAME
SMI# FRAME
IRQ0 FRAME
START FRAME
SL
or
H
H
R
T
S
R
T
S
R
T
S
R
T
PCICLK
SERIRQ
START 1
2
None
None
IRQ1
Drive Source
IRQ1
Host Controller
Figure 14-1 Start Frame Timing with Source Sampled A Low Pulse on IRQ1
H=Host Control
SL=Slave Control
R=Recovery
T=Turn-around
S=Sample
Note:
1. The Start Frame pulse can be 4-8 clocks wide.
2. The first clock of Start Frame is driven low by the W83627UHG because IRQ1 of the W83627UHG
needs an interrupt request. Then the host takes over and continues to pull the SERIRQ low.
Publication Release Date: May 25, 2007
-145-
Revision 1.0
W83627UHG
14.2 IRQ/Data Frame
Once the Start Frame has been initiated, the W83627UHG must start counting frames based on the
rising edge of the start pulse. Each IRQ/Data Frame has three clocks: the Sample phase, the
Recovery phase, and the Turn-around phase.
During the Sample phase, the W83627UHG drives SERIRQ low if the corresponding IRQ is active. If
the corresponding IRQ is inactive, then SERIRQ must be left tri-stated. During the Recovery phase,
the W83627UHG device drives the SERIRQ high. During the Turn-around phase, the W83627UHG
device leaves the SERIRQ tri-stated. The W83627UHG starts to drive the SERIRQ line from the
beginning of "IRQ0 FRAME" based on the rising edge of PCICLK.
The IRQ/Data Frame has a specific numeral order, as shown in Table 14-1.
Table 14-1 SERIRQ Sampling Periods
SERIRQ SAMPLING PERIODS
IRQ/DATA FRAME
SIGNAL SAMPLED
# OF CLOCKS PAST
START
EMPLOYED BY
1
2
IRQ0
IRQ1
2
-
5
Keyboard
3
SMI#
8
-
4
IRQ3
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
95
UART B
5
IRQ4
UART A
6
IRQ5
-
7
IRQ6
FDC
8
IRQ7
LPT
9
IRQ8
-
10
11
12
13
14
15
16
17
18
19
20
21
32:22
IRQ9
-
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IOCHCK#
INTA#
INTB#
INTC#
INTD#
Unassigned
-
-
Mouse
-
-
-
-
-
-
-
-
-
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W83627UHG
14.3 Stop Frame
After all IRQ/Data Frames have completed, the host controller will terminates SERIRQ with a Stop
frame. Only the host controller can initiate the Stop Frame by driving SERIRQ low for 2 or 3 clocks. If
the Stop Frame is low for 2 clocks, the Sample mode of next SERIRQ cycle’s Sample mode is the
Quiet mode. If the Stop Frame is low for 3 clocks, the Sample mode of next SERIRQ cycle is the
Continuous mode.
Please see the diagram below for more details.
IRQ14
FRAME
IRQ15
FRAME
IOCHCK#
FRAME
STOP FRAME
NEXT CYCLE
START2
I 1
S
R
T
S
R
T
S
R
T
H
R
T
PCICLK
SERIRQ
STOP
Driver
None
IRQ15
None
Host Controller
Figure 14-2 Stop Frame Timing with Host Using 17 SERIRQ Sampling Period
H=Host Control
R=Recovery
T=Turn-around
S=Sample
I= Idle.
Note:
1. There may be none, one or more Idle states during the Stop Frame.
2. The Start Frame pulse of next SERIRQ cycle may or may not start immediately after the
turn-around clock of the Stop Frame.
Publication Release Date: May 25, 2007
-147-
Revision 1.0
W83627UHG
15. WATCHDOG TIMER
Pin 77 is the WDTO# pin in the W83627UHG.
The Watchdog Timer of the W83627UHG consists of an 8-bit programmable time-out counter and a
control and status register. The time-out counter ranges from 1 to 255 minutes in the minute mode, or
1 to 255 seconds in the second mode. The units of Watchdog Timer counter are selected at Logical
Device 8, CR[F5h], bit[3]. The time-out value is set at Logical Device 8, CR[F6h]. Writing zero disables
the Watchdog Timer function. Writing any non-zero value to this register causes the counter to load
this value into the Watchdog Timer counter and start counting down.
The W83627UHG outputs a low signal to the WDTO# pin (pin 77) when a time-out event occurs. In
other words, when the value is counted down to zero, the timer stops, and the W83627UHG sets the
WDTO# status bit in Logical Device 8, CR[F7h], bit[4], outputting a low signal to the WDTO# pin(pin
77). Writing a zero will clear the status bit and the WDTO# pin returns to high. Writing a zero will clear
the status bit. This bit will also be cleared if LRESET# or PWROK# signal is asserted.
Please note that the output type of WDTO# (pin 77) is open-drain.
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W83627UHG
16. GENERAL PURPOSE I/O
16.1 GPIO Architecture
The W83627UHG provides 45 input/output ports that can be individually configured to perform a
simple basic I/O function or an alternative, pre-defined function. GPIO ports 1 ~2 are configured
through control registers in Logical Device 9, GPIO ports 3~4 in Logical Device 7, and GPIO ports 5~6
in Logic Device 8. Users can configure each individual port to be an input or output port by
programming respective bit in the selection register ( 0 = output, 1 = input). Invert port value by setting
inversion register ( 0 = non -inverse, 1 = inverse). The port value is read / written through data
registers.
In addition, only GP25, GP26 and GP27 are designed to be able to assert PSOUT# or PME# signal to
wake up the system if any of them has any transitions. The rising or falling edge can be set to perform
the wake-up function. The following table gives a more detailed register map on GP25, GP26 and
GP27.
Table 16-1 Relative Control Registers of GPIO 25, 26 and 27 that Support Wake-Up Function
EVENTROUTE I
(PSOUT#)
EVENTROUTE II
(PME#)
EVENT POLARITY
EVENT STATUS
0: DISABLE
1: ENABLE
0: DISABLE
1: ENABLE
0 : RISING
1 : FALLING
GP25
GP26
GP27
LDA,
LDA,
LD9,
LD9,
CR[FEh]
bit4
CR[FEh]
bit0
CR[E6h]
bit5
CR[E7h]
bit5
LDA,
LDA,
LD9,
LD9,
CR[FEh]
bit5
CR[FEh]
bit1
CR[E6h]
bit6
CR[E7h]
bit6
LDA,
LDA,
LD9,
LD9,
CR[FEh]
bit6
CR[FEh]
bit2
CR[E6h]
bit7
CR[E7h]
bit7
16.2 Access Channels
There are two different channels to set up/access the GPIO ports. The first one is the indirect access
via register 2E/2F (4E/4F, it depends by HEFRAS trapping). The registers can be read / written only
when the respective logical device ID and port number are selected.
The other is the direct access through GPIO register table that can be configured by {CR61, CR60} of
logic device 8. The mapped 5 registers are defined in table 11.2. Since the base address is set, the
GPIO number can be selected by writing the group number to GSR [INDEX] (GPIO Select Register,
#1~#6 for GPIO1 ~ GPIO6 respectively; #0 and #7 is invalid for GSR [INDEX]). Then the I/O register,
the Data register and the Inversion register are mapped to addresses Base+0, Base+1 and Base+2
respectively. Only one GPIO can be accessed at one time. The chip will ignore more than one “1”
written in GSR. The most significant bit (MSB) is with higher priority.
Publication Release Date: May 25, 2007
-149-
Revision 1.0
W83627UHG
Table 16-2 GPIO Register Addresses
BIT NUMBER
ADDRESS ABBR
7
6
5
4
3
2
1
0
Base + 0
Base + 1
Base + 2
Base + 3
Base + 4
GSR
IOR
DAT
INV
Reserved
INDEX
GPIO I/O Register
GPIO Data Register
GPIO Inversion Register
GPIO Status Register
DST
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W83627UHG
17. CONFIGURATION REGISTER
17.1 Chip (Global) Control Register
CR 02h. (Software Reset; Write Only)
BIT
READ / WRITE
DESCRIPTION
7~1 Reserved.
0
Write “1” Only Software RESET.
CR 07h. (Logical Device; Default 00h)
BIT
READ / WRITE
DESCRIPTION
DESCRIPTION
7~0
R / W
Logical Device Number.
CR 20h. (Chip ID, MSB; Read Only)
BIT
READ / WRITE
7~0
Read Only
Chip ID number = A2h (high byte).
CR 21h. (Chip ID, LSB; Read Only)
BIT
READ / WRITE
DESCRIPTION
7~0
Read Only
Chip ID number = 3xh (low byte). x is the IC version
CR 22h. (Device Power Down; Default FFh)
BIT
7
READ / WRITE
Reserved.
R / W
DESCRIPTION
6
HM Power Down.
0: Powered down 1: Not powered down
5
R / W
UARTB Power Down. 0: Powered down 1: Not powered down
UARTA Power Down. 0: Powered down 1: Not powered down
4
R / W
3
R / W
PRT Power Down.
0: Powered down 1: Not powered down
2~1 Reserved.
R / W
0
FDC Power Down.
0: Powered down 1: Not powered down
CR 23h. (IPD&Device Power Down; Default F0h)
BIT
7
READ / WRITE
R / W
DESCRIPTION
UARTF Power Down 0: Powered down 1: Not powered down
UARTE Power Down 0: Powered down 1: Not powered down
UARTD Power Down. 0: Powered down 1: Not powered down
6
R / W
5
R / W
Publication Release Date: May 25, 2007
Revision 1.0
-151-
W83627UHG
CR 23h. (IPD&Device Power Down; Default F0h), continued
BIT
READ / WRITE
DESCRIPTION
4
R / W
UARTC Power Down. 0: Powered down 1: Not powered down
3~1 Reserved.
R / W
IPD (Immediate Power Down). When set to 1, the whole chip is put into
power-down mode immediately.
0
CR 24h. (Global Option; Default 0100_0ss0b)
s: value by strapping
BIT
READ / WRITE
DESCRIPTION
7
Reserved.
CLKSEL => Input clock rate selection
6
5
4
R / W
Reserved.
R / W
= 0 The clock input on pin 18 is 24 MHz.
= 1 The clock input on pin 18 is 48 MHz. (Default)
Select output type of SYSFANOUT
=0 SYSFANOUT is Open-drain. (Default)
=1 SYSFANOUT is Push-pull.
Select output type of CPUFANOUT0
=0 CPUFANOUT is Open-drain. (Default)
=1 CPUFANOUT is Push-pull.
3
2
R / W
ENKBC => Enable keyboard controller
= 0 KBC is disabled after hardware reset.
= 1 KBC is enabled after hardware reset.
Read Only
This bit is read-only, and it is set or reset by a power-on strapping pin (Pin
54, SOUTA).
ENFDC => Enable FDC interface
= 0 FDC is enabled after hardware reset.
= 1 FDC is disabled after hardware reset.
This bit is set or reset by a power-on strapping pin (Pin 52, DTRA#).
Note 1
1
R / W
0
Reserved.
Note1:
Disable FDC interface
Pin 5 Æ CTSF#
Pin 6 Æ GP64
Enable FDC interface
Pin 5 Æ DRVDEN0
Pin 6 Æ INDEX#
Pin 7 Æ MOA#
Pin 7 Æ DSRF#
Pin 8 Æ RTSF#
Pin 8 Æ DSA#
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W83627UHG
Disable FDC interface
Pin 9 Æ DTRF#
Pin 10 Æ SINF
Pin 11Æ SOUTF
Pin 13 Æ DCDF#
Pin 14 Æ GP63
Pin 15 Æ GP62
Pin 16 Æ GP61
Pin 17Æ RIF#
Enable FDC interface
Pin 9 Æ DIR#
Pin 10 Æ STEP#
Pin 11Æ WD#
Pin 13 Æ WE#
Pin 14 Æ TRAK0#
Pin 15 Æ WP#
Pin 16 Æ RDATA#
Pin 17Æ HEAD#
Pin 18Æ DSKCHG#
Pin 18Æ GP60
CR 25h. (Interface Tri-state Enable; Default 00h)
BIT
READ / WRITE
DESCRIPTION
7~6 Reserved.
UARTBTRI =>
5
4
3
R / W
R / W
R / W
=0 Tri-state disabled
=1 Tri-state enabled
UARTATRI =>
=0 Tri-state disabled
=1 Tri-state enabled
PRTTRI =>
=0 Tri-state disabled
=1 Tri-state enabled
2~1 Reserved.
R / W
FDCTRI. =>
0
=0 Tri-state disabled
=1 Tri-state enabled
CR 26h. (Global Option; Default 0s000000b)
s: value by strapping
BIT
READ / WRITE
DESCRIPTION
7
Reserved.
HEFRAS =>
= 0 Write 87h to location 2E twice.
= 1 Write 87h to location 4E twice.
6
5
R / W
R / W
The corresponding power-on strapping pin is RTSA# (Pin 51).
LOCKREG =>
= 0 Enable R/W configuration registers.
= 1 Disable R/W configuration registers.
Publication Release Date: May 25, 2007
Revision 1.0
-153-
W83627UHG
CR 26h. (Global Option; Default 0s000000b), continued
BIT
READ / WRITE
DESCRIPTION
4
Reserved.
DSFDLGRQ =>
= 0 Enable FDC legacy mode for IRQ and DRQ selection. Then DO
register (base address + 2) bit 3 is effective when selecting IRQ.
3
2
1
0
R / W
R / W
R / W
R / W
= 1 Disable FDC legacy mode for IRQ and DRQ selection. Then DO
register (base address + 2) bit 3 is not effective when selecting IRQ.
DSPRLGRQ =>
= 0 Enable PRT legacy mode for IRQ and DRQ selection. Then DCR
register (base address + 2) bit 4 is effective when selecting IRQ.
= 1 Disable PRT legacy mode for IRQ and DRQ selection. Then DCR
register (base address + 2) bit 4 is not effective when selecting IRQ.
DSUALGRQ =>
= 0 Enable UART A legacy mode for IRQ selection. Then HCR register
(base address + 4) bit 3 is not effective when selecting IRQ.
= 1 Disable UART A legacy mode for IRQ selection. Then HCR register
(base address + 4) bit 3 is not effective when selecting IRQ.
DSUBLGRQ =>
= 0 Enable UART B legacy mode for IRQ selection. Then HCR register
(base address + 4) bit 3 is not effective when selecting IRQ.
= 1 Disable UART B legacy mode for IRQ selection. Then HCR register
(base address + 4) bit 3 is not effective when selecting IRQ.
CR 27h. (Reserved)
CR 28h. (Global Option; Default 00h)
BIT
READ / WRITE
DESCRIPTION
DSUFLGRQ =>
= 0 Enable UART F legacy mode for IRQ selection. Then HCR register
(base address + 4) bit 3 is not effective when selecting IRQ.
R/W
7
= 1 Disable UART F legacy mode for IRQ selection. Then HCR register
(base address + 4) bit 3 is not effective when selecting IRQ.
DSUELGRQ =>
= 0 Enable UART E legacy mode for IRQ selection. Then HCR register
(base address + 4) bit 3 is not effective when selecting IRQ.
6
R/W
= 1 Disable UART E legacy mode for IRQ selection. Then HCR register
(base address + 4) bit 3 is not effective when selecting IRQ.
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W83627UHG
CR 28h. (Global Option; Default 00h), continued
BIT
READ / WRITE
DESCRIPTION
DSUDLGRQ =>
= 0 Enable UART D legacy mode for IRQ selection. Then HCR register
(base address + 4) bit 3 is not effective when selecting IRQ.
5
R/W
= 1 Disable UART D legacy mode for IRQ selection. Then HCR register
(base address + 4) bit 3 is not effective when selecting IRQ.
DSUCLGRQ =>
= 0 Enable UART C legacy mode for IRQ selection. Then HCR register
(base address + 4) bit 3 is not effective when selecting IRQ.
4
R/W
= 1 Disable UART C legacy mode for IRQ selection. Then HCR register
(base address + 4) bit 3 is not effective when selecting IRQ.
3
Reserved.
R / W
PRTMODS2 ~ 0 =>
= 0xx Parallel Port Mode.
= 1xx Reserved.
2~0
CR 29h. (OVT#/HM_SMI#, PLED & GPIO3, 4, 5, 6 Output Type Select; Default 00h)
BIT
READ / WRITE
DESCRIPTION
Select output type of GPIO 6
7
R/W
=0 GPIO6 (pins 6, 14, 15, 16 & 18) are open-drain. (Default)
=1 GPIO6 are push-pull.
Pin 95 function select
= 0 OVT#
= 1 SMI#
6
5
4
3
R / W
R/W
R/W
R/W
Select output type of GPIO 5
= 0 GPIO 5 (pins 125 ~ 4) are open-drain. (Default)
= 1 GPIO 5 are push-pull.
Select output type of GPIO 4
= 0 GPIO 4 (pins 117 ~ 124) are open-drain. (Default)
= 1 GPIO 4 are push-pull.
Select output type of GPIO 3
= 0 GPIO 3 (pins 109 ~ 116) are open-drain. (Default)
= 1 GPIO 3 are push-pull.
Select Power LED mode.
00: Power LED pin is tri-stated.
2~1
0
R / W
01: Power LED pin is driven low.
10: Power LED pin outputs 1Hz pulse with 50% duty cycle.
11: Power LED pin outputs 1/4Hz pulse with 50% duty cycle.
Reserved.
Publication Release Date: May 25, 2007
Revision 1.0
-155-
W83627UHG
CR 2Ah. (I2C Pin Select; Default 00h)
BIT READ / WRITE
7~4 Reserved.
(VSB Power)
DESCRIPTION
SDA_filter_EN:
3
2
R/W
0: Enable SDA input to a filter
1: Disable SDA input to a filter
SCL_filter_EN:
0: Enable SCL input to a filter
R / W
1: Disable SCL input to a filter
Pin 69, Pin 70 function select (I2C interface)
= 0 Pin 69, 70 Æ GP25, GP26 (Default)
= 1 Pin 69, 70 Æ SDA, SCL
1
0
R / W
Reserved.
CR 2Bh. (Reserved)
CR 2Ch. (GPIO1 Multi-function and GPIO1, 2 Output Type Select; Default 02h)
(VSB Power)
BIT
READ / WRITE
DESCRIPTION
Select output type of GPIO 2
= 0 GPIO 2 (pins 108, 107, 106, 96, 94, 70, 69, 58) are open-drain.
(Default)
7
R / W
= 1 GPIO 2 are push-pull.
Select output type of GPIO 1
6
R / W
= 0 GPIO 1 (pins 78 ~ 85) are open-drain. (Default)
= 1 GPIO 1 are push-pull.
5~3 Reserved.
EN_PWRDN. (VBAT)
2
R / W
= 0 Disable thermal shutdown function.
= 1 Enable thermal shutdown function.
Pins 78 ~ 85 function select
Bit-1
Bit-0
Pins 78 ~ 85 function
Pin 82 Æ Reserved (tri-state)
0
0
Pin 83 Æ Reserved (always low)
Others Æ GPIO1
1~0
R / W
Pin 82 Æ IRRX
Pin 83 Æ IRTX
Others Æ GPIO1
0
1
1
1
0
1
Pins 78 ~ 85 Æ GPIO1
Pins 78 ~ 85 Æ UART B
CR 2Dh. (Default 00h)
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W83627UHG
BIT
READ / WRITE
DESCRIPTION
7
Reserved.
0: Enable GP27 input de-bouncer.
6
5
R / W
R / W
1: Disable GP27 input de-bouncer.
0: Enable GP26 input de-bouncer.
1: Disable GP26 input de-bouncer.
0: Enable GP25 input de-bouncer.
1: Disable GP25 input de-bouncer.
4
3
2
R / W
Reserved.
R / W
0: GP27 trigger type :edge
1: GP27 trigger type :level
0: GP26 trigger type :edge
1: GP26 trigger type :level
1
0
R / W
R / W
0: GP25 trigger type :edge
1: GP25 trigger type :level
CR 2Eh. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
7~0
R / W
Test Mode Bits: Reserved.
Test Mode Bits: Reserved.
CR 2Fh. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
DESCRIPTION
7~0
R / W
17.2 Logical Device 0 (FDC)
CR 30h. (Default 01h)
BIT
READ / WRITE
7~1 Reserved.
0: Logical device is inactive.
1: Logical device is active.
0
R / W
CR 60h, 61h. (Default 03h,F0h)
BIT
READ / WRITE
DESCRIPTION
These two registers select FDC I/O base address <100h : FF8h> on 8-
byte boundary.
7~0
R / W
Publication Release Date: May 25, 2007
-157-
Revision 1.0
W83627UHG
CR 70h. (Default 06h)
BIT READ / WRITE
7~4 Reserved.
3~0 R / W
DESCRIPTION
These bits select IRQ resource for FDC.
CR 74h. (Default 02h)
BIT READ / WRITE
7~3 Reserved.
DESCRIPTION
These bits select DRQ resource for FDC.
2~0
R / W
000: DMA0.
001: DMA1.
010: DMA2.
011: DMA3.
1xx: No DMA active.
CR F0h. (Default 8Eh)
BIT
READ / WRITE
DESCRIPTION
FIPURDWN
This bit controls the internal pulled-up resistors of the FDC input pins
RDATA#, INDEX#, TRAK0#, DSKCHG# and WP#.
7
R / W
0: The internal pulled-up resistors of FDC are turned on.
1: The internal pulled-up resistors of FDC are turned off. (Default)
This bit determines the polarity of all FDD interface signals.
0: FDD interface signals are active low.
6
R / W
1: FDD interface signals are active high.
When this bit is logic 0, it indicates a second drive is installed and is
reflected in status register A. (PS2 mode only)
5
4
R / W
R / W
R / W
R / W
R / W
Swap Drive 0, 1 Mode =>
0: No Swap.
1: Drive and Motor select 0 and 1 are swapped.
Interface Mode.
00: Model 30.
10: Reserved.
01: PS/2.
3~2
1
11: AT Mode
FDC DMA Mode.
Floppy Mode.
0: Burst Mode is enabled
1: Non-Burst Mode.
0: Normal Floppy Mode.
0
1: Enhanced 3-mode FDD.
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W83627UHG
CR F1h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
00: FDD A.
10: FDD C.
Boot Floppy.
01: FDD B.
11: FDD D.
7~6
R / W
Media ID1, Media ID0. These bits will be reflected on FDC’s Tape Drive
Register bit 7, 6.
5~4
3~2
R / W
R / W
Density Select.
00: Normal.
01 Normal.
10: 1 (Forced to logic 1).
11: 0 (Forced to logic 0).
DISFDDWR =>
1
0
R / W
R / W
0: Enable FDD write.
1: Disable FDD write (forces pins WE, WD stay high).
SWWP =>
0: Normal, use WP to determine whether the FDD is write protected or
not.
1: FDD is always write-protected.
CR F2h. (Default FFh)
BIT
7~6
5~4
3~2
1~0
READ / WRITE
R / W
DESCRIPTION
FDD D Drive Type.
R / W
FDD C Drive Type.
R / W
FDD B Drive Type.
R / W
FDD A Drive Type.
CR F4h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
7
Reserved.
0: Enable FDC Pre-compensation.
1: Disable FDC Pre-compensation.
6
5
R / W
Reserved.
Data Rate Table selection (Refer to TABLE A).
00: Select regular drives and 2.88 format.
4~3
R / W
01: 3-mode drive.
10: 2 Meg Tape.
11: Reserved.
2
Reserved.
R / W
1~0
Drive Type selection (Refer to TABLE B).
Publication Release Date: May 25, 2007
Revision 1.0
-159-
W83627UHG
CR F5h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
7~0
R / W
Same as FDD0 of CR F5h.
TABLE A
DRIVE RATE TABLE
SELECT
DATA RATE
SELECTED DATA RATE
SELDEN
DRTS1
DRTS0
DRATE1
DRATE0
MFM
1Meg
500K
300K
250K
1Meg
500K
500K
250K
1Meg
500K
2Meg
250K
FM
---
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
250K
150K
125K
---
0
0
250K
250K
125K
---
0
1
1
0
250K
---
125K
TABLE B
DTYPE0
DTYPE1
DRVDEN0 (pin 2)
SELDEN
DRVDEN1 (pin 3)
DRIVE TYPE
4/2/1 MB 3.5”“
2/1 MB 5.25”
0
0
DRATE0
2/1.6/1 MB 3.5” (3-MODE)
0
1
1
1
0
1
DRATE1
DRATE0
DRATE0
DRATE1
SELDEN
DRATE0
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W83627UHG
17.3 Logical Device 1 (Parallel Port)
CR 30h. (Default 01h)
BIT
READ / WRITE
DESCRIPTION
7~1 Reserved.
0: Logical device is inactive.
1: Logical device is active.
0
R / W
CR 60h, 61h. (Default 03h, 78h)
BIT
READ / WRITE
DESCRIPTION
These two registers select PRT I/O base address.
<100h : FFCh> on 4-byte boundary (EPP not supported) or
<100h : FF8h> on 8-byte boundary (all modes supported, EPP is only
available when the base address is on 8-byte boundary).
7~0
R / W
CR 70h. (Default 07h)
BIT READ / WRITE
7~4 Reserved.
3~0 R / W
DESCRIPTION
These bits select IRQ resource for PRT.
CR 74h. (Default 04h)
BIT READ / WRITE
7~3 Reserved.
DESCRIPTION
These bits select DRQ resource for PRT.
2~0
R / W
000: DMA0.
001: DMA1.
010: DMA2.
011: DMA3.
1xx: No DMA active.
CR F0h. (Default 3Fh)
BIT
7
READ / WRITE
Reserved.
R / W
DESCRIPTION
6~3
ECP FIFO Threshold.
Parallel Port Mode selection (CR28 bit2 PRTMODS2 = 0).
000: Standard and Bi-direction (SPP) mode.
001: EPP – 1.9 and SPP mode.
010: ECP mode.
2~0
R / W
011: ECP and EPP – 1.9 mode.
100: Printer Mode.
101: EPP – 1.7 and SPP mode.
110: Reserved.
111: ECP and EPP – 1.7 mode.
Publication Release Date: May 25, 2007
Revision 1.0
-161-
W83627UHG
17.4 Logical Device 2 (UART A)
CR 30h. (Default 01h)
BIT
READ / WRITE
DESCRIPTION
7~1 Reserved.
0: Logical device is inactive.
1: Logical device is active.
0
R / W
CR 60h, 61h. (Default 03h, F8h)
BIT
READ / WRITE
DESCRIPTION
These two registers select Serial Port 1 I/O base address <100h: FF8h>
on 8-byte boundary.
7~0
R / W
CR 70h. (Default 04h)
BIT READ / WRITE
7~4 Reserved.
3~0 R / W
DESCRIPTION
These bits select IRQ resource for Serial Port A.
CR F0h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
0: Delay RXCLK for 5 ns for LG issue.
1: No delay of 5 ns for RXCLK.
7
R / W
0: IRQ is the level mode.
1: IRQ is the pulse mode.
6
5
R / W
R / W
0: Using the original RX FIFO Error Indication signal (USR bit 7).
1: Using new RX FIFO Error Indication signal to solve some issues.
4~2 Reserved.
00: UART A clock source is 1.8462 MHz (24 MHz / 13).
01: UART A clock source is 2 MHz (24 MHz / 12).
00: UART A clock source is 24 MHz (24 MHz / 1).
00: UART A clock source is 14.769 MHz (24 MHz / 1.625).
1~0
R / W
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W83627UHG
17.5 Logical Device 3 (UART B)
CR 30h. (Default 01h)
BIT
READ / WRITE
DESCRIPTION
7~1 Reserved.
0: Logical device is inactive.
1: Logical device is active.
0
R / W
CR 60h, 61h. (Default 02h, F8h)
BIT
READ / WRITE
DESCRIPTION
These two registers select Serial Port 2 I/O base address <100h: FF8h>
on 8-byte boundary.
7~0
R / W
CR 70h. (Default 03h)
BIT READ / WRITE
7~4 Reserved.
3~0 R / W
DESCRIPTION
These bits select IRQ resource for Serial Port B.
CR F0h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
0: Delay RXCLK for 5 ns for LG issue.
1: No delay of 5 ns for RXCLK.
7
R / W
0: IRQ is the level mode.
1: IRQ is the pulse mode.
6
R / W
0: Using the original RX FIFO Error Indication signal (USR bit 7).
1: Using new RX FIFO Error Indication signal to solve some issues.
5
4
R / W
Reserved.
0: No reception delay when SIR is changed from TX mode to RX mode.
3
2
R / W
R / W
1: Reception delay 4 characters’ time (40 bit-time) when SIR is changed
from TX mode to RX mode.
0: No transmission delay when SIR is changed from RX mode to TX
mode.
1: Transmission delay 4 characters’ time (40 bit-time) when SIR is
changed from RX mode to TX mode.
00: UART B clock source is 1.8462 MHz (24 MHz / 13).
01: UART B clock source is 2 MHz (24 MHz / 12).
00: UART B clock source is 24 MHz (24 MHz / 1).
00: UART B clock source is 14.769 MHz (24 MHz / 1.625).
1~0
R / W
Publication Release Date: May 25, 2007
-163-
Revision 1.0
W83627UHG
CR F1h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
7
R / W
Reserved.
IRLOCSEL => IR I/O pins’ location selection.
0: Through SINB / SOUTB.
6
5~3
2
R / W
R / W
R / W
1: Through IRRX / IRTX.
IRMODE => IR function mode selection. See the table below.
IR half / full duplex function selection.
0: IR function is Full Duplex.
1: IR function is Half Duplex.
0: SOUTB pin of UART B function or IRTX pin of IR function is in normal
condition.
1
0
R / W
R / W
1: Inverse SOUTB pin of UART B function or IRTX pin of IR function.
0: SINB pin of UART B function or IRRX pin of IR function is in normal
condition.
1: Inverse SINB pin of UART B function or IRRX pin of IR function.
IR MODE
IR FUNCTION
IRTX
IRRX
00X
Disable
Tri-state
High
010*
011*
100
IrDA
IrDA
Demodulation into SINB/IRRX
Demodulation into SINB/IRRX
Routed to SINB/IRRX
Active pulse 1.6 μS
Active pulse 3/16 bit time
Inverting IRTX/SOUTB pin
ASK-IR
Inverting IRTX/SOUTB & 500
KHZ clock
101
110
ASK-IR
ASK-IR
ASK-IR
Routed to SINB/IRRX
Inverting IRTX/SOUTB
Demodulation into SINB/IRRX
Demodulation into SINB/IRRX
Inverting IRTX/SOUTB & 500
KHZ clock
111*
Note: The notation is normal mode in the IR function.
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W83627UHG
17.6 Logical Device 5 (Keyboard Controller)
CR 30h. (Default 01h)
BIT
READ / WRITE
DESCRIPTION
7~1 Reserved.
0: Logical device is inactive.
1: Logical device is active.
0
R / W
CR 60h, 61h. (Default 00h,60h)
BIT
READ / WRITE
DESCRIPTION
These two registers select the first KBC I/O base address <100h: FFFh>
on 1-byte boundary.
7~0
R / W
CR 62h, 63h. (Default 00h,64h)
BIT
READ / WRITE
DESCRIPTION
These two registers select the second KBC I/O base address <100h:
FFFh> on 1-byte boundary.
7~0
R / W
CR 70h. (Default 01h)
BIT READ / WRITE
7~4 Reserved.
3~0 R / W
DESCRIPTION
These bits select IRQ resource for KINT. (Keyboard interrupt)
CR 72h. (Default 0Ch)
BIT READ / WRITE
7~4 Reserved.
3~0 R / W
DESCRIPTION
These bits select IRQ resource for MINT. (PS/2 Mouse interrupt)
CR F0h. (Default 83h)
BIT
READ / WRITE
DESCRIPTION
KBC clock rate selection
00: 6MHz
7~6
R / W
01: 8MHz
10: 12MHz
11: 16MHz
5~3 Reserved.
Publication Release Date: May 25, 2007
-165-
Revision 1.0
W83627UHG
CR F0h. (Default 83h), continued
BIT
READ / WRITE
DESCRIPTION
0: Port 92 disabled.
1: Port 92 enabled.
2
R / W
0: Gate A20 software control.
1
0
R / W
R / W
1: Gate A20 hardware speed up.
0: KBRST software control.
1: KBRST hardware speeds up.
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W83627UHG
17.7 Logical Device 6 (UART C)
CR 30h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
7~1 Reserved.
0: Logical device is inactive.
1: Logical device is active.
0
R / W
CR 60h, 61h. (Default 03h, E0h)
BIT
READ / WRITE
DESCRIPTION
These two registers select Serial Port 1 I/O base address <100h : FF8h>
on 8-byte boundary.
7~0
R / W
CR 70h. (Default 04h)
BIT READ / WRITE
7~4 Reserved.
3~0 R / W
DESCRIPTION
These bits select IRQ resource for Serial Port C.
CR F0h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
0: Delay RXCLK for 5 ns for LG issue.
1: No delay of 5 ns for RXCLK.
7
R / W
0: IRQ is the level mode.
1: IRQ is the pulse mode.
6
5
R / W
R / W
0: Using the original RX FIFO Error Indication signal (USR bit 7).
1: Using new RX FIFO Error Indication signal to solve some issues.
4~2 Reserved.
00: UART C clock source is 1.8462 MHz (24 MHz / 13).
01: UART C clock source is 2 MHz (24 MHz / 12).
00: UART C clock source is 24 MHz (24 MHz / 1).
00: UART C clock source is 14.769 MHz (24 MHz / 1.625).
1~0
R / W
Publication Release Date: May 25, 2007
-167-
Revision 1.0
W83627UHG
17.8 Logical Device 7 (GPIO3, GPIO4)
CR 30h. (Default 03h)
BIT
READ / WRITE
DESCRIPTION
7~2 Reserved.
1
0
R / W
R / W
0: GPIO4 is inactive.
0: GPIO3 is inactive.
1: GPIO4 is active.
1: GPIO3 is active.
CR E0h. (GPIO3 I/O Register; Default FFh)
BIT
READ / WRITE
DESCRIPTION
GPIO3 I/O register
7~0
R / W
0: The respective GPIO3 PIN is programmed as an Output port
1: The respective GPIO3 PIN is programmed as an Input port.
CR E1h. (GPIO3 Data Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO3 Data register
R / W
For Output ports, the respective bits can be read and written by the pins.
7~0
For Input ports, the respective bits can be read only from pins. Write
accesses will be ignored.
Read Only
CR E2h. (GPIO3 Inversion Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO3 Inversion register
0: The respective bit and the port value are the same.
7~0
R / W
1: The respective bit and the port value are inverted. (Both Input & Output
ports)
CR E3h. (Status Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO3 Event Status
Bit 7-0 corresponds to GP37-GP30, respectively.
0 : No active edge(rising/falling) has been detected
1 : An active edge(rising/falling) has been detected
Reading the status bit clears it to 0.
Read Only
Read-Clear
7~0
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W83627UHG
CR E4h. (GPIO4 I/O Register; Default FFh)
BIT
READ / WRITE
DESCRIPTION
GPIO4 I/O register
7~0
R / W
0: The respective GPIO4 PIN is programmed as an Output port
1: The respective GPIO4 PIN is programmed as an Input port.
CR E5h. (GPIO4 Data Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO4 Data register
R / W
For Output ports, the respective bits can be read and written by the pins.
7~0
For Input ports, the respective bits can be read only from pins. Write
accesses will be ignored.
Read Only
CR E6h. (GPIO4 Inversion Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO4 Inversion register
0: The respective bit and the port value are the same.
7~0
R / W
1: The respective bit and the port value are inverted. (Both Input & Output
ports)
CR E7h. (Status Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO4 Event Status
Bits 7-0 correspond to GP47-GP40, respectively.
0 : No active edge(rising/falling) has been detected
1 : An active edge(rising/falling) has been detected
Reading the status bit clears it to 0.
Read Only
Read-Clear
7~0
Publication Release Date: May 25, 2007
Revision 1.0
-169-
W83627UHG
17.9 Logical Device 8 (WDTO#, PLED, GPIO5, 6 & GPIO Base Address)
CR 30h. (Default 02h)
BIT READ / WRITE
7~3 Reserved.
DESCRIPTION
2
1
0
R / W
R / W
R / W
0: GPIO6 is inactive.
0: GPIO5 is inactive.
1: GPIO6 is active.
1: GPIO5 is active.
0: WDTO# and PLED are inactive. 1: WDTO# and PLED are active.
CR 60h 61h. (Default 00h, 00h)
BIT
READ / WRITE
DESCRIPTION
These two registers select GPIO base address <100h: FF8h> on 4-byte
boundary.
7~0
R / W
CR E0h. (GPIO5 I/O Register; Default FFh)
BIT
READ / WRITE
DESCRIPTION
GPIO5 I/O register
7~0
R / W
0: The respective GPIO5 PIN is programmed as an Output port
1: The respective GPIO5 PIN is programmed as an Input port.
CR E1h. (GPIO5 Data Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO5 Data register
R / W
For Output ports, the respective bits can be read and written by the pins.
7~0
For Input ports, the respective bits can be read only from pins. Write
accesses will be ignored.
Read Only
CR E2h. (GPIO5 Inversion Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO5 Inversion register
0: The respective bit and the port value are the same.
7~0
R / W
1: The respective bit and the port value are inverted. (Both Input & Output
ports)
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CR E3h. (Status Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO5 Event Status
Bits 7-0 correspond to GP57-GP50, respectively.
0 : No active edge(rising/falling) has been detected
1 : An active edge(rising/falling) has been detected
Reading the status bit clears it to 0.
Read Only
Read-Clear
7~0
CR E4h. (GPIO6 I/O Register; Default FFh)
BIT
READ / WRITE
DESCRIPTION
GPIO6 I/O register
7~0
R / W
0: The respective GPIO6 PIN is programmed as an Output port
1: The respective GPIO6 PIN is programmed as an Input port.
CR E5h. (GPIO6 Data Register; Default 1Fh)
BIT
READ / WRITE
DESCRIPTION
GPIO6 Data register
R / W
For Output ports, the respective bits can be read and written by the pins.
7~0
For Input ports, the respective bits can be read only from pins. Write
accesses will be ignored.
Read Only
CR E6h. (GPIO6 Inversion Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO6 Inversion register
0: The respective bit and the port value are the same.
7~0
R / W
1: The respective bit and the port value are inverted. (Both Input & Output
ports)
CR E7h. (Status Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO6 Event Status
Bits 7-0 correspond to GP67-GP60, respectively.
0 : No active edge(rising/falling) has been detected
1 : An active edge(rising/falling) has been detected
Reading the status bit clears it to 0.
Read Only
Read-Clear
7~0
Publication Release Date: May 25, 2007
Revision 1.0
-171-
W83627UHG
CR F5h. (WDTO# and KBC P20 Control Mode Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
7~5 Reserved.
1000 times faster in WDTO# count mode.
0: Disable.
1: Enable.
4
R / W
(If bit-3 is Second Mode, the count mode is 1/1000 Sec.)
(If bit-3 is Minute Mode, the count mode is 1/1000 Min.)
Select WDTO# count mode.
0: Second Mode.
3
2
R / W
R / W
1: Minute Mode.
Enable the rising edge of KBC reset (P20) to issue time-out event.
0: Disable.
1: Enable.
Disable / Enable the WDTO# output low pulse to the KBRST# pin (PIN60)
1
0
R / W
0: Disable.
1: Enable.
Reserved.
CR F6h. (WDTO# Counter Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
Watch Dog Timer Time-out value. Writing a non-zero value to this
register causes the counter to load the value to Watch Dog Counter
and start counting down. If bits 7 and 6 of CR F7h are set, any
Mouse Interrupt or Keyboard Interrupt event will also cause the
reload of previously-loaded non-zero value to Watch Dog Counter
and start counting down. Reading this register returns current value
in Watch Dog Counter instead of Watch Dog Timer Time-out value.
7~0
R / W
00h: Time-out Disable
01h: Time-out occurs after 1 second/minute
02h: Time-out occurs after 2 second/minutes
03h: Time-out occurs after 3 second/minutes
……………………….......................................
FFh: Time-out occurs after 255 second/minutes
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CR F7h. (WDTO# Control & Status Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
Mouse interrupt reset watch-dog timer enable
0: Watchdog timer is not affected by mouse interrupt.
1: Watchdog timer is reset by mouse interrupt.
7
R / W
Keyboard interrupt reset watch-dog timer enable
6
5
R / W
0: Watchdog timer is not affected by keyboard interrupt.
1: Watchdog timer is reset by keyboard interrupt.
Write “1” Only Trigger WDTO# event. This bit is self-clearing.
WDTO# status bit
R / W
4
0: Watchdog timer is running.
Write “0” Clear
1: Watchdog timer issues time-out event.
3~0
R / W
These bits select IRQ resource for WDTO#. (02h for SMI# event.)
Publication Release Date: May 25, 2007
Revision 1.0
-173-
W83627UHG
17.10 Logical Device 9 (GPIO1, GPIO2 and SUSLED)
CR 30h. (Default 03h)
BIT
READ / WRITE
DESCRIPTION
7~2 Reserved.
1
0
R / W
R / W
0: GPIO2 is inactive.
0: GPIO1 is inactive.
1: GPIO2 is active.
1: GPIO1 is active.
CR E0h. (GPIO1 I/O Register; Default FFh)
BIT
READ / WRITE
DESCRIPTION
GPIO1 I/O register
7~0
R / W
0: The respective GPIO1 PIN is programmed as an Output port
1: The respective GPIO1 PIN is programmed as an Input port.
CR E1h. (GPIO1 Data Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO1 Data register
R / W
For Output ports, the respective bits can be read and written by the pins.
7~0
For Input ports, the respective bits can be read only from pins. Write
accesses will be ignored.
Read Only
CR E2h. (GPIO1 Inversion Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO1 Inversion register
0: The respective bit and the port value are the same.
7~0
R / W
1: The respective bit and the port value are inverted. (Both Input & Output
ports)
CR E3h. (Status Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO1 Event Status
Bits 7-0 correspond to GP17-GP10, respectively.
0 : No active edge(rising/falling) has been detected
1 : An active edge(rising/falling) has been detected
Reading the status bit clears it to 0.
Read Only
Read-Clear
7~0
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CR E4h. (GPIO2 I/O Register; Default FFh)
BIT
READ / WRITE
DESCRIPTION
GPIO2 I/O register
7~0
R / W
0: The respective GPIO2 PIN is programmed as an Output port
1: The respective GPIO2 PIN is programmed as an Input port.
CR E5h. (GPIO2 Data Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO2 Data register
R / W
For Output ports, the respective bits can be read and written by the pins.
7~0
For Input ports, the respective bits can be read only from pins. Write
accesses will be ignored.
Read Only
CR E6h. (GPIO2 Inversion Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO2 Inversion register
0: The respective bit and the port value are the same.
7~0
R / W
1: The respective bit and the port value are inverted. (Both Input & Output
ports)
CR E7h. (Status Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
GPIO2 Event Status
Bit 4-0 corresponds to GP24-GP20, respectively.
0 : No active edge(rising/falling) has been detected
1 : An active edge(rising/falling) has been detected
Reading the status bit clears it to 0.
Read Only
Read-Clear
7~0
CR F3h. (Suspend LED Mode Register; Default 00h)
(VBAT power)
BIT
READ / WRITE
DESCRIPTION
Select Suspend LED mode.
00: Suspend LED pin is driven low.
01: Suspend LED pin is tri-stated.
7~6
R / W
10: Suspend LED pin outputs 1Hz pulse with 50% duty cycle.
11: Suspend LED pin outputs 1/4Hz pulse with 50% duty cycle.
5~0 Reserved.
Publication Release Date: May 25, 2007
Revision 1.0
-175-
W83627UHG
17.11 Logical Device A (ACPI)
(CR30, CR70 are VCC powered; CRE0~F7 and CRFE are VRTC powered)
CR 30h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
7~1 Reserved.
0: Logical device is inactive.
1: Logical device is active.
0
R / W
CR 70h. (Default 00h)
BIT READ / WRITE
7~4 Reserved.
3~0 R / W
DESCRIPTION
These bits select IRQ resource for PME#.
CR E0h. (Default 01h) (VBAT Power)
BIT
READ / WRITE
DESCRIPTION
DIS_PSIN => Disable panel switch input to turn system power supply on.
0: PSIN# is wire-AND and connected to PSOUT#.
7
R / W
1: PSIN# is blocked and cannot affect PSOUT#.
Enable KBC wake-up
6
5
R / W
R / W
0: Disable keyboard wake-up function via PSOUT#.
1: Enable keyboard wake-up function via PSOUT#.
Enable Mouse wake-up
0: Disable mouse wake-up function via PSOUT#.
1: Enable mouse wake-up function via PSOUT#.
MSRKEY =>
3 keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1])
define the combinations of the mouse wake-up events. Please refer to the
following table for the details.
ENMDAT_UP MSRKEY MSXKEY
Wake-up event
1
1
x
x
1
0
Any button clicked or movement.
4
R / W
One click of either left or right MS
button.
0
0
0
0
0
1
0
1
1
1
0
0
One click of the MS left button.
One click of the MS right button.
Two clicks of the MS left button.
Two clicks of the MS right button.
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CR E0h. (Default 01h) (VBAT Power), continued
BIT
READ / WRITE
DESCRIPTION
3
Reserved.
Keyboard / Mouse swap enable
2
1
R / W
R / W
0: Normal mode.
1: Keyboard / Mouse ports are swapped.
MSXKEY =>
3 keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1])
define the combinations of the mouse wake-up events. Please refer to the
table in CRE0[4] for the details.
KBXKEY =>
0: Only the pre-determined key combination in sequence can wake up the
system.
0
R / W
1: Any character received from the keyboard can wake up the system.
CR E1h. (KBC Wake-Up Index Register; Default 00h) (VSB Power)
BIT
READ / WRITE
DESCRIPTION
Keyboard wake-up index register.
It is the index register of CRE2, which is the access window of keyboard
pre-determined key combination characters. The first set of wake up key
combination is in the range of 0x00 - 0x0E, the second set 0x30 – 0x3E,
and the third set 0x40 – 0x4E. Incoming key combination can be read
through 0x10 – 0x1E.
7~0
R / W
CR E2h. (KBC Wake-Up Data Register; Default FFh) (VSB Power)
BIT
READ / WRITE
DESCRIPTION
Keyboard wake-up data register.
7~0
R / W
It is the data register of the keyboard pre-determined key combination
characters, which is indexed by CRE1.
CR E3h. (Event Status Register; Default 08h)
BIT READ / WRITE
DESCRIPTION
7~6 Reserved.
Read Only
5
This event status is caused by VSB power off/on.
Read-Clear
Publication Release Date: May 25, 2007
Revision 1.0
-177-
W83627UHG
CR E3h. (Event Status Register; Default 08h), continued
BIT
READ / WRITE
DESCRIPTION
If E4[7] is 1 =>
This bit is 0: When power loss occurs and VSB power is on, it indicates
that the system power is turned on.
This bit is 1: When power loss occurs and VSB power is on, it indicates
that the system power is turned off.
Read Only
Read-Clear
4
If E4[7] is 0 => This bit is always 0.
Thermal shutdown status.
0: No thermal shutdown event is issued.
1: The thermal shutdown event is issued.
Read Only
Read-Clear
3
2
1
0
PSIN_STS
0: No PSIN event is issued.
1: The PSIN event is issued.
Read Only
Read-Clear
MSWAKEUP_STS => The bit is latched by the mouse wake-up event.
0: No mouse wake-up event is issued.
1: The mouse wake-up event is issued.
Read Only
Read-Clear
KBWAKEUP_STS => The bit is latched by the keyboard wake-up event.
0: No keyboard wake-up event is issued.
1: The keyboard wake-up event is issued.
Read Only
Read-Clear
CR E4h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
Disable / Enable power loss control function (LDA: CRE4[6:5]) for Intel
chipset. (VBAT)
0: Disable.
7
R / W
1: Enable.
Power-loss control bits => (VBAT)
00: System always turns off when it returns from the power-loss state.
01: System always turns on when it returns from the power-loss state.
10: System turns off / on when it returns from the power-loss state
depending on the state before the power loss.
6~5
R / W
11: User defines the state before power loss.(i.e. the last state set of
CRE6[4])
4
3
Reserved.
R / W
Keyboard wake-up options. (LRESET#)
0: Password or sequence hot keys programmed in the registers.
1: Any key.
Enable the hunting mode for all wake-up events set in CRE0. This bit is
cleared when any wake-up events is captured. (LRESET#)
0: Disable.
1: Enable.
2
R / W
1~0
Reserved.
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CR E5h. (GPIOs Reset Source Register; Default 00))
BIT
READ / WRITE
DESCRIPTION
GPIO 6 reset source control bit.
7
R / W
=0 Enable GPIO 6 reset source by LRESET#
=1 Disable GPIO 6 reset source by LRESET#
GPIO 5 reset source control bit.
6
5
4
3
R / W
R / W
R / W
R / W
=0 Enable GPIO 5 reset source by LRESET#
=1 Disable GPIO 5 reset source by LRESET#
GPIO 4 reset source control bit.
=0 Enable GPIO 4 reset source by LRESET#
=1 Disable GPIO 4 reset source by LRESET#
GPIO 3 reset source control bit.
=0 Enable GPIO 3 reset source by LRESET#
=1 Disable GPIO 3 reset source by LRESET#
GPIO 2 reset source control bit.
=0 Enable GPIO 2 reset source by LRESET#
=1 Disable GPIO 2 reset source by LRESET#
GP25~27 reset source control bit.
=0 LRESET#
2
R / W
=1 RSMRST#
1-0
Reserved.
CR E6h. (Default 1Ch)
BIT READ / WRITE
DESCRIPTION
ENMDAT => (VSB)
3 keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1])
define the combinations of the mouse wake-up events. Please refer to the
table in CRE0[4] for the details.
7
R / W
6
5
Reserved.
R / W
CASEOPEN Clear Control. (VSB)
Write 1 to this bit will clear CASEOPEN status. This bit will clear the status
itself. The function is the same as Index 46h bit 7 of H/W Monitor part.
Power-loss Last State Flag. (VBAT)
4
R / W
0: ON
1: OFF.
Publication Release Date: May 25, 2007
-179-
Revision 1.0
W83627UHG
CR E6h. (Default 1Ch), continued
BIT READ / WRITE
DESCRIPTION
PWROK_DEL (first stage) (VSB)
Set the delay time when rising from PWROK_LP to PWROK_ST.
0: 300 ~ 500 ms.
1: 200 ~ 300 ms.
3
R / W
PWROK_DEL (VSB)
Set the delay time when rising from PWROK_ST to PWROK.
2~1
0
R / W
00: No delay time.
10: 96 ms
01: Delay 32 ms
11: Delay 250 ms
PWROK_TRIG =>
Write 1 to re-trigger the PWROK signal from low to high.
R / W-Clear
CR E7h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
ENKD3 => (VSB)
Enable the third set of keyboard wake-up key combination. Its values are
accessed through keyboard wake-up index register (CRE1) and keyboard
wake-up data register (CRE2) at the index from 40h to 4eh.
0: Disable the third set of the key combinations.
7
R / W
1: Enable the third set of the key combinations.
ENKD2 => (VSB)
Enable the second set of keyboard wake-up key combination. Its values
are accessed through keyboard wake-up index register (CRE1) and
keyboard wake-up data register (CRE2) at the index from 30h to 3eh.
0: Disable the second set of the key combinations.
6
5
R / W
R / W
1: Enable the second set of the key combinations.
ENWIN98KEY => (VSB)
Enable Win98 keyboard dedicated key to wake-up the system via
PSOUT# when keyboard wake-up function is enabled.
0: Disable Win98 keyboard wake-up.
1: Enable Win98 keyboard wake-up.
EN_ONPSOUT (VBAT)
Disable/Enable to issue a 0.5s long PSOUT# pulse when the system
returns from the power-loss state and is supposed to be on as described
in CRE4[6:5], logic device A. (for SiS & VIA chipsets)
0: Disable.
4
3
R / W
R / W
1: Enable.
Select WDTO# reset source (VSB)
0: Watchdog timer is reset by LRESET#.
1: Watchdog timer is reset by PWROK.
2~1 Reserved.
R / W
Hardware Monitor RESET source select (VBAT)
0: PWROK.
0
1: LRESET#.
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CR E8h. (Reserved)
CR E9h. (Reserved.)
CR F2h. (Default 3Eh) (VSB Power)
BIT
7~1 Reserved.
R / W
READ / WRITE
DESCRIPTION
0
EN_PME =>
0: Disable PME.
1: Enable PME.
CR F3h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
7
Reserved.
PME status of the URC IRQ event.
Write 1 to clear this status.
6
5
4
3
2
1
0
R /W-Clear
R / W-Clear
R / W-Clear
R / W-Clear
R / W-Clear
R / W-Clear
R / W-Clear
PME status of the Mouse IRQ event.
Write 1 to clear this status.
PME status of the KBC IRQ event.
Write 1 to clear this status.
PME status of the PRT IRQ event.
Write 1 to clear this status.
PME status of the FDC IRQ event.
Write 1 to clear this status.
PME status of the URA IRQ event.
Write 1 to clear this status.
PME status of the URB IRQ event.
Write 1 to clear this status.
CR F4h. (Default 00h)
BIT READ / WRITE
7~6 Reserved.
DESCRIPTION
PME status of the URF IRQ event.
Write 1 to clear this status.
5
4
3
R / W-Clear
PME status of the URE IRQ event.
Write 1 to clear this status.
R / W-Clear
R / W-Clear
PME status of the HM IRQ event.
Write 1 to clear this status.
Publication Release Date: May 25, 2007
Revision 1.0
-181-
W83627UHG
CR F4h. (Default 00h), continued
BIT
READ / WRITE
DESCRIPTION
PME status of the WDTO# event.
2
R / W-Clear
Write 1 to clear this status.
PME status of the URD IRQ event.
Write 1 to clear this status.
1
0
R / W-Clear
R / W-Clear
PME status of the RIB event.
Write 1 to clear this status.
CR F6h. (Default 00h) (VSB Power)
BIT
READ / WRITE
DESCRIPTION
7
Reserved.
0: Disable PME interrupt of the URC IRQ event.
1: Enable PME interrupt of the URC IRQ event.
6
5
4
3
2
1
0
R / W
R / W
R / W
R / W
R / W
R / W
R / W
0: Disable PME interrupt of the Mouse IRQ event.
1: Enable PME interrupt of the Mouse IRQ event.
0: Disable PME interrupt of the KBC IRQ event.
1: Enable PME interrupt of the KBC IRQ event.
0: Disable PME interrupt of the PRT IRQ event.
1: Enable PME interrupt of the PRT IRQ event.
0: Disable PME interrupt of the FDC IRQ event.
1: Enable PME interrupt of the FDC IRQ event.
0: Disable PME interrupt of the URA IRQ event.
1: Enable PME interrupt of the URA IRQ event.
0: Disable PME interrupt of the URB IRQ event.
1: Enable PME interrupt of the URB IRQ event.
CR F7h. (Default 00h) (VSB Power)
BIT READ / WRITE
7~6 Reserved.
DESCRIPTION
0: Disable PME interrupt of the URF IRQ event.
1: Enable PME interrupt of the URF IRQ event.
5
4
3
R / W
R / W
R / W
0: Disable PME interrupt of the URE IRQ event.
1: Enable PME interrupt of the URE IRQ event.
0: Disable PME interrupt of the HM IRQ event.
1: Enable PME interrupt of the HM IRQ event.
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CR F7h. (Default 00h) (VSB Power), continued
BIT
READ / WRITE
DESCRIPTION
0: Disable PME interrupt of the WDTO# event.
1: Enable PME interrupt of the WDTO# event.
2
R / W
0: Disable PME interrupt of the URD IRQ event.
1: Enable PME interrupt of the URD IRQ event.
1
0
R / W
R / W
0: Disable PME interrupt of the RIB event.
1: Enable PME interrupt of the RIB event.
CR FEh. (GPIO2 Event Route Selection Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
7
R / W
Reserved.
0: Disable GP27 event route to PSOUT#.
1: Enable GP27 event route to PSOUT#.
6
5
R / W
R / W
0: Disable GP26 event route to PSOUT#.
1: Enable GP26 event route to PSOUT#.
0: Disable GP25 event route to PSOUT#.
1: Enable GP25 event route to PSOUT#.
4
3
2
R / W
Reserved.
R / W
0: Disable GP27 event route to PME#.
1: Enable GP27 event route to PME#.
0: Disable GP26 event route to PME#.
1: Enable GP26 event route to PME#.
1
0
R / W
R / W
0: Disable GP25 event route to PME#.
1: Enable GP25 event route to PME#.
Publication Release Date: May 25, 2007
Revision 1.0
-183-
W83627UHG
17.12 Logical Device B (Hardware Monitor)
CR 30h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
7~1 Reserved.
0: Logical device is inactive.
1: Logical device is active.
0
R / W
CR 60h, 61h. (Default 00h, 00h)
BIT
READ / WRITE
DESCRIPTION
These two registers select HM base address <100h : FFEh> on 2-byte
boundary.
7~0
R / W
CR 70h. (Default 00h)
BIT READ / WRITE
7~4 Reserved.
3~0 R / W
DESCRIPTION
These bits select IRQ resource for HM.
CR F0h. (Reserved.)
CR F1h. (Reserved.)
CR F2h. (Multi-function Select & FAN Strapping Status Register; Default 00h) (VCC Power)
BIT READ / WRITE DESCRIPTION
7~2 Reserved.
GPI_MUL strapping status.
This bit is strapped by pin 122 (SOUTD / GP42).
0: PIN 107,108 Æ BEEP, PLED
1
0
Read Only
Read Only
1: PIN 107,108 Æ GP20, GP21
FAN_SET strapping status.
This bit is strapped by pin 119 (RTSD# / GP45).
0: The initial speed is 100%.
1: The initial speed is 50%.
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17.13 Logical Device C (PECI, SST)
CR E0h. (Agent Configuration Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
Agt4EN (Agent 4 Enable Bit)
0: Agent 4 is disabled.
1: Agent 4 is enabled.
7
R / W
Agt3EN (Agent 3 Enable Bit)
0: Agent 3 is disabled.
1: Agent 3 is enabled.
6
5
4
R / W
R / W
R / W
Agt2EN (Agent 2 Enable Bit)
0: Agent 2 is disabled.
1: Agent 2 is enabled.
Agt1EN (Agent 1 Enable Bit)
0: Agent 1 is disabled.
1: Agent 1 is enabled.
RTD4 (Agent 4 Return Domain 1 Enable Bit, Functions only when CR E5h
bit 7 is set to 1)
3
2
1
0
R / W
R / W
R / W
R / W
0: Agent 4 always returns the relative temperature from domain 0.
1: Agent 4 always returns the relative temperature from domain 1.
RTD3 (Agent 3 Return Domain 1 Enable Bit, Functions only when CR E5h
bit 6 is set to 1)
0: Agent 3 always returns the relative temperature from domain 0.
1: Agent 3 always returns the relative temperature from domain 1.
RTD2 (Agent 2 Return Domain 1 Enable Bit, Functions only when CR E5h
bit 5 is set to 1)
0: Agent 2 always returns the relative temperature from domain 0.
1: Agent 2 always returns the relative temperature from domain 1.
RTD1 (Agent 1 Return Domain 1 Enable Bit, Functions only when CR E5h
bit 4 is set to 1)
0: Agent 1 always returns the relative temperature from domain 0.
1: Agent 1 always returns the relative temperature from domain 1.
(When CR E8 [3] is set to 1, this register is used to read the relative temperature of Agent 1 (Low
Byte)).
Note. Agent 1 ~ Agent 4 represent the addresses of PECI devices from 0x30h to 0x33h
respectively.
Publication Release Date: May 25, 2007
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CR E1h. (Agent 1 TControl Register; Default 48h)
BIT
READ / WRITE
DESCRIPTION
7
Reserved.
Agent 1 TBase must always be a positive value; a negative value will
introduce abnormal temperature response. (Note1)
6~0
R / W
(When CR E8 [3] is set to 1, this register is used to read the relative temperature of Agent 1 (High
Byte))
CR E2h. (Agent 2 TControl Register; Default 48h)
BIT
READ / WRITE
DESCRIPTION
7
Reserved.
Agent 2 TBase must always be a positive value; a negative value will
introduce abnormal temperature response. (Note1)
6~0
R / W
(When CR E8 [3] is set to 1, this register is used to read the relative temperature of Agent 2 (Low
Byte))
CR E3h. (Agent 3 TControl Register; Default 48h)
BIT
READ / WRITE
DESCRIPTION
7
Reserved.
Agent 3 TBase must always be a positive value; a negative value will
introduce abnormal temperature response. (Note1)
6~0
R / W
(When CR E8 [3] is set to 1, this register is used to read the relative temperature of Agent 2 (High
Byte))
CR E4h. (Agent 4 TControl Register; Default 48h)
BIT
READ / WRITE
DESCRIPTION
7
Reserved.
Agent 4 TBase must always be a positive value; a negative value will
introduce abnormal temperature response. (Note1)
6~0
R / W
(When CR E8 [3] is set to 1, this register is used to read the relative temperature of Agent 3 (Low
Byte))
Note1: TBase is a temperature reference based on the experiment of the processor actual
temperature. For more details, please refer to section 7.5.
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CR E5h. (PECI Domain Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
Agt4D1 (Agent 4 Domain 1 Enable Bit)
7
R / W
0: Agent 4 does not have domain 1.
1: Agent 4 has domain 1.
Agt3D1 (Agent 3 Domain 1 Enable Bit)
0: Agent 3 does not have domain 1.
1: Agent 3 has domain 1.
6
5
4
R / W
R / W
R / W
Agt2D1 (Agent 2 Domain 1 Enable Bit)
0: Agent 2 does not have domain 1.
1: Agent 2has domain 1.
Agt1D1 (Agent 1 Domain 1 Enable Bit)
0: Agent 1 does not have domain 1.
1: Agent 1 has domain 1.
3~2 Reserved.
Return High Temperature
0: The temperature of each Agent is returned from domain 0 or domain 1, which is
controlled by CRE0 bit 0~3.
1
R / W
1: Return the highest temperature in domain 0 and domain 1 of each
individual Agent.
0
Reserved.
(When CR E8 [3] is set to 1, this register is used to read the relative temperature of Agent 3 (High
Byte))
CR E6h. (Agent 4 Relative Temperature (Low Byte))
BIT
READ / WRITE
DESCRIPTION
7~0
Read Only
Agent 4 Relative Temperature (Low Byte)
Before reading this register, this must be set to 1 in CR E8[3]
CR E7h. (Agent 4 Relative Temperature (High Byte))
BIT
READ / WRITE
DESCRIPTION
7~0
Read Only
Agent 4 Relative Temperature (High Byte)
Before reading this register, this must be set to 1 in CR E8[3]
Publication Release Date: May 25, 2007
Revision 1.0
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CR E8h. (PECI Warning Flag Register; Default 00h)
BIT
READ / WRITE
DESCRIPTION
Agent 4 Alert Bit (When CR E8[3] is 0)
0: Agent 4 has valid FCS.
1: Agent 4 has invalid FCS in the previous 3 transactions.
7
R / W
Agent 4 Absent Bit (When CR E8[3] is 1)
0: Agent 4 is detected.
1: Agent 4 cannot be detected.
Agent 3 Alert Bit (When CR E8[3] is 0)
0: Agent 3 has valid FCS.
1: Agent 3 has invalid FCS in the previous 3 transactions.
6
5
4
R / W
R / W
R / W
Agent 3 Absent Bit (When CR E8[3] is 1)
0: Agent 3 is detected.
1: Agent 3 cannot be detected.
Agent 2 Alert Bit (When CR E8[3] is 0)
0: Agent 2 has valid FCS.
1: Agent 2 has invalid FCS in the previous 3 transactions.
Agent 2 Absent Bit (When CR E8[3] is 1)
0: Agent 2 is detected.
1: Agent 2 cannot be detected.
Agent 1 Alert Bit (When CR E8[3] is 0)
0: Agent 1 has valid FCS.
1: Agent 1 has invalid FCS in the previous 3 transactions.
Agent 1 Absent Bit (When CR E8[3])
0: Agent 1 is detected.
1: Agent 1 cannot be detected.
Bank Select. This bit is used in Bank index selection. The relative data
delivered over PECI interface and PECI Agent Absent Bit can be read
from the registers below by setting Bank selection.
Agt1RelTemp: CR E0 (Low Byte), CR E1 (High Byte)
Agt2RelTemp: CR E2 (Low Byte), CR E3 (High Byte)
Agt3RelTemp: CR E4 (Low Byte), CR E5 (High Byte)
Agt4RelTemp: CR E6 (Low Byte), CR E7 (High Byte)
Agent 4 Absent Bit: CR E8 bit 7
3
2
R / W
Agent 3 Absent Bit: CR E8 bit 6
Agent 2 Absent Bit: CR E8 bit 5
Agent 1 Absent Bit: CR E8 bit 4
Reserved.
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CR E8h. (PECI Warning Flag Register; Default 00h), continued
BIT
READ / WRITE
DESCRIPTION
PECI Speed Select.
00: The PECI speed is 1.5 MHz
01: The PECI speed is 750 KHz
10: The PECI speed is 375 KHz
11: The PECI speed is 187 KHz
1~0
R / W
BANK SELECT
CR E8 BIT 3 = 0
Agent Configuration Register
Agent 1 TBase Register
Agent 2 TBase Register
Agent 3 TBase Register
Agent 4 TBase Register
PECI Domain Register
Reserved
CR E8 BIT 3 = 1
CR E0
CR E1
CR E2
CR E3
CR E4
CR E5
CR E6
CR E7
Agt1RelTemp (Low Byte)
Agt1RelTemp (High Byte)
Agt2RelTemp (Low Byte)
Agt2RelTemp (High Byte)
Agt3RelTemp (Low Byte)
Agt3RelTemp (High Byte)
Agt4RelTemp (Low Byte)
Agt4RelTemp (High Byte)
Agent Absent Bit
Reserved
CR E8 (bit 4 ~ 7)
Agent Alert Bit
CR F1h. (SST Address Register; Default 48h)
BIT
READ / WRITE
DESCRIPTION
7~0
R / W
SST address
CR F2h. (SST Vendor ID Low Byte; Default 50h)
BIT
READ / WRITE
DESCRIPTION
SST Vendor ID Low Byte. (Note 2)
7~0
R / W
Publication Release Date: May 25, 2007
Revision 1.0
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CR F3h. (SST Vendor ID High Byte; Default 10h)
BIT
READ / WRITE
DESCRIPTION
DESCRIPTION
DESCRIPTION
7~0
R / W
SST Vendor ID High Byte. (Note 2)
CR FEh. (SST Device ID Low Byte; Default 23h)
BIT
READ / WRITE
7~0
R / W
SST Device ID Low Byte. (Note 3)
CR FFh. (SST Device ID High Byte; Default 5Ah)
BIT
READ / WRITE
7~0
R / W
SST Device ID High Byte. (Note 3)
Note 2: Vendor ID identifies the device from a specific vendor. The PCI SIG or TBA assigns the
contents of this value.
Note 3: This value is assigned by vendor and must be exclusive to that vendor and to the device. It
will be used in conjunction with the Vendor ID to associate the correct software driver with the
sensor.
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17.14 Logical Device D (UART D)
CR 30h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
7~1 Reserved.
0: Logical device is inactive.
1: Logical device is active.
0
R / W
CR 60h, 61h. (Default 02h, E0h)
BIT
READ / WRITE
DESCRIPTION
These two registers select Serial Port 1 I/O base address <100h : FF8h>
on 8-byte boundary.
7~0
R / W
CR 70h. (Default 03h)
BIT READ / WRITE
7~4 Reserved.
3~0 R / W
DESCRIPTION
These bits select IRQ resource for Serial Port D.
CR F0h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
0: Delay RXCLK for 5 ns for LG issue.
1: No delay of 5 ns for RXCLK.
7
R / W
0: IRQ is the level mode.
1: IRQ is the pulse mode.
6
5
R / W
R / W
0: Using the original RX FIFO Error Indication signal (USR bit 7).
1: Using new RX FIFO Error Indication signal to solve some issues.
4~2 Reserved.
00: UART D clock source is 1.8462 MHz (24 MHz / 13).
01: UART D clock source is 2 MHz (24 MHz / 12).
00: UART D clock source is 24 MHz (24 MHz / 1).
00: UART D clock source is 14.769 MHz (24 MHz / 1.625).
1~0
R / W
Publication Release Date: May 25, 2007
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17.15 Logical Device E (UART E)
CR 30h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
7~1 Reserved.
0: Logical device is inactive.
1: Logical device is active.
0
R / W
CR 60h, 61h. (Default 03h, E8h)
BIT
READ / WRITE
DESCRIPTION
These two registers select Serial Port 1 I/O base address <100h : FF8h>
on 8-byte boundary.
7~0
R / W
CR 70h. (Default 04h)
BIT READ / WRITE
7~4 Reserved.
3~0 R / W
DESCRIPTION
These bits select IRQ resource for Serial Port E.
CR F0h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
7
Reserved
0: IRQ is the level mode.
1: IRQ is the pulse mode.
6
5
R / W
R / W
0: Using the original RX FIFO Error Indication signal (USR bit 7).
1: Using new RX FIFO Error Indication signal to solve some issues.
4~2 Reserved.
00: UART E clock source is 1.8462 MHz (24 MHz / 13).
01: UART E clock source is 2 MHz (24 MHz / 12).
00: UART E clock source is 24 MHz (24 MHz / 1).
00: UART E clock source is 14.769 MHz (24 MHz / 1.625).
1~0
R / W
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17.16 Logical Device F (UART F)
CR 30h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
7~1 Reserved.
0: Logical device is inactive.
1: Logical device is active.
0
R / W
CR 60h, 61h. (Default 02h, E8h)
BIT
READ / WRITE
DESCRIPTION
These two registers select Serial Port 1 I/O base address <100h : FF8h>
on 8-byte boundary.
7~0
R / W
CR 70h. (Default 03h)
BIT READ / WRITE
7~4 Reserved.
3~0 R / W
DESCRIPTION
These bits select IRQ resource for Serial Port F.
CR F0h. (Default 00h)
BIT
READ / WRITE
DESCRIPTION
0: Delay RXCLK for 5 ns for LG issue.
1: No delay of 5 ns for RXCLK.
7
R / W
0: IRQ is the level mode.
1: IRQ is the pulse mode.
6
5
R / W
R / W
0: Using the original RX FIFO Error Indication signal (USR bit 7).
1: Using new RX FIFO Error Indication signal to solve some issues.
4~2 Reserved.
00: UART F clock source is 1.8462 MHz (24 MHz / 13).
01: UART F clock source is 2 MHz (24 MHz / 12).
00: UART F clock source is 24 MHz (24 MHz / 1).
00: UART F clock source is 14.769 MHz (24 MHz / 1.625).
1~0
R / W
Publication Release Date: May 25, 2007
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18. SPECIFICATIONS
18.1 Absolute Maximum Ratings
PARAMETER
Power Supply Voltage (5V)
Input Voltage
RATING
4.5 to 5.5
UNIT
V
-0.5 to 5VCC+0.5
3.0 to 3.6
V
RTC Battery Voltage VBAT
Operating Temperature
Storage Temperature
V
0 to +70
°C
°C
-55 to +150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
18.2 DC CHARACTERISTICS
(Ta = 0°C to 70°C, 5VCC = 5V ± 10%, VSS = 0V)
PARAMETER
SYM
MIN
TYP
MAX. UNIT
CONDITIONS
RTC Battery Quiescent Current
IBAT
2.4
VBAT = 2.5 V
μA
VSB = 5V, All
ACPI pins are
not
ACPI Stand-by Power Supply Quiescent
Current
IsB
2.0
mA
connected.
I/O12tp3 – 5V TTL level bi-directional pin with 12mA source-sink capability
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.8
V
V
2.0
2.4
0.4
V
IOL = 12 mA
IOH = -12 mA
VIN = 5V
V
+10
-10
μA
μA
VIN = 0V
I/O12ts - TTL level Schmitt-trigger bi-directional pin with 12mA source-sink capability
Input Low Threshold Voltage
Input High Threshold Voltage
Hysteresis
Vt-
Vt+
0.5
1.6
0.5
0.8
2.0
1.2
1.1
2.4
V
V
VTH
VOL
VOH
ILIH
ILIL
V
5VCC= 5V
IOL = 12 mA
IOH = -12 mA
VIN = 5V
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
0.4
V
2.4
V
+10
-10
μA
μA
VIN = 0V
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DC CHARACTERISTICS, continued
PARAMETER
SYM
MIN
TYP
MAX. UNIT
CONDITIONS
I/OD12t - TTL level bi-directional pin and open-drain output with 12mA sink capability
Input Low Voltage
Input High Voltage
Output Low Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
ILIH
ILIL
0.8
V
V
2.0
0.4
+10
-10
V
IOL = 12 mA
VIN = 5V
μA
μA
VIN = 0V
I/OD12ts - TTL level Schmitt-trigger bi-directional pin and open drain output with 12mA sink
capability
Input Low Threshold Voltage
Input High Threshold Voltage
Hysteresis
Vt-
Vt+
0.5
1.6
0.5
0.8
2.0
1.2
1.1
2.4
V
V
VTH
VOL
ILIH
ILIL
V
5VCC= 5V
IOL = 12 mA
VIN = 5V
Output Low Voltage
Input High Leakage
Input Low Leakage
0.4
+10
-10
V
μA
μA
VIN = 0V
I/OD12tsu - TTL level Schmitt-trigger bi-directional pin with internal pull-up resistor and open
drain output with 12mA sink capability
Input Low Threshold Voltage
Input High Threshold Voltage
Hysteresis
Vt-
Vt+
0.5
1.6
0.5
0.8
2.0
1.2
1.1
2.4
V
V
VTH
VOL
ILIH
ILIL
V
5VCC= 5V
IOL = 12 mA
VIN = 5V
Output Low Voltage
Input High Leakage
Input Low Leakage
0.4
+10
-10
V
μA
μA
VIN = 0V
I/OD16ts - TTL level Schmitt-trigger bi-directional pin and open drain output with 16mA sink
capability
Input Low Threshold Voltage
Input High Threshold Voltage
Hysteresis
Vt-
Vt+
0.5
1.6
0.5
0.8
2.0
1.2
1.1
2.4
V
V
VTH
VOL
ILIH
ILIL
V
5VCC= 5V
IOL = 16 mA
VIN = 5V
Output Low Voltage
Input High Leakage
Input Low Leakage
0.4
+10
-10
V
μA
μA
VIN = 0V
Publication Release Date: May 25, 2007
Revision 1.0
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W83627UHG
DC CHARACTERISTICS, continued
PARAMETER
SYM
MIN
TYP
MAX. UNIT
CONDITIONS
O8 - Output pin with 8mA source-sink capability
Output Low Voltage
Output High Voltage
VOL
VOH
0.4
0.4
V
V
IOL = 8 mA
IOH = -8 mA
2.4
O12 - Output pin with 12mA source-sink capability
Output Low Voltage
Output High Voltage
VOL
VOH
V
V
IOL = 12 mA
IOH = -12 mA
2.4
O24 - Output pin with 24mA source-sink capability
Output Low Voltage
Output High Voltage
VOL
VOH
0.4
0.4
V
V
IOL = 24 mA
IOH = -24 mA
2.4
O12p3 - 5V output pin with 12mA source-sink capability
Output Low Voltage
Output High Voltage
VOL
VOH
V
V
IOL = 12 mA
IOH = -12 mA
2.4
OD12 - Open drain output pin with 12mA sink capability
Output Low Voltage
OD24 - Open drain output pin with 24mA sink capability
VOL
0.4
0.4
V
V
IOL = 12 mA
IOL = 24 mA
Output Low Voltage
VOL
INt - TTL level input pin
Input Low Voltage
Input High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
ILIH
ILIL
0.8
V
V
2.0
+10
-10
VIN = 5V
VIN = 0 V
μA
μA
INtu - TTL level input pin with internal pull-up resistor
Input Low Voltage
Input High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
ILIH
ILIL
0.8
V
V
2.0
+10
-10
VIN = 5V
VIN = 0 V
μA
μA
INts
- TTL level Schmitt-trigger input pin
Input Low Threshold Voltage
Input High Threshold Voltage
Hysteresis
Vt-
Vt+
0.8
1.8
0.8
0.9
1.9
1.0
1.0
2.0
V
V
V
5VCC = 5V
5VCC = 5V
5VCC = 5V
VTH
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DC CHARACTERISTICS, continued
PARAMETER
SYM
ILIH
ILIL
MIN
TYP
MAX. UNIT
CONDITIONS
VIN = 5V
Input High Leakage
Input Low Leakage
+10
-10
μA
μA
VIN = 0 V
INtsu - TTL level Schmitt-trigger input pin with internal pull-up resistor
Input Low Threshold Voltage
Input High Threshold Voltage
Hystersis
Vt-
Vt+
VTH
ILIH
ILIL
0.8
1.8
0.8
0.9
1.9
1.0
1.0
2.0
V
V
5VCC = 5V
5VCC = 5V
5VCC = 5V
VIN = 5V
V
Input High Leakage
Input Low Leakage
+10
-10
μA
μA
VIN = 0 V
INtsp3 - 3.3V TTL level Schmitt-trigger input pin
Input Low Threshold Voltage
Input High Threshold Voltage
Hysteresis
Vt-
Vt+
VTH
ILIH
ILIL
0.5
1.6
0.5
0.8
2.0
1.2
1.1
2.4
V
V
5VCC = 5 V
5VCC = 5 V
5VCC = 5 V
VIN = 3.3 V
VIN = 0 V
V
Input High Leakage
Input Low Leakage
+10
-10
μA
μA
INcd
- CMOS level input pin with internal pull-down resistor
0.3
5VCC
Input Low Voltage
Input High Voltage
VIL
VIH
V
V
0.7
5VCC
Input High Leakage
Input Low Leakage
ILIH
ILIL
+10
-10
VIN = 5V
VIN = 0 V
μA
μA
I/OV3 – Bi-direction pin with source capability of 6 mA and sink capability of 1 mA for INTEL®
PECI
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Hysteresis
VIL
0.275Vtt
0.55Vtt
0.5Vtt
0.725Vtt
0.25Vtt
V
V
V
V
V
VIH
VOL
VOH
VHys
0.75Vtt
0.1Vt t
Publication Release Date: May 25, 2007
Revision 1.0
-197-
W83627UHG
DC CHARACTERISTICS, continued
PARAMETER
SYM
MIN
TYP
MAX. UNIT
CONDITIONS
I/OV4 – Bi-direction pin with source capability of 6 mA and sink capability of 1 mA for INTEL®
SST
Input Low Threshold Voltage
Input High Threshold Voltage
Input High Leakage
Input Low Leakage
Vt-
0.4
0.65
1.1
V
Vt+
ILIH
ILIL
VTH
0.75
V
+10
-10
VIN = 1.5 V
VIN = 0V
μA
μA
V
Hysteresis
0.15
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18.3 AC CHARACTERISTICS
18.3.1
Power On / Off Timing
PSON#
T3
T4
SUSB#
(Intel Chipset)
SUSB#
(Other Chipset)
PSOUT#
PSIN#
T2
T5
T1
5VSB
S0
S5
T1
64m
T2
T3
T4
282m
T5
Over 64m at
least
IDEAL TIMING (SEC)
16m
32m
Publication Release Date: May 25, 2007
Revision 1.0
-199-
W83627UHG
18.3.2
AC Power Failure Resume Timing
1. Logic device A CRE4 bit7 = “0” and CRE4 bits[6:5] are selected to “OFF” state
(“OFF” means always turn off or last state is off)
5VCC
PSOUT#
PSON#
SUSB#
RSMRST#
5VSB
ACLOSS
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2. Logic device A CRE4 bit7 = “0” and CRE4 bits[6:5] are selected to “ON” state
(“ON” means always turn on or last state is on)
5VCC
PSOUT#
PSON#
SUSB#
RSMRST#
5VSB
ACLOSS
Publication Release Date: May 25, 2007
Revision 1.0
-201-
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3. Logic device A CRE4 bit7 = “1” and CRE4 bits[6:5] are selected to “OFF” state
(“OFF” means always turn off or last state is off)
5VCC
PSOUT#
PSON#
T ? 4S
SUSB#
RSMRST#
5VSB
ACLOSS
-202-
W83627UHG
4. Logic device A CRE4 bit7 = “1” and CRE4 bits[6:5] are selected to “ON” state
(“ON” means always turn on or last state is on)
5VCC
PSOUT#
PSON#
SUSB#
RSMRST#
5VSB
ACLOSS
Publication Release Date: May 25, 2007
Revision 1.0
-203-
W83627UHG
** What’s the definition of last state when AC power failure?
1) Last state is “ON”
5VCC is falling to 3.75V and SUSB# keeps VIH 2.0V
5VCC
SUSB#
2) Last state is “OFF”
5VCC is falling to 3.75V and SUSB# keeps VIL 0.8V
5VCC
SUSB#
To prevent that VCC goes down faster than VSB in various ATX Power Supplies. W83627UHG add
the “user define mode” option for AC power loss pre-state. BIOS can set the pre-state that is “On” or
“Off” state, because the status of AC power resume depends on it.
Logical Device A, CR E4h
Power loss control bits => (VBAT)
00: System always turns off when come back from power loss state.
01: System always turns on when come back from power loss state.
10: System turns off / on when come back from power loss state depend
on the state before power loss.
6~5
R / W
11: User define the state before power loss.(The last state set at CRE6[4])
Logical Device A, CR E6h
Power loss Last State Flag. (VBAT)
4
R / W
0: ON
1: OFF
-204-
W83627UHG
18.3.3
Clock Input Timing
PARAMETER
48MHZ / 24MHZ
UNIT
MIN
MAX
300/500
55
Cycle to cycle jitter
Duty cycle
ps
%
45
t1
t2
t3
48MHZ / 24MHZ
TYP
PARAMETER
DESCRIPTION
Clock cycle time
UNIT
MAX
MIN
t1
t2
20.8 / 41.7
10 / 21
ns
ns
Clock high time/low time
9 / 19
Clock rising time/falling time
(0.4V~2.4V)
t3
3
ns
Publication Release Date: May 25, 2007
Revision 1.0
-205-
W83627UHG
18.3.4
PECI and SST Timing
SST / PECI
Logic - 1
Minimum tH1
Maximum tH1
tBIT
Next-bit
Previous bit
SST / PECI
Logic - 0
Minimum tH0
Maximum tH0
Previous bit
Next-bit
tBIT
SYMBOL
MIN
TYP
MAX
UNITS
μs
Client
0.495
0.495
500
250
tBIT
Originator
tH1
0.6
0.2
3/4
1/4
0.8
0.4
× tBIT
tH0
× t BIT
-206-
W83627UHG
18.3.5
SMBus Timing
TR
TLOW
TF
SMBCLK
THIGH
TSU:DAT
TSU:STO
THD:STA
TSU:STA
THD:DAT
SMBDAT
TBUF
P
S
S
P
18.3.6
Floppy Disk Drive Timing
FDC: Data rate = 1MB, 500KB, 300KB, 250KB/sec.
TYP.
PARAMETER
DIR# setup time to STEP#
DIR# hold time from STEP#
SYM.
TDST
TSTD
MIN.
MAX.
UNIT
µS
(NOTE 1)
1.0/1.6
/2.0/4.0
24/40
µS
/48/96
6.8/11.5
7/11.7
/14/28
7.2/11.9
STEP# pulse width
STEP# cycle width
INDEX# pulse width
RDATA# pulse width
WD# pulse width
TSTP
TSC
µS
mS
nS
nS
nS
/13.8/27.8
/14.2/28.2
NOTE 2
NOTE 2
NOTE 2
125/250
/417/500
TIDX
TRD
TWD
40
100/185
/225/475
125/210
/250/500
150/235
/275/525
Notes:
1. Typical values for T = 25°C and normal supply voltage.
2. Programmable from 0.5 mS through 32 mS as described in step rate table.
(Please refer to the description of the SPECIFY command set.)
Publication Release Date: May 25, 2007
Revision 1.0
-207-
W83627UHG
Step Rate Table
DATA RATE
SRT
1MB/S
500KB/S
300KB/S
250KB/S
0
1
8
16
15
…
2
26.7
25
32
30
…
4
7.5
…
…
E
F
…
1.0
0.5
3.33
1.67
1
2
Floppy Disk Driving Timing
TSTD
DIR#
TSTP
TDST
TSC
STEP#
TIDX
INDEX#
RDATA#
WD#
TRD
TWD
-208-
W83627UHG
18.3.7
UART/Parallel Port
PARAMETER
SYMBOL
TEST
MIN.
MAX.
UNIT
CONDITIONS
Delay from Stop to Set Interrupt
TSINT
9/16
Baud
Rate
TRINT
TIRS
9
1000
8/16
nS
Delay from IOR Reset Interrupt
Delay from Initial IRQ Reset to
Transmit Start
1/16
Baud
Rate
Delay from to Reset interrupt
THR
TSI
175
nS
9/16
16/16
Baud
Rate
Delay from Initial IOW to interrupt
Delay from Stop to Set Interrupt
TSTI
8/16
Baud
Rate
TIR
8
6
250
200
250
nS
nS
nS
Delay from IOR to Reset Interrupt
Delay from IOR to Output
TMWO
TSIM
Set Interrupt Delay from Modem
Input
18
TRIM
N
9
250
nS
Reset Interrupt Delay from IOR
Baud Divisor
216-1
100 pF Loading
UART Receiver Timing
Receiver Timing
SIN
(RECEIVER
INPUT DATA)
START
DATA BITS (5-8)
PARITY
STOP
TSINT
IRQ
(INTERNAL SIGNAL)
TSTI
IRQ#
(INTERNAL SIGNAL.
READ RECEIVER
BUFFER REGISTER)
Publication Release Date: May 25, 2007
Revision 1.0
-209-
W83627UHG
UART Transmitter Timing
SOUT
(SERIAL OUT)
START
START
STOP
(1-2)
TSTI
DATA BITS (5-8)
PARITY
TIRS
IRQ
(INTERNAL SIGNAL)
THR
TSI
THR
IOW#
(INTERNAL SIGNAL,
WRITE THR)
TIR
IOR#
(INTERNAL SIGNAL,
READ TIR)
18.3.7.1 Modem Control Timing
MODEM Control Timing
START
IOW#
(INTERNAL SIGNAL,
WRITE MCR)
TMWO
TMWO
RTS#, DTR#
CTS#, DSR#, DCD#
TSIM
TSIM
IRQ
TRIM
TRIM
(INTERNAL SIGNAL)
IOR#
(INTERNAL SIGNAL
READ MSR)
TSIM
RI#
-210-
W83627UHG
18.3.8
Parallel Port Mode Parameters
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
t1
100
nS
PD0-7, INDEX, STROBE, AUTOFD Delay from
IOW
t2
t3
60
nS
nS
IRQ Delay from ACK, nFAULT
105
IRQ Delay from IOW
IRQ Active Low in ECP and EPP Modes
t4
t5
200
300
105
nS
nS
ERROR Active to IRQ Active
PARAMETER
SYM.
t1
MIN.
TYP. MAX.
100
UNIT
nS
PD0-7, INDEX, STROBE, AUTOFD Delay from
IOW
t2
t3
60
nS
nS
IRQ Delay from ACK, nFAULT
105
IRQ Delay from IOW
IRQ Active Low in ECP and EPP Modes
t4
t5
200
300
105
nS
nS
ERROR Active to IRQ Active
Publication Release Date: May 25, 2007
Revision 1.0
-211-
W83627UHG
18.3.9
Parallel Port
18.3.9.1 Parallel Port Timing
IOW
t1
INIT, STROBE
AUTOFD, SLCTIN
PD<0:7>
ACK
t2
IRQ (SPP)
t3
t4
IRQ
(EPP or ECP)
nFAULT
(ECP)
ERROR
(ECP)
t5
t4
t2
IRQ
18.3.9.2 EPP Data or Address Read Cycle Timing Parameters
PARAMETER
WAIT Asserted to WRITE Deasserted
Deasserted to WRITE Modified
SYM.
MIN.
MAX.
UNIT
t14
0
185
nS
t15
t17
60
60
190
180
nS
nS
WAIT Asserted to PD Hi-Z
Command Asserted to PD Valid
Command Deasserted to PD Hi-Z
t18
t19
t20
0
0
nS
nS
nS
60
190
WAIT Deasserted to PD Drive
WRITE Deasserted to Command
t21
1
nS
-212-
W83627UHG
EPP Data or Address Read Cycle Timing Parameters, continued
PARAMETER
SYM.
t22
MIN.
0
MAX.
20
UNIT
nS
PBDIR Set to Command
PD Hi-Z to Command Asserted
Asserted to Command Asserted
t23
0
30
nS
t24
0
195
180
nS
t25
60
nS
WAIT Deasserted to Command Deasserted
Time out
t26
t27
10
0
12
nS
nS
PD Valid to WAIT Deasserted
PD Hi-Z to WAIT Deasserted
PARAMETER
t28
0
μS
SYM.
MIN.
MAX.
UNIT
t1
t2
t3
t4
t5
40
0
nS
nS
nS
Ax Valid to IOR Asserted
IOCHRDY Deasserted to IOR Deasserted
IOR Deasserted to Ax Valid
10
40
0
10
24
IOR Deasserted to
or IOR Asserted
IOW
nS
IOR Asserted to IOCHRDY Asserted
PD Valid to SD Valid
t6
t7
0
0
75
40
nS
μS
nS
nS
IOR Deasserted to SD Hi-Z (Hold Time)
SD Valid to IOCHRDY Deasserted
t8
t9
0
85
60
160
WAIT Deasserted to IOCHRDY Deasserted
PD Hi-Z to PDBIR Set
t10
t13
0
0
nS
nS
WRITE Deasserted to IOR Asserted
WAIT Asserted to WRITE Deasserted
Deasserted to WRITE Modified
IOR Asserted to PD Hi-Z
t14
t15
t16
t17
0
60
0
185
190
50
nS
nS
nS
nS
60
180
WAIT Asserted to PD Hi-Z
Command Asserted to PD Valid
Command Deasserted to PD Hi-Z
t18
t19
t20
0
0
nS
nS
nS
60
190
WAIT Deasserted to PD Drive
t21
1
nS
WRITE Deasserted to Command
PBDIR Set to Command
t22
t23
t24
0
0
0
20
30
nS
nS
nS
PD Hi-Z to Command Asserted
Asserted to Command Asserted
195
Publication Release Date: May 25, 2007
Revision 1.0
-213-
W83627UHG
EPP Data or Address Read Cycle Timing Parameters, continued
PARAMETER
SYM.
MIN.
MAX.
UNIT
t25
60
180
nS
WAIT Deasserted to Command Deasserted
Time out
t26
t27
10
0
12
nS
nS
PD Valid to WAIT Deasserted
PD Hi-Z to WAIT Deasserted
t28
0
μS
18.3.9.3 EPP Data or Address Read Cycle (EPP Version 1.9)
EPP Data or Address Read Cycle (EPP Version 1.9)
t14
t15
STB# / WRITE
PD<0:7>
t17
t18
t19
t20
t21
t23
t25
t24
ADDRSTB
DATASTB
t27
t28
BUSY / WAIT
-214-
W83627UHG
18.3.9.4 EPP Data or Address Read Cycle (EPP Version 1.7)
EPP Data or Address Read Cycle (EPP Version 1.7)
t14
t15
STB# / WRITE
t17
t18
t19
t20
PD<0:7>
t21
t23
t25
t24
ADDRSTB
DATASTB
t27
t28
BUSY / WAIT
Publication Release Date: May 25, 2007
Revision 1.0
-215-
W83627UHG
18.3.9.5 EPP Data or Address Write Cycle Timing Parameters
PARAMETER
PBDIR Low to WRITE Asserted
WAIT Asserted to WRITE Asserted
WAIT Asserted to WRITE Change
SYM.
MIN.
MAX.
UNIT
t10
0
-
nS
t11
t12
t14
60
60
0
185
185
-
nS
nS
nS
WAIT Asserted to PD Invalid
PD Invalid to Command Asserted
t15
t17
10
60
-
nS
nS
210
WAIT Asserted to Command Asserted
t18
t19
t20
t21
t1
60
0
190
10
12
-
nS
WAIT Deasserted to Command Deasserted
μS
Command Asserted to WAIT Deasserted
Time out
10
0
μS
nS
Command Deasserted to WAIT Asserted
40
-
nS
Ax Valid to IOW Asserted
SD Valid to Asserted
t2
t3
10
10
-
-
nS
nS
IOW Deasserted to Ax Invalid
t4
t5
0
10
40
0
-
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
WAIT Deasserted to IOCHRDY Deasserted
Command Asserted to WAIT Deasserted
IOW Deasserted to IOW or IOR Asserted
IOCHRDY Deasserted to IOW Deasserted
WAIT Asserted to Command Asserted
IOW Asserted to WAIT Asserted
PBDIR Low to WRITE Asserted
t6
-
t7
24
160
70
-
t8
60
0
t9
t10
t11
t12
t13
t14
0
60
60
0
185
185
50
-
WAIT Asserted to WRITE Asserted
WAIT Asserted to WRITE Change
IOW Asserted to PD Valid
0
WAIT Asserted to PD Invalid
PD Invalid to Command Asserted
t15
t16
10
5
-
nS
nS
35
IOW to Command Asserted
t17
t18
t19
t20
t21
t22
60
60
0
210
190
10
12
-
nS
nS
μS
WAIT Asserted to Command Asserted
WAIT Deasserted to Command Deasserted
Command Asserted to WAIT Deasserted
Time out
10
0
μS
nS
Command Deasserted to WAIT Asserted
0
-
nS
IOW Deasserted to WRITE Deasserted and PD
invalid
t16
5
35
nS
WRITE
to Command Asserted
-216-
W83627UHG
18.3.9.6 EPP Data or Address Write Cycle (EPP Version 1.9)
EPP Data or Address Write Cycle (EPP Version 1.9)
t11
t10
t12
t14
STB# / WRITE
PD<0:7>
t15
t16
t18
t17
ADDRSTB
DATASTB
t19
t21
BUSY / WAIT
PBDIR
t22
Publication Release Date: May 25, 2007
Revision 1.0
-217-
W83627UHG
18.3.9.7 EPP Data or Address Write Cycle (EPP Version 1.7)
EPP Data or Address Write Cycle (EPP Version 1.7)
t11
t10
STB# / WRITE
PD<0:7>
t15
t16
t18
t17
DATAST
ADDRSTB
t19
BUSY / WAIT
18.3.9.8 Parallel Port FIFO Timing Parameters
PARAMETER
DATA Valid to nSTROBE Active
nSTROBE Active Pulse Width
DATA Hold from nSTROBE Inactive
BUSY Inactive to PD Inactive
SYMBOL
MIN.
600
600
450
80
MAX.
UNIT
nS
t1
t2
t3
t4
t5
t6
-
-
nS
-
nS
-
-
nS
BUSY Inactive to nSTROBE Active
nSTROBE Active to BUSY Active
680
-
nS
500
nS
-218-
W83627UHG
18.3.9.9 Parallel FIFO Timing
t4
t3
PD<0:7>
STB#
t1
t2
t5
t6
BUSY
18.3.9.10 ECP Parallel Port Forward Timing Parameters
PARAMETER
SYMBOL
MIN.
MAX.
60
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nAUTOFD Valid to nSTROBE Asserted
PD Valid to nSTROBE Asserted
t1
t2
t3
t4
t5
t6
t7
t8
0
0
60
BUSY Deasserted to nAUTOFD Changed
BUSY Deasserted to PD Changed
80
80
0
180
180
-
nSTROBE Deasserted to BUSY Deasserted
BUSY Deasserted to nSTROBE Asserted
nSTROBE Asserted to BUSY Asserted
BUSY Asserted to nSTROBE Deasserted
80
0
200
-
80
180
Publication Release Date: May 25, 2007
Revision 1.0
-219-
W83627UHG
18.3.9.11 ECP Parallel Port Forward Timing
t3
t4
nAUTOFD
PD<0:7>
t1
t2
t6
t8
STB#
t5
t5
t7
BUSY
18.3.9.12 ECP Parallel Port Reverse Timing Parameters
PARAMETER
PD Valid to nACK Asserted
SYMBOL
MIN.
0
MAX.
UNIT
nS
t1
t2
t3
t4
t5
t6
-
nAUTOFD Deasserted to PD Changed
nAUTOFD Asserted to nACK Asserted
nAUTOFD Deasserted to nACK Deasserted
nACK Deasserted to nAUTOFD Asserted
PD Changed to nAUTOFD Deasserted
0
-
-
nS
0
nS
0
-
nS
80
80
200
200
nS
nS
-220-
W83627UHG
18.3.9.13 ECP Parallel Port Reverse Timing
t2
PD<0:7>
t1
t3
t4
nACK
t5
t6
t5
nAUTOFD
18.3.10 KBC Timing Parameters
NO.
T1
DESCRIPTION
MIN.
MAX.
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
μS
μS
μS
μS
μS
Address Setup Time from WRB
Address Setup Time from RDB
WRB Strobe Width
0
0
-
-
T2
T3
20
20
0
-
T4
RDB Strobe Width
-
T5
Address Hold Time from WRB
Address Hold Time from RDB
Data Setup Time
-
T6
0
-
T7
50
0
-
T8
Data Hold Time
-
T9
Gate Delay Time from WRB
RDB to Drive Data Delay
RDB to Floating Data Delay
Data Valid After Clock Falling (SEND)
K/B Clock Period
10
-
30
40
20
4
-
T10
T11
T12
T13
T14
T15
T16
0
-
20
10
4
K/B Clock Pulse Width
-
Data Valid Before Clock Falling (RECEIVE)
K/B ACK After Finish Receiving
-
20
-
Publication Release Date: May 25, 2007
Revision 1.0
-221-
W83627UHG
KBC Timing Parameters, continued
NO.
DESCRIPTION
MIN.
-
MAX.
2
UNIT
mS
μS
T19
T20
T21
T22
T23
T24
Transmit Timeout
Data Valid Hold Time
0
-
63
30
30
5
167
50
50
25
nS
Input Clock Period (6−16 Mhz)
Duration of CLK inactive
Duration of CLK active
μS
μS
μS
Time from inactive CLK transition, used to time when
the auxiliary device sample DATA
T25
T26
T27
T28
T29
Time of inhibit mode
100
5
300
T28-5
50
μS
μS
μS
μS
μS
Time from rising edge of CLK to DATA transition
Duration of CLK inactive
30
30
5
Duration of CLK active
50
Time from DATA transition to falling edge of CLK
25
18.3.10.1 Writing Cycle Timing
A2, CSB
T1
T3
T5
WRB
ACTIVE
T7
T8
D0 ~ D7
DATA IN
T9
GA20
OUTPUT
PORT
-222-
W83627UHG
18.3.10.2 Read Cycle Timing
A2, CSB
AEN
T6
T2
T4
RDB
ACTIVE
T11
T10
D0 ~ D7
DATA OUT
18.3.10.3 Send Data to K/B
CLOCK
(KCLK)
T14
T13
D4
T26
T12
SERIAL DATA
START D0
D1
D2
D3
D5
D6
D7
P
STOP
(KDAT)
18.3.10.4 Receive Data from K/B
CLOCK
(KCLK)
T14
T13
T15
SERIAL DATA
START D0
D1
D2
D3
D4
D5
D6
D7
P
STOP
(T1)
T20
Publication Release Date: May 25, 2007
Revision 1.0
-223-
W83627UHG
18.3.10.5 Input Clock
CLOCK
T21
18.3.10.6 Send Data to Mouse
MCLK
T25
T23
T24
D6
T22
D2
START
MDAT
D0
D1
D3
D4
D5
D7
P
Bit
STOP
Bit
18.3.10.7 Receive Data from Mouse
MCLK
T27
T26
T29
T28
D4
MDAT
START
D0
D1
D2
D3
D5
D6
D7
P
STOP
Bit
18.3.11 GPIO Timing Parameters
SYMBOL
tWGO
PARAMETER
Write data to GPIO update
SWITCH pulse width
MIN.
-
MAX.
UNIT
ns
300(Note 1)
-
tSWP
16
msec
Note: Refer to Microprocessor Interface Timing for Read Timing.
-224-
W83627UHG
18.3.11.1 GPIO Write Timing
GPIO Write Timing diagram
A0 – A15
VALID
IOW
D0-7
VALID
GPIO 10-17
PREVIOUS STATE
VALID
GPIO 20-25
tWGO
18.4 LRESET Timing
LRESET Timing
Vcc
MR
tVMR
Publication Release Date: May 25, 2007
Revision 1.0
-225-
W83627UHG
19. TOP MARKING SPECIFICATION
inbond
W83627UHG
606G9A28201234UB
1st line: Winbond logo
2nd line: part number: W83627UHG (Pb-free package)
3rd line: tracking code 606G9A28201234UB
606: packages made in '06, week 06
G: assembly house ID; G means GR, A means ASE ... etc.
9: code version; 9 means code 009
A: IC revision; A means version A, B means version B
28201234: wafer production series lot number
UB: Winbond internal use.
-226-
W83627UHG
20. PACKAGE SPECIFICATION
Dimension in mm
Dimension in inch
HE
E
Symbol
Min
0.25
2.57
Nom
0.35
Max
0.45
2.87
Min Nom Max
0.010 0.014 0.018
0.101 0.107 0.113
65
102
1
A
2
A
2.72
64
103
0.10
0.10
0.20
0.15
0.30
0.20
0.004 0.008 0.012
0.004 0.006 0.008
0.547 0.551 0.555
b
c
D
E
e
13.90
19.90
14.00
20.00
0.50
14.10
20.10
0.783 0.787 0.791
0.020
HD
D
D
H
17.20
23.20
0.669 0.677 0.685
0.905 0.913 0.921
17.40
23.40
0.95
17.00
23.00
H
E
0.80
1.60
0.025 0.031 0.037
0.063
L
L
y
0.65
39
128
1
0.08
7
1
38
0.003
e
b
0
7
0
0
c
Note:
A
1.Dimension D & E do not include interlead
flash.
A2
2.Dimension b does not include dambar
protrusion/intrusion
.
3.Controlling dimension : Millimeter
4.General appearance spec. should be based
on final visual inspection spec.
A1
See Detail F
Seating Plane
L
y
L1
Detail F
5. PCB layout please use the "mm".
(128-pin (QFP)
Publication Release Date: May 25, 2007
Revision 1.0
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W83627UHG
APPENDIX – ABBREVIATIONS
A
G
ACLOSS – AC power failure
GPIO – General-purpose Input and Output
ACPI – Advanced Configuration and Power
Interface
H
ADC – Analog Digital Converter
HM – Hardware Monitor
ASK-IR – Amplitude Shift Keyed IR
ATX – Advanced Technology Extended
HSR – Handshake Status Register
I
I2C – Inter-Integrated Circuit
INIT# – Initialization (PRT Port)
IOH – High Output Leakage
IOL – Low Output Leakage
IR – Infrared
B
BPP – Bi-directional Parallel Port
BIOS – Basic Input/Output System
C
CRC – Cyclic Redundancy Check
CLKSEL – Clock Select
CTS – Clear to Send
IrDA – Infrared Data Association
IRQ – Interrupt
IRRX – Infrared Receiver
IRTX – Infrared Transmitter
ISA – Industry Standard Architecture
ISR – Interrupt Service Routine
D
DCD – Data Carrier Detect
DMA – Direct Memory Access
DR Register – Data Rate Register
DSR – Data Set Ready
DTR – Data Terminal Ready
K
KBRESET – Keyboard Reset
KCLK – Keyboard Clock
KDAT – Keyboard Data
KINT – Keyboard Interrupt
E
ECP – Extended Capabilities Port
EPP – Enhanced Parallel Port
L
LAD – LPC Address and Data
LCLK – PCI Clock
F
FCS – Frame Check Sequence
FDC – Floppy Disk Controller
FDD – Floppy Disk Drive
FIFO – First-in First-out buffer
LD – Logical Device
LDRQ# – LPC DMA Request
LFRAME# – LPC Frame
LPC – Low Pin Count
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W83627UHG
LRESET# – LPC Reset
R/W – Read / Write
RI – Ring Indicator
LSB – Least Significant Bit (Byte)
RLE – Run Length Encoding/ Expanding
RPM – Revolutions per Minute
RSMRST# – Resume Reset
RTC – Real Time Clock
M
MCLK – Mouse Clock
MDAT – Mouse Data
MIDI – Musical Instrument Digital Interface
MINT – Mouse Interrupt
MSB – Most Significant Bit (Byte)
RTS – Request to Send
S
S/W Reset – Software Reset
SCL – Serial Clock
O
OVT# – Over Temperature
SDA – Serial Data
SERIRQ – Serialized IRQ
SLCT – Select Status
P
PANSWIN# – Panel Switch Input
PANSWOUT# – Panel Switch Output
PC – Personal Computer
SLIN – Select Input
SMI# - System Management Interrupt
SPP – Standard Parallel Port
SST – Simple Serial Transport
SYSFANIN – System Fan Input
SYSTIN – System Temperature Input
PCI
SIG
–
Peripheral
Component
Interconnect Special Interest Group
PD – Parallel Port Data
PDRQ – Parallel Port DMA Request
PE – Paper End
T
PECI
–
Platform Environment Control
Tcontrol: a temperature spec. based on a
temperature from the thermal diode
Interface
PLED – Power LED
TTL – Transistor-Transistor Logic
PME – Power Management Event
PnP – Plug and Play
U
PRT – Printer
UART – Universal Asynchronous Receiver/
Transmitter
PS/2 – IBM Personal System/2
PSIN_STS – PSIN# Status
PWM – Pulse Width Modulation
PWROK – Power OK
V
VSB – Standby Supply Voltage
VSS – GND
Q
W
QFP – Quad Flat Package
WDTO# – Watch Dog Timer Output
R
Publication Release Date: May 25, 2007
-229-
Revision 1.0
W83627UHG
Please note that all data and specifications are subject to change without notice. All the trade marks
of products and companies mentioned in this data sheet belong to their respective owners.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation wherein personal injury, death or severe property
or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
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