W83977TF-PW [WINBOND]
I/O chip disk drive adapter; I / O芯片磁盘驱动器适配器
| 型号： | W83977TF-PW |
| 厂家： | 
WINBOND |
| 描述： | I/O chip disk drive adapter |
| 文件： | 总154页 (文件大小：802K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W83877TF
WINBOND I/O
W83877TF
WINBOND I/O
GENERAL DESCRIPTION
The W83877TF is an enhanced version from Winbond's most popular I/O chip W83877F --- which
integrates the disk drive adapter, serial port (UART), IrDA 1.0 SIR, parallel port, configurable Plug-
and-Play registers for the whole chip --- plus additional powerful features: ACPI / legacy power
management, serial IRQ, and IRQ sharing.
The disk drive adapter functions of W83877TF include a floppy disk controller compatible with the
industry standard 82077/765, data separator, write pre-compensation circuit, decode logic, data rate
selection, clock generator, drive interface control logic, interrupt and DMA logic. The wide range of
functions integrated into the W83877TF greatly reduces the number of components required for
interfacing with floppy disk drives. The W83877TF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M
disk drives and data transfer rates of 250 Kb/S, 300 Kb/S, 500 Kb/S,1 Mb/S, and 2 Mb/S.
The W83877TF provides two high-speed serial communication ports (UARTs), one of which supports
serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable
baud rate generator, complete modem control capability, and a processor interrupt system. One of
the UARTs support infrared (IR) IrDA1.0. Both UARTs provide legacy speed with baud rate up to
115.2K and provide advanced speed with baud rate up to 230k, 460k, and 921k bps which support
higher speed Modems.
The W83877TF supports one PC-compatible printer port (SPP), Bi-directional printer port (BPP) and
also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port
interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or
two external floppy disk drives to be connected. This function is especially valuable for notebook
computer applications.
Winbond W83877TF provides functions that comply with ACPI (Advanced Configuration and Power
Interface), which includes support of legacy and ACPI power management through SMI or SCI
function pins. One 24-bits power management timer is implemented with the carry notify interrupt.
W83877TF also has auto power management mode to reduce the power consumption.
The serial IRQ for PCI architecture is supported, ISA IRQs (IRQ1~IRQ15) can be cascaded into one
IRQSER pin. W83877TF also features ISA bus IRQ sharing and allows two or more devices to share
the same IRQ pin.
W83877TF is made to fully comply with MicrosoftTM PC97 Hardware Design Guide. IRQs, DMAs,
and I/O space resources are flexible to adjust to meet ISA PnP requirement. Moreover W83877TF is
made to meet the specification of PC97's requirement in the power management: ACPI and DPM
(Device Power Management).
The configuration registers support mode selection, function enable/disable, and power down function
selection. Furthermore, the configurable PnP registers are compatible with the Plug-and-Play feature
demand of Windows 95TM , which makes system resource allocation more efficient than ever.
Another benefit of W83877TF is that it is pin-to-pin compatible to W83877F, and all of the 100-pin
Winbond I/O IC family. Thus makes the design of applications very convenient and flexible.
Publication Release Date: March 1998
- 1 -
Preliminary Version 0.61
W83877TF
3.2 Register Address
TABLE 3-1 UART Register Bit Map
Bit Number
Register Address Base
0
1
2
3
4
5
6
7
8
Receiver
Buffer
Register
RBR
TBR
RX Data
Bit 0
RX Data
Bit 1
RX Data
Bit 2
RX Data
Bit 3
RX Data
Bit 4
RX Data
Bit 5
RX Data
Bit 6
RX Data
Bit 7
BDLAB = 0
(Read Only)
8
Transmitter
Buffer Register
(Write Only)
TX Data
Bit 0
TX Data
Bit 1
TX Data
Bit 2
TX Data
Bit 3
TX Data
Bit 4
TX Data
Bit 5
TX Data
Bit 6
TX Data
Bit 7
BDLAB = 0
9
Interrupt Control ICR
Register
RBR Data
Ready
Interrupt
Enable
TBR
Empty
Interrupt
Enable
USR
Interrupt
Enable
HSR
Interrupt
Enable
0
0
0
0
BDLAB = 0
(EUSRI)
(EHSRI)
(ERDRI)
(ETBREI)
A
A
Interrupt Status
Register
(Read Only)
ISR
"0" if
Interrupt
Pending
Interrupt
Status
Interrupt
Status
Interrupt
Status
0
0
FIFOs
Enabled
**
FIFOs
Enabled
**
Bit (0)
Bit (1)
Bit (2)**
UART FIFO
Control
Register
UFR
FIFO
Enable
RCVR
FIFO
Reset
XMIT
FIFO
Reset
DMA
Mode
Select
Reserved
Reversed
RX
Interrupt
Active Level Active Level
RX
Interrupt
(Write Only)
(LSB)
(MSB)
B
UART Control
Register
UCR
Data
Length
Select
Bit 0
Data
Length
Select
Bit 1
Multiple
Stop Bits
Enable
Parity
Bit
Enable
Even
Parity
Enable
Parity
Bit Fixed
Enable
Set
Silence
Enable
Baud rate
Divisor
Latch
Access Bit
(BDLAB)
(MSBE)
(PBE)
(EPE)
PBFE)
(SSE)
(DLS0)
(DLS1)
C
D
Handshake
Control
Register
HCR
USR
Data
Terminal
Ready
Request
to
Send
(RTS)
Loopback
RI
Input
IRQ
Enable
Internal
Loopback
Enable
0
0
0
(DTR)
UART Status
Register
RBR Data
Ready
Overrun
Error
Parity Bit
Error
No Stop
Bit
Silent
Byte
TBR
Empty
TSR
Empty
RX FIFO
Error
Error
(NSER)
Detected
(SBD)
Indication
(RFEI) **
(RDR)
(OER)
(PBER)
(TBRE)
(TSRE)
E
F
Handshake
Status Register
HSR
UDR
CTS
Toggling
DSR
Toggling
RI Falling
Edge
DCD
Toggling
Clear
to Send
Data Set
Ready
Ring
Indicator
Data Carrier
Detect
(DCD)
(TCTS)
Bit 0
(TDSR)
Bit 1
(FERI)
Bit 2
(TDCD)
Bit 3
(CTS)
Bit 4
(DSR)
Bit 5
(RI)
User Defined
Register
Bit 6
Bit 7
Bit 7
8
Baudrate Divisor BLL
Latch Low
Bit 0
Bit 8
Bit 1
Bit 9
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
BDLAB = 1
9
Baudrate
Divisor Latch
High
BHL
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
BDLAB = 1
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 mode.
Publication Release Date: March 1998
Version 0.61
- 40 -
W83877TF
3.2.1 UART Control Register (UCR) (Read/Write)
The UART Control Register controls and defines the protocol for asynchronous data communications,
including data length, stop bit, parity, and baud rate selection.
5
4
2
6
7
3
0
1
Data length select bit 0 (DLS0)
Data length select bit 1(DLS1)
Multiple stop bits enable (MSBE)
Parity bit enable (PBE)
Even parity enable (EPE)
Parity bit fixed enable (PBFE)
Set silence enable (SSE)
Baudrate divisor latch access bit (BDLAB)
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary
format) from the divisor latches of the baud rate generator during a read or write operation.
When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the
Interrupt Control Register can be accessed.
Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only SOUT is
affected by this bit; the transmitter is not affected.
Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,
(1) if EPE is a logical 1, the parity bit is fixed as a logical 0 to transmit and check.
(2) if EPE is a logical 0, the parity bit is fixed as a logical 1 to transmit and check.
Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit
3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When
the bit is reset, an odd number of logic 1's are sent or checked.
Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT
will be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same
position as the transmitter will be detected.
Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or
received.
(1) If MSBE is set to a logical 0, one stop bit is sent and checked.
(2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and
checked.
(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and
checked.
Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in
each serial character.
Publication Release Date: March 1998
- 41 -
Version 0.61
W83877TF
TABLE 3-2 WORD LENGTH DEFINITION
DLS1
DLS0
DATA LENGTH
5 bits
0
0
1
1
0
1
0
1
6 bits
7 bits
8 bits
3.2.2 UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of the data transfer during communication.
2
7
6
4
3
1
0
5
RBR Data ready (RDR)
Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)
Transmitter Shift Register empty (TSRE)
RX FIFO Error Indication (RFEI)
Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic
1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO.
In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left
in the FIFO.
Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In
16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other
than these two cases, this bit will be reset to a logical 0.
Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be
set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU
to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO
is empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO.
Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full
word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the
same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit
to a logical 0.
Publication Release Date: March 1998
- 42 -
Version 0.61
W83877TF
Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads
USR, it will clear this bit to a logical 0.
Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In
16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU
reads USR, it will clear this bit to a logical 0.
Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next
received data before they were read by the CPU. In 16550 mode, it indicates the same
condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.
Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in
the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
3.2.3 Handshake Control Register (HCR) (Read/Write)
This register controls the pins of the UART used for handshaking peripherals such as modem, and
controls the diagnostic mode of the UART.
2
7
0
5
4
3
1
0
6
0
0
Data terminal ready (DTR)
Request to send (RTS)
Loopback RI input
IRQ enable
Internal loopback enable
Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as
follows:
(1) SOUT is forced to a logical 1, and SIN is isolated from the communication link instead of
the TSR.
(2) Modem output pins are set to their inactive state.
(3) Modem input pins are isolated from the communication link and connect internally as DTR
(bit 0 of HCR) ® DSR, RTS ( bit 1 of HCR) ® CTS, Loopback RI input ( bit 2 of HCR) ®
RI and IRQ enable ( bit 3 of HCR) ® DCD.
Aside from the above connections, the UART operates normally. This method allows the
CPU to test the UART in a convenient way.
Publication Release Date: March 1998
- 43 -
Version 0.61
W83877TF
Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this
bit is internally connected to the modem control input DCD .
Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally
connected to the modem control input RI .
Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS .
Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR.
3.2.4 Handshake Status Register (HSR) (Read/Write)
This register reflects the current state of four input pins for handshake peripherals such as a modem
and records changes on these pins.
7
6
5
4
3
2
1
0
toggling (TCTS)
toggling (TDSR)
CTS
DSR
RI falling edge (FERI)
DCD
toggling (TDCD)
Clear to send (CTS)
Data set ready (DSR)
Ring indicator (RI)
Data carrier detect (DCD)
Bit 7: This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loopback
mode.
Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode.
Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback
mode.
Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback
mode.
Bit 3: TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the CPU.
Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read
by the CPU.
Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read by the CPU.
Publication Release Date: March 1998
- 44 -
Version 0.61
W83877TF
3.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
2
1
7
6
5
4
3
0
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
TABLE 3-3 FIFO TRIGGER LEVEL
BIT 7
BIT 6
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
0
0
1
1
0
1
0
1
01
04
08
14
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
UFR bit 0 = 1.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to
a logical 0 by itself after being set to a logical 1.
Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to
a logical 0 by itself after being set to a logical 1.
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1
before other bits of UFR are programmed.
Publication Release Date: March 1998
- 45 -
Version 0.61
W83877TF
3.2.6 Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
7
6
5
0
4
0
3
2
1
0
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-
out interrupt is pending.
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has
occurred, this bit will be set to a logical 0.
TABLE 3-4 INTERRUPT CONTROL FUNCTION
ISR
INTERRUPT SET AND FUNCTION
Bit
3
Bit
2
Bit
1
Bit Interrupt
Interrupt Type
-
Interrupt Source
Clear Interrupt
0
priority
0
0
0
1
0
1
1
0
-
No Interrupt pending
-
First
UART Receive
Status
1. OER = 1 2. PBER =1
3. NSER = 1 4. SBD = 1
Read USR
0
1
0
0
Second
RBR Data Ready
1. RBR data ready
1. Read RBR
2. FIFO interrupt active level
reached
2. Read RBR until FIFO
data under active level
1
0
1
0
0
1
0
0
Second
Third
FIFO Data Timeout
TBR Empty
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
Read RBR
TBR empty
1. Write data into TBR
2. Read ISR (if priority is
third)
0
0
0
0
Fourth
Handshake status
1. TCTS = 1 2. TDSR = 1
3. FERI = 1 4. TDCD = 1
Read HSR
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
Publication Release Date: March 1998
Version 0.61
- 46 -
W83877TF
3.2.7 Interrupt Control Register (ICR) (Read/Write)
This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal
separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt
Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this
register to a logical 1.
5
6
0
3
0
4
0
2
7
0
1
0
RBR data ready interrupt enable (ERDRI)
TBR empty interrupt enable (ETBREI)
UART receive status interrupt enable (EUSRI)
Handshake status interrupt enable (EHSRI)
Bit 7-4: These four bits are always logic 0.
Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt.
Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt.
Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt.
Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.
3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)
Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to
generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 216-1. The output frequency of
the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter
and receiver. The table below illustrates the use of the baud generator with a frequency of 1.8461
MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud
generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed
mode, the data transmission rate can be as high as 1.5M bps.
Publication Release Date: March 1998
- 47 -
Version 0.61
W83877TF
3.2.9 User-defined Register (UDR) (Read/Write)
This is a temporary register that can be accessed and defined by the user.
TABLE 3-5 BAUD RATE TABLE
BAUD RATE USING 24 MHZ TO GENERATE 1.8461 MHZ
Desired Baud Rate
Decimal divisor used to
generate 16X clock
Percent error difference between
desired and actual
50
75
2304
1536
1047
857
768
384
192
96
**
**
110
0.18%
134.5
150
0.099%
**
**
300
600
**
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
230400
460800
921600
1.5M
**
64
**
58
0.53%
**
48
32
**
24
**
16
**
12
**
6
**
3
**
2
**
1
**
4 Note 1
2 Note 1
1 Note 1
1 Note 2
**
**
**
0%
Note 1: Only use in high speed mode, when FASTA/FASTB bits are set (refer to CR19 bit1 and CR19 bit0).
Note 2: Only use in high speed mode, when TURA/TURB bits are set (refer to CR0C bit7 and bit6).
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%
Publication Release Date: March 1998
Version 0.61
- 48 -
W83877TF
FEATURES
General:
· Plug & Play 1.0A Compliant
· Support 8 IRQs (ISA), or 15 IRQs (Serial IRQ), 3 DMA channels, and 480 re-locatable address
· Capable of ISA Bus IRQ Sharing
· Comply with Microsoft PC 97 Hardware Design Guide
· Support DPM (Device Power Management), ACPI
· Report ACPI status interrupt by SCI signal from SCI pin, serial IRQ IRQSER pin, or IRQ A~H pins
· Single 24MHz/48MHZ clock input
FDC:
· Compatible with IBM PC AT disk drive systems
· Variable write pre-compensation with track selectable capability
· DMA enable logic
· Supports floppy disk drives and tape drives
· Detects all overrun and underrun conditions
· Built-in address mark detection circuit to simplify the read electronics
· FDD anti-virus functions with software write protect and FDD write enable signal (write data signal
was forced to be inactive)
· Supports up to four 3.5-inch or 5.25-inch floppy disk drives
· Completely compatible with industry standard 82077
· 360K/720K/1.2M/1.44M/2.88M format;250K, 300K, 500K, 1M, 2M bps data transfer rate
· Supports vertical recording format
·
Support 3-mode FDD, and its Win95 driver
· 16-byte data FIFOs
UART:
· Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs
· MIDI compatible
· Fully programmable serial-interface characteristics:
- 5, 6, 7 or 8-bit characters
- Even, odd or no parity bit generation/detection
- 1, 1.5 or 2 stop bits generation
· Internal diagnostic capabilities:
- Loop-back controls for communications link fault isolation
- Break, parity, overrun, framing error simulation
· Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1)
· Maximum baud rate is up to 921k bps for 14.768MHz and 1.5M bps for 24MHz
Publication Release Date: March 1998
Version 0.61
- 2 -
W83877TF
Infrared:
· Supports IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
· Supports SHARP ASK-IR protocol with maximum baud rate up to 57600 bps
Parallel Port:
· Compatible with IBM parallel port
· Supports PS/2 compatible bi-directional parallel port
· Supports Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification
· Supports Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification
· Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and
B through parallel port
· Enhanced printer port back-drive current protection
Others:
· Programmable configuration settings
· Immediate or automatic power-down mode for the power management
· All hardware power-on settings have internal pull-up or pull-down resistors as default value
· Dedicated Infrared Communication Pins
Package:
· 100-pin QFP (W83877TF), and also 100-pin LQFP (W83877TD)
Publication Release Date: March 1998
- 3 -
Version 0.61
W83877TF
PIN CONFIGURATION
/
D
S
K
C
H
G
/
/
R
D
A
T
A
T
/
/
/
R
A
K
0
/
A
1
0
M
O
A
N
W
P
I
M
O
B
G I
V
D
D
A
E
N
D
4
D
0
D
5
D
3
D
1
O
R
A
9
A
5
A
4
D
6
D
2
N O
D W
A
8
A A
7 6
A A
D
7
A
3
A
0
2
1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RIB
50
X
X
X
X
X
X
X
X
INDEX
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DCDB
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
STEP
DSA
DSB
WE
DSRB
CTSB
DTRB
RTSB
IRQ_C
SOUTB
WD
RWC
HEAD
SINB
DIR
GND
DACK_A
GND
IRQ_H
IRQ_B
DRQ_A
SOUTA
IRQ_D
IRQIN
IRRX2
X
X
RTSA
DTRA
CTSA
DSRA
DCDA
RIA
IRTX2
IRQ_A
X
X
X
X
TC
DACK_B
IRQ_F
DRQ_B
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
/
P
D
1
P
D
4
P
D
6
/
/
/
/
P
E
I
/
D
C
L
K
I
P
D
5
I
B G /
/
/
C
S
I
M
P
D
0
P P
D D
V
D
D
P /
S
L
C
T
S
I
N
A
S
T
B
S
L
I
R
Q
S R
C Q
S
M
I
A I
R
Q
|
E
R
R
U N
S D
Y
A
O R
C
D D
F N
D I
2
3
7
A
C
K
|
C
K
I
|
C
H
T N
G
N
E
R
D
Y
C
Publication Release Date: March 1998
Version 0.61
- 4 -
W83877TF
1.0 PIN DESCRIPTION
(Note: Refer to section 9.2 DC CHARACTERISTICS for details.)
I/O8tc - TTL level output pin with 8 mA source-sink capability; CMOS level input voltage
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability
I/O24t - TTL level bi-directional pin with 24 mA source-sink capability
OUT8t - TTL level output pin with 8 mA source-sink capability
OUT12t - TTL level output pin with 12 mA source-sink capability
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INt - TTL level input pin
INts - TTL level Schmitt-triggered input pin
INc - CMOS level input pin
INcs - CMOS level Schmitt-triggered input pin
1.1 Host Interface
SYMBOL
D0- D7
PIN
66-73
51-55
57-61
75
I/O
I/O24t
INt
FUNCTION
System data bus bits 0-7.
System address bus bits 0-9.
A0- A9
A10
INt
In ECP Mode, this pin is the A10 address input.
IOCHRDY
5
OD24
In EPP Mode, this pin is the IO Channel Ready output to extend
the host read/write cycle.
MR
6
2
INts
INt
Master Reset. Active high. MR is low during normal operations.
Active low chip select signal.
CS
AEN
62
63
INt
System address bus enable.
CPU I/O read signal.
INts
IOR
64
INts
CPU I/O write signal.
IOW
DRQ_B
100
98
OUT12t DMA request signal B.
INts
DMA Acknowledge signal B.
DACK_B
Publication Release Date: March 1998
Version 0.61
- 5 -
W83877TF
1.1 Host Interface, continued
SYMBOL
PIN
4
I/O
FUNCTION
DRQ_C
OUT12t DMA request signal C.
18
INts
INts
DMA Acknowledge signal C.
DACK_C
TC
97
93
96
Terminal Count. When active, this pin indicates termination of a
DMA transfer.
IRQIN
INt
Interrupt request input for IRQ routing ; For example , the IRQ12
can be routed into this port when PS/2 mouse is not installed.
OUT12t Interrupt request signal A, when CR16 Bit 5 (G1IQSEL) = 0.
I/O12t General Purpose I/O port 1, when CR16 Bit 5 (G1IQSEL) = 1.
OUT12t Interrupt request signal B, when CR16 Bit 4 (G0IQSEL) = 0.
I/O12t General Purpose I/O port 0, when CR16 Bit 4 (G0IQSEL) = 1.
IRQ_ A
GIO1
92
IRQ_B
GIO0
IRQ_C
IRQ_D
IRQ_E
IRQ_F
44
37
23
99
1
OUT12t Interrupt request signal C.
OUT12t Interrupt request signal D.
OUT12t Interrupt request signal E.
OUT12t Interrupt request signal F.
OUT12t Interrupt request signal G.
IRQ_G
PCICLK
IRQ_H
INt
PCI clock input, when the serial IRQ function is selected.
91
3
OUT12t Interrupt request signal H.
SERIRQ
I/O12t
Serial interrupt input/output, when the Serial IRQ mode is
selected by setting IRQMODS bit in CR31 register.
OD12
SCI
For the ACPI power management, SCI is active low 200ns for
the power management events, which generate an SCI interrupt
in the ACPI mode.
CLKIN
SMI
7
8
INt
24MHz/48MHZ clock input. CLKINSEL bit in CR2C register
should be correctly reset/set according to the input frequency.
OD12
For the legacy power management, theSMI is active low 200ns
for the power management events, which generate an SMI
interrupt in the legacy power management mode.
This SMI output is enabled by setting the SMI_EN bit in CR3A
register.
41
39
INts
DMA acknowledge signal A.
DACK_A
DRQ_A
OUT12t DMA request signal A.
Publication Release Date: March 1998
Version 0.61
- 6 -
W83877TF
1.2 Serial Port Interface
SYMBOL
SINA
PIN
30
I/O
FUNCTION
INt
Serial Input. It is used to receive serial data from the
communication link.
SINB/IRRX1
42
31
INt
INt
INt
Ring Indicator. An active low indicates that a ring signal is being
received by the modem or data set.
RIA
50
RIB
32
49
Data Carrier Detect. An active low indicates the modem or data
set has detected a data carrier.
DCDA
DCDB
DSRA
DSRB
33
48
Data Set Ready. An active low indicates the modem or data set
is ready to establish a communication link and transfer data to
the UART.
34
47
INt
Clear To Send. It is the modem control input.
CTSA
CTSB
The function of these pins can be tested by reading Bit 4 of the
handshake status register.
35
I/O8tc
UART A Data Terminal Ready. An active low informs the
modem or data set that the controller is ready to communicate.
DTRA
PHEFRAS
During power-on reset, this pin is pulled down internally and is
defined as PHEFRAS, which provides the power-on value for
CR16 bit 0 (HEFRAS). While it is at Low, it selects the EFER
(Extended Functions Enable Register) to be 250H. While it is at
High, it selects the EFER to be 3F0H. A 4.7 kW is recommended
when intends to pull up at power-on reset.
36
I/O8tc
UART A Request To Send. An active low informs the modem or
data set that the controller is ready to send data.
RTSA
PPNPCVS
During power-on reset, this pin is pulled up internally and is
defined as PPNPCVS, which provides the power-on value for
CR16 bit 2 (PNPCVS). While it is at Low, all PnP-related
registers (CR20 to CR29) are all set to be 0s. While it is at High,
all PnP-related registers (CR20 to CR 29) are set to default
values. A 4.7 kW is recommended when intends to pull down at
power-on reset.
SOUTA
38
I/O8tc
UART A Serial Output. It is used to transmit serial data out to the
communication link.
PENFDC
During power-on reset, this pin is pulled up internally and used to
enable or disable the FDC. While it is at Low, FDC PnP-related
register (CR20) is set to be 0, i.e. FDC is disabled. While it is at
High, CR20 is set to the default value, i.e. FDC is enabled. A
4.7 kW is recommended when intends to pull down at power-on
reset.
Publication Release Date: March 1998
- 7 -
Version 0.61
W83877TF
1.2 Serial Port Interface ,continued
SYMBOL
SOUTB
PIN
I/O
FUNCTION
43
I/O8tc
UART B Serial Output. It is used to transmit serial data out to the
communication link.
IRTX1
During power-on reset, this pin is pulled down internally and is
defined as PIRQMDS to select the IRQ mode. While it is at
Low, IRQ pins can be set to Normal mode or IRQ sharing mode
which decided by CR18. If it is at High, the Serial IRQ mode is
selected. A 4.7 kW is recommended when intending to pull up at
power-on reset.
PIRQMDS
45
I/O8tc
UART B Request To Send. An active low informs the modem or
data set that the controller is ready to send data.
RTSB
PGOIQSEL
During power-on reset, this pin is pulled down internally and is
defined as PGOIQSEL, which provides the power-on value for
CR16 bit 4 and bit 5 (G0IQSEL & G1IQSEL). While it is at Low,
pins 92 and 96 function as IRQ pins IRQ_B,IRQ_A respectively.
While it is at high, pins 92 and 96 function as General Purpose
I/O pins GIO0,GIO1 respectively. A 4.7 kW is recommended
when intends to pull up at power-on reset.
46
I/O8tc
UART B Data Terminal Ready. An active low informs the
modem or data set that the controller is ready to communicate.
DTRB
IRTX2
IRRX2
95
94
OUT12t Functions as a InfraRed data transmission line.
INt Functions as a InfraRed data receiving line.
1.3 Multi-Mode Parallel Port
The following pins have six functions, which are controlled by bits PRTMOD0, PRTMOD1, and
PRTMOD2 of CR0 and CR9 (refer to section 8.0, Extended Functions).
SYMBOL
BUSY
PIN
I/O
FUNCTION
24
INt
PRINTER MODE: BUSY
An active high input indicates that the printer is not ready to
receive data. This pin is pulled high internally. Refer to the
description of the parallel port for the definition of this pin in ECP
and EPP mode.
OD12
OD12
EXTENSION FDD MODE: MOB2
This pin is for Extension FDD B; the function of this pin is the
same as that of the MOB pin.
EXTENSION 2FDD MODE: MOB2
This pin is for Extension FDD A and B; the function of this pin is
the same as that of the MOB pin.
Publication Release Date: March 1998
- 8 -
Version 0.61
W83877TF
1.3 Multi-Mode Parallel Port, continued
SYMBOL
ACK
PIN
I/O
FUNCTION
26
INt
PRINTER MODE: ACK
An active low input on this pin indicates that the printer has
received data and is ready to accept more data. This pin is
pulled high internally. Refer to the description of the parallel port
for the definition of this pin in ECP and EPP mode.
OD12
OD12
INt
EXTENSION FDD MODE: DSB2
This pin is for the Extension FDD B; its functions are the same
as those of the DSB pin.
EXTENSION 2FDD MODE: DSB2
This pin is for Extension FDD A and B; the function of this pin is
the same as that of the DSB pin.
PE
27
PRINTER MODE: PE
An active high input on this pin indicates that the printer has
detected the end of the paper. This pin is pulled high internally.
Refer to the description of the parallel port for the definition of
this pin in ECP and EPP mode.
OD12
OD12
INt
EXTENSION FDD MODE: WD2
This pin is for Extension FDD B; its function is the same as that
of the WD pin.
EXTENSION 2FDD MODE: WD2
This pin is for Extension FDD A and B; this function of this pin is
the same as that of the WD pin.
SLCT
28
PRINTER MODE: SLCT
An active high input on this pin indicates that the printer is
selected. This pin is pulled high internally. Refer to the
description of the parallel port for the definition of this pin in ECP
and EPP mode.
OD12
OD12
EXTENSION FDD MODE: WE2
This pin is for Extension FDD B; its functions are the same as
those of the
pin.
WE
EXTENSION 2FDD MODE: WE2
This pin is for Extension FDD A and B; this function of this pin is
the same as that of the WE pin.
Publication Release Date: March 1998
- 9 -
Version 0.61
W83877TF
1.3 Multi-Mode Parallel Port, continued
SYMBOL
ERR
PIN
I/O
FUNCTION
29
INt
PRINTER MODE: ERR
An active low input on this pin indicates that the printer has
encountered an error condition. This pin is pulled high internally.
Refer to the description of the parallel port for the definition of
this pin in ECP and EPP mode.
OD12
OD12
OD12
EXTENSION FDD MODE: HEAD2
This pin is for Extension FDD B; its function is the same as that
of the HEAD pin.
EXTENSION 2FDD MODE: HEAD2
This pin is for Extension FDD A and B; its function is the same
as that of the HEAD pin.
22
SLIN
PRINTER MODE: SLIN
Output line for detection of printer selection. This pin is pulled
high internally. Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.
OD12
OD12
OD12
EXTENSION FDD MODE: STEP2
This pin is for Extension FDD B; its function is the same as that
of the STEP pin.
EXTENSION 2FDD MODE: STEP2
This pin is for Extension FDD A and B; its function is the same
as that of the STEP pin .
21
INIT
PRINTER MODE: INIT
Output line for the printer initialization. This pin is pulled high
internally. Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.
OD12
OD12
EXTENSION FDD MODE: DIR2
This pin is for Extension FDD B; its function is the same as that
of the DIR pin.
EXTENSION 2FDD MODE: DIR2
This pin is for Extension FDD A and B; its function is the same
as that of the DIR pin.
Publication Release Date: March 1998
- 10 -
Version 0.61
W83877TF
1.3 Multi-Mode Parallel Port, continued
SYMBOL
AFD
PIN
I/O
FUNCTION
20
OD12
PRINTER MODE: AFD
An active low output from this pin causes the printer to auto feed
a line after a line is printed. This pin is pulled high internally.
Refer to the description of the parallel port for the definition of
this pin in ECP and EPP mode.
OD12
OD12
OD12
EXTENSION FDD MODE: RWC2
This pin is for Extension FDD B; its function is the same as that
of the RWC pin.
EXTENSION 2FDD MODE: RWC2
This pin is for Extension FDD A and B; its function is the same
as that of the RWC pin.
19
STB
PRINTER MODE: STB
An active low output is used to latch the parallel data into the
printer. This pin is pulled high internally. Refer to the description
of the parallel port for the definition of this pin in ECP and EPP
mode.
-
-
EXTENSION FDD MODE: NC pin
EXTENSION 2FDD MODE: NC pin
PRINTER MODE: PD0
PD0
9
I/O24t
Parallel port data bus bit 0. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
INt
INt
EXTENSION FDD MODE: INDEX2
This pin is for Extension FDD B; the function of this pin is the
same as that of the INDEX pin. This pin is pulled high internally.
EXTENSION 2FDD MODE: INDEX2
This pin is for Extension FDD A and B; this function of this pin is
the same as INDEX pin. This pin is pulled high internally.
Publication Release Date: March 1998
- 11 -
Version 0.61
W83877TF
1.3 Multi-Mode Parallel Port, continued
SYMBOL
PD1
PIN
I/O
FUNCTION
10
I/O24t
PRINTER MODE: PD1
Parallel port data bus bit 1. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
INt
INt
EXTENSION FDD MODE: TRAK02
This pin is for Extension FDD B; the function of this pin is the
same as that of the TRAK0 pin. This pin is pulled high internally.
EXTENSION. 2FDD MODE: TRAK02
This pin is for Extension FDD A and B; this function of this pin is
the same as TRAK0 pin. This pin is pulled high internally.
PD2
11
I/O24t
PRINTER MODE: PD2
Parallel port data bus bit 2. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
INt
EXTENSION FDD MODE: WP2
This pin is for Extension FDD B; the function of this pin is the
same as that of the
pin. This pin is pulled high internally.
WP
INt
EXTENSION. 2FDD MODE: WP2
This pin is for Extension FDD A and B; this function of this pin is
the same as that of the
pin. This pin is pulled high internally.
WP
PD3
12
I/O24t
PRINTER MODE: PD3
Parallel port data bus bit 3. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
INt
EXTENSION FDD MODE: RDATA2
Motor on B for Extension FDD B; the function of this pin is the
same as that of the RDATA pin. This pin is pulled high internally.
INt
EXTENSION 2FDD MODE: RDATA2
This pin is for Extension FDD A and B; this function of this pin is
the same as that of the RDATA pin. This pin is pulled high
internally.
Publication Release Date: March 1998
- 12 -
Version 0.61
W83877TF
1.3 Multi-Mode Parallel Port, continued
SYMBOL
PD4
PIN
I/O
FUNCTION
13
I/O24t
PRINTER MODE: PD4
Parallel port data bus bit 4. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
INt
INt
EXTENSION FDD MODE: DSKCHG2
Drive select B for Extension FDD B; the function of this pin is the
same as that of DSKCHG pin. This pin is pulled high internally.
EXTENSION 2FDD MODE: DSKCHG2
This pin is for Extension FDD A and B; this function of this pin is
the same as that of the DSKCHG pin. This pin is pulled high
internally.
PD5
PD6
14
16
I/O24t
PRINTER MODE: PD5
Parallel port data bus bit 5. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: This pin is a tri-state output.
I/O24t
I/O24t
I/O24t
PRINTER MODE: PD6
Parallel port data bus bit 6. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
-
EXTENSION FDD MODE: NC pin
EXTENSION. 2FDD MODE: MOA2
OD24
This pin is for Extension FDD A; its function is the same as that
of the MOA pin.
PD7
17
I/O24t
PRINTER MODE: PD7
Parallel port data bus bit 7. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
-
EXTENSION FDD MODE: NC pin
EXTENSION 2FDD MODE: DSA2
OD24
This pin is for Extension FDD A; its function is the same as that
of the DSA pin.
Publication Release Date: March 1998
- 13 -
Version 0.61
W83877TF
1.4 FDC Interface
SYMBOL PIN
WE
I/O
FUNCTION
85
89
OD24
OD24
Write enable. An open drain output.
Direction of the head step motor. An open drain output.
Logic 1 = outward motion
DIR
Logic 0 = inward motion
88
87
OD24
OD24
Head select. This open drain output determines which disk drive
head is active.
HEAD
Logic 1 = side 0
Logic 0 = side 1
Reduced write current. This signal can be used on two-speed
disk drives to select the transfer rate. An open drain output.
RWC
Logic 0 = 250 Kb/s
Logic 1 = 500 Kb/s
When bit 5 of CR9 (EN3MODE) is set to high, the three-mode
FDD function is enabled, and the pin will have a different
definition. Refer to the EN3MODE bit in CR9.
86
82
81
OD24
OD24
INcs
Write data. This logic low open drain writes precompensation
serial data to the selected FDD. An open drain output.
WD
Step output pulses. This active low open drain output produces a
pulse to move the head to another track.
STEP
INDEX
This schmitt input from the disk drive is active low when the
head is positioned over the beginning of a track marked by an
index hole. This input pin is pulled up internally by an
approximately 1K ohm resistor. The resistor can be disabled by
bit 4 of CR6 (FIPURDWN).
78
77
INcs
Track 0. This schmitt input from the disk drive is active low when
the head is positioned over the outermost track. This input pin is
pulled up internally by an approximately 1K ohm resistor. The
resistor can be disabled by bit 4 of CR6 (FIPURDWN).
TRAK0
WP
INcs
Write protected. This active low schmitt input from the disk drive
indicates that the diskette is write-protected. This input pin is
pulled up internally by an approximately 1K ohm resistor. The
resistor can be disabled by bit 4 of CR6 (FIPURDWN).
74
76
INcs
INcs
The read data input signal from the FDD. This input pin is pulled
up internally by an approximately 1K ohm resistor. The resistor
can be disabled by bit 4 of CR6 (FIPURDWN).
RDATA
Diskette change. This signal is active low at power on and
whenever the diskette is removed. This input pin is pulled up
internally by an approximately 1K ohm resistor. The resistor can
be disabled by bit 4 of CR6 (FIPURDWN).
DSKCHG
Publication Release Date: March 1998
- 14 -
Version 0.61
W83877TF
1.4 FDC Interface, continued
SYMBOL
MOA
PIN
I/O
FUNCTION
79
OD24
Motor A On. When set to 0, this pin enables disk drive 0. This is
an open drain output.
80
83
84
OD24
OD24
OD24
Motor B On. When set to 0, this pin enables disk drive 1. This is
an open drain output.
MOB
DSA
Drive Select A. When set to 0, this pin enables disk drive A. This
is an open drain output.
Drive Select B. When set to 0, this pin enables disk drive B. This
is an open drain output.
DSB
VDD
15,
56
+5 power supply for the digital circuitry.
GND
25,
40
Ground.
65,
90
Publication Release Date: March 1998
- 15 -
Version 0.61
W83877TF
2.0 FDC FUNCTIONAL DESCRIPTION
2.1 W83877TF FDC
The floppy disk controller of the W83877TF integrates all of the logic required for floppy disk control.
The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible
values. The FIFO provides better system performance in multi-master systems. The digital data
separator supports up to data rate 1 M bits/sec. (2 M bits/sec for fast tape drive)
The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital
Data Separator, FIFO, and FDC Core.
2.1.1 AT interface
The interface consists of the standard asynchronous signals: RD , WR, A0-A3, IRQ, DMA control,
and a data bus. The address lines select between the configuration registers, the FIFO and
control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal
modes. The PS/2 register sets are a superset of the registers found in a PC/AT.
2.1.2 FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM
and DIO bits in the Main Status Register.
The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The
advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors.
The following tables give several examples of the delays with a FIFO. The data are based upon the
following formula:
THRESHOLD ´ (1/Data Rate) *8 - 1.5 mS = DELAY
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT 500K BPS
Data Rate
1 Byte
2 Byte
8 Byte
15 Byte
1 ´ 16 mS - 1.5 mS = 14.5 mS
2 ´ 16 mS - 1.5 mS = 30.5 mS
8 ´ 16 mS - 1.5 mS = 6.5 mS
15 ´ 16 mS - 1.5 mS = 238.5 mS
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT 1M BPS
Data Rate
1 Byte
2 Byte
8 Byte
15 Byte
1 ´ 8 mS - 1.5 mS = 6.5 mS
2 ´ 8 mS - 1.5 mS = 14.5 mS
8 ´ 8 mS - 1.5 mS = 62.5 mS
15 ´ 8 mS - 1.5 mS = 118.5 mS
At the start of a command the FIFO is always disabled and command parameters must be sent based
upon the RQM and DIO bit settings in the main status register. When the FDC enters the command
execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.
Publication Release Date: March 1998
- 16 -
Version 0.61
W83877TF
An overrun and underrun will terminate the current command and the data transfer. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to
remove the remaining data so that the result phase may be entered.
DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating
the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK and
addresses need not be valid.
Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed
by the FDC based only on DACK . This mode is only available when the FDC has been configured
into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above
operation is performed by using the new VERIFY command. No DMA operation is needed.¡ @
2.1.3 Data Separator
The function of the data separator is to lock onto the incoming serial read data. When a lock is
achieved the serial front end logic of the chip is provided with a clock which is synchronized to the
read data. The synchronized clock, called the Data Window, is used to internally sample the serial
data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel
conversion logic separates the read data into clock and data bytes.
The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking.
The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized
and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for
every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on
speed. A digital integrator is used to keep track of the speed changes in the input data stream.
2.1.4 Write Precompensation
The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk
drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media
and the floppy drive.
The FDC monitors the bit stream that is being sent to the drive. The data patterns that require
precompensation are well known. Depending upon the pattern, the bit is shifted either early or late
relative to the surrounding bits.
2.1.5 Perpendicular Recording Mode
The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular
recording differs from the traditional longitudinal method in that the magnetic bits are oriented
vertically. This scheme packs more data bits into the same area.
FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write
perpendicular media. Some manufacturers offer drives that can read and write standard and
perpendicular media in a perpendicular media drive.
A single command puts the FDC into perpendicular mode. All other commands operate as they
normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the
FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk.
Publication Release Date: March 1998
- 17 -
Version 0.61
W83877TF
2.1.6 Tape Drive
The W83877TF supports standard tape drives (1 Mbps, 500 Kbps, 250 Kbps) and new fast tape drive
(2M bps).
2.1.7 FDC Core
The W83877TF FDC is capable of performing twenty commands. Each command is initiated by a
multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the
microprocessor. Each command consists of three phases: command, execution, and result.
Command
The microprocessor issues all required information to the controller to perform a specific operation.
Execution
The controller performs the specified operation.
Result
After the operation is completed, status information and other housekeeping information is provided
to the microprocessor.
2.1.8 FDC Commands
Command Symbol Descriptions:
C:
Cylinder number 0 - 256
Data Pattern
D:
DIR:
Step Direction
DIR = 0, step out
DIR = 1, step in
Disk Drive Select 0
Disk Drive Select 1
Data Length
DS0:
DS1:
DTL:
EC:
Enable Count
EOT:
EFIFO:
EIS:
End of Track
Enable FIFO
Enable Implied Seek
End of track
EOT:
FIFOTHR: FIFO Threshold
GAP:
GPL:
H:
Gap length selection
Gap Length
Head number
HDS:
HLT:
HUT:
LOCK:
MFM:
MT:
Head number select
Head Load Time
Head Unload Time
Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset
MFM or FM Mode
Multitrack
N:
The number of data bytes written in a sector
New Cylinder Number
NCN:
Publication Release Date: March 1998
Version 0.61
- 18 -
W83877TF
ND:
Non-DMA Mode
Overwritten
OW:
PCN:
POLL:
Present Cylinder Number
Polling Disable
PRETRK: Precompensation Start Track Number
R:
Record
RCN:
R/W:
SC:
Relative Cylinder Number
Read/Write
Sector/per cylinder
Skip deleted data address mark
Step Rate Time
SK:
SRT:
ST0:
ST1:
ST2:
ST3:
WG:
Status Register 0
Status Register 1
Status Register 2
Status Register 3
Write gate alters timing of WE
2.1.9 FDC Instruction Sets
(1) Read Data
PHASE
R/W
W
D7
MT
0
D6
MFM
0
D5
SK
0
D4
0
D3
0
D2
1
D1
1
D0
0
REMARKS
Command
Command codes
0
0
HDS
DS1
DS0
W
W
---------------------- C ------------------------
---------------------- H ------------------------
Sector ID information
prior to command
execution
W
W
W
W
W
W
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Execution
Result
Data transfer between the
FDD and system
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
R
R
R
R
R
Sector ID information
after command execution
Publication Release Date: March 1998
Version 0.61
- 19 -
W83877TF
(2) Read Deleted Data
PHASE
R/W
W
D7
MT
0
D6
MFM
0
D5
SK
0
D4
0
D3
1
D2
1
D1 D0
REMARKS
0
0
Command
Command codes
0
0
HDS
DS1 DS0
W
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to command execution
W
W
W
W
W
W
Execution
Result
Data transfer between the
FDD and system
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: March 1998
Version 0.61
- 20 -
W83877TF
(3) Read A Track
PHASE
R/W D7
D6
MFM
0
D5
0
D4
0
D3
0
D2
0
D1 D0
REMARKS
0
0
1
0
Command
W
W
W
W
W
W
W
W
W
Command codes
0
0
0
HDS
DS1
DS0
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to command execution
Execution
Result
Data transfer between the
FDD and system; FDD
reads contents of all
cylinders from index hole to
EOT
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: March 1998
Version 0.61
- 21 -
W83877TF
(4) Read ID
PHASE
R/W
W
D7
0
D6
MFM
0
D5 D4
D3 D2 D1 D0
REMARKS
0
0
0
0
1
0
0
1
0
Command
Command codes
0
HDS DS1 DS0
W
Execution
Result
The first correct ID
information on the cylinder
is stored in Data Register
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
R
R
Disk status after the
command has been
completed
R
R
(5) Verify
PHASE
R/W
W
D7
MT
EC
D6
MFM
0
D5 D4
D3 D2 D1 D0
REMARKS
SK
0
1
0
0
0
1
1
0
Command
Command codes
HDS DS1 DS0
W
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL/SC -------------------
Sector ID information prior
to command execution
W
W
W
W
W
Execution
Result
No data transfer takes
place
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: March 1998
Version 0.61
- 22 -
W83877TF
(6) Version
PHASE
Command
Result
R/W D7 D6
D5
0
D4
1
D3
0
D2
0
D1
0
D0
0
REMARKS
0
1
0
0
W
W
Command codes
0
1
0
0
0
0
Enhanced controller
(7) Write Data
PHASE
R/W D7 D6
D5
0
D4
0
D3
0
D2
1
D1
0
D0
1
REMARKS
MT
0
MFM
0
Command
W
W
W
W
Command codes
0
0
0
HDS
DS1
DS0
---------------------- C ------------------------
---------------------- H ------------------------
Sector ID information
prior to Command
execution
W
W
W
W
W
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Execution
Result
Data transfer between the
FDD and system
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
Command execution
Sector ID information
after Command execution
Publication Release Date: March 1998
Version 0.61
- 23 -
W83877TF
(8) Write Deleted Data
PHASE
R/W D7 D6
D5
0
D4
0
D3
1
D2
0
D1
0
D0
1
REMARKS
MT
0
MFM
0
Command
W
W
W
W
W
W
W
W
W
Command codes
0
0
0
HDS
DS1
DS0
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to command execution
Execution
Result
Data transfer between the
FDD and system
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: March 1998
Version 0.61
- 24 -
W83877TF
(9) Format A Track
PHASE
R/W
W
W
W
W
W
W
W
W
W
W
R
D7
0
D6
MFM
0
D5
0
D4 D3 D2 D1
D0
1
REMARKS
0
0
1
0
1
0
Command
Command codes
0
0
HDS DS1
DS0
---------------------- N ------------------------
--------------------- SC -----------------------
--------------------- GPL ---------------------
---------------------- D ------------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------- Undefined -------------------
---------------- Undefined -------------------
---------------- Undefined -------------------
---------------- Undefined -------------------
Bytes/Sector
Sectors/Cylinder
Gap 3
Filler Byte
Execution
for Each
Sector
Input Sector Parameters
Repeat:
Result
Status information after
command execution
R
R
R
R
R
R
(10) Recalibrate
PHASE
R/W
D7
D6
0
D5
0
D4
0
D3
0
D2
1
D1 D0
REMARKS
0
0
1
1
Command
W
W
Command codes
0
0
0
0
0
DS1
DS0
Execution
Head retracted to Track 0
Interrupt
(11) Sense Interrupt Status
PHASE
Command
Result
R/W
W
D7
D6
D5
D4
D3
D2
D1 D0
REMARKS
0
0
0
0
1
0
0
0
Command codes
R
---------------- ST0 -------------------------
---------------- PCN -------------------------
Status information at the
end of each seek operation
R
Publication Release Date: March 1998
Version 0.61
- 25 -
W83877TF
(12) Specify
PHASE
R/W
W
D7
D6
D5
D4
D3
D2
D1 D0
REMARKS
0
0
0
0
0
0
1
1
Command
Command codes
W
| ---------SRT ----------- | --------- HUT ---------- |
|------------ HLT -----------------------------------| ND
W
(13) Seek
PHASE
R/W D7 D6 D5
D4
D3
D2
D1
D0
REMARKS
0
0
0
0
1
1
1
1
Command
W
W
W
R
Command codes
0
0
0
0
0
HDS
DS1
DS0
-------------------- NCN -----------------------
Execution
Head positioned over
proper cylinder on diskette
(14) Configure
PHASE
R/W
W
D7
D6
D5
D4
D3
D2
D1
D0
REMARKS
0
0
0
1
0
0
1
1
Command
Configure information
0
0
0
0
0
0
0
0
W
W
0
EIS EFIFO POLL | ------ FIFOTHR ----|
W
| --------------------PRETRK ---------------------- |
Execution
Internal registers written
(15) Relative Seek
PHASE
R/W
W
D7
1
D6
DIR
0
D5
0
D4
0
D3
1
D2
1
D1 D0
REMARKS
1
1
Command
Command codes
0
0
0
0
HDS
DS1
DS0
W
W
| -------------------- RCN ---------------------------- |
Publication Release Date: March 1998
Version 0.61
- 26 -
W83877TF
(16) Dumpreg
PHASE
Command
Result
R/W D7 D6
D5
D4
D3
D2
D1
D0
REMARKS
0
0
0
0
1
1
1
0
Registers placed in FIFO
W
R
R
R
R
R
R
R
R
R
R
-------------------- PCN-Drive 0-----------------
-------------------- PCN-Drive 1 ----------------
-------------------- PCN-Drive 2-----------------
-------------------- PCN-Drive 3 ----------------
-------- SRT ----------- | -------- HUT ----------
------------ HLT -------------------------------------| ND
-------------------- SC/EOT --------------------
LOCK
0
D3 D2
D1 D0 GAP WG
0
EIS EFIFO POLL| --- FIFOTHR ---- |
--------------------PRETRK ---------------------
(17) Perpendicular Mode
PHASE
R/W
W
D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1 D0
REMARKS
1
0
Command
Command code
OW
0
D3
D2
D1
D0
GAP
WG
W
(18) Lock
PHASE
Command
Result
R/W
W
D7
LOCK
0
D6
D5
D4
D3 D2 D1 D0
REMARKS
0
0
0
0
1
0
0
1
0
0
0
0
0
Command code
LOCK
R
(19) Sense Drive Status
PHASE
R/W
W
D7
0
D6
D5
D4
D3
0
D2
1
D1 D0
REMARKS
0
0
0
0
0
0
0
0
Command
Command code
0
0
HDS
DS1
DS0
W
Result
R
---------------- ST3 -------------------------
Status information about
disk drive
(20) Invalid
PHASE
R/W
D7
D6
D5
D4
D3
D2
D1 D0
REMARKS
Command
W
------------- Invalid Codes -----------------
Invalid codes (no operation -
FDC goes into standby state)
Result
R
-------------------- ST0 ----------------------
ST0 = 80H
Publication Release Date: March 1998
Version 0.61
- 27 -
W83877TF
2.2 Register Descriptions
There are several status, data, and control registers in W83877TF. These registers are defined below:
ADDRESS
REGISTER
OFFSET
READ
WRITE
base address + 0
base address + 1
base address + 2
base address + 3
base address + 4
base address + 5
base address + 7
SA REGISTER
SB REGISTER
DO REGISTER
TD REGISTER
TD REGISTER
MS REGISTER
DR REGISTER
DT (FIFO) REGISTER
DI REGISTER
DT (FIFO) REGISTER
CC REGISTER
2.2.1 Status Register A (SA Register) (Read base address + 0)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2
mode, the bit definitions for this register are as follows:
2
1
7
6
5
4
3
0
DIR
WP
INDEX
HEAD
TRAK0
STEP
DRV2
INIT PENDING
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
DRV2 (Bit 6):
0
1
A second drive has been installed
A second drive has not been installed
STEP (Bit 5):
This bit indicates the complement of STEP output.
TRAK0 (Bit 4):
This bit indicates the value of TRAK0 input.
HEAD (Bit 3):
This bit indicates the complement of HEAD output.
0
1
side 0
side 1
Publication Release Date: March 1998
Version 0.61
- 28 -
W83877TF
INDEX (Bit 2):
This bit indicates the value of INDEX output.
WP
(Bit 1):
0disk is write-protected
1disk is not write-protected
DIR (Bit 0)
This bit indicates the direction of head movement.
0
1
outward direction
inward direction
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
2
1
7
6
5
4
3
0
DIR
WP
INDEX
HEAD
TRAK0
STEP F/F
DRQ
INIT PENDING
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
DRQ (Bit 6):
This bit indicates the value of DRQ output pin.
STEP F/F (Bit 5):
This bit indicates the complement of latched STEP output.
TRAK0 (Bit 4):
This bit indicates the complement of TRAK0 input.
HEAD (Bit 3):
This bit indicates the value of HEAD output.
0
1
side 1
side 0
Publication Release Date: March 1998
Version 0.61
- 29 -
W83877TF
INDEX (Bit 2):
This bit indicates the complement of INDEX output.
WP (Bit 1):
0
1
disk is not write-protected
disk is write-protected
DIR (Bit 0)
This bit indicates the direction of head movement.
0
1
inward direction
outward direction
2.2.2 Status Register B (SB Register) (Read base address + 1)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2
mode, the bit definitions for this register are as follows:
2
1
7
1
6
5
4
3
0
1
MOT EN A
MOT EN B
WE
RDATA Toggle
WDATA Toggle
Drive SEL0
Drive SEL0 (Bit 5):
This bit indicates the status of DO REGISTER bit 0 (drive select bit 0).
WDATA Toggle (Bit 4):
This bit changes state at every rising edge of the WD output pin.
RDATA Toggle (Bit 3):
This bit changes state at every rising edge of the RDATA output pin.
WE (Bit 2):
This bit indicates the complement of the WE output pin.
MOT EN B (Bit 1)
This bit indicates the complement of the MOB output pin.
MOT EN A (Bit 0)
This bit indicates the complement of the MOA output pin.
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
Publication Release Date: March 1998
Version 0.61
- 30 -
W83877TF
2
1
7
6
5
4
3
0
DSC
DSD
WE F/F
RDATA F/F
WD F/F
DSA
DSB
DRV2
DRV2 (Bit 7):
0
1
A second drive has been installed
A second drive has not been installed
DSB (Bit 6):
This bit indicates the status of DSB output pin.
DSA (Bit 5):
This bit indicates the status of DSA output pin.
WD F/F(Bit 4):
This bit indicates the complement of the latched WD output pin at every rising edge of the WD
output pin.
RDATA F/F(Bit 3):
This bit indicates the complement of the latched RDATA output pin .
WE F/F (Bit 2):
This bit indicates the complement of latched WE output pin.
DSD (Bit 1):
0
1
Drive D has been selected
Drive D has not been selected
DSC (Bit 0):
0
1
Drive C has been selected
Drive C has not been selected
2.2.3 Digital Output Register (DO Register) (Write base address + 2)
The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ
enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions
are as follows:
Publication Release Date: March 1998
- 31 -
Version 0.61
W83877TF
7
6
3
1-0
5
4
2
Drive Select: 00 select drive A
01 select drive B
10 select drive C
11 select drive D
Floppy Disk Controller Reset
Active low resets FDC
DMA and INT Enable
Active high enable DRQ/IRQ
Motor Enable A. Motor A on when active high
Motor Enable B. Motor B on when active high
Motor Enable C. Motor C on when active high
Motor Enable D. Motor D on when active high
2.2.4 Tape Drive Register (TD Register) (Read base address + 3)
This register is used to assign a particular drive number to the tape drive support mode of the data
separator. This register also holds the media ID, drive type, and floppy boot drive information of the
floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are
as follows:
2
1
7
6
5
4
3
0
X
X
X
X
X
X
Tape sel 0
Tape sel 1
If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows:
2
1
7
6
5
4
3
0
Tape Sel 0
Tape Sel 1
Floppy boot drive 0
Floppy boot drive 1
Drive type ID0
Drive type ID1
Media ID0
Media ID1
Media ID1 Media ID0 (Bit 7, 6):
These two bits are read only. These two bits reflect the value of CR8 bit 3, 2.
Drive type ID1 Drive type ID0 (Bit 5, 4):
These two bits reflect two of the bits of CR7. Which two bits are reflected depends on the last drive
selected in the DO REGISTER.
Floppy Boot drive 1, 0 (Bit 3, 2):
These two bits reflect the value of CR8 bit 1, 0.
Tape Sel 1, Tape Sel 0 (Bit 1, 0):
Publication Release Date: March 1998
- 32 -
Version 0.61
W83877TF
These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive
and is reserved as the floppy disk boot drive.
TAPE SEL 1
TAPE SEL 0
DRIVE SELECTED
0
0
1
1
0
1
0
1
None
1
2
3
2.2.5 Main Status Register (MS Register) (Read base address + 4)
The Main Status Register is used to control the flow of data between the microprocessor and the
controller. The bit definitions for this register are as follows:
6
4
0
7
5
3
2
1
FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode.
FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode.
FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode.
FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode.
FDC Busy, (CB). A read or write command is in the process when CB = HIGH.
Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the
execution phase in non-DMA mode.
Transition to LOW state indicates execution phase has ended.
DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor.
If DIO = LOW then transfer is from processor to Data Register.
Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor.
2.2.6 Data Rate Register (DR Register) (Write base address + 4)
The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of
the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and
not by the DR REGISTER. The real data rate is determined by the most recent write to either of the
DR REGISTER or CC REGISTER.
1
7
6
5
0
4
3
2
0
DRATE0
DRATE1
PRECOMP0
PRECOMP1
PRECOMP2
POWER DOWN
S/W RESET
S/W RESET (Bit 7):
This bit is the software reset bit.
Publication Release Date: March 1998
Version 0.61
- 33 -
W83877TF
POWER-DOWN (Bit 6):
0
1
FDC in normal mode
FDC in power-down mode
PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2):
These three bits select the value of write precompensation. The following tables show the
precompensation values for the combination of these bits.
PRECOM
PRECOMPENSATION DELAY
250K - 1Mbps
2 Mbps Tape drive
Default Delays
20.8nS
2
0
0
1
0
0
0
0
1
Default Delays
41.67 nS
0
1
0
83.34 nS
41.17nS
0
1
1
125.00 nS
62.5nS
1
0
0
166.67 nS
83.3nS
1
1
1
0
1
1
1
0
1
208.33 nS
104.2nS
250.00 nS
125.00nS
0.00 nS (disabled)
0.00nS (disabled)
DATA RATE
250 KB/S
300 KB/S
500 KB/S
1 MB/S
DEFAULT PRECOMPENSATION DELAYS
125 nS
125 nS
125 nS
41.67 nS
20.8 nS
2 MB/S
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC and reduced write current control.
00 500 KB/S (MFM), 250 KB/S (FM), RWC = 1.
01 300 KB/S (MFM), 150 KB/S (FM), RWC = 0.
10 250 KB/S (MFM), 125 KB/S (FM), RWC = 0.
11 1 MB/S (MFM), Illegal (FM), RWC = 1.
The 2MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as
well as setting 10 to DRTA1 and DRTA0 bits which are two of the Configuration CR2D. Please refer
to the function of CR2D and the data rate table for individual data rates setting.
Publication Release Date: March 1998
- 34 -
Version 0.61
W83877TF
2.2.7 FIFO Register (R/W base address + 5)
The Data Register consists of four status registers in a stack with only one register presented to the
data bus at a time. This register stores data, commands, and parameters and provides diskette-drive
status information. Data bytes are passed through the data register to program or obtain results after
a command. In the W83877TF, this register defaults to FIFO disabled mode after reset. The FIFO
can change its value and enable its operation through the CONFIGURE command.
Status Register 0 (ST0)
7-6
5
3
2
1-0
4
US1, US0 Drive Select:
00 Drive A selected
01 Drive B selected
10 Drive C selected
11 Drive D selected
HD Head address:
1 Head selected
0 Head selected
NR Not Ready:
1 Drive is not ready
0 Drive is ready
EC Equipment Check:
1 When a fault signal is received from the FDD or the track
0 signal fails to occur after 77 step pulses
0 No error
SE Seek end:
1 seek end
0 seek error
IC Interrupt Code:
00 Normal termination of command
01 Abnormal termination of command
10 Invalid command issue
11 Abnormal termination because the ready signal from FDD changed state during command executio
Status Register 1 (ST1)
7
6
5
4
3
2
1
0
Missing Address Mark. 1 When the FDC cannot detect the data address mark
or the data address mark has been deleted.
NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during
execution of write data.
ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data.
Not used. This bit is always 0.
OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer.
DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field.
Not used. This bit is always 0.
EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder.
Publication Release Date: March 1998
- 35 -
Version 0.61
W83877TF
Status Register 2 (ST2)
7
1
0
4
3
2
6
5
MD (Missing Address Mark in Data Field).
1 If the FDC cannot find a data address mark
(or the address mark has been deleted)
when reading data from the media
0 No error
BC (Bad Cylinder)
1 Bad Cylinder
0 No error
SN (Scan Not satisfied)
1 During execution of the Scan command
0 No error
SH (Scan Equal Hit)
1 During execution of the Scan command, if the equal condition is satisfied
0 No error
WC (Wrong Cylinder)
1 Indicates wrong Cylinder
DD (Data error in the Data field)
1 If the FDC detects a CRC error in the data field
0 No error
CM (Control Mark)
1 During execution of the read data or scan command
0 No error
Not used. This bit is always 0
Status Register 3 (ST3)
6
4
2
1
0
7
5
3
US0 Unit Select 0
US1 Unit Select 1
HD Head Address
TS Two-Side
TO Track 0
RY Ready
WP Write Protected
FT Fault
2.2.8 Digital Input Register (DI Register) (Read base address + 7)
The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or
AT only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of
DSKCHG , while other bits of the data bus remain in tri-state. Bit definitions are as follows:
7
6
5
4
3
2
1
0
x x x
x x x
x
Reserved for the hard disk controller
x
During a read of this register, these bits are in tri-state
DSKCHG
In the PS/2 mode, the bit definitions are as follows:
Publication Release Date: March 1998
Version 0.61
- 36 -
W83877TF
7
6
1
5
4
3
1
2
0
1
1
1
HIGH DENS
DRATE0
DRATE1
DSKCHG
DSKCHG (Bit 7):
This bit indicates the complement of the DSKCHG input.
Bit 6-3: These bits are always a logic 1 during a read.
DRATE1 DRATE0 (Bit 2, 1):
These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings
corresponding to the individual data rates.
HIGH DENS (Bit 0):
0
1
500 KB/S or 1 MB/S data rate (high density FDD)
250 KB/S or 300 KB/S data rate
In the PS/2 Model 30 mode, the bit definitions are as follows:
7
6
0
5
0
4
3
2
0
1
0
DRATE0
DRATE1
NOPREC
DMAEN
DSKCHG
DSKCHG (Bit 7):
This bit indicates the status of DSKCHG input.
Bit 6-4: These bits are always a logic 1 during a read.
DMAEN (Bit 3):
This bit indicates the value of DO REGISTER bit 3.
NOPREC (Bit 2):
This bit indicates the value of CC REGISTER NOPREC bit.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
Publication Release Date: March 1998
Version 0.61
- 37 -
W83877TF
2.2.9 Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as
follows:
4
2
1
3
6
5
7
0
x
x
x
x
x
x
DRATE0
DRATE1
X: Reserved
Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
In the PS/2 Model 30 mode, the bit definitions are as follows:
2
1
7
6
5
4
3
0
X
X
X
X
X
DRATE0
DRATE1
NOPREC
X: Reserved
Bit 7-3: Reserved. These bits should be set to 0.
NOPREC (Bit 2):
This bit indicates no precompensation. It has no function and can be set by software.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
Publication Release Date: March 1998
Version 0.61
- 38 -
W83877TF
3.0 UART PORT
3.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial
data to parallel format on the receiver side. The serial format, in order of transmission and reception,
is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half
(five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and
producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this
16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the
UARTs also include complete modem control capability and a processor interrupt system that may be
software trailed to the computing time required to handle the communication link. The UARTs have a
FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-
byte FIFOs for both receive and transmit mode.
Publication Release Date: March 1998
- 39 -
Version 0.61
W83877TF Data Sheet Revision History
Pages
n.a.
Dates
Version Version
on Web
0.50
Main Contents
Not published, for internal reference only.
First published.
1
2
3
03/20/97
05/20/97
03/20/98
n.a.
0.60
0.61
1,8,9,63,65,
78,80,104-
107,116,118,
119,133
Typo correction and data calibrated
4
5
6
7
8
9
10
Please note that all data and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result
in personal injury. Winbond customers using or selling these products for use in
such applications do so at their own risk and agree to fully indemnify Winbond for
any damages resulting from such improper use or sales.
W83877TF
WINBOND I/O
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................1
FEATURES ..........................................................................................................................2
PIN CONFIGURATION......................................................................................................4
1.0
1.1
1.2
1.3
1.4
PIN DESCRIPTION ........................................................................................................................5
HOST INTERFACE .........................................................................................................................5
SERIAL PORT INTERFACE ...........................................................................................................7
MULTI-MODE PARALLEL PORT..................................................................................................8
FDC INTERFACE..........................................................................................................................14
2.0 FDC FUNCTIONAL DESCRIPTION........................................................................16
2.1
2.2
W83877TF FDC .............................................................................................................................16
REGISTER DESCRIPTIONS .........................................................................................................28
3.0 UART PORT................................................................................................................39
3.1
3.2
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)..................39
REGISTER ADDRESS...................................................................................................................40
4.0 PARALLEL PORT.....................................................................................................49
4.1
4.2
4.3
4.4
4.5
PRINTER INTERFACE LOGIC.....................................................................................................49
ENHANCED PARALLEL PORT (EPP) .........................................................................................51
EXTENDED CAPABILITIES PARALLEL (ECP) PORT...............................................................55
EXTENSION FDD MODE (EXTFDD)...........................................................................................64
EXTENSION 2FDD MODE (EXT2FDD).......................................................................................64
5.0 PLUG AND PLAY CONFIGURATION ....................................................................65
6.0 ACPI /LEGACY FEATURE AND AUTO POWER MANAGEMENT.....................65
6.1
6.2
ACPI/LEGACY POWER MANAGEMENT ...................................................................................65
AUTO(DEVICE) POWER MANAGEMENT..................................................................................65
Publication Release Date: May 1997
- I -
Preliminary Version 0.60
W83877TF
7.0 SERIAL IRQ.................................................................................................................66
7.1
7.2
7.3
7.4
START FRAME .............................................................................................................................67
IRQ/DATA FRAME.......................................................................................................................67
STOP FRAME................................................................................................................................68
RESET AND INITIALIZATION....................................................................................................68
8.0 EXTENDED FUNCTION REGISTERS ....................................................................69
8.1 EXTENDED FUNCTIONS ENABLE REGISTERS (EFERS).............................................................69
8.2 EXTENDED FUNCTION INDEX REGISTERS (EFIRS), EXTENDED FUNCTION DATA
REGISTERS (EFDRS) .....................................................................................................................70
8.3 ACPI REGISTERS FEATURES .......................................................................................................113
8.4 ACPI REGISTERS (ACPIRS)...........................................................................................................115
9.0 SPECIFICATIONS....................................................................................................129
9.1
9.2
9.2
9.3
ABSOLUTE MAXIMUM RATINGS............................................................................................129
DC CHARACTERISTICS ............................................................................................................129
DC CHARACTERISTICS, CONTINUED ....................................................................................130
AC CHARACTERISTICS ............................................................................................................131
10.0 TIMING WAVEFORMS ........................................................................................137
10.1 FDC..............................................................................................................................................137
10.2 UART/PARALLEL.......................................................................................................................138
10.3 PARALLEL PORT .......................................................................................................................140
11.0 APPLICATION CIRCUITS....................................................................................146
11.1 PARALLEL PORT EXTENSION FDD ........................................................................................146
11.2 PARALLEL PORT EXTENSION 2FDD.......................................................................................147
11.3 FOUR FDD MODE......................................................................................................................147
12.0 ORDERING INFORMATION ...............................................................................148
13.0 HOW TO READ THE TOP MARKING ...............................................................148
14.0 PACKAGE DIMENSIONS.....................................................................................149
Publication Release Date: May 1997
- II -
Preliminary Version 0.60
W83877TF
4.0 PARALLEL PORT
4.1 Printer Interface Logic
The parallel port of the W83877TF makes possible the attachment of various devices that accept
eight bits of parallel data at standard TTL level. The W83877TF supports an IBM XT/AT compatible
parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended
Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), and Extension 2FDD mode
(EXT2FDD) on the parallel port. Refer to the configuration registers for more information on disabling,
power-down, and on selecting the mode of operation.
Table 4-1 shows the pin definitions for different modes of the parallel port.
TABLE 4-1-A Parallel Port Connector and Pin Definition for SPP/EPP/ECP Modes
HOST
CONNECTOR
PIN NUMBER
OF W83877TF
PIN
ATTRIBUTE
SPP
EPP
ECP
1
19
O
I/O
I
nSTB
PD<0:7>
nACK
BUSY
PE
nWrite
PD<0:7>
Intr
nSTB, HostClk
PD<0:7>
2-9
10
11
12
13
14
15
16
17
9-14,16-17
26
24
27
28
20
29
21
22
nACK, PeriphClk
BUSY, PeriphAck
2
I
nWait
PE
2
I
PEerror, nAckReverse
SLCT, Xflag
I
SLCT
nAFD
nERR
nINIT
nSLIN
Select
nDStrb
nError
nInit
2
O
I
nAFD, HostAck
1
2
nFault , nPeriphRequest
1
2
O
O
nINIT , nReverseRqst
1
2
nAStrb
nSLIN , ECPMode
Notes:
n<name > : Active Low
1. Compatible Mode
2. High Speed Mode
3. For more information, refer to the IEEE 1284 standard.
Publication Release Date: March 1998
Version 0.61
- 49 -
W83877TF
TABLE 4-1-B Parallel Port Connector and Pin Definition for EXTFDD and EXT2FDD Modes
HOST
CONNECTOR
PIN NUMBER
OF W83877TF
PIN
ATTRIBUTE
SPP
PIN
ATTRIBUTE
EXT2FDD
PIN
ATTRIBUTE
EXTFDD
1
2
19
9
O
nSTB
PD0
---
I
---
---
I
---
I/O
INDEX2
TRAK02
WP2
INDEX2
3
4
5
6
10
11
12
13
I/O
I/O
I/O
I/O
PD1
PD2
PD3
PD4
I
I
I
I
I
I
I
I
RDATA2
RDATA2
DSKCHG2
---
DSKCHG2
7
8
14
15
I/O
I/O
PD5
PD6
---
---
---
---
---
OD
MOA2
DSA2
DSB2
MOB2
WD2
9
16
26
24
27
28
20
29
21
22
I/O
I
PD7
nACK
BUSY
PE
OD
OD
OD
OD
OD
OD
OD
OD
OD
---
---
10
11
12
13
14
15
16
17
OD
OD
OD
OD
OD
OD
OD
OD
I
I
WD2
WE2
I
SLCT
nAFD
nERR
nINIT
nSLIN
WE2
O
I
RWC2
NERR2
DIR2
RWC2
O
O
DIR2
STEP2
Publication Release Date: March 1998
Version 0.61
- 50 -
W83877TF
4.2 Enhanced Parallel Port (EPP)
TABLE 4-2 PRINTER MODE AND EPP REGISTER ADDRESS
A2
0
A1
0
A0
0
REGISTER
NOTE
Data port (R/W)
1
1
1
1
2
2
2
2
2
0
0
1
Printer status buffer (Read)
Printer control latch (Write)
Printer control swapper (Read)
EPP address port (R/W)
EPP data port 0 (R/W)
0
1
0
0
1
0
0
1
1
1
0
0
1
0
1
EPP data port 1 (R/W)
1
1
0
EPP data port 2 (R/W)
1
1
1
EPP data port 2 (R/W)
Notes:
1. These registers are available in all modes.
2. These registers are available only in EPP mode.
4.2.1 Data Swapper
The system microprocessor can read the contents of the printer's data latch by reading the data
swapper.
4.2.2 Printer Status Buffer
The system microprocessor can read the printer status by reading the address of the printer status
buffer. The bit definitions are as follows:
7
6
5
4
3
2
1
0
1
1
TMOUT
ERROR
SLCT
PE
ACK
BUSY
Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print
head is changing position, or during an error state. When this signal is active, the printer is
busy and cannot accept data.
Publication Release Date: March 1998
- 51 -
Version 0.61
W83877TF
Bit 6: This bit represents the current state of the printer's
signal. A 0 means the printer has
ACK
received a character and is ready to accept another. Normally, this signal will be active for
approximately 5 microseconds before BUSY stops.
Bit 5: A 1 means the printer has detected the end of paper.
Bit 4: A 1 means the printer is selected.
Bit 3: A 0 means the printer has encountered an error condition.
Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register.
Bit 0: This bit is valid in EPP mode only. It indicates that a 10 mS time-out has occurred on the EPP
bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error
has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0
has no effect.
4.2.3 Printer Control Latch and Printer Control Swapper
The system microprocessor can read the contents of the printer control latch by reading the printer
control swapper. Bit definitions are as follows:
7
1
6
1
5
4
3
2
1
0
STROBE
AUTO FD
INIT
SLCT IN
IRQ ENABLE
DIR
Bit 7, 6: These two bits are a logic one during a read. They can be written.
Bit 5: Direction control bit
When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the
parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit is
invalid and fixed at zero.
Bit 4: A 1 in this position allows an interrupt to occur when ACK changes from low to high.
Bit 3: A 1 in this bit position selects the printer.
Bit 2: A 0 starts the printer (50 microsecond pulse, minimum).
Bit 1: A 1 causes the printer to line-feed after a line is printed.
Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be
present for a minimum of 0.5 microseconds before and after the strobe pulse.
Publication Release Date: March 1998
- 52 -
Version 0.61
W83877TF
4
.2.4 EPP Address Port
The address port is available only in EPP mode. Bit definitions are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write
operation. The leading edge of IOW causes an EPP address write cycle to be performed, and the
trailing edge of IOW latches the data for the duration of the EPP write cycle.
PD0-PD7 ports are read during a read operation. The leading edge of IOR causes an EPP address
read cycle to be performed and the data to be output to the host CPU.
4.2.5 EPP Data Port 0-3
These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-
inverting) and output to the ports PD0-PD7 during a write operation. The leading edge of IOW causes
an EPP data write cycle to be performed, and the trailing edge of IOW latches the data for the
duration of the EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of IOR causes an EPP read
cycle to be performed and the data to be output to the host CPU.
Publication Release Date: March 1998
- 53 -
Version 0.61
W83877TF
4
.2.6 Bit Map of Parallel Port and EPP Registers
REGISTER
Data Port (R/W)
7
6
5
4
3
2
PD2
1
1
PD1
1
0
PD7
PD6 PD5
PD4
SLCT
PD3
PD0
Status Buffer (Read)
PE
TMOUT
BUSY ACK
ERROR
SLIN
Control Swapper (Read)
Control Latch (Write)
1
1
1
1
1
IRQEN
IRQ
INIT
AUTOFD STROBE
AUTOFD STROBE
DIR
SLIN
INIT
EPP Address Port
(R/W)
PD7
PD6 PD5
PD4
PD3
PD2
PD1
PD0
EPP Data Port 0 (R/W)
EPP Data Port 1 (R/W)
EPP Data Port 2 (R/W)
EPP Data Port 3 (R/W)
PD7
PD7
PD7
PD7
PD6 PD5
PD6 PD5
PD6 PD5
PD6 PD5
PD4
PD4
PD4
PD4
PD3
PD3
PD3
PD3
PD2
PD2
PD2
PD2
PD1
PD1
PD1
PD1
PD0
PD0
PD0
PD0
4.2.7 EPP Pin Descriptions
EPP NAME
nWrite
TYPE
EPP DESCRIPTION
O
I/O
I
Denotes an address or data read or write operation.
Bi-directional EPP address and data bus.
PD<0:7>
Intr
Used by peripheral device to interrupt the host.
nWait
I
Inactive to acknowledge that data transfer is completed. Active to
indicate that the device is ready for the next transfer.
PE
I
I
Paper end; same as SPP mode.
Select
nDStrb
nError
nInits
Printer selected status; same as SPP mode.
This signal is active low. It denotes a data read or write operation.
Error; same as SPP mode.
O
I
O
This signal is active low. When it is active, the EPP device is reset to its
initial operating mode.
nAStrb
O
This signal is active low. It denotes an address read or write operation.
4.2.8 EPP Operation
When the EPP mode is selected in the configuration register, the standard and bi-directional modes
are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or
address cycle is currently being executed. In this condition all output signals are set by the SPP
Control Port and the direction is controlled by DIR of the Control Port.
Publication Release Date: March 1998
- 54 -
Version 0.61
W83877TF
A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 mS
have elapsed from the start of the EPP cycle to the time
is de-asserted. The current EPP cycle
WAIT
is aborted when a time-out occurs. The time-out condition is indicated in Status bit 0.
EPP Operation
The EPP operates on a two-phase cycle. First, the host selects the register within the device for
subsequent operations. Second, the host performs a series of read and/or write byte operations to the
selected register. Four operations are supported on the EPP: Address Write, Data Write, Address
Read, and Data Read. All operations on the EPP device are performed synchronously.
EPP Version 1.9 Operation
The EPP read/write operation can be completed under the following conditions:
a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or
write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds
normally and will be completed when nWait goes inactive high.
b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to
active low, at which time it will start as described above.
EPP Version 1.7 Operation
The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the
read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive
high.
4.3 Extended Capabilities Parallel (ECP) Port
This port is software and hardware compatible with existing parallel ports, so it may be used as a
standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel
that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host)
directions.
Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth
requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for
the standard parallel port to improve compatibility mode transfer speed.
The ECP port supports run-length-encoded (RLE) decompression (required) in the hardware.
Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates
how many times the next byte is to be repeated. The hardware support for compression is optional.
For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and
ISA Interface Standard.
Publication Release Date: March 1998
- 55 -
Version 0.61
W83877TF
4.3.1 ECP Register and Mode Definitions
NAME
data
ADDRESS
Base+000h
Base+000h
Base+001h
Base+002h
Base+400h
Base+400h
Base+400h
Base+400h
Base+401h
Base+402h
I/O
R/W
R/W
R
ECP MODES
FUNCTION
Data Register
000-001
011
All
ecpAFifo
dsr
ECP FIFO (Address)
Status Register
dcr
R/W
R/W
R/W
R/W
R
All
Control Register
cFifo
010
011
110
111
111
All
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
Configuration Register A
Configuration Register B
Extended Control Register
R/W
R/W
Note: The base addresses are specified by CR23, which are determined by configuration register or hardware setting.
MODE
000
001
010
011
100
101
110
111
DESCRIPTION
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
ECP Parallel Port mode
EPP mode (If this option is enabled in the CR9 and CR0 to select ECP/EPP mode)
Reserved
Test mode
Configuration mode
Note: The mode selection bits are bit 7-5 of the Extended Control Register.
4.3.2 Data and ecpAFifo Port
Modes 000 (SPP) and 001 (PS/2) (Data Port)
During a write operation, the Data Register latches the contents of the data bus on the rising edge of
the input. The contents of this register are output to the PD0-PD7 ports. During a read operation,
ports PD0-PD7 are read and output to the host. The bit definitions are as follows:
Publication Release Date: March 1998
- 56 -
Version 0.61
W83877TF
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Mode 011 (ECP FIFO-Address/RLE)
A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The
hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this
register is defined only for the forward direction. The bit definitions are as follows:
7
6
5
4
3
2
1
0
Address or RLE
Address/RLE
4.3.3 Device Status Register (DSR)
These bits are at low level during a read of the Printer Status Register. The bits of this status register
are defined as follows:
7
6
5
4
3
2
1
0
1
1
1
nFault
Select
PError
nAck
nBusy
Bit 7: This bit reflects the complement of the Busy input.
Bit 6: This bit reflects the nAck input.
Bit 5: This bit reflects the PError input.
Bit 4: This bit reflects the Select input.
Bit 3: This bit reflects the nFault input.
Bit 2-0: These three bits are not implemented and are always logic one during a read.
Publication Release Date: March 1998
Version 0.61
- 57 -
W83877TF
4.3.4 Device Control Register (DCR)
The bit definitions are as follows:
7
6
5
4
3
2
1
0
1
1
Strobe
Autofd
nInit
Select In
AckInt En
Direction
Bit 6, 7: These two bits are logic one during a read and cannot be written.
Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is
valid in all other modes.
0 the parallel port is in output mode.
1 the parallel port is in input mode.
Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt
requests from the parallel port to the CPU due to a low to high transition on the ACK input.
Bit 3: This bit is inverted and output to the SLIN output.
0 The printer is not selected.
1 The printer is selected.
Bit 2: This bit is output to the INIT output.
Bit 1: This bit is inverted and output to the AFD output.
Bit 0: This bit is inverted and output to the STB output.
4.3.5 cFifo (Parallel Port Data FIFO) Mode = 010
This mode is defined only for the forward direction. The standard parallel port protocol is used by a
hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this
FIFO. Transfers to the FIFO are byte aligned.
4.3.6 ecpDFifo (ECP Data FIFO) Mode = 011
When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a
hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are
byte aligned.
When the direction bit is 1, data bytes from the peripheral are read under automatic hardware
handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to
the system.
Publication Release Date: March 1998
- 58 -
Version 0.61
W83877TF
4.3.7 tFifo (Test FIFO Mode) Mode = 110
Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction.
Data in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be
displayed on the parallel port data lines.
4.3.8 cnfgA (Configuration Register A) Mode = 111
This register is a read-only register. When it is read, 10H is returned. This indicates to the system that
this is an 8-bit implementation.
4.3.9 cnfgB (Configuration Register B) Mode = 111
The bit definitions are as follows:
7
6
5
4
3
2
1
1
0
1
1
IRQx 0
IRQx 1
IRQx 2
intrValue
compress
Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support
hardware RLE compression.
Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts.
Bit 5-3: Reflect the IRQ resource assigned for ECP port.
cnfgB[5:3]
000
IRQ resource
reflect other IRQ resources selected by PnP register (default)
001
IRQ7
010
IRQ9
011
IRQ10
IRQ11
IRQ14
IRQ15
IRQ5
100
101
110
111
Bit 2-0: These five bits are at high level during a read and can be written.
Publication Release Date: March 1998
Version 0.61
- 59 -
W83877TF
4.3.10 ecr (Extended Control Register) Mode = all
This register controls the extended ECP parallel port functions. The bit definitions are follows:
7
6
5
4
3
2
1
0
Empty
Full
Service Intr
DMA En
nErrIntr En
MODE
MODE
MODE
Bit 7-5: These bits are read/write and select the mode.
000
001
Standard Parallel Port mode. The FIFO is reset in this mode.
PS/2 Parallel Port mode. This is the same as 000 except that direction may be
used to tri-state the data lines and reading the data register returns the value on the
data lines and not the value in the data register.
010
011
Parallel Port FIFO mode. This is the same as 000 except that bytes are written or
DMAed to the FIFO. FIFO data are automatically transmitted using the standard
parallel port protocol. This mode is useful only when direction is 0.
ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed
into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and
transmitted automatically to the peripheral using ECP Protocol. When the direction
is 1 (reverse direction) bytes are moved from the ECP parallel port and packed into
bytes in the ecpDFifo.
100
Selects EPP Mode. In this mode, EPP is active if the EPP supported option is
selected.
101
110
Reserved.
Test Mode. The FIFO may be written and read in this mode, but the data will not be
transmitted on the parallel port.
111
Configuration Mode. The confgA and confgB registers are accessible at 0x400 and
0x401 in this mode.
Bit 4: Read/Write (Valid only in ECP Mode)
1
0
Disables the interrupt generated on the asserting edge of nFault.
Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted
(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.
Bit 3: Read/Write
1
0
Enables DMA.
Disables DMA unconditionally.
Publication Release Date: March 1998
- 60 -
Version 0.61
W83877TF
Bit 2: Read/Write
1
0
Disables DMA and all of the service interrupts.
Enables one of the following cases of interrupts. When one of the service interrupts
has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to
0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.
(a) dmaEn = 1:
During DMA this bit is set to a 1 when terminal count is reached.
(b) dmaEn = 0 direction = 0:
This bit is set to 1 whenever there are writeIntr Threshold or more bytes free in the
FIFO.
(c) dmaEn = 0 direction = 1:
This bit is set to 1 whenever there are readIntr Threshold or more valid bytes to be
read from the FIFO.
Bit 1: Read only
0
1
The FIFO has at least 1 free byte.
The FIFO cannot accept another byte or the FIFO is completely full.
Bit 0: Read only
0
1
The FIFO contains at least 1 byte of data.
The FIFO is completely empty.
4.3.11 Bit Map of ECP Port Registers
D7
D6
D5
D4
D3
D2
D1
D0
NOTE
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
data
Addr/RLE
nBusy
1
Address or RLE field
2
1
1
2
2
2
ecpAFifo
dsr
nAck
1
PError
Select
nFault
1
1
1
Directio
ackIntEn
SelectIn
nInit
autofd
strobe
dcr
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
cFifo
ecpDFifo
tFifo
0
0
0
1
1
1
0
1
0
1
0
1
0
1
cnfgA
cnfgB
ecr
compress
intrValue
MODE
nErrIntrEn
dmaEn
serviceIntr
full
empty
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16-byte FIFO.
Publication Release Date: March 1998
Version 0.61
- 61 -
W83877TF
4
.3.12 ECP Pin Descriptions
NAME
TYPE
DESCRIPTION
nStrobe (HostClk)
O
The nStrobe registers data or address into the slave on the
asserting edge during write operations. This signal
handshakes with Busy.
PD<7:0>
I/O
I
These signals contains address or data or RLE data.
nAck (PeriphClk)
This signal indicates valid data driven by the peripheral when
asserted. This signal handshakes with nAutofd in reverse.
Busy (PeriphAck)
I
This signal desserts to indicate that the peripheral can accept
data. It indicates whether the data lines contain ECP
command information or data in the reverse direction. When
in reverse direction, normal data are transferred when Busy
(PeriphAck) is high and an 8-bit command is transferred when
it is low.
PError (nAckReverse)
I
This signal is used to acknowledge a change in the direction
of the transfer (asserted = forward). The peripheral drives this
signal low to acknowledge nReverseRequest. The host relies
upon nAckReverse to determine when it is permitted to drive
the data bus.
Select (Xflag)
I
Indicates printer on line.
nAutoFd (HostAck)
O
Requests a byte of data from the peripheral when it is
asserted. This signal indicates whether the data lines contain
ECP address or data in the forward direction. When in forward
direction, normal data are transferred when nAutoFd
(HostAck) is high and an 8-bit command is transferred when it
is low.
nFault (nPeriphRequest)
I
Generates an error interrupt when it is asserted. This signal is
valid only in the forward direction. The peripheral is permitted
(but not required) to drive this pin low to request a reverse
transfer during ECP Mode.
nInit (nReverseRequest)
nSelectIn (ECPMode)
O
O
This signal sets the transfer direction (asserted = reverse,
deasserted = forward). This pin is driven low to place the
channel in the reverse direction.
This signal is always deasserted in ECP mode.
Publication Release Date: March 1998
- 62 -
Version 0.61
W83877TF
4.3.13 ECP Operation
The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol
before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The
following are required:
(a) Set direction = 0, enabling the drivers.
(b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state.
(c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state.
(d) Set mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo,
respectively.
Mode Switching
Software will execute P1284 negotiation and all operations prior to a data transfer phase under
programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake,
moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010).
If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001
it can only be switched into mode 000 or 001. The direction can be changed only in mode 001.
When in extended forward mode, the software should wait for the FIFO to be empty before switching
back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the
FIFO before changing back to mode 000 or 001.
Command/Data
ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction,
normal data are transferred when HostAck is high and an 8-bit command is transferred when HostAck
is low. The most significant bits of the command indicate whether it is a run-length count (for
compression) or a channel address.
In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is
transferred when PeriphAck is low. The most significant bit of the command is always zero.
Data Compression
The W83877TF supports run length encoded (RLE) decompression in hardware and can transfer
compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported.
In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data
byte is written to the ecpDFifo.
4.3.14 FIFO Operation
The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can
proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO
is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO
is disabled.
Publication Release Date: March 1998
- 63 -
Version 0.61
W83877TF
4.3.15 DMA Transfers
DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC
DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA
will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the
DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the
DMA.
4.3.16 Programmed I/O (NON-DMA) Mode
The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O.
Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo
located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and
serviceIntr = 0 in the programmed I/O transfers.
The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The
programmed I/O will empty or fill the FIFO using the appropriate direction and mode.
4.4 Extension FDD Mode (EXTFDD)
In this mode, the W83877TF changes the printer interface pins to FDC input/output pins, allowing the
user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin
assignments for the FDC input/output pins are shown in Table 5-1.
After the printer interface is set to EXTFDD mode, the following occur:
(1) Pins MOB and DSB will be forced to inactive state.
(2) Pins DSKCHG, RDATA, WP, TRAK0, INDEX will be logically ORed with pins PD4-PD0 to
serve as input signals to the FDC.
(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for
FDD open drain/collector output.
(4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating
system, a warm reset is needed to enable the system to recognize the extension floppy drive.
4.5 Extension 2FDD Mode (EXT2FDD)
In this mode, the W83877TF changes the printer interface pins to FDC input/output pins, allowing the
user to install two external floppy disk drives through the DB-25 printer connector to replace internal
floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table 5-
1.
After the printer interface is set to EXTFDD mode, the following occur:
(1) Pins MOA , DSA, MOB, and DSB will be forced to inactive state.
(2) Pins DSKCHG, RDATA, WP, TRAK0, and INDEX will be logically ORed with pins PD4-PD0 to
serve as input signals to the FDC.
(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for
FDD open drain/collector output.
(4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating
system, a warm reset is needed to enable the system to recognize the extension floppy drive.
Publication Release Date: March 1998
- 64 -
Version 0.61
W83877TF
5.0 PLUG AND PLAY CONFIGURATION
A powerful new plug-and-play function has been built into the W83877TF to help simplify the task of
setting up a computer environment. With appropriate support from BIOS manufacturers, the system
designer can freely allocate Winbond I/O devices (i.e., the FDC, PRT and UART ) in the PC's I/O
space (100H - 3FFH). In addition, the W83877TF also provides 8 interrupt requests and 3 DMA pairs
for designers to assign in interfacing FDCs, UARTs, and PRTs. Hence this powerful I/O chip offers
greater flexibility for system designers.
The PnP feature is implemented through a set of Extended Function Registers (CR20 to 29). Details
on configuring these registers are given in Section 8. The default values of these PnP-related
registers set the system to a configuration compatible with environments designed with previous
Winbond I/O chips.
6.0 ACPI /LEGACY FEATURE AND AUTO POWER MANAGEMENT
6.1 ACPI/Legacy power management
W83877TF supports both ACPI and legacy power management models. For the ACPI power
management, the SCI pin is dedicated to the SCI interrupt signal for the SCI interrupt handler; For
the legacy power management, the SMI pin is dedicated to the SMI interrupt signal for the SMI
interrupt handler.
Two register blocks is used for the ACPI/Legacy power management. They are the PM1 and GPE
register blocks. Their base addresses are held in the W83877TF configuration registers CR33 and
CR34 respectively. Configuration registers CR40 to CR45 are for the legacy power management. The
above configuration registers hold the interrupt event enable and status bits of the SMI interrupts.
Control over the routing of SCI and SMI interrupts to the output pins is also contained in the above
registers.
One 24-bit power management timer is also implemented. It provides an accurate time value used by
the system software to measure and profiles system idleness.
6.2 Device(auto) power management
W83877TF also provides the auto power management function for each device within it. They are the
printer port, FDC, UART A, and UART B devices in W83877TF respectively. Device idle and trap
status are provided to indicate the device's working/sleeping state. Device idle timer with
programmable initial value is provided for each device, which enter the powerdown state when the
powerdown conditions are met. Any access to certain registers and external event input will wake up
the devices. The global stand-by timer deals with the other logic part excluding the printer port, FDC,
UART A , and UART B devices. The global stand-by timer reloads and counts down as soon as the 4
devices enter the powerdown mode and W83877TF enters the powerdown mode as soon as it
expires. Once any device is awakened, the global stand-by is also awakened. The initial count values
of the devices are held in the configuration registers CR35 to CR39.
Publication Release Date: March 1998
- 65 -
Version 0.61
W83877TF
7.0 SERIAL IRQ
W83877TF supports a serial IRQ scheme. This allow a signal line to be used to report the legacy ISA
interrupt requests. Because more than one device may need to share the signal serial IRQ signal
line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is
transferred on the IRQSER signal, one cycle consisting of three frames types: a start frame, several
IRQ/Data frame, and one Stop frame. The serial interrupt scheme adheres to the Serial IRQ
Specification for PCI System, Version 6.0.
Ti mi ng Di agr ams For I RQSER Cycl e
St ar t Fr ame t i mi ng wi t h sour ce sampl ed a l ow pul se on I RQ1
START FRAME
IRQ0 FRAME
IRQ1 FRAME
IRQ2 FRAME
SL
or
H
H
R
T
S
R
T
S
R
T
S
R
T
PCICLK
IRQSER
1
START
Drive Source
Host Controller
SL=Slave Control
1. Start Frame pulse can be 4-8 clocks wide.
None
IRQ1
T=Turn-around
None
S=Sample
IRQ1
H=Host Control
R=Recovery
Stop Frame Timing with Host using 17 IRQSER sampling period
IRQ14
FRAME
IRQ15
FRAME
IOCHCK
FRAME
STOP FRAME
NEXT CYCLE
2
S
R
T
S
R
T
S
R
T
I
H
R
T
PCICLK
IRQSER
1
3
STOP
START
Drive
None
IRQ15
None
Host Controller
S=Sample
H=Host Control
R=Recovery
T=Turn-around
I=Idle
1. Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
2. There may be none, one or more Idle states during the Stop Frame.
3. The next IRQSER cycle's Start Frame pulse may or may not start immediately after the turn-around clock of the Stip Frame.
Publication Release Date: March 1998
Version 0.61
- 66 -
W83877TF
7.1 Start Frame
There are two modes of operation for the IRQSER Start frame: Quiet mode and Continuous mode.
In the Quiet mode, the peripheral drives the SERIRQ signal active low for one clock, and then tri-
states it. This brings all the states machines of the peripherals from idle to active states. the host
controller will then take over driving IRQSER signal low in the next clock and will continue driving the
IRQSER low for programmable 3 to 7 clock periods. This makes the total number of clocks low for 4
to 8 clock periods. After these clocks, the host controller will drive the IRQSER high for one clock and
then tri-stated.
In the Continuous mode, only the host controller initiates the START frame to update IRQ/Data line
information. The host controller drives the IRQSER signal low for 4 to 8 period clocks. Upon reset, the
IRQSER signal is defaulted to the Continuous mode for the host controller to initiate the first Start
frame.
7.2 IRQ/Data Frame
Once the start frame has been initiated, all the peripherals must start counting frames based on the
rising edge of the start pulse. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase,
and Turn-around phase.
During the Sample phase, the peripheral drives SERIRQ low if the corresponding IRQ should be
active. If the corresponding IRQ is inactive, then IRQSER must be left tri-stated. During the Recovery
phase, the peripheral device drives the IRQSER high. During the Turn-around phase, the peripheral
device left the IRQSER tri-stated.
The IRQ/Data Frame has a number of specific order, as shown in Table 7-1.
Publication Release Date: March 1998
- 67 -
Version 0.61
W83877TF
Table 7-1 IRQSER Sampling periods
IRQ/Data Frame
Signal Sampled
# of clocks past Start
1
2
3
IRQ0
IRQ1
2
5
8
SMI
IRQ3
4
5
11
14
17
20
23
26
29
32
35
38
41
44
47
50
IRQ4
6
IRQ5
7
IRQ6
8
IRQ7
9
IRQ8
10
11
12
13
14
15
16
17
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IOCHCK
INTA
18
19
53
56
59
62
95
INTB
20
INTC
21
INTD
32:22
Unassigned
7.3 Stop Frame
After all IRQ/Data Frames have completed , the host controller will terminate IRQSER by a Stop
frame. Only the host controller can initiate the Stop frame by driving IRQSER low for 2 or 3 clocks. If
the Stop Frame is low for 2 clocks, the next IRQSER cycle's Sample mode is the Quiet mode. If the
Stop Frame is low for 3 clocks, the next IRQSER cycle's Sample mode is the Continuous mode.
7.4 Reset and Initialization
After MR reset, IRQSER Slaves are put into the Continuous(Idle) mode. The Host Controller is
responsible for starting the initial IRQSER Cycle to collect system's IRQ/Data default values. The
system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for
subsequent IRQSER cycles. It's the Host Controller's responsibility to provide the default values to
8259's and other system logic before the first IRQSER cycle is performed. For IRQSER system
suspend, insertion, or removal application, the Host controller should be programmed into
Continuous(Idle) mode first. This is to guarantee IRQSER bus in the Idle state before the system
configuration changes.
Publication Release Date: March 1998
- 68 -
Version 0.61
W83877TF
8.0 EXTENDED FUNCTION REGISTERS
The W83877TF provides many configuration registers for setting up different types of configurations.
After power-on reset, the state of the hardware setting of each pin will be latched by the relevant
configuration register to allow the W83877TF to enter the proper operating configuration. To protect
the chip from invalid reads or writes, the configuration registers cannot be accessed by the user.
There are four ways to enable the configuration.
n registers to be read or written. HEFERE (CR0C bit 5) and HEFRAS (CR16 bit 0) can be used to
select one out of these four methods of entering the Extended Function mode as follows:
HEFRAS
HEFERE
address and value
write 88H to the location 250H
0
0
1
1
0
1
0
1
write 89H to the location 250H (power-on default)
write 86H to the location 3F0H twice
write 87H to the location 3F0H twice
First, a specific value must be written once (88H/89H) or twice (86H/87H) to the Extended Functions
Enable Register (I/O port address 250H or 3F0H). Second, an index value (00H-19H, 20H-29H, 2CH-
2DH, 31H-3AH, 40H-45H) must be written to the Extended Functions Index Register (I/O port address
251H or 3F0H) to identify which configuration register is to be accessed. The designer can then
access the desired configuration register through the Extended Functions Data Register (I/O port
address 252H or 3F1H).
After programming of the configuration register is finished, an additional value should be written to
EFERs to exit the Extended Function mode to prevent unintentional access to those configuration
registers. In the case of EFER at 250H, this additional value can be any value other than 88H if
HEFERE = 0 and 89H if HEFERE = 1. While EFER is at 3F0H, this additional value must be AAH.
The designer can also set bit 6 of CR9 (LOCKREG) to high to protect the configuration registers
against accidental accesses.
The configuration registers can be reset to their default or hardware settings only by a cold reset (pin
MR = 1). A warm reset will not affect the configuration registers.
8.1 Extended Functions Enable Registers (EFERs)
After a power-on reset, the W83877TF enters the default operating mode. Before the W83877TF
enters the extended function mode, a specific value must be programmed into the Extended Function
Enable Register (EFER) so that the extended function register can be accessed. The Extended
Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are
250H or 3F0H (as described in the above section).
Publication Release Date: March 1998
- 69 -
Version 0.61
W83877TF
9.0 SPECIFICATIONS
9.1 Absolute Maximum Ratings
PARAMETER
Power Supply Voltage
Input Voltage
RATING
-0.5 to 7.0
UNIT
V
-0.5 to VDD+0.5
0 to +70
V
Operating Temperature
Storage Temperature
° C
° C
-55 to +150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
9.2 DC CHARACTERISTICS
(Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V)
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNI
CONDITIONS
I/O8tc - TTL level output pin with source-sink capabilities of 8 mA; CMOS level input voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
-0.5
0.3xVDD
VDD+0.5
0.4
V
V
0.7xVDD
V
IOL = 8 mA
IOH = -8 mA
VIN = VDD
VIN = 0V
2.4
V
+10
-10
mA
mA
I/O12t - TTL level bi-directional pin with source-sink capabilities of 12 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
-0.5
2.0
0.8
VDD+0.5
0.4
V
V
V
IOL = 12 mA
IOH = -12 mA
VIN = VDD
2.4
V
+10
-10
mA
mA
VIN = 0V
I/O24t - TTL level bi-directional pin with source-sink capabilities of 24 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
-0.5
2.0
0.8
VDD+0.5
0.4
V
V
V
IOL = 24 mA
IOH = -24 mA
VIN = VDD
2.4
V
+10
-10
mA
mA
VIN = 0V
Publication Release Date: March 1998
Version 0.61
- 129 -
W83877TF
9.2 DC Characteristics, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
OUT8t - TTL level output pin with source-sink capabilities of 8 mA
Output Low Voltage
Output High Voltage
VOL
VOH
0.4
V
V
IOL = 8 mA
IOH = -8 mA
2.4
OUT12t - TTL level output pin with source-sink capabilities of 12 mA
Output Low Voltage
Output High Voltage
VOL
VOH
0.4
V
V
IOL = 12 mA
IOH = -12 mA
2.4
OD12 - Open-drain output pin with sink capabilities of 12 mA
Output Low Voltage 0.4
OD24 - Open-drain output pin with sink capabilities of 24 mA
VOL
V
V
IOL = 12 mA
IOL = 24 mA
Output Low Voltage
INt - TTL level input pin
Input Low Voltage
VOL
0.4
VIL
VIH
ILIH
ILIL
0.8
V
V
VDD = 5 V
VDD = 5 V
VIN = VDD
VIN = 0V
Input High Voltage
Input High Leakage
Input Low Leakage
2.0
+10
-10
mA
mA
INts - TTL level input pin Schmitt-trigger input pin
Input Low Threshold Voltage
Input High Threshold Voltage
Hysteresis (Vt+ - Vt-)
Input High Leakage
Vt-
Vt+
0.5
1.6
0.5
0.8
2.0
1.2
1.1
2.4
V
V
VDD = 5 V
VDD = 5 V
VDD = 5 V
VIN = VDD
VIN = 0V
VTH
ILIH
ILIL
V
+10
-10
mA
mA
Input Low Leakage
INc - CMOS level input pin
Input Low Voltage
VIL
VIH
ILIH
ILIL
0.3xVDD
V
V
VDD = 5 V
VDD = 5 V
VIN = VDD
VIN = 0V
Input High Voltage
0.7xVDD
Input High Leakage
+10
-10
mA
mA
Input Low Leakage
INcs - CMOS level schmitt-triggered input pin
Input Low Threshold Voltage
Input High Threshold Voltage
Hysteresis (Vt+ - Vt-)
Vt-
Vt+
1.3
3..2
1.5
1.5
3.5
2
1.7
3.8
V
V
VDD = 5 V
VDD = 5 V
VDD = 5 V
VIN = VDD
VIN = 0V
VTH
ILIH
ILIL
V
Input High Leakage
+10
-10
mA
mA
Input Low Leakage
Publication Release Date: March 1998
Version 0.61
- 130 -
W83877TF
9.3 AC Characteristics
9.3.1 FDC: Data rate = 1 MB/500 KB/300 KB/250 KB/sec.
PARAMETER
SYM.
TEST
MIN.
TYP.
MAX.
UNIT
CONDITIONS
(NOTE 1)
TAR
25
nS
SA9-SA0, AEN, DACK ,
¡ õ
IOR
CS, setup time to
TAR
0
nS
SA9-SA0, AEN, DACK ,
¡ ô
hold time for IOR
IOR width
TRR
TFD
80
nS
nS
CL = 100 pf
Data access time from
¡ õ
80
50
IOR
Data hold from IOR
¡ ô
CL = 100 pf
CL = 100 pf
TDH
TDF
TRI
10
10
nS
nS
nS
¡ õ
SD to from IOR
IRQ delay from IOR
360/570
/675
¡ ô
TAW
TWA
25
0
nS
nS
SA9-SA0, AEN, DACK ,
¡ õ
setup time to IOW
SA9-SA0, AEN, DACK ,
¡ ô
hold time for IOW
TWW
TDW
TWD
60
60
0
nS
nS
nS
IOW width
¡ ô
Data setup time to IOW
Data hold time from
¡ ô
IOW
TWI
360/570
/675
nS
¡ ô
IRQ delay from IOW
DRQ cycle time
TMCY
TAM
TMA
TAA
27
0
mS
50
nS
¡ õ
DRQ delay time DACK
DRQ to DACK delay
DACK width
nS
nS
260/430
/510
TMR
0
0
nS
nS
IOR delay from DRQ
IOW delay from DRQ
TMW
Publication Release Date: March 1998
Version 0.61
- 131 -
W83877TF
9.3 AC Characteristics, FDC continued
PARAMETER
SYM.
TEST
CONDITIONS
MIN.
TYP.
(NOTE 1)
MAX.
UNIT
mS
TMRW
6/12
/20/24
IOW or IOR response time
from DRQ
TC width
TTC
TRST
TIDX
TDST
135/220
/260
nS
RESET width
1.8/3/3.
5
mS
0.5/0.9
/1.0
mS
INDEX width
1.0/1.6
/2.0
mS
DIR setup time to STEP
TSTD
TSTP
24/40/48
mS
mS
DIR hold time from STEP
STEP pulse width
6.8/11.5
/13.8
7/11.7
/14
7.2/11.9
/14.2
TSC
Note 2
Note 2
Note 2
mS
mS
STEP cycle width
WD pulse width
TWDD
100/185
/225
125/210
/250
150/235
/275
Write precompensation
TWPC
100/138
/225
125/210
/250
150/235
/275
mS
Notes:
1. Typical values for T = 25° C and normal supply voltage.
2. Programmable from 2 mS through 32 mS in 2 mS increments.
Publication Release Date: March 1998
Version 0.61
- 132 -
W83877TF
9.3.2 UART/Parallel Port
PARAMETER
SYMBOL
TEST
MIN.
MAX.
UNIT
CONDITIONS
Delay from Stop to Set Interrupt
TSINT
9/16
Baud
Rate
TRINT
TIRS
100 pF Loading
100 pF Loading
1
mS
Delay from IOR Reset Interrupt
Delay from Initial IRQ Reset to
Transmit Start
1/16
9/16
8/16
Baud
Rate
THR
TSI
175
nS
Delay from IOW to Reset interrupt
Delay from Initial IOW to interrupt
16/16
Baud
Rate
Delay from Stop to Set Interrupt
TSTI
1/2
Baud
Rate
TIR
TMWO
TSIM
100 pF Loading
100 pF Loading
250
200
250
nS
nS
nS
Delay from IOR to Reset Interrupt
Delay from IOR to Output
Set Interrupt Delay from Modem
Input
TRIM
TIAD
250
nS
Reset Interrupt Delay from IOR
Interrupt Active Delay
Interrupt Inactive Delay
Baud Divisor
100 pF Loading
100 pF Loading
100 pF Loading
25
30
216-1
nS
nS
TIID
N
9.3.3 Parallel Port Mode Parameters
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
t1
100
nS
PD0-7, INDEX, STROBE, AUTOFD Delay from
IOW
t2
t3
t4
t5
60
nS
nS
nS
nS
IRQ Delay from ACK, nFAULT
105
300
105
IRQ Delay from IOW
IRQ Active Low in ECP and EPP Modes
200
ERROR Active to IRQ Active
Publication Release Date: March 1998
Version 0.61
- 133 -
W83877TF
9.3.4 EPP Data or Address Read Cycle Timing Parameters
PARAMETER SYM.
Ax Valid to IOR Asserted
MIN.
40
0
MAX.
UNIT
nS
t1
t2
t3
t4
t5
nS
IOCHRDY Deasserted to IOR Deasserted
IOR Deasserted to Ax Valid
10
40
0
10
24
nS
IOR Deasserted to
or IOR Asserted
IOW
nS
IOR Asserted to IOCHRDY Asserted
PD Valid to SD Valid
t6
t7
0
0
75
40
nS
mS
nS
nS
IOR Deasserted to SD Hi-Z (Hold Time)
SD Valid to IOCHRDY Deasserted
t8
t9
0
85
60
160
WAIT Deasserted to IOCHRDY Deasserted
PD Hi-Z to PDBIR Set
t10
t13
t14
t15
t16
t17
t18
t19
t20
t21
0
0
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
WRITE Deasserted to IOR Asserted
WAIT Asserted to WRITE Deasserted
Deasserted to WRITE Modified
IOR Asserted to PD Hi-Z
0
185
190
50
60
0
60
0
180
WAIT Asserted to PD Hi-Z
Command Asserted to PD Valid
Command Deasserted to PD Hi-Z
0
60
1
190
WAIT Deasserted to PD Drive
WRITE Deasserted to Command
PBDIR Set to Command
t22
t23
t24
t25
0
0
20
30
nS
nS
nS
nS
PD Hi-Z to Command Asserted
Asserted to Command Asserted
0
195
180
60
WAIT Deasserted to Command Deasserted
Time out
t26
t27
10
0
12
nS
nS
PD Valid to WAIT Deasserted
PD Hi-Z to WAIT Deasserted
t28
0
mS
Publication Release Date: March 1998
Version 0.61
- 134 -
W83877TF
9.3.5 EPP Data or Address Write Cycle Timing Parameters
PARAMETER SYM.
Ax Valid to IOW Asserted
MIN.
40
10
10
0
MAX.
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t1
t2
SD Valid to Asserted
t3
IOW Deasserted to Ax Invalid
t4
WAIT Deasserted to IOCHRDY Deasserted
Command Asserted to WAIT Deasserted
IOW Deasserted to IOW or IOR Asserted
IOCHRDY Deasserted to IOW Deasserted
WAIT Asserted to Command Asserted
IOW Asserted to WAIT Asserted
PBDIR Low to WRITE Asserted
t5
10
40
0
t6
t7
24
160
70
t8
60
0
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
0
60
60
0
185
185
50
WAIT Asserted to WRITE Asserted
WAIT Asserted to WRITE Change
IOW Asserted to PD Valid
0
WAIT Asserted to PD Invalid
PD Invalid to Command Asserted
10
5
35
210
190
10
IOW to Command Asserted
60
60
0
WAIT Asserted to Command Asserted
WAIT Deasserted to Command Deasserted
mS
Command Asserted to WAIT Deasserted
Time out
10
0
12
mS
nS
Command Deasserted to WAIT Asserted
0
nS
IOW Deasserted to WRITE Deasserted and PD
invalid
Publication Release Date: March 1998
Version 0.61
- 135 -
W83877TF
9.3.6 Parallel Port FIFO Timing Parameters
PARAMETER
SYMBOL
MIN.
600
600
450
80
MAX.
UNIT
nS
DATA Valid to nSTROBE Active
nSTROBE Active Pulse Width
DATA Hold from nSTROBE Inactive
BUSY Inactive to PD Inactive
BUSY Inactive to nSTROBE Active
nSTROBE Active to BUSY Active
t1
t2
t3
t4
t5
t6
nS
nS
nS
680
nS
500
nS
9.3.7 ECP Parallel Port Forward Timing Parameters
PARAMETER
SYMBOL
MIN.
0
MAX.
60
UNIT
nS
nAUTOFD Valid to nSTROBE Asserted
PD Valid to nSTROBE Asserted
t1
t2
t3
t4
t5
t6
t7
t8
0
60
nS
BUSY Deasserted to nAUTOFD Changed
BUSY Deasserted to PD Changed
80
80
0
180
180
nS
nS
nSTROBE Deasserted to BUSY Deasserted
BUSY Deasserted to nSTROBE Asserted
nSTROBE Asserted to BUSY Asserted
BUSY Asserted to nSTROBE Deasserted
nS
80
0
200
180
nS
nS
80
nS
9.3.8 ECP Parallel Port Reverse Timing Parameters
PARAMETER
SYMBOL
MIN.
0
MAX.
UNIT
nS
PD Valid to nACK Asserted
t1
t2
t3
t4
t5
t6
nAUTOFD Deasserted to PD Changed
nAUTOFD Asserted to nACK Asserted
nAUTOFD Deasserted to nACK Deasserted
nACK Deasserted to nAUTOFD Asserted
PD Changed to nAUTOFD Deasserted
0
nS
0
nS
0
nS
80
80
200
200
nS
nS
Publication Release Date: March 1998
Version 0.61
- 136 -
W83877TF
10.0 TIMING WAVEFORMS
10.1 FDC
Write Date
Processor Read Operation
WD
SA0-SA9
AEN
TWDD
CS
TAR
TRA
DACK
TRR
IOR
TDH
Index
TFD
TDF
D0-D7
IRQ
INDEX
TR
TIDX
TIDX
Processor Write Operation
Terminal Count
SA0-SA9
AEN
TC
TAW
TWA
DACK
IOW
TTC
TWW
TWD
Reset
TDW
D0-D7
IRQ
RESET
TWI
TRST
DMA Operation
Drive Seek operation
TAM
DRQ
DIR
TMCY
TAA
DACK
TMA
TSTP
TSTD
TDST
TMRW
IOW or
IOR
STEP
TMW (IOW)
TMR (IOR)
TSC
Publication Release Date: March 1998
Version 0.61
- 137 -
W83877TF
10.2 UART/Parallel
Receiver Timing
SIN
(RECEIVER
STAR
INPUT DATA)
DATA BITS
(5-8)
PARITY
STOP
TSINT
IRQ3 or IRQ4
IOR
TRINT
(READ RECEIVER
BUFFER REGISTER)
Transmitter Timing
SERIAL OUT
(SOUT)
STAR
STAR
DATA
(5-8)
PARITY
STOP
(1-2)
THRS
THR
TSTI
IRQ3 or IRQ4
THR
IOW
TSI
(WRITE THR)
TIR
IOR
(READ TIR)
Publication Release Date: March 1998
Version 0.61
- 138 -
W83877TF
10.2.1 Modem Control Timing
MODEM Control Timing
IOW
¢x
¢x
¢x
(WRITE MCR)
¢x
¢x
¢x
¢x
¢x
TMWO
¢
¢
¡ ÷
TMWO
¡ ÷ ¡ ö
¢¡x ö
¢x
¢x
¢x
RTS,DTR
¢x
¢x
¢x
¢
¢x
¢
¢x
¢x
¢x
¢x
¢x
¢x
CTS,DSR
DCD
¢
¢
¢x
¡ ÷
¢
TSIM
TSIM
¢¡x ö
¡ ö
¡ ÷
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
IRQ3 or
IRQ4
¢x
¢x
¢x
¢x
¢x
¢
¢x
¢
¢x
¢
¢
¢
¢
¢x
¡ öTRIM
TRIM
¢x
¡ ö
¡ ÷
¡ ÷
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
IOR
(READ MSR)
¢
TSIM
¡ ÷
¡ ö
¢x
¢x
¢
¢x
¢x
¢x
¢x
¢x
¢x
¢
RI
Printer Interrupt Timing
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢
¢
ACK
¢x
TLAD
TLID
¢x
¡ ÷
¡ ö
¡ ÷
¢x¡ ö
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢
¢
IRQ7
Publication Release Date: March 1998
Version 0.61
- 139 -
W83877TF
10.3 PARALLEL PORT
10.3.1 Parallel Port Timing
IOW
t1
INIT, STROBE
AUTOFD, SLCTIN
PD<0:7>
ACK
t2
IRQ (SPP)
IRQ
t3
t4
(EPP or ECP)
nFAULT
(ECP)
ERROR
(ECP)
t5
t2
t4
IRQ
Publication Release Date: March 1998
Version 0.61
- 140 -
W83877TF
10.3.2 EPP Data or Address Read Cycle (EPP Version 1.9)
t3
A<0:10>
t1
t2
t4
IOR
t6
t7
SD<0:7>
t8
t9
t5
IOCHRDY
t10
t13
t14
t15
WRITE
t16
t18
t19
t20
t17
t21
PD<0:7>
t22
t23
t25
t24
ADDRSTB
DATASTB
t27
t28
t26
WAIT
Publication Release Date: March 1998
Version 0.61
- 141 -
W83877TF
10.3.3 EPP Data or Address Write Cycle (EPP Version 1.9)
t3
t4
A10-A0
SD<0:7>
t5
t1
t2
t6
IOW
IOCHRDY
t
7
t8
t9
t10
t11
t12
t14
WRITE
t13
PD<0:7>
t15
t16
t17
t18
DATAST
ADDRSTB
t19
t21
t20
WAIT
t22
PBDIR
Publication Release Date: March 1998
Version 0.61
- 142 -
W83877TF
10.3.4 EPP Data or Address Read Cycle (EPP Version 1.7)
t3
A<0:10>
t1
t2
t4
IOR
t6
t7
SD<0:7>
t8
t9
t5
IOCHRDY
t10
t13
t14
t15
WRITE
t16
t18
t19
t20
t17
t21
PD<0:7>
t22
t23
t25
ADDRSTB
DATASTB
t24
t26
t28
t27
WAIT
Publication Release Date: March 1998
Version 0.61
- 143 -
W83877TF
10.3.5 EPP Data or Address Write Cycle (EPP Version 1.7)
t3
t4
A10-A0
SD<0:7>
t5
t1
t2
t6
IOW
t7
t8
IOCHRDY
t9
t10
t11
t22
t22
WRITE
t13
PD<0:7>
t15
t16
t17
t18
DATAST
ADDRSTB
t19
t20
WAIT
10.3.6 Parallel Port FIFO Timing
t4
>|
>|
t3
PD<0:7>
t1
t2
t5
>|
>
>|
nSTROBE
t6
>|
BUSY
Publication Release Date: March 1998
Version 0.61
- 144 -
W83877TF
10.3.7 ECP Parallel Port Forward Timing
t3
t4
nAUTOFD
PD<0:7>
t1
t2
t6
t8
nSTROBE
BUSY
t5
t5
t7
10.3.8 ECP Parallel Port Reverse Timing
t2
PD<0:7>
t1
t3
t4
nACK
t5
t5
t6
nAUTOFD
Publication Release Date: March 1998
Version 0.61
- 145 -
W83877TF
11.0 APPLICATION CIRCUITS
11.1 Parallel Port Extension FDD
JP13
13
WE2/SLCT
25
12
JP 13A
WD2/PE
24
11
23
10
DCH2
HEAD2
RDD2
WP2
34
33
31
29
27
25
23
21
19
17
15
13
11
9
MOB2/BUSY
32
30
28
26
24
22
20
18
16
14
12
10
8
DSB2/ACK
22
TRK02
WE2
9
21
8
20
7
19
6
PD7
WD2
PD6
STEP2
DIR2
PD5
MOB2
DCH2/PD4
DSB2
IDX2
18
RDD2/PD3
5
17
4
16
3
15
2
14
1
7
5
3
1
STEP2/SLIN
WP2/PD2
6
4
2
RWC2
DIR2/INIT
TRK02/PD1
EXT FDC
HEAD2/ERR
IDX2/PD0
RWC2/AFD
STB
PRINTER PORT
Parallel Port Extension FDD Mode Connection Diagram
Publication Release Date: March 1998
Version 0.61
- 146 -
W83877TF
11.2 Parallel Port Extension 2FDD
JP13
13
25
12
WE2/SLCT
JP 13A
WD2/PE
DCH2
HEAD2
RDD2
WP2
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
34
33
31
29
27
25
23
21
19
17
15
13
11
9
MOB2/BUSY
32
30
28
26
24
22
20
18
16
14
12
10
8
DSB2/ACK
TRK02
DSA2/PD7
MOA2/PD6
WE2
WD2
STEP2
DIR2
PD5
MOB2
DSA2
DSB2
MOA2
IDX2
DCH2/PD4
RDD2/PD3
7
5
3
1
STEP2/SLIN
WP2/PD2
6
4
2
DIR2/INIT
TRK02/PD1
RWC2
EXT FDC
HEAD2/ERR
IDX2/PD0
RWC2/AFD
STB
PRINTER PORT
Parallel Port Extension 2FDD Connection Diagram
11.3 Four FDD Mode
74LS139
G1
7407(2)
W83777F
1Y0
1Y1
DSA
DSB
DSC
DSD
MOA
DSA
DSB
A1
B1
1Y2
1Y3
2Y0
2Y1
MOA
MOB
MOB
MOC
MOD
G2
2Y2
2Y3
A2
B2
Publication Release Date: March 1998
Version 0.61
- 147 -
W83877TF
12.0 ORDERING INFORMATION
Part No.
W83877TF
W83877TD
Package
100-pin QFP
100-pin LQFP
13.0 HOW TO READ THE TOP MARKING
Example: The top marking of W83977TF-A
inbond
W83877TF
719AB27039520
1st line: Winbond logo
2nd line: the type number: W83877TF
3rd line: tracking code
719 A B 2 7039530
719: packages made in '97, week 19
A: assembly house ID; A means ASE, S means SPIL....etc
C: IC revision; B means version B, C means version C
2: wafers manufactured in Winbond FAB 2
7039530: wafer production series lot number
Publication Release Date: March 1998
Version 0.61
- 148 -
W83877TF
14.0 PACKAGE DIMENSIONS
W83877TF (100-pin QFP)
H D
D
100
81
Dimension in inches Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
1
80
0.130
3.30
A
0.004
0.107 0.112 0.117
0.10
2.73
A 1
A 2
b
c
D
E
2.85
0.30
2.97
0.40
0.010
0.004
0.546
0.25
0.012 0.016
0.006
0.551
0.10
0.15
0.25
0.010
0.556
0.792
0.032
0.752
14.00
20.00
0.65
13.87
19.87
14.13
20.13
0.80
0.782 0.787
0.020 0.026
E
E
H
0.50
e
0.728
0.740
18.80 19.10
18.49
HD
HE
L
0.964
0.039
0.087
0.988 24.49 24.80 25.10
0.976
0.047
0.055
1.40
2.62
0.10
12
1.00
2.21
1.20
2.40
0.094 0.103
0.004
L1
y
30
51
0
12
0
q
Notes:
31
50
b
e
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
c
A2
A1
A
q
See Detail F
L
y
Seating Plane
1
L
Detail F
Publication Release Date: March 1998
Version 0.61
- 149 -
W83877TF
W83877TD (100-pin LQFP)
H
D
D
100
81
Dimension in inches Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
1
80
A
A 1
A 2
b
c
D
0.05
1.35
0.22
0.10
0.10
0.002 0.004 0.006
0.055
0.15
1.45
1.40
0.32
0.053
0.009
0.004
0.057
0.015
0.008
0.555
0.791
0.38
0.013
0.006
0.551
0.787
0.026
0.15
0.20
14.00
0.547
0.783
0.020
0.626
14.10
13.90
19.90
0.498
20.00 20.10
E
H
E
e
E
0.032
0.634
0.65
0.802
16.10
16.00
0.630
15.90
21.90
0.45
HD
HE
L
L1
y
0.866 0.870
22.00 22.10
0.862
0.030
0.60
0.75
0.018 0.024
0.039
1.00
0.08
7
0.003
7
30
51
0
0
q
Notes:
31
50
b
e
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
c
A
2
A
q
A
1
See Detail F
L
y
Seating Plane
L
1
Detail F
Headquarters
No. 4, Creation Rd. III
Science-Based Industrial Park
Hsinchu, Taiwan
TEL: 886-35-770066
FAX: 886-35-789467
Winbond Electronics
(North America) Corp.
2730 Orchard Parkway
San Jose, CA 95134 U.S.A.
TEL: 1-408-9436666
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
TEL: 852-27516023-7
FAX: 852-27552064
FAX: 1-408-9436668
www: http://www.winbond.com.tw/
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without
notice. All the trade marks of products and companies mentioned in this data
sheet belong to their respective owners.
Publication Release Date: March 1998
- 150 -
Version 0.61
W83877TF
8.2 Extended Function Index Registers (EFIRs), Extended Function Data Registers
(EFDRs)
After the extended function mode is entered, the Extended Function Index Register (EFIR) must be
loaded with an index value (0H, 1H, 2H, ..., or 29H) to access Configuration Register 0 (CR0),
Configuration Register 1 (CR1), Configuration Register 2 (CR2), and so forth through the Extended
Function Data Register (EFDR). The EFIRs are write-only registers with port address 251H or 3F0H
(as described in section 8.0) on PC/AT systems; the EFDRs are read/write registers with port address
252H or 3F1H (as described in section 8.0) on PC/AT systems. The function of each configuration
register is described below.
8.2.1 Configuration Register 0 (CR0), default = 00H
When the device is in Extended Function mode and EFIR is 0H, the CR0 register can be accessed
through EFDR. The bit definitions for CR0 are as follows:
7
6
5
4
3
2
1
0
IPD
reserved
PRTMODS0
PRTMODS1
reserved
reserved
reserved
reserved
Bit 7-bit 4: Reserved.
PRTMOD1 PRTMOD0 (Bit 3, 2):
These two bits and PRTMOD2 (CR9 bit 7) determine the parallel port mode of the W83877TF (as
shown in the following Table 8-1).
Table 8-1
PRTMODS2
PRTMODS1
PRTMODS0
(BIT 7 OF CR9)
(BIT 3 OF CR0)
(BIT 2 OF CR0)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Normal
EXTFDC
Reserved
EXT2FDD
Reserved
EPP/SPP
ECP
ECP/EPP
Publication Release Date: March 1998
Version 0.61
- 70 -
W83877TF
00
Normal Mode (Default), PRTMOD2 = 0
Default state after power-on reset. In this mode, the W83877TF is fully compatible
with the SPP and BPP mode.
01
10
11
00
01
10
11
Extension FDD Mode (EXTFDD), PRTMOD2 = 0
Reserved, PRTMOD2 = 0
Extension 2FDD Mode (EXT2FDD), PRTMOD2 = 0
Reserved, PRTMOD2 = 1
EPP Mode and SPP Mode, PRTMOD2 = 1
ECP Mode, PRTMOD2 = 1
ECP Mode and EPP Mode, PRTMOD2 = 1
Bit 1: Reserved.
IPD (Bit 0):
This bit is used to select the W83877TF's legacy power-down functions. When the bit 0 is set to 1, the
W83877TF will stop its clock internally and enter power-down (IPD) mode immediately. The
W83877TF will not leave the power-down mode until either a system power-on reset from the MR pin
or this bit is reset to 0 to program the chip back to power-on state.
8.2.2 Configuration Register 1 (CR1), default = 00H
When the device is in Extended Function mode and EFIR is 01H, the CR1 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
reserved
reserved
reserved
reserved
reserved
reserved
reserved
ABCHG
ABCHG (Bit 7):
This bit enables the FDC AB Change Mode. Default to be enabled at power-on reset.
0
1
Drives A and B assigned as usual
Drive A and drive B assignments exchanged
Bit 6-bit 0: Reserved.
Publication Release Date: March 1998
Version 0.61
- 71 -
W83877TF
8.2.3 Configuration Register 2 (CR2), default = 00H
When the device is in Extended Function mode and EFIR is 02H, the CR2 register can be accessed
through EFDR. This register is reserved.
8.2.4 Configuration Register 3 (CR3), default = 30H
When the device is in Extended Function mode and EFIR is 03H, the CR3 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
SUBMIDI
SUAMIDI
reserved
reserved
reserved
EPPVER
reserved
reserved
Bit 7-bit 6: Reserved.
EPPVER (Bit 5):
This bit selects the EPP version of parallel port:
0
Selects the EPP 1.9 version
Selects the EPP 1.7 version (default)
1
Bit 4: Reserved.
Bit 3-bit 2: Reserved.
SUAMIDI (Bit 1):
This bit selects the clock divide rate of UARTA.
0
1
Disables MIDI support, UARTA clock = 24 MHz divided by 13 (default)
Enables MIDI support, UARTA clock = 24 MHz divided by 12
SUBMIDI (Bit 0):
This bit selects the clock divide rate of UARTB.
0
1
Disables MIDI support, UARTB clock = 24 MHz divided by 13 (default)
Enables MIDI support, UARTB clock = 24 MHz divided by 12
Publication Release Date: March 1998
Version 0.61
- 72 -
W83877TF
8.2.5 Configuration Register 4 (CR4), default = 00H
When the device is in Extended Function mode and EFIR is 04H, the CR4 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
URBTRI
URATRI
reserved
PRTTRI
URBPWD
URAPWD
reserved
PRTPWD
PRTPWD (Bit 7):
0
1
Supplies power to the parallel port (default)
Puts the parallel port in power-down mode
Bit 6: Reserved.
URAPWD (Bit 5):
0
1
Supplies power to COMA (default)
Puts COMA in power-down mode
URBPWD (Bit 4):
0
1
Supplies power to COMB (default)
Puts COMB in power-down mode
PRTTRI (Bit 3):
This bit enables or disables the tri-state outputs of parallel port in power-down mode.
0
The output pins of the parallel port will not be tri-stated when parallel port is in power-
down mode. (default)
1
The output pins of the parallel port will be tri-stated when parallel port is in power-
down mode.
Bit 2: Reserved.
URATRI (Bit 1):
This bit enables or disables the tri-state outputs of UARTA in power-down mode.
0
The output pins of UARTA will not be tri-stated when UARTA is in power-down mode.
The output pins of UARTA will be tri-stated when UARTA is in power-down mode.
1
URBTRI (Bit 0):
This bit enables or disables the tri-state outputs of UARTB in power-down mode.
0
1
The output pins of UARTB will not be tri-stated when UARTB is in power-down mode.
The output pins of UARTB will be tri-stated when UARTB is in power-down mode.
Publication Release Date: March 1998
- 73 -
Version 0.61
W83877TF
8.2.6 Configuration Register 5 (CR5), default = 00H
When the device is in Extended Function mode and EFIR is 05H, the CR5 register can be accessed
through EFDR. The bit definitions are as follows:
0
7
6
5
4
3
2
1
ECPFTHR0
ECPFTHR1
ECPFTHR2
ECPFTHR3
reserved
reserved
reserved
reserved
Bit 7- bit 4: Reserved
ECPFTHR3-0 (bit 3-0): These four bits define the FIFO threshold for the ECP mode parallel port. The
default value is 0000 after power-up.
8.2.7 Configuration Register 6 (CR6), default = 00H
When the device is in Extended Function mode and EFIR is 06H, the CR6 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
reserved
FDCTRI
reserved
FDCPWD
FIPURDWM
SEL4FDD
reserved
reserved
Bit 7- bit 6: Reserved
SEL4FDD (Bit 5): Selects four FDD mode
0
1
Selects two FDD mode (default, see Table 8-2)
Selects four FDD mode
DSA, DSB, MOA and MOB output pins are encoded as show in Table 8-3 to select
four drives.
Publication Release Date: March 1998
- 74 -
Version 0.61
W83877TF
Table 8-2
DO REGISTER ( 3F2H )
Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0
DRIVE
MOB
MOA
DSB
DSA
SELECTED
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
0
1
1
1
0
1
1
1
1
1
0
1
1
1
0
1
1
1
--
FDD A
FDD B
--
--
Table 8-3
DO REGISTER ( 3F2H )
Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0
DRIVE
SELECTED
--
MOB
MOA
DSB
DSA
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
X
0
0
1
1
X
0
1
0
1
1
0
0
0
0
1
0
0
0
0
x
0
0
1
1
x
0
1
0
1
FDD A
FDD B
FDD C
FDD D
FIPURDWN (Bit 4):
This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0,
DSKCHG, and WP.
0
1
The internal pull-up resistors of FDC are turned on. (default)
The internal pull-up resistors of FDC are turned off.
FDCPWD (Bit 3):
This bit controls the power to the FDC.
0
Power is supplied to the FDC. (default)
Puts the FDC in power-down mode.
1
Bit 2: Reserved.
FDCTRI (Bit 1):
This bit enables or disables the tri-state outputs of the FDC in power-down mode.
0
The output pins of the FDC will not be tri-stated when FDC is in power-down mode.
The output pins of the FDC will be tri-stated when FDC is in power-down mode.
1
Bit 0: Reserved.
Publication Release Date: March 1998
- 75 -
Version 0.61
W83877TF
8.2.8 Configuration Register 7 (CR7), default = 00H
When the device is in Extended Function mode and EFIR is 07H, the CR7 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
FDD A type 0
FDD A type 1
FDD B type 0
FDD B type 1
FDD C type 0
FDD C type 1
FDD D type 0
FDD D type 1
FDD D type 1, 0 (Bit 7, 6):
These two bits select the type of FDD D.
00
Selects normal mode. When RWC = 0, the data transfer rate is 250 Kb/s. When
RWC = 1, the data transfer rate is 500 Kb/s.
Three mode FDD select (EN3MODE = 1):
01
10
11
RWC = 0, selects 1.2 MB high-density FDD.
RWC = 1, selects 1.44 MB high-density FDD.
Don't care RWC, selects 720 KB double-density FDD.
FDD C type 1, 0 (Bit 5, 4):
These two bits select the type of FDD C.
00
Selects normal mode. When RWC = 0, the data transfer rate is 250 kb/s. When
RWC = 1, he data transfer rate is 500 kb/s.
Three mode FDD select (EN3MODE = 1):
01
10
11
RWC = 0, selects 1.2 MB high-density FDD.
RWC = 1, selects 1.44 MB high-density FDD.
Don't care RWC, selects 720 KB double-density FDD.
FDD B type 1, 0 (Bit 3, 2):
These two bits select the type of FDD B.
00
Selects normal mode. When RWC = 0, the data transfer rate is 250 Kb/s. When
RWC = 1, the data transfer rate is 500 Kb/s.
Three mode FDD select (EN3MODE = 1):
01
10
11
RWC = 0, selects 1.2 MB high-density FDD.
RWC = 1, selects 1.44 MB high-density FDD.
Don't care RWC, selects 720 KB double-density FDD.
Publication Release Date: March 1998
Version 0.61
- 76 -
W83877TF
FDD A type 1, 0 (Bit 1, 0):
These two bits select the type of FDD A.
00
Selects normal mode. When RWC = 0, the data transfer rate is 250 Kb/s. When
RWC = 1, the data transfer rate is 500 Kb/s.
Three mode FDD select (EN3MODE = 1):
01
10
11
RWC = 0, selects 1.2 MB high-density FDD.
RWC = 1, selects 1.44 MB high-density FDD.
Don't care RWC, selects 720 KB double-density FDD.
8.2.9 Configuration Register 8 (CR8), default = 00H
When the device is in Extended Function mode and EFIR is 08H, the CR8 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
Floppy Boot Drive 0
Floppy Boot Drive 1
Media ID 0
Media ID 1
SWWP
DISFDDWR
reserved
reserved
Bit 7 - bit 6: Reserved.
DISFDDWR (Bit 5):
This bit enables or disables FDD write data.
0
1
Enables FDD write
Disables FDD write (forces pins WE, WD to stay high)
Once this bit is set high, the FDC operates normally, but because pin WE is inactive, the FDD will not
write data to diskettes. For example, if a diskette is formatted with DISFDDWR = 1, after the format
command has been executed, messages will be displayed that appear to indicate that the format is
complete. If the diskette is removed from the disk drive and inserted again, however, typing the DIR
command will reveal that the contents of the diskette have not been modified and the diskette was
not actually reformatted.
Publication Release Date: March 1998
- 77 -
Version 0.61
W83877TF
Because as the operating system (e.g., DOS) reads the diskette files, it keeps the files in memory, if
there is a write operation, DOS will write data to the diskette and memory simultaneously. When DOS
wants to read the diskette, it will first search for the files in memory. If DOS finds the file in memory, it
will not issue a read command to read the diskette. When DISFDDWR = 1, DOS still writes data to
the diskette and memory, but only the data in memory are updated. If a read operation is performed,
data are read from memory first, and not from the diskette. The action of removing the diskette from
the drive and inserting it again forces the DSKCHG pin active. DOS will then read the contents of the
diskette and will show that the contents have not been modified. The same holds true with write
commands.
This disable FDD write function allows users to protect diskettes against computer viruses by ensuring
that no data are written to the diskette.
SWWP (Bit 4):
0
1
Normal, use
to determine whether the FDD is write-protected or not
WP
FDD is always write-protected
Media ID 1 Media ID 0 (Bit 3, 2):
These two bits hold the media ID bit 1, 0 for three mode
Floppy Boot Drive 1 Floppy Boot Drive 0 (Bit 1, 0)
These two bits hold the value of floppy boot drive 1 and drive 0 for three mode
8.2.10 Configuration Register 9 (CR9), default = 0CH
When the device is in Extended Function mode and EFIR is 09H, the CR9 register can be accessed
through EFDR. The bit definitions are as follows:
7
6
5
4
3
2
1
0
CHIP ID0
CHIP ID1
CHIP ID2
CHIP ID3
reserved
EN3MODE
LOCKREG
PRTMODS2
PRTMODS2 (Bit 7):
This bit and PRTMODS1, PRTMODS0 (bits 3, 2 of CR0) select the operating mode of the
W83877TF. Refer to the descriptions of CR0.
LOCKREG (Bit 6):
This bit enables or disables the reading and writing of all configuration registers.
0
1
Enables the reading and writing of CR0-CR45
Disables the reading and writing of CR0-CR45 (locks W83877TF extension functions)
Publication Release Date: March 1998
- 78 -
Version 0.61
W83877TF
EN3MODE (Bit 5):
This bit enables or disables three mode FDD selection. When this bit is high, it enables the read/write
3F3H register.
0
1
Disables 3 mode FDD selection
Enables 3 mode FDD selection
When three mode FDD function is enabled, the value of RWC depends on bit 5 and bit 4 of
TDR(3F3H). The values of RWC and their meaning are shown in Table 8-4.
Table 8-4
BIT 5 OF TDR
BIT 4 OF TDR
RWC
RWC = 0
250K bps
1.2 M FDD
X
RWC = 1
500K bps
X
0
0
1
1
0
1
0
1
Normal
0
1
X
1.4M FDD
X
X
Bit 4: Reserved.
CHIP ID 3, CHIP ID 2, CHIP ID 1, CHIP ID 0 (Bit 3-bit 0):
These four bits are read-only bits that contain chip identification information. The value is 0CH for
W83877TF during a read.
8.2.11 Configuration Register A (CR0A), default = 00H
When the device is in Extended Function mode and EFIR is 0AH, the CRA register can be accessed
through EFDR. This register is reserved.
8.2.12 Configuration Register B (CR0B), default = 0CH
When the device is in Extended Function mode and EFIR is 0BH, the CRB register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
DRV2EN
INVERTZ
MFM
IDENT
ENIFCHG
RXW4C
TXW4C
reserved
Publication Release Date: March 1998
Version 0.61
- 79 -
W83877TF
Bit 7: Reserved.
TXW4C (Bit 6):
This bit is active high. When active, the IR controller will wait for a 4-character period of time after the
end of last receiving before it can start transmitting data.
RXW4C (Bit 5):
This bit is active high. When active, the IR controller will wait for a 4-character period of time after the
end of last transmitting before it can start receiving data.
ENIFCHG (Bit 4):
This bit is active high. When active, it enables host interface mode change, which is determined by
IDENT (Bit 3) and MFM (Bit 2).
IDENT (Bit 3):
This bit indicates the type of drive being accessed and changes the level on RWC (pin 87).
0
1
RWC will be active low for high data rates (typically used for 3.5" drives)
RWC will be active high for high data rates (typically used for 5.25" drives)
When hardware reset or ENIFCHG is a logic 1, IDENT and MFM select one of three interface modes,
as shown in Table 8-5.
Table 8-5
IDENT
MFM
INTERFACE
Model 30 mode
0
0
1
1
0
1
0
1
PS/2 mode
AT mode
AT mode
MFM (Bit 2):
This bit and IDENT select one of the three interface modes (PS/2 mode, Model 30, or PC/AT mode).
INTVERTZ (Bit 1):
This bit determines the polarity of all FDD interface signals.
0
1
FDD interface signals are active low
FDD interface signals are active high
DRV2EN (Bit 0): PS/2 mode only
When this bit is a logic 0, this indicates that a second drive is installed and is reflected in status
register A.
Publication Release Date: March 1998
- 80 -
Version 0.61
W83877TF
8.2.13 Configuration Register C (CR0C), default = 28H
When the device is in Extended Function mode and EFIR is 0CH, the CR0C register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
TX2INV
RX2INV
reserved
URIRSEL
reserved
HEFERE
TURB
TURA
TURA (Bit 7):
0
1
the clock source of UART A is 1.8462 MHZ (24 MHz divide 13) (default)
the clock source of UART A is 24 MHz, it can make the baudrate of UART A up to 1.5
MHz
TURB (Bit 6):
0
1
the clock source of UART B is 1.8462 MHz (24 MHz divide 13) (default)
the clock source of UART B is 24 MHz, it can make the baudrate of UART A up to 1.5
MHz
HEFERE (Bit 5): this bit combines with HEFRAS (CR16 bit 0) to define how to enable Extended
Function Registers.
HEFRAS
HEFERE
address and value
0
0
1
1
0
1
0
1
write 88H to the location 250H
write 89H to the location 250H (default)
write 86H to the location 3F0H twice
write 87H to the location 3F0H twice
The default value of HEFERE is 1.
Bit 4: Reserved.
URIRSEL (Bit 3):
0
1
select UART B as IR function.
select UART B as normal function.
The default value of URIRSEL is 1.
Bit 2: Reserved.
RX2INV (Bit 1):
0
the SINB pin of UART B function or IRRX pin of IR function in normal condition.
inverse the SINB pin of UART B function or IRRX pin of IR function
1
TX2INV (Bit 0):
0
1
the SOUTB pin of UART B function or IRTX pin of IR function in normal condition.
inverse the SOUTB pin of UART B function or IRTX pin of IR function.
Publication Release Date: March 1998
- 81 -
Version 0.61
W83877TF
8.2.14 Configuration Register D (CR0D), default = A3H
When the device is in Extended Function mode and EFIR is 0DH, the CR0D register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
IRMODE0
IRMODE1
IRMODE2
HDUPLX
SIRRX0
SIRRX1
SIRTX0
SIRTX1
SIRTX1 (Bit 7): IRTX pin selection bit 1
SIRTX0 (Bit 6): IRTX pin selection bit 0
SIRTX1
SIRTX0
IRTX output on pin
disabled
0
0
1
1
0
1
0
1
IRTX1 (pin 43)
IRTX2 (pin 95)
disabled
SIRRX1 (Bit 5): IRRX pin selection bit 1
SIRRX0 (Bit 4): IRRX pin selection bit 0
SIRRX1
SIRRX0
IRRX input on pin
disabled
0
0
1
1
0
1
0
1
IRRX1 (pin 42)
IRRX2 (pin 94)
disabled
HDUPLX (Bit 3):
0
1
The IR function is Full Duplex.
The IR function is Half Duplex.
IRMODE2 (Bit 2): IR function mode selection bit 2
IRMODE1 (Bit 1): IR function mode selection bit 1
IRMODE0 (Bit 0): IR function mode selection bit 0
Publication Release Date: March 1998
Version 0.61
- 82 -
W83877TF
IR MODE IR FUNCTION
IRTX
IRRX
00X
010*
011*
100
Disable
IrDA
tri-state
high
Demodulation into SINB
Demodulation into SINB
routed to SINB
Active pulse 1.6 mS
IrDA
Active pulse 3/16 bit time
Inverting IRTX pin
ASK-IR
ASK-IR
ASK-IR
ASK-IR
101
Inverting IRTX & 500 KHZ clock
Inverting IRTX
routed to SINB
110
Demodulation into SINB
Demodulation into SINB
111*
Inverting IRTX & 500 KHZ clock
Note: The notation is normal mode in the IR function.
The SIR schematic diagram for registers CRC and CRD is shown below.
HUPLX
(CRD.bit3)
Transmission
Time Frame
IRRX1
IRRX2
SIN2
16550A
Demodulation
IR-DA
1
1
Demodulation
01
00
10
11
SIN
0
1
MUX
ASK_IR
+5V
0
MUX
NCS0 (default)
+5V
MUX 0
IRMODE2,1=00
RX2INV
(CRC.bit1)
MUX
URIRSEL
(CRC.bit3)
UART2
SOUT
IRMODE2
(CRD.bit2)
IRMODE1
(CRD.bit1)
IRDA Mod.
3/16
SIRRX1~0
CR0D.bit5,4
1
IRDA
0
IRDA Mod.
Mod1.6u
disable
0 MUX
11,00
01
0
1 MUX
IRTX1
IRTX2
SOUT2
(default)
IRMODE0
(CRD.bit0)
1 MUX
NCS1
10
MUX
IRMODE2
(CRD.bit2)
TX2INV
CRC.bit0
1
URIRSEL
(CRC,bit3)
SIRTX1~0
CRD.bit7,6
500KHZ
0 MUX
IRMODE0
(CRD.bit0)
8.2.15 Configuration Register E (CR0E), Configuration Register F (CR0F)
Reserved for testing. Should be kept all 0's.
Publication Release Date: March 1998
Version 0.61
- 83 -
W83877TF
8.2.16 Configuration Register 10 (CR10), default = 00H
When the device is in Extended Function mode and EFIR is 10H, the CR10 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
GIO0AD0
GIO0AD1
GIO0AD2
GIO0AD3
GIO0AD4
GIO0AD5
GIO0AD6
GIO0AD7
GIO0AD7-GIO0AD0 (Bit 7-bit 0): GIOP0 (pin 92) address bit 7 - bit 0.
8.2.17 Configuration Register 11 (CR11), default = 00H
When the device is in Extended Function mode and EFIR is 11H, the CR11 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
GIO0AD8
GIO0AD9
GIO0AD10
reserved
reserved
reserved
G0CADM0
G0CADM1
G0CADM1-G0CADM0 (Bit 7, 6): GIOP0 address bit compare mode selection
G0CADM1
G0CADM0
GIOP0 pin
0
0
1
1
0
1
0
1
compare GIO0AD10-GIO0AD0 with SA10-SA0
compare GIO0AD10-GIO0AD1 with SA10-SA1
compare GIO0AD10-GIO0AD2 with SA10-SA2
compare GIO0AD10-GIO0AD3 with SA10-SA3
Bit 5-bit 3: Reserved
GIO0AD10-GIO0AD8 (Bit 2-bit 0): GIOP0 (pin 92) address bit 10-bit 8.
Publication Release Date: March 1998
Version 0.61
- 84 -
W83877TF
8.2.18 Configuration Register 12 (CR12), default = 00H
When the device is in Extended Function mode and EFIR is 12H, the CR12 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
GIO1AD0
GIO1AD1
GIO1AD2
GIO1AD3
GIO1AD4
GIO1AD5
GIO1AD6
GIO1AD7
GIO1AD7-GIO1AD0 (Bit 7-bit 0): GIOP1 (pin 96) address bit 7-bit 0.
8.2.19 Configuration Register 13 (CR13), default = 00H
When the device is in Extended Function mode and EFIR is 13H, the CR13 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
GIO1AD8
GIO1AD9
GIO1AD10
reserved
reserved
reserved
G1CADM0
G1CADM1
G1CADM1-G1CADM0 (bit 7, 6): GIOP1 address bit compare mode selection
G1CADM1
G1CADM0
GIOP1 pin
0
0
1
1
0
1
0
1
compare GIO1AD10-GIO1AD0 with SA10-SA0
compare GIO1AD10-GIO1AD1 with SA10-SA1
compare GIO1AD10-GIO1AD2 with SA10-SA2
compare GIO1AD10-GIO1AD3 with SA10-SA3
Bit 5- bit 3: Reserved
GIO1AD10-GIO1AD8 (Bit 2-bit 0): GIOP1 (pin 96) address bit 10-bit 8.
Publication Release Date: March 1998
Version 0.61
- 85 -
W83877TF
8.2.20 Configuration Register 14 (CR14), default = 00H
When the device is in Extended Function mode and EFIR is 14H, the CR14 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
GDA0IPI
GDA0OPI
GCS0IOW
GCS0IOR
GIO0CSH
GIOP0MD0
GIOP0MD1
GIOP0MD2
GIOP0MD2-GIOP0MD0 (Bit 7-bit 5): GIOP0 pin mode selection
GIOP0MD2 GIOP0MD1 GIOP0MD0
GIOP0 pin
0
0
0
0
0
1
inactive (tri-state)
as a data output pin (SD0® GIOP0), when (AEN = L)
AND (NIOW = L) AND (SA10-0 = GIO0AD10-0), the
value of SD0 will be present on GIOP0
0
0
1
1
0
1
as a data input pin (GIOP0® SD0), when (AEN = L)
AND (NIOR = L) AND (SA10-0 = GIO0AD10-0), the
value of GIOP0 will be present on SD0
as a data input/output pin (GIOP0« SD0).
When (AEN = L) AND (NIOW = L) AND (SA10-0 =
GIO0AD10-0), the value of SD0 will be present on
GIOP0 When (AEN = L) AND (NIOR = L) AND (SA10-
0 = GIO0AD10-0), the value of GIOP0 will be present
on SD0
1
X
X
as a Chip Select pin, the pin will be active at (AEN =
L) AND (SA10-0 = GIO0AD10-0) OR (NIOR = L) OR
(NIOW = L)
GIO0CSH(Bit 4):
0
the Chip Select pin will be active LOW when (AEN = L) AND (SA10-0 = GIO0AD10-
0) OR (NIOR = L) OR (NIOW = L)
1
the Chip Select pin will be active HIGH when (AEN = L) AND (SA10-0 = GIO0AD10-
0) OR (NIOR = L) OR (NIOW = L)
GCS0IOR (Bit 3): See below.
Publication Release Date: March 1998
Version 0.61
- 86 -
W83877TF
GCS0IOW (Bit 2): See below.
GCS0IOR
GCS0IOW
0
0
GIOP0 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO0AD10-0)
0
1
1
1
0
1
GIOP0 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO0AD10-0) AND (NIOW = L)
GIOP0 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO0AD10-0) AND (NIOR = L)
GIOP0 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO0AD10-0) AND (NIOW = L OR
NIOR = L)
GDA0OPI (Bit 1): See below.
GDA0IPI (Bit 0): See below.
GDA0OPI
GDA0IPI
0
0
0
1
GIOP0 functions as a data pin, and GIOP0® SD0, SD0® GIOP0
GIOP0 functions as a data pin, and inverse GIOP0® SD0, SD0®
GIOP0
1
1
0
1
GIOP0 functions as a data pin, and GIOP0® SD0, inverse SD0®
GIOP0
GIOP0 functions as a data pin, and inverse GIOP0® SD0, inverse SD0
® GIOP0
8.2.21 Configuration Register 15 (CR15), default = 00H
When the device is in Extended Function mode and EFIR is 15H, the CR15 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
GDA0IPI
GDA0OPI
GCS0IOW
GCS0IOR
GIO0CSH
GIOP0MD0
GIOP0MD1
GIOP0MD2
Publication Release Date: March 1998
Version 0.61
- 87 -
W83877TF
GIOP1MD2-GIOP1MD0 (Bit 7-bit 5): GIOP1 pin mode selection
GIOP1MD2 GIOP1MD1 GIOP1MD0
GIOP1 pin
0
0
0
0
0
1
inactive (tri-state)
as a data output pin (SD1® GIOP1), when (AEN = L)
AND (NIOW = L) AND (SA10-0 = GIO1AD10-0), the
value of SD1 will be present on GIOP1
0
0
1
1
0
1
as a data input pin (GIOP1® SD1), when (AEN = L)
AND (NIOR = L) AND (SA10-0 = GIO1AD10-0), the
value of GIOP1 will be present on SD1
as a data input/output pin (GIOP1« SD1).
When (AEN = L) AND (NIOW = L) AND (SA10-0 =
GIO1AD10-0), the value of SD1 will be present on
GIOP1 When (AEN = L) AND (NIOR = L) AND (SA10-
0 = GIO1AD10-0), the value of GIOP1 will be present
on SD1
1
X
X
as a Chip Select pin, the pin will be active at (AEN =
L) AND (SA10-0 = GIO1AD10-0) OR (NIOR = L) OR
(NIOW = L)
GIO1CSH (Bit 4):
0
1
the Chip Select pin will active LOW when (AEN = L) AND (SA10-0 = GIOAD10-0)
OR (NIOR = L) OR (NIOW = L)
the Chip Select pin will active HIGH when (AEN = L) AND (SA10-0 = GIOAD10-0)
OR (NIOR = L) OR (NIOW = L)
GCS1IOR (Bit 3): See below.
GCS1IOW (Bit 2): See below.
GCS1IOR
GCS1IOW
0
0
GIOP1 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO1AD10-0)
0
1
1
1
0
1
GIOP1 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO1AD10-0) AND (NIOW = L)
GIOP1 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO1AD10-0) AND (NIOR = L)
GIOP1 functions as a Chip Select pin, and will be active when
(AEN = L) AND (SA10-0 = GIO1AD10-0) AND (NIOW = L OR
NIOR = L)
GDA0OPI (Bit 1): See below.
Publication Release Date: March 1998
Version 0.61
- 88 -
W83877TF
GDA1IPI (Bit 0): See below.
GDA1OPI
GDA1IPI
0
0
0
1
GIOP1 functions as a data pin, and GIOP1® SD1, SD1® GIOP1
GIOP1 functions as a data pin, and inverse GIOP1® SD1, SD1®
GIOP1
1
1
0
1
GIOP1 functions as a data pin, and GIOP1® SD1, inverse SD1®
GIOP1
GIOP1 functions as a data pin, and inverse GIOP1® SD1, inverse
SD1® GIOP1
8.2.22 Configuration Register 16 (CR16), default = 04H
When the device is in Extended Function mode and EFIR is 16H, the CR16 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
HEFRAS
reserved
PNPCVS
reserved
G0IQSEL
G1IQSEL
reserved
reserved
Bit 7-bit 6: Reserved.
G1IQSEL (Bit 5):
0
1
pin 96 function as IRQ_A.
pin 96 function as GIO1.
The corresponding power-on setting pin is NRTSB (pin 45).
G0IQSEL (Bit 4):
0
1
pins 92 function as IRQ_B.
pins 92 function as GIO0.
The corresponding power-on setting pin is NRTSB (pin 45).
Bit 3: Reserved.
PNPCVS (bit 2):
0
1
PnP-related registers (CR20, CR23-29) reset to be all 0s.
default settings for these registers.
Publication Release Date: March 1998
Version 0.61
- 89 -
W83877TF
The corresponding power-on setting pin is NRTSA (pin 36).
PnP register
CR20
PNPCVS = 1
FCH
PNPCVS = 0
00H
CR23
DEH
00H
CR24
FEH
00H
CR25
BEH
00H
CR26
23H
00H
CR27
05H
00H
CR28
43H
00H
CR29
60H
00H
Note: The new value of PNPCVS must be complementary to the old one to make an effective change. For example, the user must
set PNPCVS to 1 first and then reset it to 0 to reset these PnP registers if the present value of PNPCVS is 0.
Bit 1: Reserved.
HEFRAS (Bit 0): combines with HEFERE (bit 5 of CR0C) to define how to access Extended Function
Registers (refer to bit 5 of CR0C description). The corresponding power-on setting
pin is NDTRA (pin 35).
8.2.23 Configuration Register 17 (CR17), default = 00H
When the device is in Extended Function mode and EFIR is 17H, the CR17 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
DSUBLGRQ
DSUALGRQ
DSPRLGRQ
DSFDLGRQ
PRIRQOD
reserved
reserved
reserved
Bit 7-bit 5: Reserved.
Publication Release Date: March 1998
Version 0.61
- 90 -
W83877TF
PRIRQOD (Bit 4):
0
1
printer IRQ ports are totem-poles in SPP mode and open-drains in ECP/EPP mode.
printer IRQ ports are totem-poles in all modes.
DSFDLGRQ (Bit 3):
0
1
enable FDC legacy mode on IRQ and DRQ selections. DO register bit 3 has effect on
selecting IRQ.
disable FDC legacy mode on IRQ and DRQ selections. DO register bit 3 has no effect
on selecting IRQ.
DSPRLGRQ (Bit 2):
0
1
enable PRT legacy mode on IRQ and DRQ selections. DCR bit 4 has effect on
selecting IRQ.
disable PRT legacy mode on IRQ and DRQ selections. DCR bit 4 has no effect on
selecting IRQ.
DSUALGRQ (Bit 1):
0
1
enable UART A legacy mode on IRQ selection. MCR bit 3 has effect on selecting IRQ.
disable UART A legacy mode on IRQ selection. MCR bit 3 has no effect on selecting
IRQ.
DSUBLGRQ (Bit 0):
0
1
enable UART B legacy mode on IRQ selection. MCR bit 3 has effect on selecting IRQ.
disable UART B legacy mode on IRQ selection. MCR bit 3 has no effect on selecting
IRQ.
8.2.24 Configuration Register 18 (CR18), default=00H
When the device is in Extended Function mode and EFIR is 18H, the CR18 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
SHARA
SHARB
SHARC
SHARD
SHARE
SHARF
SHARG
SHARH
Publication Release Date: March 1998
Version 0.61
- 91 -
W83877TF
This register is used to select whether these interrupt request pins are in the IRQ sharing mode. While
in the IRQ sharing mode, the corresponding pin is low active for 200ns for the interrupt request and
keeps tri-stated otherwise.
SHARH (Bit 7):
0
1
pin IRQ_H in the legacy ISA IRQ mode.
pin IRQ_H in the IRQ sharing mode.
SHARG (Bit 6):
0
1
pin IRQ_G in the legacy ISA IRQ mode.
pin IRQ_G in the IRQ sharing mode.
SHARF (Bit 5):
0
1
pin IRQ_F in the legacy ISA IRQ mode.
pin IRQ_F in the IRQ sharing mode.
SHARE (Bit 4):
0
1
pin IRQ_E in the legacy ISA interrupt mode.
pin IRQ_E in the IRQ sharing mode.
SHARD (Bit 3):
0
1
pin IRQ_D in the legacy ISA IRQ mode.
pin IRQ_D in the IRQ sharing mode.
SHARC (Bit 2):
0
1
pin IRQ_C in the legacy ISA IRQ mode.
pin IRQ_C in the IRQ sharing mode.
SHARB(Bit 1):
0
1
pin IRQ_B in the legacy ISA IRQ mode.
pin IRQ_B in the IRQ sharing mode.
SHARA (Bit 0):
0
1
pin IRQ_A in the legacy ISA IRQ mode.
pin IRQ_A in the IRQ sharing mode.
Publication Release Date: March 1998
Version 0.61
- 92 -
W83877TF
8.2.25 Configuration Register 19 (CR19), default=00H
When the device is in Extended Function mode and EFIR is 19H, the CR19 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
FASTB
FASTA
reserved
reserved
reserved
reserved
reserved
reserved
This register is used for the high speed modem application. While the bit is set to logic 1 it can make
the baudrate of UART up to 921.2KBPS (the clock source of UART is 14.769MHz) for high speed
transmit/receive.
Bit 7 - bit 2: Reserved.
FASTA (Bit 1):
0
1
the clock source of UART A is the same as the frequency of TURA (CR0C bit 7)
and SUAMIDI (CR3 bit 1) selected.
the clock source of UART A is 14.769MHZ.
FASTB (Bit 0):
0
the clock source of UART B is the same as the frequency of TURB (CR0C bit 6)
and SUBMIDI (CR3 bit 0) selected.
1
the clock source of UART B is 14.769MHZ.
8.2.26 Configuration Register 20 (CR20)
When the device is in Extended Function mode and EFIR is 20H, the CR20 register can be accessed
through EFDR. Default = FCH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions
are as follows:
2
1
7
6
5
4
3
0
reserved
reserved
FDCAD2
FDCAD3
FDCAD4
FDCAD5
FDCAD6
FDCAD7
Publication Release Date: March 1998
Version 0.61
- 93 -
W83877TF
This register is used to select the base address of the Floppy Disk Controller (FDC) from 100H-3F0H
on 16-byte boundaries. NCS = 0 and A10 = 0 are required to access the FDC registers. A[3:0] are
always decoded as 0xxxb.
FDCAD7-FDCAD2 (Bit 7-bit 2): match A[9:4]. Bit 7 = 0 and bit 6 = 0 disable this decode.
Bit 1-bit 0: Reserved, fixed at zero.
8.2.27 Configuration Register 23 (CR23)
When the device is in Extended Function mode and EFIR is 23H, the CR23 register can be accessed
through EFDR. Default = DEH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions
are as follows:
2
1
7
6
5
4
3
0
PRTAD0
PRTAD1
PRTAD2
PRTAD3
PRTAD4
PRTAD5
PRTAD6
PRTAD7
This register is used to select the base address of the parallel port. If EPP is disable, the parallel port
can be set from 100H-3FCH on 4-byte boundaries. If EPP is enable, the parallel port can be set from
100H-3F8H on 8-byte boundaries. NCS = 0 and A10 = 0 are required to access the parallel port when
in compatible, bi-directional, or EPP modes. A10 is active in ECP mode.
PRTAD7-PRTAD0 (Bit 7-bit 0): match A[9:2]. Bit 7 = 0 and bit 6 = 0 disable this decode.
8.2.28 Configuration Register 24 (CR24)
When the device is in Extended Function mode and EFIR is 24H, the CR24 register can be accessed
through EFDR. Default = FEH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions
are as follows:
2
1
7
6
5
4
3
0
reserved
URAAD1
URAAD2
URAAD3
URAAD4
URAAD5
URAAD6
URAAD7
This register is used to select the base address of the UART A from 100H-3F8H on 8-byte
boundaries. NCS = 0 and A10 = 0 are required to access the UART A registers. A[2:0] are don't-care
conditions.
Publication Release Date: March 1998
- 94 -
Version 0.61
W83877TF
URAAD7-URAAD1 (Bit 7-bit 1): match A[9:3]. Bit 7 = 0 and bit 6 = 0 disable this decode.
Bit 0: Reserved, fixed at zero.
8.2.29 Configuration Register 25 (CR25)
When the device is in Extended Function mode and EFIR is 25H, the CR25 register can be accessed
through EFDR. Default = BEH if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions
are as follows:
2
1
7
6
5
4
3
0
reserved
URBAD1
URBAD2
URBAD3
URBAD4
URBAD5
URBAD6
URBAD7
This register is used to select the base address of the UART B from 100H-3F8H on 8-byte
boundaries. NCS = 0 and A10 = 0 are required to access the UART B registers. A[2:0] are don't-care
conditions.
URBAD7-URBAD1 (Bit 7-bit 1): match A[9:3]. Bit 7 = 0 and bit 6 = 0 disable this decode.
Bit 0: Reserved, fixed at zero.
8.2.30 Configuration Register 26 (CR26)
When the device is in Extended Function mode and EFIR is 26H, the CR26 register can be accessed
through EFDR. Default = 23H if CR16 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
2
1
7
6
5
4
3
0
PRTDQS0
PRTDQS1
PRTDQS2
PRTDQS3
FDCDQS0
FDCDQS1
FDCDQS2
FDCDQS3
FDCDQS3-FDCDQS0 (Bit 7-bit 4): Allocate DMA resource for FDC.
PRTDQS3-PRTDQS0 (Bit 3-bit 0): Allocate DMA resource for PRT.
Publication Release Date: March 1998
Version 0.61
- 95 -
W83877TF
Bit 7- bit4, Bit 3 - bit 0
DMA selected
None
0000
0001
0010
0011
DMA_A
DMA_B
DMA_C
8.2.31 Configuration Register 27 (CR27)
When the device is in Extended Function mode and EFIR is 27, the CR27 register can be accessed
through EFDR. Default = 05H if CR6 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
2
1
7
6
5
4
3
0
PRTIQS0
PRTIQS1
PRTIQS2
PRTIQS3
reserved
ECPIRQx0
ECPIRQx1
ECPIRQx2
ECPIRQx2-ECPIRQx0 (Bit7-bit 5): These bits are configurable equivalents to bit[5:3] of cnfgB
register in ECP mode except that cnfgB[5:3] are read-only bits. They indicate the IRQ resource
assigned for the ECP printer port. It is the software designer's responsibility to ensure that CR27[7:5]
and CR27[3:0] are consistent. For example, CR27[7:5] should be filled with 001 (select IRQ 7) if
CR27[3:0] are to be programmed as 0101 (select IRQ_E) while IRQ_E is connected to IRQ 7.
CR27[7:5]
000
IRQ resource
reflect other IRQ resources selected by CR27[3:0] (default)
001
IRQ 7
010
IRQ 9
011
IRQ 10
IRQ 11
IRQ 14
IRQ 15
IRQ 5
100
101
110
111
Bit 4: Reserved.
PRTIQS3-PRTIQS0 (Bit 3-bit 0): Select IRQ resource for the parallel port. Any unselected IRQ pin is
in tri-state.
Publication Release Date: March 1998
- 96 -
Version 0.61
W83877TF
CR27[3:0]
0000
select IRQ pin
None
0001
IRQ_A
0010
IRQ_B
0011
IRQ_C
IRQ_D
IRQ_E
0100
0101
0110
IRQ_F
0111
IRQ_G
IRQ_H
1000
While in the Serial IRQ mode (IRQMODS=1, CR31 bit2), the above selection is invalid and all the
IRQ signal pins, from IRQ_A to IRQ_H, are all in tri-state. The parallel port IRQ is dedicated to the
SERIRQ pin. For the host controller to correctly sample the parallel port IRQ, the parallel port IRQ
should be programmed to appear in one of IRQ/Data Frame sampling periods.
In Serial IRQ mode, the definition of PRTIQS3-PRTIQS0 (bit 3-bit 0) is as follows:
PRTIQS3-PRTIQS0 (Bit 3-bit 0): Select the IRQ/Data Frame sampling period on the SERIRQ pin.
CR27[3:0]
0000
IRQ/Data Frame Period
None
IRQ1
0001
0010
Reserved for SMI
IRQ3
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
Publication Release Date: March 1998
Version 0.61
- 97 -
W83877TF
8.2.32 Configuration Register 28 (CR28)
When the device is in Extended Function mode and EFIR is 28, the CR28 register can be accessed
through EFDR. Default = 43H if CR6 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
2
1
7
6
5
4
3
0
URBIQS0
URBIQS1
URBIQS2
URBIQS3
URAIQS0
URAIQS1
URAIQS2
URAIQS3
URAIQS3-URAIQS0 (Bit 7-bit 4): Allocate interrupt resource for UART A.
URBIQS3-URBIQS0 (Bit 3-bit 0): Allocate interrupt resource for UART B.
8.2.33 Configuration Register 29 (CR29)
When the device is in Extended Function mode and EFIR is 29, the CR29 register can be accessed
through EFDR. Default = 62H if CR6 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
2
1
7
6
5
4
3
0
IQNIQS0
IQNIQS1
IQNIQS2
IQNIQS3
FDCIQS0
FDCIQS1
FDCIQS2
FDCIQS3
FDCIQS3-FDCIQS0 (Bit 7-bit 4): Allocate interrupt resource for FDC.
IQNIQS3-IQNIQS0 (Bit 3-bit 0): Allocate interrupt resource for IRQIN.
8.2.34 Configuration Register 2C (CR2C), default=00H
When the device is in Extended Function mode and EFIR is 2CH, the CR2C register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
reserved
reserved
CLKINSEL
reserved
reserved
reserved
reserved
reserved
Bit 7 - bit 3 : Reserved.
Publication Release Date: March 1998
Version 0.61
- 98 -
W83877TF
CLKINSEL (Bit 2): Clock input frequency selection.
This pin should be reset/set according the CLKIN pin.
0
1
the clock source on CLKIN pin is 24 MHz.(default)
the clock source on CLKIN pin is 48 MHz.
Bit 1- bit 0: Reserved.
8.2.35 Configuration Register 2D (CR2D), default=00H
When the device is in Extended Function mode and EFIR is 2DH, the CR2D register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
DRTA0
DRTA1
DIS_PRECOMP0
DRTB0
DRTB1
DIS_PRECOMP1
reserved
reserved
This register controls the data rate selection for FDC. It also controls if precompensation is enabled.
Bit 7 - bit 6: Reserved.
DIS_PRECOMP1 (Bit 5):
This bit controls if precompensation is enabled for FDD B.
0 enable precompensation for FDD B
1 disable precompensation for FDD B
DRTB1, DRTB0 (Bit 4,3):
These two bits combining with data rate selection bits in Date Rate Register select the operational
data rate for FDD B as shown in last table.
DIS_PRECOMP0 (Bit 2):
This bit controls if precompensation is enabled for FDD A.
0 enable precompensation for FDD A
1 disable precompensation for FDD A
DRTA1, DRTA0 (Bit 1 - bit 0):
These two bits combining with data rate selection bits in Date Rate Register select the operational
data rate for FDD A as follows:
Publication Release Date: March 1998
- 99 -
Version 0.61
W83877TF
Drive Rate Table
DRTA1 DRTA0
Data Rate
operational data rate
DRATE1
DRATE0
MFM
FM
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1M
500K
300K
250K
1M
---
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
250K
150K
125K
---
500K
500K
250K
1M
250K
250K
125K
---
500K
2M
250K
---
250K
125K
8.2.36 Configuration Register 31 (CR31), default=00H
When the device is in Extended Function mode and EFIR is 31H, the CR31 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
reserved
reserved
IRQMODS
reserved
SCIIRQ0
SCIIRQ1
SCIIRQ2
SCIIRQ3
SCIIRQ3 ~ SCIIRQ0 (Bit 7 - bit 4):
The four bits select one IRQ pin for the SCI signal except for dedicated SCI signal output pin. Any
unselected pin is in tri-state.
Publication Release Date: March 1998
- 100 -
Version 0.61
W83877TF
CR31[7:4]
0000
Mapped IRQ pin
None (default)
IRQ_A
0001
0010
IRQ_B
0011
IRQ_C
0100
IRQ_D
0101
IRQ_E
0110
IRQ_F
0111
IRQ_G
IRQ_H
1000
While in the Serial IRQ mode (IRQMODS=1, CR31 bit 2), the above selection is invalid and all the
IRQ signal pins, from IRQ_A to IRQ_H, are all in tri-state. The SCI interrupt output is dedicated to the
SERIRQ pin. For the host controller to correctly sample the SCI interrupt, the SCI interrupt should be
programmed to appear in one of IRQ/Data Frame sampling periods.
In Serial IRQ mode, the definition of SCIIQS3-SCIIQS0 (bit 7-bit 4) is as follows:
SCIIQS3-SCIIQS0 (bit 7-bit 4): Select the IRQ/Data sampling period on the SERIRQ pin.
CR27[7:4]
0000
IRQ/Data Frame Period
None
IRQ1
0001
0010
Reserved for SMI
IRQ3
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
Bit 3: Reserved.
Publication Release Date: March 1998
Version 0.61
- 101 -
W83877TF
IRQMODS (Bit 2):
IRQ mode selection. The W83877TF supports: (1) legacy ISA IRQ mode or ISA IRQ sharing mode.
(2) Serial IRQ mode used in the PCI bus. In the legacy ISA IRQ sharing mode, the selected IRQ pin
for the device's IRQ is defined in the configuration registers CR27 - CR29. In the ISA IRQ sharing
mode, configuration register CR18 indicates which IRQ pin is in the IRQ sharing mode.
0: legacy ISA IRQ mode or ISA IRQ sharing mode.(default)
1: Serial IRQ mode used in PCI bus.
Bit 1 - bit 0: Reserved.
8.2.37 Configuration Register 32 (CR32), default=00H
When the device is in Extended Function mode and EFIR is 32H, the CR32 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
URBPME
URAPME
FDCPME
PRTPME
reserved
reserved
reserved
CHIPPME
CHIPPME (Bit 7): W83877TF chip power management enable.
0
1
disable the ACPI/Legacy and the auto power management functions.
enable the ACPI/Legacy and the auto power management functions.
Bit 6 - bit 4: Reserved.
PRTPME (Bit 3): Printer port power management enable.
0
1
disable the auto power management function.
enable the auto power management function, if this bit and CHIPPME(CR32 bit
7) are both set to 1.
.
FDCPME (Bit 2): FDC power management enable.
0
1
disable the auto power management function.
enable the auto power management function, if this bit and CHIPPME(CR32 bit
7) are both set to 1.
.
Publication Release Date: March 1998
- 102 -
Version 0.61
W83877TF
URAPME (Bit 1): UART A power management enable.
0
1
disable and the auto power management function.
enable auto power management function, if this bit and CHIPPME(CR32 bit 7)
are both set to 1.
.
URBPME (Bit 0): UART B power management enable.
0
1
disable the auto power management functions.
enable the auto power management function, if this bit and CHIPPME(CR32 bit
7) are both set to 1.
.
8.2.38 Configuration Register 33 (CR33), default=00H
When the device is in Extended Function mode and EFIR is 33H, the CR33 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
reserved
reserved
PM1AD2
PM1AD3
PM1AD4
PM1AD5
PM1AD6
PM1AD7
PM1AD7 - PM1AD2 (Bit 7 - bit 2): Base address of the power management register block PM1.
This address is the base address of PM1a_EVT_BLK in the ACPI specification. The based address
should range from 01,0000,0000b to 11,1111,0000b ,i.e., 100H ~ 3F0H, where bit 1 and bit 0 of the
base address should be set to 0 and the based address is in the 16-byte alignment. Note that the
based address of PM1a_CNT_BLK is equal to PM1a_EVT_BLK + 4, and PM_TMR_BLK is equal to
PM1a_EVT_BLK + 8.
Bit 1 - bit 0: Reserved, fixed at 0.
8.2.39 Configuration Register 34 (CR34), default=00H
When the device is in Extended Function mode and EFIR is 34H, the CR34 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
reserved
GPEAD1
GPEAD2
GPEAD3
GPEAD4
GPEAD5
GPEAD6
GPEAD7
Publication Release Date: March 1998
Version 0.61
- 103 -
W83877TF
GPEAD7 - GPEAD1 (Bit7 - bit 1): Base address of the power management register block GPE.
This address is the base address of GPE0_BLK in the ACPI specification. The based address should
range from 01,0000,0000b to 11,1111,1000b ,i.e., 100H ~ 3F8H, where bit 0 of the base address
should be set to 0 and the based address is in the 8-byte alignment. Note that the base address of
GPE1_BLK is GPE0_BLK + 4.
Bit 0: Reserved, fixed at 0.
8.2.40 Configuration Register 35 (CR35), default=00H
When the device is in Extended Function mode and EFIR is 35H, the CR35 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
URACNT0
URACNT1
URACNT2
URACNT3
URACNT4
URACNT5
URACNT6
URACNT7
URACNT7 - URACNT0 (Bit 7 - bit 0): UART A idle timer count.
This register is used to specify the initial value of UART A idle timer. Once UART A enters the
working state (that is, after any access to this device, any IRQ, and any external input), the power
down machine of UART A reloads this count value and the idle timer counts down. When the timer
counts down to zero, UART A enters the power down state ,i.e., sleeping state. If this register is set to
00H, the power down function will be invalid. The time resolution of this value is minute or second,
which is defined by the TMIN_SEL bit of the CR3A. Note that (1). this register is valid only when the
power management function of UART A is enabled, that is, CHIPPME=1 (CR32 bit 7) and
URAPME=1 (CR32 bit 1), (2). If the register is set to 00H, UART A will remain in the current
state(working or sleeping).
8.2.41 Configuration Register 36 (CR36), default=00H
When the device is in Extended Function mode and EFIR is 36H, the CR36 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
URBCNT0
URBCNT1
URBCNT2
URBCNT3
URBCNT4
URBCNT5
URBCNT6
URBCNT7
Publication Release Date: March 1998
Version 0.61
- 104 -
W83877TF
URBCNT7 - URBCNT0 (Bit 7 - bit 0): UART B idle timer count.
This register is used to specify the initial value of UART B idle timer. Once UART B enters the
working state (that is, after any access to this device, any IRQ, and any external input), the power
down machine of UART B reloads this count value and the idle timer counts down. When the timer
counts down to zero, UART B enters the power down state ,i.e., sleeping state. If this register is set to
00H, the power down function will be invalid. The time resolution of this value is minute or second,
which is defined by the TMIN_SEL bit of CR3A. Note that (1). this register is valid only when the
power management function of UART B is enabled, that is, CHIPPME=1 (CR32 bit 7) and
URBPME=1 (CR32 bit 0), (2). If the register is set to 00H, UART B will remain in the current
state(working or sleeping).
8.2.42 Configuration Register 37 (CR37), default=00H
When the device is in Extended Function mode and EFIR is 37H, the CR37 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
FDCCNT0
FDCCNT1
FDCCNT2
FDCCNT3
FDCCNT4
FDCCNT5
FDCCNT6
FDCCNT7
FDCCNT7 - FDCCNT0 (Bit 7 - bit 0): FDC idle timer count.
This register is used to specify the initial value of FDC idle timer. Once FDC enters the working state
(that is, after any access to this device, any IRQ, and any external input), the power down machine of
FDC reloads this count value and the idle timer counts down. When the timer counts down to zero,
FDC enters the power down state ,i.e., sleeping state. If this register is set to 00H, the power down
function will be invalid. The time resolution of this value is minute or second, which is defined by the
TMIN_SEL bit of the CR3A. Note that (1). this register is valid only when the power management
function of FDC is enabled, that is, CHIPPME=1 (CR32 bit 7) and FDCPME=1 (CR32 bit 2), (2). If the
register is set to 00H, FDC will remain in the current state(working or sleeping).
Publication Release Date: March 1998
- 105 -
Version 0.61
W83877TF
8.2.43 Configuration Register 38 (CR38), default=00H
When the device is in Extended Function mode and EFIR is 38H, the CR38 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
PRTCNT0
PRTCNT1
PRTCNT2
PRTCNT3
PRTCNT4
PRTCNT5
PRTCNT6
PRTCNT7
PRTCNT7 - PRTCNT0 (Bit 7 - bit 0): printer port idle timer count.
This register is used to specify the initial value of the printer port idle timer. Once the printer port
enters the working state (that is, after any access to this device, any IRQ, and any external input), the
power down machine of the printer port reloads this count value and this idle timer counts down.
When the timer counts down to zero, printer port enters the power down state ,i.e., sleeping state. If
this register is set to 00H, the power down function will be invalid. The time resolution of this value is
minute or second, which is defined by the TMIN_SEL bit of CR3A. Note that (1). this register is valid
only when the power management function of the printer port is enabled, that is, CHIPPME=1 (CR32
bit 7) and PRTPME=1 (CR32 bit 3), (2). If the register is set to 00H, the printer port will remain in the
current state(working or sleeping).
8.2.44 Configuration Register (CR39), default=00H
When the device is in Extended Function mode and EFIR is 39H, the CR39 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
GSBCNT0
GSBCNT1
GSBCNT2
GSBCNT3
GSBCNT4
GSBCNT5
GSBCNT6
GSBCNT7
GSBCNT7 - GSBCNT0 (Bit 7 - bit 0): global stand-by idle timer count.
Once all devices of the chip (including UART A, UART B, FDC and the printer port) are in the power
down state, the power down machine of W83877TF chip loads this register value and counts down.
When the timer counts to zero, the whole chip enters the power down state, i.e., sleeping state. If this
register is set to 0, the power down function will be invalid. The time resolution of this register value is
minute or second, which is defined by the TMIN_SEL bit of CR3A. Note that (1). this register is valid
when the CHIPPME = 1 (CR32 bit 7), and (2) If the register is set to 00H, W83877TF chip will remain
in the current state(working or sleeping).
Publication Release Date: March 1998
- 106 -
Version 0.61
W83877TF
8.2.45 Configuration Register 3A (CR3A), default=00H
When the device is in Extended Function mode and EFIR is 3AH, the CR3A register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
UPULLEN
SMI_EN
reserved
reserved
reserved
TMIN_SEL
reserved
reserved
Bit 7 - bit 6 : Reserved, fixed at 0.
TMIN_SEL (Bit 5): Time resolution of the auto power machines of all devices.
CR35 to CR39 store the initial counts of the devices.
0
one second
one minute
1
Bit 4 - bit 2: Reserved, fixed at 0.
SMI_EN (Bit 1): SMI output pin enable.
While an SMI event is raised on the output of the SMI logic, this bit determines whether the SMI
interrupt will be generated on the SMI output SMI pin and on the Serial IRQ IRQSER pin while in
Serial IRQ mode.
0
1
disable
enable
UPULLEN (Bit 0): Enable the pull up of IRQSER pin in Serial IRQ mode.
0
1
disable the pull up of IRQSER pin.
enable the pull up of IRQSER pin.
8.2.46 Configuration Register 3B (CR3B), default=00H
Reserved for testing. Should be kept all 0's.
Publication Release Date: March 1998
Version 0.61
- 107 -
W83877TF
8.2.47 Configuration Register 40 (CR40), default=00H
When the device is in Extended Function mode and EFIR is 40H, the CR40 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
URBIDLSTS
URAIDLSTS
FDCIDLSTS
PRTIDLSTS
reserved
reserved
reserved
reserved
Bit 7 - bit 4 : Reserved, fixed at 0.
Bit 3 - bit 0 : Devices' idle status.
These bits indicate that the individual device's idle timer expires due to no I/O access, IRQ, and
external input to the device respectively. These 4 bits are controlled by the printer port, FDC, UART
A, and UART B power down machines individually. The bits are set/cleared by W83877TF
automatically. Writing a 1 can also clear this bit, and writing a 0 has no effect.
PRTIDLSTS (Bit 3): printer port idle status.
0
1
printer port is now in the working state.
printer port is now in the sleeping state due to no printer port access, IRQ, DMA
acknowledge, and no transition on BUSY, ACK , PE, SLCT, and ERR pins.
FDCIDLSTS (Bit 2): FDC idle status.
0
1
FDC is now in the working state.
FDC is now in the sleeping state due to no FDC access, no IRQ, no DMA
acknowledge, and no enabling of the motor enable bits in the DOR register.
URAIDLSTS (Bit 1): UART A idle status.
0
1
UART A is now in the working state.
UART A is now in the sleeping state due to no UART A access, no IRQ, the
receiver is now waiting for a start bit, the transmitter shift register is now empty,
and no transition on MODEM control input lines.
URBIDLSTS (Bit 0): UART B idle status.
0
1
UART B is now in the working state.
UART B is now in the sleeping state due to no UART B access, no IRQ, the
receiver is now waiting for a start bit, the transmitter shift register is now empty,
and no transition on MODEM control input lines.
Publication Release Date: March 1998
- 108 -
Version 0.61
W83877TF
8.2.48 Configuration Register 41 (CR41), default=00H
When the device is in Extended Function mode and EFIR is 41H, the CR41 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
URBTRAPSTS
URATRAPSTS
FDCTRAPSTS
PRTTRAPSTS
reserved
reserved
reserved
reserved
Bit 7 - bit 4 : Reserved, fixed at 0.
Bit 3 - bit 0 : Devices' trap status.
These bits indicate that the individual device wakes up due to any I/O access, IRQ, and external input
to the device respectively. The device's idle timer reloads the initial count value from CR35-CR39,
depending on which device wakes up. These 4 bits are controlled by the printer port, FDC, UART A,
and UART B power down machines individually. The bits are set/cleared by W83877TF
automatically. Writing a 1 can also clear this bit, and writing a 0 has no effect.
PRTTRAPSTS (Bit 3): printer port trap status.
0
1
the printer port is now in the sleeping state.
the printer port is now in the working state due to any printer port access, any
IRQ, any DMA acknowledge, and any transition on BUSY, ACK , PE, SLCT, and
ERR pins.
FDCTRAPSTS (Bit 2): FDC trap status.
0
1
FDC is now in the sleeping state.
FDC is now in the working state due to any FDC access, any IRQ, any DMA
acknowledge, and any enabling of the motor enable bits in the DOR register.
URATRAPSTS (Bit 1): UART A trap status.
0
1
UART A is now in the sleeping state.
UART A is now in the working state due to any UART A access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins
transmitting a start bit, and any transition on MODEM control input lines.
URBTRAPSTS (Bit 0): UART B trap status.
0
1
UART B is now in the sleeping state.
UART B is now in the working state due to any UART B access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins
transmitting a start bit, and any transition on MODEM control input lines.
Publication Release Date: March 1998
- 109 -
Version 0.61
W83877TF
8.2.49 Configuration Register 42 (CR42), default=N/A
When the device is in Extended Function mode and EFIR is 42H, the CR42 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
URBIRQSTS
URAIRQSTS
FDCIRQSTS
PRTIRQSTS
reserved
reserved
reserved
reserved
Bit 7 - bit 4 : Reserved, fixed at 0.
Bit 3 - bit 0 : Device's IRQ status .
These bits indicate the IRQ pin status of the individual device respectively. The device's IRQ status
bit is set or cleared at their source device, writing a 1 or 0 has no effect.
PRTIRQSTS (Bit 3) : printer port IRQ status. While the IRQ type of printer port is edge trigger-type,
this bit will set and reset immediately. As the software reads this bit, it indicates low level. The
software must read the IRQ status bit in the printer port device register to correctly identify whether
the printer port IRQ occurs.
FDCIRQSTS (Bit 2) : FDC IRQ status.
URAIRQSTS (Bit 1) : UART A IRQ status.
URBIRQSTS (Bit 0) : UART B IRQ status.
8.2.50 Configuration Register 43 (CR43), default=00H
When the device is in Extended Function mode and EFIR is 43H, the CR43 register can be accessed
through EFDR. This register is reserved.
8.2.51 Configuration Register 44 (CR44), default=00H
When the device is in Extended Function mode and EFIR is 44H, the CR44 register can be accessed
through EFDR. This register is reserved.
Publication Release Date: March 1998
- 110 -
Version 0.61
W83877TF
8.2.52 Configuration Register 45 (CR45), default=00H
When the device is in Extended Function mode and EFIR is 45H, the CR45 register can be accessed
through EFDR. The bit definitions are as follows:
2
1
7
6
5
4
3
0
URBIRQEN
URAIRQEN
FDCIRQEN
PRTIRQEN
reserved
reserved
reserved
reserved
Bit 7 - bit 4 : Reserved, fixed at 0.
Bit 3 - bit 0 : Enable bits of the SMI generation due to the device's IRQ.
These bits enable the generation of an SMI interrupt due to any IRQ of the devices respectively.
These 4 bits control the printer port, FDC, UART A, and UART B SMI logic's individually. The SMI
logic output for the IRQs is as follows:
SMI logic output = (URBIRQEN and URBIRQSTS) or (URAIRQEN and URAIRQSTS)
(FDCIRQEN and FDCIRQSTS) or (PRTIRQEN and PRTIRQSTS)
or
If any device's IRQ is raised, the corresponding IRQ status bit in CR42 is set. If the device's enable
bit is set and SMI_EN(in CR3A) and CHIPPME(in CR32) is both set, then SMI interrupt occurs on the
SMI output pin.
PRTIRQEN (Bit 3):
0
1
disable the generation of an SMI interrupt due to the printer port's IRQ.
enable the generation of an SMI interrupt due to the printer port's IRQ.
FDCIRQEN (Bit 2):
0
1
disable the generation of an SMI interrupt due to the FDC's IRQ.
enable the generation of an SMI interrupt due to the FDC's IRQ.
URAIRQEN (Bit 1):
0
1
disable the generation of an SMI interrupt due to the UART A's IRQ.
enable the generation of an SMI interrupt due to the UART A's IRQ.
URBIRQEN (Bit 0):
0
1
disable the generation of an SMI interrupt due to the UART B's IRQ.
enable the generation of an SMI interrupt due to the UART B's IRQ.
Publication Release Date: March 1998
Version 0.61
- 111 -
W83877TF
8.2.53 Bit Map Configuration Registers
Table 8-1: Bit Map of Configuration Registers
Power-on
Register
Reset Value
D7
D6
D5
0
D4
D3
PRTMODS1
0
D2
D1
0
D0
IPD
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
CR8
CR9
CRA
CRB
CRC
CRD
0000 0000
0000 0000
0000 0000
0011 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 1010
0000 0000
0000 1100
0010 1000
1010 0011
0
0
0
PRTMODS0
ABCHG
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EPPVER
URAPWD
0
0
URBPWD
0
0
0
SUAMIDI
URATRI
ECPFTHR1
FDCTRI
FDD A T1
BOOT 1
CHIP ID 1
0
SUBMIDI
URBTRI
ECPFTHR0
0
PRTPWD
0
PRTTRI
ECPFTHR3
FDCPWD
FDD B T1
MEDIA 1
CHIP ID 3
0
0
ECPFTHR2
0
0
0
0
0
SEL4FDD
FDD C T1
DISFDDWR
EN3MODE
0
FIPURDWN
FDD C T0
SWWP
0
FDD D T1
FDD D T0
0
FDD B T0
MEDIA 0
CHIP ID 2
0
FDD A T0
BOOT 0
CHIP ID 0
0
0
PRTMODS2
LOCKREG
0
0
0
0
Tx4WC
TURB
SIRTX0
Rx4WC
HEFERE
SIRRX1
ENIFCHG
0
IDENT
URIRSEL
HDUPLX
MFM
INVERTZ
RX2INV
IRMODE1
DRV2EN
TX2INV
IRMODE0
TURA
SIRTX1
0
SIRRX0
IRMODE2
CR10
CR11
CR12
CR13
CR14
CR15
CR16
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
GIO0AD7
G0CADM1
GIO1AD7
G1CADM1
GIOP0MD2
GIOP1MD2
0
GIO0AD6
G0CADM0
GIO1AD6
G1CADM0
GIOP0MD1
GIOP1MD1
0
GIO0AD5
0
GIO0AD4
0
GIO0AD3
GIO0AD2
GIO0AD10
GIO1AD2
GIO1AD10
GCS0IOW
GCS1IOW
PNPCVS
GIO0AD1
GIO0AD9
GIO1AD1
GIO1AD9
GDA0OPI
GDA1OPI
0
GIO0AD0
GIO0AD8
GIO1AD0
GIO1AD8
GDA0IPI
GDA1IPI
HEFRAS
0
GIO1AD5
0
GIO1AD4
0
GIO1AD3
0
GIOP0MD0
GIOP1MD0
G1IQSEL
GIO0CSH
GIO1CSH
G0IQSEL
GCS0IOR
GCS1IOR
0
1
00ss 0s0s
CR17
CR18
CR19
0000 0000
0000 0000
0000 0000
0
SHARH
0
0
SHARG
0
0
SHARF
0
PRIRQOD
SHARE
0
DSFDLGRQ
SHARD
0
DSPRLGRQ
SHARC
0
DSUALGRQ
SHARB
DSUBLGRQ
SHARA
FASTA
FASTB
2
CR20
CR23
CR24
CR25
CR26
CR27
CR28
CR29
FDCAD7
PRTAD7
URAAD7
URBAD7
FDCDQS3
ECPIRQx2
URAIQS3
FDCIQS3
FDCAD6
PRTAD6
URAAD6
URBAD6
FDCDQS2
ECPIRQx1
URAIQS2
FDCIQS2
FDCAD5
PRTAD5
URAAD5
URBAD5
FDCDQS1
ECPIRQx0
URAIQS1
FDCIQS1
FDCAD4
PRTAD4
URAAD4
URBAD4
FDCDQS0
0
FDCAD3
PRTAD3
URAAD3
URBAD3
PRTDQS3
PRTIQS3
URBIQS3
IQNIQS3
FDCAD2
PRTAD2
URAAD2
URBAD2
PRTDQS2
PRTIQS2
URBIQS2
IQNIQS2
0
0
1111 1100
2
PRTAD1
URAAD1
URBAD1
PRTDQS1
PRTIQS1
URBIQS1
IQNIQS1
PRTAD0
0
1101 1110
2
1111 1110
2
0
1011 1110
2
PRTDQS0
PRTIQS0
URBIQS0
IQNIQS0
0010 0011
2
0000 0101
2
URAIQS0
FDCIQS0
0100 0011
2
0110 0000
CR2C
CR2D
CR31
CR32
CR33
CR34
CR35
CR36
CR37
CR38
CR39
CR3A
0000 0000
0000 0000
0000 0s00
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0
0
0
0
0
CLKINSEL
DIS-PRECOM0
IRQMODS
FDCPME
PM1AD2
0
0
0
0
DIS-PRECOM1
SCIIRQ1
0
DRTB 1
SCIIRQ0
0
DRTB 0
0
DRTA 1
0
DRTA 0
0
SCIIRQ3
CHIPPME
PM1AD7
GPEAD7
URACNT7
URBCNT7
FDCCNT7
PRTCNT7
GSBCNT7
0
SCIIRQ2
0
PRTPME
PM1AD3
GPEAD3
URACNT3
URBCNT3
FDCCNT3
PRTCNT3
GSBCNT3
0
URAPME
0
URBPME
0
PM1AD6
GPEAD6
URACNT6
URBCNT6
FDCCNT6
PRTCNT6
GSBCNT6
0
PM1AD5
GPEAD5
URACNT5
URBCNT5
FDCCNT5
PRTCNT5
GSBCNT5
TMIN_SEL
PM1AD4
GPEAD4
URACNT4
URBCNT4
FDCCNT4
PRTCNT4
GSBCNT4
0
GPEAD2
GPEAD1
URACNT1
URBCNT1
FDCCNT1
PRTCNT1
GSBCNT1
SMI_EN
0
URACNT2
URBCNT2
FDCCNT2
PRTCNT2
GSBCNT2
0
URACNT0
URBCNT0
FDCCNT0
PRTCNT0
GSBCNT0
UPULLEN
CR40
CR41
CR42
CR43
CR44
CR45
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PRTIDLSTS
FDCIDLSTS
URAIDLSTS
URBIDLSTS
PRTTRAPSTS FDCTRAPSTS URATRAPSTS URBTRAPSTS
PRTIRQSTS
FDCIRQSTS
URAIRQSTS
URBIRQSTS
0
0
0
0
0
0
0
0
PRTIRQEN
FDCIRQEN
URAIRQEN
URBIRQEN
Notes:
1. 's' means its value depends on corresponding power-on setting pin.
2. These default values are valid when CR16 bit 2 is 1 during power-on reset; They will be all 0's if CR16 bit 2 is 0.
Publication Release Date: March 1998
Version 0.61
- 112 -
W83877TF
8.3 ACPI Registers Features
W83877TF supports both the ACPI and legacy power management's. The switch logic of the power
management block generates an SMI interrupt in the legacy mode and an SCI interrupt in the ACPI
mode. For the legacy mode, the SMI_EN bit is used. If it is set, it routes the power management
events from the SMI interrupt logic to the SMI output pin. For the ACPI mode, the SCI_EN bit is used.
If it is set, it route the power management events to the SCI interrupt logic. The SMI_EN bit is located
in the CR3A register and the SCI_EN bit is located in the PM1 register block. See the following figure
for illustration.
SMI_EN
IRQs
SMI events
SMI Logic
SMI output
Logic
SMI
0
1
IRQs
PM Timer
SCI output
Logic
SCI
SCI_EN
SCI events
SCI Logic
WAK_STS
IRQs
Sleep/Wake
State machine
Clock
Control
Device Idle
Timers
Device Trap
Global STBY
Timer
The SMI interrupt is routed to pin SMI , which is dedicated for the SMI interrupt output. Another way
to output the SMI interrupt is to route to pin IRQSER, which is the signal pin in the Serial IRQ mode.
The SCI interrupt is routed to pin SCI , which is dedicated for the SCI function. The other way to
output the SCI interrupt is to route to one interrupt request signal pin IRQA~H, which is selected
through CR31 bit[7:4]. Another way is output the SCI interrupt is to route to pin IRQSER.
Publication Release Date: March 1998
- 113 -
Version 0.61
W83877TF
8.3.1 SMI to SCI/SCI to SMI and Bus Master
For the process of generating an interrupt from SMI to SCI or from SCI to SMI, see the following
figure for illustration.
clear
GBL_STS
from SMI to SCI
set
BIOS_RLS
To SCI Logic
GBL_EN
clear
BIOS_STS
from SCI to SMI
set
GBL_RLS
To SMI Logic
BIOS_EN
clear
BM_STS
Bus Master SCI
set
BM_CNTPL
To SCI Logic
BM_RLD
: Status bit
: Enable bit
For the BIOS software to raise an event to the ACPI software, BIOS_RLS, GBL_EN, and GBL_STS
bits are involved. GBL_EN is the enable bit and the GBL_STS is the status bit. Both are controlled by
the ACPI software. If BIOS_RLS is set by the BIOS software and GBL_EN is set by the ACPI
software, an SCI interrupt is raised. Writing a 1 to BIOS_RLS sets it to logic 1 and also sets
GBL_STS to logic 1; Writing a 0 to BIOS_RLS has no effect. Writing a 1 to GBL_STS clears it to
logic 0 and also clears BIOS_RLS to logic 0; writing a 0 to GBL_STS has no effect.
For the ACPI software to raise an event to the BIOS software, GBL_RLS, BIOS_EN, and BIOS_STS
bits are involved. BIOS_EN is the enable bit and the BIOS_STS is the status bit. Both are controlled
by the BIOS software. If GBL_RLS is set by the ACPI software and BIOS_EN is set by the BIOS
software, an SMI is raised. Writing a 1 to GBL_RLS sets it to logic 1 and also sets BIOS_STS to
logic 1; Writing a 0 to GBL_RLS has no effect. Writing a 1 to BIOS_STS clears it to logic 0 and also
clears GBL_RLS to logic 0; writing a 0 to BIOS_STS has no effect.
Publication Release Date: March 1998
- 114 -
Version 0.61
W83877TF
For the bus master to raise an event to the ACPI software, BM_CNTRL, BM_RLD, and BM_STS bits
are involved. Both BM_RLD and BM_STS are controlled by the ACPI software. If BM_CNTRL is set
by the BIOS software and BM_RLD is set by the ACPI software, an SCI interrupt is raised. Writing a
1 to BM_CNTRL sets it to logic 1 and also sets BM_STS to logic 1; Writing a 0 to BM_CNTRL has no
effect. Writing a 1 to BM_STS clears it to logic 0 and also clears BM_CNTRL to logic 0; writing a 0 to
BM_STS has no effect.
8.3.2 Power Management Timer
In the ACPI specification, it requires a power management timer. The power management timer is a
24-bit fixed rate free running count-up timer that runs off a 3.579545MHZ clock. The power
management timer has the corresponding status bit (TMR_STS) and enable bit (TMR_EN). The
TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1 or from 1 to 0. If the
TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. Three registers are
used to read the timer value, they are located in the PM1 register block. The power management
timer has one enable bit (TMR_ON) to turn if on or off. The TMR_ON is located in GPE register
block. If it is cleared to 0, the power management timer function would not work. There are no timer
reset requirements, except that the timer should function after power-up. See the following figure for
illustration.
TMR_STS
TMR_EN
TMR_ON
24 bit
counter
To SCI Logic
Bits (23-0)
3.579545 MHz
24
TMR_VAL
8.4 ACPI Registers (ACPIRs)
The ACPI register model consists of the fixed register blocks that perform the ACPI functions. A
register block may be a event register block which deals with ACPI events or a control register block
which deals with control features. The ordering in the event register block is the status register,
followed by the enable register.
Each event register, if implemented, contains two two register: a status register and an enable
register, both in 16-bit size. The status register indicates what defined function needs the ACPI
System Control Interrupt (SCI). While the hardware event occurs, the defined status bit is set.
However, to generate the SCI, the associated enable bit is required to be set. If the enable bit is not
set, the software can examine the state of the hardware event by reading the status bit without
generating an SCI interrupt.
Any status bit, unless otherwise noted, can only be set by some defined hardware event. It is cleared
by writing a 1 to its bit position and writing a 0 has no effect. Except for some special status bits,
every status bit has an associated enable bit in the same bit position in the enable register. Those
Publication Release Date: March 1998
- 115 -
Version 0.61
W83877TF
status bits which have no respective enable bit are read for special purposes. Revered or un-
implemented enable bits always return zero, and writing to these bits should have no effect.
The control bit in the control register provides some special control functions over the hardware
event, or some special control over SCI event. Reversed or un-implemented control bits always
return zero, and writing to those bits should have no effect.
Table 8-4 lists the PM1 register block and the relative locations of the registers within it. The base
address of PM1 register block is named as PM1a_EVT_BLK in the ACPI specification. The based
address should range from 01,0000,0000b to 11,1111,0000b ,i.e., 100H ~ 3F0H, where bit 1 and bit 0
of PM1 register block should be set to 0 and the based address is in the 16-byte alignment.
Table 8-5 lists the GPE register block and the relative locations within it. The base address of power
management event block GPE is named as GPE0_BLK in the ACPI specification. The based address
should range from 01,0000,0000b to 11,1111,1000b ,i.e., 100H ~ 3F8H, where bit 0 of the base
address should be set to 0 and the base address is in the 8-byte alignment.
8.4.1 Power Management 1 Status Register 1 (PM1STS1)
Register Location:
Default Value:
Attribute:
<CR33> System I/O Space
00h
Read/write
8 bits
Size:
2
1
7
6
5
4
3
0
TMR_STS
Reserved
Reserved
Reserved
BM_STS
GBL_STS
Reserved
Reserved
Bit
Name
Description
0
TMR_STS
This bit is the timer carry status bit. This bit gets set anytime the bit 23 of the
24-bit counter changes(whenever the MSB changes from low to high or high
to low). While TMR_EN and TMR_STS are set a power magnet event is
raised. This bit is only set by hardware and can only be cleared by the
software writing a 1 to this bit position. Writing a 0 has no effect.
1-3
4
Reserved
BM_STS
Reserved.
This is the bus master status bit. Writing a 1 to BM_CNTRL also sets
BM_STS. Writing a 1 clears this bit and also clears BM_CNTRL. Writing a 0
has no effect.
5
GBL_STS
Reserved
This is the global status bit. This bit is set when the BIOS want the attention
of the SCI handler. BIOS sets this bit by setting BIOS_RLS and can only be
cleared by software writing a 1 to this bit position. Writing a 1 to this bit
position also clears BIOS_RLS. Writing a 0 has no effect.
6-7
Reserved. These bits always return a value of zero.
Publication Release Date: March 1998
- 116 -
Version 0.61
W83877TF
8.4.2 Power Management 1 Status Register 2 (PM1STS2)
Register Location:
Default Value:
Attribute:
<CR33>+1H System I/O Space
00h
Read/write
8 bits
Size:
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
WAK_STS
Bit
0-6
Name
Reserved
WAK_STS
Description
Reserved.
7
This bit is set when the system is in the sleeping state and an enabled resume
event occurs. Upon setting this bit, the sleeping/working state machine will
transition the system to the working state. This bit is only set by hardware and
is cleared by software writing a 1 to this bit position or by the sleeping/working
state machine automatically upon the global standby timer expires. Writing a
0 has no effect. Once the WAK_STS is cleared and all devices have been in
sleeping state, the whole chip enters the sleeping state.
8.4.3 Power Management 1 Enable Register 1(PM1EN1)
Register Location:
Default Value:
Attribute:
<CR33>+2H System I/O Space
00h
Read/write
8 bits
Size:
2
1
7
6
5
4
3
0
TMR_EN
Reserved
Reserved
Reserved
GBL_EN
Reserved
Reserved
Reserved
Publication Release Date: March 1998
Version 0.61
- 117 -
W83877TF
Bit
Name
Description
0
TMR_EN
This is the timer carry interrupt enable bit. When this bit is set then an SCI
event is generated anytime the TMR_STS bit is set. When this bit is reset
then no interrupt is generated when the TMR_STS bit is set.
1-4
5
Reserved
GBL_EN
Reserved. These bits always return a value of zero.
The global enable bit. When both the GBL_EN bit and the GBL_STS bit are
set, an SCI interrupt is raised.
6-7
Reserved
Reserved.
8.4.4 Power Management 1 Enable Register 2 (PM1EN2)
Register Location:
Default Value:
Attribute:
<CR33>+3H System I/O Space
00h
Read/write
8 bits
Size:
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
0-7
Name
Description
Reserved. These bits always return a value of zero.
Reserved
8.4.5 Power Management 1 Control Register 1 (PM1CTL1)
Register Location:
Default Value:
Attribute:
<CR33>+4H System I/O Space
00h
Read/write
8 bits
Size:
Publication Release Date: March 1998
Version 0.61
- 118 -
W83877TF
2
1
7
6
5
4
3
0
SCI_EN
BM_RLD
GBL_RLD
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
Name
SCI_EN
Description
0
Selects the power management event to be either an SCI or an SMI interrupt.
When this bit is set, then the power management events will generate an SCI
interrupt. When this bit is reset and SMI_EN bit is set, then the power
management events will generate an SMI interrupt.
1
2
BM_RLD
This is the bus master reload enable bit. If this bit is set and BM_CNTRL is
set, an SCI interrupt is raised.
GBL_RLS
The global release bit. This bit is used by the ACPI software to raise an event
to the BIOS software. The BIOS software has a corresponding enable and
status bit to control its ability to receive the ACPI event. Setting GBL_RLS
sets BIOS_STS, and it generates an SMI interrupt if BIOS_EN is also set.
3-7
Reserved
Reserved. These bits always return a value of zero.
8.4.6 Power Management 1 Control Register 2 (PM1CTL2)
Register Location:
Default Value:
Attribute:
<CR33>+5H System I/O Space
00h
Read/write
8 bits
Size:
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
0-7
Name
Description
Reserved. These bits always return a value of zero.
Reserved
Publication Release Date: March 1998
Version 0.61
- 119 -
W83877TF
8.4.7 Power Management 1 Control Register 3 (PM1CTL3)
Register Location:
Default Value:
Attribute:
<CR33>+6H System I/O Space
00h
Read/write
8 bits
Size:
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
0-7
Name
Description
Reserved. These bits always return a value of zero.
Reserved
8.4.8 Power Management 1 Control Register 4 (PM1CTL4)
Register Location:
Default Value:
Attribute:
<CR33>+7H System I/O Space
00h
Read/write
8 bits
Size:
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
0-7
Name
Description
Reserved. These bits always return a value of zero.
Reserved
Publication Release Date: March 1998
Version 0.61
- 120 -
W83877TF
8.4.9 Power Management 1 Timer 1 (PM1TMR1)
Register Location:
Default Value:
Attribute:
<CR33>+8H System I/O Space
00h
Read only
8 bits
Size:
2
1
7
6
5
4
3
0
TMR_VAL0
TMR_VAL1
TMR_VAL2
TMR_VAL3
TMR_VAL4
TMR_VAL5
TMR_VAL6
TMR_VAL7
Bit
0-7
Name
Description
TMR_VAL
This read-only field returns the running count of the power management timer.
This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts
while in the system working state. The timer is reset and then continues
counting until the CLKIN input the the chip is stopped. If the clock is restarted
without a MR reset, then the counter will continue counting from where it
stopped. The TMR_STS bit is set any time the last bit of the timer (bit 23)
goes from 0 to 1 or from 1 to 0. If the TMR_EN bit is set, the setting of the
TMR_STS bit will generate an SCI interrupt.
8.4.10 Power Management 1 Timer 2 (PM1TMR2)
Register Location:
Default Value:
Attribute:
<CR33>+9H System I/O Space
00h
Read only
8 bits
Size:
2
1
7
6
5
4
3
0
TMR_VAL8
TMR_VAL9
TMR_VAL10
TMR_VAL11
TMR_VAL12
TMR_VAL13
TMR_VAL14
TMR_VAL15
Publication Release Date: March 1998
Version 0.61
- 121 -
W83877TF
Bit
0-7
Name
Description
TMR_VAL
This read-only field returns the running count of the power management timer.
This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts
while in the system working state. The timer is reset and then continues
counting until the CLKIN input the the chip is stopped. If the clock is restarted
without a MR reset, then the counter will continue counting from where it
stopped. The TMR_STS bit is set any time the last bit of the timer (bit 23)
goes from 0 to 1 or from 1 to 0. If the TMR_EN bit is set, the setting of the
TMR_STS bit will generate an SCI interrupt.
8.4.11 Power Management 1 Timer 3 (PM1TMR3)
Register Location:
Default Value:
Attribute:
<CR33>+AH System I/O Space
00h
Read only
8 bits
Size:
2
1
7
6
5
4
3
0
TMR_VAL16
TMR_VAL17
TMR_VAL18
TMR_VAL19
TMR_VAL20
TMR_VAL21
TMR_VAL22
TMR_VAL23
Bit
0-7
Name
Description
TMR_VAL
This read-only field returns the running count of the power management timer.
This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts
while in the system working state. The timer is reset and then continues
counting until the CLKIN input the the chip is stopped. If the clock is restarted
without a MR reset, then the counter will continue counting from where it
stopped. The TMR_STS bit is set any time the last bit of the timer (bit 23)
goes from 0 to 1 or from 1 to 0. If the TMR_EN bit is set, the setting of the
TMR_STS bit will generate an SCI interrupt.
Publication Release Date: March 1998
- 122 -
Version 0.61
W83877TF
8.4.12 Power Management 1 Timer 4 (PM1TMR4)
Register Location:
Default Value:
Attribute:
<CR33>+BH System I/O Space
00h
Read only
Size:
8 bits
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
0-7
Name
Description
Reserved. These bits always return a value of zero.
Reserved
8.4.13 General Purpose Event 0 Status Register 1 (GP0STS1)
Register Location:
Default Value:
Attribute:
<CR34> System I/O Space
00h
Read/write
8 bits
Size:
2
1
7
6
5
4
3
0
URBSCISTS
URASCISTS
FDCSCISTS
PRTSCISTS
Reserved
Reserved
Reserved
Reserved
These bits indicate the status of the SCI input, which is set when the device's IRQ is raised. If the
corresponding enable bit in the SCI interrupt enable register (in GP0EN1) is set, an SCI interrupt is
raised and routed to the output pin. Writing a 1 clears the bit, and writing a 0 has no effect. If the bit
is not cleared, new IRQ for the SCI logic input is ignored, therefore no SCI interrupt is raised.
Bit
Name
Description
0
URBSCISTS UART B SCI status, which is set by the UART B IRQ.
URASCISTS UART A SCI status, which is set by the UART A IRQ.
FDCSCISTS FDC SCI status, which is set by the FDC IRQ.
PRTSCISTS PRT SCI status, which is set by the printer port IRQ.
1
2
3
4-7
Reserved
Reserved.
Publication Release Date: March 1998
Version 0.61
- 123 -
W83877TF
8.4.14 General Purpose Event 0 Status Register 2 (GP0STS2)
Register Location:
Default Value:
Attribute:
<CR34>+1H System I/O Space
00h
Read/write
8 bits
Size:
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
0-7
Name
Description
Reserved. These bits always return a value of zero.
Reserved
8.4.15 General Purpose Event 0 Enable Register 1 (GP0EN1)
Register Location:
Default Value:
Attribute:
<CR34> +2H System I/O Space
00h
Read/write
8 bits
Size:
2
1
7
6
5
4
3
0
URBSCIEN
URASCIEN
FDCSCIEN
PRTSCIEN
Reserved
Reserved
Reserved
Reserved
These bits are used to enable the device's IRQ sources onto the SCI logic. The SCI logic output for
the IRQs is as follows:
SCI logic output = (URBSCIEN and URBSCISTS) or (URASCIEN and URASCISTS) or (FDCSCIEN
and FDCSCISTS) or (PRTSCIEN and PRTSCISTS)
Publication Release Date: March 1998
- 124 -
Version 0.61
W83877TF
Bit
Name
Description
0
URBSCIEN
URASCIEN
FDCSCIEN
PRTSCIEN
Reserved
UART B SCI enable, which controls the UART B IRQ for SCI.
UART A SCI enable, which controls the UART A IRQ for SCI.
FDC SCI enable, which controls the FDC IRQ for SCI.
printer port SCI enable, which controls the printer port IRQ for SCI.
Reserved.
1
2
3
4-7
8.4.16 General Purpose Event 0 Enable Register 2 (GP0EN2)
Register Location:
Default Value:
Attribute:
<CR34>+3H System I/O Space
00h
Read/write
8 bits
Size:
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
0-7
Name
Description
Reserved. These bits always return a value of zero.
Reserved
8.4.17 General Purpose Event 1 Status Register 1 (GP1STS1)
Register Location:
Default Value:
Attribute:
<CR34>+4H System I/O Space
00h
Read/write
8 bits
Size:
Publication Release Date: March 1998
Version 0.61
- 125 -
W83877TF
2
1
7
6
5
4
3
0
BIOS_STS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
Name
Description
0
BIOS_STS
The BIOS status bit. This bit is set when GBL_RLS is set. If BIOS_EN is set,
setting GBL_RLS will raise an SMI event. Writing a 1 to its bit location clears
BIOS_STS and also clears GBL_RLS. Writing a 0 has no effect.
1-7
Reserved
Reserved.
8.4.18 General Purpose Event 1 Status Register 2 (GP1STS2)
Register Location:
Default Value:
Attribute:
<CR34>+5H System I/O Space
00h
Read/write
8 bits
Size:
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
0-7
Name
Description
Reserved. These bits always return a value of zero.
Reserved
8.4.19 General Purpose Event 1 Enable Register 1 (GP1EN1)
Register Location:
Default Value:
Attribute:
<CR34>+6H System I/O Space
00h
Read/write
8 bits
Size:
Publication Release Date: March 1998
Version 0.61
- 126 -
W83877TF
2
1
7
6
5
4
3
0
BIOS_EN
TMR_ON
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
Name
Description
0
BIOS_EN
This bit is raise the SMI event. When this bit is set and the ACPI software
writes a 1 to the GBL_RLS bit, an SMI event is raised on the SMI logic output.
1
TMR_ON
Reserved
This bit is used to turn on the power management timer. 1: timer on ; 0: timer
off.
2-7
Reserved.
8.4.20 General Purpose Event 1 Enable Register 2 (GP1EN2)
Register Location:
Default Value:
Attribute:
<CR34>+7H System I/O Space
00h
Read/write
8 bits
Size:
2
1
7
6
5
4
3
0
BIOS_RLS
BM_CNTRL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
Name
Description
0
BIOS_RLS
The BIOS release bit. This bit is used by the BIOS software to raise an event
to the ACPI software. The ACPI software has a corresponding enable and
status bit to control its ability to receive the ACPI event. Setting BIOS_RLS
sets GBL_STS, and it generates an SCI interrupt if GBL_EN is also set.
Writing a 1 to its bit position sets this bit and also sets the BM_STS bit.
Writing a 0 has no effect. This bit is cleared by writing a 1 to the GBL_STS
bit.
1
BM_CNTRL
This bit is used to set the BM_STS bit and if the BM_RLD bit is also set, then
an SCI interrupt is generated. Writing a 1 sets BM_CNTRL to 1 and also sets
BM_STS. Writing a 0 has no effect. Writing a 1 to BM_STS clears BM_STS
and also clears BM_CNTRL.
2-7 Reserved
Reserved.
Publication Release Date: March 1998
- 127 -
Version 0.61
W83877TF
8.4.21 Bit Map Configuration Registers
Table 8-4: Bit Map of PM1 Register Block
Register
Address
Power-On
D7
D6
D5
D4
D3
D2
D1
D0
Reset
Value
PM1STS1
PM1STS2
PM1EN1
<CR33>
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0
0
GBL_STS
BM_STS
0
0
0
TMR_STS
<CR33>+1H
<CR33>+2H
<CR33>+3H
<CR33>+4H
<CR33>+5H
<CR33>+6H
<CR33>+7H
<CR33>+8H
<CR33>+9H
<CR33>+AH
<CR33>+BH
WAK_STS
0
0
0
0
0
0
0
0
0
GBL_EN
0
0
0
0
TMR_EN
PM1EN2
0
0
0
0
0
0
0
0
PM1CTL1
PM1CTL2
PM1CTL3
PM1CTL4
PM1TMR1
PM1TMR2
PM1TMR3
PM1TMR4
0
0
0
0
0
GBL_RLS
BM_RLD
SCI_EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TMR_VAL7
TMR_VAL6
TMR_VAL5
TMR_VAL4
TMR_VAL3
TMR_VAL2
TMR_VAL1
TMR_VAL9
TMR_VAL0
TMR_VAL8
TMR_VAL16
0
TMR_VAL15 TMR_VAL14 TMR_VAL13 TMR_VAL12 TMR_VAL11 TMR_VAL10
TMR_VAL23 TMR_VAL22 TMR_VAL21 TMR_VAL20 TMR_VAL19 TMR_VAL18 TMR_VAL17
0
0
0
0
0
0
Table 8-5: Bit Map of GPE Register Block
Register
Address
Power-On
Reset Value
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
D7
D6
D5
D4
D3
D2
D1
D0
GP0STS1
GP0STS2
GP0EN1
GP0EN2
GP1STS1
GP1STS2
GP1EN1
GP1EN2
<CR34>
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PRTSCISTS
FDCSCISTS
URASCISTS
URBSCISTS
<CR34>+1H
<CR34>+2H
<CR34>+3H
<CR34>+4H
<CR34>+5H
<CR34>+6H
<CR34>+7H
0
0
0
0
PRTSCIEN
FDCSCIEN
URASCIEN
URBSCIEN
0
0
0
0
0
0
0
0
0
0
0
0
0
BIOS_STS
0
0
TMR_ON
BM_CNTRL
BIOS_EN
BIOS_RLS
Publication Release Date: March 1998
Version 0.61
- 128 -
相关型号：
W83C17P
Processor Specific Clock Generator, 80MHz, CMOS, PDSO14, 0.150 INCH, PLASTIC, SOP-14
WINBOND
W83C553F-G
W83C553F-G Highly Integrated System I/O Controller for Power PCTM (South Bridge) QFP 208
ETC
©2020 ICPDF网 联系我们和版权申明