W83C43 [WINBOND]
KEYBOARD CONTROLLER; 键盘控制器
| 型号： | W83C43 |
| 厂家： | 
WINBOND |
| 描述： | KEYBOARD CONTROLLER |
| 文件： | 总21页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W83C43
KEYBOARD CONTROLLER
GENERAL DESCRIPTION
The W83C43 is a keyboard controller designed to provide the functions needed to interface a CPU to
a keyboard or to a PS/2 mouse. The W83C43 can be used with IBMÒ-compatible personal computers
or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks
the parity of the data, and presents the data to the system as a byte of data in its output buffer. The
controller will interrupt the system when data are placed in its output buffer. The keyboard and PS/2
mouse are required to acknowledge all data transmissions. No transmission should be sent to the
keyboard or PS/2 mouse until acknowledge is received for the previous byte sent.
This fast keyboard controller can improve the performance of IBM PC/ATÒ 386Ô DX/SX and 486Ô
DX/SX machines and their compatibles. Hardwire methodology is used in this controller instead of
software implementation, as in the traditional 8042 keyboard BIOS. With full hardware
implementation, this enables the keyboard controller to respond instantly to all commands sent from
the keyboard and PS/2 mouse to the CPU BIOS.
The keyboard controller enables popular programs such as AutoCADÒ, MicrosoftÒ WindowsÔ 3.1,
NOVELLÒ, and other programs to run much faster.
FEATURES
· Supports IBM PC/AT 386 DX/SX and 486 DX/SX system designs
· Full hardwire design based on advanced VLSI CMOS technology
· Supports PS/2 Mouse
· 6 MHz to 12 MHz operating frequency
· Supports AT mode and PS/2 mode for different hardware configurations
· Automatically detects PS/2 mode or AT mode
· Much faster than traditional keyboard controller
· Packaged in 40-pin DIP or 44-pin PLCC
Publication Release Date: January 1996
- 1 -
Revision A2
W83C43
PIN CONFIGURATIONS
40-pin DIP
T0
X1
X2
1
Vcc
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
2
T1
3
P27 (KDAT)
P26 (KCLK)
P25 (IEMP/MINT)
P24 (KINT)
P17 (KINH)
P16 (DISP)
P15 (JUMP)
P14 (RAM)
P13
RESET
Vcc
CS
4
5
6
GND
RD
A2
7
8
9
WR
NC
D0
10
11
12
13
14
15
16
17
18
19
20
P12
D1
P11
D2
P10
D3
NC
D4
Vcc
D5
P23 (NC/MCLK)
P22 (NC/MDAT)
P21 (GA20)
P20 (RC)
D6
D7
GND
44-pin PLCC
/
R
E
V
S
P
2
7
V
c
c
P
2
6
P
2
5
c
T
0
N
C
T
1
X
2
X
1
E
T
c
40
6
5
4
3
2
1
44 43 42
41
7
8
9
P24
39
CS
38
37
36
35
34
33
32
31
GND
P17
P16
P15
RD
A2
WR
10
11
12
13
14
15
P14
NC
NC
NC
D0
D1
P13
P12
P11
P10
NC
16
17
D2
D3
30
29
18 19 20 21 22 23 24 25 26 27 28
D
4
D
5
D
6
D
7
G
N
D
P
2
3
N
C
P
2
0
P
2
1
P
2
2
V
c
c
- 2 -
W83C43
PIN DESCRIPTION
PIN NO.
I/O
NAME
FUNCTION
(40-pin
DIP)
(44-pin
PLCC)
AT MODE
PS/2 MODE
1
2
3
4
2
3
4
5
I
I
I
I
T0
X1
X2
K/B Clock Input
Crystal Clock I/P
Crystal Clock I/P
Chip Reset
K/B Clock Input
Crystal Clock I/P
Crystal Clock I/P
Chip Reset
RESET
VCC
5
6
-
Optional +5V Power
Supply
Optional + 5V Power
Supply
6
7
I
Chip Select
Chip Select
CS
7
8
8
9
-
I
GND
Optional Ground Power
I/O Read
Optional Ground Power
I/O Read
RD
A2
9
10
11
I
I
Connect to Address A2
I/O Write
Connect to Address A2
I/O Write
10
WR
NC
11, 26
1, 12, 13,
23, 29, 34
-
Reserved
Reserved
12, 13, 14, 14, 15, 16,
15, 16, 17, 17, 18, 19,
I/O
D0- D7
Data Bus D0- D7
Data Bus D0- D7
18, 19
20, 21
20
22
-
GND
P20
Ground Power Supply
Bit 0 of Port2
Ground Power Supply
Bit 0 of Port2
21
22
23
24
25
26
O
(RC : System Reset)
Bit 1 of Port2
(RC : System Reset)
Bit 1 of Port2
O
P21
P22
( GA20 : GATE A20)
Bit 2 of Port2
( GA20 : GATE A20)
Bit 2 of Port2
I/O
(NC: User-defined I/O)
(MDAT: Mouse Data
Output)
24
25
27
28
I/O
-
P23
VCC
Bit 3 of Port2
Bit 3 of Port2
(NC: User-defined I/O)
(MCLK: Mouse Clock
Output)
Optional +5V Power
Supply
Optional + 5V Power
Supply
Publication Release Date: January 1996
Revision A2
- 3 -
W83C43
Pin Description, continued
PIN NO.
I/O
NAME
FUNCTION
(40-pin
DIP)
(44-pin
PLCC)
AT MODE
Bit 0 of Port1
PS/2 MODE
27
28
29
30
31
30
I/O
P10
P11
P12
P13
P14
Bit 0 of Port1
PU*
(User-defined I/O)
Bit 1 of Port1
(K/B Data Input)
Bit 1 of Port1
31
32
33
35
I/O
PU*
(User-defined I/O)
Bit 2 of Port2
(Mouse Data Input)
Bit 2 of Port2
I/O
I/O
(User-defined I/O)
Bit 3 of Port1
(User-defined I/O)
Bit 3 of Port1
(User-defined I/O)
Bit 4 of Port1
(User-defined I/O)
Bit 4 of Port1
I
PU*
(RAM: RAM Jumper
Select)
(RAM: RAM Jumper
Select)
32
33
34
35
36
37
38
39
I
P15
P16
P17
P24
Bit 5 of Port1
(JUMP: Jumper)
Bit 5 of Port1
(JUMP: Jumper)
PU*
I
Bit 6 of Port1
(DISP: Display Select)
Bit 6 of Port1
(DISP: Display Select)
PU*
I
Bit 7 of Port1
Bit 7 of Port1
PU*
(KINH: K/B Inhibit Switch) (KINH: K/B Inhibit Switch)
O
Bit 4 of Port2
Bit 4 of Port2
(KINT: K/B OBF O/P
Interrupt)
(KINT: K/B OBF O/P
Interrupt)
36
40
O
P25
Bit 5 of Port2
Bit 5 of Port2
(IEMP: I/P Buffer Empty)
(MINT: Mouse OBF O/P
Interrupt)
37
38
41
42
O
O
P26
P27
Bit 6 of Port2
Bit 6 of Port2
(KCLK: K/B Clock Output) (KCLK: K/B Clock Output)
Bit 7 of Port2 Bit 7 of Port2
(KDAT: K/B Data Output) (KDAT: K/B Data Output)
39
40
43
44
I
T1
K/B Data Input
Mouse Clock Input
+5V Power Supply
-
Vcc
+5V Power Supply
* Internal pull-up resistor
- 4 -
W83C43
BLOCK DIAGRAM
TRANSMIT
CONTRROL
SCAN
CODE
ROM
T0
T1
RECEIVE
CONTROL
TRANSMIT
REGISTER
x1
x2
HARDWIRE
CONTROL &
SELECT
WR
RD
CS
STATUS
REGISTER
LOGIC
A2
RESET
P10
R64
STATUS
BUFFER
REGISTER
INPUT &
OUTPUT
P11
P12
P13
P14 (RAM)
P15 (JUMP)
P16 (DISP)
P17 (KINH)
PORT
DATA
BUFFER
REGISTER
W60
W64
INPUT
BUFFER
REGISTER
D0~D7
INTERFACE
OUTPUT
BUFFER
REGISTER
R60
P20 (RC)
P21 (GA20)
P22 (NC/MDAT)
P23 (NC/MCLK)
P24 (KINT)
OUTPUT
PORT
P25 (IEMP/MINT)
P26 (KCLK)
INTERFACE
P27 (KDAT)
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Ambient Operating Temperature
Storage Temperature
RATING
-0 to + 85
-65 to + 150
-0.3 to + 7.0
-0.3 to + 7.0
50
UNIT
°C
°C
Supply Voltage to Ground Potential
Applied Input/Output Voltage
Power Dissipation
V
V
mW
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Publication Release Date: January 1996
- 5 -
Revision A2
W83C43
ELECTRICAL CHARACTERISTICS & CAPACITANCE
(Ta = 0° C to + 70° C, VDD = +5V ± 5%)
SYMBOL
VDD
DESCRIPTION
Power Supply
MIN. TYP. MAX. UNIT
NOTE
4.75
5.0
5.25
0.8
V
V
VIL
Input Low Voltage (except RESET, T0,
T1)
VIL1
VIH1
Input Low Voltage (RESET, T0, T1)
0.6
V
V
Input High Voltage (except RESET, T0,
T1, P10, P11)
2.0
VIH2
VIH3
Input High Voltage (P10, P11)
3.0
3.5
V
V
V
Input High Voltage (T0, T1, RESET)
VOH1
2.4
2.4
IOH = -2
mA
Output High Voltage (P10- P13,
P20- P27)
VOH2
VOL1
V
V
IOH = -4
mA
Output High Voltage (D0- D7)
0.4
IOL = 2 mA
Output Low Voltage (P10- P13,
P20- P27)
VOL2
RIP
0.4
10K
-10
V
W
IOL = 4 mA
Output Low Voltage (D0- D7)
Min. I/P Resist
IOFL
10
10
O/P Leakage Current (D0- D7, High Z
State)
mA
IIH
IIL
I/P Leakage Current
-10
-10
-10
15
VDD = 5.5V,
VIN = VDD
mA
mA
mA
pF
I/P Leakage Current (Except P10, P11,
P14, P15, P16, P17)
10
VDD = 5.5V,
VIN = VSS
IIL1
CL
I/P Leakage Current (P10, P11, P14,
P15, P16, P17)
550
50
VDD = 5.5V,
VIN = VSS
O/P Load Capacity
STATUS REGISTER (AT MODE)
The status register is an 8-bit read-only register at I/O address hex 64 that holds information about the
status of the keyboard controller and interface. It may be read at any time.
BIT
BIT FUNCTION
Output Buffer Full
DESCRIPTION
0: Output buffer empty
0
1: Output buffer full
0: Input buffer empty
1: Input buffer full
1
Input Buffer Full
- 6 -
W83C43
Status Register (AT Mode), continued
BIT
BIT FUNCTION
DESCRIPTION
2
System Flag
This bit may be set to 0 or 1 by writing to the system
flag bit in the command byte of the keyboard controller.
It is set to 0 after a power-on reset
3
4
5
6
7
Command/data
Inhibit Switch
0: Data byte
1: Command byte
0: Keyboard is inhibited
1: Keyboard is not inhibited
0: No transmit time-out error
1: Transmit time-out error
0: No receive time-out error
1: Receive time-out error
0: Odd parity (no error)
1: Even parity (error)
Transmit Time-out
Receive Time-out
Parity Error
OUTPUT BUFFER
The output buffer is an 8-bit read-only register at I/O address hex 60. The keyboard controller uses
the output buffer to send the scan code received from the keyboard and data bytes required by
commands to the system. The output buffer should be read only when the output buffer full bit in the
register is 1.
ONPUT BUFFER
The input buffer is an 8-bit write-only register at I/O address hex 60 or 64. Writing to address hex 60
sets a flag that indicates a data write; writing to address hex 64 sets a flag that indicates a command
write. Data written to I/O address hex 60 are sent to the keyboard (unless the keyboard controller is
expecting a data byte) following the controller's input buffer only if the input buffer full bit in the status
register is set to 0.
(A) Input Port Definition (AT Mode)
BIT
0
FUNCTION
Undefined
1
Undefined
2
Undefined
3
Undefined
4
RAM on System Board
0: Disable second 256 KB of system board RAM
1: Enable second 256 KB of system board RAM
Publication Release Date: January 1996
Revision A2
- 7 -
W83C43
(A) Input Port Definition (AT Mode), continued
BIT
FUNCTION
Manufacturing Jumper Installed
0: Manufacturing jumper
1: Jumper not installed
5
6
7
Display Type Switch
0: Primary display attached to color/graphics
1: Primary display attached to monochrome
Keyboard Inhibit Switch
0: Keyboard inhibited
1: Keyboard not inhibited
(B) Output Port Definition (AT Mode)
BIT
FUNCTION
0
1
2
3
4
5
6
7
System Reset
Gate A20
Undefined
Undefined
Output Buffer Full
Input Buffer Empty
Keyboard Clock (Output)
Keyboard Data (Output)
(C) Test-input Port Definition (AT Mode)
BIT
FUNCTION
0
1
Keyboard Clock (Input)
Keyboard Data (Input)
Status Register (PS/2 Mode)
BIT
BIT FUNCTION
DESCRIPTION
0: Output buffer empty
0
Output Buffer Full
1: Output buffer full
1
2
Input Buffer Full
System Flag
0: Input buffer empty
1: Input buffer full
This bit may be set to 0 or 1 by writting to the system flag
bit in the command byte of the keyboard controller. It is
set to 0 after a power-on reset.
- 8 -
W83C43
Status Register (PS/2 Mode), continued
BIT
BIT FUNCTION
DESCRIPTION
3
Command/Data
0: Data byte
1: Command byte
4
5
6
7
Inhinit Switch
0: Keyboard is inhibited
1: Keyboard is not inhibited
Auxiliary Device Output 0: Auxiliary device output buffer empty
Buffer
1: Auxiliary device output buffer full
General Purpose Time-
out
0: No time-out error
1: Time-out error
Parity Error
0: Odd parity
1: Even parity (error)
Input Port Definition
BIT
0
FUNCTION
Keyboard Data Input
1
Mouse Data Input
Undefined
2
3
Undefined
4
RAM on System Board
0: Disable second 256 KB of system board RAM
1: Enable second 256 KB of system board RAM
5
6
7
Manufacturing Jumper
0: Manufacturing jumper
1: Jumper not installed
Display Type Switch
0: Primary display attached to color/graphics
1: Primary display attached to monochrome
Keyboard Input Switch
0: Keyboard inhibited
1: Keyboard not inhibited
Output Port Definition
BIT
0
FUNCTION
System Reset
1
Gate A20
2
Mouse Data Output
Mouse Clock Output
3
Publication Release Date: January 1996
Revision A2
- 9 -
W83C43
Output Port Definition, continued
BIT
4
FUNCTION
Keyboard Output Buffer Full Interrupt
5
Mouse Output Buffer Full Interrupt
Keyboard Clock Output
6
7
Keyboard Data Output
Test-input Port Definition
BIT
FUNCTION
0
1
Keyboard Clock Input
Mouse Clock Input
Commands (I/O Address HEX 64) (AT Mode)
COMMAND
FUNCTION
20
60
Read Command Byte of Keyboard Controller
Write Command Byte of Keyboard Controller
BIT
BIT DEFINITION
Reserved
7
6
IBM PC Compatible Mode
IBM PC Mode
5
4
3
2
1
Disable Keyboard
Inhibit Override
System Flag
Reserved
Enable Output Buffer Full Interrupt
0
AA
AB
Self-test
Interface Test
BIT
BIT DEFINITION
No Error Detected
00
01
K/B Clock Line is Stuck Low
K/B Clock Line is Stuck High
K/B Data Line is Stuck Low
K/B Data Line is Stuck High
02
03
04
AD
AE
Disable Keyboard Feature
Enable Keyboard Interface
- 10 -
W83C43
Commands (I/O Address HEX 64) (AT Mode), continued
COMMAND
FUNCTION
C0
D0
Read Input Port
Read Output Port
Write Output Port
Read Test Inputs
Pulse Output Port
D1
E0
F0-FF
Commands (I/O Address HEX 64) (PS/2 Mode)
COMMAND
FUNCTION
20
60
Read Command Byte of Keyboard Controller
Write Command Byte of Keyboard Controller
BIT
BIT DEFINITION
7
6
Reserved
IBM Keyboard Translate Mode
Disable Auxiliary Device
5
4
3
2
1
Disable Keyboard
Reserve
System Flag
Enable Auxiliary Interrupt
Enable Keyboard Interrupt
0
A7
A8
A9
Disable Auxiliary Device Interface
Enable Auxiliary Device Interface
Interface Test
BIT
BIT DEFINITION
No Error Detected
00
01
Auxiliary Device "Clock" line is stuck low
Auxiliary Device "Clock" line is stuck high
Auxiliary Device "Data" line is stuck low
02
03
04
Auxiliary Device "Data" line is stuck low
AA
Self-test
Publication Release Date: January 1996
Revision A2
- 11 -
W83C43
Commands (I/O Address HEX 64) (PS/2 Mode), continued
COMMAND
FUNCTION
AB
Interface Test
BIT DEFINITION
No Error Detected
BIT
00
01
02
03
04
Keyboard "Clock" line is stuck low
Keyboard "Clock" line is stuck high
Keyboard "Data" line is stuck low
Keyboard "Data" line is stuck high
AD
AE
C0
Disable Keyboard Interface
Enable Keyboard Interface
Read Input Port
C1
Poll Input Port Low
C2
Poll Input Port High
D0
Read Output Port
D1
Write Output Port
D2
Write Keyboard Output Buffer
Write Auxiliary Device Output Buffer
Write to Auxiliary Device
Read Test Inputs
D3
D4
E0
F0-FF
Pulse Output Port
AC TIMING
NO.
T1
T2
T3
T4
T5
T6
T7
T8
T9
DESCRIPTION
MIN.
0
MAX.
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
Address Setup Time from WRB
Address Setup Time from RDB
WRB Strobe Width
0
20
20
0
RDB Strobe Width
Address Hold Time from WRB
Address Hold Time from RDB
Data Setup Time
0
50
0
Data Hold Time
Gate Delay Time from WRB
10
30
- 12 -
W83C43
AC Timing, continued
NO.
DESCRIPTION
RDB to Drive Data Delay
RDB to Floating Data Delay
MIN.
MAX.
UNIT
nS
nS
mS
mS
mS
mS
mS
mS
mS
mS
mS
nS
mS
mS
mS
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
40
20
4
0
Data Valid After Clock Falling (SEND)
K/B Clock Period
20
10
4
K/B Clock Pulse Width
Data Valid Before Clock Falling (RECEIVE)
K/B ACK After Finish Receiving
RC Fast Reset Pulse Delay (8 MHz)
RC Pulse Width (8 MHz)
Transmit Timeout
20
2
3
2
6
Data Valid Hold Time
0
83
30
30
5
167
50
X1/X2 Period (6- 12 MHz)
Duration of CLK inactive
Duration of CLK active
50
Time from inactive CLK transition, used to time when
the auxiliary device sample DATA
25
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
Time of inhibit mode
100
5
300
T28-5
50
mS
mS
mS
mS
mS
Time from rising edge of CLK to DATA transition
Duration of CLK inactive
30
30
5
Duration of CLK active
50
Time from DATA transition to falling edge of CLK
Mode detect signal after P10 goes high
High pulse of mode detect signal
Low pulse of mode detect signal
25
Typical 1 mS
Typical 220 mS
Typical 220 mS
Typical 1 mS
Typical 64 mS
Mode detect signal after RESET goes high
Time out of AT mode‘ s mode detect signal
Publication Release Date: January 1996
Revision A2
- 13 -
W83C43
TIMING WAVEFORMS
Write Cycle Timing
A2, CSB
WRB
T1
T5
T3
ACTIVE
T7
T8
D0~D7
DATA IN
T9
GA20
OUTPUT PORT
T17
T18
FAST RESET PULSE RC
FE COMMAND
Read Cycle Timing
A2,CSB
AEN
T2
T6
T4
RDB
ACTIVE
T10
T11
D0-D7
DATA OUT
Send Data to K/B
CLOCK
(KCLK)
T12
T13
D4
T16
T14
SERIAL DATA
D5
D1
START
D2
D3
D0
D6
D7
P
STOP
(KDAT)
T19
- 14 -
W83C43
Receive Data from K/B
CLOCK
(KCLK)
T14
T13
T15
SERIAL DATA
(T1)
D5
START
T20
D1
D2
D3
D4
D0
D6
D7
P
STOP
X1/X2 Clock
CLCOLCOKCK
T21
Send Data to Mouse
MCLK
T25
T23
T24
T22
MDAT
START
Bit
D5
D1
D2
D3
D4
D0
D6
D7
P
STOP
Bit
Receive Data from Mouse
MCLK
T29
T26
D1
T27
T28
D3
MDAT
D5
START
D2
D4
D0
D6
D7
P
STOP
Bit
Publication Release Date: January 1996
Revision A2
- 15 -
W83C43
PS2 Mode's Mode Detect
(P10 released to high by keyboard before RESET goes high)
RESET
P27
T31
T33
P10
T32
PS2 Mode's Mode Detect
(P10 released to high by keyboard after RESET goes high)
RESET
P27
T31
T30
P10
T32
AT Mode's Mode Detect
(P10 internal pull high. As there is no external loop between P27 and P10 so P27 issues pulse until
time out )
RESET
P27
T34
T31
T32
T33
P10
- 16 -
W83C43
TYPICAL APPLICATION CIRCUITS
Application for AT Mode
2
3
40
25
Vcc
Vcc
X1
X2
27
28
29
30
31
32
33
34
P10
P11
P12
P13
P14
P15
P16
P17
4
1
39
9
6
5
8
10
RESETB
RESET
T0
T1
RAM SELECT JUMPER
MANUFACTURING MODE JUMPER
A2
SA2
CS
Vcc
RD
8042CS#
IORD#
IOWR#
21
22
23
24
35
36
P20
P21
P22
P23
WR
RCB
GATE20
12
13
14
15
16
17
18
19
D0
D1
Vcc
KEYBOARD INTERRUPT
P24/OB
P25
P26/KCLK
P27/KDAT
D2
D3
D4
D5
D6
D7
37
38
11
26
NC
NC
D[0..7]
7
20
GND
GND
7407
1
2
1
1
2
2
KB8042-DIP
KEYBOARD CLOCK
74ALS04
7407
KEYBOARD DATA
Publication Release Date: January 1996
Revision A2
- 17 -
W83C43
Application for PS/2 Mode
KEYBOARD INTERRUPT
PS/2 MOUSE INTERRUPT
2
40
25
X1
Vcc
Vcc
3
27
X2
P10
P11
P12
P13
P14
P15
P16
P17
28
29
30
31
32
33
34
4
1
39
9
6
5
RESET
T0
T1
RESETB
RAM SELECT JUMPER
MANUFACTURING MODE JUMPER
A2
SA2
8042CS#
CS
Vcc
RD
WR
8
10
IORD#
IOWR#
21
22
23
24
35
36
37
38
P20
P21
P22
P23
P24/OB
P25
P26/KCLK
P27/KDAT
RCB
GATE20
Vcc
12
13
14
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
11
26
PS/2 MOUSE DATA
7406
1
NC
NC
D[0..7]
2
2
7
20
GND
GND
KB8042-DIP
PS/2 MOUSE CLOCK
7406
1
Vcc
7406
1
1
2
2
KEYBOARD CLOCK
KEYBOARD DATA
7406
- 18 -
W83C43
Driving from External Source
OPTION 1
2
3
X1
X2
PCLK
1
2
OPTION 2
PCLK
2
3
1
2
X1
X2
N.C.
+5V
OPTION 3
470
470
PCLK
2
3
1
2
1
1
2
2
X1
X2
7404
7407
7407
Publication Release Date: January 1996
Revision A2
- 19 -
W83C43
PACKAGE DIMENSIONS
40-pin DIP
Dimension in inch
Dimension in mm
Symbol
A
Nom.
Nom.
Min.
Max. Min.
0.210
Max.
5.33
0.010
0.25
1
A
0.155
0.018
0.050
0.010
2.055
0.160
0.022
0.054
0.014
2.070
0.610
0.150
0.016
3.81
0.41
1.22
0.20
3.94
0.46
1.27
0.25
52.20
4.06
0.56
A
2
B
1.37
0.048
0.008
1
B
c
0.36
52.58
15.49
13.97
2.79
D
E
D
15.24
13.84
0.590 0.600
14.99
13.72
40
21
0.540
0.090
0.120
0
0.545
0.100
0.550
0.110
1
E
2.29
3.05
2.54
3.30
e1
0.140
15
0.130
3.56
15
L
a
1
0
E
17.02
0.630 0.650
0.670
16.00
16.51
A
e
S
0.090
2.29
Notes:
1
20
1. Dimensions D Max & S include mold flash or
tie bar burrs.
E
S
2. Dimension E1 does not include interlead flash.
c
2
1
A
3. Dimensions D & E1 include mold mismatch and
A
A
L
.
Base Plane
are determined at the mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
Seating Plane
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
B
e1
eA
a
B 1
44-pin PLCC
H D
D
1
Dimension in inch
Min. Nom. Max. Min. Nom. Max.
Dimension in mm
6
44
40
Symbol
A
0.185
4.70
7
39
0.020
0.145
0.51
1
A
2
A
0.150
3.81
0.71
0.155 3.68
0.032 0.66
3.94
0.81
0.026 0.028
0.016
1
b
b
c
D
E
e
0.018 0.022
0.46 0.56
E
H
0.41
E
G
E
0.008 0.010 0.014 0.20 0.25
16.46 16.59 16.71
0.36
0.648 0.653 0.658
16.59
0.653
16.46
16.71
1.27 BSC
0.648
0.658
BSC
0.050
0.590
0.590
0.680
0.680
14.99
16.00
15.49
0.630
0.610
D
G
G
H
17
29
16.00
14.99 15.49
0.610 0.630
E
17.27
0.700
17.53 17.78
0.690
0.690 0.700
D
18
28
c
17.27 17.53 17.78
HE
0.090 0.100
2.54 2.79
0.10
0.110 2.29
0.004
L
y
L
Notes:
2
A
1. Dimensions D & E do not include interlead
flash.
A
2. Dimension b1 does not include dambar
protrusion/intrusion
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
1
A
e
b
y
b1
Seating Plane
G D
- 20 -
W83C43
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792646
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27516023
FAX: 852-27552064
2730 Orchard Parkway, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
Publication Release Date: January 1996
Revision A2
- 21 -
相关型号：
W83C553F-G
W83C553F-G Highly Integrated System I/O Controller for Power PCTM (South Bridge) QFP 208
ETC
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