W93910_技术文档

W93910

ERMES PAGING DECODER

GENERAL DESCRIPTION

The W93910 is a low-power ERMES (Enhanced Radio MEssage System) paging protocol decoder

using a single 100 kHz crystal. The W93910 supports individual call, group call, long message,

changing character set and remote programming functions. To enhance the sensitivity of the pager

system, a digital filter and DPLL are incorporated to remove noise and lock the signal. For convenient

pager programming, the W93910 provides fully software-programmable options and also offers an

independent LED frequency output.

With built-in flexible RF power saving control, frequency synthesizer enable control, quick charge

controls, as well as automatic channel scan algorithm, the W93910 can combine with different RF

receivers to construct a high performance, low power dissipation pager system.

FEATURES

· 100 kHz crystal

· Built-in digital filter and digital phase lock loop

· Built-in two addresses concurrently

· One remote programming address

· International roaming capability

· Automatic channel scan algorithm

· Built in de-interleaving circuit

· 2-bit random error correction

· Individual call, long message, changing character set and remote programming

· CTAP group call

m

· Serial interface with C

· 2-bit signal input from RF receiver

· RF and frequency synthesizer power saving control available

· Quick charge-discharge timing control

· Provides LED output

· 2.5 to 3.5 volts operating voltage range

· Packaged in 28-pin SSOP

Publication Release Date: Auguest 1999

Revision A1

- 1 -

W93910

PIN CONFIGURATION

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

OSCI

OSCO

GND

VDD

2

LEDO

3

TEST2

TEST1

ENLED

MCLK

4

TCTL2

D0

5

6

D1

7

QC2

MDATA

MSGVAL

ADRDET

SYNVAL

XCNCG

CHRS

8

TCTL1

QC1

9

10

11

12

13

14

RFEN

PLEN

TXCLK

TXDATA

ON

PTEST

XRST

PIN DESCRIPTION

SYMBOL

OSCI

OSCO

GND

TCTL2

D0

1

I/O

I

PIN DESCRIPTION

100 kHz crystal input.

100 kHz crystal output.

Ground power.

2

O

I

3

4

O

I

RF control pin. Inversion output of QC2.

Demodulated data input bit0(LSB).

Demodulated data input bit1(MSB).

5

D1

6

I

QC2

7

O

Receiver quick charge 2 signal enable. Active high/low is dependent

on QC2L option bit.

TCTL1

QC1

8

9

O

RF control pin.

Receiver quick charge 1 signal enable. Active high/low is dependent

on QC1L option bit.

RFEN

PLEN

10

11

O

Receiver power control. Active high/low is dependent on RFENL option

bit.

PLL frequency synthesizer power control. Active high/low depends on

m

PLENL option bit. C must program the freq. synthesizer counter while

PLEN inactive. W93910 internal channel will be decided during PLEN

active edge.

- 2 -

W93910

Pin Description, continued

SYMBOL

I/O

PIN DESCRIPTION

TXCLK

12

I

m

192 option bits clock input from C. TXDATA will be latched by

W93910 during TXCLK rising edge.

TXDATA

ON

13

14

I/O

I

m

192 option bits serial data input from C. Option bit address will be

increased by one after each TXCLK period. After 192 option setting,

the TXDATA pin will change to output pin for received OPID

information access.

Active high to enable W93910 chip operating. Oscillator starts

oscillation after ON rising edge. OSCO will always stop while ON is

low.

XRST

PTEST

CHRS

15

16

17

I

Internal pull low, Active high to reset decoder.

Internal pull low, Test mode only.

Force roaming control pin. Connect to GND for normal operation. Pull

high is only for test purpose.

XCNCG

18

O

During PLEN pin high level, XCNCG (eXternal ChaNnel ChanGe)

rising edge will inform mC to change channel according to channel

scanning rule.

19

20

21

22

O

Synchronization Indicator (out-of-range indicator output). Output low

when synchronized with paging system.

SYNVAL

ADRDET

Active high while the user IA detected in the address partition.

(normally Low)

MSGVAL

MDATA

MSGVAL will be active during MCLK, MDATA available period. Active

high/low is dependent on MSGI option bit.

m

Serial paging message output to C. Rising/falling edge is dependent

-

on MCKEG option bit. UDI1 0 used to select interval per bytes

MDATA.

MCLK

23

O

m

Serial clock output to C for available paging message. MCKI used to

select initial state, and MCK1, MCK0 used to select clock rate.

Internal pull low, Active high to enable LEDO output.

Test only. No connection for normal operation

10/4 kHz or 40/16 kHz CMOS clock output.

3 volts power supply.

ENLED

TEST1

TEST2

LEDO

24

25

26

27

28

I

O

I

DD

V

Publication Release Date: Auguest 1999

- 3 -

Revision A1

W93910

BLOCK DIAGRAM

PTEST

VDD

XRST

GND

TXCLK

D0

DATA INPUT

FILTER & PLL

128 OPTIONS

BITS

TXDATA

D1

MAIN

CONTROL

CIRCUIT &

ERROR

AIR PROGRAMMING

REGISTER

OSCI

OSCILLATOR

CORRECTION

OSCO

MSGVAL

MDATA

MCLK

DATA OUTPUT

BUFFER &

CONTROL

TIME OUT

CONTROL

ADRDET

RFEN

PLEN

QC1

LEDO

CHANNEL

STATUS

CONTROL

RECEIVEING

ENABLE

CONTROL

LED & ALERT

TYPE CONTROL

ENLED

QC2

TEST2 TEST1

TCTL1 TCTL2 ON

SYNVAL CHRS XCNCG

- 4 -

W93910

ADDRESS & OPTION LIST

BIT NO. DATA BIT NO. DATA BIT NO. DATA BIT NO. DATA BIT NO. DATA BIT NO. DATA

b0

b1

0

b32

b33

b34

b35

b36

b37

b38

b39

b40

b41

b42

b43

b44

b45

b46

b47

b48

b49

b50

b51

b52

b53

b54

b55

b56

b57

b58

b59

b60

b61

b62

b63

FILT1

GIA17

GIA16

GIA15

GIA14

GIA13

GIA12

GIA11

GIA10

GIA9

GIA8

GIA7

GIA6

GIA5

GIA4

GIA3

GIA2

GIA1

GIA0

CH3

b64

b65

b66

b67

b68

b69

b70

b71

b72

b73

b74

b75

b76

b77

b78

b79

b80

b81

b82

b83

b84

b85

b86

b87

b88

b89

b90

b91

b92

b93

b94

b95

1

ZC2

ZC1

ZC0

CC6

CC5

CC4

CC3

CC2

CC1

CC0

OP2

OP1

OP0

FSN3

FSN2

FSN1

FSN0

0

b96

b97

SIEN

b128

1

b160

1

QCON0

IA17

IA16

IA15

IA14

IA13

IA12

IA11

IA10

IA9

b129 RPIA17 b161 RPZC2

b130 RPIA16 b162 RPZC1

b131 RPIA15 b163 RPZC0

b132 RPIA14 b164 RPCC6

b2

b98

RFON

PL1

b3

b99

b4

b100

PL0

b5

b101 GIAEN b133 RPIA13 b165 RPCC5

b102 PAEN b134 RPIA12 b166 RPCC4

b103 GPAEN b135 RPIA11 b167 RPCC3

b6

b7

b8

b104

b105

MCKI

MDAI

b136 RPIA10 b168 RPCC2

b9

b137

RPIA9 b169 RPCC1

RPIA8 b170 RPCC0

RPIA7 b171 RPOP2

RPIA6 b172 RPOP1

RPIA5 b173 RPOP0

b10

b11

b12

b13

b14

b15

b16

b17

b18

b19

b20

b21

b22

b23

b24

b25

b26

b27

b28

b29

b30

b31

IA8

b106 MCKEG b138

b107 RFENL b139

b108 PLENL b140

IA7

IA6

IA5

b109

b110

b111

b112

b113

b114

b115

b116

b117

b118

b119

b120

b121

b122

b123

b124

b125

b126

b127

QC1L

QC2L

D0IV

b141

b142

b143

b144

b145

b146

b147

b148

b149

b150

IA4

RPIA5 b174

RPIA3 b175

RPIA2 b176

RPIA1 b177

RPIA0 b178

RSVD

0

IA3

IA2

D1IV

IA1

MCK1

MCK0

LKR1

LKR0

0

IA0

BN3

BN2

BN1

BN0

PA5

PA4

PA3

PA2

PA1

PA0

0

1

RPI

b179

b180

b181

b182

CH2

0

RSVD

CH1

1

CH0

1

LEDF

MSGI

UDI1

UDI0

QC1WTH

GPA5

GPA4

GPA3

0

b151 RPPA5 b183

b152 RPPA4 b184

b153 RPPA3 b185

b154 RPPA2 b186

b155 RPPA1 b187

b156 RPPA0 b188

0

GPA2

GPA1

GPA0

LPWR

QCON1

0

b157

b158

b159

RSVD

0

b189

b190

b191

0

Table 1

Publication Release Date: Auguest 1999

Revision A1

- 5 -

W93910

192 OPTION BITS

Detailed description given in Function Description section.

RIC format

-

IA17 IA0: Basic RIC initial address

-

BN3 BN0: Basic RIC batch number A(0000) P(1111)

-

PA5 PA0: Basic RIC paging area code (000000 111111)

PAEN: Enable PA5- PA0 while PAEN active

-

GIA17 GIA0: Second RIC initial address

-

CH3 CH0: Home channel initial value from Channel 0 (0000) Channel F (1111)

-

GPA5 GPA0: Second RIC paging area code (000000 111111)

-

GPAEN: Enable GPA5 GPA0 while GPAEN active

-

GIAEN: Enable GIA17 GIA0 initial address

-

ZC2 ZC0: Receiver zone code

CC6- CC0: Receiver country code

-

OP2 OP0: Receiver operator code

-

FSN3 FSN0: Frequency subset number (0000 1111)

-

RPIA17 RPIA0: Remote programming initial address

-

RPPA5 RPPA0: Remote programming paging area code (000000 111111)

-

RPZC2 RPZC0: Remote programming zone code

-

RPCC6 RPCC0: Remote programming country code

RPOP2- RPOP0: Remote programming operation code

RPI: Remote programming index

RF Interface:

RFENL: RFEN pin active level option bit

PLENL: PLEN pin active level option bit

QC1L: QC1 active level option bit

QC2L: QC2 active level option bit

D0IV: D0 input polarity option bit

D1IV: D1 input polarity option bit

-

PL1 0, RFON, QCON1 0, QC1WTH: RFEN, PLEN, QC1 and QC2 active timing control bits.

uC Interface:

MSGI, MCKI, MDA I: MSGVAL, MCLK, MDATA pin initial state option bit

MCKEG: MCLK active edge;

-

MCK1 MCK0: MCLK output clock option bits

-

UDI1 0: MCLK stop clock option

LEDF: LED freq. output selection(1:10/40 kHz; 0:4/16 kHz)

Others:

-

LKR1 LKR0: SYNC lost hold time option

SIEN: System information output enable option

LPWR: Power saving option

FILT1: Digital filter option

- 6 -

W93910

FUNCTION DESCRIPTION

The W93910 ERMES paging decoder can be used to easily construct an ERMES pager with RF

m

receiver and C. To initialize the decoder, first, 192 option bits must be programmed through TXCLK,

m

TXDATA pin by C. After the oscillator has been turned on and is stable, the decoder can then receive

and decode the 2 bit digital QFSK signal from the RF receiver. With built-in PLEN, RFEN, QC1 and QC2

controls, the decoder can warm up and shut down the frequency synthesizer and IF demodulator for

optimum reception in different stages.

While starting, the pager will begin to search the home channel. If system synchronization can't occur in

the current channel, the pager will change to the next channel according to the channel scan algorithm

until synchronization occurs. Once synchronized with the channel, the pager will lock to its own batch,

ready to receive paging message. If an address-matched message is received, the de-interleaved data

m

will be transferred to C through MDATA and MCLK pin. With the automatic channel scan algorithm, the

decoder will inform mC by PLEN and XCNCG to change channel during channel scan and normal

mode.

RECEIVING OPERATION FLOW

Power on

and XREST

192 options

setting

ON

Oscillator stable

CHANNEL

SCANNING MODE

IDLE MODE

SYNC MODE

LOCK MODE NORMAL MODE

Figure 1. Operating Flow Chart

Publication Release Date: Auguest 1999

- 7 -

Revision A1

W93910

192 OPTION BITS PROGRAMMING

m

After power on and XRST pin active, the C should send 192 clock inputs to TXCLK pin and 192 options

to TXDATA pin. Figure 2 shows the TXCLK and TXDATA programming timing. The data values in

TXDATA are latched at TXCLK rising edge. The clock rate of TXCLK should be smaller than 1 MHz.

Txrst

XRST

Ttdst

TXCLK

......

Ttdhd

Ttxck

TXDATA

PLEN

b1

......

b190

b191

b0

b189

Low

Ton

ON

OSCO

Tosc

Figure 2. 192 option bits programming timing

RECEIVING ENABLE CONTROL

After the W93910 has received the 192 options, it will start the operation if the ON pin is high, or in

stand-by mode if ON pin is low. The On pin can be pulled high at any time to activate the oscillator. After

oscillator is stable, the decoder will activate the PLEN. RFEN, QC1, QC2, TCTL1, and TCTL2 to control

the frequency synthesizer and IF demodulator, based on the option setting as shown in Figure 3. The

frequency synthesizer need to be programmed to the right channel (normally home channel) before

m

PLEN active. The PLEN is used to control the frequency synthesizer power, and inform C of the

receiving status. The output levels of RFEN, PLEN, QC1 and QC2 are defined by the option bits RFENL,

PLENL, QC1L and QC2L as shown in Table 2. TCTL2 is the inversion output of QC2. The TCTL1 active

level is fixed. The TCTL1 and TCTL2 output will be activated only when the LEDF option bit is set to 1.

-

Option bit PL1 0, RFON, QCON1 0 and QC1WTH provides different set up time for PLEN, RFEN,

QC1, QC2, TCTL1 and TCTL2, as shown in Table 3, to meet different RF receiver requirements.

- 8 -

W93910

PLEN

RFEN

Tqc1w

QC1

TCTL1

QC2

TCTL2

Tplst

Batch n

High

Batch n+1

Trfdy

ON

(While RFENL, PLENL, QC1L and QC2L are "0")

Figure 3. PLEN, RFEN, QC1, QC2, TCTL1 and TCTL2 timing

OPTION BIT

FUNCTION

RFENL, PLEN, QC1L, QC2L

RFEN, PLEN, QC1, and QC2 pin voltage level

0

1

Active high

Active low

Table 2. RF interface active option bits

OPTION BIT

FUNCTION

Tplst setting

9.6 mS

PL1

0

PL0

0

1

19.2 mS

1

0

28.8 mS

1

Reserved

Table 3. PLL enable timing

Publication Release Date: Auguest 1999

Revision A1

- 9 -

W93910

OPTION BIT

FUNCTION

Trfdy

RFON

0

1

4.8 mS

9.6 mS

Table 4. RF interface timing control option bit

OPTION BIT

FUNCTION

Tqc1w

QC1WTH

0

1

3.8 mS

2.5 mS

Table 5. Quick-charge duration option bit

OPTION BIT

FUNCTION

QCON1

QCON0

QC1 duration

QC2 duration

1

0

1

Tplst + Trfdy + Tqc1w

Trfdy + Tqc1w

Tqc1w

Tplst + Trfdy + 9.6ms

Trfdy + 9.6ms

9.6 ms

Table 6. Quick-charge active timing control option bits

CHANNEL SCAN MODE

In this mode, decoder will enable the receiver to search the available channel in different frequency

channels based on the channel scan control algorithm.

...

RFEN

...

XCNCG

+

Home channel 2

CHANNEL NO

Home channel

Change channel

Figure 4. Channel Scan Mode

- 10 -

W93910

CHANNEL SCAN CONTROL

The channel scanning and switching are controlled by the decoder. Table 7 shows the channel number

and frequency. In channel scan mode, the decoder will first search the home channel, defined by the

-

CH3 CH0. Therefore, the synthesizer should be programmed to home channel before the channel

scan mode. If the pager can not detect a valid signal in the home channel, the pager will change to the

next channel to search until the decoder lock to the signal. The scanning sequence is shown in Figure 5,

and needs to be followed to avoid losing signal.

OPTION BIT

FUNCTION

Home channel number

RF center frequency

169.425 MHz

169.475 MHz

169.525 MHz

169.575 MHz

169.625 MHz

169.675 MHz

169.725 MHz

169.775 MHz

169.800 MHz

169.750 MHz

169.700 MHz

169.650 MHz

169.600 MHz

169.550 MHz

169.500 MHz

169.450 MHz

-

CH3 CH0

0000

0010

0100

0110

1000

1010

1100

1110

1111

1101

1011

1001

0111

0101

0011

0001

0

2

4

6

8

A

C

E

F

D

B

9

7

5

3

1

Table 7. Channel number and frequency

Ch 0

Ch 2

Ch A

Ch C

Ch 3

Ch 1

Figure 5. Channel scan sequence

Publication Release Date: Auguest 1999

Revision A1

- 11 -

W93910

m

The frequency channel adjustment is implemented by XCNCG, PLEN, and C. XCNCG is used to

m

output a high pulse to inform C of the frequency channel increment request. C needs to count the

XCNCG high pulse during the PLEN active period. Each XCNCG pulse indicates one frequency channel

m

increment. During the PLEN inactive period, the C should program the synthesizer with suitable data

based on the previous XCNCG counting result to ensure the receiver can catch the right channel.

During the lock mode, the pager will fix at the same channel as shown in Figure 6 and 7. The normal

mode operation is described in Figure 8 and 9. The batch number setting is shown in Table 8.

OPTION BIT

FUNCTION

Batch Number

-

bn3 bn0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Table 8. bn3 bn0 batch number format

-

IDLE MODE

If there is no meaningful signal after scanning the channel several times, the decoder will enter idle

mode to save power, and will re-enter the channel scan mode after a period of time.

SYNC MODE

SYNVAL

While synchronizing with the paging system, the decoder enters sync mode and the

outputs LOW The decoder will then change to lock mode or normal mode based on the receiving

information.

- 12 -

W93910

LOCK MODE

In lock mode, the decoder will stay at the same channel. If matching addresses appear, all the available

paging messages will be received until messages are finished or time out occurs.

PLEN

receiving message

no message

Figure 6. Lock Mode

Status

Lock mode

Top

Channel scanning mode

Lock mode

ON

PLEN

XCNCG

Txcncg:XCNCG pulse

9 7

due to XCNCG rising

uC

internal

channel

5

7

9

7

3

9

Tpll:uC change frequency synthesizer counter

PLL freq.

synthesizer

channel

7

5

9

7

due to PLEN active edge

Decoder

channel

9

7

5

9

7

The above example shows the home channel of the pager is

channel 9 (CH3-CH0 = 1001) and pager locks to channel 7.

Figure 7. Channel Scan mode and lock mode

Publication Release Date: Auguest 1999

Revision A1

- 13 -

W93910

NORMAL MODE (NON-LOCK)

Decoder will enter normal mode while not in the home network or the border area indication condition.

In this mode, the decoder will switch and listen to different frequency channel based on the channel

scan control algorithm. The PLEN operating timing is shown in Figure 8.

PLEN

Batch A of Batch A of

channel 2 channel 4

Batch A of

channel 6

Batch A of

channel 1

Batch A of

channel 0

Status

The batch number is set to batch A

Figure 8. Normal Mode

High

ON

PLEN

XCNCG

uc

internal

channel

2

4

6

8

A

C

E

F

E

D

B

9

PLL freq.

synthesizer

channel

6

C

B

4

Decoder

channel

2

4

6

A

C

E

B

Notes:

1. uC need to count the number of XCNCG pulse during the PLEN active

period, and program the synthesizer with suitable data during the

PLEN inactive period.

2. PLEN will be the dash line if there is no paging message.

Figure 9. Channel scan in NORMAL MODE

- 14 -

W93910

LOST SYNCHCONIZATION

If synchronization is lost for several minutes (pre-defined by option bit LKR1 LKR0 ), the pager will

SYNVAL

-

change to the channel scan mode. The

pin will keep low during the lock mode and normal

SYNVAL

mode unless the synchronization lost duration exceeds the hold time condition, then the

will change to high level and the decoder will go back to the channel scan mode.

OPTION BIT

FUNCTION

LKR1

LKR0

Synchronization lost hold time

0

1

0

1

0

1

1 min.

2 min.

3 min.

4 min.

Table 9. Lock re-try option bits

RIC (Radio Identify Code) FORMAT

For ERMES system, RIC has 35 bits and is defined by ZC2 ZC0, CC6 CC0, OP2 OP0, IA17 IA0, and

-

BN3 BN0 option bits as shown in Table 10.

Radio Identify Code

Function

OPID

LOCAL ADDRESS

Zone Code Country Code Operator Code Initial Address Batch Number Paging area

OPTION

bit

-

PA5 PA0

ZC2 ZC0

CC6 CC0

OP2 OP0

IA17 IA0

BN3 BN0

-

GPA5 GPA0

GIA17 GIA0

Table 10. RIC format

-

The W93910 provides two initial addresses with corresponding paging area code, IA17 IA0 with

-

PA5 PA0 and GIA17 GIA0 with GPA5 GPA0, for the same OPID. The first one is dedicated for the

-

basic RIC. Each pager has one unique batch number, defined by BN3 BN0, and will only turn on and

listen at that specific batch except where a message continues over one batch. If PAEN option bit is set

-

to "1", the received message must match to the pre--defined paging area code, PA5 PA0. Other than in

-

this situation, the received paging area code doesn't need to match the pre-defined PA5 PA0, but must

-

be consistent throughout the whole message. The second IA, GIA17 GIA0, is enabled by setting the

-

GIAEN option bit to 1. GPAEN has the same function as PAEN, but for GIA17 GIA0 address only.

OPTION BIT

FUNCTION

Second user address (GPA+GIA)

Disable

GIAEN

0

1

Enable

Table 11-1. Second initial address setting option bits

Publication Release Date: Auguest 1999

Revision A1

- 15 -

W93910

OPTION

FUNCTION

PAEN, GPAEN

PA5- PA0, GPA5- GPA0

Don't care

0

1

Enable

Table 11-2. Paging area setting

REMOTE PROGRAMMING

The W93910 provides remote programming addresses including initial address, paging area, zone

code, and country code to support the remote programming function. These option bits are listed in

Table 12. These temporary addresses can be programmed during the initial setting or modified by the

air message. While receiving the remote programming address message, W93910 will automatic

m

C

update the internal remote programming addresses and also pass the programming message to

through MDATA pin. The data should be stored for re-initialization purpose. Please refer to Summary of

Data Output Format. If the remote programming data is less than 18 bits, the dummy "0" is filled in the

-

other low bits of rd17 rd0. For the first time initialization, all the option bits should be "0" including the

RPI. The RPI is the remote programming index, which can be read out from MDW while receiving the

remote programming message.

OPTION BIT

FUNCTION

Initial Address

-

RPIA17 RPIA0

Paging Area

-

RPPA5 RPPA0

Zone Code

-

RPZC2 RPZC0

Country Code

-

RPCC6 RPCC0

Operator Code

Remote Programming Index

-

RPOP2 RPOP0

RPI

Table 12. Remote programming register

SYSTEM INFORMATION

By setting the SIEN option bit to 1, the system information can also be read out from TXDATA pin. After

m

192 option bits setting, if the C decides to read out the received system information, the C needs to

send 31 clocks to TXCLK pin. The first clock pulse will switch TXDATA pin from input to output, and the

last clock pulse will disable this function. At the falling edge of the each clock pulse except the first and

last clock one, the system information (batch no, country code, operator code, cycle no., hour) can be

read out from the TXDATA pin. The best timing to read out the system information is right after PLEN

falling edge. The format and timing are shown in Figure 10. This function is disabled if SIEN is set to 0.

- 16 -

W93910

TXCLK

TXDATA

Start Batch3-0

CC6-0

Op2-0

Cycle No5-0

Hour4-0 Reserved Stop

Figure 10. System information read out format

DATA INPUT

The 4 level FSK signal is converted to 2 bit digital signal by IF demodulator, as shown in Figure 11,

where fn is the carrier frequency from 169.425 MHz to 169.8 MHz. The 2 bit digital signal should be

connected to the D1(MSB), D0(LSB) inputs of W93910. The D1 and D0 inputs could be inverted by

setting the D1IV, and D0IV option bits to provide some flexibility.

OPTION BIT

FUNCTION

D1 input, D0 input

Non-inversion

Inversion

D1IV, D0IV

0

1

Table 13. D1, D0 relative option bits

10

(fn-4687.5Hz)

11

(fn-1562.5Hz)

01

(fn+1562.5Hz)

00

(fn+4687.5Hz)

D1

D0

:

0

1

0

1

0

1

0

1

0

Figure 11. 4 PAM mapping to D1, D0(fn is the channel carrier frequency)

Publication Release Date: Auguest 1999

Revision A1

- 17 -

W93910

DIGITAL FILTER & POWER SAVING

The W93910 provides different digital filter to remove the noise of the 4FSK signal. The enhanced

filtering require higher power consumption. Table 14 shows different combinations of digital filtering and

power saving.

OPTION BIT

FUNCTION

FILT1

LPWR

Digital filter & power saving

0

1

0

1

Low power consumption, normal filtering

Enhanced filtering, high power consumption

Table 14. Digital filter and power saving option

DE-INTERLEAVER AND ERROR CORRECTION

The W93910 performs 2 bits random error correction for system information, address partition as well

as message partition, and codeword de-interleaving for message partition.

TIME OUT CONTROL

When the decoder recognizes a valid initial address it will start to search the associated paging

message. Time out criteria will stop message searching at once. While the searching is stopped due to

time out issue, the "epa" and "etm" in EDW format will be set to indicated the time out situation. At the

mean time, the RF control signal will become inactive at once when ending message delimiter (MD) has

been detected.

For Individual calls

·

Two time out criteria shall apply. The earliest detected shall prevail:

-

1. If PA5 PA0 in paging message is not consistent throughout the receiving, then the epa flag will be

set to "1".

2. If the paging message lasts more than 12 sec, then etm flag will be set to "1".

For group calls

·

Individual member shall cease message search if:

-

1. If PA5 PA0 in paging message is not consistent throughout the receiving, then the epa flag will be

set to "1".

2. If the paging message lasts more than 12 sec, then etm flag will be set to "1".

For long message calls

·

The time out criteria for each sub-message is the same as for individual call. The time out of the whole

long message should be proceeded by the software to meet the ERMES protocol.

- 18 -

W93910

DATA OUTPUT CONTROL

When the chip detects the proper address, the chip will first activate ADRVAL pin to inform the C and

m

then send the de-interleaved paging message and related system information to the C through MCLK

and MDATA pin. The format and timing of the data output is shown in Figure 12. The data output is

Function Code,

packed into a 3-byte word format. The function of each word is defined by the

the first

4 bits of byte3, as shown in Table 15. The format of the rest 20 bits will depend on the function code.

HIGH NIBBLE OF BYTE 3

FUNCTION CODE

System Information Word (SIW)

ComMand Word (CMW)

Addition Information Word (AIW)

Message data Word (MDW)

EnD message Word (EDW)

RESERVED

0000

0010

010x

0110

1110

Others

Table 15. Data Output Function Code

Publication Release Date: Auguest 1999

Revision A1

- 19 -

W93910

ADRDET

MSGVAL

Taddt

Message 1

AIW

Message 2

Tint

MDATA

MCLK

Tmsgv

MDW0

SIW

CMW

EDW

SIW

EDW

Tudi

D23-17

byte3

D15-D8

byte2

D7-D0

byte 1

D23-17

MDATA

MCLK

Tint

(MCKEG=1)

Tunit

MCKI=0

....

MDATA

D23 D22

Tmdst

D17

D16 D15

D8

....

MCLK

(MCKEG=1)

Tmclk

....

MCLK

(MCKEG=0)

MCKI=1

....

D23 D22

D17

D15

....

D8

D16

MDATA

Tmclk

....

MCLK

(MCKEG=1)

Tmclk

....

MCLK

(MCKEG=0)

Figure 12. Data Output Timing

- 20 -

W93910

-

Table 16 Table 19 list the active level and timing option bit settings of the data output format. MCLK

-

clock rate is defined by option bit MCK1 0. The duration between each word, Tint, and the duration

-

between each byte, Tudi, are defined by option bit UDI1 UDI0. Option bit MCKEG defines MCLK active

edge. MCKI, MSGI and MDAI option bits set MCLK, MSGVAL and MDATA pin initial and active state.

The output sequence of MDATA pin is SIW, CMW, MDW0, MDW1...MDWn, EDW for all the message

types except long message. For long message, an extra AIW is added between CMW and MDW0.

Summary of Data Output Format

Please refer to

for different paging message format.

OPTION BIT

FUNCTION

MCKEG

MCLK active edge

Falling edge active

Rising edge active

0

1

Table 16. Data output pin option

OPTION BIT

FUNCTION

MSGVAL active level

active low

MSGI

0

1

active high

Table 17. Data output pin option

OPTION BIT

FUNCTION

MDATA, MCKI pin initial state

Initial low

MDAI, MCKI

0

1

Initial high

Table 18. Data output pin option

Publication Release Date: Auguest 1999

Revision A1

- 21 -

W93910

OPTION

FUNCTION

MCK1, MCK0

00

UD1, UD0

00

Tudi timing

0

Tint timing

2.08 mS

1.76 mS

1.44 mS

01

m

160 S

10

m

320 S

Tmclk = 80 S

11

m

640 S

800 S

00

0

3.04 mS

2.72 mS

1.76 mS

1.04 mS

3.52 mS

3.2 mS

01

m

160 S

10

m

Tmclk = 40 S

640 S

11

1 mS

0

00

10

01

m

160 S

10

2.24 mS

1.2 mS

m

Tmclk = 20 S

640 S

11

1.16 mS

0

00

3.88 mS

3.72 mS

2.66 mS

1.33 mS

11

01

m

80 S

10

m

Tmclk = 5 S

640 S

11

1.275 mS

Table 19. Tudi and Tint timing option (where Tunit = 4 mS minimum)

SIW Definition

When the W93910 receives a message, the MSGVAL pin will be activated first, and then SIW will be the

first word to output from the MDATA pin. System information, such as year, month, date, hour, day and

OPID, may resolve from SIW.

SIW

byte3

byte2

byte1

b7

0

b6

0

b5

0

b4

b3

fsi

s9

s1

b2

sn2

s8

b1

sn1

s7

b0

sn0

s6

0

s13

s5

s12

s4

s11

s3

s10

s2

s0

X

Table 20. SIW format

- 22 -

W93910

SIW Description:

fsi

0

s13 s12 s11 s10

s9

s8

s7

s6

s5

d4

s4

d3

s3

d2

s2

d1

s1

d0

s0

rv

z2

z1

z0

h4

h3

h2

h1

h0

1

w2

w1

w0

mt3 mt2 mt1 mt0 yr6

yr5

yr4

yr3

yr2

yr1

yr0

Table 21. s13 s0 format

-

sn2 sn0 is the subsequence number 0(000) to 4(100) that existed in SI field.

fsi is the function bit of s13- s0 that provides all transmitter time base information.

1. fsi = 0 while SSIT is equal "0000" in SSI field

-

z2 z0: RIC zone code from 000 111

-

h4 h0: Local hour from 0(00000) 23(10111)

-

d4 d0: Local date from 1(00001) 31(11111)

rv: reserve bit for future

-

(Note: minute will be shown as cy5 cy0 in EDW)

2. fsi = 1 while SSIT is equal "0001" in SSI field

-

w2 w0: Local day of week from Monday(001) Sunday(111)

-

mt4 mt0: Month from January(0001) December(1100)

-

yr6 yr0: Year from 1990(0000000) 2117(1111111)

CMW Definition

The second word is CMW, which indicates the message type, message number, paging category, and

alert type of received paging message.

CMW

byte3

byte2

byte1

b7

0

b6

0

b5

1

b4

0

b3

b2

b1

b0

cm3

mn3

ain3

cm2

mn2

ain2

cm1

mn1

ain1

cm0

mn0

ain0

eb

0

g1

0

g0

mn4

pc0 / f0

pc1 / f1

Table 22. CMW format

Publication Release Date: Auguest 1999

Revision A1

- 23 -

W93910

CMW Description:

cm3 cm0

message type description

-

0000

1000

1001

1010

1100

1101

1110

1111

Others

individual call

long message w/o C.S--First submessage.

long message w/o C.S--Others submessage.

remote programming

retransmit latest message no#

long message with C.S--Others submessage.

long message with C.S--First submessage.

Change Character Set (C.S.)

Reserved

Table 23. Message type description (cm3 cm0)

-

eb

0

External flag

Home Receiver

External receiver

1

Table 24. External receiver index

g1 g0

00

RIC address index of received message

-

IA17 IA0 available

01

Air Programming RIC

GIA17- GIA0 available

10

11

Group call by CTAP method

Table 25. Received message address index

Message number

mn4- mn0

00000

For group calls the reserved dummy value 00000 shall be used. The reserved

dummy value may also be used when the message numbering is deactivated,

as with remote programming.

Others

-

For individual calls the initial value shall be 00001; then mn4 mn0 will be

increased by 1 continuously for the following message.

Table 26. Message number description (mn4 mn0)

-

- 24 -

W93910

pc1 pc0

00

Paging category

Tone only

01

Numeric

10

Alphanumeric

transparent data

11

Table 27. Paging category index

-

The ain3 ain0 is used to indicated the alert type of the message, except in the remote programming

situation.

Alert type description

non-urgent alert type 0

non-urgent alert type 1

non-urgent alert type 2

non-urgent alert type 3

non-urgent alert type 4

non-urgent alert type 5

non-urgent alert type 6

non-urgent alert type 7

urgent alert type 0

ain3- ain0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

urgent alert type 1

urgent alert type 2

urgent alert type 3

urgent alert type 4

urgent alert type 5

urgent alert type 6

urgent alert type 7

Table 28. Alert type index

CMW for remote programming

When the pager receives the remote programming message, the W93910 will program the internal

remote programming addresses automatically, and will also inform the mC by sending out the received

-

message. For remote programming, the cm3 cm0 of CMW is equal to 1010, the f1 f0 and ain3 ain0 of

-

m

CMD, and rd17 rd0 of MDW will send out the received programming message to C as shown below.

Publication Release Date: Auguest 1999

- 25 -

Revision A1

W93910

Programmable function

ain3-

0 of CMW

rd17-rd0 definition in MDW

0001

Initial Address

Paging Area

-

RIA17 RIA0

0010

-

RPA5 RPA0 + 12 dummy '"0"

RZC3 + RCC7 + ROP3 + 5 dummy "0"

SM5 + HNL3 + 12 dummy "0"

0100

OPID

1000

Home receiver battery saving

External receiver battery saving

0111

SM5 + ENL3 + 12 dummy "0"

Table 29. Remote programming MDW format only

Function description

Add RIA, RPA, ROPID or replace SM

Remove RIA, RIA, ROPID

Restore SM, ENL, HNL to Table 1

Reserve

f1-f0

00

01

10

11

Table 30. Remote programming MDW format only

AIW Definition

AIW

byte3

byte2

byte1

b7

b6

b5

0

b4

b3

cs3

lc11

lc3

b2

cs2

lc10

lc2

b1

cs1

lc9

lc1

b0

cs0

lc8

lc0

0

1

cs4

lc12

lc15

lc7

lc14

lc6

lc13

lc5

lc4

Table 31. AIW format

The AIW is only available for long message (cm3- cm0 = 1000,1001,1101,1110) or changing character

-

set (cm3 cm0 = 1111), otherwise it's absent. The cs4 0 indicate character set and lc15 lc0 indicate link

counter. The different formats of AIW for the four different types of long message and changing

character set are listed in Summary of Data Output Format.

-

Each long message is divided into many submessages. The first submessage (cm3 cm0 = 1000 or

1110) must be transmitted first, then other submessages follow in sequence. Each submessage has its

-

own link counter lc15 lc0, which indicates how many message bits remain to be transmitted. The ter

flag is defined to indicate the end of the long message as shown in Table 28. When ter flag is 1, it

means the long message is completed. Otherwise, it means there are still some other submessages in

the coming signal.

For a long message, the W93910 will store all the received submessages including the EOM and filler

bits in MDW and then send to UC. The filler bits and EOM are the last message part of MDW group,

MDW1, MDW2...MDWn, and need to be removed to construct the long message. The following

equation shows how many message bits of the previous MDW group need to be truncated. The long

message can then be reproduced by connecting all the submessages except the truncated parts.

- 26 -

W93910

No. of message bits needing to be truncated in previous MDW group

-

= Total message bits of previous MDW group - [ (lc15 lc0)_previous- (lc15 lc0)_current

]

ter flag in EDW

ter = 1

Status

long message is completed

ter = 0

long message is not completed

Table 32. ter flag of EDW for long message

MDW Definition

The received paging message will be output as MDW1, MDW2 ....MDWn format (MDW group).

-

md17 md0 are the actual paging message data resolved from the message partition, including

terminator character EOM and any dummy bit such as a filler. For any submessage of a long message,

m

-

C needs to use AIW's lc15 lc0 to truncate terminator or dummy bit from md17 md0 according to AIW

-

description. While remote programming, rd17 rd0 is used for remote programming data only. RPI is the

remote programming index received from system. This bit should be loaded into b147 of option bit

during the re-initialization stage if the remote address is programmed.

MDW

byte3

b7

0

b6

1

b5

1

b4

0

b3

b2

b1

b0

md17/

rd17

md16/

rd16

md15/

rd15

md14/

rd14

byte2

byte1

md13/

rd13

md12/

rd12

md11/

rd11

md10/

rd10

md9/

rd9

md8/

rd8

md7/

rd7

md6/

rd6

md5/rd5 md4/rd4 md3/rd3 md2/rd2 md1/rd1 md0/rd0

er1

RPI

Table 33. MDW format

MDW Description:

BIT

FUNCTION

Available paging message

Remote programming data only

-

md17 md0 (normal message)

-

rd17 rd0 (remote programming)

er1

set to 1 if the random error can't be corrected in this message

word

rsv

don't care, reserved for future

Table 34. MDW bit description

Any paging message such as 7 bit alphanumeric, 4 numeric or transparent data will be placed

-

continuously in the 18 bit information field, md17 md0. After the last character (or bit) of message the

following message termination procedures shall be used:

·

Alphanumeric: an EOM character (0010001) shall be appended;

Numeric: no terminating character required;

Transparent data: a single bit set to one shall be appended;

Publication Release Date: Auguest 1999

Revision A1

- 27 -

W93910

Unused bit in message shall be set as the following default values:

·

Alphanumeric: EOM character and partial EOM character (MSB used first) shall be repeated to fill the

remaining bits;

Numeric: space character and partial space character ( MSB used first ) shall be repeated to fill the

remaining bits;

Transparent data: binary zeros shall be used to fill the remaining bits;

The bit mapping in MDW unit for numeric and 7 bit alphanumeric are as follows.

For numeric format, bit17- 14 of MDW0 construct the first numeric, bit13- 10 are the second... bit1- 0 of

-

MDW0 and bit17 16 of MDW1 are the fifth numeric.... Therefore, two MDWs will construct 9 numeric.

-

For 7 bit alphanumeric format, bit17 11 of MDW0 construct the first character, bit10 4 of MDW0 are the

-

second character, bit 3 0 of MDW0 and bit17 15 of MDW1 are the third character... The alphanumeric

definition is depended on Character Set (C.S.). The default C.S. is 00000.

EDW Definition

The EDW will follow the last MDW while the paging message is completed. Normally, the ter flag is

"0" except in a long message completion situation. For any submessage of a long message except the

last one, the ter flag of EDW is "0". Only when the long message is completed will the ter flag of EDW

be "1". There is some other system information in byte2 of EDW such as eti flag, bai flag and current

-

cycle number, cy5 cy0. The ch3 0 of byte3 indicate which frequency channel the current paging

message is caught from and the bn3- bn0 of byte3 indicate which batch the message is completed in.

EDW

byte3

byte2

byte1

b7

1

b6

1

b5

1

b4

b3

0

b2

ter

b1

b0

etm

cy0

ch0

0

epa

cy1

ch1

eti

bai

bn2

cy5

bn1

cy4

bn0

cy3

ch3

cy2

ch2

bn3

Table 35. EDW format

EDW description:

BIT

FUNCTION

ter

set to "1" while current long message is completed, otherwise ter flag is "0" for any

individual call or submessage.

epa

etm

set to "1" if paging message searching is stopped due to PA inconsistency

set to "1" if paging message searching is stopped due to 12 sec time out

.

cy5- cy0 cycle number from 0(000000) - 59(111011) as minute index

eti

External Traffic indicator in SI field

Border Area Indicator flag in SI field

bai

Table 36. EDW description

- 28 -

W93910

Summary of Data Output Format

message type

byte

SIW

(D23- D0)

CMW

AIW

MDW

(D23- D0)

EDW

(D23- D0)

(cm3- 0)

(D23- D0)

Individual

3

2

1

0000 fsi sn2- sn0

s13- s6

0010 cm3- cm0

X

0110 md17- md14

md13- md6

1110 0 ter epa etm

eti bai cy5- cy0

bn3- bn0 ch3- ch0

0000

eb g1 g0 mn4- mn0

s5- s0 0 0

0 0 pc1- pc0 ain3- ain0

md5- md0 er1 rsv

0XXX(Reserved)

Long w/o C.S.

(First submessage)

1000

3

2

1

3

2

0000 fsi sn2- sn0

s13- s6

0010 cm3- cm0

010 xxxxx

lc15- lc8

lc7- lc0

0110 md17- md14

md13- md6

1110 0 ter epa etm

eti bai cy5- cy0

eb g1 g0 mn4- mn0

0 0 pc1- pc0 ain3- ain0

0010 cm3- cm0

s5- s0 0 0

md5- md0 er1 rsv

0110 md17- md14

md13- md6

bn3- bn0 ch3- ch0

1110 0 ter epa etm

eti bai cy5- cy0

Long w/o C.S.

0000 fsi sn2- sn0

s13- s6

010 xxxxx

lc15- lc8

(Other

eb g1 g0 mn4- mn0

submessages)

1001

1

3

2

1

s5- s0 0 0

0 0 pc1- pc0 ain3- ain0

0010 cm3- cm0

lc7- lc0

md5- md0 er1 rsv

bn3- bn0 ch3- ch0

Remote

0000 fsi sn2- sn0

s13- s6

X

0110 md17- md14 1110 0 ter epa etm

Programming

1010

eb g1 g0 mn4- mn0

0 0 f1- f0 ain3- ain0

rd13- rd6

eti bai cy5- cy0

s5- s0 0 0

rd5- rd0 er1 rsv

bn3- bn0 ch3- ch0

1011(reserved)

Retransmit

Latest msg no

1100

3

2

1

3

2

1

3

2

0000 fsi sn2- sn0

s13- s6

0010 cm3- cm0

X

0110 md17- md14

md13- md6

1110 0 ter epa etm

eti bai cy5- cy0

eb g1 g0 mn4~mn0

0 0 pc1- pc0 ain3- ain0

0010 cm3- cm0

X

s5- s0 0 0

X

md5- md0 er1 rsv

0110 md17- md14

md13- md6

bn3- bn0 ch3- ch0

1110 0 ter epa etm

eti bai cy5- cy0

Long with C.S.

(First submessage)

1101

0000 fsi sn2- sn0

s13- s6

010 cs5- cs0

lc15- lc8

lc7~lc0

010 cs5- cs0

lc15- lc8

eb g1 g0 mn4- mn0

0 0 pc1- pc0 ain3- ain0

0010 cm3- cm0

s5- s0 0 0

md5~md0 er1 rsv

0110 md17- md14

md13- md6

bn3- bn0 ch3- ch0

1110 0 ter epa etm

eti bai cy5- cy0

Long with C.S.

0000 fsi sn2- sn0

s13- s6

(Other

eb g1 g0 mn4- mn0

submessages)

1110

1

3

2

1

s5- s0 0 0

0 0 pc1- pc0 ain3- ain0

0010 cm3- cm0

lc7- lc0

md5- md0 er1 rsv

0110 md17- md14

md13- md6

bn3- bn0 ch3- ch0

1110 0 ter epa etm

eti bai cy5- cy0

Change

Character Set

1111

0000 fsi sn2- sn0

s13- s6

010 cs5- cs0

xxxx xxxx

eb g1 g0 mn4- mn0

0 0 pc1- pc0 ain3- ain0

s5- s0 0 0

md5- md0 er1 rsv

bn3- bn0 ch3- ch0

Table 37. MDATA output summary

Note: where "x" means don't care

Publication Release Date: Auguest 1999

Revision A1

- 29 -

W93910

LED CONTROL

LEDO will output a frequency while ENLED is in high level. The LEDO output frequency is selected by

option bit LEDF and PLEN condition as described in table 38. When the LEDF is set to 1, the TCTL1

and TCTL2 control pin will also be activated to output the control signal. The TCTL1 and TCTL2 timing

is shown in figure 3.

PLEN

ENLED

.......

LEDO

10 kHZ

40 kHZ

Option bit LEDF = 1

Figure 13. LEDO Timing

OPTION BIT AND PLEN PIN

FUNCTION

LEDF

PLEN Status

inactive

active

LEDO output frequency

0

1

4 kHz

16 kHz

10 kHZ

40 kHZ

inactive

active

Table 38. LED option bit

RESET CONDITION

The W93910 has two reset conditions.

Power on & XRST active

·

Reset all 192 option bits and all remote programming registers

RFEN, PLEN, QC1, QC2, LOCK, MSGVAL, MCLK, MDATA in non-active state

ON pin rising edge is occurred

·

Oscillator start oscillation

-

Reset channel number to CH3 CH0 of the 192 option bits

The values of remote programming registers is not changed

- 30 -

W93910

ABSOLUTE MAXIMUM RATINGS

PARAMETER

Supply Voltage to Ground Potential

Applied Input/Output Voltage

Power Dissipation

RATING

-0.3 to +7.0

120

UNIT

V

mW

Ambient Operating Temperature

Storage temperature

-20 to +70

-55 to +155

°

C

°

Note: The device should be operated under the above conditions. Operation beyond these conditions may result in permanent

damage to the device.

DC/AC ELECTRONIC CHARACTERISTICS

(V_DD= 3 volt, Fosc = 100 kHz, Ta = 25 C )

°

SYMBOL

PARAMETER

Operating Voltage

Operating Current

Stand By current

CONDITION

MIN.

TYP

3

MAX.

3.5

UNIT NOTE

DD

V

2.5

V

OP

I

V_DD= 3 volt

ON = 0 volt

25

1

100

2

m

A

SB

I

m

A

OH

V

Output high voltage

Output Low voltage

Input high voltage

Input low voltage

2.4

2

V

OL

V

0.4

0.8

V

IH

V

IL

V

OH

O

I

Output High Current

Output Low Current

CHRS Active Width

XCNCG Active Width

TXCLK Period

V = 2.1 volt

500

1

mA

mS

OL

I

O

V = 0.4 volt

CHRS

T

XCNCG

T

4

4.5

1

TXCK

T

1

m

S

TDST

T

TXDATA Setup Time

TXDATA Hold Time

OSCO Stable Time

XRST Active Width

Programming setup

TXCLK to ON delay

20

nS

S

TDHD

T

OSC

T

XRST

T

10

1

m

S

PG

T

m

S

ON

T

3

Txclk

Publication Release Date: Auguest 1999

Revision A1

- 31 -

W93910

DC/AC Electronic Charac, continued

SYMBOL

PARAMETER

CONDITION

MIN.

TYP

MAX.

UNIT NOTE

OP

T

ON active to PLEN

active delay

4

S

ADDT

T

ADRDET active to

MCLK active

45

mS

MSGV

T

MSGAVL active to

MCLK active

700

m

S

MCLK

T

MCLK Period

80

40

20

5

-

m

S

MCK1 0 = 00

-

m

S

MCK1 0 = 01

-

m

S

MCK1 0 = 10

-

m

S

MCK1 0 = 11

MDST

T

MDATA Setup Time

MDATA Hold Time

PLEN Pre-Active Time

MCLK active edge

1/4

Tmclk

mS

MDHD

T

PLST

T

9.6

19.2

28.8

38

-

PL1 0 = 00

mS

-

PL1 0 = 01

mS

-

PL1 0 = 10

mS

-

PL1 0 = 11

RFDY

T

RFEN Delay to

Preamble

RFON = 0

4.8

mS

RFON = 1

QC1WTH = 0

QC1WTH = 1

9.6

mS

QC1W

T

QC1 Active Width

2.5

3.8

4

UNIT

T

MDATA D23 to Next

unit D23

UDI

T

MCLK Stop Clock per

byte

1.2

2

1.3

2.1

mS

-

MCK1 0 = 11

-

UDI1 0 = 11

INT

T

MDATA D0 Delay to

Next D23

-

MCK1 0 = 00

-

UDI1 0 = 00

- 32 -

W93910

TYPICAL APPLICATION CIRCUIT

LCD

c1=20pf

VDD

OSCI

LEDO

XRS

VDD

100khz

ENLED

CHRS

OSCO

TXCLK

TXDATA

ON

W93910

UC

VDD

TCTL2

3V

1.5V

ADRDET

SYNVAL

XCNCG

MDATA

MCLK

TCTL1

RFEN

DC/DC

QC1

QC2

D0

RECEIVER

MSGVAL

D1

M

1.5V

PLEN

VSS

CLK

DATA

EN

Publication Release Date: Auguest 1999

Revision A1

- 33 -

W93910

Package Information

D

28

DETAIL A

E E1

1

2

A2 A

SEATING PLANE

0.10

A1

b

e

e/2

R1

O

R1

b/2

ODD

0.25

L

EVEN

DETAIL A

L1

Symbol

Common Dimension (Millimeters)

Nom.

Common Dimension (Inches)

Nom.

Min.

Max.

Min.

Max.

A

A1

A2

b

2.0

0.079

0.05

1.65

0.22

9.9

0.002

0.065

0.009

0.390

0.291

0.197

1.75

1.85

0.38

10.5

8.20

5.60

0.069

0.073

0.015

0.413

0.323

0.220

D

10.2

7.80

5.30

0.65

0.75

1.25

0.401

0.307

0.209

0.0256

0.030

0.050

E

7.40

5.00

E1

e

L

0.55

0.95

8

0.021

0.037

8

L1

R1

O

0.09

0

0.004

0

4

- 34 -

W93910

Winbond Electronics (H.K.) Ltd.

Winbond Electronics North America Corp.

Winbond Memory Lab.

Winbond Microelectronics Corp.

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

Headquarters

Rm. 803, World Trade Square, Tower II,

123 Hoi Bun Rd., Kwun Tong,

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5792766

http://www.winbond.com.tw/

TEL: 408-9436666

FAX: 408-5441798

Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Note: All data and specifications are subject to change without notice.

Publication Release Date: Auguest 1999

Revision A1

- 35 -


型号：	W93910
厂家：	WINBOND
描述：	ERMES PAGING DECODER ERMES寻呼解码器解码器寻呼；传讯
文件：	总35页 (文件大小：265K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W93910 [WINBOND]

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