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W9425G6JH-5I [WINBOND]

DDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, ROHS COMPLIANT, TSOP2-66;
W9425G6JH-5I
型号： W9425G6JH-5I
厂家： WINBOND    WINBOND
描述：

DDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, ROHS COMPLIANT, TSOP2-66

时钟 动态存储器 双倍数据速率 光电二极管 内存集成电路
文件： 总52页 (文件大小：946K)
中文：  中文翻译
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W9425G6JH  
4 M 4 BANKS 16 BITS DDR SDRAM  
Table of Contents-  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
GENERAL DESCRIPTION.............................................................................................................................4  
FEATURES....................................................................................................................................................4  
ORDER INFORMATION ................................................................................................................................4  
KEY PARAMETERS ......................................................................................................................................5  
PIN CONFIGURATION ..................................................................................................................................6  
PIN DESCRIPTION........................................................................................................................................7  
BLOCK DIAGRAM .........................................................................................................................................8  
FUNCTIONAL DESCRIPTION.......................................................................................................................9  
8.1  
8.2  
Power Up Sequence ..........................................................................................................................9  
Command Function..........................................................................................................................10  
8.2.1 Bank Activate Command......................................................................................................10  
8.2.2 Bank Precharge Command ..................................................................................................10  
8.2.3 Precharge All Command ......................................................................................................10  
8.2.4 Write Command ...................................................................................................................10  
8.2.5 Write with Auto-precharge Command...................................................................................10  
8.2.6 Read Command ...................................................................................................................10  
8.2.7 Read with Auto-precharge Command ..................................................................................10  
8.2.8 Mode Register Set Command ..............................................................................................11  
8.2.9 Extended Mode Register Set Command ..............................................................................11  
8.2.10 No-Operation Command ......................................................................................................11  
8.2.11 Burst Read Stop Command..................................................................................................11  
8.2.12 Device Deselect Command..................................................................................................11  
8.2.13 Auto Refresh Command.......................................................................................................11  
8.2.14 Self Refresh Entry Command...............................................................................................12  
8.2.15 Self Refresh Exit Command .................................................................................................12  
8.2.16 Data Write Enable /Disable Command.................................................................................12  
8.3  
8.4  
8.5  
8.6  
8.7  
8.8  
8.9  
Read Operation................................................................................................................................12  
Write Operation ................................................................................................................................13  
Precharge.........................................................................................................................................13  
Burst Termination.............................................................................................................................13  
Refresh Operation............................................................................................................................13  
Power Down Mode...........................................................................................................................14  
Input Clock Frequency Change during Precharge Power Down Mode ............................................14  
8.10 Mode Register Operation .................................................................................................................14  
8.10.1 Burst Length field (A2 to A0) ................................................................................................14  
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8.10.2 Addressing Mode Select (A3)...............................................................................................15  
8.10.3 CAS Latency field (A6 to A4)................................................................................................16  
8.10.4 DLL Reset bit (A8)................................................................................................................16  
8.10.5 Mode Register /Extended Mode register change bits (BA0, BA1)........................................16  
8.10.6 Extended Mode Register field ..............................................................................................16  
8.10.7 Reserved field ......................................................................................................................16  
9.  
OPERATION MODE ....................................................................................................................................17  
9.1  
9.2  
9.3  
9.4  
Simplified Truth Table ......................................................................................................................17  
Function Truth Table ........................................................................................................................18  
Function Truth Table for CKE...........................................................................................................21  
Simplified Stated Diagram................................................................................................................22  
10. ELECTRICAL CHARACTERISTICS ............................................................................................................23  
10.1 Absolute Maximum Ratings..............................................................................................................23  
10.2 Recommended DC Operating Conditions ........................................................................................23  
10.3 Capacitance .....................................................................................................................................24  
10.4 Leakage and Output Buffer Characteristics......................................................................................24  
10.5 DC Characteristics ...........................................................................................................................25  
10.6 AC Characteristics and Operating Condition....................................................................................26  
10.7 AC Test Conditions ..........................................................................................................................27  
11. SYSTEM CHARACTERISTICS FOR DDR SDRAM.....................................................................................29  
11.1 Table 1: Input Slew Rate for DQ, DQS, and DM ..............................................................................29  
11.2 Table 2: Input Setup & Hold Time Derating for Slew Rate ...............................................................29  
11.3 Table 3: Input/Output Setup & Hold Time Derating for Slew Rate....................................................29  
11.4 Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate ....................................29  
11.5 Table 5: Output Slew Rate Characteristics (X16 Devices only)........................................................29  
11.6 Table 6: Output Slew Rate Matching Ratio Characteristics..............................................................30  
11.7 Table 7: AC Overshoot/Undershoot Specification for Address and Control Pins..............................30  
11.8 Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins...............................31  
11.9 System Notes:..................................................................................................................................32  
12. TIMING WAVEFORMS ................................................................................................................................34  
12.1 Command Input Timing....................................................................................................................34  
12.2 Timing of the CLK Signals................................................................................................................34  
12.3 Read Timing (Burst Length = 4) .......................................................................................................35  
12.4 Write Timing (Burst Length = 4) .......................................................................................................36  
12.5 DM, DATA MASK (W9425G6JH) .....................................................................................................37  
12.6 Mode Register Set (MRS) Timing.....................................................................................................38  
12.7 Extend Mode Register Set (EMRS) Timing ......................................................................................39  
12.8 Auto-precharge Timing (Read Cycle, CL = 2) ..................................................................................40  
12.9 Auto-precharge Timing (Read cycle, CL = 2), continued..................................................................41  
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12.10 Auto-precharge Timing (Write Cycle) ...............................................................................................42  
12.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8)..............................................................................43  
12.12 Burst Read Stop (BL = 8) .................................................................................................................43  
12.13 Read Interrupted by Write & BST (BL = 8) .......................................................................................44  
12.14 Read Interrupted by Precharge (BL = 8) ..........................................................................................44  
12.15 Write Interrupted by Write (BL = 2, 4, 8)...........................................................................................45  
12.16 Write Interrupted by Read (CL = 2, BL = 8)......................................................................................45  
12.17 Write Interrupted by Read (CL = 3, BL = 4)......................................................................................46  
12.18 Write Interrupted by Precharge (BL = 8)...........................................................................................46  
12.19 2 Bank Interleave Read Operation (CL = 2, BL = 2).........................................................................47  
12.20 2 Bank Interleave Read Operation (CL = 2, BL = 4).........................................................................47  
12.21 4 Bank Interleave Read Operation (CL = 2, BL = 2).........................................................................48  
12.22 4 Bank Interleave Read Operation (CL = 2, BL = 4).........................................................................48  
12.23 Auto Refresh Cycle ..........................................................................................................................49  
12.24 Precharged/Active Power Down Mode Entry and Exit Timing..........................................................49  
12.25 Input Clock Frequency Change during Precharge Power Down Mode Timing.................................49  
12.26 Self Refresh Entry and Exit Timing...................................................................................................50  
13. PACKAGE SPECIFICATION .......................................................................................................................51  
14. REVISION HISTORY ...................................................................................................................................52  
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1. GENERAL DESCRIPTION  
W9425G6JH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR  
SDRAM), organized as 4,194,304 words 4 banks 16 bits. W9425G6JH delivers a data bandwidth  
of up to 500M words per second (-4). To fully comply with the personal computer industrial standard,  
W9425G6JH is sorted into the following speed grades: -4, -5, -5I and -5A. The -4 grade parts is  
compliant to the DDR500/CL3 and CL4 specification. The -5/-5I/-5A grade parts are compliant to the  
DDR400/CL3 specification (the -5I industrial grade, -5A automotive grade which is guaranteed to  
support -40°C ~ 85°C).  
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference  
point for the differential clock is when the CLK and CLK signals cross during a transition. Write and  
Read data are synchronized with the both edges of DQS (Data Strobe).  
By having a programmable Mode Register, the system can change burst length, latency cycle,  
interleave or sequential burst to maximize its performance. W9425G6JH is ideal for main memory in  
high performance applications.  
2. FEATURES  
2.5V ± 0.2V Power Supply for DDR400  
2.4V~2.7V Power Supply for DDR500  
Up to 250 MHz Clock Frequency  
Double Data Rate architecture; two data transfers per clock cycle  
Differential clock inputs (CLK and CLK )  
DQS is edge-aligned with data for Read; center-aligned with data for Write  
CAS Latency: 2, 2.5, 3 and 4  
Burst Length: 2, 4 and 8  
Auto Refresh and Self Refresh  
Precharged Power Down and Active Power Down  
Write Data Mask  
Write Latency = 1  
7.8µS refresh interval (8K/64 mS refresh)  
Maximum burst refresh cycle: 8  
Interface: SSTL_2  
Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant  
3. ORDER INFORMATION  
SELF REFRESH  
CURRENT (MAX.)  
OPERATING  
TEMPERATURE  
PART NUMBER  
SPEED  
W9425G6JH-4  
W9425G6JH-5  
W9425G6JH-5I  
W9425G6JH-5A  
DDR500/CL3 and CL4  
DDR400/CL3  
2 mA  
2 mA  
2 mA  
2 mA  
0°C ~ 70°C  
0°C ~ 70°C  
DDR400/CL3  
-40°C ~ 85°C  
-40°C ~ 85°C  
DDR400/CL3  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
4. KEY PARAMETERS  
SYMBOL  
DESCRIPTION  
MIN/MAX.  
Min.  
-4  
-
-5/-5I/-5A  
7.5 nS  
12 nS  
6 nS  
CL = 2  
CL = 2.5  
CL = 3  
CL = 4  
Max.  
Min.  
-
-
Max.  
Min.  
-
12 nS  
5 nS  
Clock Cycle Time  
tCK  
4 nS  
Max.  
Min.  
12 nS  
4 nS  
12 nS  
-
Max.  
Min.  
12 nS  
36 nS  
52 nS  
75 mA  
90 mA  
140 mA  
135 mA  
70 mA  
2 mA  
-
Active to Precharge Command Period  
Active to Ref/Active Command Period  
40 nS  
55 nS  
65 mA  
80 mA  
120 mA  
115 mA  
65 mA  
2 mA  
tRAS  
tRC  
Min.  
Operating Current: One Bank Active-Precharge  
Operating Current: One Bank Active-Read-Precharge  
Burst Operation Current  
Max.  
Max.  
Max.  
Max.  
Max.  
Max.  
IDD0  
IDD1  
IDD4R  
IDD4W  
IDD5  
IDD6  
Burst Operation Current  
Auto Refresh Burst current  
Self-Refresh Current  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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5. PIN CONFIGURATION  
VDD  
DQ0  
VDDQ  
DQ1  
DQ2  
VSSQ  
1
2
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
VSS  
DQ15  
VSSQ  
DQ14  
DQ13  
VDDQ  
DQ12  
DQ11  
VSSQ  
DQ10  
DQ9  
3
4
5
6
7
DQ3  
DQ4  
VDDQ  
DQ5  
DQ6  
VSSQ  
DQ7  
NC  
8
9
10  
11  
12  
13  
14  
VDDQ  
DQ8  
NC  
VSSQ  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
VDDQ  
LDQS  
NC  
UDQS  
NC  
VDD  
VREF  
VSS  
NC  
UDM  
CLK  
CLK  
CKE  
NC  
LDM  
WE  
CAS  
RAS  
CS  
NC  
A12  
A11  
A9  
BA0  
BA1  
A10/AP  
A0  
A8  
A7  
A1  
A6  
A2  
A5  
A3  
A4  
VDD  
VSS  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
6. PIN DESCRIPTION  
PIN  
PIN NUMBER  
NAME  
FUNCTION  
DESCRIPTION  
Multiplexed pins for row and column address.  
Row address: A0 A12.  
28 32,  
A0 A12  
35 42  
Address  
Column address: A0 A8. (A10 is used for Auto-precharge)  
Select bank to activate during row address latch time, or  
bank to read/write during column address latch time.  
26, 27  
BA0, BA1  
Bank Select  
2, 4, 5, 7, 8, 10,  
11, 13, 54, 56, 57,  
59, 60, 62, 63, 65  
The DQ0 – DQ15 input and output data are synchronized  
with both edges of DQS.  
DQ0   
DQ15  
Data Input/ Output  
DQS is Bi-directional signal. DQS is input signal during write  
operation and output signal during read operation. It is Edge-  
aligned with read data, Center-aligned with write data.  
LDQS,  
UDQS  
16,51  
24  
Data Strobe  
Chip Select  
Disable or enable the command decoder. When command  
decoder is disabled, new command is ignored and previous  
operation continues.  
CS  
RAS  
CAS  
,
Command inputs (along with CS ) define the command  
being entered.  
23, 22, 21  
20, 47  
Command Inputs  
Write Mask  
,
WE  
When DM is asserted “high” in burst write, the input data is  
masked. DM is synchronized with both edges of DQS.  
LDM, UDM  
All address and control input signals are sampled on the  
crossing of the positive edge of CLK and negative edge of  
CLK,  
CLK  
Differential Clock  
Inputs  
45, 46  
44  
CLK  
.
CKE controls the clock activation and deactivation. When  
CKE is low, Power Down mode, Suspend mode, or Self  
Refresh mode is entered.  
CKE  
Clock Enable  
49  
VREF  
VDD  
VSS  
Reference Voltage VREF is reference voltage for inputs.  
1, 18, 33  
34, 48, 66  
Power  
Power for logic circuit inside DDR SDRAM.  
Ground for logic circuit inside DDR SDRAM.  
Ground  
Power for I/O  
Buffer  
Separated power from VDD, used for output buffer, to  
improve noise.  
3, 9, 15, 55, 61  
6, 12, 52, 58, 64  
VDDQ  
VSSQ  
NC  
Ground for I/O  
Buffer  
Separated ground from VSS, used for output buffer, to  
improve noise.  
14, 17, 19, 25,  
43, 50, 53  
No Connection  
No connection  
Publication Release Date: Aug. 27, 2013  
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Revision A03  
W9425G6JH  
7. BLOCK DIAGRAM  
CLK  
DLL  
CLOCK  
CLK  
BUFFER  
CKE  
CONTROL  
CS  
SIGNAL  
GENERATOR  
RAS  
CAS  
COMMAND  
DECODER  
COLUMN DECODER  
COLUMN DECODER  
WE  
CELL ARRAY  
BANK #0  
CELL ARRAY  
BANK #1  
A10  
A0  
MODE  
REGISTER  
SENSE AMPLIFIER  
SENSE AMPLIFIER  
ADDRESS  
BUFFER  
A9  
A11  
A12  
BA0  
BA1  
PREFETCH REGISTER  
DQ0  
DQ  
DATA CONTROL  
CIRCUIT  
BUFFER  
DQ15  
COLUMN  
COUNTER  
LDQS  
UDQS  
REFRESH  
COUNTER  
LDM  
UDM  
COLUMN DECODER  
COLUMN DECODER  
CELL ARRAY  
BANK #2  
CELL ARRAY  
BANK #3  
SENSE AMPLIFIER  
SENSE AMPLIFIER  
NOTE: The cell array configuration is 8192 * 512 * 16  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
8. FUNCTIONAL DESCRIPTION  
8.1 Power Up Sequence  
(1) Apply power and attempt to CKE at a low state (  
0.2V), all other inputs may be undefined  
1) Apply VDD before or at the same time as VDDQ.  
2) Apply VDDQ before or at the same time as VTT and VREF.  
(2) Start Clock and maintain stable condition for 200 µS (min.).  
(3) After stable power and clock, apply NOP and take CKE high.  
(4) Issue precharge command for all banks of the device.  
(5) Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type.  
(6) Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8.  
(An additional 200 cycles(min) of clock are required for DLL Lock before any executable  
command applied.)  
(7) Issue precharge command for all banks of the device.  
(8) Issue two or more Auto Refresh commands.  
(9) Issue MRS-Initialize device operation with the reset DLL bit deactivated A8 to low.  
CLK  
CLK  
ANY  
CMD  
Command  
PREA  
EMRS  
2 Clock min.  
MRS  
PREA  
AREF  
AREF  
MRS  
tRFC  
2 Clock min.  
2 Clock min.  
tRP  
tRP  
tRFC  
200 Clock min.  
Inputs  
maintain stable  
for 200 µS min.  
Disable DLL reset with A8 = Low  
Enable DLL  
DLL reset with A8 = High  
Initialization sequence after power-up  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
8.2 Command Function  
8.2.1 Bank Activate Command  
(
RAS = “L”, CAS = “H”, WE = “H”, BA0, BA1 = Bank, A0 to A12 = Row Address)  
The Bank Activate command activates the bank designated by the BA (Bank address) signal. Row  
addresses are latched on A0 to A12 when this command is issued and the cell data is read out of  
the sense amplifiers. The maximum time that each bank can be held in the active state is specified  
as tRAS (max). After this command is issued, Read or Write operation can be executed.  
8.2.2 Bank Precharge Command  
(
RAS = “L”, CAS = “H”, WE = “L”, BA0, BA1 = Bank, A10 = “L”, A0 to A9, A11, A12 = Don’t  
Care)  
The Bank Precharge command percharges the bank designated by BA. The precharged bank is  
switched from the active state to the idle state.  
8.2.3 Precharge All Command  
(
RAS = “L”, CAS = “H”, WE = “L”, BA0, BA1 = Don’t Care, A10 = “H”, A0 to A9, A11, A12 =  
Don’t Care)  
The Precharge All command precharges all banks simultaneously. Then all banks are switched to  
the idle state.  
8.2.4 Write Command  
(
RAS = “H”, CAS = “L”, WE = “L”, BA0, BA1 = Bank, A10 = “L”, A0 to A8 = Column Address)  
The write command performs a Write operation to the bank designated by BA. The write data are  
latched at both edges of DQS. The length of the write data (Burst Length) and column access  
sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write  
operation.  
8.2.5 Write with Auto-precharge Command  
(
RAS = “H”, CAS = “L”, WE = “L”, BA0, BA1 = Bank, A10 = “H”, A0 to A8 = Column Address)  
The Write with Auto-precharge command performs the Precharge operation automatically after the  
Write operation. This command must not be interrupted by any other commands.  
8.2.6 Read Command  
(
RAS = “H”, CAS = “L”, WE = "H", BA0, BA1 = Bank, A10 = “L”, A0 to A8 = Column Address)  
The Read command performs a Read operation to the bank designated by BA. The read data are  
synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode  
and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the  
Mode Register at power-up prior to the Read operation.  
8.2.7 Read with Auto-precharge Command  
(
RAS =“H”, CAS= “L”, WE = “H”, BA0, BA1 = Bank, A10 = “H”, A0 to A8 = Column Address)  
The Read with Auto-precharge command automatically performs the Precharge operation after the  
Read operation.  
Publication Release Date: Aug. 27, 2013  
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W9425G6JH  
1) READA tRAS (min) - (BL/2) x tCK  
Internal precharge operation begins after BL/2 cycle from Read with Auto-precharge command.  
2) tRCD(min) READA < tRAS(min) - (BL/2) x tCK  
Data can be read with shortest latency, but the internal Precharge operation does not begin until  
after tRAS (min) has completed.  
This command must not be interrupted by any other command.  
8.2.8 Mode Register Set Command  
(
RAS = “L”, CAS = “L”, WE = “L”, BA0 = “L”, BA1 = “L”, A0 to A12 = Register Data)  
The Mode Register Set command programs the values of CAS Latency, Addressing Mode, Burst  
Length and DLL reset in the Mode Register. The default values in the Mode Register after power-  
up are undefined, therefore this command must be issued during the power-up sequence. Also,  
this command can be issued while all banks are in the idle state. Refer to the table for specific  
codes.  
8.2.9 Extended Mode Register Set Command  
(
RAS = “L”, CAS = “L”, WE = “L”, BA0 = “H”, BA1 = “L”, A0 to A12 = Register data)  
The Extended Mode Register Set command can be implemented as needed for function  
extensions to the standard (SDR-SDRAM). These additional functions include DLL enable/disable,  
output drive strength selection. The default value of the extended mode register is not defined;  
therefore this command must be issued during the power-up sequence for enabling DLL. Refer to  
the table for specific codes.  
8.2.10 No-Operation Command  
(
RAS = “H”, CAS = “H”, WE = “H”)  
The No-Operation command simply performs no operation (same command as Device Deselect).  
8.2.11 Burst Read Stop Command  
(
RAS = “H”, CAS= “H”, WE = “L”)  
The Burst stop command is used to stop the burst operation. This command is only valid during a  
Burst Read operation.  
8.2.12 Device Deselect Command  
(
CS = “H”)  
The Device Deselect command disables the command decoder so that the RAS  
,
CAS ,  
WE and Address inputs are ignored. This command is similar to the No-Operation command.  
8.2.13 Auto Refresh Command  
(
RAS = “L”, CAS = “L”, WE = “H”, CKE = “H”, BA0, BA1, A0 to A12 = Don’t Care)  
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS–  
BEFORE–RAS (CBR) refresh in previous DRAM types. This command is non persistent, so it  
must be issued each time a refresh is required.  
The refresh addressing is generated by the internal refresh controller. This makes the address bits  
“Don’t Care” during an AUTO REFRESH command. The DDR SDRAM requires AUTO REFRESH  
Publication Release Date: Aug. 27, 2013  
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W9425G6JH  
cycles at an average periodic interval of tREFI (maximum). To allow for improved efficiency in  
scheduling and switching between tasks, some flexibility in the absolute refresh interval is  
provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR  
SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the  
next AUTO REFRESH command is 8 * tREFI.  
8.2.14 Self Refresh Entry Command  
(
RAS = “L”, CAS = “L”, WE = “H”, CKE = “L”, BA0, BA1, A0 to A12 = Don’t Care)  
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of  
the system is powered down. When in the self refresh mode, the DDR SDRAM retains data  
without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH  
command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF  
REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is  
enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command  
can be issued. Input signals except CKE are “Don’t Care” during SELF REFRESH. Since CKE is a  
SSTL_2 input, VREF must be maintained during SELF REFRESH.  
8.2.15 Self Refresh Exit Command  
(CKE = “H”, CS = “H” or CKE = "H", RAS = “H”, CAS = “H”)  
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be  
stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP  
commands issued for tXSNR because time is required for the completion of any internal refresh in  
progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for  
200 clock cycles before applying any other command.  
The use of SELF REFREH mode introduces the possibility that an internally timed event can be  
missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an  
extra auto refresh command is recommended.  
8.2.16 Data Write Enable /Disable Command  
(DM = “L/H” or LDM, UDM = “L/H”)  
During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every  
word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to  
DQ15.  
8.3 Read Operation  
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read  
command is issued after tRCD from the Bank Activate command, the data is read out sequentially,  
synchronized with both edges of DQS (Burst Read operation). The initial read data becomes  
available after CAS Latency from the issuing of the Read command. The CAS Latency must be set  
in the Mode Register at power-up.  
When the Precharge Operation is performed on a bank during a Burst Read and operation, the  
Burst operation is terminated.  
When the Read with Auto-precharge command is issued, the Precharge operation is performed  
automatically after the Read cycle then the bank is switched to the idle state. This command  
cannot be interrupted by any other commands. Refer to the diagrams for Read operation.  
Publication Release Date: Aug. 27, 2013  
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Revision A03  
W9425G6JH  
8.4 Write Operation  
Issuing the Write command after tRCD from the bank activate command. The input data is latched  
sequentially, synchronizing with both edges(rising & falling) of DQS after the Write command  
(Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode  
must be set in the Mode Register at power-up.  
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst  
operation is terminated.  
When the Write with Auto-precharge command is issued, the Precharge operation is performed  
automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto-  
precharge command cannot be interrupted by any other command for the entire burst data  
duration.  
Refer to the diagrams for Write operation.  
8.5 Precharge  
There are two Commands, which perform the precharge operation (Bank Precharge and  
Precharge All). When the Bank Precharge command is issued to the active bank, the bank is  
precharged and then switched to the idle state. The Bank Precharge command can precharge one  
bank independently of the other bank and hold the unprecharged bank in the active state. The  
maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each  
bank must be precharged within tRAS(max) from the bank activate command.  
The Precharge All command can be used to precharge all banks simultaneously. Even if banks  
are not in the active state, the Precharge All command can still be issued. In this case, the  
Precharge operation is performed only for the active bank and the precharge bank is then  
switched to the idle state.  
8.6 Burst Termination  
When the Precharge command is used for a bank in a Burst cycle, the Burst operation is  
terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is  
disabled after clock cycle of (CAS Latency) from the Precharge command. When the Burst Write  
cycle is interrupted by the Precharge command, the input circuit is reset at the same clock cycle at  
which the precharge command is issued. In this case, the DM signal must be asserted "high"  
during tWR to prevent writing the invalided data to the cell array.  
When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read  
operation is terminated. The Burst read Stop command is not supported during a write burst  
operation. Refer to the diagrams for Burst termination.  
8.7 Refresh Operation  
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh.  
By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh  
operation must be performed 8192 times (rows) within 64mS. The period between the Auto  
Refresh command and the next command is specified by tRFC.  
Self Refresh mode enters issuing the Self Refresh command (CKE asserted "low") while all banks  
are in the idle state. The device is in Self Refresh mode for as long as CKE held "low". In the case  
of distributed Auto Refresh commands, distributed auto refresh commands must be issued every  
7.8 µS and the last distributed Auto Refresh commands must be performed within 7.8 µS before  
entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation  
must be performed within 7.8 µS. In Self Refresh mode, all input/output buffers are disabled,  
Publication Release Date: Aug. 27, 2013  
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Revision A03  
W9425G6JH  
resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh  
operation.  
8.8 Power Down Mode  
Two types of Power Down Mode can be performed on the device: Active Standby Power Down  
Mode and Precharge Standby Power Down Mode.  
When the device enters the Power Down Mode, all input/output buffers and DLL are disabled  
resulting in low power dissipation (except CKE buffer).  
Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking  
CKE "high" can exit this mode. When CKE goes high, a No operation command must be input at  
next CLK rising edge. Refer to the diagrams for Power Down Mode.  
8.9 Input Clock Frequency Change during Precharge Power Down Mode  
DDR SDRAM input clock frequency can be changed under following condition:  
DDR SDRAM must be in precharged power down mode with CKE at logic LOW level. After a  
minimum of 2 clocks after CKE goes LOW, the clock frequency may change to any frequency  
between minimum and maximum operating frequency specified for the particular speed grade.  
During an input clock frequency change, CKE must be held LOW. Once the input clock frequency  
is changed, a stable clock must be provided to DRAM before precharge power down mode may be  
exited. The DLL must be RESET via EMRS after precharge power down exit. An additional MRS  
command may need to be issued to appropriately set CL etc. After the DLL relock time, the DRAM  
is ready to operate with new clock frequency.  
8.10 Mode Register Operation  
The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all  
banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to  
A12 and BA0, BA1 address inputs.  
The Mode Register designates the operation mode for the read or write cycle. The register is  
divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode  
selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set  
the assess time in clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode  
Register filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented  
the extended function (DLL enable/Disable mode).  
The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the  
Mode Register Set command must be issued before power operation.  
8.10.1 Burst Length field (A2 to A0)  
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst  
Length to be 2, 4, and 8 words.  
A2  
0
A1  
0
A0  
0
BURST LENGTH  
Reserved  
2 words  
0
0
1
0
1
0
4 words  
0
1
1
8 words  
1
x
x
Reserved  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
8.10.2 Addressing Mode Select (A3)  
The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the  
A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both  
addressing Mode support burst length 2, 4, and 8 words.  
A3  
0
ADDRESSING MODE  
Sequential  
1
Interleave  
8.10.2.1. Addressing Sequence of Sequential Mode  
A column access is performed by incrementing the column address input to the device. The  
address is varied by the Burst Length as the following.  
Addressing Sequence of Sequential Mode  
DATA  
Data 0  
Data 1  
Data 2  
Data 3  
Data 4  
Data 5  
Data 6  
Data 7  
ACCESS ADDRESS  
BURST LENGTH  
n
2 words (address bits is A0)  
not carried from A0 to A1  
4 words (address bit A0, A1)  
Not carried from A1 to A2  
n + 1  
n + 2  
n + 3  
n + 4  
n + 5  
n + 6  
n + 7  
8 words (address bits A2, A1 and A0)  
Not carried from A2 to A3  
8.10.2.2. Addressing Sequence for Interleave Mode  
A Column access is started from the inputted column address and is performed by interleaving the  
address bits in the sequence shown as the following.  
Addressing Sequence of Interleave Mode  
DATA  
Data 0  
Data 1  
ACCESS ADDRESS  
BURST LENGTH  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
2 words  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
Data 2  
Data 3  
Data 4  
Data 5  
Data 6  
Data 7  
4 words  
8 words  
Publication Release Date: Aug. 27, 2013  
Revision A03  
- 15 -  
W9425G6JH  
8.10.3 CAS Latency field (A6 to A4)  
This field specifies the number of clock cycles from the assertion of the Read command to the first  
data read. The minimum values of CAS Latency depend on the frequency of CLK.  
A6  
0
A5  
0
A4  
0
CAS LATENCY  
Reserved  
Reserved  
2
0
0
1
0
1
0
0
1
1
3
1
0
0
Reserved  
Reserved  
2.5  
1
0
1
1
1
0
1
1
1
Reserved  
8.10.4 DLL Reset bit (A8)  
This bit is used to reset DLL. When the A8 bit is “1”, DLL is reset.  
8.10.5 Mode Register /Extended Mode register change bits (BA0, BA1)  
These bits are used to select MRS/EMRS.  
BA1  
0
BA0  
A12-A0  
0
1
x
Regular MRS Cycle  
Extended MRS Cycle  
Reserved  
0
1
8.10.6 Extended Mode Register field  
1) DLL Switch field (A0)  
This bit is used to select DLL enable or disable  
A0  
0
DLL  
Enable  
Disable  
1
2) Output Driver Size Control field (A6, A1)  
The 100%, 60% and 30% or matched impedance driver strength are required Extended Mode  
Register Set (EMRS) as the following:  
A6  
0
A1  
0
BUFFER STRENGTH  
100% Strength  
60% Strength  
Reserved  
0
1
1
0
1
1
30% Strength  
8.10.7 Reserved field  
Test mode entry bit (A7)  
This bit is used to enter Test mode and must be set to “0” for normal operation.  
Reserved bits (A9, A10, A11, A12)  
These bits are reserved for future operations. They must be set to “0” for normal operation.  
Publication Release Date: Aug. 27, 2013  
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Revision A03  
W9425G6JH  
9. OPERATION MODE  
The following table shows the operation commands.  
9.1 Simplified Truth Table  
A12,  
A11,  
A9-A0  
DEVICE  
STATE  
BA0,  
BA1  
SYM.  
COMMAND  
CKEn-1 CKEn DM(4)  
A10  
CS RAS  
CAS  
WE  
ACT  
Bank Active  
Idle(3)  
Any(3)  
Any  
H
H
H
H
X
X
X
X
X
X
X
X
V
V
X
V
V
L
V
X
X
V
L
L
L
L
L
L
H
H
H
L
H
L
L
L
PRE  
Bank Precharge  
Precharge All  
Write  
PREA  
WRIT  
H
L
L
Active(3)  
H
Write with Auto-  
precharge  
WRITA  
READ  
READA  
MRS  
Active(3)  
Active(3)  
Active(3)  
Idle  
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
V
V
H
L
V
V
V
C
V
L
L
L
L
L
H
H
H
L
L
L
L
L
L
L
H
H
L
Read  
Read with Auto-  
precharge  
V
H
C
V
Mode Register Set  
L, L  
H, L  
Extended Mode  
Register Set  
EMRS  
Idle  
L
L
NOP  
BST  
No Operation  
Burst Read Stop  
Device Deselect  
Auto Refresh  
Any  
Active  
Any  
H
H
H
H
H
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
X
L
H
H
X
L
H
L
DSL  
H
L
X
H
H
X
X
X
X
X
X
X
X
AREF  
SELF  
Idle  
Self Refresh Entry  
Idle  
L
L
L
H
L
X
H
X
H
X
H
X
X
X
H
X
H
X
H
X
X
Idle (Self  
Refresh)  
SELEX  
PD  
Self Refresh Exit  
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
H
L
Power Down  
Mode Entry  
Idle/  
Active(5)  
H
L
Power Down  
Mode Exit  
Any (Power  
Down)  
PDEX  
H
WDE  
WDD  
Data Write Enable  
Data Write Disable  
Active  
Active  
H
H
X
X
L
X
X
X
X
X
X
X
X
H
Notes  
1. V = Valid X = Don’t Care L = Low level H = High level  
2. CKEn signal is input level when commands are issued.  
CKEn-1 signal is input level one clock cycle before the commands are issued.  
3. These are state designated by the BA0, BA1 signals.  
4. LDM, UDM (W9425G6JH).  
5. Power Down Mode can not entry in the burst cycle.  
Publication Release Date: Aug. 27, 2013  
Revision A03  
- 17 -  
W9425G6JH  
9.2 Function Truth Table  
(Note 1)  
CURRENT  
STATE  
ADDRESS  
COMMAND  
ACTION  
NOTES  
CS RAS CAS  
WE  
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
X
H
H
H
L
X
H
L
X
X
H
L
X
DSL  
NOP/BST  
NOP  
NOP  
X
BA, CA, A10  
READ/READA ILLEGAL  
3
3
L
BA, CA, A10  
WRIT/WRITA  
ACT  
ILLEGAL  
Idle  
H
H
L
H
L
BA, RA  
Row activating  
NOP  
L
BA, A10  
PRE/PREA  
AREF/SELF  
MRS/EMRS  
DSL  
L
H
L
X
Refresh or Self refresh  
Mode register accessing  
NOP  
2
2
L
L
Op-Code  
X
H
H
H
L
X
H
L
X
X
H
L
X
X
NOP/BST  
NOP  
BA, CA, A10  
READ/READA Begin read: Determine AP  
4
4
3
5
L
BA, CA, A10  
WRIT/WRITA  
ACT  
Begin write: Determine AP  
ILLEGAL  
Row Active  
H
H
L
H
L
BA, RA  
L
BA, A10  
PRE/PREA  
AREF/SELF  
MRS/EMRS  
DSL  
Precharge  
L
H
L
X
ILLEGAL  
L
L
Op-Code  
ILLEGAL  
X
H
H
H
H
L
X
H
H
L
X
H
L
X
Continue burst to end  
Continue burst to end  
Burst stop  
X
NOP  
X
BST  
H
L
BA, CA, A10  
BA, CA, A10  
BA, RA  
BA, A10  
X
READ/READA Term burst, new read: Determine AP  
6
3
Read  
L
WRIT/WRITA  
ACT  
ILLEGAL  
H
H
L
H
L
ILLEGAL  
L
PRE/PREA  
AREF/SELF  
MRS/EMRS  
DSL  
Term burst, precharging  
ILLEGAL  
L
H
L
L
L
Op-Code  
X
ILLEGAL  
X
X
X
Continue burst to end  
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
H
L
X
NOP  
BST  
Continue burst to end  
ILLEGAL  
X
H
L
BA, CA, A10  
BA, CA, A10  
BA, RA  
BA, A10  
X
READ/READA Term burst, start read: Determine AP  
6, 7  
6
Write  
L
WRIT/WRITA  
ACT  
Term burst, start read: Determine AP  
ILLEGAL  
H
H
L
H
L
3
L
PRE/PREA  
AREF/SELF  
MRS/EMRS  
Term burst, precharging  
ILLEGAL  
8
L
H
L
L
L
Op-Code  
ILLEGAL  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
Function Truth Table, continued  
CURRENT  
ADDRESS  
COMMAND  
DSL  
ACTION  
NOTES  
CS RAS  
STATE  
CAS  
WE  
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
X
H
H
H
H
L
X
H
H
L
X
H
L
X
Continue burst to end  
Continue burst to end  
ILLEGAL  
X
X
NOP  
BST  
H
L
BA, CA, A10 READ/READA  
BA, CA, A10 WRIT/WRITA  
ILLEGAL  
Read with  
Auto-  
precharge  
L
ILLEGAL  
3
3
H
H
L
H
L
BA, RA  
ACT  
ILLEGAL  
L
BA, A10  
PRE/PREA  
AREF/SELF  
MRS/EMRS  
DSL  
ILLEGAL  
L
H
L
X
ILLEGAL  
L
L
Op-Code  
ILLEGAL  
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
Continue burst to end  
Continue burst to end  
ILLEGAL  
NOP  
BST  
H
L
BA, CA, A10 READ/READA  
BA, CA, A10 WRIT/WRITA  
ILLEGAL  
Write with  
Auto-  
precharge  
L
ILLEGAL  
H
H
L
H
L
BA, RA  
ACT  
ILLEGAL  
3
3
L
BA, A10  
PRE/PREA  
AREF/SELF  
MRS/EMRS  
DSL  
ILLEGAL  
L
H
L
X
ILLEGAL  
L
L
Op-Code  
ILLEGAL  
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
NOP-> Idle after tRP  
NOP-> Idle after tRP  
ILLEGAL  
NOP  
BST  
H
L
BA, CA, A10 READ/READA  
BA, CA, A10 WRIT/WRITA  
ILLEGAL  
3
3
3
Precharging  
L
ILLEGAL  
H
H
L
H
L
BA, RA  
BA, A10  
X
ACT  
ILLEGAL  
L
PRE/PREA  
AREF/SELF  
MRS/EMRS  
DSL  
Idle after tRP  
ILLEGAL  
L
H
L
L
L
Op-Code  
X
ILLEGAL  
X
X
X
NOP-> Row active after tRCD  
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
H
L
X
X
NOP  
BST  
NOP-> Row active after tRCD  
ILLEGAL  
H
L
BA, CA, A10 READ/READA  
BA, CA, A10 WRIT/WRITA  
ILLEGAL  
3
3
3
3
Row  
Activating  
L
ILLEGAL  
H
H
L
H
L
BA, RA  
BA, A10  
X
ACT  
ILLEGAL  
L
PRE/PREA  
AREF/SELF  
MRS/EMRS  
ILLEGAL  
L
H
L
ILLEGAL  
L
L
Op-Code  
ILLEGAL  
Publication Release Date: Aug. 27, 2013  
Revision A03  
- 19 -  
W9425G6JH  
Function Truth Table, continued  
CURRENT  
ADDRESS  
COMMAND  
ACTION  
NOTES  
CS RAS CAS  
STATE  
WE  
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
X
H
H
H
H
L
X
H
H
L
X
H
L
X
DSL  
NOP  
BST  
NOP->Row active after tWR  
NOP->Row active after tWR  
ILLEGAL  
X
X
H
L
BA, CA, A10  
READ/READA  
WRIT/WRITA  
ACT  
ILLEGAL  
3
3
3
3
Write  
L
BA, CA, A10  
ILLEGAL  
Recovering  
H
H
L
H
L
BA, RA  
ILLEGAL  
L
BA, A10  
PRE/PREA  
AREF/SELF  
MRS/EMRS  
DSL  
ILLEGAL  
L
H
L
X
ILLEGAL  
L
L
Op-Code  
ILLEGAL  
X
H
H
H
H
L
X
H
H
L
X
H
L
X
NOP->Enter precharge after tWR  
NOP->Enter precharge after tWR  
ILLEGAL  
X
NOP  
X
BST  
Write  
H
L
BA, CA, A10  
READ/READA  
WRIT/WRITA  
ACT  
ILLEGAL  
3
3
3
3
Recovering  
with Auto-  
precharge  
L
BA, CA, A10  
ILLEGAL  
H
H
L
H
L
BA, RA  
ILLEGAL  
L
BA, A10  
PRE/PREA  
AREF/SELF  
MRS/EMRS  
DSL  
ILLEGAL  
L
H
L
X
ILLEGAL  
L
L
Op-Code  
ILLEGAL  
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
X
X
NOP->Idle after tRC  
NOP->Idle after tRC  
ILLEGAL  
NOP  
BST  
Refreshing  
H
X
X
X
READ/WRIT  
ACT/PRE/PREA  
ILLEGAL  
H
L
ILLEGAL  
L
AREF/SELF/MRS/EMRS ILLEGAL  
X
X
DSL  
NOP->Row after tMRD  
L
L
L
H
H
H
H
H
L
H
L
X
X
X
NOP  
NOP->Row after tMRD  
ILLEGAL  
Mode  
Register  
Accessing  
BST  
X
READ/WRIT  
ILLEGAL  
ACT/PRE/PREA/ARE  
F/SELF/MRS/EMRS  
L
L
X
X
X
ILLEGAL  
Notes  
1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle.  
2. Illegal if any bank is not idle.  
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the  
state of that bank.  
4. Illegal if tRCD is not satisfied.  
5. Illegal if tRAS is not satisfied.  
6. Must satisfy burst interrupt condition.  
7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements.  
8. Must mask preceding data which don’t satisfy tWR  
Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data  
Publication Release Date: Aug. 27, 2013  
- 20 -  
Revision A03  
W9425G6JH  
9.3 Function Truth Table for CKE  
CKE  
CURRENT  
STATE  
ADDRESS  
ACTION  
NOTES  
CS RAS CAS  
WE  
n-1  
H
L
n
X
H
H
H
H
L
X
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID  
Exit Self Refresh->Idle after tXSNR  
Exit Self Refresh->Idle after tXSNR  
ILLEGAL  
L
Self Refresh  
L
L
L
L
X
X
X
X
X
X
X
H
L
ILLEGAL  
L
X
X
X
X
X
H
L
X
X
X
X
X
X
H
L
Maintain Self Refresh  
INVALID  
H
L
X
H
L
Power Down  
Exit Power down->Idle after tIS  
Maintain power down mode  
Refer to Function Truth Table  
Enter Power down  
Enter Power down  
Self Refresh  
L
H
H
H
H
H
H
L
H
L
2
2
1
L
All banks Idle  
L
L
L
L
H
L
L
ILLEGAL  
L
L
X
X
X
X
H
L
ILLEGAL  
X
H
L
X
X
H
L
X
X
X
H
L
Power down  
H
H
H
H
H
H
L
Refer to Function Truth Table  
Enter Power down  
Enter Power down  
ILLEGAL  
3
3
L
Row Active  
L
L
L
L
H
L
L
ILLEGAL  
L
L
X
X
ILLEGAL  
X
X
X
Power down  
Any State  
Other Than  
Listed Above  
H
H
X
X
X
X
X
Refer to Function Truth Table  
Notes  
1. Self refresh can enter only from the all banks idle state.  
2. Power Down occurs when all banks are idle; this mode is referred to as precharge power down.  
3. Power Down occurs when there is a row active in any bank; this mode is referred to as active power down.  
Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data  
Publication Release Date: Aug. 27, 2013  
Revision A03  
- 21 -  
W9425G6JH  
9.4 Simplified Stated Diagram  
SELF  
REFRESH  
SREF  
SREFX  
AREF  
MRS/EMRS  
MODE  
REGISTER  
SET  
AUTO  
REFRESH  
IDLE  
PD  
PDEX  
ACT  
POWER  
DOWN  
ACTIVE  
POWERDOWN  
PDEX  
PD  
ROW  
ACTIVE  
BST  
Read  
Read  
Write  
Write  
Read  
Write  
Read  
Read A  
Write A  
Read A  
Write A  
Read A  
PRE  
Write A  
Read A  
PRE  
PRE  
POWER  
APPLIED  
POWER  
ON  
PRE  
CHARGE  
PRE  
Automatic Sequence  
Command Sequence  
Publication Release Date: Aug. 27, 2013  
Revision A03  
- 22 -  
W9425G6JH  
10. ELECTRICAL CHARACTERISTICS  
10.1 Absolute Maximum Ratings  
PARAMETER  
Voltage on any pin relative to VSS  
Voltage on VDD/VDDQ supply relative to VSS  
Operating Temperature (-4/-5)  
Operating Temperature (-5I/-5A)  
Storage Temperature  
SYMBOL  
VIN, VOUT  
VDD, VDDQ  
TOPR  
RATING  
UNIT  
-0.5 ~ VDDQ + 0.5  
V
V
-1 ~ 3.6  
0 ~ 70  
-40 ~ 85  
-55 ~ 150  
260  
°C  
°C  
°C  
°C  
W
TOPR  
TSTG  
Soldering Temperature (10s)  
Power Dissipation  
TSOLDER  
PD  
1
Short Circuit Output Current  
IOUT  
50  
mA  
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.  
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in  
the operational sections of this specification is not implied.  
Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
10.2 Recommended DC Operating Conditions  
(TA = 0 to 70°C for -4/-5, TA = -40 to 85°C for -5I/-5A)  
SYM.  
VDD  
PARAMETER  
MIN.  
2.3  
TYP.  
MAX.  
2.7  
UNIT NOTES  
Power Supply Voltage (for -5/-5I/-5A)  
Power Supply Voltage (for -4)  
2.5  
-
V
V
V
V
2
2
2
2
VDD  
2.4  
2.7  
VDDQ  
I/O Buffer Supply Voltage (for -5/-5I/-5A)  
2.3  
2.5  
-
2.7  
VDDQ  
2.4  
2.7  
I/O Buffer Supply Voltage (for -4)  
Input reference Voltage  
VREF  
VTT  
0.49 x VDDQ  
VREF - 0.04  
VREF + 0.15  
-0.3  
0.50 x VDDQ  
0.51 x VDDQ  
VREF + 0.04  
VDDQ + 0.3  
VREF - 0.15  
VDDQ + 0.3  
V
V
V
V
V
2, 3  
2, 8  
2
Termination Voltage (System)  
Input High Voltage (DC)  
VREF  
VIH (DC)  
VIL (DC)  
VICK (DC)  
-
-
-
Input Low Voltage (DC)  
2
Differential Clock DC Input Voltage  
Input Differential Voltage.  
CLK and CLK inputs (DC)  
-0.3  
15  
VID (DC)  
0.36  
-
VDDQ + 0.6  
V
13, 15  
VIH (AC)  
VIL (AC)  
Input High Voltage (AC)  
Input Low Voltage (AC)  
Input Differential Voltage.  
CLK and CLK inputs (AC)  
VREF + 0.31  
-
-
-
-
V
V
2
2
VREF - 0.31  
VID (AC)  
0.7  
-
VDDQ + 0.6  
V
13, 15  
VX (AC)  
Differential AC input Cross Point Voltage  
Differential Clock AC Middle Point  
VDDQ/2 - 0.2  
VDDQ/2 - 0.2  
-
-
VDDQ/2 + 0.2  
VDDQ/2 + 0.2  
V
V
12, 15  
14, 15  
VISO (AC)  
Notes: VIH (DC) and VIL (DC) are levels to maintain the current logic state.  
VIH (AC) and VIL (AC) are levels to change to the new logic state.  
Publication Release Date: Aug. 27, 2013  
Revision A03  
- 23 -  
W9425G6JH  
10.3 Capacitance  
(VDD = VDDQ = 2.5V ± 0.2V, f = 1 MHz, TA = 25°C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V)  
DELTA  
UNIT  
SYMBOL  
PARAMETER  
MIN.  
MAX.  
(MAX.)  
CIN  
CCLK  
CI/O  
Input Capacitance (except for CLK pins)  
Input Capacitance (CLK pins)  
DQ, DQS, DM Capacitance  
2.0  
2.0  
4.0  
3.0  
3.0  
5.0  
0.5  
0.25  
0.5  
pF  
pF  
pF  
Note: These parameters are periodically sampled and not 100% tested.  
10.4 Leakage and Output Buffer Characteristics  
SYMBOL  
PARAMETER  
UNIT  
MIN.  
MAX.  
NOTES  
Input Leakage Current  
II (L)  
-2  
2
µA  
Any input 0V VIN VDD, VREF Pin 0V VIN 1.35V  
(All other pins not under test = 0V)  
Output Leakage Current  
IO (L)  
VOH  
VOL  
-5  
5
µA  
V
(Output disabled, 0V VOUT VDDQ)  
Output High Voltage  
VTT +0.76  
-
-
(under AC test load condition)  
Output Low Voltage  
VTT -0.76  
V
(under AC test load condition)  
Output Levels: Full drive option  
High Current  
IOH  
IOL  
-15  
15  
-
-
mA  
mA  
4, 6  
4, 6  
(VOUT = VDDQ - 0.373V, min. VREF, min. VTT  
Low Current  
(VOUT = 0.373V, max. VREF, max. VTT)  
Output Levels: Reduced drive option - 60%  
High Current  
IOHR  
-9  
-
mA  
5
(VOUT = VDDQ - 0.763V, min. VREF, min. VTT  
Low Current  
IOLR  
9
-
-
-
mA  
mA  
mA  
5
5
5
(VOUT = 0.763V, max. VREF, max. VTT)  
Output Levels: Reduced drive option - 30%  
High Current  
IOHR(30)  
IOLR(30)  
-4.5  
4.5  
(VOUT = VDDQ – 1.056V, min. VREF, min. VTT  
Low Current  
(VOUT = 1.056V, max. VREF, max. VTT)  
Publication Release Date: Aug. 27, 2013  
Revision A03  
- 24 -  
W9425G6JH  
10.5 DC Characteristics  
MAX.  
-5/-5I/-5A  
SYM.  
PARAMETER  
UNIT NOTES  
-4  
Operating current: One Bank Active-Precharge;  
tRC = tRC min; tCK = tCK min;  
DQ, DM and DQS inputs changing once per clock cycle;  
Address and control inputs changing once every two clock cycles  
IDD0  
75  
65  
7
Operating current: One Bank Active-Read-Precharge;  
Burst = 4; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA;  
Address and control inputs changing once per clock cycle.  
Precharge Power Down standby current:  
All Banks Idle; Power down mode;  
IDD1  
90  
5
80  
5
7, 9  
IDD2P  
CKE VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM  
Idle standby current:  
CS VIH min; All Banks Idle; CKE VIH min; tCK = tCK min;  
Address and other control inputs changing once per clock cycle;  
Vin VIH min or Vin VIL max for DQ, DQS and DM  
Precharge floating standby current:  
IDD2N  
IDD2F  
25  
25  
20  
20  
7
CS VIH min; all banks idle; CKE VIH min;  
Address and other control inputs changing once per clock cycle;  
VIN = VREF for DQ, DQS and DM.  
Precharge quiet standby current:  
CS VIH min; all banks idle; CKE > VIH min;  
IDD2Q  
IDD3P  
20  
20  
20  
20  
Address and other control inputs stable at > VIH min or VIL max;  
Vin = VREF for DQ, DQS and DM.  
Active Power Down standby current:  
One Bank Active; Power down mode;  
CKE VIL max; tCK = tCK min;  
mA  
Vin = VREF for DQ, DQS and DM  
Active standby current:  
CS VIH min; CKE VIH min; One Bank Active-Precharge;  
tRC = tRAS max; tCK = tCK min;  
IDD3N  
35  
30  
7
DQ, DM and DQS inputs changing twice per clock cycle;  
Address and other control inputs changing once per clock cycle  
Operating current:  
Burst = 2; Reads; Continuous burst; One Bank Active;  
Address and control inputs changing once per clock cycle;  
CL = 2; tCK = tCK min; IOUT = 0mA  
IDD4R  
IDD4W  
140  
135  
120  
115  
7, 9  
Operating current:  
Burst = 2; Write; Continuous burst; One Bank Active;  
Address and control inputs changing once per clock cycle;  
CL = 2; tCK = tCK min;  
DQ, DM and DQS inputs changing twice per clock cycle  
Auto Refresh current: tRC = tRFC min  
7
7
IDD5  
IDD6  
70  
2
65  
2
Self Refresh current: CKE 0.2V; external clock on; tCK = tCK min  
Random Read current: 4 Banks Active Read with activate every  
20nS, Auto-Precharge Read every 20 nS;  
Burst = 4; tRCD = 3; IOUT = 0mA;  
IDD7  
210  
175  
DQ, DM and DQS inputs changing twice per clock cycle;  
Address changing once per clock cycle  
Publication Release Date: Aug. 27, 2013  
Revision A03  
- 25 -  
W9425G6JH  
10.6 AC Characteristics and Operating Condition  
-4  
-5/-5I/-5A  
SYM.  
PARAMETER  
UNIT  
NOTES  
MIN.  
52  
60  
36  
16  
16  
1
MAX.  
MIN.  
MAX.  
tRC  
tRFC  
tRAS  
tRCD  
tRAP  
tCCD  
tRP  
Active to Ref/Active Command Period  
Ref to Ref/Active Command Period  
Active to Precharge Command Period  
Active to Read/Write Command Delay Time  
Active to Read with Auto-precharge Enable  
Read/Write(a) to Read/Write(b) Command Period  
Precharge to Active Command Period  
Active(a) to Active(b) Command Period  
Write Recovery Time  
55  
70  
40  
15  
15  
1
70000  
100000  
nS  
tCK  
nS  
16  
8
15  
10  
15  
tRRD  
tWR  
15  
(tWR/tCK)  
+
(tRP/tCK)  
(tWR/tCK)  
+
(tRP/tCK)  
tDAL  
Auto-precharge Write Recovery + Precharge Time  
CL = 2  
tCK  
18  
-
-
4
4
-
7.5  
6
5
12  
12  
12  
-
CL = 2.5  
-
10  
10  
tCK  
CLK Cycle Time  
CL = 3  
CL = 4  
-
nS  
tAC  
-0.7  
-0.6  
0.7  
0.6  
-0.7  
-0.6  
0.7  
0.6  
16  
16  
Data Access Time from CLK, CLK  
tDQSCK  
DQS Output Access Time from CLK, CLK  
tDQSQ  
tCH  
Data Strobe Edge to Output Data Edge Skew  
CLk High Level Width  
0.4  
0.55  
0.55  
0.4  
0.55  
0.55  
0.45  
0.45  
min  
(tCL,tCH)  
tHP-0.5  
0.9  
0.45  
0.45  
Min,  
(tCL,tCH)  
tHP-0.5  
0.9  
tCK  
nS  
tCK  
nS  
11  
tCL  
CLK Low Level Width  
tHP  
CLK Half Period (minimum of actual tCH, tCL)  
tQH  
tRPRE  
tRPST  
tDS  
DQ Output Data Hold Time from DQS  
DQS Read Preamble Time  
1.1  
0.6  
1.1  
0.6  
11  
DQS Read Postamble Time  
0.4  
0.4  
DQ and DM Setup Time to DQS, slew rate 0.5V/nS  
DQ and DM Hold Time to DQS, slew rate 0.5V/nS  
DQ and DM Input Pulse Width (for each input)  
DQS Input High Pulse Width  
0.4  
0.4  
0.4  
0.4  
tDH  
tDIPW  
tDQSH  
tDQSL  
tDSS  
tDSH  
1.75  
0.35  
0.35  
0.2  
1.75  
0.35  
0.35  
0.2  
DQS Input Low Pulse Width  
tCK  
11  
11  
DQS Falling Edge to CLK Setup Time  
DQS Falling Edge Hold Time from CLK  
0.2  
0
0.2  
0
tWPRES Clock to DQS Write Preamble Set-up Time  
nS  
tCK  
tWPRE  
tWPST  
tDQSS  
tIS  
DQS Write Preamble Time  
0.25  
0.4  
0.85  
0.6  
0.25  
0.4  
0.72  
0.6  
DQS Write Postamble Time  
0.6  
1.15  
0.6  
1.25  
Write Command to First DQS Latching Transition  
Input Setup Time (fast slew rate)  
Input Hold Time (fast slew rate)  
Input Setup Time (slow slew rate)  
Input Hold Time (slow slew rate)  
19, 21-23  
19, 21-23  
20-23  
tIH  
0.6  
0.7  
0.6  
0.7  
tIS  
tIH  
0.7  
0.7  
20-23  
nS  
tIPW  
Control & Address Input Pulse Width (for each input)  
2.2  
2.2  
tHZ  
tLZ  
0.7  
0.7  
Data-out High-impedance Time from CLK, CLK  
-0.7  
0.7  
1.5  
-0.7  
0.7  
1.5  
Data-out Low-impedance Time from CLK, CLK  
tT(SS)  
tWTR  
tXSNR  
tXSRD  
tREFI  
tMRD  
SSTL Input Transition  
0.5  
2
0.5  
2
Internal Write to Read Command Delay  
Exit Self Refresh to non-Read Command  
Exit Self Refresh to Read Command  
Refresh Interval Time (8K/ 64mS)  
Mode Register Set Cycle Time  
tCK  
nS  
tCK  
µS  
nS  
72  
200  
75  
200  
7.8  
7.8  
17  
8
10  
Publication Release Date: Aug. 27, 2013  
Revision A03  
- 26 -  
W9425G6JH  
10.7 AC Test Conditions  
PARAMETER  
SYMBOL  
VIH  
VALUE  
UNIT  
V
Input High Voltage (AC)  
VREF + 0.31  
VREF - 0.31  
0.5 x VDDQ  
0.5 x VDDQ  
Vx (AC)  
Input Low Voltage (AC)  
VIL  
V
Input Reference Voltage  
Termination Voltage  
VREF  
VTT  
V
V
Differential Clock Input Reference Voltage  
VR  
V
VID (AC)  
1.5  
V
V
Input Difference Voltage. CLK and CLK Inputs (AC)  
Output Timing Measurement Reference Voltage  
VOTR  
0.5 x VDDQ  
VDDQ  
VTT  
VIH min (AC)  
V SWING(MAX)  
VREF  
50 Ω  
VIL max (AC)  
VSS  
Output  
T
T
Output  
V(out)  
30pF  
SLEW = (VIH min (AC) - VILmax (AC)) /  
T
Timing Reference Load  
Notes:  
(1) Conditions outside the limits listed under “Absolute Maximum Ratings” may cause permanent damage to the device.  
(2)  
(3)  
(4)  
(5)  
(6)  
All voltages are referenced to VSS, VSSQ.  
Peak to peak AC noise on VREF may not exceed ±2% VREF(DC).  
VOH = 1.95V, VOL = 0.35V  
VOH = 1.9V, VOL = 0.4V  
The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V.  
The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V.  
(7)  
(8)  
(9)  
These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values  
of tCK and tRC.  
VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set  
equal to VREF and must track variations in the DC level of VREF.  
These parameters depend on the output loading. Specified values are obtained with the output open.  
(10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed  
slope.  
(11) IF the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to  
the nearest decimal place.  
(i.e., tDQSS = 1.25 tCK, tCK = 5 nS, 1.25 5 nS = 6.25 nS is rounded up to 6.2 nS.)  
Publication Release Date: Aug. 27, 2013  
- 27 -  
Revision A03  
W9425G6JH  
(12) VX is the differential clock cross point voltage where input timing measurement is referenced.  
(13) VID is magnitude of the difference between CLK input level and CLK input level.  
(14) VISO means {VICK(CLK)+VICK( CLK )}/2.  
(15) Refer to the figure below.  
CLK  
VX  
VX  
VICK  
VICK  
VX  
VX  
VX  
VID(AC)  
CLK  
VSS  
VICK  
VICK  
VID(AC)  
0 V Differential  
VISO  
VSS  
VISO(min)  
VISO(max)  
(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.  
(17) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.  
(18) tDAL = (tWR/tCK) + (tRP/tCK)  
For each of the terms above, if not already an integer, round to the next highest integer.  
Example: For -5 speed grade at CL=2.5 and tCK=6 nS  
tDAL = ((15 nS / 6 nS) + (15 nS / 6 nS)) clocks = ((3) + (3)) clocks = 6 clocks  
(19) For command/address input slew rate ≥1.0 V/nS.  
(20) For command/address input slew rate ≥0.5 V/nS and <1.0 V/nS.  
(21) For CLK & CLK slew rate ≥1.0 V/nS (single--ended).  
(22) These parameters guarantee device timing, but they are not necessarily tested on each device. They may be  
guaranteed by device design or tester correlation.  
(23) Slew Rate is measured between VOH(ac) and VOL(ac).  
Publication Release Date: Aug. 27, 2013  
- 28 -  
Revision A03  
W9425G6JH  
11. SYSTEM CHARACTERISTICS FOR DDR SDRAM  
The following specification parameters are required in systems using DDR500, DDR400 & DDR333  
devices to ensure proper system performance. These characteristics are for system simulation  
purposes and are guaranteed by design.  
11.1 Table 1: Input Slew Rate for DQ, DQS, and DM  
AC CHARACTERISTICS  
PARAMETER  
DDR500  
DDR400  
SYM.  
UNIT NOTES  
MIN. MAX. MIN. MAX.  
DQ/DM/DQS input slew rate measured between  
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)  
DCSLEW  
0.5  
4.0  
0.5  
4.0  
V/nS  
a, m  
11.2 Table 2: Input Setup & Hold Time Derating for Slew Rate  
INPUT SLEW RATE  
0.5 V/nS  
ΔtIS  
0
ΔtIH  
0
UNIT  
pS  
NOTES  
i
i
i
0.4 V/nS  
+50  
+100  
0
pS  
0.3 V/nS  
0
pS  
11.3 Table 3: Input/Output Setup & Hold Time Derating for Slew Rate  
INPUT SLEW RATE  
0.5 V/nS  
ΔtDS  
0
ΔtDH  
UNIT  
pS  
NOTES  
0
0
0
k
k
k
0.4 V/nS  
+75  
+150  
pS  
0.3 V/nS  
pS  
11.4 Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate  
INPUT SLEW RATE  
±0.0 nS/V  
ΔtDS  
0
ΔtDH  
UNIT  
pS  
NOTES  
0
0
0
j
j
j
±0.25 nS/V  
+50  
+100  
pS  
±0.5 nS/V  
pS  
11.5 Table 5: Output Slew Rate Characteristics (X16 Devices only)  
SLEW RATE  
CHARACTERISTIC  
TYPICAL  
RANGE (V/NS)  
MINIMUM  
(V/NS)  
MAXIMUM  
(V/NS)  
NOTES  
Pullup Slew Rate  
1.2 ~ 2.5  
1.2 ~ 2.5  
0.7  
0.7  
5.0  
5.0  
a, c, d, f, g, h  
b, c, d, f, g, h  
Pulldown Slew Rate  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
11.6 Table 6: Output Slew Rate Matching Ratio Characteristics  
SLEW RATE CHARACTERISTIC  
PARAMETER  
DDR500  
DDR400  
NOTES  
MIN.  
0.67  
MAX.  
MIN.  
MAX.  
Output Slew Rate Matching Ratio (Pullup to Pulldown)  
1.5  
0.67  
1.5  
e, m  
11.7 Table 7: AC Overshoot/Undershoot Specification for Address and Control Pins  
SPECIFICATION  
PARAMETER  
DDR500  
DDR400  
Maximum peak amplitude allowed for overshoot  
Maximum peak amplitude allowed for undershoot  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
The area between the overshoot signal and VDD must be less than  
or equal to Max. area in Figure 3  
4.5 V-nS  
4.5 V-nS  
4.5 V-nS  
4.5 V-nS  
The area between the undershoot signal and GND must be less than  
or equal to Max. area in Figure 3  
VDD  
Overshoot  
5
Max. amplitude = 1.5V  
4
3
2
Max. area  
1
0
-1  
-2  
Max. amplitude = 1.5V  
-3  
GND  
-4  
-5  
0
0.5 0.68751.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.06.3125 6.5 7.0  
Time (nS)  
Undershoot  
Figure 3: Address and Control AC Overshoot and Undershoot Definition  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
11.8 Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins  
SPECIFICATION  
PARAMETER  
DDR500  
DDR400  
Maximum peak amplitude allowed for overshoot  
Maximum peak amplitude allowed for undershoot  
1.2 V  
1.2 V  
1.2 V  
1.2 V  
The area between the overshoot signal and VDD must be less than  
or equal to Max. area in Figure 4  
2.4 V-nS  
2.4 V-nS  
2.4 V-nS  
2.4 V-nS  
The area between the undershoot signal and GND must be less than  
or equal to Max. area in Figure 4  
VDD  
Overshoot  
5
Max. amplitude = 1.2V  
4
3
2
Max. area  
1
0
-1  
-2  
Max. amplitude = 1.2V  
-3  
GND  
-4  
-5  
0
0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0  
Time (nS)  
Undershoot  
Figure 4: DQ/DM/DQS AC Overshoot and Undershoot Definition  
Publication Release Date: Aug. 27, 2013  
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W9425G6JH  
11.9 System Notes:  
a. Pullup slew rate is characterized under the test conditions as shown in Figure 1.  
Test point  
Output  
50 Ω  
VSSQ  
Figure 1: Pullup slew rate test load  
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.  
VDDQ  
50 Ω  
Output  
Test point  
Figure 2: Pulldown slew rate test load  
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV ± 250 mV)  
Pulldown slew rate is measured between (VDDQ/2 + 320 mV ± 250 mV)  
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs  
switching and only one output switching.  
Example: For typical slew rate, DQ0 is switching  
For minimum slew rate, all DQ bits are switching worst case pattern  
For maximum slew rate, only one DQ is switching from either high to low, or low to high  
The remaining DQ bits remain the same as for previous state  
d. Evaluation conditions  
Typical:  
25°C (T Ambient), VDDQ = nominal, typical process  
Minimum: 70°C (T Ambient), VDDQ = minimum, slow-slow process  
Maximum: 0°C (T Ambient), VDDQ = maximum, fast-fast process  
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and  
voltage, over the entire temperature and voltage range. For a given output, it represents the  
maximum difference between pullup and pulldown drivers due to process variation.  
Publication Release Date: Aug. 27, 2013  
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W9425G6JH  
f. Verified under typical conditions for qualification purposes.  
g. TSOP II package devices only.  
h. Only intended for operation up to 266 Mbps per pin.  
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below  
0.5 V/nS as shown in Table 2. The Input slew rate is based on the lesser of the slew rates  
determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.  
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew  
rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise,  
fall rate and DC-DC delta rise, fall rate. Input slew rate is based on the lesser of the slew rates  
determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.  
The delta rise/fall rate is calculated as:  
{1/(Slew Rate1)}-{1/(slew Rate2)}  
For example: If Slew Rate 1 is 0.5 V/nS and Slew Rate 2 is 0.4 V/nS, then the delta rise, fall rate is  
-0.5 nS/V. Using the table given, this would result in the need for an increase in tDS and tDH of 100  
pS.  
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/nS. The  
I/O slew rate is based on the lesser of the AC-AC slew rate and the DC-DC slew rate. The input  
slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC)  
to VIL(DC), and similarly for rising transitions.  
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve  
setup and hold times. Signal transitions through the DC region must be monotonic.  
Publication Release Date: Aug. 27, 2013  
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Revision A03  
W9425G6JH  
12. TIMING WAVEFORMS  
12.1 Command Input Timing  
tCK  
tCK  
tCH  
tCL  
CLK  
CLK  
tIS  
tIS  
tIS  
tIS  
tIH  
tIH  
tIH  
tIH  
CS  
RAS  
CAS  
WE  
tIS  
tIH  
A0~A12  
BA0,1  
Refer to the Command Truth Table  
12.2 Timing of the CLK Signals  
tCH  
tCL  
VIH  
VIH(AC)  
VIL(AC)  
CLK  
CLK  
VIL  
tT  
tT  
tCK  
CLK  
CLK  
VIH  
VIL  
VX  
VX  
VX  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
12.3 Read Timing (Burst Length = 4)  
tCH  
tCL  
tCK  
CLK  
CLK  
tIS  
tIH  
CMD  
READ  
tIS  
tIH  
ADD  
Col  
tDQSCK  
tDQSCK  
tRPST  
tDQSCK  
CAS Latency = 2  
DQS  
tRPRE  
Hi-Z  
Hi-Z  
Hi-Z  
tQH  
Preamble  
Postamble  
tDQSQ  
tDQSQ  
tQH  
tDQSQ  
Hi-Z  
Hi-Z  
Hi-Z  
Output  
(Data)  
QA0  
QA1  
QA2  
QA3  
tAC  
tLZ  
tHZ  
tDQSCK  
tDQSCK  
tRPST  
tDQSCK  
tRPRE  
CAS Latency = 3  
DQS  
Hi-Z  
Hi-Z  
tQH  
Preamble  
Postamble  
tDQSQ  
tDQSQ  
tQH  
tDQSQ  
Output  
(Data)  
QA0  
QA1  
QA2  
QA3  
tAC  
tLZ  
tHZ  
Notes: The correspondence of LDQS, UDQS to DQ. (W9425G6JH)  
LDQS  
UDQS  
DQ0~7  
DQ8~15  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
12.4 Write Timing (Burst Length = 4)  
tCH  
tCL  
tCK  
CLK  
CLK  
tIS  
tIH  
WRIT  
CMD  
tIS  
tIH  
tDSH  
tDSS  
tDSH  
tDSS  
ADD  
Col  
x4, x8 device  
DQS  
tWPRES  
tDQSH  
tDQSL  
tDQSH  
tWPST  
tWPRE  
Postamble  
tDH  
Preamble  
tDS  
tDS  
tDS  
tDH  
tDH  
Input  
(Data)  
DA0  
DA1  
DA2  
DA3  
tDQSS  
tDSH  
tDSS  
tDSH  
tDSS  
x16 device  
LDQS  
tWPRES  
tDQSH  
tDQSL  
tDQSH  
tWPST  
tWPRE  
Postamble  
tDH  
Preamble  
tDS  
tDS  
tDS  
tDH  
tDH  
DQ0~7  
DA0  
DA1  
DA2  
DA3  
tDQSS  
tDSH  
tDSS  
tDSH  
tDSS  
tWPRES  
tDQSL  
tDQSH  
tWPST  
tDQSH  
tWPRE  
UDQS  
Preamble  
tDS  
Postamble  
tDH  
tDS  
tDS  
tDH  
tDH  
DA0  
DA1  
DA2  
DA3  
DQ8~15  
tDQSS  
Note: x16 has two DQSs (UDQS for upper byte and LDQS for lower byte). Even if one of the 2 bytes is not used, both UDQS  
and LDQS must be toggled.  
Publication Release Date: Aug. 27, 2013  
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Revision A03  
W9425G6JH  
12.5 DM, DATA MASK (W9425G6JH)  
CLK  
CLK  
WRIT  
CMD  
LDQS  
tDS  
tDS  
tDH  
tDH  
LDM  
DQ0~DQ7  
UDQS  
tDIPW  
D0  
D1  
D3  
Masked  
tDIPW  
tDH  
tDS  
tDS  
tDH  
UDM  
tDIPW  
D2  
D3  
D0  
DQ8~DQ15  
Masked  
tDIPW  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
12.6 Mode Register Set (MRS) Timing  
CLK  
CLK  
tMRD  
CMD  
ADD  
MRS  
NEXT CMD  
Register Set data  
Burst Length  
A0  
A1  
A2  
A2  
0
A1  
0
A0  
0
Sequential  
Interleaved  
Burst Length  
Addressing Mode  
CAS Latency  
Reserved  
Reserved  
0
0
1
2
4
8
2
4
8
0
1
0
0
1
1
A3  
A4  
1
0
0
1
0
1
Reserved  
Reserved  
1
1
0
A5  
A6  
A7  
A8  
1
1
1
Addressing Mode  
A3  
0
Sequential  
Interleaved  
Reserved  
"0"  
1
DLL Reset  
CAS Latency  
Reserved  
A6  
0
A5  
0
A4  
0
"0"  
"0"  
"0"  
"0"  
"0"  
"0"  
A9  
0
0
1
A10  
A11  
A12  
BA0  
BA1  
2
3
0
1
0
Reserved  
0
1
1
1
0
0
4
Reserved  
2.5  
1
0
1
1
1
0
Mode Register Set  
or  
Extended Mode  
Register Set  
Reserved  
1
1
1
DLL Reset  
No  
A8  
0
Yes  
1
* "Reserved" should stay "0" during MRS cycle.  
MRS or EMRS  
Regular MRS cycle  
Extended MRS cycle  
BA1  
BA0  
0
0
1
1
0
1
0
1
Reserved  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
12.7 Extend Mode Register Set (EMRS) Timing  
CLK  
CLK  
tMRD  
CMD  
ADD  
EMRS  
NEXT CMD  
Register Set data  
DLL Switch  
A0  
0
A0  
DLL Switch  
Enable  
Disable  
1
A1  
A2  
Buffer Strength  
"0"  
"0"  
"0"  
"0"  
A3  
A4  
A5  
A6  
A1  
0
A6  
0
Buffer Strength  
100% Strength  
60% Strength  
Reserved  
Reserved  
1
0
0
1
1
1
30% Strength  
Buffer Strength  
A7  
A8  
A9  
"0"  
"0"  
"0"  
BA0  
MRS or EMRS  
Regular MRS cycle  
Extended MRS cycle  
BA1  
0
0
1
Reserved  
0
0
1
1
1
A10 "0"  
A11 "0"  
A12 "0"  
Mode Register Set  
or  
"0"  
BA0  
Extended Mode  
Register Set  
BA1 "0"  
* "Reserved" should stay "0" during EMRS cycle  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
12.8 Auto-precharge Timing (Read Cycle, CL = 2)  
1) tRCD (READA) tRAS (MIN) – (BL/2) tCK  
tRAS  
tRP  
CLK  
CLK  
BL=2  
ACT  
READA  
ACT  
AP  
CMD  
DQS  
DQ  
Q0 Q1  
BL=4  
ACT  
READA  
AP  
ACT  
CMD  
DQS  
DQ  
Q0 Q1 Q2 Q3  
BL=8  
READA  
ACT  
AP  
ACT  
CMD  
DQS  
DQ  
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7  
Notes: CL=2 shown; same command operation timing with CL = 2,5 and CL=3  
In this case, the internal precharge operation begin after BL/2 cycle from READA command.  
AP  
Represents the start of internal precharging.  
The Read with Auto-precharge command cannot be interrupted by any other command.  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
12.9 Auto-precharge Timing (Read cycle, CL = 2), continued  
2) tRCD/RAP(min) tRCD (READA) tRAS (min) – (BL/2) tCK  
tRAS  
tRP  
CLK  
CLK  
BL=2  
ACT  
READA  
ACT  
AP  
CMD  
tRAP  
tRCD  
DQS  
DQ  
Q0 Q1  
BL=4  
ACT  
READA  
AP  
ACT  
CMD  
DQS  
DQ  
tRAP  
tRCD  
Q0 Q1 Q2 Q3  
BL=8  
ACT  
READA  
AP  
ACT  
CMD  
tRAP  
tRCD  
DQS  
DQ  
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7  
Notes: CL2 shown; same command operation timing with CL = 2.5, CL=3.  
In this case, the internal precharge operation does not begin until after tRAS (min) has command.  
AP  
Represents the start of internal precharging.  
The Read with Auto-precharge command cannot be interrupted by any other command.  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
12.10 Auto-precharge Timing (Write Cycle)  
CLK  
CLK  
tDAL  
BL=2  
WRITA  
AP  
ACT  
CMD  
DQS  
DQ  
D0 D1  
tDAL  
AP  
BL=4  
CMD  
DQS  
DQ  
WRITA  
ACT  
D0 D1 D2 D3  
tDAL  
AP  
BL=8  
WRITA  
CMD  
ACT  
DQS  
DQ  
D0 D1 D2 D3 D4 D5 D6 D7  
The Write with Auto-precharge command cannot be interrupted by any other command.  
AP  
Represents the start of internal precharging.  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
12.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8)  
CLK  
CLK  
CMD  
ADD  
ACT  
READ A  
READ B  
READ C  
READ D  
READ E  
tRCD  
tCCD  
COl,Add,A  
tCCD  
tCCD  
tCCD  
Row Address  
Col,Add,B  
Col,Add,C  
Col,Add,D  
Col,Add,E  
DQS  
DQ  
QA0 QA1 QB0 QB1 QC0  
12.12 Burst Read Stop (BL = 8)  
CLK  
CLK  
CMD  
READ  
BST  
CAS Latency = 2  
DQS  
CAS Latency  
Q3 Q4 Q5  
DQ  
Q0  
Q1  
Q2  
CAS Latency = 3  
DQS  
CAS Latency  
DQ  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
12.13 Read Interrupted by Write & BST (BL = 8)  
CLK  
CLK  
CAS Latency = 2  
CMD  
READ  
BST  
WRIT  
DQS  
DQ  
Q0 Q1 Q2 Q3 Q4 Q5  
D0 D1 D2 D3 D4 D5 D6 D7  
Burst Read cycle must be terminated by BST Command to avoid I/O conflict.  
12.14 Read Interrupted by Precharge (BL = 8)  
CLK  
CLK  
CMD  
READ  
PRE  
CAS Latency = 2  
DQS  
CAS Latency  
DQ  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
CAS Latency = 3  
DQS  
CAS Latency  
DQ  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
12.15 Write Interrupted by Write (BL = 2, 4, 8)  
CLK  
CLK  
ACT  
WRIT A  
WRIT B  
WRIT C  
WRIT D  
WRIT E  
CMD  
tRCD  
tCCD  
tCCD  
tCCD  
tCCD  
ADD  
DQS  
Row Address  
COl. Add. A  
Col.Add.B  
Col. Add. C  
Col. Add. D  
Col. Add. E  
DA0  
DA1  
DB0  
DB1  
DC0  
DC1  
DD0  
DD1  
DQ  
12.16 Write Interrupted by Read (CL = 2, BL = 8)  
CLK  
CLK  
CMD  
WRIT  
READ  
DQS  
DM  
tWTR  
D3  
D0  
D1  
D2  
D4  
D5  
D6  
D7  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
DQ  
Data must be  
masked by DM  
Data masked by READ command,  
DQS input ignored.  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
12.17 Write Interrupted by Read (CL = 3, BL = 4)  
CLK  
CLK  
CMD  
DQS  
WRIT  
READ  
DM  
DQ  
tWTR  
D3  
D0  
D1  
D2  
Q0  
Q1  
Q2  
Q3  
Data must be masked by DM  
12.18 Write Interrupted by Precharge (BL = 8)  
CLK  
CLK  
CMD  
DQS  
WRIT  
PRE  
ACT  
tWR  
tRP  
DM  
DQ  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
Data must be  
masked by DM  
Data masked by PRE  
command, DQS input ignored.  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
12.19 2 Bank Interleave Read Operation (CL = 2, BL = 2)  
CLK  
CLK  
tRC(b)  
tRC(a)  
tRRD  
tRRD  
ACTa  
ACTb  
READAa  
READAb  
tRP(a)  
ACTa  
ACTb  
CMD  
tRCD(a)  
tRAS(a)  
tRCD(b)  
tRAS(b)  
tRP(b)  
DQS  
DQ  
Preamble  
CL(a)  
Postamble  
CL(b)  
Preamble  
Postamble  
Q0a Q1a  
Q0b Q1b  
ACTa/b  
: Bank Act. CMD of bank a/b  
READAa/b : Read with Auto Pre.CMD of bank a/b  
APa/b : Auto Pre. of bank a/b  
APa  
APb  
12.20 2 Bank Interleave Read Operation (CL = 2, BL = 4)  
CLK  
CLK  
tRC(b)  
tRC(a)  
tRRD  
tRRD  
CMD  
ACTa  
ACTb  
READAa  
READAb  
ACTa  
ACTb  
tRCD(a)  
tRP(a)  
tRAS(a)  
tRCD(b)  
tRP(b)  
tRAS(b)  
DQS  
DQ  
Preamble  
CL(a)  
Postamble  
CL(b)  
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b  
ACTa/b  
: Bank Act. CMD of bank a/b  
READAa/b : Read with Auto Pre.CMD of bank a/b  
APa/b : Auto Pre. of bank a/b  
APa  
APb  
Publication Release Date: Aug. 27, 2013  
Revision A03  
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W9425G6JH  
12.21 4 Bank Interleave Read Operation (CL = 2, BL = 2)  
CLK  
CLK  
tRC(a)  
tRRD  
tRRD  
tRRD  
tRRD  
CMD  
ACTa  
ACTb  
ACTc  
READAa  
ACTd  
READAb  
ACTa  
READAc  
tRCD(a)  
tRAS(a)  
tRP  
tRCD(b)  
tRAS(b)  
tRCD(c)  
tRAS(c)  
tRCD(d)  
tRAS(d)  
DQS  
DQ  
Preamble  
Postamble Preamble  
CL(b)  
CL(a)  
Q0a Q1a  
Q0b Q1b  
ACTa/b/c/d  
: Bank Act. CMD of bank a/b/c/d  
READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d  
APa/b/c/d : Auto Pre. of bank a/b/c/d  
APa  
APb  
12.22 4 Bank Interleave Read Operation (CL = 2, BL = 4)  
CLK  
CLK  
tRC(a)  
tRRD  
tRRD  
tRRD  
tRRD  
ACTa  
ACTb  
tRCD(a)  
READAa  
ACTc  
READAb  
ACTd  
READAc  
ACTa  
READAd  
CMD  
tRP(a)  
tRAS(a)  
tRCD(b)  
tRAS(b)  
tRCD(c)  
tRAS(c)  
tRCD(d)  
tRAS(d)  
DQS  
DQ  
Preamble  
CL(a)  
CL(b)  
CL(c)  
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b Q0c Q1c  
ACTa/b/c/d  
: Bank Act. CMD of bank a/b/c/d  
READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d  
APa/b/c/d : Auto Pre. of bank a/b/c/d  
APa  
APb  
APc  
Publication Release Date: Aug. 27, 2013  
Revision A03  
- 48 -  
W9425G6JH  
12.23 Auto Refresh Cycle  
CLK  
CLK  
PREA  
NOP  
tRP  
AREF  
NOP  
tRFC  
AREF  
CMD  
CMD  
NOP  
tRFC  
Note: CKE has to be kept “High” level for Auto-Refresh cycle.  
12.24 Precharged/Active Power Down Mode Entry and Exit Timing  
CLK  
CLK  
tIH  
tIS  
tCK  
tIH  
tIS  
CKE  
Precharge/Activate  
Note 1,2  
Entry  
Exit  
NOP  
CMD  
CMD  
NOP  
CMD  
NOP  
Note:  
1. If power down occurs when all banks are idle, this mode is referred to as precharge power down.  
2. If power down occurs when there is a row active in any bank, this mode is referred to as active power down.  
12.25 Input Clock Frequency Change during Precharge Power Down Mode Timing  
CLK  
CLK  
DLL  
RESET  
NOP  
NOP  
NOP  
tIS  
NOP  
NOP  
CMD  
CMD  
CKE  
Frequency Change  
Occurs here  
200 clocks  
tRP  
Stable new clock  
before power down exit  
Minmum 2 clocks  
required before  
changing frequency  
Publication Release Date: Aug. 27, 2013  
Revision A03  
- 49 -  
W9425G6JH  
12.26 Self Refresh Entry and Exit Timing  
CLK  
CLK  
tIH  
tIS  
tIH  
tIS  
CKE  
CMD  
PREA  
NOP  
tRP  
SELF  
SELEX  
NOP  
CMD  
Exit  
Entry  
tXSNR  
tXSRD  
SELF  
SELFX  
NOP  
ACT  
NOP  
READ  
NOP  
Entry  
Exit  
Note: If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.  
Publication Release Date: Aug. 27, 2013  
Revision A03  
- 50 -  
W9425G6JH  
13. PACKAGE SPECIFICATION  
Package Outline 66L TSOP – 400 mil  
66  
34  
E
E1  
1
33  
DETAIL “A”  
e
b
RAD. R1  
RAD. R  
D
ZD  
A2  
A1  
A
θ1  
θ
L
c
L1  
Y
SEATING PLANE  
DETAIL “A”  
Controlling Dimension : Millimeters  
DIMENSION (mm)  
DIMENSION (inch)  
SYMBOL  
MIN.  
NOM.  
---  
MAX.  
MIN.  
NOM.  
---  
MAX.  
0.047  
---  
1.20  
---  
A
0.05  
0.95  
0.22  
0.12  
22.09  
11.56  
0.15  
1.05  
0.38  
0.21  
22.35  
11.96  
10.29  
0.002  
0.037  
0.009  
0.005  
0.870  
0.455  
0.395  
0.006  
0.041  
0.015  
0.008  
0.880  
0.471  
0.405  
A1  
A2  
b
c
D
E
E1  
e
---  
1.00  
---  
---  
0.039  
---  
---  
---  
22.22  
11.76  
10.16  
0.65 BASIC  
0.875  
0.463  
0.400  
0.026 BASIC  
10.03  
L
L1  
R
R1  
ZD  
θ
0.40  
0.50  
0.80 BASIC  
---  
0.60  
0.016  
0.020  
0.031 BASIC  
---  
0.024  
0.25  
---  
0.010  
---  
0.12  
0.12  
0.005  
0.005  
---  
0.71 REF  
---  
---  
0.028 REF  
---  
8°  
20°  
0.10  
8°  
20°  
0°  
10°  
---  
0°  
10°  
---  
---  
---  
---  
---  
θ1  
Y
0.004  
Publication Release Date: Aug. 27, 2013  
Revision A03  
- 51 -  
W9425G6JH  
14. REVISION HISTORY  
VERSION  
A01  
DATE  
PAGE  
DESCRIPTION  
Initial formally datasheet  
May 26, 2010  
Feb. 29, 2012  
Aug. 27, 2013  
All  
A02  
4, 5, 23, 25, 26 Added -5A automotive grade parts  
Added order information table  
A03  
4
Important Notice  
Winbond products are not designed, intended, authorized or warranted for use as components  
in systems or equipment intended for surgical implantation, atomic energy control  
instruments, airplane or spaceship instruments, transportation instruments, traffic signal  
instruments, combustion control instruments, or for other applications intended to support or  
sustain life. Further more, Winbond products are not intended for applications wherein failure  
of Winbond products could result or lead to a situation wherein personal injury, death or  
severe property or environmental damage could occur.  
Winbond customers using or selling these products for use in such applications do so at their  
own risk and agree to fully indemnify Winbond for any damages resulting from such improper  
use or sales.  
Publication Release Date: Aug. 27, 2013  
- 52 -  
Revision A03  

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