W9451GBDA-7 [WINBOND]

DDR DRAM Module, 64MX64, 0.75ns, CMOS, DIMM-184;


型号：	W9451GBDA-7
厂家：	WINBOND
描述：	DDR DRAM Module, 64MX64, 0.75ns, CMOS, DIMM-184 时钟动态存储器双倍数据速率内存集成电路
文件：	总15页 (文件大小：218K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W9451GBDA

512MB (64M

´ 64) DDR SDRAM DIMM

1. GENERAL DESCRIPTION

The W9451GBDA is a 512MB Double Data Rate Synchronous Dynamic RAM (DDR SDRAM) memory

modules. It is organized in a 64M x 64 bit configuration using eight pieces of Winbond W942508BH

(64M x 8 bits) DDR SDRAMs and assembled on a JEDEC standard 184-pin DIMM PCB.

To provide high data bandwidth, W9451GBDA uses a double data rate architecture to transfer two

data words per clock cycle and delivers a data bandwidth of up to 2.1G (DDR266) bytes per second. It

is ideal for high performance systems that require fast data transfer memory modules.

By reading the Serial Presence-Detect (SPD), the system can identify the module type, DDR SDRAM

timing parameters and other necessary information to optimize system setting and maximize its

performance.

2. FEATURES

JEDEC standard 184-pin, Dual In-Line Memory Module (DIMM)

Comply to DDR266 and DDR200 specification

Two memory rows on this module

Differential clock inputs (CLK and CLK )

Double Data Rate architecture, two data transfers per clock cycle

CAS Latency: 2 and 2.5

Burst Lengths: 2, 4, 8

Auto Refresh and Self Refresh

8K refresh cycles / 64 ms

Serial Presence Detect with EEPROM

Interface: SSTL-2

Power supply: 2.5V ±0.2V

PCB height: 1.25 inches

3. AVAILABLE PART NUMBERS

MODULE PART NUMBER

SPEED

W9451GBDA-7

DDR266/CL2

W9451GBDA-75

DDR266/CL2.5

Publication Release Date: March 15, 2002

Revision A1

- 1 -

W9451GBDA

4. PIN ASSIGNMENT

FONT

BACK

RAS

VREF

VDDQ

VSS

124 VSS

125 A6

154

DQ0

DQ24

DQ4

155 DQ45

156 VDDQ

VSS

DQ41

DQ5

126 DQ28

127 DQ29

DQ1

DQ25

VDDQ

157

CS0

CAS

VSS

DQS0

DQS3

DQS9

128 VDDQ

158

CS1

DQ2

VDD

DQ3

DQS5

DQ42

DQ43

VDD

DQ6

DQ7

129 DQS12

130 A3

159 DQS14

160 VSS

VDD

DQ26

DQ27

100 VSS

101 NC

131 DQ30

132 VSS

161 DQ46

162 DQ47

163 *S3

*S2

102 NC

133 DQ31

134 *CB4

135 *CB5

136 VDDQ

137 CLK0

VSS

DQ48

DQ49

VSS

103 *A13

104 VDDQ

105 DQ12

106 DQ13

164 VDDQ

165 DQ52

166 DQ53

167 NC

DQ8

DQ9

DQS1

*CB0

*CB1

CLK2

VDDQ

VDD

107 DQS10

138

168 VDD

CLK0

CKL1

*DQS8

VDDQ

108 VDD

139 VSS

169 DQS15

170 DQ54

DQS6

109 DQ14

140 *DQS17

CLK1

VSS

*CB2

VSS

DQ50

DQ51

VSS

110 DQ15

111 CKE1

112 VDDQ

113 *BA2

114 DQ20

115 A12

141 A10

142 *CB6

143 VDDQ

144 *CB7

KEY

171 DQ55

172 VDDQ

173 NC

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

*CB3

BA1

VDDID

DQ56

DQ57

VDD

174 DQ60

175 DQ61

KEY

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

145 VSS

146 DQ36

147 DQ37

148 VDD

149 DQS13

150 DQ38

151 DQ39

152 VSS

153 DQ44

VSS

116 VSS

177 DQS16

178 DQ62

179 DQ63

180 VDDQ

181 SA0

DQS7

DQ58

DQ59

VSS

117 DQ21

118 A11

119 DQS11

120 VDD

DQ18

BA0

121 DQ22

122 A8

182 SA1

VDDQ

DQ19

DQ35

DQ40

SDA

183 SA2

SCL

123 DQ23

184 VDDSPD

*These pins are not used in this module.

- 2 -

W9451GBDA

5. PIN DESCRIPTIONS

NAME

FUNCTION DESCRIPTION

CLKn, CLKn

CLKn and CLKn are differential clock inputs. All input

command signals are sampled at the positive edge of

CLK(except for DQ, DM and CKE).

Clock Input

Chip Select

Disable or enable the command decoder. When command

decoder is disabled, new command is ignored and previous

operation continues.

CSn

CKE controls the clock activation and deactivation. When CKE

is low, Power Down mode, Suspend mode, or Self-Refresh

mode is entered.

CKEn

Clock Enable

Address

Multiplexed pins for row and column address.

Row address: A0 - A12. Column address: A0 - A9.

A0 - A12

Bank Select

Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

BA0 - BA1

Command input. When sampled at the rising edge of the

Row Address

Strobe

RAS

clock, RAS , CAS and WE define the operation to be

executed.

Column Address

Strobe

CAS

Referred to RAS

Write Enable

Referred to RAS

The output buffer is placed at Hi-Z when DM is sampled high

Input/Output Mask in read cycle. In write cycle, sampling DM high will block the

write data.

DM0 - DM7

Data Input/Output Multiplexed pins for data output and input

DQ0 - DQ63

Data Strobe

Input/Output

Output with read data, input with write data. DQS is edge-

aligned with read data, centered in write data.

DQS0 - DQS7

VDD

VSS

Power (+2.5V)

Ground

Power supply (2.5V).

Ground

VREF

VDDSPD

SCL

Reference Voltage SSTL-2 Reference voltage

SPD Power

Separated power supply for SPD EEPROM (2.3V - 3.6V)

Clock for serial presence detection

Serial Clock

Serial Data I/O

SDA

Data line for serial presence detection

System assigned address (SA0 - SA2) to identify different

memory module in a system board.

SAn

SPD Address Line

No Connection

No connection

Publication Release Date: March 15, 2002

- 3 -

Revision A1

W9451GBDA

6. BLOCK DIAGRAM

CS1

CS0

DQS0

DM0/DQS9

DQS4

DM4/DQS13

DQS

U12

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS1

DQS5

DM5/DQS14

DM1/DQS10

DQS

U13

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2/DQS11

DQS6

DM6/DQS15

DQS

U10

DQS

U14

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ22

DQ23

DQ54

DQ55

DQS3

DM3/DQS12

DQS7

DM7/DQS16

DQS

U11

DQS

U15

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ24

DQ25

DQ56

DQ57

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

SDRAMs U0 ~ U15

A0 ~ A13, BA0 & 1

RAS

CAS

SDRAMs U0 ~ U15

SERIAL PD

SDA

SCL

SA0

SA1

SA2

CKE1

CKE0

SDRAMs U8 ~ U15

SDRAMs U0 ~ U7

SPD

SDA

VDD SPD

VDD/VDDQ

D0~D15

V^REF

D0~D15

V^SS

V^DDID

- 4 -

W9451GBDA

7. ABSOLUTE MAXIMUM RATINGS

PARAMETER

Input, Output Voltage

SYMBOL

VIN, VOUT

VDD, VDDQ

TOPR

RATING

-0.3 - VDDQ +0.3

-0.3 - 3.6

0 - 70

UNIT

NOTES

Power Supply Voltage

Operating Temperature

°C

Storage Temperature

TSTG

-55 - 150

260

Soldering Temperature (10s)

Power Dissipation for Each Component

Short Circuit Output Current

TSOLDER

IOUT

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

8. RECOMMENDED DC OPERATING CONDITIONS

(TA = 0 to 70 °C)

PARAMETER

Power Supply Voltage

SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

VDD

VDDQ

2.3

2.5

2.7

2.5

VDD

Power Supply Voltage (for I/O Buffer)

Input reference Voltage

VREF

0.49 x VDDQ

VREF -0.04

VREF +0.15

-0.3

0.50 x VDDQ

0.51 x VDDQ

VREF +0.04

VDDQ +0.3

VREF -0.15

VDDQ +0.1

2, 3

VTT

VREF

Termination Voltage (System)

Input High Voltage (DC)

VIH (DC)

VIL (DC)

VICK (DC)

Input Low Voltage (DC)

-0.1

Differential Clock DC Input Voltage

Input Differential Voltage. CLK and

CLK inputs (DC)

VID (DC)

0.36

VDDQ +0.6

14, 16

VIH (AC)

VIL (AC)

VREF +0.31

Input High Voltage (AC)

Input Low Voltage (AC)

VREF -0.31

Input Differential Voltage. CLK and

CLK inputs (AC)

VID (AC)

0.7

VDDQ +0.6

14, 16

Differential AC input Cross Point

Voltage

VX (AC)

VDDQ/2 -0.2

VDDQ/2 +0.2

13, 16

15, 16

VISO (AC)

Differential Clock AC Middle Point

Notes: Undershoot limit: VIL(min.) = -0.9V with a pulse width < 5 nS

Overshoot limit: VIH(max.) = VDDQ +0.9V with a pulse width < 5 nS

VIH(DC) and VIL(DC) are levels to maintain the current logic state, VIH(AC) and VIL(AC) are levels to change to the new logic

state.

Publication Release Date: March 15, 2002

- 5 -

Revision A1

W9451GBDA

9. CAPACITANCE

(VDD = VDDQ = 2.5V ±0.2V, f = 1 MHz, TA = 25 °C, VOUT(DC) = VDDQ/2, VOUT(Peak to Peak) = 0.2V)

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

Cadd-IN

Address Input Capacitance (A0 - A12, BA0, BA1)

CCMD-IN

Command Input Capacitance (RAS , CAS , WE )

CCS-IN

CCKE-IN

CCLK-IN

CS signals Input Capacitance ( CS0 , CS1)

CKE signal Input Capacitance (CKE0, CKE1)

CLK signals Input Capacitance (CLKn, CLKn )

CI/O

DM/DQS/DQ Input capacitance (DM0 - DM7, DQS0 - 7, DQ0 - 63)

10. DC CHARACTERISTICS

MAX.

UNIT

NOTES

PARAMETER

SYM.

-7

-75

OPERATING CURRENT: One Bank Active-Precharge; tRC = tRC min; tCK =

tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address

and control inputs changing once per clock cycle

IDD0

1240

1200

OPERATING CURRENT: One Bank Active-Read-Precharge; Burst = 2; tRC =

tRC min; CL=2.5; tCK = tCK min; IOUT = 0 mA; Address and control inputs

changing once per clock cycle.

IDD1

1240

1200

7, 9

PRECHARGE-POWER-DOWN STANDBY CURRENT: All Banks Idle; Power

down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM

IDD2P

IDLE FLOATING STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE

> VIH min; Address and other control inputs changing once per clock cycle;

Vin = Vref for DQ, DQS and DM

IDD2F

IDD2N

720

640

IDLE STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min;

tCK = tCK min; Address and other control inputs changing once per clock cycle;

Vin > VIH min or Vin < VIL max for DQ, DQS and DM

IDLE QUIET STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH

min; tCK = tCK min; Address and other control inputs stable; Vin > VREF for DQ,

DQS and DM

IDD2Q

IDD3P

640

320

560

320

ACTIVE POWER-DOWN STANDBY CURRENT: One Bank Active; Power

down mode; CKE < VIL max; tCK = tCK min

ACTIVE STANDBY CURRENT: CS > VIH min; CKE > VIH min; One Bank

Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs

changing twice per clock cycle; Address and other control inputs changing

once per clock cycle

IDD3N

920

840

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One Bank

Active; Address and control inputs changing once per clock cycle; CL=2.5; tCK

= tCK min; IOUT = 0 mA

IDD4R

IDD4W

1710

1560

7,9

OPERATING CURRENT: Burst = 2; Write; Continuous burst; One Bank

Active; Address and control inputs changing once per clock cycle; CL = 2.5;

tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle

AUTO REFRESH CURRENT: tRC = tRFC min

SELF REFRESH CURRENT: CKE < 0.2V

IDD5

IDD6

1880

1840

RANDOM READ CURRENT: 4 Banks Active Read with activate every 20ns,

Auto-Precharge Read every 20ns; Burst = 4; tRCD = 3; IOUT = 0 mA; DQ, DM

and DQS inputs changing twice per clock cycle; Address changing once per

clock cycle

IDD7

2520

2480

- 6 -

W9451GBDA

11. AC CHARACTERISTICS OF SDRAM COMPONENTS (Notes: 10, 12)

SYM.

PARAMETER

-7

-75

UNITS NOTES

MIN.

7.5

MAX.

MIN.

MAX.

tRC

tRFC

tRAS

tRCD

tRAP

tCCD

tRP

Active to Ref/Active Command Period

Ref to Ref/Active Command Period

tCK

Active to Precharge Command Period

Active to Read/Write Command Delay Time

Active to Read with Auto Precharge Enable

Read/Write(a) to Read/Write(b) Command Period

Precharge to Active Command Period

Active(a) to Active(b) Command Period

Write Recovery Time

100000

tRRD

tWR

tDAL

tCK

Auto Precharge Write Recovery + Precharge Time

CLK Cycle Time

CL = 2

CL = 2.5

7.5

tAC

-0.75

0.75

-0.75

0.75

Data Access Time from CLK, CLK

tDQSCK

DQS Output Access Time from CLK, CLK

tDQSQ Data Strobe Edge to Output Data Edge Skew

0.5

tCH

tCL

tHP

CLk High Level Width

CLK Low Level Width

CLK Half Period (minimum of actual tCH, tCL)

0.45

Min.

0.55

0.45

Min.

(tCL, tCH)

tHP

-0.75

0.9

0.4

0.55

tCK

(tCL, tCH)

tQH

DQ Output Data Hold Time from DQS

tHP

-0.75

0.9

0.4

0.5

tRPRE DQS Read Preamble Time

tRPST DQS Read Postamble Time

1.1

0.6

1.1

0.6

tCK

tDS

tDH

DQ and DM Setup Time

DQ and DM Hold Time

0.5

tDIPW

DQ and DM Input Pulse Width (for each input)

1.75

0.35

0.2

1.75

0.35

0.2

tDQSH DQS Input High Pulse Width

tDQSL DQS Input Low Pulse Width

tCK

tDSS

tDSH

DQS Falling Edge to CLK Setup Time

DQS Falling Edge Hold Time from CLK

0.2

tWPRES Clock to DQS Write Preamble Set-up Time

tWPRE DQS Write Preamble Time

0.25

0.4

0.25

0.4

tWPST DQS Write Postamble Time

tDQSS Write Command to First DQS Latching Transition

tDSSK UDQS – LDQS Skew (x 16)

0.75

-0.25

0.9

1.25

0.25

0.75

-0.25

0.9

1.25

0.25

tIS

tIH

Input Setup Time

Input Hold Time

0.9

tIPW

tHZ

Control & Address Input Pulse Width (for each input)

2.2

-0.75

0.75

-0.75

0.75

Data-out High-impedance Time from CLK, CLK

tLZ

0.75

1.5

0.75

1.5

Data-out Low-impedance Time from CLK, CLK

SSTL Input Transition

Internal Write to Read Command Delay

tT(SS)

tWTR

0.5

tCK

tXSNR Exit Self Refresh to Non-read Command

tXSRD Exit Self Refresh to Read Command

tREF

Refresh Time (8K)

Mode Register Set Cycle Time

tMRD

Publication Release Date: March 15, 2002

Revision A1

- 7 -

W9451GBDA

12. AC TEST CONDITION OF SDRAM COMPONENTS

PARAMETER

Input High Voltage (AC)

SYMBOL

VIH

VALUE

VREF +0.31

VREF -0.31

0.5 x VDDQ

1.0

UNIT

Input Low Voltage (AC)

VIL

Input Reference Voltage

VREF

VTT

Termination Voltage

Input Signal Peak to Peak Swing

Differential Clock Input Reference Voltage

VSWING

Vx (AC)

VID(AC)

1.5

Input Difference Voltage. CLK and CLK Inputs (AC)

Input Signal Minimum Slew Rate

SLEW

VOTR

1.0

V/nS

Output Timing Measurement Reference Voltage

0.5 x VDDQ

V Q

VTT

IH min (AC)

SWING (MAX)

REF

RT= 50 ohms

IL max (AC)

VSS

Z = 50 ohms

output

30pF

SLEW = (VIH min (AC) - VILmax (AC)) /

A.C. TEST LOAD (A)

Notes:

(1) Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the

device.

(2)

(3)

(4)

(5)

(6)

All voltages are referenced to VSS, VSSQ.

Peak to peak AC noise on VREF may not exceed ±2% of VREF(DC).

VOH = 1.95V,VOL = 0.35V

VOH = 1.9V,VOL = 0.4V

The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V. The values of IOL(DC) is based on VDDQ = 2.3V and

VTT = 1.11V.

(7) These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values

of tCK and tRC.

(8) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set

equal to VREF and must track variations in the DC level of VREF.

- 8 -

W9451GBDA

(9) These parameters depend on the output loading. Specified values are obtained with the output open.

(10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed

slope.

(11) If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to

the nearest decimal place. i.e., tDQSS = 0.75´ tCK, tCK=7.5ns, 0.75 ´ 7.5 nS = 5.625 nS is rounded up to 5.6ns.

(12) VX is the differential clock cross point voltage where input timing measurement is referenced.

(13) VID is magnitude of the difference between CLK input level and CLK input level.

(14) VISO means {VICK(CLK) + VICK( CLK )}/2.

(15) Refer to the figure below.

(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.

CLK

ICK

VICK

ID(AC)

CLK

VSS

ICK

VICK

VID(AC)

0 V Differential

ISO

ISO(min)

ISO(max)

VSS

(17) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.

Publication Release Date: March 15, 2002

Revision A1

- 9 -

W9451GBDA

13. OPERATION MODES

The following Simplified Truth Table illustrates the operation modes of DDR SDRAM. For more

detailed information please refer to the DDR SDRAM datasheet.

Simplified Truth Table

COMMAND

DEVICE CKEN-1 CKEN DMN BS0,

A10

A12,

A11,

RAS CAS WE

STATE

BS1

A9-A0

Bank Active

Idle

Any

Bank Precharge

Precharge All

Any

Write

Active⁽³⁾

Idle

Write with Autoprecharge

Read

Read with Autoprecharge

Mode Register Set

L, L

H, L

Extended Mode Register

Set

Idle

No Operation

Any

Active

Any

Burst Read Stop

Device Deselect

Auto Refresh

Idle

Self Refresh Entry

Self Refresh Exit

Idle

Idle (Self

Refresh)

Power Down Mode Entry

Power Down Mode Exit

Idle/

Active⁽⁵⁾

Any

(Power

Down)

Data Write Enable

Data Write Disable

Notes:

Active

1. V = Valid X = Don’t Care L = Low level H = High level

2. CKE_nsignal is input level when commands are issued.

3. CKE_n-1signal is input level one clock cycle before the commands are issued.

4. These are state designated by the BS0, BS1 signals.

5. Power Down Mode can not entry in the burst cycle.

- 10 -

W9451GBDA

14. SERIAL PRESENCE DETECT EEPROM

The Serial Presence Detect (SPD) function is implemented by using a 2,408-bit EEPROM component.

This nonvolatile storage device contains those data for identifying the module type and various

SDRAM organizations and timing parameters. System read operations to the EEPROM device occur

using the DIMM SCL(clock) and SDA (data) signals, together with SA(2:0) which provide the

EEPROM Device Address.

SPD EEPROM DC Operating Conditions

(Vcc = 2.3V - 3.6V)

PARAMETER/CONDITION

Supply Voltage

SYM.

VCC

VIH

VIL

MIN.

2.3

MAX.

UNIT

NOTES

3.6

Input High (Logic 1) Voltage, all inputs

Input Low (Logic 0) Voltage, all inputs

Output low voltage, lout = 3 mA

VCC x 0.7

-0.3

VCC +0.5

VCC x 0.3

VOL

ILI

0.4

IOL = 3 mA

Input leakage current, VIN = GND to Vcc

Output leakage current, VOUT = GND to Vcc

Power Supply Current

ILO

ICC

SCL Clock Frequency = 100 KHz

SPD AC Operating Conditions

(Vcc = 2.3V - 3.6V)

PARAMETER

SYM.

MIN.

MAX.

UNIT

KHz

SCL Clock Frequency

fSCL

100

3.5

Noise Suppression Time Constant at SCL, SDA Inputs

SCL Low to SDA Data Out Valid

Time the bus must be free before a new transition can start

Start Condition Hold Time

Clock Low Period

tAA

tBUF

0.2

4.7

tHD:STA

tLOW

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

4.0

4.7

4.0

4.7

Clock High Period

Start Condition Setup Time

Data in Hold Time

Data in Setup Time

250

SDA and SCL Rise time

SDA and SCL Fall Time

300

Stop Condition Setup Time

Data Out Hold Time

tSU:STO

tDH

200

Write Cycle Time

tWR

Note: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal

erase/program cycle. During the write cycle the EEPROM bus interface circuits are disabled, SDA is allowed to remain

high the bus level pull-up resistor, and the device does not respond to its slave address.

Publication Release Date: March 15, 2002

- 11 -

Revision A1

W9451GBDA

15. SPD DATA

Byte

No.

FUNCTION SUPPORTED

-7 -75

HEX VALUE

FUNCTION DESCRIBED

-7

-75

Defines # bytes written into serial memory at module

manufacturer

128 bytes

80h

Total # bytes of SPD memory device

Fundamental memory type (FPM, EDO, DRAM..)

# Row Addresses on this assembly

# Column Addresses on this assembly

# Module Rows on this assembly

Data Width of this assembly.

256 bytes (2K-bit)

08h

07h

0Dh

0Ah

02h

40h

00h

04h

DDR SDRAM

2 row

64 bits

Data Width continuation

Voltage interface standard of this assembly

SDRAM Cycle time @CAS latency of 2.5

SDRAM Access time @CAS latency of 2.5

DIMM Configuration type (Non-parity, Parity ECC)

Refresh Rate/Type

SSTL 2.5V

7 nS

+/-0.75 nS

7.5 nS

70h

75h

+/-0.75 nS

Non parity

00h

82h

08h

00h

01h

0Eh

04h

0Ch

01h

02h

7.8 mS, support self refresh

SDRAM width, Primary DRAM

X 8

None

Error Checking SDRAM data width

Minimum Clock Delay, Back Random Column Addresses

Burst Lengths supported

TCCD = 1 CLK

2, 4, 8

#Bank on Each SDRAM device

CAS# Latencies Supported

4 banks

2 & 2.5

CS# Latency

0 CLK

Write Latency

1 CLK

Differential Clock, Non-

buffered Non–registered &

redundant addressing

SDRAM Module Attributes

20h

00h

2.5V+/-10% voltage

tolerance, Burst Read, Write,

precharge all, auto precharge

SDRAM Device Attributes: General

SDRAM cycle time @ CAS latency of 2

SDRAM access time @CAS latency of 2

SDRAM cycle time @ CAS latency of 1.5

SDRAM access time @CAS latency of 1.5

7.5 nS

+/-0.75 nS

10 nS

+/-0.75 nS

75h

A0h

75h

00h

50h

3Ch

50h

2Dh

75h

00h

50h

3Ch

50h

2Dh

Precharge to active command period (t_RP

Active to Active command period (t_RRD

Active to Read/Write command delay time (t_RCD

)

20 nS

15 nS

20 nS

45 nS

20 nS

15 nS

20 nS

45 nS

)

Minimum Active to precharge period (t_RAS

)

Density of each Row on Module

Each row of 256MB

40h

Command and Address signal input setup time

Command and Address signal input hold time

Data signal input setup time

0.9 nS

0.5 nS

0.9 nS

0.5 nS

90h

50h

90h

50h

Data signal input hold time

Superset Information (may be used in future)

SPD data specification revision

00h

90h

00h

36 - 61

Initial release revision

C0h

Checksum for Bytes 0 - 62

Unused storage locations

64 - 128

- 12 -

W9451GBDA

16. LABELING INFORMATION

There is a product description sticker stuck on each module to fully describe the information of the

module. The following are examples of the product description sticker.

Examples:

MODULE P/N

EXAMPLE OF STICKER

W9451GBDA-7

512MB DDR266/CL2 DIMM

TAIWAN 126K264896

W9451GBDA-75

(DDR266/CL2 DIMM)

W9451GBDA-75

512MB DDR266/CL2.5 DIMM

TAIWAN 126K264896

(DDR266/CL2.5 DIMM)

The content of this product description sticker is described as below:

MODULE PART NUMBER W9451GBDA-7/-75

DIMM Module Part Number Informatoin

W94 51 G D A -7/-75

Speed Grade

-7: DDR266/CL2

-75: DDR266/CL2.5

Winbond Product Line

W94: DDR SDRAM

Memory Size

Module Version

51: 512Mbytes

A: A Version

DDR SDRAM Type

Module Type

G: 32M x 8

D: Unbuffered DIMM

DDR SDRAM Version

B: B Version

Total Memory Size: 512 Mbytes

Compliant Industry Spec: DDR266/CL2, DDR266/CL2.5

Module Type: DIMM

Manufacturing Location: TAIWAN

Tracking Number: 926K264896

(The number “926K264896” is for reference only. It is changed according to assembly

date, assembly site, and serial lot number.)

Publication Release Date: March 15, 2002

- 13 -

Revision A1

W9451GBDA

17. PACKAGE DIMENSION

Units:Inches

Front View

5.25

1.250

0.098

Rear View

SPD

0.170 Max

SIDE VIEW

0.050 0.004

Tolerances: .005 unless othrerwise specified

Component P/N: W942508BH-7/-75 (32M X 8 DDR-SDRAM,TSOP-66)

- 14 -

W9451GBDA

Headquarters

Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.

27F, 2299 Yan An W. Rd. Shanghai,

2727 North First Street, San Jose,

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5665577

200336 China

CA 95134, U.S.A.

TEL: 1-408-9436666

FAX: 1-408-5441798

TEL: 86-21-62365999

FAX: 86-21-62365998

http://www.winbond.com.tw/

Taipei Office

Winbond Electronics Corporation Japan

7F Daini-ueno BLDG, 3-7-18

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

9F, No.480, Rueiguang Rd.,

Neihu Chiu, Taipei, 114,

Taiwan, R.O.C.

TEL: 886-2-8177-7168

FAX: 886-2-8751-3579

TEL: 81-45-4781881

FAX: 81-45-4781800

TEL: 852-27513100

FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Publication Release Date: March 15, 2002

Revision A1

- 15 -

W9451GBDA-7 [WINBOND]

相关型号：

W9451GBDA-75

W946432AD

W946432AD-55

W946432AD-6

W9464G2IB-4

W9464G2IB-5

W9464G6IB

W9464G6IH

W9464G6IH-4

W9464G6IH-5

W9464G6IH-5I

W9464G6IH-6