W981216DH-7 [WINBOND]
Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, TSOP2-54;
| 型号： | W981216DH-7 |
| 厂家： | 
WINBOND |
| 描述： | Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, TSOP2-54 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总44页 (文件大小：1221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W981216DH / W9812G6DH
2M × 4 BANKS × 16 BIT SDRAM
Table of Contents-
1.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES................................................................................................................................. 3
PIN CONFIGURATION............................................................................................................... 4
PIN DESCRIPTION..................................................................................................................... 5
BLOCK DIAGRAM ...................................................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ............................................................................................. 7
RECOMMENDED DC OPERATING CONDITIONS................................................................... 7
CAPACITANCE........................................................................................................................... 7
AC CHARACTERISTICS AND OPERATING CONDITION........................................................ 8
DC CHARACTERISTICS............................................................................................................ 9
OPERATION MODE ................................................................................................................. 12
FUNCTIONAL DESCRIPTION.................................................................................................. 13
12.1 Power Up and Initialization ........................................................................................... 13
12.2 Programming Mode Register........................................................................................ 13
12.3 Bank Activate Command .............................................................................................. 13
12.4 Read and Write Access Modes .................................................................................... 14
12.5 Burst Read Command .................................................................................................. 14
12.6 Burst Write Command .................................................................................................. 14
12.7 Read Interrupted by a Read ......................................................................................... 14
12.8 Read Interrupted by a Write.......................................................................................... 14
12.9 Write Interrupted by a Write.......................................................................................... 14
12.10 Write Interrupted by a Read ........................................................................................ 15
12.11 Burst Stop Command.................................................................................................. 15
12.12 Addressing Sequence of Sequential Mode................................................................. 15
12.13 Addressing Sequence of Interleave Mode .................................................................. 16
12.14 Auto-Precharge Command.......................................................................................... 16
12.15 Precharge Command .................................................................................................. 16
12.16 Self Refresh Command............................................................................................... 17
12.17 Power Down Mode...................................................................................................... 17
12.18 No Operation Command ............................................................................................. 17
12.19 Deselect Command..................................................................................................... 17
12.20 Clock Suspend Mode .................................................................................................. 17
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Publication Release Date: June 6, 2005
- 1 -
Revision A08
W981216DH / W9812G6DH
13.
14.
TIMING WAVEFORMS............................................................................................................. 18
13.1 Command Input Timing ................................................................................................ 18
13.2 Read Timing.................................................................................................................. 19
13.3 Control Timing of Input/Output Data............................................................................. 20
13.4 Mode Register Set Cycle.............................................................................................. 21
OPERATING TIMING EXAMPLE ............................................................................................. 22
14.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 22
14.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)............ 23
14.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 24
14.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge)............ 25
14.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 26
14.6 Interleaved Bank Write (Burst Length = 8, Autoprecharge).......................................... 27
14.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)............................................... 28
14.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)................................... 29
14.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3)........................................ 30
14.10 Auto Precharge Write (Burst Length = 4).................................................................... 31
14.11 Auto Refresh Cycle ..................................................................................................... 32
14.12 Self Refresh Cycle....................................................................................................... 33
14.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)............................ 34
14.14 PowerDown Mode....................................................................................................... 35
14.15 Autoprecharge Timing (Read Cycle)........................................................................... 36
14.16 Autoprecharge Timing (Write Cycle)........................................................................... 37
14.17 Timing Chart of Read to Write Cycle........................................................................... 38
14.18 Timing Chart of Write to Read Cycle........................................................................... 38
14.19 Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 39
14.20 Timing Chart of Burst Stop Cycle (Precharge Command).......................................... 39
14.21 CKE/DQM Input Timing (Write Cycle)......................................................................... 40
14.22 CKE/DQM Input Timing (Read Cycle)......................................................................... 41
14.23 Self Refresh/Power Down Mode Exit Timing .............................................................. 42
PACKAGE DIMENSION ........................................................................................................... 43
15.1 54L TSOP (II)-400 mil................................................................................................... 43
REVISION HISTORY................................................................................................................ 44
15.
16.
- 2 -
W981216DH/ W9812G6DH
1. GENERAL DESCRIPTION
W981216DH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
2M words × 4 banks × 16 bits. Using pipelined architecture and 0.13 µm process technology,
W981216DH delivers a data bandwidth of up to 166M words per second (-6). For different application,
W981216DH is sorted into four speed grades: -6, -7, -75, and -8H. The –6 is compliant to the
166Mhz/CL3 specification, the -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -
75 is compliant to the PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W981216DH is ideal for main memory in
high performance applications.
2. FEATURES
x
x
x
x
x
x
x
x
x
x
x
x
x
3.3V ± 0.3V Power Supply
Up to 166 MHz Clock Frequency
2,097,152 Words × 4 banks × 16 bits organization
Self Refresh Mode: Standard and Low Power
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Burst Read, Single Writes Mode
Byte Data Controlled by DQM
Auto-precharge and Controlled Precharge
4K Refresh cycles / 64 mS
Interface: LVTTL
Packaged in TSOP II 54 pin, 400 mil - 0.80
W9812G6DH is using Lead free materials, RoHS compliant
AVAILABLE PART NUMBER
MAXIMUM SELF REFRESH
OPERATING
PART NUMBER
SPEED
CURRENT
3 mA
TEMPERATURE
W981216DH-6
W981216DH-7
W981216DH-75
W981216DH-8H
166MHz/CL3
PC133/CL2
PC133/CL3
PC100/CL2
0°C - 70°C
0°C - 70°C
0°C - 70°C
0°C - 70°C
3 mA
3mA
3 mA
Publication Release Date: June 6, 2005
Revision A08
- 3 -
W981216DH / W9812G6DH
3. PIN CONFIGURATION
VCC
VSS
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
DQ15
DQ0
2
VSSQ
3
VCCQ
DQ1
DQ14
DQ13
4
DQ2
5
VSSQ
VCCQ
6
DQ12
DQ11
DQ3
DQ4
7
8
V
CCQ
V
SSQ
9
DQ10
DQ9
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
V
SSQ
VCCQ
DQ8
VSS
NC
DQ7
VCC
LDQM
WE
UDQM
CLK
CKE
NC
CAS
RAS
CS
A11
A9
BS0
BS1
A10/AP
A0
A8
A7
A6
A1
A5
A2
A4
VSS
A3
VCC
- 4 -
W981216DH/ W9812G6DH
4. PIN DESCRIPTION
PIN NUMBER PIN NAME
FUNCTION
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0 − A11. Column address: A0 − A8.
23 − 26, 22,
A0 − A11
29 − 35
Address
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
20, 21
BS0, BS1
Bank Select
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
Data Input/
Output
DQ0 −
Multiplexed pins for data output and input.
DQ15
Disable or enable the command decoder. When
19
18
Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
CS
Command input. When sampled at the rising edge of
Row Address
RAS
the clock, RAS , CAS and WE define the operation
Strobe
to be executed.
Column Address
17
16
CAS
WE
Referred to RAS
Strobe
Write Enable
Referred to RAS
The output buffer is placed at Hi-Z (with latency of 2)
UDQM/
LDQM
Input/Output when DQM is sampled high in read cycle. In write
39, 15
Mask
cycle, sampling DQM high will block the write operation
with zero latency.
System clock used to sample inputs on the rising edge
of clock.
38
37
CLK
CKE
Clock Inputs
CKE controls the clock activation and deactivation.
Clock Enable When CKE is low, Power Down mode, Suspend mode
or Self Refresh mode is entered.
1, 14, 27
28, 41, 54
VCC
VSS
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside DRAM.
Power (+3.3V) Separated power from VCC, used for output buffers to
for I/O Buffer improve noise.
3, 9, 43, 49
VCCQ
Ground for I/O Separated ground from VSS, used for output buffers to
6, 12, 46, 52
36, 40
VSSQ
NC
Buffer
improve noise.
No Connection No connection
Publication Release Date: June 6, 2005
Revision A08
- 5 -
W981216DH / W9812G6DH
5. BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CS
CONTROL
SIGNAL
GENERATOR
RAS
COMMAND
DECODER
CAS
COLUMN DECODER
COLUMN DECODER
WE
R
R
O
W
O
W
D
E
C
O
D
E
R
D
CELL ARRAY
BANK #0
CELL ARRAY
BANK #1
E
A10
C
O
D
E
R
MODE
REGISTER
A0
SENSE AMPLIFIER
SENSE AMPLIFIER
ADDRESS
BUFFER
A9
DMn
A11
BS0
BS1
DQ0
DATA CONTROL
CIRCUIT
DQ
BUFFER
DQ15
REFRESH
COUNTER
COLUMN
COUNTER
UDQM
LDQM
COLUMN DECODER
COLUMN DECODER
R
R
O
W
O
W
CELL ARRAY
BANK #3
CELL ARRAY
BANK #2
D
E
C
O
D
E
R
D
E
C
O
D
E
R
SENSE AMPLIFIER
SENSE AMPLIFIER
Note: The cell array configuration is 4096 * 512 * 16.
- 6 -
W981216DH/ W9812G6DH
6. ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VIN, VOUT
VCC, VCCQ
TOPR
RATING
-0.3 − VCC +0.3
-0.3 − 4.6
0 − 70
UNIT
V
Input/Output Voltage
Power Supply Voltage
V
Operating Temperature(-6/-7/-75/-8H)
Storage Temperature
°C
°C
°C
W
TSTG
-55 − 150
260
Soldering Temperature (10s)
Power Dissipation
TSOLDER
PD
1
Short Circuit Output Current
IOUT
50
mA
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
7. RECOMMENDED DC OPERATING CONDITIONS
(Ta = 0 to 70°C for -6/-7/-75/-8H)
PARAMETER
Power Supply Voltage
Power Supply Voltage (for I/O Buffer)
Input High Voltage
SYMBOL
VCC
MIN.
3.0
3.0
2.0
-0.3
TYP.
3.3
3.3
-
MAX.
3.6
3.6
UNIT
V
V
V
V
VCCQ
VIH
VCC +0.3
0.8
Input Low Voltage
VIL
-
Note: VIH(max) = VCC/ VCCQ+1.2V for pulse width < 5 nS
VIL(min) = VSS/ VSSQ-1.2V for pulse width < 5 nS
8. CAPACITANCE
(VCC = 3.3V, f = 1 MHz, Ta 25°C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Input Capacitance
(A0 to A11, BS0, BS1, CS, RAS , CAS , WE , DQM,
CKE)
CI
-
3.8
pf
Input Capacitance (CLK)
Input/Output capacitance
CCLK
CIO
-
-
3.5
6.5
pf
pf
Note: These parameters are periodically sampled and not 100% tested.
Publication Release Date: June 6, 2005
Revision A08
- 7 -
W981216DH / W9812G6DH
9. AC CHARACTERISTICS AND OPERATING CONDITION
(Vcc = 3.3V ± 0.3V, Ta = 0 to 70°C for -6/-7/-75//-8H ; Notes: 5, 6, 7, 8)
UNIT
PARAMETER
SYM.
-6
-7
-75
-8H
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Ref/Active to Ref/Active Command
Period
60
63
65
68
tRC
tRAS
tRCD
tCCD
tRP
Active to precharge Command
42 100000 42 100000 45 100000 48 100000
nS
Period
Active to Read/Write Command
Delay Time
15
1
15
1
20
1
20
1
Read/Write(a) to Read/Write(b)
tCK
Command Period
Precharge to Active Command
Period
15
12
15
15
2
20
15
2
20
20
Active(a) to Active(b) Command
nS
tRRD
Period
Write Recovery Time
CLK Cycle Time
CL* = 2
CL* = 3
CL* = 2
CL* = 3
2
2
tCK
tWR
tCK
7.5 1000
7.5
7
2.5
2.5
1000
1000
10
7.5
2.5
2.5
1000 10 1000
6
2
2
1000
1000
8
3
3
1000
CLK High Level width
CLK Low Level width
Access Time from
CLK
tCH
tCL
tAC
CL* = 2
CL* = 3
5.4
5
5.4
5.4
6
5.4
6
6
nS
2.7
5
Output Data Hold Time
3
3
3
3
3
3
tOH
tHZ
2.7
Output Data High Impedance Time
6
7
7.5
8
5
Output Data Low Impedance Time
Power Down Mode Entry Time
0
0
0
0
0
0
0
0
tLZ
tSB
6
1
7
1
7.5
1
8
1
Transition Time of CLK
0.
0.5
0.5
0.5
tT
(Rise and Fall)
5
Data-in Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
1.5
0.7
1.5
0.7
1.5
0.7
1.5
0.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2
1
2
1
2
1
2
1
tDS
tDH
tAS
tAH
tCKS
tCKH
tCMS
tCMH
tREF
tRSC
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
Mode register Set Cycle Time
*CL = CAS Latency
64
64
64
64
mS
nS
12
14
15
16
- 8 -
W981216DH/ W9812G6DH
10. DC CHARACTERISTICS
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C for -6/-7/-75/-8H)
PARAMETER
SYM.
-6
-7
-75
-8H UNIT NOTES
MAX. MAX. MAX. MAX.
Operating Current
t
CK = min., tRC = min.
1 bank
ICC1
85
80
75
70
3
Active precharge command
cycling without burst
operation
operation
Standby Current
CKE = VIH
ICC2
ICC2P
ICC2S
45
3
40
3
35
3
30
3
3
3
tCK = min, CS = VIH
CKE = VIL
(Power Down
mode)
VIH/L = VIH(min)/VIL(max.)
Bank: Inactive state
Standby Current
CKE = VIH
10
10
10
10
CLK = VIL, CS = VIH
CKE = VIL
(Power down
mode)
VIH/L = VIH(min)/VIL(max)
BANK: Inactive state
ICC2PS
ICC3P
ICC3P
3
3
3
3
mA
No Operating Current
tCK = min., CS = VIH(min)
CKE = VIH
65
10
60
10
55
10
50
10
CKE = VIL
(Power down
mode)
BANK: Active state
(4 banks)
Burst Operating Current
tCK = min.
Read/ Write command cycling
Auto Refresh Current
ICC4
ICC5
ICC6
105 100
95
90
3, 4
3
tCK = min.
180 170 160 150
Auto refresh command cycling
Self Refresh Current
Self Refresh Mode
CKE = 0.2V
Normal
3
3
3
3
(-6/-7/-75/-8H)
Publication Release Date: June 6, 2005
Revision A08
- 9 -
W981216DH / W9812G6DH
PARAMETER
Input Leakage Current
SYMBOL
MIN. MAX. UNIT NOTES
II(L)
-5
-5
2.4
-
5
5
µA
µA
V
(0V ≤VIN ≤ VCC, all other pins not under test = 0V)
Output Leakage Current
IO(L)
VOH
VOL
(Output disable , 0V ≤ VOUT ≤ VCCQ)
″
″
LVTTL Output H Level Voltage
(IOUT = -2 mA )
-
″
″
LVTTL Output L Level Voltage
(IOUT = 2 mA )
0.4
V
Notes:
1. Operation exceeds “ABSOLUTE MAXIMUM RATING” may cause permanent damage to the
devices.
2. All voltages are referenced to VSS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power up sequence is further described in the “Functional Description” section.
6. AC Testing Conditions
PARAMETER
CONDITIONS
1.4V/1.4V
Output Reference Level
Output Load
See diagram below
2.4V/0.4V
2 nS
Input Signal Levels
Transition Time (Rise and Fall) of Input Signal
Input Reference Level
1.4V
- 10 -
W981216DH/ W9812G6DH
1.4 V
50 ohms
Z = 50 ohms
Output
50 pF
AC TEST LOAD
7. Transition times are measured between VIH and VIL.
8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to
output level.
9. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e.,[(tr + tf)/2-1]ns should be added to the parameter
( The tT maximum can’t be more than 10nS for low frequency application. )
Publication Release Date: June 6, 2005
- 11 -
Revision A08
W981216DH / W9812G6DH
11. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
Table 1 Truth Table (Note (1), (2))
DEVICE
STATE
A0−A9
COMMAND
Bank Active
Bank Precharge
Precharge All
Write
CKEN-1 CKEN DQM BS0, 1 A10
CS RAS CAS
WE
A11
Idle
Any
Any
H
H
H
H
x
x
x
x
x
x
x
x
v
v
x
v
v
L
H
L
v
x
x
v
L
L
L
L
L
L
L
H
H
H
L
H
L
L
L
Active (3)
H
Write with
Active (3)
Active (3)
Active (3)
H
H
H
x
x
x
x
x
x
v
v
v
H
L
v
v
v
L
L
L
H
H
H
L
L
L
L
H
H
Autoprecharge
Read
Read with
H
Autoprecharge
Mode Register Set
No – Operation
Burst Stop
Device Deselect
Auto – Refresh
Self – Refresh Entry
Idle
Any
Active (4)
Any
H
H
H
H
H
H
x
x
x
x
H
L
x
x
x
x
x
x
v
x
x
x
x
x
v
x
x
x
x
x
v
x
x
x
x
x
L
L
L
H
L
L
L
H
H
x
L
L
L
H
H
x
L
L
L
H
L
x
Idle
Idle
H
H
x
x
X
idle
(S.R.)
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
H
x
H
Self Refresh Exit
Clock suspend Mode
Entry
Active
H
L
x
x
x
x
x
x
x
x
x
x
X
Idle
Active (5)
H
H
L
L
x
x
x
x
x
x
x
x
H
L
x
H
x
H
Power Down Mode
Entry
Clock Suspend Mode
Exit
Active
Any
L
H
x
x
x
x
x
x
x
x
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
Power Down Mode
Exit
(power
down)
Data write/Output
Enable
Data Write/Output
Disable
Active
Active
H
H
x
x
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
H
- 12 -
W981216DH/ W9812G6DH
Notes:
(1) v = valid
x = Don’t care
L = Low Level H = High Level
(2) CKEn signal is input level when commands are provided.
CKEn-1 signal is the input level one clock cycle before the command is issued.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
12. FUNCTIONAL DESCRIPTION
12.1 Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.
During power up, all Vcc and VccQ pins must be ramp up simultaneously to the specified voltage
when the input signals are held in the “NOP” state. The power up voltage must not exceed VCC +0.3V
on any of the input pins or Vcc supplies. After power up, an initial pause of 200 µS is required followed
by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power up, it is required that the DQM and CKE pins be held high during the initial pause period.
Once all banks have been precharged, the Mode Register Set Command must be issued to initialize
the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after
programming the Mode Register to ensure proper subsequent operation.
12.2 Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this
cycle defines the parameters to be set as shown in the Mode Register Operation table. A new
command may be issued following the mode register set command once a delay equal to tRSC has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
12.3 Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is
specified as tRAS (max).
Publication Release Date: June 6, 2005
- 13 -
Revision A08
W981216DH / W9812G6DH
12.4 Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting
RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level
defines whether the access cycle is a read operation (WE high), or a write operation (WE low). The
address inputs determine the starting column address.
Reading or writing to a different row within an activated bank requires the bank be precharged and a
new Bank Activate command be issued. When more than one bank is activated, interleaved bank
Read or Write operations are possible. By using the programmed burst length and alternating the
access and precharge operations between multiple banks, seamless data access operation among
many different pages can be realized. Read or Write Commands can also be issued to the same bank
or between active banks on every clock cycle.
12.5 Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS
and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequential mode.
12.6 Burst Write Command
The Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding
RAS high at the rising edge of the clock. The address inputs determine the starting column address.
Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the
Write Command is issued. The remaining data inputs must be supplied on each subsequent rising
clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be
ignored.
12.7 Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.
12.8 Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
12.9 Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
- 14 -
W981216DH/ W9812G6DH
12.10 Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
12.11 Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank, if the burst length is full page.
Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock.
The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst
read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write
operation, then any residual data from the burst write cycle will be ignored.
12.12 Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
ACCESS ADDRESS
BURST LENGTH
n
BL = 2 (disturb address is A0)
No address carry from A0 to A1
BL = 4 (disturb addresses are A0 and A1)
No address carry from A1 to A2
n + 1
n + 2
n + 3
n + 4
n + 5
n + 6
n + 7
BL = 8 (disturb addresses are A0, A1 and A2)
No address carry from A2 to A3
Publication Release Date: June 6, 2005
- 15 -
Revision A08
W981216DH / W9812G6DH
12.13 Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
Data 0
Data 1
ACCESS ADDRESS
BUST LENGTH
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
BL = 4
BL = 8
12.14 Auto-Precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is
entered. During auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS latency.
A Read or Write Command with auto-precharge can not be interrupted before the entire burst
operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during
a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot
be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-Precharge command is
illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write
with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation
two clocks delay from the last burst write cycle. This delay is referred to as Write tWR. The bank
undergoing auto-precharge can not be reactivated until tWR and tRP are satisfied. This is referred to as
tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-precharge Command, the interval
between the Bank Activate Command and the beginning of the internal precharge operation must
satisfy tRAS (min).
12.15 Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of
the clock. The Precharge Command can be used to precharge each bank separately or all banks
simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be
precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(tRP).
- 16 -
W981216DH/ W9812G6DH
12.16 Self Refresh Command
The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at
the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once
the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the
SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled.
The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self
Refresh operation after CKE is returned high. A minimum delay time is required when the device exits
Self Refresh Operation and before the next command can be issued. This delay is equal to the tAC
cycle time plus the Self Refresh exit time.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.
12.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCKS (min) + tCK (min).
12.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the
clock. A No Operation Command will not terminate a previous operation that is still executing, such as
a burst read or write cycle.
12.19 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS, CAS, and WE signals become don’t cares.
12.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
Publication Release Date: June 6, 2005
- 17 -
Revision A08
W981216DH / W9812G6DH
13. TIMING WAVEFORMS
13.1 Command Input Timing
t
CL
tCH
t
CK
V
V
IH
IL
CLK
CS
t
T
tT
t
CMS
tCMH
t
CMH
tCMS
t
CMS
t
CMH
RAS
t
t
CMS
CMS
t
t
CMH
CMH
CAS
WE
t
AS
tAH
A0-A11
BS0, 1
t
CKS
t
CKH
tCKH
t
CKS
t
CKS
t
CKH
CKE
- 18 -
W981216DH/ W9812G6DH
Timing Waveforms, continued
13.2 Read Timing
Read CAS Latency
CLK
CS
RAS
CAS
WE
A0-A11
BS0, 1
t
AC
t
AC
t
HZ
t
OH
t
OH
t
LZ
Valid
Data-Out
Valid
Data-Out
DQ
Read Command
Burst Length
Publication Release Date: June 6, 2005
Revision A08
- 19 -
W981216DH / W9812G6DH
Timing Waveforms, continued
13.3 Control Timing of Input/Output Data
Control Timing of Input Data
(Word Mask)
CLK
t
CMS
tCMH
t
CMH
tCMS
DQM
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
tDH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
DQ0 -15
(Clock Mask)
CLK
tCKH
t
CKS
t
CKH
tCKS
CKE
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
tDS
tDH
Valid
Valid
Data-in
Valid
Valid
DQ0 -15
Data-in
Data-in
Data-in
Control Timing of Output Data
(Output Enable)
CLK
t
CMH
t
CMS
tCMS
t
CMH
DQM
t
AC
t
HZ
tAC
t
AC
t
AC
t
LZ
t
OH
t
OH
t
OH
t
OH
Valid
Data-Out
Valid
Valid
Data-Out
Data-Out
OPEN
DQ0 -15
(Clock Mask)
CLK
t
CKH
t
CKS
t
CKH
tCKS
CKE
t
AC
t
AC
tAC
t
AC
t
OH
t
OH
tOH
tOH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
DQ0 -15
- 20 -
W981216DH/ W9812G6DH
Timing Waveforms, continued
13.4 Mode Register Set Cycle
t
RSC
CLK
t
CMS
tCMH
CS
t
CMS
tCMH
RAS
CAS
WE
t
t
CMS
CMS
t
t
CMH
CMH
t
AS
tAH
Register
set data
A0-A11
BS0,1
next
command
A
BurstLength
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A2 A1A0
Sequential
Interleave
Burst Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
1
2
4
8
2
4
8
Addressing Mode
CAS Latency
0
Reserved
Reserved
1
A10
FullAP0age
A3
0
A10
Addressing Mode
Sequential
InteArle0ave
"0" (Test Mode)
"0"
Reserved
A6 A5A4
CAS Latency
Reserved
Reserved
2
0
0
0
0
1
0
A00
1
1
A00
0
1
0
1
0
WriteMode
"0"
"0"
3
Reserved
BS0 "0"
"0"
Reserved
A9
0
A10
Single Write Mode
Burst read andBurst write
Burst read anAd0single write
BS1
Publication Release Date: June 6, 2005
Revision A08
- 21 -
W981216DH / W9812G6DH
14. OPERATING TIMING EXAMPLE
14.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
0
CLK
CS
t
RC
tRC
t
RC
tRC
RAS
CAS
t
RAS
t
RP
t
RAS
RP
tRP
t
RAS
t
tRAS
WE
BS0
BS1
t
RCD
t
RCD
t
RCD
t
RCD
RAa
RAa
RBb
RAc
RAc
RBd
RBd
A10
RAe
RAe
A0-A9,
A11
CBx
RBb
CAy
CAw
CBz
DQM
CKE
DQ
t
AC
t
AC
t
AC
t
AC
bx3
bx1
aw0
aw2 aw3
bx0
bx2
cy0 cy1
cy2 cy3
aw1
t
RRD
t
RRD
tRRD
t
RRD
Precharge
Read
Active
Read
Precharge
Active
Bank #0
Bank #1
Read
Active
Precharge
Read
Active
Active
Bank #2
Bank #3
Idle
- 22 -
W981216DH/ W9812G6DH
Operating Timing Example, continued
14.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)
(CLK = 100 MHz)
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
0
CLK
CS
t
RC
tRC
t
RC
t
RC
RAS
CAS
t
RAS
t
RP
t
RAS
t
t
RP
RAS
t
RAS
RP
t
WE
BS0
BS1
t
RCD
t
RCD
t
RCD
t
RCD
RAe
RBd
RAa
RBb
RAc
A10
A0-A9,
A11
CBz
RAa
CAw
CAy
RAe
CBx
RBb
RAc
RBd
DQM
CKE
t
AC
t
AC
t
AC
t
AC
aw0 aw1 aw2
aw3
bx0 bx1
bx2 bx3
cy0
cy1
cy2
cy3
dz0
DQ
t
RRD
tRRD
t
RRD
tRRD
Read
AP*
Active
AP*
Read
Active
Active
Active
AP*
Bank #0
Bank #1
Bank #2
Bank #3
Read
Read
Active
Idle
* AP is the internal precharge start timing
Publication Release Date: June 6, 2005
Revision A08
- 23 -
W981216DH / W9812G6DH
Operating Timing Example, continued
14.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
(CLK = 100 MHz)
6
7
8
9
10 11 12 13 14
15 16 17 18 19
20 21 22 23
1
2
3
4
5
0
CLK
CS
t
RC
tRC
t
RC
RAS
t
RAS
t
RP
tRAS
t
RP
t
RAS
tRP
CAS
WE
BS0
BS1
t
RCD
t
RCD
tRCD
RAa
RAa
RAc
RAc
A10
RBb
RBb
A0-A9,
A11
CAx
CBy
CAz
DQM
CKE
t
AC
t
AC
t
AC
ax0 ax1
ax2
ax3
ax4
ax5 ax6
by0
by1
by4 by5
by6
by7
DQ
CZ0
t
RRD
t
RRD
Read
Active
Precharge
Active
Read
Precharge
Bank #0
Bank #1
Bank #2
Bank #3
Active
Precharge
Read
Idle
- 24 -
W981216DH/ W9812G6DH
Operating Timing Example, continued
14.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge)
(CLK = 100 MHz)
6
7
8
9
10 11 12 13 14
15 16 17 18 19
20 21 22 23
1
2
3
4
5
0
CLK
CS
t
RC
t
RC
RAS
CAS
t
RAS
t
RP
tRAS
t
RAS
tRP
WE
BS0
BS1
A10
t
RCD
t
RCD
t
RCD
RBb
RBb
RAc
RAc
RAa
RAa
A0-A9,
A11
CAz
CAx
CBy
DQM
CKE
DQ
t
CAC
t
CAC
t
CAC
ax3
ax4
ax0
ax2
ax5 ax6
ax7
by0
by1
by4
by5
by6
ax1
CZ0
t
RRD
t
RRD
AP*
Read
Read
Active
Bank #0 Active
Bank #1
Read
Active
AP*
Bank #2
Idle
* AP is the internal precharge start timing
Bank #3
Publication Release Date: June 6, 2005
Revision A08
- 25 -
W981216DH / W9812G6DH
Operating Timing Example, continued
14.5 Interleaved Bank Write (Burst Length = 8)
(CLK = 100 MHz)
6
7
8
9
10 11 12 13 14
15 16 17 18 19
20 21 22 23
1
2
3
4
5
0
CLK
CS
t
RC
RAS
CAS
t
RAS
t
RAS
t
RP
tRP
t
RAS
t
RCD
t
RCD
t
RCD
WE
BS0
BS1
RBb
RAc
RAc
RAa
RAa
A10
A0-A9,
A11
CAx
RBb
CBy
CAz
DQM
CKE
DQ
ax0 ax1
RRD
ax4
ax5
ax6 ax7 by0
by1 by2
RRD
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
t
t
Active
Write
Precharge
Active
Write
Bank #0
Active
Write
Precharge
Bank #1
Bank #2
Bank #3
Idle
- 26 -
W981216DH/ W9812G6DH
Operating Timing Example, continued
14.6 Interleaved Bank Write (Burst Length = 8, Autoprecharge)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17
18
19
20 21
22 23
CLK
CS
RC
t
RAS
CAS
RAS
t
RP
t
RAS
t
WE
BS0
BS1
RCD
RCD
RCD
t
t
t
RAa
RAa
RBb
RBb
RAb
A10
CAx
CBy
CAz
RAc
A0-A9
DQM
CKE
DQ
ax4
by2
by5
ax0 ax1
ax5 ax6 ax7 by0 by1
by3
by4
by6 by7 CZ0 CZ1
CZ2
RRD
RRD
t
t
AP*
Write
AP*
Active
Active
Write
Bank #0
Bank #1
Bank #2
Bank #3
Active
Write
Idle
* AP is the internal precharge start timing
Publication Release Date: June 6, 2005
Revision A08
- 27 -
W981216DH / W9812G6DH
Operating Timing Example, continued
14.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16 17 18 19
20 21 22 23
CLK
CS
t
CCD
t
CCD
tCCD
t
RAS
tRP
t
RAS
tRP
RAS
CAS
WE
BS0
BS1
t
RCD
tRCD
RAa
RAa
RBb
RBb
A10
A0-A9,
A11
CBx
CAy
CAm
CBz
CAI
DQM
CKE
tAC
t
AC
t
AC
t
AC
tAC
am1
am2 bz0
bz1
bz2
bz3
a0
a1
a3
bx0
Ay0
Ay1 Ay2
am0
a2
bx1
DQ
t
RRD
Read
Bank #0 Active
Bank #1
Read
Read
Precharge
AP*
Active
Read
Read
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
- 28 -
W981216DH/ W9812G6DH
Operating Timing Example, continued
14.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)
(CLK = 100 MHz)
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
0
CLK
CS
t
RAS
tRP
RAS
CAS
WE
BS0
BS1
t
RCD
RAa
RAa
A10
A0-A9,
A11
CAx
CAy
DQM
CKE
t
AC
tWR
ax5
ay1
ax0
ax1
ax3
ay0
ay2
ay4
ax2
ax4
ay3
DQ
Q
Q
Q
Q
Q
Q
D
D
D
D
D
Bank #0
Bank #1
Bank #2
Bank #3
Active
Idle
Read
Write
Precharge
Publication Release Date: June 6, 2005
Revision A08
- 29 -
W981216DH / W9812G6DH
Operating Timing Example, continued
14.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
RAS
t
RAS
t
RP
t
RAS
tRP
CAS
WE
BS0
BS1
A10
t
RCD
t
RCD
RAa
RAb
A0-A9,
A11
CAx
RAa
CAw
RAb
DQM
CKE
DQ
tAC
tAC
aw0
aw1 aw2 aw3
bx0
bx1
bx2 bx3
Bank #0
AP*
Active
Idle
Read
Active
Read
AP*
Bank #1
Bank #2
Bank #3
* AP is the internal precharge start timing
- 30 -
W981216DH/ W9812G6DH
Operating Timing Example, continued
14.10 Auto Precharge Write (Burst Length = 4)
(CLK = 100 MHz)
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
0
4
20
22
23
CLK
CS
t
RC
t
RC
RAS
CAS
t
t
t
t
RP
RP
RAS
RAS
WE
BS0
BS1
t
RCD
t
RCD
RAc
A10
A0-A9
DQM
CKE
RAa
RAa
RAb
CAw
RAb
CAx
RAc
aw0 aw1 aw2 aw3
bx0
bx1
bx3
bx2
DQ
AP*
Active
Idle
Bank #0
Bank #1
Bank #2
Bank #3
Write
Active
Write
AP*
Active
* AP is the internal precharge start
Publication Release Date: June 6, 2005
Revision A08
- 31 -
W981216DH / W9812G6DH
Operating Timing Example, continued
14.11 Auto Refresh Cycle
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16 17 18 19
20 21 22 23
CLK
CS
t
RP
t
RC
tRC
RAS
CAS
WE
BS0,1
A10
A0-A9,
A11
DQM
CKE
DQ
All Banks
Prechage
Auto
Auto Refresh (Arbitrary Cycle)
Refresh
- 32 -
W981216DH/ W9812G6DH
Operating Timing Example, continued
14.12 Self Refresh Cycle
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
t
RP
RAS
CAS
WE
BS0,1
A10
A0-A9,
A11
DQM
t
CKS
t
CKS
t
SB
CKE
DQ
t
CKS
t
RC
Self Refresh Cycle
No Operation Cycle
All Banks
Self Refresh
Entry
Arbitrary Cycle
Precharge
Publication Release Date: June 6, 2005
Revision A08
- 33 -
W981216DH / W9812G6DH
Operating Timing Example, continued
14.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
RAS
CAS
t
RCD
WE
BS0
BS1
A10
RBa
A0-A9,
A11
CBz
RBa
CBv
CBw
CBx CBy
DQM
CKE
t
AC
tAC
DQ
av0
av1
av3
aw0
ax0
ay0
az1
az2
az3
az0
av2
Q
Q
Q
Q
D
D
D
Q
Q
Q
Q
Read
Active
Single Write
Read
Bank #0
Bank #1
Bank #2
Bank #3
Idle
- 34 -
W981216DH/ W9812G6DH
Operating Timing Example, continued
14.14 PowerDown Mode
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
WE
BS
RAa
RAa
RAa
RAa
A10
A0-A9
A11
CAa
CAx
DQM
t
SB
tSB
CKE
DQ
t
CKS
t
CKS
t
CKS
t
CKS
ax0
ax2
ax3
ax1
Active
NOP Read
Active Standby
Precharge
NOPActive
Precharge Standby
Power Down mode
Power Down mode
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
Publication Release Date: June 6, 2005
Revision A08
- 35 -
W981216DH / W9812G6DH
Operating Timing Example, continued
14.15 Autoprecharge Timing (Read Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
(1) CAS Latency=2
( a ) burst length = 1
Command
Read AP
Read
Act
t
RP
DQ
Q0
( b ) burst length = 2
Command
AP
Q0
Act
t
RP
DQ
Q1
( c ) burst length = 4
Command
Read
AP
Q2
Act
Q4
t
RP
DQ
Q0
Q0
Q1
Q1
Q3
( d ) burst length = 8
Command
Read
AP
Q6
Act
t
RP
DQ
Q2
Act
Q3
Act
Q5
Q7
(2) CAS Latency=3
( a ) burst length = 1
Command
Read AP
Read
t
RP
DQ
Q0
Q0
Q0
Q0
( b ) burst length = 2
AP
Command
t
RP
DQ
Q1
AP
Q1
( c ) burst length = 4
Command
Read
Act
Q4
t
RP
DQ
Q2
Q2
Q3
Q3
( d ) burst length = 8
Command
Read
AP
Q5
Act
t
RP
DQ
Q1
Q6
Q7
Note )
Read
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
AP
Act
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least tRAS(min).
- 36 -
W981216DH/ W9812G6DH
Operating Timing Example, continued
14.16 Autoprecharge Timing (Write Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
(1) CAS Latency = 2
(a) burst length = 1
Command
Write
D0
AP
Act
tWR
tRP
DQ
(b) burst length = 2
Command
Write
D0
AP
Act
AP
tWR
tRP
DQ
D1
D1
(c) burst length = 4
Command
Act
D7
Write
D0
tRP
tWR
DQ
D2
D3
D3
(d) burst length = 8
Command
Write
D0
AP
Act
tWR
tRP
DQ
D1
D2
AP
D4
D5
D6
(2) CAS Latency = 3
(a) burst length = 1
Write
D0
Act
Command
tWR
tRP
DQ
(b) burst length = 2
Command
Write
D0
AP
Act
tWR
tRP
DQ
D1
D1
D1
(c) burst length = 4
Command
Write
D0
AP
D5
Act
tWR
tRP
DQ
D2
D2
D3
D3
(d) burst length = 8
Command
Write
D0
AP
Act
tWR
tRP
DQ
D4
D6
D7
Note )
represents the Write with Auto precharge command.
represents the start of internal precharing.
represents the Bank Active command.
Write
AP
Act
When the /auto precharge command is asserted,the period from Bank Activate
command to the start of intermal precgarging must be at least tRAS (min).
Publication Release Date: June 6, 2005
Revision A08
- 37 -
W981216DH / W9812G6DH
Operating Timing Example, continued
14.17 Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
1
2
3
4
5
6
7
8
9
10
11
0
(1) CAS Latency=2
( a ) Command
Read Write
DQM
DQ
D0
D1
D2
D1
D3
D2
( b ) Command
Read
Write
DQM
DQ
D0
D3
D3
(2) CAS Latency=3
( a ) Command
DQM
Read Write
DQ
D0
D1
Write
D2
D1
D3
D2
( b ) Command
Read
DQM
DQ
D0
Note: The Output data must be masked by DQM to avoid I/O conflict
14.18 Timing Chart of Write to Read Cycle
In the case of Burst Length=4
1
2
3
4
5
6
7
8
9
10
11
0
(1) CAS Latency=2
Write Read
( a ) Command
DQM
DQ
D0
Q0
Q1
Q0
Q2
Q1
Q3
Q2
( b ) Command
DQM
Read
Write
DQ
D0
D1
Q3
(2) CAS Latency=3
( a ) Command
DQM
Write Read
DQ
D0
Write
Q0
Q1
Q0
Q2
Q1
Q3
Q2
( b ) Command
DQM
Read
DQ
Q3
D0
D1
- 38 -
W981216DH/ W9812G6DH
Operating Timing Example, continued
14.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
( a ) CAS latency =2
Command
Read
BST
Q3
DQ
Q4
Q3
Q0
Q1
Q0
Q2
Q1
( b )CAS latency = 3
Command
Read
BST
Q2
DQ
Q4
(2) Write cycle
Command
Write
Q0
BST
DQ
Q1
Q2
Q3
Q4
Note: BST
represents the Burst stop command
14.20 Timing Chart of Burst Stop Cycle (Precharge Command)
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
(a) CAS latency =2
Read
Read
PRCG
Q3
Command
DQ
Q0
Q1
Q0
Q2
Q1
Q4
Q3
(b) CAS latency =3
PRCG
Q2
Command
DQ
Q4
(2) Write cycle
(a) CAS latency =2
PRCG
PRCG
Write
Command
tWR
tWR
DQM
DQ
Q0
Q1
Q1
Q2
Q2
Q3
Q4
(b) CAS latency =3
Write
Command
DQM
DQ
Q0
Q3
Q4
Publication Release Date: June 6, 2005
Revision A08
- 39 -
W981216DH / W9812G6DH
Operating Timing Example, continued
14.21 CKE/DQM Input Timing (Write Cycle)
1
CLK cycle No.
2
3
4
5
7
6
External
CLK
Internal
CKE
DQM
DQ
D1
1
D2
2
D3
3
D5
D6
7
DQM MASK
CKE MASK
( 1 )
CLK cycle No.
External
4
5
6
CLK
Internal
CKE
DQM
DQ
D1
1
D2
D3
D5
D6
DQM MASK
( 2 )
CKE MASK
2
3
4
5
6
7
CLK cycle No.
External
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D4
D5
D6
CKE MASK
( 3 )
- 40 -
W981216DH/ W9812G6DH
Operating Timing Example, continued
14.22 CKE/DQM Input Timing (Read Cycle)
1
CLK cycle No.
2
3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
Q6
7
Q1
1
Q2
2
Q3
3
Q4
Open
Open
( 1 )
4
5
CLK cycle No.
External
6
CLK
Internal
CKE
DQM
DQ
Q3
Q4
Q6
7
Q1
1
Q2
Open
( 2 )
CLK cycle No.
2
3
4
5
6
External
CLK
Internal
CKE
DQM
DQ
Q6
Q3
Q1
Q5
Q4
Q2
( 3 )
Publication Release Date: June 6, 2005
Revision A08
- 41 -
W981216DH / W9812G6DH
Operating Timing Example, continued
14.23 Self Refresh/Power Down Mode Exit Timing
Asynchronous Control
Input Buffer turn on time ( Power down mode exit time ) is specified by tCKS(min) + tCK(min)
A ) tCK < tCKS(min)+tCK(min)
t
CK
CLK
CKE
t
CKS(min)+tCK(min)
Command
Command
NOP
Input Buffer Enable
B) tCK >= tCKS(min) + tCK (min)
t
CK
CLK
CKE
tCKS(min)+tCK(min)
Command
Input Buffer Enable
Command
Note )
All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode
and Self Refresh mode
NOP
Represents the No-Operation command
Represents one command
Command
- 42 -
W981216DH/ W9812G6DH
15. PACKAGE DIMENSION
15.1 54L TSOP (II)-400 mil
54
28
HE
E
1
27
e
b
C
D
L
A2
A1
A
L1
ZD
Y
SEATING PLANE
Controlling Dimension: Millimeters
DIMENSION
DIMENSION
(INCH)
(MM)
SYM.
MIN.
MAX.
MIN.
NOM.
MAX.
NOM.
1.20
0.15
0.047
0.006
A
A1
0.10
0.05
0.24
0.002
0.009
0.004
0.039
1.00
0.32
0.15
A2
b
c
0.40
0.016
0.012
0.006
D
E
22.12
10.06
11.56
22.62
10.26
11.96
0.871
0.396
0.455
0.875
0.400
0.905
0.404
0.471
22.22
10.16
11.76
0.80
0.50
0.80
HE
e
L
0.463
0.0315
0.020
0.60
0.10
0.40
0.016
0.024
0.004
0.032
L1
Y
0.71
0.028
ZD
Publication Release Date: June 6, 2005
Revision A08
- 43 -
W981216DH / W9812G6DH
16. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A01
10/15/2003
all
Formal version
A02
A03
A04
A05
A06
A07
A08
11/11/2003
11/21/2003
12/12/2003
2/18/2004
4/9/2004
6,7
1,7
6
Adjust tT and Icc2ps spec
Icc2P,Icc6 spec
Adjust tRC spec
8
Add note 9
6
tDH, tCKH,tAH,tCMH adjust to 0.7nS
Note 9
4/16/2004
1/6/2005
8
Adjust tRC spec, remove -75I/-75L SPEC
Add important notice
6/6/2005
44
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
2727 North First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 886-3-5770066
FAX: 1-408-5441798
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 44 -
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