W9864G2JH [WINBOND]
512K ? 4 BANKS ? 32BITS SDRAM; 512K ？ 4银行呢？ 32位SDRAM
| 型号： | W9864G2JH |
| 厂家： | 
WINBOND |
| 描述： | 512K ? 4 BANKS ? 32BITS SDRAM |
| 文件： | 总43页 (文件大小：740K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W9864G2JH
512K 4 BANKS 32BITS SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES................................................................................................................................. 3
AVAILABLE PART NUMBER...................................................................................................... 3
PIN CONFIGURATION............................................................................................................... 4
PIN DESCRIPTION..................................................................................................................... 5
BLOCK DIAGRAM ...................................................................................................................... 6
FUNCTIONAL DESCRIPTION.................................................................................................... 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Power Up and Initialization ............................................................................................. 7
Programming Mode Register.......................................................................................... 7
Bank Activate Command ................................................................................................ 7
Read and Write Access Modes ...................................................................................... 7
Burst Read Command .................................................................................................... 8
Burst Command.............................................................................................................. 8
Read Interrupted by a Read ........................................................................................... 8
Read Interrupted by a Write............................................................................................ 8
Write Interrupted by a Write............................................................................................ 8
7.10 Write Interrupted by a Read............................................................................................ 8
7.11 Burst Stop Command ..................................................................................................... 9
7.12 Addressing Sequence of Sequential Mode .................................................................... 9
7.13 Addressing Sequence of Interleave Mode...................................................................... 9
7.14 Auto-precharge Command ........................................................................................... 10
7.15 Precharge Command.................................................................................................... 10
7.16 Self Refresh Command ................................................................................................ 10
7.17 Power Down Mode ....................................................................................................... 11
7.18 No Operation Command............................................................................................... 11
7.19 Deselect Command ...................................................................................................... 11
7.20 Clock Suspend Mode.................................................................................................... 11
OPERATION MODE ................................................................................................................. 12
8.
9.
8.1
Simplified Stated Diagram ............................................................................................ 13
ELECTRICAL CHARACTERISTICS......................................................................................... 14
9.1
9.2
9.3
9.4
9.5
Absolute Maximum Ratings.......................................................................................... 14
Recommended DC Operating Conditions .................................................................... 14
Capacitance.................................................................................................................. 15
DC Characteristics........................................................................................................ 15
AC Characteristics and Operating Condition................................................................ 16
10.
TIMING WAVEFORMS............................................................................................................. 18
10.1 Command Input Timing ................................................................................................ 18
10.2 Read Timing.................................................................................................................. 19
Publication Release Date: Dec. 01, 2011
- 1 -
Revision A01
W9864G2JH
10.3 Control Timing of Input/Output Data............................................................................. 20
10.4 Mode Register Set Cycle.............................................................................................. 21
OPERATING TIMING EXAMPLE ............................................................................................. 22
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 22
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)........... 23
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 24
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)........... 25
11.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 26
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 27
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) .............................................. 28
11.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)..................................... 29
11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3)........................................ 30
11.10 Auto-precharge Write (Burst Length = 4) .................................................................... 31
11.11 Auto Refresh Cycle ..................................................................................................... 32
11.12 Self Refresh Cycle....................................................................................................... 33
11.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)............................. 34
11.14 Power Down Mode...................................................................................................... 35
11.15 Auto-precharge Timing (Write Cycle).......................................................................... 36
11.16 Auto-precharge Timing (Read Cycle).......................................................................... 37
11.17 Timing Chart of Read to Write Cycle........................................................................... 38
11.18 Timing Chart of Write to Read Cycle........................................................................... 38
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 39
11.20 Timing Chart of Burst Stop Cycle (Precharge Command).......................................... 39
11.21 CKE/DQM Input Timing (Write Cycle)......................................................................... 40
11.22 CKE/DQM Input Timing (Read Cycle)......................................................................... 41
PACKAGE SPECIFICATION.................................................................................................... 42
12.1 86L TSOP (II)-400 mil................................................................................................... 42
REVISION HISTORY................................................................................................................ 43
11.
12.
13.
Publication Release Date: Dec. 01, 2011
- 2 -
Revision A01
W9864G2JH
1. GENERAL DESCRIPTION
W9864G2JH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words 4 banks 32 bits. W9864G2JH delivers a data bandwidth of up to 200M words per
second. For different application, W9864G2JH is sorted into the following speed grades: -5/-6/-6I/-6A
and -7. The -5 parts can run up to 200MHz/CL3. The -6/-6I/-6A parts can run up to 166 MHz/CL3. (the
-6I industrial grade, -6A automotive grade which is guaranteed to support -40°C ~ 85°C.) The -7 parts
can run up to 143 MHz/CL3.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9864G2JH is ideal for main memory in
high performance applications.
2. FEATURES
3.3V± 0.3V for -5/-6/-6I/-6A grades power supply
2.7V~3.6V for -7 grade power supply
Up to 200 MHz Clock Frequency
524,288 words 4 banks 32 bits organization
Self Refresh Current: Standard and Low Power
CAS Latency: 2 & 3
Burst Length: 1, 2, 4, 8 and full page
Sequential and Interleave Burst
Byte data controlled by DQM0-3
Auto-precharge and controlled precharge
Burst read, single write operation
4K refresh cycles/64 mS
Interface: LVTTL
Packaged in TSOP II 86-pin, using Lead free materials with RoHS compliant
3. AVAILABLE PART NUMBER
MAXIMUM SELF
REFRESH CURRENT
OPERATING
TEMPERATURE
PART NUMBER
SPEED
W9864G2JH-5
W9864G2JH-6
W9864G2JH-6I
W9864G2JH-6A
W9864G2JH-7
200MHz/CL3
166MHz/CL3
166MHz/CL3
166MHz/CL3
143MHz/CL3
2mA
2mA
2mA
2mA
2mA
0°C ~ 70°C
0°C ~ 70°C
-40°C ~ 85°C
-40°C ~ 85°C
0°C ~ 70°C
Publication Release Date: Dec. 01, 2011
Revision A01
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W9864G2JH
4. PIN CONFIGURATION
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
1
2
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
3
4
5
6
VDDQ
DQ12
7
8
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VDD
VSS
DQM0
WE
DQM1
NC
CAS
RAS
NC
CLK
CKE
A9
CS
NC
BS0
A8
BS1
A7
A10/AP
A0
A6
A5
A1
A4
A2
A3
DQM2
VDD
DQM3
VSS
NC
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
Publication Release Date: Dec. 01, 2011
Revision A01
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W9864G2JH
5. PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0A10. Column address: A0A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or
bank selected by BS0, BS1.
24, 25, 26, 27, 60, 61, 62,
63, 64, 65, 66
Address
A0A10
Select bank to activate during row address latch
22, 23
BS0, BS1
Bank Select time, or bank to read/write during address latch
time.
2, 4, 5, 7, 8, 10, 11, 13, 31,
33, 34, 36, 37, 39, 40, 42,
45, 47, 48, 50, 51, 53, 54,
56, 74, 76, 77, 79, 80, 82,
83, 85
Data
Multiplexed pins for data output and input.
Input/ Output
DQ0DQ31
Disable or enable the command decoder. When
20
19
Chip Select
command decoder is disabled, new command is
ignored and previous operation continues.
CS
Command input. When sampled at the rising
Row Address
Strobe
RAS
edge of the clock
,
and
RAS CAS
WE
define
the operation to be executed.
Column Address
Strobe
18
17
CAS
WE
Referred to RAS
Write Enable
Referred to RAS
The output buffer is placed at Hi-Z (with latency
Input/Output of 2) when DQM is sampled high in read cycle.
16, 28, 59, 71
DQM0DQM3
CLK
Mask
In write cycle, sampling DQM high will block the
write operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
68
67
Clock Inputs
CKE controls the clock activation and
deactivation. When CKE is low, Power Down
mode, Suspend mode, or Self Refresh mode is
entered.
CKE
Clock Enable
Power for input buffers and logic circuit inside
DRAM.
1, 15, 29, 43
44, 58, 72, 86
VDD
VSS
Power
Ground for input buffers and logic circuit inside
DRAM.
Ground
Power for I/O Separated power from VDD, to improve DQ
Buffer noise immunity.
3, 9, 35, 41, 49, 55, 75, 81
VDDQ
Ground for I/O Separated ground from VSS, to improve DQ
Buffer noise immunity.
6, 12, 32, 38, 46, 52, 78, 84
14, 21, 30, 57, 69, 70, 73
VSSQ
NC
No Connection No connection.
Publication Release Date: Dec. 01, 2011
Revision A01
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W9864G2JH
6. BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
GENERATOR
RAS
COMMAND
CAS
DECODER
COLUMN DECODER
COLUMN DECODER
WE
A10
CELL ARRAY
BANK #0
CELL ARRAY
BANK #1
MODE
REGISTER
A0
SENSE AMPLIFIER
SENSE AMPLIFIER
ADDRESS
BUFFER
A9
BS0
BS1
DQ0
DATA CONTROL
CIRCUIT
DQ
BUFFER
DQ31
COLUMN
REFRESH
COUNTER
COUNTER
DQM0~3
COLUMN DECODER
COLUMN DECODER
CELL ARRAY
BANK #2
CELL ARRAY
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE:
The cell array configuration is 2048 * 256 * 32
Publication Release Date: Dec. 01, 2011
Revision A01
- 6 -
W9864G2JH
7. FUNCTIONAL DESCRIPTION
7.1 Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.
During power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage
when the input signals are held in the “NOP” state. The power up voltage must not exceed VDD + 0.3V
on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required
followed by a precharge of all banks using the precharge command. To prevent data contention on the
DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required
before or after programming the Mode Register to ensure proper subsequent operation.
7.2 Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of RAS
CAS CS and WE at the positive edge of the clock. The address input data during
, ,
this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new
command may be issued following the mode register set command once a delay equal to tRSC has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
7.3 Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is
specified as tRAS (max.).
7.4 Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting
RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level
defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The
address inputs determine the starting column address. Reading or writing to a different row within an
activated bank requires the bank be precharged and a new Bank Activate command be issued. When
more than one bank is activated, interleaved bank Read or Write operations are possible. By using the
programmed burst length and alternating the access and precharge operations between multiple
banks, seamless data access operation among many different pages can be realized. Read or Write
Commands can also be issued to the same bank or between active banks on every clock cycle.
Publication Release Date: Dec. 01, 2011
- 7 -
Revision A01
W9864G2JH
7.5 Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS
and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8 and full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.
7.6 Burst Command
The Burst Write command is initiated by applying logic low level to CS
,
CAS and WE while holding
RAS high at the rising edge of the clock. The address inputs determine the starting column address.
Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the
Write Command is issued. The remaining data inputs must be supplied on each subsequent rising
clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be
ignored.
7.7 Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS Latency from the
interrupting Read Command the is satisfied.
7.8 Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
7.9 Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
7.10 Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
Publication Release Date: Dec. 01, 2011
- 8 -
Revision A01
W9864G2JH
7.11 Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank, if the burst length is full
page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the
clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS Latency in
a burst read cycle, interrupted by Burst Stop.
7.12 Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
ACCESS ADDRESS
BURST LENGTH
n
BL = 2 (disturb address is A0)
No address carry from A0 to A1
BL = 4 (disturb addresses are A0 and A1)
No address carry from A1 to A2
n + 1
n + 2
n + 3
n + 4
n + 5
n + 6
n + 7
BL = 8 (disturb addresses are A0, A1 and A2)
No address carry from A2 to A3
7.13 Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 4
BL = 8
Publication Release Date: Dec. 01, 2011
Revision A01
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W9864G2JH
7.14 Auto-precharge Command
If A10 is set to high when the Read or Write Command is issued, then the Auto-precharge function is
entered. During Auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS Latency.
A Read or Write Command with Auto-precharge cannot be interrupted before the entire burst
operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is
prohibited during a read or write cycle with Auto-precharge. Once the precharge operation has started,
the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-
precharge command is illegal if the burst is set to full page length. If A10 is high when a Write
Command is issued, the Write with Auto-precharge function is initiated. The SDRAM automatically
enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred
to as write tWR. The bank undergoing Auto-precharge cannot be reactivated until tWR and tRP are
satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-
precharge Command, the interval between the Bank Activate Command and the beginning of the
internal precharge operation must satisfy tRAS (min).
7.15 Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when CS
,
RAS and WE are low and CAS is high at the rising
edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. Three address bits, A10, BS0 and BS1 are used to define which bank(s) is to
be precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(tRP).
7.16 Self Refresh Command
The Self Refresh Command is defined by having CS
RAS CAS and CKE held low with WE high
, ,
at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will
exit Self Refresh operation after CKE is returned high. Any subsequent commands can be issued after
tXSR from the end of Self Refresh Command.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.
Publication Release Date: Dec. 01, 2011
- 10 -
Revision A01
W9864G2JH
7.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCKS (min.) + tCK (min.).
7.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS
,
CAS and WE held high at the rising edge of
the clock. A No Operation Command will not terminate a previous operation that is still executing, such
as a burst read or write cycle.
7.19 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS
,
CAS and WE signals become don’t cares.
7.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
Publication Release Date: Dec. 01, 2011
- 11 -
Revision A01
W9864G2JH
8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
TABLE 1 TRUTH TABLE (NOTE (1), (2))
Device State CKEn-1 CKEn DQM BS0, 1 A10 A0-A9
COMMAND
RAS CAS WE
CS
L
Bank Active
Idle
Any
H
H
H
H
H
H
H
H
H
H
H
H
H
x
x
x
x
x
x
x
x
x
x
x
H
L
x
x
x
x
x
x
x
x
x
x
x
x
x
v
v
x
v
v
v
v
v
x
x
x
x
x
v
L
H
L
H
L
H
v
V
x
x
v
v
v
v
v
x
x
x
x
x
L
L
H
H
H
L
H
L
Bank Precharge
Precharge All
L
Any
L
L
L
Write
Active (3)
Active (3)
Active (3)
Active (3)
Idle
L
H
H
H
H
L
L
Write with Auto-precharge
Read
L
L
L
L
L
H
H
L
Read with Auto-precharge
Mode Register Set
No-Operation
L
L
L
L
Any
x
L
H
H
x
H
H
x
H
L
Burst Stop
Active (4)
x
L
Device Deselect
Auto-Refresh
Any
x
H
L
x
Idle
x
L
L
H
H
Self-Refresh Entry
Idle
x
L
L
L
idle
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
x
x
x
Self Refresh Exit
(S.R)
H
H
Clock suspend Mode
Entry
Active
H
L
x
x
x
x
x
x
x
x
Idle
H
H
L
L
x
x
x
x
x
x
x
x
H
L
x
x
X
H
Power Down Mode Entry
Clock Suspend Mode Exit
Active (5)
H
H
Active
L
H
x
x
x
x
x
x
x
X
Any
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
x
X
H
Power Down Mode Exit
(power
down)
H
H
Data write/Output Enable
Data Write/Output Disable
Active
Active
H
x
x
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
H
H
Notes:
(1) v = valid, x = Don’t care, L = Low Level, H = High Level
(2) CKEn signal is input leve l when commands are provided.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
Publication Release Date: Dec. 01, 2011
Revision A01
- 12 -
W9864G2JH
8.1 Simplified Stated Diagram
Self
Refresh
F
L
E
S
it
ex
F
L
E
S
Mode
Register
Set
MRS
REF
CBR
Refresh
IDLE
C
K
E
C
K
E
Power
Down
CKE
Active
Power
Down
ROW
ACTIVE
CKE
BST
A
e
R
u
e
BST
e
ad
rg
t
it
o
r
a
R
h
t
h
pr
W
e
i
c
a
e
w
e
Write
d
c
Read
CKE
CKE
e
pr
h
w
it
a
r
o
it
t
rg
h
u
W
e
A
CKE
CKE
Read
WRITE
READ
WRITE
READ
SUSPEND
SUSPEND
Write
)
P
n
R
CKE
CKE
CKE
CKE
io
E
t
WRITEA
SUSPEND
READA
SUSPEND
a
(
READA
WRITEA
p
in
re
c
rm
h
e
t
a
rg
e
e
rg
a
t
e
h
rm
c
re
in
a
p
(
t
E
io
R
n
)
P
POWER
ON
Precharge
Precharge
Automatic sequence
Manual input
MRS = Mode Register Set
REF = Refresh
ACT = Active
PRE = Precharge
WRITEA = Write with Auto-precharge
READA = Read with Auto-precharge
Publication Release Date: Dec. 01, 2011
Revision A01
- 13 -
W9864G2JH
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT NOTES
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ VDD + 0.5 (< 4.6V max.)
V
V
1
1
1
1
1
1
1
1
Voltage on VDD/VDDQ supply relative to VSS VDD, VDDQ
-0.5 ~ 4.6
0 ~ 70
-40 ~ 85
-55 ~ 150
260
Operating Temperature (-5/-6/-7)
Operating Temperature (-6I/-6A)
Storage Temperature
TOPR
TOPR
TSTG
TSOLDER
PD
°C
°C
°C
°C
W
Soldering Temperature (10s)
Power Dissipation
1
Short Circuit Output Current
IOUT
50
mA
Note:
1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of
the device.
9.2 Recommended DC Operating Conditions
(TA = 0 to 70°C for -5/-6/-7, TA = -40 to 85°C for -6I/-6A)
PARAMETER
SYM. MIN.
TYP.
MAX.
UNIT
NOTES
Power Supply Voltage for -6/-6I/-6A
VDD
3.0
3.0
3.3
3.6
V
Power Supply Voltage (I/O Buffer) for -6/-6I/-6A
VDDQ
3.3
3.6
V
Power Supply Voltage for -7
Power Supply Voltage (I/O Buffer) for -7
Input High Voltage
VDD
VDDQ
VIH
2.7
2.7
2
3.3
3.6
V
V
3.3
3.6
-
-
-
-
-
-
VDD + 0.3
V
1
Input Low Voltage
VIL
-0.3
2.4
-
+0.8
-
V
2
IOH= -2mA
Output logic high voltage
Output logic low voltage
Input leakage current
VOH
VOL
II(L)
V
IOL= 2mA
0.4
10
10
V
-10
-10
µA
µA
3
4
Output leakage current
Io(L)
Note:
1. VIH (max.) = VDD/VDDQ+1.5V for pulse width < 5 nS.
2. VIL (min.) = VSS/VSSQ-1.5V for pulse width < 5 nS.
3. Any input 0V<VIN<VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Output disabled, 0V ≤ VOUT ≤ VDDQ
Publication Release Date: Dec. 01, 2011
Revision A01
- 14 -
W9864G2JH
9.3 Capacitance
(VDD = 3.3V±0.3V for -5/-6/-6I/-6A, VDD = 2.7V-3.6V for -7, TA = 25°C, f = 1 MHz)
PARAMETER
SYM.
MIN.
MAX.
UNIT
Input Capacitance
Ci
2.5
4
pf
(A0 to A10, BS0, BS1, CS
Input Capacitance (CLK)
RAS CAS
, , ,
WE , DQM, CKE)
CCLK
Co
2.5
4
4
pf
pf
6.5
Input/Output capacitance (DQ0DQ31)
Note: These parameters are periodically sampled and not 100% tested
9.4 DC Characteristics
(VDD = 3.3V±0.3V for -6, VDD = 2.7V-3.6V for -7 on TA = 0 to 70°C, VDD = 3.3V±0.3V for -6I/-6A on TA = -40 to 85°C)
MAX.
-6/-6I/-6A
PARAMETER
SYM.
UNIT NOTES
-5
-7
Operating Current
tCK = min., tRC = min.
Active precharge command
cycling without burst operation
1 Bank Operation
CKE = VIH
IDD1
90
80
75
3
Standby Current
IDD2
IDD2P
IDD2S
25
2
25
2
25
2
3
3
tCK = min., CS = VIH
VIH/L = VIH (min.)/VIL (max.)
CKE = VIL
(Power Down mode)
Bank: Inactive State
Standby Current
CKE = VIH
15
15
15
CLK = VIL, CS = VIH
VIH/L=VIH (min.)/VIL (max.)
CKE = VIL
(Power Down mode)
Bank: Inactive State
IDD2PS
IDD3
2
2
2
mA
No Operating Current
CKE = VIH
60
10
55
10
50
10
tCK = min., CS = VIH (min.)
CKE = VIL
(Power Down mode)
Bank: Active State (4 Banks)
IDD3P
Burst Operating Current
(tCK = min.)
Read/Write command cycling
IDD4
IDD5
145
155
130
140
120
130
3, 4
3
Auto Refresh Current
(tCK = min.)
Auto refresh command cycling
Self Refresh Current
Self refresh mode
(CKE = 0.2V)
IDD6
2
2
2
Publication Release Date: Dec. 01, 2011
Revision A01
- 15 -
W9864G2JH
9.5 AC Characteristics and Operating Condition
(VDD = 3.3V±0.3V for -5/-6, VDD = 2.7V~3.6V for -7 on TA = 0 to 70°C, VDD = 3.3V±0.3V for -6I/-6A on TA = -40 to 85°C)
(Notes: 5, 6)
-5
-6/-6I/-6A
MIN. MAX.
-7
PARAMETER
SYM.
UNIT NOTES
MIN.
MAX.
MIN. MAX.
Ref/Active to Ref/Active Command
Period
55
60
65
tRC
tRAS
tRCD
Active to precharge Command Period
40 100000 42 100000 45 100000 nS
Active to Read/Write Command Delay
Time
15
18
20
Read/Write(a) to Read/Write(b)
Command Period
1
1
1
tCCD
tRP
tCK
nS
Precharge to Active Command Period
15
10
18
12
20
14
Active(a) to Active(b) Command
Period
tRRD
CL* = 2
Write Recovery Time
CL* = 3
2
2
2
2
2
2
tWR
tCK
CL* = 2
CLK Cycle Time
10
5
1000
1000
7.5
6
1000
1000
10
7
1000
1000
tCK
tCH
tCL
CL* = 3
2
2
2
8
8
CLK High Level width
CLK Low Level width
2
2
2
CL* = 2
Access Time from CLK
CL* = 3
6
5.5
5
6
9
9
7
9
tAC
tOH
tHZ
4.5
5.5
3
3
3
Output Data Hold Time
CL* = 2
CL* = 3
6
6
5
6
Output Data High
Impedance Time
4.5
5.5
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK (Rise and Fall)
Data-in Set-up Time
0
0
0
0
0
0
tLZ
tSB
nS
5
1
6
1
7
1
tT
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
8
8
8
8
8
8
8
8
tDS
Data-in Hold Time
tDH
Address Set-up Time
tAS
Address Hold Time
tAH
CKE Set-up Time
tCKS
tCKH
tCMS
tCMH
tREF
tRSC
tXSR
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
64
64
64
mS
tCK
nS
Mode register Set Cycle Time
Exit self refresh to ACTIVE command
*CL = CAS Latency
2
2
2
70
72
75
Publication Release Date: Dec. 01, 2011
Revision A01
- 16 -
W9864G2JH
Notes:
1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices.
2. All voltages are referenced to VSS
.
• 2.7V~3.6V power supply for -7 speed grades.
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum
values of tCK and tRC
.
4. These parameters depend on the output loading conditions. Specified values are obtained with output open.
5. Power up sequence please refer to “Functional Description” section described before.
6. AC test load diagram.
1.4 V
50 ohms
output
Z = 50 ohms
30pF
ACTEST LOAD
7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output
level.
8. Assumed input rise and fall time (tT) = 1nS.
If tr & tf is longer than 1nS, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]nS should be added to the parameter.
9. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter.
Publication Release Date: Dec. 01, 2011
- 17 -
Revision A01
W9864G2JH
10. TIMING WAVEFORMS
10.1 Command Input Timing
tCK
tCL
tCH
VIH
CLK
VIL
tT
tT
tCMS
tCMH
tCMS
tCMH
tCMH
CS
tCMS
RAS
tCMS
tCMS
tCMH
tCMH
tAH
CAS
WE
tAS
A0-A10
BS0,1
tCKS
tCKH
tCKS
tCKH
tCKS
tCKH
CKE
Publication Release Date: Dec. 01, 2011
Revision A01
- 18 -
W9864G2JH
10.2 Read Timing
Read CAS Latency
CLK
CS
RAS
CAS
WE
A0-A10
BS0,1
tHZ
tAC
tAC
tOH
tLZ
tOH
Valid
Data-Out
Valid
Data-Out
DQ
Read Command
Burst Length
Publication Release Date: Dec. 01, 2011
Revision A01
- 19 -
W9864G2JH
10.3 Control Timing of Input/Output Data
Control Timing of Input Data
(Word Mask)
CLK
tCMH
tCMS
tCMH
tCMS
tDS
DQM
tDS
tDH
tDH
tDS
tDH
tDS
tDH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
DQ0~31
(Clock Mask)
CLK
tCKH
tCKS
tDS
tCKH
tDH
tCKS
CKE
tDH
tDS
tDH
tDS
tDH
tDS
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
DQ0~31
Control Timing of Output Data
(Output Enable)
CLK
tCMS
tCMH
tCMS
tCMH
DQM
tAC
tOH
tAC
tAC
tHZ
tOH
tAC
tLZ
tOH
tOH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
DQ0~31
OPEN
(Clock Mask)
CLK
tCKS
tCKH
tCKS
tCKH
CKE
tAC
tAC
tAC
tAC
tOH
tOH
tOH
tOH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
DQ0~31
Publication Release Date: Dec. 01, 2011
Revision A01
- 20 -
W9864G2JH
10.4 Mode Register Set Cycle
tRSC
CLK
tCMS
tCMS
tCMS
tCMH
tCMH
tCMH
CS
RAS
CAS
WE
tCMS
tAS
tCMH
tAH
A0-A10
BS0,1
Register
set data
next
command
Burst Length
A0
A1
Sequential
A2 A1A0
Interleave
Burst Length
Addressing Mode
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
A2
A3
Reserved
Full Page
0
A4
Reserved
1
1
A5
Addressing Mode
A6
A3
0
1
Sequential
Interleave
A7
0
0
(Test Mode)
Reserved
A8
CAS Latency
Reserved
Reserved
2
A6 A5A4
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
A9
Write Mode
Reserved
0
0
0
A10
BS0
3
Reserved
Mode
Register Set
Single Write Mode
Burst read and Burst write
Burst read and single write
BS1
A9
0
1
* "Reserved" should stay "0" during MRS cycle.
Publication Release Date: Dec. 01, 2011
Revision A01
- 21 -
W9864G2JH
11. OPERATING TIMING EXAMPLE
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
0
CLK
CS
tRC
tRC
tRC
tRC
RAS
CAS
tRP
tRAS
tRP
tRAS
tRAS
tRP
tRAS
WE
BS0
BS1
A10
tRCD
tRCD
tRCD
tRCD
RBb
RAa
RAa
RAe
RAe
RAc
RBd
RBd
CAw
CBx
RBb
RAc
CAy
CBz
A0-A9
DQM
CKE
tAC
tAC
tAC
tAC
bx3
cy0 cy1
cy2 cy3
aw0 aw1 aw2 aw3
bx1 bx2
bx0
DQ
tRRD
tRRD
tRRD
tRRD
Precharge
Read
Active
Active
Read
Bank #0
Active
Read
Precharge
Precharge
Bank #1
Bank #2
Bank #3
Active
Read
Active
Idle
Publication Release Date: Dec. 01, 2011
Revision A01
- 22 -
W9864G2JH
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
10
0
CLK
CS
tRC
tRC
tRC
tRC
RAS
CAS
WE
tRAS
tRP
tRAS
tRP
tRP
tRAS
BS0
BS1
tRCD
tRCD
tRCD
tRCD
RAa
RBb
RBd
RAc
RAe
A10
RAa
CAw RBb
CBx
RAc
CAy
RBd
CBz
RAe
A0-A9
DQM
CKE
tAC
tAC
tAC
tAC
aw2 aw3
aw0 aw1
bx0
bx1
bx2 bx3
cy0 cy1
cy2 cy3
dz0
DQ
tRRD
tRRD
tRRD
tRRD
Read
Active
AP*
Read
Active
Active
AP*
Bank #0
Read
Active
Read
Active
AP*
Bank #1
Bank #2
Bank #3
Idle
* AP is the internal precharge start timing
Publication Release Date: Dec. 01, 2011
Revision A01
- 23 -
W9864G2JH
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
8
9
10 11 12 13 14 15 16 17 18
1
2
3
4
5
6
7
19 20 21 22 23
0
CLK
CS
tRC
RAS
CAS
tRAS
tRP
tRP
tRAS
WE
BS0
BS1
A10
tRCD
tRCD
tRCD
RAa
RAa
RBb
RBb
RAc
CAx
CBy
RAc
CAz
A0-A9
DQM
CKE
tAC
tAC
ax6
tAC
by4
by5
by6
by7
CZ0
ax0
ax1
ax2
ax3
ax4
ax5
by0
by1
DQ
tRRD
tRRD
Read
Active
Idle
Precharge
Active
Read
Bank #0
Bank #1
Bank #2
Bank #3
Active
Precharge
Precharge
Read
Publication Release Date: Dec. 01, 2011
Revision A01
- 24 -
W9864G2JH
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
21 22 23
0
CLK
CS
tRC
RAS
tRAS
tRP
tRAS
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
tRCD
tRCD
RAc
RAa
RAa
RBb
RBb
A10
CAx
CBy
RAc
CAz
A0-A9
DQM
CKE
tAC
tAC
tAC
by0
ax3
ax4
ax5 ax6
ax7
by1
by4
by5
by6
CZ0
ax0
ax1
ax2
DQ
tRRD
tRRD
AP*
Read
Active
Bank #0 Active
Bank #1
Read
Active
Read
AP*
Bank #2
Idle
* AP is the internal precharge start timing
Bank #3
Publication Release Date: Dec. 01, 2011
Revision A01
- 25 -
W9864G2JH
11.5 Interleaved Bank Write (Burst Length = 8)
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
1
2
3
4
5
0
CLK
CS
tRC
RAS
CAS
tRAS
tRP
tRAS
tRCD
tRCD
tRCD
WE
BS0
BS1
RBb
RAc
RAa
RAa
A10
CAx
RBb
CBy
RAc
CAz
A0-A9
DQM
CKE
ax0
ax1
ax4
ax5
ax6
ax7
by0
by1
by2
by3
CZ2
by4
by5
by6
by7
CZ0
CZ1
DQ
tRRD
tRRD
Active
Write
Precharge
Write
Active
Write
Active
Precharge
Bank #0
Bank #1
Idle
Bank #2
Bank #3
Publication Release Date: Dec. 01, 2011
Revision A01
- 26 -
W9864G2JH
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
tRC
RAS
CAS
tRP
tRAS
tRAS
WE
BS0
BS1
A10
tRCD
tRCD
tRCD
RAa
RAa
RBb
RBb
RAb
CAx
CBy
RAc
CAz
A0-A9
DQM
CKE
ax0
ax1
ax4
ax5
ax6
ax7
by0
by1 by2 by3
by4
by5
by6
by7 CZ0
CZ1
CZ2
DQ
tRRD
tRRD
AP*
Write
Write
AP*
Active
Active
Write
Bank #0
Bank #1
Bank #2
Bank #3
Active
Idle
* AP is the internal precharge start timing
Publication Release Date: Dec. 01, 2011
Revision A01
- 27 -
W9864G2JH
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
tCCD
tCCD
tCCD
tRAS
tRAS
RAS
CAS
WE
BS0
BS1
tRCD
tRCD
RAa
RAa
RBb
A10
CAI RBb
CBx
CAy
CAm
CBz
A0-A9
DQM
CKE
tAC
tAC
tAC
tAC
tAC
a0
a1
a2
a3
bx0
bx1
Ay0
Ay1 Ay2 am0 am1 am2
bz0
bz1
bz2
bz3
DQ
tRRD
Read
Bank #0 Active
Bank #1
Read
Read
Precharge
AP*
Active
Read
Read
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Publication Release Date: Dec. 01, 2011
Revision A01
- 28 -
W9864G2JH
11.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)
6
7
8
11
12
13
16
17
18
1
2
3
5
9
10
14
15
19
21
0
4
20
22
23
CLK
CS
tRAS
RAS
CAS
WE
BS0
BS1
A10
tRCD
RAa
RAa
CAx
CAy
A0-A9
DQM
CKE
tAC
tWR
ay1
ay0
ay2
ay3
ay4
ax0
ax1
ax2
ax3
ax4
ax5
DQ
Q Q
Q
Q
Q
Q
D
D
D
D
D
Bank #0 Active
Bank #1
Read
Write
Precharge
Bank #2
Idle
Bank #3
Publication Release Date: Dec. 01, 2011
Revision A01
- 29 -
W9864G2JH
11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3)
6
7
8
11
12
13
16
17
18
1
2
3
5
9
10
14
15
19
21
0
4
20
22
23
CLK
CS
tRC
RAS
tRAS
tRP
tRAS
CAS
WE
BS0
BS1
A10
tRCD
tRCD
RAa
RAb
CAx
RAa
CAw
RAb
A0-A9
DQM
CKE
tAC
tAC
aw0
aw1 aw2 aw3
bx0
bx1
bx2
bx3
DQ
AP*
Active
Idle
Read
Active
Read
AP*
Bank #0
Bank #1
Bank #2
Bank #3
* AP is the internal precharge start timing
Publication Release Date: Dec. 01, 2011
Revision A01
- 30 -
W9864G2JH
11.10 Auto-precharge Write (Burst Length = 4)
6
7
8
11
12
13
16
17
18
1
2
3
5
9
10
14
15
19
21
0
4
20
22
23
CLK
CS
tRC
tRC
RAS
CAS
tRAS
tRP
tRAS
tRP
WE
BS0
BS1
tRCD
tRCD
RAb
RAc
RAa
RAa
A10
CAw
RAb
CAx
RAc
A0-A9
DQM
CKE
aw0 aw1 aw2 aw3
bx0
bx1 bx2
bx3
DQ
Active
Idle
Bank #0
Write
Active
Write
Active
AP*
AP*
Bank #1
Bank #2
Bank #3
* AP is the internal precharge start timing
Publication Release Date: Dec. 01, 2011
Revision A01
- 31 -
W9864G2JH
11.11 Auto Refresh Cycle
6
7
8
11 12 13
16 17 18
1
2
3
5
9
10
14 15
19
21
0
4
20
22 23
CLK
CS
tRP
tRC
tRC
RAS
CAS
WE
BS0,1
A10
A0-A9
DQM
CKE
DQ
All Banks
Prechage
Auto
Refresh
Auto Refresh (Arbitrary Cycle)
Publication Release Date: Dec. 01, 2011
Revision A01
- 32 -
W9864G2JH
11.12 Self Refresh Cycle
CLK
CS
tRP
RAS
CAS
WE
BS0,1
A10
A0-A9
DQM
tCKS
tSB
CKE
tCKS
DQ
tXSR
Self Refresh Cycle
No Operation / Command Inhibit
All Banks
Precharge
Self Refresh
Entry
Self Refresh
Exit
Arbitrary Cycle
Publication Release Date: Dec. 01, 2011
Revision A01
- 33 -
W9864G2JH
11.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
RAS
CAS
WE
tRCD
BS0
BS1
A10
RBa
RBa
CBv
CBw
CBx CBy CBz
A0-A9
DQM
CKE
tAC
tAC
av0
av1
av2
av3
aw0
ax0
ay0
az0
az1
az2
az3
DQ
Q
Q
Q
Q
D
D
D
Q
Q
Q
Q
Active
Read
Single Write Read
Bank #0
Bank #1
Bank #2
Bank #3
Idle
Publication Release Date: Dec. 01, 2011
Revision A01
- 34 -
W9864G2JH
11.14 Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
WE
BS
RAa
RAa
RAa
RAa
A10
CAa
CAx
A0-A9
DQM
CKE
tSB
tSB
tCKS
tCKS
tCKS
tCKS
ax0
ax1
ax2
ax3
DQ
Active
NOP Read
Precharge
NOP Active
Precharge Standby
Power Down mode
Active Standby
Power Down mode
Note: The Power Down Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
Violating refresh requirements during power-down may result in a loss of data.
Publication Release Date: Dec. 01, 2011
Revision A01
- 35 -
W9864G2JH
11.15 Auto-precharge Timing (Write Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
(1) CAS Latency = 2
(a) burst length = 1
Command
Write
D0
AP
Act
tWR
tRP
DQ
(b) burst length = 2
Command
Write
D0
AP
Act
AP
tWR
tRP
DQ
D1
D1
(c) burst length = 4
Command
Act
D7
Write
D0
tRP
tWR
DQ
D2
D3
D3
(d) burst length = 8
Command
Write
D0
AP
Act
tWR
tRP
DQ
D1
D2
AP
D4
D5
D6
(2) CAS Latency = 3
(a) burst length = 1
Command
Write
D0
Act
tWR
tRP
DQ
(b) burst length = 2
Command
Write
D0
AP
Act
tWR
tRP
DQ
D1
D1
D1
(c) burst length = 4
Command
Write
D0
AP
D5
Act
tWR
tRP
DQ
D2
D2
D3
D3
(d) burst length = 8
Command
Write
D0
AP
Act
tWR
tRP
DQ
D4
D6
D7
Note )
represents the Write with Auto precharge command.
represents the start of internal precharing.
represents the Bank Active command.
Write
AP
Act
When the /auto precharge command is asserted,the period f rom Bank Activate
command to the start of intermal precgarging must be at least tRAS (min).
Publication Release Date: Dec. 01, 2011
Revision A01
- 36 -
W9864G2JH
11.16 Auto-precharge Timing (Read Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
(1) CAS Latency=2
( a ) burst length = 1
Command
Read
AP
Act
tRP
DQ
Q0
( b ) burst length = 2
Command
Read
Read
Read
AP
Q0
Act
tRP
DQ
Q1
( c ) burst length = 4
Command
AP
Q2
Act
Q4
tRP
DQ
Q0
Q0
Q1
Q1
Q3
( d ) burst length = 8
Command
AP
Q6
Act
tRP
DQ
Q2
Act
Q3
Act
Q5
Q7
(2) CAS Latency=3
( a ) burst length = 1
Command
Read
Read
Read
Read
AP
tRP
DQ
Q0
Q0
Q0
Q0
( b ) burst length = 2
Command
AP
tRP
DQ
Q1
AP
Q1
( c ) burst length = 4
Command
Act
Q4
tRP
DQ
Q2
Q2
Q3
Q3
( d ) burst length = 8
Command
AP
Q5
Act
tRP
DQ
Q1
Q6
Q7
Note:
Read
AP
Act
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least tRAS (min).
Publication Release Date: Dec. 01, 2011
Revision A01
- 37 -
W9864G2JH
11.17 Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
1
2
3
4
5
6
7
8
9
10
11
0
(1) CAS Latency=2
( a ) Command
Read
Write
DQM
DQ
D0
D1
D2
D3
( b ) Command
Read
Write
DQM
DQ
D0
D1
D2
D2
D3
D3
(2) CAS Latency=3
( a ) Command
Read
Read
Write
D0
DQM
DQ
D1
( b ) Command
Write
DQM
DQ
D0
D1
D2
D3
Note: The Output data must be masked by DQMto avoid I/O conflict.
11.18 Timing Chart of Write to Read Cycle
In the case of Burst Length=4
1
2
3
4
5
6
7
8
9
10
11
0
(1) CAS Latency=2
Write Read
( a ) Command
DQM
DQ
D0
Q0
Q1
Q0
Q2
Q1
Q3
Q2
( b ) Command
DQM
Read
Write
DQ
D0
D1
Q3
(2) CAS Latency=3
( a ) Command
DQM
Write Read
DQ
D0
Q0
Q1
Q0
Q2
Q1
Q3
Q2
( b ) Command
DQM
Write
Read
DQ
D0
D1
Q3
Publication Release Date: Dec. 01, 2011
Revision A01
- 38 -
W9864G2JH
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
( a ) CAS latency =2
Command Read
BST
Q3
DQ
Q0
Q1
Q0
Q2
Q1
Q4
Q3
( b )CAS latency = 3
Command
Read
BST
Q2
DQ
Q4
(2) Write cycle
Command
Write
Q0
BST
DQ
Q1
Q2
Q3
Q4
Note: BST
represents the Burst stop command
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
(a) CAS latency =2
Command
Read
Read
PRCG
Q3
DQ
Q0
Q1
Q0
Q2
Q1
Q4
Q3
(b) CAS latency =3
Command
PRCG
Q2
DQ
Q4
(2) Write cycle
Write
Q0
PRCG
Command
tWR
DQM
DQ
Q1
Q2
Q3
Q4
Publication Release Date: Dec. 01, 2011
Revision A01
- 39 -
W9864G2JH
11.21 CKE/DQM Input Timing (Write Cycle)
1
CLK cycle No.
2
3
4
5
7
6
External
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D5
D6
DQM MASK
CKE MASK
( 1 )
CLK cycle No.
External
2
3
4
5
7
1
6
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D6
D5
DQM MASK
( 2 )
CKE MASK
1
2
3
4
5
6
7
CLK cycle No.
External
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D4
D5
D6
CKE MASK
( 3 )
Publication Release Date: Dec. 01, 2011
Revision A01
- 40 -
W9864G2JH
11.22 CKE/DQM Input Timing (Read Cycle)
1
CLK cycle No.
6
2
3
4
5
7
External
Internal
CLK
CKE
DQM
DQ
Q6
Q1
Q2
Q3
Q4
Open
Open
( 1 )
1
2
3
4
5
7
CLK cycle No.
6
External
Internal
CLK
CKE
DQM
DQ
Q6
Q3
Q1
Q2
Q4
Open
( 2 )
1
CLK cycle No.
2
3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
Q6
Q1
Q4
Q5
Q3
Q2
( 3 )
Publication Release Date: Dec. 01, 2011
Revision A01
- 41 -
W9864G2JH
12. PACKAGE SPECIFICATION
12.1 86L TSOP (II)-400 mil
86
44
HE
E
1
43
e
b
C
D
q
L
A2
A1
A
L1
ZD
Y
SEATING PLANE
Controlling Dimension: Millimeters
DIMENSION
(MM)
DIMENSION
(INCH)
SYM.
MIN.
NOM.
MAX. MIN.
MAX.
NOM.
1.20
0.047
0.006
A
A1
0.15
0.05
0.002
1.00
0.039
A2
b
0.17
0.12
0.27
0.21
0.007
0.005
0.011
0.008
0.905
0.404
0.471
c
22.12
10.06
11.56
22.22
10.16
11.76
0.50
22.62
10.26
11.96
0.871
0.396
0.455
0.875
0.400
0.463
0.020
0.020
0.032
D
E
HE
e
0.40
0.50
0.60
0.10
0.016
0.024
0.004
L
0.80
L1
Y
ZD
0.61
0.024
Publication Release Date: Dec. 01, 2011
Revision A01
- 42 -
W9864G2JH
13. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A01
Dec. 01, 2011
All
Initial formal data sheet
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Publication Release Date: Dec. 01, 2011
- 43 -
Revision A01
相关型号：
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