W9864G6DB-7 [WINBOND]
1M x 4 BANKS x 16 BITS SDRAM; 1M ×4银行×16位的SDRAM
| 型号： | W9864G6DB-7 |
| 厂家： | 
WINBOND |
| 描述： | 1M x 4 BANKS x 16 BITS SDRAM |
| 文件： | 总48页 (文件大小：1383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W9864G6DB
1M × 4 BANKS × 16 BITS SDRAM
Table of Contents-
1. GENERAL DESCRIPTION.................................................................................................................. 3
2. FEATURES ......................................................................................................................................... 3
3. AVAILABLE PART NUMBER.............................................................................................................. 3
4. PIN CONFIGURATION ....................................................................................................................... 4
5. PIN DESCRIPTION............................................................................................................................. 5
6. BLOCK DIAGRAM .............................................................................................................................. 6
7. FUNCTIONAL DESCRIPTION............................................................................................................ 7
Power Up and Initialization................................................................................................................ 7
Programming Mode Register ............................................................................................................ 7
Bank Activate Command................................................................................................................... 7
Read and Write Access Modes......................................................................................................... 7
Burst Read Command....................................................................................................................... 8
Burst Command ................................................................................................................................ 8
Read Interrupted by a Read.............................................................................................................. 8
Read Interrupted by a Write.............................................................................................................. 8
Write Interrupted by a Write .............................................................................................................. 8
Write Interrupted by a Read.............................................................................................................. 8
Burst Stop Command........................................................................................................................ 8
Addressing Sequence of Sequential Mode....................................................................................... 9
Addressing Sequence of Interleave Mode........................................................................................ 9
Auto Precharge Command.............................................................................................................. 10
Precharge Command...................................................................................................................... 10
Self Refresh Command................................................................................................................... 10
Power Down Mode.......................................................................................................................... 10
No Operation Command ................................................................................................................. 11
Deselect Command......................................................................................................................... 11
Clock Suspend Mode...................................................................................................................... 11
Table of Operating Modes............................................................................................................... 12
Simplified State Diagram................................................................................................................. 13
8. DC CHARACTERISTICS .................................................................................................................. 14
Absolute Maximum Rating .............................................................................................................. 14
Recommended DC Operating Conditions....................................................................................... 14
Capacitance .................................................................................................................................... 14
Publication Release Date: January 27, 2003
- 1 -
Revision A1
W9864G6DB
DC Characteristics .......................................................................................................................... 15
9. AC CHARACTERISTICS .................................................................................................................. 16
10. TIMING WAVEFORMS ................................................................................................................... 19
Command Input Timing................................................................................................................... 19
Read Timing.................................................................................................................................... 20
Control Timing of Input Data ........................................................................................................... 21
Control Timing of Output Data ........................................................................................................ 22
Mode Register Set Cycle ................................................................................................................ 23
11. OPERATING TIMING EXAMPLE.................................................................................................... 24
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ........................................................ 24
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge)............................. 25
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ........................................................ 26
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge)............................. 27
Interleaved Bank Write (Burst Length = 8)...................................................................................... 28
Interleaved Bank Write (Burst Length = 8, Auto Precharge) .......................................................... 29
Page Mode Read (Burst Length = 4, CAS Latency = 3)................................................................. 30
Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ....................................................... 31
Auto Precharge Read (Burst Length = 4, CAS Latency = 3) .......................................................... 32
Auto Precharge Write (Burst Length = 4)........................................................................................ 33
Auto Refresh Cycle ......................................................................................................................... 34
Self Refresh Cycle........................................................................................................................... 35
Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)................................................. 36
Power Down Mode.......................................................................................................................... 37
Auto Precharge Timing (Write Cycle) ............................................................................................. 38
Auto Precharge Timing (Read Cycle) ............................................................................................. 39
Timing Chart of Read to Write Cycle............................................................................................... 40
Timing Chart of Write to Read Cycle............................................................................................... 41
Timing Chart of Burst Stop Cycle (Burst Stop Command).............................................................. 42
Timing Chart of Burst Stop Cycle (Precharge Command).............................................................. 43
CKE/DQM Input Timing (Write Cycle)............................................................................................. 44
CKE/DQM Input Timing (Read Cycle) ............................................................................................ 45
Self Refresh/Power Down Mode Exit Timing.................................................................................. 46
12. PACKAGE DIMENSIONS ............................................................................................................... 47
BGA 60 Balls Pitch = 0.65 mm........................................................................................................ 47
13. VERSION HISTORY ....................................................................................................................... 48
- 2 -
W9864G6DB
1. GENERAL DESCRIPTION
W9864G6DB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1M words × 4 banks × 16 bits. Using pipelined architecture and 0.175 µm process technology,
W9864G6DB delivers a data bandwidth of up to 286M bytes per second (-7).
W9864G6DB -7.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9864G6DB is ideal for main memory in
high performance applications.
2. FEATURES
• 2.7V − 3.6V power supply
• 1048576 words × 4 banks × 16 bits organization
• Self refresh current: Standard and low power
• CAS latency: 2 and 3
• Burst Length: 1, 2, 4, 8, and full page
• Sequential and Interleave burst
• Burst read, single write operation
• Byte data controlled by DQM
• Power-down Mode
• Auto-precharge and controlled precharge
• 4K refresh cycles/ 64 mS
• Interface: LVTTL
• Packaged in BGA 60 balls pitch = 0.65 mm, using PB free materials
3. AVAILABLE PART NUMBER
PART NUMBER
SPEED (CL = 3)
SELF REFRESH CURRENT (MAX.)
W9864G6DB-7
143 MHz
1 mA
Publication Release Date: January 27, 2003
Revision A1
- 3 -
W9864G6DB
4. PIN CONFIGURATION
Top View
Bottom View
7 6
2 1
1 2
6 7
VDD
VDD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
VSS
DQ15
DQ0
DQ0
DQ15
VSS
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
NC
VSSQ
VDDQ
DQ11
VSSQ
VDDQ
NC
VDDQ
VSSQ
DQ4
VDDQ
VSSQ
NC
VDDQ
VSSQ
DQ4
VDDQ
VSSQ
NC
VSSQ
VDDQ
DQ11
VSSQ
VDDQ
NC
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
NC
VSS
UDQM
CLK
NC
VDD
LDQM
RAS#
NC
VDD
LDQM
RAS#
NC
VSS
UDQM
CLK
NC
WE#
CAS#
CS#
BS0
A10
WE#
NC
NC
CAS#
CS#
BS0
A10
A1
NC
NC
CKE
A11
A8
CKE
A11
A8
A9
BS1
BS1
A9
A7
A0
A0
A7
A1
A6
A5
A2
A2
A5
A6
VDD
VDD
VSS
A4
A3
A3
A4
VSS
- 4 -
W9864G6DB
5. PIN DESCRIPTION
BALL LOCATION PIN NAME FUNCTION
DESCRIPTION
Multiplexed pins for row and column address. Row
address: A0 − A11. Column address: A0 − A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
M1, M2, N1, N2,
N6, N7, P1, P2,
P6, P7, R6,
Address
A0 − A11
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
M6, M7
BS0, BS1 Bank Select
A2, A6, B1, B7,
C1, C7, D1, D2,
D6, D7, E1, E7,
F1, F7, G1, G7
Data Input/
Output
DQ0 −
Multiplexed pins for data output and input.
DQ15
Disable or enable the command decoder. When
L7
K6
Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
CS
Command input. When sampled at the rising edge of
Row Address
RAS
the clock RAS, CAS and WE define the
Strobe
operation to be executed.
Column
K7
J7
Address
Strobe
CAS
WE
Referred to RAS
Write Enable
Referred to RAS
The output buffer is placed at Hi-Z (with latency of 2)
UDQM
LDQM
Input/Output when DQM is sampled high in read cycle. In write
J6, J5
Mask
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
K2
L1
CLK
CKE
Clock Inputs
CKE controls the clock activation and deactivation.
Clock Enable When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
A7, H6, R7
A1, H2, R1
VDD
VSS
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside
Ground
DRAM.
Power (+3.3V) Separated power from VDD, to improve DQ noise
for I/O Buffer immunity.
B6, C2, E6, F2
B2, C6, E2, F6
VDDQ
VSSQ
NC
Ground for I/O Separated ground from VSS, to improve DQ noise
Buffer
immunity.
G2, G6, H1, H7,
J1, K1, L2, L6
No Connection No connection
Publication Release Date: January 27, 2003
Revision A1
- 5 -
W9864G6DB
6. BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
GENERATOR
RAS
CAS
COMMAND
DECODER
COLUMN DECODER
COLUMN DECODER
WE
CELL ARRAY
BANK #0
CELL ARRAY
BANK #1
A10
A0
MODE
REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
ADDRESS
BUFFER
A9
BS0
BS1
DQ0
DATA CONTROL
CIRCUIT
DQ
BUFFER
DQ15
COLUMN
COUNTER
REFRESH
COUNTER
UDQM
LDQM
COLUMN DECODER
COLUMN DECODER
CELL ARRAY
BANK #2
CELL ARRAY
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE:
The cell array configuration is 2048 * 256 * 32
- 6 -
W9864G6DB
7. FUNCTIONAL DESCRIPTION
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.
During power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage
when the input signals are held in the "NOP" state. The power up voltage must not exceed VDD +0.3V
on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required
followed by a precharge of all banks using the precharge command. To prevent data contention on
the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required
before or after programming the Mode Register to ensure proper subsequent operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of RAS, CAS , CS and WE at the positive edge of the clock. The address input data
during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A
new command may be issued following the mode register set command once a delay equal to tRSC has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is
specified as TRAS (max.).
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting
RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level
defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The
address inputs determine the starting column address. Reading or writing to a different row within an
activated bank requires the bank be precharged and a new Bank Activate command be issued. When
more than one bank is activated, interleaved bank Read or Write operations are possible. By using the
programmed burst length and alternating the access and precharge operations between multiple
banks, seamless data access operation among many different pages can be realized. Read or Write
Commands can also be issued to the same bank or between active banks on every clock cycle.
Publication Release Date: January 27, 2003
- 7 -
Revision A1
W9864G6DB
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding
RAS and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.
Burst Command
The Burst Write command is initiated by applying logic low level to CS , CAS and WE while
holding RAS high at the rising edge of the clock. The address inputs determine the starting column
address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank
open for future Read or Write Commands to the same page of the active bank, if the burst length is full
page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
- 8 -
W9864G6DB
Command is defined by having RAS and CAS high with CS and WE low at the rising edge of
the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS
Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a
full page burst write operation, then any residual data from the burst write cycle will be ignored.
Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
ACCESS ADDRESS
BURST LENGTH
n
BL = 2 (disturb address is A0)
No address carry from A0 to A1
BL = 4 (disturb addresses are A0 and A1)
No address carry from A1 to A2
n + 1
n + 2
n + 3
n + 4
n + 5
n + 6
n + 7
BL = 8 (disturb addresses are A0, A1 and A2)
No address carry from A2 to A3
Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
Data 0
Data 1
ACCESS ADDRESS
A8 A7 A6 A5 A4 A3 A2 A1 A0
BUST LENGTH
BL = 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
BL = 4
BL = 8
Publication Release Date: January 27, 2003
Revision A1
- 9 -
W9864G6DB
Auto Precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is
entered. During auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS latency.
A Read or Write Command with auto-precharge cannot be interrupted before the entire burst
operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is
prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started,
the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-
Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write
Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically
enters the precharge operation one clock delay from the last burst write cycle. This delay is referred to
as write tDPL. The bank undergoing auto-precharge cannot be reactivated until tDPL and tRP are satisfied.
This is referred to as tDAL, Data-in to Active delay (tDAL = tDPL + tRP). When using the Auto-precharge
Command, the interval between the Bank Activate Command and the beginning of the internal
precharge operation must satisfy tRAS (min).
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising
edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. Three address bits, A10, BS0, and BS1 are used to define which bank(s) is to
be precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(tRP).
Self Refresh Command
The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE
high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will
exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the
device exits Self Refresh Operation and before the next command can be issued. This delay is equal
to the tAC cycle time plus the Self Refresh exit time.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.
Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
- 10 -
W9864G6DB
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCES (min.) + tCK (min.).
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS, CAS , and WE held high at the rising edge of
the clock. A No Operation Command will not terminate a previous operation that is still executing,
such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS , CAS , and WE signals become don't
cares.
Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
Publication Release Date: January 27, 2003
- 11 -
Revision A1
W9864G6DB
Table of Operating Modes
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
TABLE 1 TRUTH TABLE (Note (1), (2))
DEVICE
COMMAND
Bank Active
CKEn-1 CKEn DQM BS0, 1 A10
A0−A9
CS
RAS CAS
WE
STATE
Idle
H
H
H
H
H
H
H
H
H
H
H
H
H
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
v
v
x
v
v
v
v
v
x
x
x
x
x
x
x
v
L
H
L
H
L
H
v
V
x
x
v
v
v
v
v
x
x
x
x
x
x
x
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
H
L
H
L
L
L
L
H
H
L
H
L
x
Bank Precharge
Precharge All
Any
Any
x
L
Write
Active (3)
Active (3)
Active (3)
Active (3)
Idle
x
H
H
H
H
L
Write with Auto Precharge
Read
x
L
x
L
Read with Auto Precharge
Mode Register Set
No-Operation
x
L
x
L
Any
x
x
H
H
x
H
H
x
Burst Stop
Active (4)
Any
x
x
Device Deselect
Auto Refresh
x
x
Idle
H
L
H
H
x
L
L
H
H
x
Self Refresh Entry
Idle
x
L
L
idle
x
x
x
Self Refresh Exit
(S.R)
L
x
H
H
x
Clock Suspend Mode
Entry
Active
H
L
x
x
x
x
x
x
x
x
Idle
Active (5)
Active
Any
H
H
L
L
L
x
x
x
x
x
x
x
x
x
x
x
x
H
L
x
x
H
x
x
H
x
X
H
X
Power Down Mode Entry
Clock Suspend Mode Exit
H
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
x
X
H
Power Down Mode Exit
(power
down)
H
H
Data Write/Output Enable
Data Write/Output Disable
Notes:
Active
Active
H
x
x
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
H
H
(1) v = valid, x = Don't care, L = Low Level, H = High Level
(2) CKEn signal is input leve l when commands are provided.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
- 12 -
W9864G6DB
Simplified State Diagram
Self
Refresh
Mode
Register
Set
MRS
REF
CBR
IDLE
Refresh
C
K
E
C
K
E
Power
Down
CKE
CKE
Active
Power
Down
ROW
ACTIVE
Write
Read
CKE
CKE
CKE
Read
WRITE
READ
WRITE
READ
SUSPEND
SUSPEND
CKE
Write
CKE
CKE
CKE
WRITEA
READA
READA
WRITEA
SUSPEND
SUSPEND
CKE
POWER
ON
Precharge
Precharge
Automatic sequence
Manual input
MRS = Mode Register Set
REF = Refresh
ACT = Active
PRE = Precharge
WRITEA = Write with Auto precharge
READA = Read with Auto precharge
Publication Release Date: January 27, 2003
Revision A1
- 13 -
W9864G6DB
8. DC CHARACTERISTICS
Absolute Maximum Rating
PARAMETER
Input, Column Output Voltage
Power Supply Voltage
Operating Temperature
Storage Temperature
SYM.
VIN, VOUT
VDD, VDDQ
TOPR
RATING
-0.3 − VDD +0.3
-0.3 − 4.6
0 − 70
UNIT
V
NOTES
1
1
1
1
1
1
1
V
°C
°C
°C
W
TSTG
-55 − 150
260
Soldering Temperature (10s)
Power Dissipation
Short Circuit Output Current
TSOLDER
PD
IOUT
1
50
mA
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Recommended DC Operating Conditions
(TA = 0 to 70°C)
PARAMETER
Power Supply Voltage
Power Supply Voltage (for I/O Buffer)
Input High Voltage
SYM.
VDD
VDDQ
VIH
MIN.
2.7
2.7
2.0
-0.3
TYP.
3.3
3.3
-
MAX.
3.6
3.6
VDD +0.3
0.8
UNIT
V
V
V
V
NOTES
2
2
2
2
Input Low Voltage
VIL
-
Note: VIH (max.) = VDD/VDDQ +1.2V for pulse width < 5 nS
VIL (min.) = VSS/VSSQ -1.2V for pulse width < 5 nS
Capacitance
(VDD = 3.3V, TA = 25 °C, f = 1 MHz)
PARAMETER
SYM.
MIN.
MAX.
UNIT
Input Capacitance
Ci
2.5
4
pF
(A0 to A11, BS0, BS1, CS , RAS , CAS , WE , DQM, CKE)
Input Capacitance (CLK)
CCLK
Co
2.5
4
4
6.5
pF
pF
Input/Output capacitance (DQ0 − DQ15)
Note: These parameters are periodically sampled and not 100% tested
- 14 -
W9864G6DB
DC Characteristics
(VDD = 3.6V ~2.7V, TA = 0°~70°C)
-7
PARAMETER
SYM.
UNIT
NOTES
MAX.
Operating Current
tCK = min., tRC = min.
1 bank operation
CKE = VIH
ICC1
80
3
Active precharge command cycling without
burst operation
Standby Current
tCK = min., CS = VIH
VIH/L = VIH (min.)/ VIL (max.)
ICC2
30
1
3
3
CKE = VIL (Power
Down mode)
Bank: Inactive State
Standby Current
ICC2P
CKE = VIH
ICC2S
8
CLK = VIL, CS = VIH
VIH/L=VIH (min.)/VIL (max.)
mA
CKE = VIL (Power
Down mode)
BANK: Inactive State
ICC2PS
1
55
5
No Operating Current
tCK = min., CS = VIH (min.)
CKE = VIH
ICC3
CKE = VIL (Power
Down mode)
BANK: active state (4 banks)
ICC3P
ICC4
Burst Operating Current
Read/Write command cycling
Auto Refresh Current
(tCK = min.)
145
3, 4
3
(tCK = min.)
ICC5
110
Auto refresh command cycling
Self Refresh Current
ICC6
1
mA
(CKE = 0.2V)
Self refresh mode
ICC6L
400
µA
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTES
Input Leakage Current
II(L)
-5
5
µA
(0V ≤ VIN ≤ VDD, all other pins not under test = 0V)
Output Leakage Current
VO(L)
VOH
-5
2.4
-
5
-
µA
V
(Output disable, 0V ≤ VOUT ≤ VDDQ)
″
″
LVTTL Output H Level Voltage
(IOUT = -2 mA)
"
″
LVTTL Output L Level Voltage
(IOUT = 2 mA)
VOL
0.4
V
Publication Release Date: January 27, 2003
Revision A1
- 15 -
W9864G6DB
9. AC CHARACTERISTICS
(VDD = 3.6V − 2.7V, VSS = 0V, TA = 0 to 70 °C) (Notes: 5, 6.)
-7
PARAMETER
SYMBOL
UNIT
MAX.
MIN.
65
45
20
1
Ref/Active to Ref/Active Command Period
Active to Precharge Command Period
tRC
tRAS
tRCD
tCCD
tRP
nS
100000
Active to Read/Write Command Delay Time
Read/Write(a) to Read/Write(b)Command Period
Precharge to Active(b) Command Period
Active(a) to Active(b) Command Period
Cycle
20
14
8
tRRD
Write Recovery Time
CL* = 2
CL* = 3
CL* = 2
CL* = 3
tWR
tCK
7
CLK Cycle Time
8
1000
1000
7
CLK High Level
tCH
tCL
2
CLK Low Level
2
Access Time from CLK
CL* = 2
CL* = 3
6
tAC
5.5
Output Data Hold Time
Output Data High Impedance Time
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK (Rise and Fall)
Data-in-Set-up Time
tOH
tHZ
3
3
nS
7
tLZ
0
tSB
0
7
tT
0.5
1.5
1
10
tDS
Data-in Hold Time
tDH
Address Set-up Time
tAS
1.5
1
Address Hold Time
tAH
CKE Set-up Time
tCKS
tCKH
tCMS
tCMH
tREF
tRSC
1.5
1
CKE Hold Time
Command Set-up Time
Command Hold Time
1.5
1
Refresh Time
64
mS
nS
Mode Register Set Cycle Time
14
- 16 -
W9864G6DB
Notes:
1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the
devices.
2. All voltages are referenced to VSS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power up Sequence
(1) Power up must be performed in the following sequence.
(2) Power must be applied to VDD and VDDQ (simultaneously) while all input signals are held in the “NOP” state. The CLK
signals must be started at the same time.
(3) After power-up a pause of at least 200 µseconds is required. It is required that DQM and CKE signals then be held ‘
high‘ (VDD levels) to ensure that the DQ output is impedance.
(4) All banks must be precharged.
(5) The Mode Register Set command must be asserted to initialize the Mode Register.
(6) A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of the device.
6. AC Testing Conditions
PARAMETER
Output Reference Level
CONDITIONS
1.4V
Output Load
See diagram below
2.4V/0.4V
1 nS
Input Signal Levels (VIH/VIL)
Transition Time (Rise and Fall) of Input Signal
Input Reference Level
1.4V
1.4 V
50 ohms
50pF
output
Z = 50 ohms
AC TEST LOAD
1. Transition times are measured between VIH and VIL.
2. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
3. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as
follows the number of clock cycles = specified value of timing/ clock period
(count fractions as whole number)
(1) tCH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min.).
tCL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max.).
Publication Release Date: January 27, 2003
- 17 -
Revision A1
W9864G6DB
(2) A.C Latency Characteristics
CKE to Clock Disable (CKE Latency)
1
Cycle
DQM to Output to HI-Z (Read DQM Latency)
DQM to Output to HI-Z (Write DQM Latency)
Write Command to Input Data (Write Data Latency)
2
0
0
0
CS to Command Input ( CS Latency)
Precharge to DQ Hi-Z Lead Time
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
2
3
1
Precharge to Last Valid Data Out
2
2
3
Bust Stop Command to DQ Hi-Z Lead Time
Bust Stop Command to Last Valid Data Out
1
2
BL + tRP
BL + tRP
BL + tRP
BL + tRP
Cycle + nS
Read with Auto Precharge Command to Active/Ref
Command
Write with Auto Precharge Command to Active/Ref
Command
- 18 -
W9864G6DB
10. TIMING WAVEFORMS
Command Input Timing
t
CL
tCH
t
CK
V
V
IH
IL
CLK
CS
t
T
tT
t
t
CMS
CMS
tCMH
t
CMH
tCMS
t
CMH
RAS
CAS
WE
t
t
CMS
CMS
t
t
CMH
CMH
t
AS
tAH
A0-A10
BS0, 1
t
CKS
t
CKH
tCKH
t
CKS
t
CKS
t
CKH
CKE
Publication Release Date: January 27, 2003
Revision A1
- 19 -
W9864G6DB
Timing Waveforms, continued
Read Timing
Read CAS Latency
CLK
CS
RAS
CAS
WE
A0-A10
BS0, 1
t
AC
t
AC
t
HZ
t
OH
t
OH
t
LZ
Valid
Data-Out
Valid
Data-Out
DQ
Read Command
Burst Length
- 20 -
W9864G6DB
Timing Waveforms, continued
Control Timing of Input Data
(Word Mask)
CLK
t
CMS
t
CMH
t
CMH
tCMS
DQM0
DQM1
t
CMH
t
CMS
tCMH
tCMS
t
DS
t
DH
t
DS
DS
t
DH
t
DS
t
DH
t
t
t
DS
tDH
Valid
Valid
Valid
Valid
Data-in
Data-in
Data-in
DQ0 -DQ7
DQ8-DQ15
Data-in
t
t
t
DS
DS
DS
t
DH
t
t
t
DS
DS
DS
t
DH
t
t
DH
DS
DS
tDH
Valid
Data-in
Valid
Valid
Valid
Data-in
Data-in
Data-in
t
DH
t
DH
t
DS
t
DH
t
t
DS
tDH
t
DH
Valid
Data-in
Valid
Data-in
Valid
Valid
Valid
DQ16 -DQ23
DQ24-DQ31
Data-in
Data-in
Data-in
t
DH
t
DH
tDS
tDH
DS
t
DH
tDS
t
DH
Valid
Data-in
Valid
Data-in
Valid
Valid
Valid
Data-in
Data-in
Data-in
*DQM2,3="L"
(Clock Mask)
CLK
t
CKH
tCKS
t
CKH
tCKS
CKE
t
DS
DS
t
DH
t
DS
t
DH
t
t
DS
DS
t
DH
t
t
DS
DS
tDH
Valid
Valid
Data-in
Valid
Valid
DQ0 -DQ7
DQ8 -DQ15
DQ16 -DQ23
DQ24 -DQ31
Data-in
Data-in
Data-in
t
t
DH
t
t
t
DS
t
DH
tDH
t
DH
Valid
Valid
Valid
Valid
Data-in
Data-in
Data-in
Data-in
t
DS
DS
t
DH
DS
DS
t
DH
t
t
DS
DS
tDH
t
t
DS
DS
t
DH
Valid
Valid
Valid
Valid
Data-in
Data-in
Data-in
Data-in
t
t
DH
t
DH
tDH
t
DH
Valid
Valid
Valid
Valid
Data-in
Data-in
Data-in
Data-in
Publication Release Date: January 27, 2003
Revision A1
- 21 -
W9864G6DB
Timing Waveforms, continued
Control Timing of Output Data
(Output Enable)
CLK
t
CMH
t
CMS
t
CMH
t
t
CMS
CMS
DQM0
DQM1
t
CMS
t
CMH
tCMH
t
AC
t
AC
t
HZ
t
AC
t
t
AC
AC
t
t
OH
OH
t
OH
t
OH
t
LZ
tOH
OPEN
Valid
Data-Out
Valid
Data-Out
Valid
DQ0 -DQ7
DQ8 -DQ15
DQ16 -DQ23
DQ24 -DQ31
Data-Out
t
AC
t
AC
AC
AC
t
AC
tHZ
t
OH
t
OH
t
OH
tLZ
Valid
OPEN
Valid
Valid
Data-Out
Data-Out
Data-Out
t
AC
t
AC
AC
t
t
t
HZ
t
t
AC
AC
t
OH
t
OH
t
OH
t
LZ
tOH
Valid
Valid
Valid
Data-Out
Valid
Data-Out
Data-Out
Data-Out
t
t
HZ
tAC
t
OH
t
OH
t
OH
t
OH
t
OH
Valid
Valid
Valid
Data-Out
Valid
Data-Out
Data-Out
Data-Out
*DQM2,3="L"
(Clock Mask)
CLK
t
CKH
t
CKS
t
CKH
tCKS
CKE
t
AC
t
t
AC
AC
t
t
AC
AC
t
AC
t
OH
t
OH
t
OH
t
OH
Valid
Valid
Valid
DQ0 -DQ7
Data-Out
Data-Out
Data-Out
t
AC
t
AC
t
OH
OH
tOH
t
OH
tOH
Valid
Valid
Valid
DQ8 -DQ15
Data-Out
Data-Out
Data-Out
t
AC
t
t
AC
AC
t
AC
t
AC
t
t
OH
t
t
t
OH
tOH
Valid
Valid
Valid
Data-Out
DQ16 -DQ23
Data-Out
Data-Out
t
AC
t
AC
t
AC
OH
OH
t
OH
tOH
Valid
Data-Out
Valid
Valid
Data-Out
DQ24 -DQ31
Data-Out
- 22 -
W9864G6DB
Timing Waveforms, continued
Mode Register Set Cycle
t
RSC
CLK
t
CMS
tCMH
CS
t
CMS
tCMH
RAS
CAS
WE
t
CMS
tCMH
t
CMS
tCMH
t
AS
tAH
A0-A10
BS0,1
Register
set data
next
command
BurstLength
A0
A1
A2
A2 A1 A0
Sequential
Interleave
Burst Length
0
0
0
0
1
1
1
1
0
00
1
1
0
0
1
0
1
0
1
0
1
1
1
A20
4
A80
A2
4
A80
A3 Addressing Mode
A4
0
Reserved
Reserved
1
A10
A5
A6
CAS Latency
FullAP0age
A3
0
A10
Addressing Mode
Sequential
InteArle0ave
A7 "0" (Test Mode)
A8 "0"
A9
Reserved
A6 A5 A4
CAS Latency
Reserved
Reserved
2
0
0
0
0
1
0
A00
1
1
A00
0
1
0
1
0
WriteMode
"0"
"0"
A10
A11
3
Reserved
Reserved
BS0 "0"
BS1 "0"
A9
0
A10
Single Write Mode
Burst read and Burst write
Burst read aAn0d single write
Publication Release Date: January 27, 2003
Revision A1
- 23 -
W9864G6DB
11. OPERATING TIMING EXAMPLE
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
0
CLK
CS
t
RC
tRC
t
RC
tRC
RAS
CAS
WE
t
RAS
t
RP
t
RAS
RP
tRP
t
RAS
t
tRAS
BS0
BS1
t
RCD
t
RCD
t
RCD
t
RCD
RAa
RAa
RBb
RAc
RAc
RBd
RBd
A10
RAe
RAe
CAw
CBx
RBb
CAy
CBz
A0-A9
DQM
CKE
DQ
t
AC
t
AC
t
AC
t
AC
cy2
bx1
bx3
aw0
aw2 aw3
bx0
bx2
cy1
cy3
aw1
cy0
t
RRD
t
RRD
tRRD
t
RRD
Precharge
Read
Active
Read
Precharge
Active
Bank #0
Bank #1
Bank #2
Read
Active
Precharge
Read
Active
Active
Idle
Bank #3
- 24 -
W9864G6DB
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge)
(CLK = 100 MHz)
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
10
0
CLK
CS
t
RC
tRC
t
RC
t
RC
RAS
CAS
t
RAS
t
RP
t
RAS
RP
t
RP
RAS
t
RAS
t
t
WE
BS0
BS1
t
RCD
t
RCD
t
RCD
t
RCD
RAe
RBd
RAa
RBb
RAc
A10
A0-A9
DQM
CKE
CBz
RAa
CAw
CAy
RAe
CBx
RBb
RAc
RBd
t
AC
t
AC
t
AC
t
AC
cy3
aw0 aw1 aw2
aw3
bx0 bx1
bx2 bx3
cy0
cy1 cy2
dz0
DQ
t
RRD
t
RRD
t
RRD
tRRD
Read
Active
AP*
Read
Active
Active
Active
AP*
Bank #0
Bank #1
Bank #2
Bank #3
Read
Read
Active
AP*
Idle
* AP is the internal precharge start timing
Publication Release Date: January 27, 2003
Revision A1
- 25 -
W9864G6DB
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
(CLK = 100 MHz)
8
9
10 11 12 13 14 15 16 17 18
1
2
3
4
5
6
7
19 20 21 22 23
0
CLK
CS
t
RC
RAS
CAS
t
RAS
t
RP
tRAS
t
RP
t
RAS
WE
BS0
BS1
A10
t
RCD
t
RCD
tRCD
RAa
RAa
RAc
RAc
RBb
RBb
CAx
CBy
CAz
A0-A9
DQM
CKE
DQ
t
AC
t
AC
t
AC
ax0 ax1
ax2
ax3
ax4
ax5 ax6
by0
by1
by4 by5
by6
by7
CZ0
t
RRD
t
RRD
Read
Active
Idle
Precharge
Active
Read
Precharge
Bank #0
Bank #1
Active
Precharge
Read
Bank #2
Bank #3
- 26 -
W9864G6DB
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge)
(CLK = 100 MHz)
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
21 22 23
0
CLK
CS
t
RC
RAS
t
RAS
t
RP
t
RAS
CAS
WE
BS0
BS1
t
RCD
tRCD
t
RCD
A10
RBb
RBb
RAc
RAa
RAa
A0-A9
DQM
CAz
CAx
RAc
CBy
CKE
DQ
t
CAC
t
CAC
t
CAC
ax3
ax4
ax0
ax2
ax5 ax6
ax7
by0
by1
by4
by5
by6
ax1
CZ0
t
RRD
t
RRD
AP*
Read
Active
Bank #0 Active
Bank #1
Read
Active
Read
AP*
Bank #2
Idle
* AP is the internal precharge start timing
Bank #3
Publication Release Date: January 27, 2003
Revision A1
- 27 -
W9864G6DB
Operating Timing Example, continued
Interleaved Bank Write (Burst Length = 8)
(CLK = 100 MHz)
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
6
7
8
1
2
3
4
5
0
CLK
CS
t
RC
RAS
CAS
t
RAS
t
RP
t
RAS
t
RCD
t
RCD
tRCD
WE
BS0
BS1
RBb
RAc
RAc
RAa
RAa
A10
CAx
RBb
CBy
CAz
A0-A9
DQM
CKE
DQ
ax0 ax1
RRD
ax4
ax5
ax6
ax7
by0
by1
RRD
by2
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
t
t
Active
Write
Precharge
Active
Write
Bank #0
Bank #1
Active
Write
Precharge
Bank #2
Bank #3
Idle
- 28 -
W9864G6DB
Operating Timing Example, continued
Interleaved Bank Write (Burst Length = 8, Auto Precharge)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
RC
RAS
CAS
t
RP
t
RAS
t
RAS
WE
BS0
BS1
t
RCD
t
RCD
tRCD
RAa
RAa
RBb
RBb
RAb
RAc
A10
CAx
CBy
CAz
A0-A9
DQM
CKE
DQ
ax4
by2
by5
ax0 ax1
ax5
ax6
ax7
by0 by1
by3
by4
by6
by7 CZ0
CZ1
CZ2
t
RRD
t
RRD
AP*
Write
AP*
Active
Active
Write
Bank #0
Bank #1
Bank #2
Bank #3
Active
Write
Idle
* AP is the internal precharge start timing
Publication Release Date: January 27, 2003
Revision A1
- 29 -
W9864G6DB
Operating Timing Example, continued
Page Mode Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
t
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
CCD
t
CCD
tCCD
RAS
t
RAS
RAS
CAS
WE
BS0
BS1
t
RCD
tRCD
RAa
RAa
RBb
RBb
A10
A0-A9
DQM
CKE
CBx
CAy
CAm
CBz
CAI
t
AC
t
AC
t
AC
t
AC
tAC
am1
am2 bz0
bz1
bz2
bz3
a0
a1
a3
bx0
Ay0
Ay1 Ay2
am0
a2
bx1
DQ
t
RRD
Read
Bank #0 Active
Bank #1
Read
Read
Precharge
AP*
Active
Read
Read
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
- 30 -
W9864G6DB
Operating Timing Example, continued
Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)
(CLK = 100 MHz)
6
7
8
11
12
13
16
17
18
1
2
3
5
9
10
14
15
19
21
0
4
20
22
23
CLK
CS
t
RAS
RAS
CAS
WE
BS0
BS1
t
RCD
RAa
RAa
A10
CAx
A0-A9
CAy
DQM
CKE
tAC
t
WR
ax5
ay1
ax0
ax1
ax3
ay0
ay2
ay4
ax2
ax4
ay3
DQ
Q
Q
Q
Q
Q
Q
D
D
D
D
D
Bank #0
Bank #1
Bank #2
Bank #3
Active
Idle
Read
Write
Precharge
Publication Release Date: January 27, 2003
Revision A1
- 31 -
W9864G6DB
Operating Timing Example, continued
Auto Precharge Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
6
7
8
11
12
13
16
17
18
1
2
3
5
9
10
14
15
19
21
0
4
20
22
23
CLK
CS
t
RC
RAS
t
RAS
t
RP
tRAS
CAS
WE
BS0
BS1
A10
t
RCD
t
RCD
RAa
RAb
CAx
RAa
CAw
RAb
A0-A9
DQM
CKE
t
AC
t
AC
aw0 aw1 aw2 aw3
bx1
bx2
bx3
bx0
DQ
Bank #0
Bank #1
Bank #2
Bank #3
AP*
Active
Idle
Read
Active
Read
AP*
* AP is the internal precharge start timing
- 32 -
W9864G6DB
Operating Timing Example, continued
Auto Precharge Write (Burst Length = 4)
(CLK = 100 MHz)
6
7
8
11
12
13
16
17
18
1
2
3
5
9
10
14
15
19
21
0
4
20
22
23
CLK
CS
t
RC
t
RC
RAS
CAS
t
RAS
t
RP
t
RAS
tRP
WE
BS0
BS1
t
RCD
t
RCD
RAc
RAa
RAa
RAb
A10
A0-A9
DQM
CKE
CAw
RAb
CAx
RAc
aw0 aw1 aw2 aw3
bx0
bx1
bx3
bx2
DQ
Active
Idle
Bank #0
Bank #1
Bank #2
Bank #3
Write
Active
Write
Active
AP*
AP*
* AP is the internal precharge start timing
Publication Release Date: January 27, 2003
Revision A1
- 33 -
W9864G6DB
Operating Timing Example, continued
Auto Refresh Cycle
(CLK = 100 MHz)
11 12 13
6
7
8
16 17 18
1
2
3
5
9
10
14 15
19
21
0
4
20
22 23
CLK
CS
t
RP
t
RC
tRC
RAS
CAS
WE
BS0,1
A10
A0-A9
DQM
CKE
DQ
All Banks
Prechage
Auto
Auto Refresh (Arbitrary Cycle)
Refresh
- 34 -
W9864G6DB
Operating Timing Example, continued
Self Refresh Cycle
(CLK = 100 MHz)
6
7
8
11
12
13
16
17
18
1
2
3
5
9
10
14
15
19
21
0
4
20
22
23
CLK
CS
tRP
RAS
CAS
WE
BS0,1
A10
A0-A9
DQM
t
CKS
t
CKS
t
SB
CKE
DQ
t
CKS
t
RC
Self Refresh Cycle
No Operation Cycle
All Banks
Self Refresh
Entry
Arbitrary Cycle
Precharge
Publication Release Date: January 27, 2003
Revision A1
- 35 -
W9864G6DB
Operating Timing Example, continued
Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
6
7
8
11 12 13
16 17 18
1
2
3
5
9
10
14 15
19
21
0
4
20
22 23
CLK
CS
RAS
CAS
t
RCD
WE
BS0
BS1
A10
RBa
CBz
A0-A9
RBa
CBv
CBw
CBx CBy
DQM
CKE
t
AC
Q
t
AC
Q
DQ
av0
av1
av3
aw0
ax0
ay0
az1
az2
az3
az0
av2
Q
Q
Q
D
D
D
Q
Q
Q
Read
Active
Idle
Single Write
Read
Bank #0
Bank #1
Bank #2
Bank #3
- 36 -
W9864G6DB
Operating Timing Example, continued
Power Down Mode
(CLK = 100 MHz)
6
7
8
11
12
13
16
17
18
1
2
3
5
9
10
14
15
19
21
0
4
20
22
23
CLK
CS
RAS
CAS
WE
BS
RAa
RAa
RAa
RAa
A10
A0-A9
DQM
CAa
CAx
t
SB
tSB
CKE
DQ
t
CKS
tCKS
t
CKS
t
CKS
ax0
ax2
ax3
ax1
Active
NOP
Precharge
NOPActive
Read
Precharge Standby
Power Down mode
Active Standby
Power Down mode
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
Publication Release Date: January 27, 2003
Revision A1
- 37 -
W9864G6DB
Operating Timing Example, continued
Auto Precharge Timing (Write Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
(1) CAS
Latency=2
( a ) burst length = 1
Command
Write
D0
AP
Act
t
WR
t
RP
DQ
( b ) burst length = 2
Command
Write
D0
AP
Act
AP
tWR
tRP
DQ
( c ) burst length = 4
Command
D1
D1
Write
D0
Act
D6
tWR
t
RP
DQ
D2
D2
D3
D3
( d ) burst length = 8
Command
Write
D0
AP
Act
tWR
tRP
DQ
D1
AP
D4
D5
D7
(2) CAS
Latency=3
( a ) burst length = 1
Command
Write
D0
Act
t
WR
tRP
DQ
( b ) burst length = 2
Command
Write
D0
AP
Act
tWR
tRP
DQ
( c ) burst length = 4
Command
D1
D1
D1
Write
D0
AP
Act
D7
tWR
tRP
DQ
D2
D2
D3
D3
( d ) burst length = 8
Command
Write
D0
AP
Act
tWR
tRP
DQ
D5
D6
D4
Note:
Write
represents the Write with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
AP
Act
When the Auto precharge command is asserted, the period from Bank Activate
command to the start of internal precgarging must be at least tRAS (min.)
- 38 -
W9864G6DB
Operating Timing Example, continued
Auto Precharge Timing (Read Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
(1) CAS
Latency=2
( a ) burst length = 1
Command
Read
AP
Act
t
RP
DQ
Q0
( b ) burst length = 2
Command
Read
Read
Read
AP
Q0
Act
t
RP
DQ
Q1
( c ) burst length = 4
Command
AP
Q2
Act
Q4
t
RP
DQ
Q0
Q0
Q1
Q1
Q3
( d ) burst length = 8
Command
AP
Q6
Act
tRP
DQ
Q2
Act
Q3
Q5
Q7
(2) CAS
Latency=3
( a ) burst length = 1
Command
Read
Read
Read
Read
AP
t
RP
DQ
Q0
Q0
Q0
Q0
( b ) burst length = 2
Command
AP
Act
t
RP
DQ
Q1
AP
Q1
( c ) burst length = 4
Command
Act
Q4
tRP
DQ
Q2
Q2
Q3
Q3
( d ) burst length = 8
Command
AP
Q5
Act
t
RP
DQ
Q1
Q6
Q7
Note:
Read
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
AP
Act
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at leastRt AS (min).
Publication Release Date: January 27, 2003
Revision A1
- 39 -
W9864G6DB
Operating Timing Example, continued
Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
1
2
3
4
5
6
7
8
9
10
11
0
(1) CAS Latency=2
( a ) Command
Read
Write
DQM
DQ
D0
D1
D2
D3
( b ) Command
Read
Write
DQM
D0
D1
D2
D2
D3
D3
D3
DQ
(2) CAS Latency=3
( a ) Command
Read
Read
Write
D0
DQM
D1
DQ
( b ) Command
Write
DQM
DQ
D0
D1
D2
Note: The Output data must be masked by DQM to avoid I/O conflict.
- 40 -
W9864G6DB
Operating Timing Example, continued
Timing Chart of Write to Read Cycle
In the case of Burst Length = 4
1
2
3
4
5
6
7
8
9
10
11
0
(1) CAS Latency = 2
( a ) Command
DQM
Write
Read
DQ
D0
Q0
Q1
Q0
Q2
Q1
Q3
Q2
( b ) Command
DQM
Read
Write
DQ
D0
D1
Q3
(2) CAS Latency = 3
( a ) Command
Read
Write
DQM
DQ
D0
Q0
Q1
Q0
Q2
Q1
Q3
Q2
( b ) Command
DQM
Write
Read
D0
D1
Q3
DQ
Publication Release Date: January 27, 2003
Revision A1
- 41 -
W9864G6DB
Operating Timing Example, continued
Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10
11
(3) Read cycle
( a ) CAS latency =2
Read
BST
Command
DQ
Q4
Q3
Q0
Q1
Q0
Q2
Q1
Q3
BST
Q2
( b ) CAS latency = 3
Command
Read
DQ
Q4
(2) Write cycle
BST
Write
D0
Command
DQ
D1
D2
D3
D4
Note:
BST
represents the Burst stop command
- 42 -
W9864G6DB
Operating Timing Example, continued
Timing Chart of Burst Stop Cycle (Precharge Command)
In the case of Burst Lenght = 8
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
( a )CAS latency =2
Commad
Read
PRCG
DQ
Q4
Q3
Q0
Q1
Q0
Q2
Q1
Q3
( b )CAS latency = 3
Commad
PRCG
Read
Q4
DQ
Q2
(2) Write cycle
( a ) CAS latency =2
PRCG
Commad
Write
t
t
WR
DQM
DQ
D4
D4
D0
D1
D2
D3
D3
( b ) CAS latency = 3
PRCG
Commad
Write
WR
DQM
DQ
D0
D1
D2
PRCG
Note:
represents the Precharge command
Publication Release Date: January 27, 2003
Revision A1
- 43 -
W9864G6DB
Operating Timing Example, continued
CKE/DQM Input Timing (Write Cycle)
1
CLK cycle No.
2
3
4
5
7
6
External
CLK
Internal
CKE
DQM
DQ
D1
1
D2
2
D3
3
D5
5
D6
DQM MASK
CKE MASK
( 1 )
CLK cycle No.
External
4
7
6
CLK
Internal
CKE
DQM
DQ
D1
1
D2
2
D3
D6
7
D5
DQM MASK
( 2 )
CKE MASK
3
4
5
6
CLK cycle No.
External
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D4
D5
D6
CKE MASK
( 3 )
- 44 -
W9864G6DB
Operating Timing Example, continued
CKE/DQM Input Timing (Read Cycle)
1
CLK cycle No.
6
2
3
4
5
7
External
Internal
CLK
CKE
DQM
DQ
Q6
7
Q1
1
Q2
2
Q3
3
Q4
Open
Open
( 1 )
4
5
CLK cycle No.
6
External
Internal
CLK
CKE
DQM
DQ
Q6
7
Q3
Q1
1
Q2
2
Q4
Open
( 2 )
CLK cycle No.
3
4
5
6
External
CLK
Internal
CKE
DQM
DQ
Q6
Q1
Q4
Q5
Q3
Q2
( 3 )
Publication Release Date: January 27, 2003
Revision A1
- 45 -
W9864G6DB
Operating Timing Example, continued
Self Refresh/Power Down Mode Exit Timing
Asynchronous Control
Input Buffer turn on time (Power down mode exit time) is specified by Ct KS (min.) + tCK (min.)
A ) tCK < tCKS (min.) + tCK (min.)
t
CK
CLK
CKE
tCKS(min)+tCK(min)
Command
Command
NOP
Input Buffer Enable
B) tCK >= tCKS (min.) + tCK (min.)
t
CK
CLK
CKE
t
CKS(min)+tCK(min)
Command
Input Buffer Enable
Command
Note:
All Input Buffer (Include CLK Buffer) are turned off in the Power Down mode
and Self Refresh mode
NOP
Represents the No-Operation command
Represents one command
Command
- 46 -
W9864G6DB
12. PACKAGE DIMENSIONS
BGA 60 Balls Pitch = 0.65 mm
Publication Release Date: January 27, 2003
Revision A1
- 47 -
W9864G6DB
13. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
January 27, 2003
-
Formal Version
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
2727 North First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 886-3-5770066
FAX: 1-408-5441798
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 48 -
相关型号：
W9864G6IH-6I
Synchronous DRAM, 4MX16, 5ns, CMOS, PDSO54, 0.400 INCH, ROHS COMPLIANT, TSOP2-54
WINBOND
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