WM2613 [WOLFSON]
Byte-wide Parallel Input, 12-bit Voltage Output DAC; 字节宽并行输入， 12位电压输出DAC
| 型号： | WM2613 |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | Byte-wide Parallel Input, 12-bit Voltage Output DAC |
| 文件： | 总11页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM2613
Byte-wide Parallel Input, 12-bit Voltage Output DAC
Production Data, June 1999, Rev 1.0
FEATURES
DESCRIPTION
·
·
·
·
·
·
Dual 12-bit voltage output DAC
Dual supply 2.7V to 5.5V operation
DNL ±0.4 LSB, INL ±1.5 LSB
Programmable settling time 1ms or 3ms typical
8-bit micro controller compatible interface
Power down mode (10nA)
The WM2613 is a 12-bit voltage output, resistor string, digital-to-
analogue converter. The DAC can be powered down under
software or hardware control, reducing power consumption to
10nA.
The device has an 8-bit microcontroller compatible parallel
interface. The eight data LSBs, the four data MSBs, and the three
control bits are written using three different addresses.
APPLICATIONS
Excellent performance is delivered with a typical DNL of 0.4 LSBs.
The output stage is buffered by a x2 gain near rail-to-rail amplifier,
which features a Class A output stage (slow mode, class AB). The
settling time of the DAC is software programmable to allow the
designer to optimize speed versus power dissipation.
·
·
·
·
·
·
·
Battery powered test instruments
Digital offset and gain adjustment
Battery operated/remote industrial controls
Machine and motion control devices
Wireless telephone and communication systems
Speech synthesis
The device is available in a 20-pin TSSOP package. Commercial
temperature (0° to 70°C) and Industrial temperature (-40° to 85°C)
variants are supported.
Arbitrary waveform generation
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
WM2613CDT
WM2613IDT
0° to 70°C
20-pin TSSOP
20-pin TSSOP
-40° to 85°C
BLOCK DIAGRAM
TYPICAL PERFORMANCE
DVDD
(10)
AVDD
(11)
1
AVDD = DVDD = 5V, VREF
= 2.048V, Speed = Fast mode, Load = 10k/100pF
0.8
0.6
0.4
0.2
0
REFIN(12)
REFERENCE
INPUT BUFFER
SPD (9)
POWERDOWN/
SPEED
CONTROL
NPD (15)
X1
3-BIT
CONTROL
LATCH
DAC
OUTPUT
BUFFER
A[0-1] (8,7)
PARALLEL
INTERFACE
AND
CONTROL
LOGIC
4-BIT DAC
MSW
HOLDING
LATCH
-0.2
-0.4
-0.6
-0.8
-1
12-BIT DAC
LATCH
(13) OUT
X2
NCS (18)
NWE (17)
8-BIT DAC
LSW
HOLDING
LATCH
D[0-7]
(19,20, 1-6)
0
512
1024
1536
2048
2559
3071
3583
4095
POWER-ON
RESET
WM2613
DIGITAL CODE
(14)
GND
(16)
NLDAC
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
Production Data Datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics’ Terms and conditions.
Master rev 1.0.doc June 17, 1999 14:12
http://www.wolfson.co.uk
Ó1999 Wolfson Microelectronics Ltd.
WM2613
Production Data Rev 1.0
PIN CONFIGURATION
D2
D3
D4
D5
D6
1
2
3
4
5
20
19
18
17
16
D1
D0
NCS
NWE
NLDAC
D7
A1
A0
6
7
8
15
14
13
NPD
GND
OUT
REFIN
SPD
9
12
11
DVDD
10
AVDD
PIN DESCRIPTION
PIN NO
NAME
D2
TYPE
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Supply
DESCRIPTION
Data input.
Data input.
Data input.
Data input.
Data input.
Data input.
1
2
D3
D4
3
D5
4
D6
5
D7
6
A1
Address input.
7
A0
Address input.
8
SPD
DVDD
AVDD
REFIN
OUT
GND
NPD
Speed select. Digital input.
Digital positive power supply.
9
10
11
12
13
14
15
Supply
Analogue positive power supply.
Voltage reference input.
DAC analogue voltage output.
Ground.
Analogue input
Analogue output
Supply
Digital input
Power down. Active low digital input which powers down all analogue
circuits.
NLDAC
Digital input
Load DAC. Digital input active low. NLDAC must be taken low to update
the DAC latch from the holding latches.
16
NWE
NCS
D0
Digital input
Digital input
Digital input
Digital input
Write enable. Digital input active low.
Chip select. Digital input active low.
Data input.
17
18
19
20
D1
Data input.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
2
Production Data
WM2613
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or
beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this
device.
CONDITION
MIN
MAX
7V
Supply voltages, AVDD or DVDD to GND
Supply voltage differences, AVDD to DVDD
Reference input voltage
-2.8V
-0.3V
-0.3V
2.8V
DVDD + 0.3V
AVDD + 0.3V
Digital input voltage range to GND
Operating temperature range, TA
WM2613C
WM2613I
0°C
70°C
85°C
-40°C
-65°C
Storage temperature
150°C
Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds
260°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage
AVDD, DVDD
2.7
2
5.5
V
V
V
V
High-level digital input voltage
Low-level digital input voltage
Reference voltage to REFIN
VIH
VIL
DVDD = 2.7V to 5.5V
DVDD = 2.7V to 5.5V
See Note
0.8
VREF
AVDD - 1.5
Load resistance
RL
CL
TA
2
kW
pF
°C
°C
Load capacitance
100
70
Operating free-air temperature
WM2613CDT
WM2613IDT
0
-40
85
Note: Reference voltages greater than AVDD/2 will cause saturation for large DAC codes.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
3
WM2613
Production Data Rev 1.0
ELECTRICAL CHARACTERISTICS
Test Conditions:
RL = 10kW, CL = 100pF. AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over
recommended operating free-air temperature range (unless noted otherwise)
TEST
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
CONDITIONS
Static DAC Specifications
Resolution
12
bits
LSB
Integral non-linearity
Differential non-linearity
Zero code error
INL
DNL
See Note 1
See Note 2
See Note 3
See Note 4
See Note 5
See Note 6
±1.5
±0.4
3
±4
±1
LSB
ZCE
mV
±20
±0.5
Gain error
GE
% FSR
mV/V
ppm/°C
±0.25
0.5
D.c power supply rejection ratio
d.c. PSRR
Zero code error temperature
coefficient
3
Gain error temperature coefficient
DAC Output Specifications
Output voltage range
See Note 6
1
ppm/°C
0
AVDD - 0.4
0.3
V
Output load regulation
Power Supplies
2kW to 10kW load. See Note 7
0.1
%
Active supply current
IDD
No load, VIH = DVDD, VIL = 0V
AVDD = DVDD = 5V,
VREF = 2.048V See Note 8
Slow
0.5
1.6
1.3
3.0
mA
mA
Fast
AVDD = DVDD = 3V,
VREF = 1.024V
Slow
Fast
0.4
1.4
1.1
2.7
10
mA
mA
mA
Power down supply current
No load, all digital inputs 0V
or DVDD. See Note 9
0.01
Dynamic DAC Specifications
Slew rate
DAC code 128 to 4095,
10%-90% See Note 10
Slow
Fast
1.5
8
V/ms
V/ms
Settling time
DAC code 128 to 4095
Slow
3.5
1.0
1
ms
ms
Fast
Glitch energy
Code 2047 to code 2048
nV-s
Signal to noise ratio
SNR
SNRD
THD
fS = 480ksps,
fOUT = 1kHz BW = 20kHz,
TA = 25°C See Note 12
65
58
78
dB
dB
dB
dB
Signal to noise and distortion ratio
Total harmonic distortion
fS = 480ksps,
fOUT = 1kHz BW = 20kHz,
TA = 25°C See Note 12
69
fS = 480ksps,
fOUT = 1kHz BW = 20kHz,
TA = 25°C See Note 12
-68
72
-60
Spurious free dynamic range
SPFDR
fS = 480ksps,
fOUT = 1kHz BW = 20kHz, TA =
25°C See Note 12
60
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
4
Production Data
WM2613
Test Conditions:
RL = 10kW, CL = 100pF. AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over
recommended operating free-air temperature range (unless noted otherwise)
TEST
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
CONDITIONS
Reference
Reference input resistance
Reference input capacitance
Reference feedthrough
RREFIN
CREFIN
10
5
MW
pF
VREF = 1VPP at 1kHz
-60
dB
+ 1.024V d.c., DAC code 0
Reference input bandwidth
VREF = 0.2VPP + 1.024V d.c.
DAC code 2048
Slow
1
MHz
MHz
Fast
1.6
Digital Inputs
High level input current
Low level input current
Input capacitance
IIH
IIL
CI
Input voltage = DVDD
Input voltage = 0V
1
mA
mA
pF
-1
8
Notes:
1.
Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding the
effects of zero code and full scale errors).
2.
Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change
of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same
direction (or remains constant) as a change in digital input code.
3.
4.
5.
Zero code error is the voltage output when the DAC input code is zero.
Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.
Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the
proportion of this signal imposed on the zero code error and the gain error.
6.
7.
Zero code error and Gain error temperature coefficients are normalised to full scale voltage.
Output load regulation is the difference between the output voltage at full scale with a 10kW load and 2kW
load. It is expressed as a percentage of the full scale output voltage with a 10kW load.
8.
IDD is measured while continuously writing code 2048 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V supply current
will increase.
9.
Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.
10. Slew rate results are for the lower value of the rising and falling edge slew rates.
11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and
falling edges. Limits are ensured by design and characterisation, but are not production tested
12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with
a sampling frequency fS.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
5
WM2613
Production Data Rev 1.0
SERIAL INTERFACE
tSUD
tHD
X
Data
X
D[0-7]
A[0-1]
NCS
tSUA
tHA
X
Address
X
tSUCSWE
tWWE
NWE
tSUWELD
tWLD
NLDAC
Figure 1 Timing Diagram
SYMBOL
TEST CONDITIONS
MIN
TYP
13
MAX
UNIT
ns
tSUCSWE
tSUDWE
tHD
Setup time NCS low before positive NWE edge
Data ready before positive NWE edge
Data hold after positive NWE edge
Setup time for address bits A0, A1
Address hold after positive NWE edge
Positive NWE edge before NLDAC low
High pulse width of NWE
9
0
ns
ns
tSUA
17
0
ns
tHA
tSUWELD
tWWE
tWLD
0
ns
ns
ns
10
10
Low pulse width of NLDAC
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
6
Production Data
WM2613
TYPICAL PERFORMANCE GRAPHS
3
AVDD
=
DVDD
=
5V, V REF
=
2.048V, Speed
=
Fast mode, Load
=
10k/100pF
2
1
0
-1
-2
-3
0
512
1024
1536
2048
2559
3071
3583
4095
DIGITAL CODE
Figure 2 Integral Non-Linearity
3
5
4.5
4
AVDD = DVDD = 5V, VREF = 2V, Input Code = 0
AVDD = DVDD =3V, VREF = 1V, Input Code = 0
2.5
2
3.5
3
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Slow
Fast
ISINK - mA
ISINK - mA
Slow
Fast
Figure 3 Sink Current AVDD = DVDD = 3V
Figure 4 Sink Current AVDD = DVDD = 5V
2.065
4.105
AVDD = DVDD = 5V, VREF = 2V, Input Code = 4095
AVDD = DVDD = 3V, VREF = 1V, Input Code = 4095
2.06
2.055
2.05
4.1
4.095
4.09
2.045
2.04
4.085
4.08
2.035
2.03
4.075
4.07
2.025
4.065
0
1
2
3
4
5
6
7
8
9
10
Fast
0
1
2
3
4
5
6
7
8
9
10
Slow
ISOURCE - mA
ISOURCE - mA
Slow
Fast
Figure 5 Source Current AVDD = DVDD = 3V
WOLFSON MICROELECTRONICS LTD
Figure 6 Source Current AVDD = DVDD = 5V
Production Data Rev 1.0 June 1999
7
WM2613
Production Data Rev 1.0
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to
analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input
voltage and the input code according to the following relationship:
CODE
Output voltage =
(
REF
)
4096
2 V
INPUT
OUTPUT
4095
1111
1111
1111
2
2
(
V
REF
)
4096
:
:
2049
4096
1000
1000
0111
0000
0001
0000
1111
(V
REF
)
2048
4096
0000
1111
(
REF
2 V
)
=
REf
V
2047
4096
2
(V
REF
)
:
:
1
0000
0000
0000
0001
0000
2
(V
REF
)
4096
0000
0V
Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kW
load with a 100pF load capacitance.
EXTERNAL REFERENCE
The reference voltage input is buffered which makes the DAC input resistance independent of code. The
REFIN pin has an input resistance of 10MW and an input capacitance of typically 5pF. The reference
voltage determines the DAC full-scale output.
HARDWARE CONFIGURATION OPTIONS
The device has three configuration options that are controlled by device pins.
DEVICE POWER DOWN
The device can be powered-down by pulling pin NPD (pin 15) low. This powers down the DAC. This will
reduce power consumption significantly. The NPD pin overrides the software control bit PWR. When the
power down function is released the device reverts to the DAC code set prior to power down.
SETTLING TIME
The settling time of the device can be controlled by pin SPD (pin 9). A ONE on pin SPD will ensure a
FAST settling time; a ZERO will ensure a SLOW settling time. The SPD pin high overrides the software
control bit SPD.
SIMULTANEOUS DAC UPDATE
The NLDAC pin (Pin 16) can be held high to prevent word writes from updating the DAC latch. By writing
the new value to the DAC then pulling NLDAC low, the new DAC code is loaded into the DAC latch.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
8
Production Data
WM2613
PARALLEL INTERFACE
The device latches data on the positive edge of NWE. It must be enabled with NCS low. Whether the
data is written to one of the DAC holding latches (MSW, LSW) or the control register, depends on the
address bits A1 and A0. NLDAC low updates the DAC with the value in the holding latch, see Figure 7.
NLDAC is an asynchronous input and can be held low, if a synchronous update is not necessary.
Alternatively, the RLDAC bit of the control register can be used to synchonously update the DAC latch via
software control, see Figure 8.
X
MSW
0
X
LSW
1
X
X
D[0-7]
A[0-1]
NCS
X
NWE
NLDAC
Figure 7 Example of a Complete Write Cycle Using NLDAC to Update the DAC
X
MSW
0
X
LSW
1
X
Control
3
X
X
D[0-7]
A[0-1]
NCS
X
X
X
NWE
NLDAC
Figure 8 Example of a Complete Write Cycle Using the Control Word to Update the DAC. If NLDAC is held low as shown
in Figure 8, latch will be transparent. This assumes that the RLDAC control register bit is low at the start and is written high on
the final write.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
9
WM2613
Production Data Rev 1.0
SOFTWARE CONFIGURATION OPTIONS
DATA FORMAT
The WM2613 writes data either to one of the DAC holding latches or to the control register depending on
the address bits A1 and A0.
A1
A0
REGISTER
DAC LSW holding
DAC MSW holding
Reserved
0
0
1
1
0
1
0
1
Control
D7
X
D6
D5
X
D4
X
D3
X
D2
D1
D0
X
RLDAC
PWR
SPD
Table 2 Register Map
PROGRAMMABLE SETTLING TIME
Settling time is a software selectable 3.5ms or 1ms, typical to within ±0.5LSB of final value. This is
controlled by the value of SPD – Bit D12. A ONE defines a settling time of 1ms, a ZERO defines a settling
time of 3.5ms.
PIN
SPD
0
BIT
SPD
0
MODE
Slow
Fast
Fast
Fast
0
1
1
0
1
1
Table 3 Programmable Settling Time
PROGRAMMABLE POWER DOWN
The power down function can be controlled by PWR. A ZERO configures the device as active, or fully
powered up, a ONE configures the device into power down mode. When the power down function is
released the device reverts to the DAC code set prior to power down.
PIN
NPD
0
BIT
POWER
PWR
0
1
0
1
Down
Down
Normal
Down
0
1
1
Table 4 Programmable Power Down
LOAD DAC LATCH
Bit RLDAC controls the function of the DAC latch. A ONE configures the DAC latch as transparent. A
ZERO configures the DAC latch to be controlled by pin NLDAC.
PIN
BIT
LATCH
NLDAC
RLDAC
0
0
1
1
0
1
0
1
Transparent
Transparent
Hold
Transparent
Table 5 Load DAC Latch
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
10
Production Data
WM2613
PACKAGE DIMENSIONS
DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm)
DM008.C
b
e
20
11
E1
E
GAUGE
PLANE
q
1
10
D
0.25
c
L
A1
A
A2
-C-
0.05 C
SEATING PLANE
Dimensions
(mm)
NOM
-----
Symbols
MIN
-----
MAX
1.20
0.15
1.05
0.30
0.20
6.60
A
A1
A2
b
c
D
e
E
E1
L
0.05
0.80
0.19
0.09
6.40
-----
1.00
-----
-----
6.50
0.65 BSC
6.4 BSC
4.40
4.30
0.45
0o
4.50
0.75
8o
0.60
-----
q
REF:
JEDEC.95, MO-153
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
11
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