WM2637 [WOLFSON]
Dual 10-Bit Serial Input Voltage Output DAC with Internal Reference; 双路10位串行输入电压输出DAC ，内置基准
| 型号： | WM2637 |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | Dual 10-Bit Serial Input Voltage Output DAC with Internal Reference |
| 文件： | 总11页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM2637
Dual 10-Bit Serial Input Voltage Output DAC
with Internal Reference
Production Data, Rev 1.0, July 1999
FEATURES
DESCRIPTION
·
·
·
·
·
Dual 10-bit voltage output DAC
Single 2.7V to 5.5V supply
DNL ±0.1 LSBs, INL ±0.4 LSBs
Internal programmable voltage reference
Low power consumption:
The WM2637 is a dual 10-bit voltage output, resistor string, digital-
to-analogue converter. A software controlled power down mode is
provided that reduces current consumption to 10nA.
The WM2637 features an internal programmable voltage reference
simplifying overall system design. A reference voltage may also be
supplied externally.
·
·
5.5 mW, slow mode - 5V supply
3.3 mW, slow mode - 3V supply
·
TMS320, (Q) SPITM, and MicrowireTM compatible serial
interface
The device has been designed to interface efficiently to industry
standard microprocessors and DSPs, including the TMS320
family. The WM2637 is programmed with a 16-bit serial word
comprising of a latch address, mode DAC control bits and DAC or
control data.
·
·
Programmable settling time of 1ms or 3.5ms typical
Power down mode 10nA
APPLICATIONS
Excellent performance is delivered with a typical DNL of 0.1 LSBs.
The programmable settling time allows the designer to optimize
speed versus power consumption. The output stage is buffered by
a x2 gain near rail-to-rail amplifier.
·
·
·
·
·
·
·
Battery powered test instruments
Digital offset and gain adjustment
Battery operated/remote industrial controls
Machine and motion control devices
Wireless telephone and communication systems
Speech synthesis
The device is available in an 8-pin SOIC package ideal for space-
critical applications. Commercial temperature (0° to 70°C) and
industrial temperature (-40° to 85 °C) variants are supported.
Arbitrary waveform generation
ORDERING INFORMATION
DEVICE
WM2637CD
WM2637ID
TEMP. RANGE
0° to 70°C
PACKAGE
8-pin SOIC
8-pin SOIC
-40° to 85°C
BLOCK DIAGRAM
TYPICAL PERFORMANCE
VDD
(8)
0.2
c
5V = VDD, VREF = External, Speed = Slow mode, Load = 10k/100pF
REFERENCE
OUTPUT BUFFER
WITH OUPUT
ENABLE
0.15
0.1
1.024V/2.048V
SELECTABLE
REFERENCE
REF(6)
X1
0.05
0
2-BIT
REFERENCE
SELECT
LATCH
REFERENCE
INPUT
BUFFER
X1
DAC
OUTPUT
BUFFER
DIN (1)
10-BIT
DAC A
LATCH
-0.05
-0.1
-0.15
-0.2
(4) OUTA
X2
16-BIT
SHIFT
REGISTER
AND
CONTROL
LOGIC
REFERENCE
INPUT BUFFER
SCLK (2)
NCS (3)
X1
DAC
OUTPUT
BUFFER
10-BIT
DAC B
HOLDING
(7) OUTB
10-BIT
DAC B
LATCH
X2
LATCH
0
256
512
767
1023
DIGITAL CODE
POWERDOWN/
SPEED
CONTROL
2-BIT
CONTROL
LATCH
POWER-ON
RESET
WM2637
(5)
AGND
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Production Data contains final specifications
current on publication date. Supply of products
conforms to Wolfson Microelectronics' Terms
and Conditions.
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk
Last printed 15/07/99 15:56
Ó1999 Wolfson Microelectronics Ltd.
WM2637
Production Data
PIN CONFIGURATION
VDD
DIN
SCLK
NCS
1
2
3
4
8
7
6
5
OUT B
REF
AGND
OUT A
PIN DESCRIPTION
PIN NO
NAME
DIN
TYPE
DESCRIPTION
Serial data input.
Serial clock input.
1
2
3
4
5
6
7
8
Digital input
Digital input
Digital input
Analogue output
Supply
SCLK
NCS
Chip select. This pin is active low.
DAC A analogue output.
Analogue ground.
OUTA
AGND
REF
Reference voltage input/output.
DAC B analogue output
Positive power supply.
Analogue I/O
Analogue output
Supply
OUTB
VDD
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or
beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this
device.
CONDITION
MIN
MAX
7V
Supply voltage, VDD to AGND
Digital input voltage
-0.3V
-0.3V
VDD + 0.3V
VDD + 0.3V
Reference input voltage
Operating temperature range, TA
WM2637CD
WM2637ID
0°C
-40°C
-65°C
70°C
85°C
Storage temperature
150°C
260°C
Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage
VDD
VIH
2.7
2
5.5
V
V
High-level digital input voltage
Low-level digital input voltage
Reference voltage to REF
Load resistance
VDD = 5V
VDD = 5V
VIL
0.8
V
VREF
RL
VDD - 1.5
V
2
kW
Load capacitance
CL
100
20
Serial Clock Rate
FSCLK
TA
Operating free-air temperature
WM2637CD
WM2637ID
0
70
°C
°C
-40
85
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
2
WM2637
Production Data
Note: Reference voltages greater than VDD/2 will cause saturation for large DAC codes.
ELECTRICAL CHARACTERISTICS
Test Conditions:
RL = 10kW, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air
temperature range (unless noted otherwise)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static DAC Specifications
Resolution
10
bits
LSB
Integral non-linearity
INL
DNL
See Note 1
See Note 2
See Note 3
See Note 4
See Note 5
See Note 6
See Note 6
±0.4
±0.1
±1.0
±0.5
±24
Differential non-linearity
Zero code error
LSB
ZCE
mV
Gain error
GE
% FSR
mV/V
ppm/°C
ppm/°C
±0.6
D.c. power supply rejection ratio
Zero code error temperature coefficient
Gain error temperature coefficient
DAC Output Specifications
Output voltage range
DC PSRR
0.5
10
10
0
VDD - 0.1
V
Output load regulation
2kW to 10kW load
%
±0.1
±0.25
See Note 7
Power Supplies
Active supply current
IDD
No load, VIH = VDD, VIL = 0V
VDD = 5V, VREF = 2.048V, Internal
Slow
2.0
4.2
2.5
5.0
mA
mA
Fast
VDD = 5V, VREF = 2.048V, External
Slow
1.7
3.8
2.1
4.6
mA
mA
Fast
VDD = 3V, VREF = 1.024V, Internal
Slow
1.7
3.7
2.2
4.6
mA
mA
Fast
VDD = 3V, VREF = 1.024V, External
Slow
Fast
1.4
3.4
1.8
4.2
mA
mA
See Note 8
Power down supply current
No load,
all digital inputs 0V or VDD
See Note 9
0.01
10
mA
Dynamic DAC Specifications
Slew rate
DAC code 32 to 1023, 10%-90%
Slow
Fast
1.5
8.0
V/ms
V/ms
See Note 10
DAC code 32 to 1023
Slow
Settling time
3.5
1.0
ms
ms
Fast
See Note 11
Code 511 to 512
Glitch energy
10
56
nV-s
dB
Signal to noise ratio
SNR
fs = 400ksps, fOUT = 1kHz,
BW = 20kHz
53
50
See Note 12
Signal to noise and distortion ratio
SNRD
fs = 400ksps, fOUT = 1kHz,
BW = 20kHz
54
dB
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
3
WM2637
Production Data
Test Conditions:
RL = 10kW, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air
temperature range (unless noted otherwise)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See Note 12
Total harmonic distortion
THD
fs = 400ksps, fOUT = 1kHz,
BW = 20kHz
-61
62
-50
dB
dB
See Note 12
Spurious free dynamic range
SPFDR
fs = 400ksps, fOUT = 1kHz,
BW = 20kHz
51
See Note 12
Reference Configured As Input
Reference input resistance
Reference input capacitance
Reference feedthrough
RREFIN
CREFIN
10
55
MW
pF
VREF = 1VPP at 1kHz
-60
dB
+ 1.024V dc, DAC code 0
Reference input bandwidth
VREF = 0.2VPP + 1.024V dc
DAC code 1024
Slow
1.0
1.0
MHz
MHz
Fast
Reference Configured As Output
Low reference voltage
High reference voltage
Output source current
Output sink current
Load Capacitance
VREFOUTL
VREFOUTH
IREFSRC
1.003 1.024
2.027 2.048
1.045
2.069
1
V
VDD > 4.75V
V
mA
mA
pF
dB
IREFSNK
-1
100
PSRR
-48
Digital Inputs
High level input current
Low level input current
Input capacitance
IIH
IIL
CI
Input voltage = VDD
Input voltage = 0V
1
mA
mA
pF
-1
8
Notes:
1.
Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the
effects of zero code and full scale errors).
2.
Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two
codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change
in digital input code.
3.
4.
5.
Zero code error is the voltage output when the DAC input code is zero.
Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.
Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal
imposed on the zero code error and the gain error.
6.
7.
Zero code error and Gain error temperature coefficients are normalised to full scale voltage.
Output load regulation is the difference between the output voltage at full scale with a 10kW load and 2kW load. It is
expressed as a percentage of the full scale output voltage with a 10kW load.
8.
9.
IDD is measured while continuously writing code 1512 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will
increase.
Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.
10. Slew rate results are for the lower value of the rising and falling edge slew rates
11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling
edges. Limits are ensured by design and characterisation, but are not production tested.
12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with a sampling
frequency fs.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
4
WM2637
Production Data
SERIAL INTERFACE
tSUCSS
tDCS1
NCS
SCLK
DIN
tSUCS1
tSUCS2
tWCL
tWCH
tSUDCLK
tHDCLK
D15
D14
D13
D12
D11
D0
Figure 1 Timing Diagram
Test Conditions:
RL = 10kW, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating free-
air temperature range (unless noted otherwise)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Setup time NCS low before SCLK low
tSUCSS
10
ns
Setup time, rising edge of SCLK to rising edge of NCS,
external end of write
tSUCS1
tSUCS2
10
ns
Setup time, rising edge of SCLK to falling edge of NCS,
start of next write cycle
5
ns
ns
ns
ns
ns
Pulse duration, SCLK high
tWCL
tWCH
tSUDCLK
tHDCLK
25
25
10
5
Pulse duration, SCLK low
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
5
WM2637
Production Data
TYPICAL PERFORMANCE GRAPHS
1
5V = VDD, VREF = External, 2.048V, Speed = Fast mode, Load = 10k/100pF
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
256
512
767
1023
Digital Code
Figure 2 Integral Non-Linearity
0.4
0.4
0.35
0.3
VDD = 3V, VREF = 1V, Input Code = 0
VDD = 5V, VREF = 2V, Input Code = 0
0.35
0.3
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0
0.05
0
0
1
2
3
4
5
6
7
8
9
10
Fast
0
1
2
3
4
5
6
7
8
9
10
ISINK - mA
ISINK- mA
Slow
Slow
Fast
Figure 3 Sink Current VDD = 3V
Figure 4 Sink Current VDD = 5V
2.06
4.1
VDD = 3V, VREF = 1V, Input Code = 4095
VDD = 5V, VREF = 2V, Input Code = 4095
2.055
2.05
4.095
4.09
2.045
2.04
4.085
4.08
2.035
2.03
4.075
4.07
2.025
2.02
4.065
4.06
0
1
2
3
4
5
6
7
8
9
10
11
Fast
0
1
2
3
4
5
6
7
8
9
10
Slow
11
Fast
ISOURCE- mA
ISOURCE - mA
Slow
Figure 5 Source Current VDD = 3V
Figure 6 Source Current VDD = 5V
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
6
WM2637
Production Data
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 10-bit digital data to
analogue voltage levels (see Block Diagram). The output voltage is determined by the reference
input voltage and the input code according to the following relationship:
code
Output voltage = 2
1111
(
VREF
)
1024
OUTPUT
INPUT
11
1111
1023
1024
2
(
VREF
)
:
:
513
1024
10
10
0000
0001
0000
(
)
REF
2V
0000
1111
512
2
(
VREF
)
= VREF
1024
01
1111
511
2
2
(
(
VREF
)
1024
:
:
00
0000
0001
0000
1
VREF
)
1024
0000
0000
0V
Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a
2kW load with a 100pF load capacitance.
SERIAL INTERFACE
When chip select (NCS) is low, the input data is read into a 16-bit shift register with the input data
clocked in most significant bit first. The falling edge of the SCLK input shifts the data into the input
register. After 16 bits have been transferred, the next rising edge on SCLK or NCS then transfers
the data to the DAC latch. When NCS is high, input data cannot be clocked into the input register
(see Table 2).
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is:
1
fSCLKmax =
= 20MHz
tWCH min+ tWCL min
The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC
settling time to 10 bits limits the update rate for large input step transitions.
SOFTWARE CONFIGURATION OPTIONS
The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D2 contains the 10-bit data
word. D15-D12 hold the programmable options which are summarized Table 3
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
x
D0
x
R1 SPD PWD R0
New DAC value or control register value
Table 2 Serial Word Format
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
7
WM2637
Production Data
PROGRAMMABLE SETTLING TIME
Settling time is a software selectable 1ms or 3.5ms typical, to within ±0.5LSB of final value. This is
controlled by the value of D14. A ONE defines a settling time of 1ms, a ZERO defines a settling time
of 3.5ms.
PROGRAMMABLE POWER DOWN
The power down function is controlled by D13. A ZERO configures the device as active, or fully
powered up, a ONE configures the device into power down mode. When the power down function is
released the device reverts back to the DAC code set prior to power down.
REGISTER ADDRESSING
A separate internal control register is available. This is accessed from the register access bits R1
(Bit D15) and R0 (Bit D12).
R1
R0
REGISTER
(BIT D15)
(BIT D12)
Write data to DAC B and BUFFER
0
0
1
1
0
1
0
1
Write data to BUFFER
Write data to DAC A and update DAC B with BUFFER content
Write data to control register
Table 3 Programmable Options
The contents of the control register, shown below in Table 4, are used to program the internal
reference function
D11 D10 D9
D8
x
D7
x
D6
x
D5
x
D4
x
D3
x
D2
X
D1
D0
x
x
x
REF1 REF0
Table 4 Control Register Contents
PROGRAMMABLE INTERNAL REFERENCE
The reference can be sourced internally or externally under software control. If an external reference
voltage is applied to the REF pin, the device must be configured to accept this.
If an external reference is selected, the reference voltage input is buffered which makes the DAC
input resistance independent of code. The REF pin has an input resistance of 10MW and an input
capacitance of typically 55pF. The reference voltage determines the DAC full-scale output.
If an internal reference is selected, a voltage of 1.024V or 2.048V is available. The internal
reference can source up to 1mA and can therefore be used as an external system reference.
REF1
REF0
REGISTER
(BIT D1)
(BIT D0)
0
0
1
1
0
1
0
1
External
1.024V
2.048V
External
Table 5 Internal Reference Options
Examples:
1. Set internal reference voltage to 2.048V
D15 D14 D13 D12 D11 D10 D9
D8
D7
x
D6
D5
x
D4
x
D3
x
D2
x
D1
1
D0
0
1
x
0
1
x
x
x
x
x
2. Write new DAC A value and update DAC A output
D15 D14 D13 D12 D11 D10 D9 D8 D7
D6
D5
D4
D3
D2
D1
x
D0
x
0
x
0
0
New DAC A output value
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
8
WM2637
Production Data
FUNCTION OF THE LATCH CONTROL BITS (D15 AND D12)
PURPOSE AND USE OF THE DOUBLE BUFFER
Normally only one DAC output can change after a write. The double buffer allows both DAC outputs
to change after a single write. This is achieved by the two following steps.
1. A double buffer only write is executed to store the new DAC B data without changing the DAC A and B
outputs.
2. Following the previous step, a write to latch A is executed. This writes the serial interface register (SIR)
data to latch A and also writes the double buffer contents to latch B. Thus both DACs receive their new
data at the same time and so both DAC outputs begin to change at the same time.
Unless a double buffer only write is issued, the latch B and double buffer contents are identical.
Thus, following a write to latch A or B with another write to latch A does not change the latch B
contents.
Three data transfer options are possible. All transfers occur immediately after NCS goes high (or on
the sixteenth positive SCLK edge, whichever is earlier) and are described in the following sections).
LATCH A WRITE, LATCH B UPDATE (D15 = HIGH, D12 = LOW)
The serial interface register (SIR) data are written to latch A and the double buffer latch contents
are written to latch B. The double buffer contents are unaffected. This program bit condition allows
simultaneous output updates of both DACs.
LATCH A
LATCH B
TO DAC A
TO DAC B
SERIAL
INTERFACE
REGISTER
DOUBLE
BUFFER LATCH
D12 = LOW
D15 = HIGH
Figure 7 Latch A Write, Latch B Update
LATCH B AND DOUBLE BUFFER 1 WRITE (D15 = LOW, D12 = LOW)
The SIR data are written to both latch B and the double buffer. Latch A is unaffected.
LATCH A
LATCH B
TO DAC A
TO DAC B
SERIAL
INTERFACE
REGISTER
DOUBLE
BUFFER LATCH
D12 = LOW
D15 = LOW
Figure 8 Latch B and Double Buffer Write
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
9
WM2637
Production Data
DOUBLE BUFFER ONLY WRITE (D15 = LOW, D12 = HIGH)
The SIR data are written to the double buffer only. Latch A and B contents are unaffected.
LATCH A
LATCH B
TO DAC A
TO DAC B
SERIAL
INTERFACE
REGISTER
DOUBLE
BUFFER
D12 = HIGH
D15 = LOW
Figure 9 Double Buffer Only Write
OPERATIONAL EXAMPLES
1. changing the latch A data from zero to full code
Assuming that latch A starts at zero code (e.g. after power up), the latch can be filled with 1s by
writing (bit D15 on the left, D0 on the right)
1X00 1111 1111 11xx
to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode.
The latch B contents and DAC B output are not changed by this write unless the double buffer
contents are different from the latch B contents. This can only be true if the last write was a double
buffer-only write.
2. changing the latch B data from zero to full code
Assuming that latch B starts at zero code (e.g. after power up), the latch can be filled with 1s by
writing (bit D15 on the left, D0 on the right)
0X00 1111 1111 11xx
to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The data
(bits D2 to D11) are written to both the double buffer and latch B.
The latch A contents and the DAC A output are not changed by this write.
3. double buffered change of both DAC outputs
Assuming that DACs A and B start at zero code (e.g. after power up), if DAC A is to be driven to
mid-scale and DAC B to full-scale, and if the outputs are to begin rising at the same time, this can
be achieved as follows:
First,
0d01 1111 1111 11xx
is written (bit D15 on the left, D0 on the right) to the serial interface. This loads the full-scale code
into the double buffer but does not change the latch B contents and the DAC B output voltage. The
latch A contents and the DAC A output are also unaffected by this write operation.
Changing from fast to slow to fast mode changes the supply current which can glitch the outputs,
and so D14 (designated by d in the above data word) should be set to maintain the speed mode set
by the previous write.
Next,
1d00 1000 0000 00xx
is written (bit D15 on the left, D0 on the right) to the serial interface. This writes the mid-scale code
(1000000000) to latch A and also copies the full-scale code from the double buffer to latch B. Both
DAC outputs thus begin to rise after the second write.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
10
WM2637
Production Data
PACKAGE DIMENSIONS
D: 8 PIN SOIC 3.9mm Wide Body
DM009.B
B
e
8
5
E
H
L
1
4
D
h x 45o
A1
A
-C-
a
C
0.10 (0.004)
SEATING PLANE
Dimensions
(mm)
Dimensions
(Inches)
Symbols
MIN
1.35
0.10
0.33
0.19
4.80
MAX
1.75
0.25
0.51
0.25
5.00
MIN
MAX
A
A1
B
C
D
e
0.0532
0.0040
0.0130
0.0075
0.1890
0.0688
0.0098
0.0200
0.0098
0.1968
1.27 BSC
0.050 BSC
E
h
H
L
3.80
0.25
5.80
0.40
0o
4.00
0.50
6.20
1.27
8o
0.1497
0.0099
0.2284
0.0160
0o
0.1574
0.0196
0.2440
0.0500
8o
a
REF:
JEDEC.95, MS-012
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).
D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
11
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