WM8706_05 [WOLFSON]
24-bit, 192kHz Stereo DAC with Volume Control; 24位， 192kHz的立体声DAC，具有音量控制
| 型号： | WM8706_05 |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | 24-bit, 192kHz Stereo DAC with Volume Control |
| 文件： | 总26页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8706
w
24-bit, 192kHz Stereo DAC with Volume Control
DESCRIPTION
FEATURES
•
•
Stereo DAC
The WM8706 is a high performance stereo DAC designed
for audio applications such as DVD, home theatre systems,
and digital TV. The WM8706 supports data input word
lengths from 16 to 32-bits and sampling rates up to 192kHz.
The WM8706 can implement 2 channels at 192kHz for high-
end DVD-Audio. The WM8706 consists of a serial interface
port, digital interpolation filters, multi-bit sigma delta
modulators and stereo DAC in a small 28-lead SSOP
package. The WM8706 also includes a digitally controllable
mute and attenuate function on each channel.
Audio Performance
-
-
106dB SNR (‘A’ weighted @ 48kHz) DAC
-97dB THD
•
•
•
DAC Sampling Frequency: 8kHz – 192kHz
3-Wire Serial Control Interface or Hardware Control
Programmable Audio Data Interface Modes
-
I2S, Left, Right Justified, DSP
16/20/24/32 bit Word Lengths
-
The WM8706 supports a variety of connection schemes for
audio DAC control. The MPU serial port provides access to
a wide range of features including on-chip mute, attenuation
and phase reversal. A hardware controllable interface is
also available. It is pin-compatible with the WM8716
provided the oscillator circuit on WM8716 is not required in
the application.
•
Independent Digital Volume Control on Each Channel with
127.5dB Range in 0.5dB Steps
•
•
•
3.0V – 5.5V Supply Operation
28-Lead SSOP Package
Exceeds Dolby Class A Performance Requirements
APPLICATIONS
The WM8706 is an ideal device to interface to AC-3,
DTS, and MPEG audio decoders for surround sound
applications, or for use in DVD players supporting DVD-A.
•
•
•
•
DVD-Audio and DVD ‘Universal’ Players
Home theatre systems
Digital TV
Digital broadcast receivers
BLOCK DIAGRAM
MLIIS
MCDM1 MDDM0 MUTEB CSBIWO ZERO
MODE
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WM8706
CONTROL INTERFACE
SIGMA
DELTA
MODULATOR
LOW
PASS
FILTER
RIGHT
DAC
MUTE/
ATTEN
VOUTR
VOUTL
BCKIN
LRCIN
DIN
SERIAL
INTERFACE
DIGITAL FILTERS
SIGMA
DELTA
MODULATOR
LOW
PASS
FILTER
LEFT
DAC
MUTE/
ATTEN
VMID
XTI
DGND
AVDD DVDD
VREFP VREFN AGND
Production Data, July 2005, Rev 4.1
WOLFSON MICROELECTRONICS plc
Copyright 2005 Wolfson Microelectronics plc
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WM8706
Production Data
TABLE OF CONTENTS
DESCRIPTION ............................................................................................................1
FEATURES..................................................................................................................1
APPLICATIONS ..........................................................................................................1
BLOCK DIAGRAM ......................................................................................................1
PIN CONFIGURATION................................................................................................3
ORDERING INFORMATION .......................................................................................3
PIN DESCRIPTION .....................................................................................................4
ABSOLUTE MAXIMUM RATINGS..............................................................................5
DC ELECTRICAL CHARACTERISTICS .....................................................................6
ELECTRICAL CHARACTERISTICS ...........................................................................6
TERMINOLOGY................................................................................................................. 7
MASTER CLOCK TIMING.................................................................................................. 8
DIGITAL AUDIO INTERFACE............................................................................................ 8
MPU INTERFACE TIMING................................................................................................. 9
DEVICE DESCRIPTION............................................................................................10
INTRODUCTION...............................................................................................................10
CLOCKING SCHEMES .....................................................................................................10
DIGITAL AUDIO INTERFACE...........................................................................................10
AUDIO DATA SAMPLING RATES.....................................................................................13
HARDWARE CONTROL MODES .....................................................................................13
SOFTWARE CONTROL INTERFACE...............................................................................15
REGISTER MAP ...............................................................................................................16
ATTENUATION CONTROL...............................................................................................18
DIGITAL FILTER CHARACTERISTICS....................................................................21
DAC FILTER RESPONSES...............................................................................................21
DIGITAL DE-EMPHASIS CHARACTERISTICS........................................................22
RECOMMENDED EXTERNAL COMPONENTS .......................................................23
RECOMMENDED EXTERNAL COMPONENT VALUES ...................................................23
RECOMMENDED ANALOGUE LOW PASS FILTER (OPTIONAL) .........................24
PACKAGE DIMENSIONS .........................................................................................25
IMPORTANT NOTICE...............................................................................................26
ADDRESS: ........................................................................................................................26
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PIN CONFIGURATION
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
MLIIS
LRCIN
DIN
2
MCDM1
MDDM0
3
BCKIN
NC
4
MUTEB
MODE
CSBIWO
NC
5
XTI
6
NC
7
DGND
DVDD
NC
8
ZERO
VREFP
VREFN
VMID
NC
9
10
11
12
13
14
NC
NC
NC
VOUTL
AVDD
VOUTR
AGND
ORDERING INFORMATION
DEVICE
TEMPERATURE
RANGE
PACKAGE
MOISTURE
PEAK SOLDERING
TEMPERATURE
SENSITIVITY LEVEL
WM8706SEDS
-25 to +85oC
MSL 1
260oC
28-lead SSOP
(lead free)
WM8706SEDS/R
-25 to +85oC
MSL 1
260oC
28-lead SSOP
(lead free, tape and
reel)
Note:
Reel quantity = 2,000
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PIN DESCRIPTION
PIN
1
NAME
LRCIN
DIN
TYPE
Digital Input
Digital Input
Digital Input
NC
DESCRIPTION
DAC Sample Rate Clock Input
2
Serial Audio Data Input
Audio Data Bit Clock Input.
No internal connection
3
BCKIN
4
5
ZERO
Digital Output (Open Drain) Infinite ZERO Detect Flag (L=IZD detected, H=IZD not detected)
6
NC
Supply
No Internal Connection
7
DGND
DVDD
Digital Ground Supply
8
Supply
Digital Positive Supply
9
NC
No Internal Connection
10
11
12
13
14
15
16
17
18
19
20
21
22
23
NC
No Internal Connection
NC
No Internal Connection
NC
No Internal Connection
VOUTR
AGND
AVDD
Analogue Output
Supply
Right Channel DAC Output
Analogue Ground Supply
Supply
Analogue Positive Supply
VOUTL
Analogue Output
NC
Left Channel DAC Output
No Internal Connection
VMID
VREFN
VREFP
ZERO
Analogue Output
Supply
Mid Rail Decoupling Point
DAC Negative Reference – normally AGND, must not be below AGND
DAC Positive Reference – normally AVDD, must not be above AVDD
Infinite Zero Detect Flag
Supply
Digital Output
NC
No Internal Connection
CSBIWO
Digital Input
Software Mode: 3-Wire Serial Control Chip Select
Hardware Mode: Input Word Length, Pull Up
Control Mode Selection (Low = Hardware, High = Software), Pull Down
24
25
MODE
Digital Input
MUTEB
Digital Bi-directional
Mute Control (L = Mute on, H = Mute off, Z = Automute Enabled), Pull
Up
26
27
28
MDDM0
MCDM1
MLIIS
Digital Bi-directional
Digital Input
Software Mode: 3-Wire Serial Control Data Input:
Hardware Mode: De-Emphasis
Software Mode: 3-Wire Serial Control Clock Input
Hardware Mode: De-Emphasis, Pull Down
Software Mode 3-Wire Serial Control Load Input
Hardware Mode: Input Data Format Selection, Pull Up
Digital Input
Note:
Digital input pins have Schmitt trigger input buffers.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
-0.3V
MAX
+7V
Digital supply voltage
Analogue supply voltage
Voltage range digital inputs
Voltage range analogue inputs
Master Clock Frequency (XTI)
Operating temperature range, TA
Storage temperature
-0.3V
+7V
DGND -0.3V
AGND -0.3V
DVDD +0.3V
AVDD +0.3V
50MHz
-25°C
-65°C
+85°C
+150°C
Note:
Analogue and digital grounds must always be within 0.3V of each other.
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DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
DVDD
TEST CONDITIONS
MIN
3.0
TYP
MAX
UNIT
V
Digital supply range
Analogue supply range
Ground
5.5
5.5
AVDD
3.0
V
AGND, DGND
0
0
V
Difference DGND to AGND
Analogue supply current
Digital supply current
Analogue supply current
Digital supply current
-0.3
+0.3
V
AVDD = 5V
DVDD = 5V
AVDD = 3.3V
DVDD = 3.3V
19
8
mA
mA
mA
mA
18
4
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
0.8
UNIT
Digital Logic Levels (TTL Levels)
Input LOW level
VIL
VIH
V
V
V
V
Input HIGH level
2.0
Output LOW
VOL
VOH
I
OL = 1mA
AGND + 0.3V
Output HIGH
I
OH = 1mA
AVDD - 0.3V
(VREFP -
Analogue Reference Levels
Reference voltage
VMID
(VREFP -
(VREFP -
V
VREFN)/2 - VREFN)/2 VREFN)2 +
50mV
50mV
Potential divider resistance
RVMID
10k
Ω
DAC Output (Load = 10K Ω. 50pF)
0dBFs Full scale output voltage
At DAC outputs
1.1 x
AVDD/5
106
Vrms
dB
SNR (Note 1,2,3)
SNR (Note 1,2,3)
SNR (Note 1,2,3)
SNR (Note 1,2,3)
A-weighted,
@ fs = 48kHz
A-weighted
@ fs = 96kHz
A-weighted
100
106
106
102
dB
dB
@ fs = 192kHz
A-weighted,
dB
@ fs = 48kHz
AVDD, DVDD = 3.3V
A-weighted
@ fs = 96kHz
AVDD, DVDD = 3.3V
SNR (Note 1,2,3)
SNR (Note 1,2,3)
102
dB
Non ‘A’ weighted @ fs
= 48kHz
103
dB
THD (Note 1,2,3)
1kHz, 0dBfs
-97
106
100
dB
dB
dB
THD+N (Dynamic range, Note 2)
DAC channel separation
1kHz, -60dBfs
100
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Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Output Levels
Output level
Load = 10k Ω, 0dBFS
1.1
VRMS
VRMS
Load = 10k Ω, 0dBFS,
0.726
(AVDD = 3.3V)
Gain mismatch
channel-to-channel
1
1
%FSR
kΩ
Minimum resistance load
To midrail or a.c.
coupled
To midrail or a.c.
coupled
600
Ω
(AVDD = 3.3V)
Maximum capacitance load
Output d.c. level
5V or 3.3V
100
pF
V
(VREFP -
VREFN)/2
Power On Reset (POR)
POR threshold
2.4
V
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted
over a 20Hz to 20kHz bandwidth.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a
filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification
values.
3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no
signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a
THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.
THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the
other. Normally measured by sending a full scale signal down one channel and measuring the other.
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MASTER CLOCK TIMING
tXTIL
XTI
tXTIH
tXTIY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Master Clock Timing Information
XTI Master clock pulse width high
XTI Master clock pulse width low
XTI Master clock cycle time
XTI Duty cycle
tXTIH
tXTIL
tXTIY
13
13
ns
ns
ns
26
40:60
60:40
DIGITAL AUDIO INTERFACE
tBCH
tBCL
BCKIN
LRCIN
DIN
tBCY
tLRSU
tDS
tLRH
tDH
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN cycle time
tBCY
tBCH
tBCL
40
16
16
8
ns
ns
ns
ns
BCKIN pulse width high
BCKIN pulse width low
LRCIN set-up time to
BCKIN rising edge
tLRSU
LRCIN hold time from
BCKIN rising edge
tLRH
tDS
8
8
8
ns
ns
ns
DIN set-up time to BCKIN
rising edge
DIN hold time from BCKIN
rising edge
tDH
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MPU INTERFACE TIMING
CSBIWO
MLIIS
tCSSU
tCSSH
tCSL
tCSH
tSCY
tCSS
tSCS
tSCH
tSCL
MCDM1
MDDM0
LSB
tDSU
tDHO
Figure 3 Program Register Input Timing - 3-Wire Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
MCDM1 rising edge to MLIIS
rising edge
tSCS
40
ns
MCDM1 pulse cycle time
MCDM1 pulse width low
MCDM1 pulse width high
MDDM0 to MCDM1 set-up time
MCDM1 to MDDM0 hold time
MLIIS pulse width low
tSCY
tSCL
80
20
20
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
Ns
ns
tSCH
tDSU
tDHO
tCSL
MLIIS pulse width high
tCSH
tCSS
tCSSU
tCSSH
MLIIS rising to SCLK rising
CSBIWO to MLIIS set-up time
MLIIS to CSBIWO hold time
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DEVICE DESCRIPTION
INTRODUCTION
The WM8706 is a high performance DAC designed for digital consumer audio applications. Its
range of features make it ideally suited for use in DVD players, AV receivers and other high end
consumer audio equipment.
The WM8706 is a complete 2-channel stereo audio digital-to-analogue converter, including
digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit
stereo DAC and output smoothing filters. The WM8706 includes an on-board digital volume
control, configurable digital audio interface and a 3 wire MPU control interface. It is fully
compatible and an ideal partner for a range of industry standard microprocessors, controllers
and DSPs.
Control of internal functionality of the device is by either hardware control (pin programmed) or
software control (3-wire serial control interface). The MODE pin selects between hardware and
software control. The software control interface may be asynchronous to the audio data
interface. Control data will be re-synchronised to the audio processing internally.
Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between
clock rates being automatically controlled in hardware mode, or serial controlled when in
software mode. Sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the
appropriate master clock is input. Support is also provided for up to 192ks/s using a master
clock of 128fs or 192fs.
The audio data interface supports right, left and I2S (Philips left justified, one bit delayed)
interface formats along with a highly flexible DSP serial port interface. When in hardware mode,
the three serial interface pins become control pins to allow selection of input data format type
(I2S or right justified), input word length (16, 20, or 24-bit) and de-emphasis functions.
The device is packaged in a small 28-pin SSOP and is a pin-compatible alternative to the
WM8716.
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference
clock to which all audio data processing is synchronised. This clock is often referred to as the
audio system’s Master Clock. The external master system clock can be applied directly through
the XTI input pin with no software configuration necessary for sample rate selection.
Note that on the WM8706, XTI is used to derive clocks for the DAC path. The DAC path
consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing.
In a system where there are a number of possible sources for the reference clock it is
recommended that the clock source with the lowest jitter be used to optimise the performance
of the DAC.
DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. 5 popular
interface formats are supported:
•
Left Justified mode
Right Justified mode
I2S mode
•
•
•
•
DSP Early mode
DSP Late mode
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits. The
exception is that 32 bit data is not supported in right justified mode. DIN and LRCIN are
sampled on the rising, or falling edge of BCKIN depending on the format selected.
In left justified, right justified and I2S modes, the digital audio interface receives data on the DIN
input. Audio Data is time multiplexed with LRCIN indicating whether the left or right channel is
present. LRCIN is also used as a timing reference to indicate the beginning or end of the data
words.
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In left justified, right justified and I2S modes, the minimum number of BCKINs per LRCIN period
is 2 times the selected word length. LRCIN must be high for a minimum of word length BCKINs
and low for a minimum of word length BCKINs. Any mark to space ratio on LRCIN is
acceptable provided the above requirements are met. The WM8706 will automatically detect
when data with a LRCIN period of exactly 32 is sent, and select 16 bit mode - overriding any
previously programmed word length. Word length will revert to the previously programmed
value when a LRCIN period other than 32 is detected. (see Figure 4, Figure 5 and Figure 6).
In DSP early or DSP late mode, the data is time multiplexed onto DIN. LRCIN is used as a
frame sync signal to identify the MSB of the first word. The minimum number of BCKINs per
LRCIN period is 2 times the selected word length. Any mark to space ratio is acceptable on
LRCIN provided the rising edge is correctly positioned (see Figure 7 and Figure 8).
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN
transition. LRCIN is high during the left samples and low during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
Figure 4 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left samples and low during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 5 Right Justified Mode Timing Diagram
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I2S MODE
In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN
transition. LRCIN is low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
1 BCKIN
1 BCKIN
DIN
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 6 I2S Mode Timing Diagram
DSP EARLY MODE
In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one which
detects a low to high transition on LRCIN. No BCKIN edges are allowed between the data
words. The word order is DIN left, DIN right.
1 BCKIN
1 BCKIN
1/fs
LRCIN
BCKIN
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DIN
1
2
n
1
2
n
n-1
n-1
MSB
LSB
Input Word Length (IWO)
Figure 7 DSP Early Mode Timing Diagram
DSP LATE MODE
In DSP late mode, the first bit is sampled on the BCKIN rising edge which detects a low to high
transition on LRCIN. No BCKIN edges are allowed between the data words. The word order is
DIN left, DIN right.
1/fs
LRCIN
BCKIN
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DIN
1
2
n
1
2
n
1
n-1
n-1
MSB
LSB
Input Word Length (IWO)
Figure 8 DSP Late Mode Timing Diagram
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AUDIO DATA SAMPLING RATES
The master clock for WM8706 supports audio sampling rates from 128fs to 768fs, where fs is
the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
master clock is used to operate the digital filters and the noise shaping circuits.
The WM8706 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 32 master clocks). If
there is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output.
The master clock should be synchronised with LRCIN, although the WM8706 is tolerant of
phase differences or jitter on this clock.
SAMPLING
RATE
MASTER CLOCK FREQUENCY (MHZ) (XTI)
128fs
192fs
256fs
384fs
512fs
768fs
(LRCIN)
32kHz
44.1kHz
48kHz
4.096
5.6448
6.114
6.144
8.467
8.192
11.2896
12.288
24.576
12.288
16.9340
18.432
36.864
16.384
22.5792
24.576
24.576
33.8688
36.864
9.216
18.432
96kHz
12.288
Unavailable Unavailable
192kHz
24.576
36.864
Unavailable Unavailable Unavailable Unavailable
Table 1 Typical Relationships Between System Frequency and Sampling Rates.
HARDWARE CONTROL MODES
When the MODE pin is held low, the following hardware modes of operation are available.
MUTE AND AUTOMUTE OPERATION
In both hardware and software modes, pin 25 (MUTEB) controls selection of MUTE directly,
and can be used to enable and disable the automute function. Automute is enabled by leaving
MUTEB pin floating, it is disabled by applying a signal to the pin. When left floating this pin
becomes an output and indicates infinite ZERO detect (IZD), see also pin 5 (ZERO). The
status of IZD controls the selection of MUTE when automute is enabled. When IZD is detected
MUTE is enabled and when IZD is not detected MUTE is disabled.
MUTEB PIN
DESCRIPTION
0
1
Mute DAC channels
Normal Operation
Floating
Enable IZD, MUTEB becomes an output to indicate when IZD occurs.
Table 2 Mute and Automute Control
ZERO PIN
DESCRIPTION
0
1
Indicates Infinite Zero detected from the digital input.
Indicates Infinite Zero not detected from the digital input.
Table 3 Zero Pin Output
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Figure 9 shows the application and release of MUTE whilst a full amplitude sinusoid is being
played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace)
begins to decay exponentially from the DC level of the last input sample. The output will decay
towards VMID with a time constant of approximately 64 input samples. When MUTE is de-
asserted, the output will restart almost immediately from the current input sample.
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
0.001
0.002
0.003
0.004
0.005
0.006
Time(s)
Figure 9 Application and Release of Soft Mute
The MUTEB pin is an input to select mute or not mute. MUTEB is active low; taking the pin low
causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking
MUTEB high again allows data into the filter.
The automute function detects a series of zero value audio samples of 1024 samples long
being applied to both channels. After such an event,
a latch is set whose output
(AUTOMUTED) is wire OR’ed through a 10kohm resistor to the MUTEB pin. Thus if the
MUTEB pin is not being driven, the automute function will assert mute.
If MUTEB is tied high, AUTOMUTE is overridden and will not mute unless the IZD register bit is
set. If MUTEB is driven from a bi-directional source, then both MUTE and automute functions
are available. If MUTEB is not driven, AUTOMUTED appears as a weak output (10k source
impedance) so can be used to drive external mute circuits. Automute will be removed as soon
as any channel receives a non-zero input.
A diagram showing how the various Mute modes interact is shown below in Figure 10.
IZD (Register Bit)
AUTOMUTED
(Internal Signal)
10kΩ
SOFTMUTE
(Internal
Signal)
MUTEB
PIN
MUT (Register Bit)
Figure 10 Selection Logic for MUTE Modes
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INPUT FORMAT SELECTION
In hardware mode, MLIIS (pin 28) and CSBIWO (pin 23) become input controls for selection of
input data format type and input data word length.
MLIIS
CSBIWO
INPUT DATA MODE
24-bit right justified**
20-bit right justified
16-bit I2S
0
0
0
1
0
1
1
1
24-bit I2S
Table 4 Input Format Selection
Note:
In 24 bit I2S mode, any width of 24 bits or less is supported provided that LRCIN is high for a
minimum of 24 BCKINs and low for a minimum of 24 BCKINs.
** This mode differs from the WM8716 which does 16-bit right justified in this mode. The
previous mode is still available by using exactly 32 BCKIN per LRCIN cycle, 16 for left and
right. This mode is automatically detected within the hardware and overrides the data width
specified but not the format.
DE-EMPHASIS CONTROL
In hardware mode, MCDM1 (pin 27) and MDDM0 (pin 26) become input controls for selection
of de-emphasis filtering to be applied.
MCDM1
MDDM0
DE-EMPHASIS**
Off
0
0
0
1
0
1
48kHz
1
44.1kHz
32kHz
1
Table 5 De-emphasis Control
Note:
** The actual de-emphasis within the WM8706 is the same for all data rates. This differs from
WM8716 which has a different response for each sample rate.
SOFTWARE CONTROL INTERFACE
SELECTION OF CONTROL MODE
The WM8706 may be programmed to operate in hardware or software control modes. This is
achieved by setting the state of the MODE pin.
MODE
INTERFACE FORMAT
Hardware Control Mode
Software Control Mode
0
1
Table 6 Control Interface Mode Selection
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3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
The WM8706 can be controlled using a 3-wire serial interface. MDDM0 is used for the program
data, MCDM1 is used to clock in the program data and MLIIS is used to latch in the program
data. The 3-wire interface protocol is shown in Figure 11.
MLIIS
MCDM1
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MDDM0
Figure 11 3-Wire Serial Interface
Notes:
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
REGISTER MAP
WM8706 uses a total of 4 programme registers, which are 16-bits long. These registers are all
loaded through input pin MDDM0. After the 16 data bits are clocked in, MLIIS is used to latch in
the data to the appropriate register. Table
4 registers.
7
shows the complete mapping of the
B15
B14
B13
B12
B11
B10
B9
0
B8
B7
B6
LAT6
RAT6
0
B5
LAT5
RAT5
IW2
B4
B3
LAT3
RAT3
IW0
0
B2
LAT2
RAT2
B1
LAT1
RAT1
B0
LAT0
RAT0
M0
M1
M2
M3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
UPDATEL LAT7
UPDATER RAT7
LAT4
RAT4
IW1
0
1
0
0
0
0
PWRDN DEEMPH MUT
I2S
0
1
IZD
SF1
SF0
BCP
REV
ATC
LRP
ADDRESS
DATA
Table 7 Mapping of Program Registers
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REGISTER
ADDRESS
A2, A1, A0
000
BITS
LABEL
DEFAULT
DESCRIPTION
[7:0]
8
LAT[7:0]
11111111 (0dB)
0
Attenuation data for left channel in 0.5dB steps.
Attenuation data load control for left channel.
A2, A1, A0
UPDATEL
DACL
Attenuation
0: Store DACL in intermediate latch (no change to output)
1: Store DACL and update attenuation on all channels.
Attenuation data for right channel in 0.5dB steps.
Attenuation data load control for right channel.
0: Store DACR in intermediate latch (no change to output)
1: Store DACR and update attenuation on all channels.
Left and right DACs soft mute control.
0: No mute
001
[7:0]
8
RAT[7:0] 11111111 (0dB)
DACR
Attenuation
UPDATER
0
0
0
0
010
0
1
2
MUT
DAC Control
1: Mute
DEEMPH
PWDN
De-emphasis control.
0: De-emphasis off
1: De-emphasis on
Left and Right DACs Power-down Control
0: All DACs running, output is active
1: All DACs in power saving mode, output muted
Audio data format select.
[5:3]
0
IW[2:0]
I2S
000
0
011
Audio data format select.
Interface
Control
1
LRP
0
Polarity select for LRCIN/DSP mode select.
0: normal LRCIN polarity/DSP late mode
1: inverted LRCIN polarity/DSP early mode
2
ATC
0
Attenuator Control.
0: All DACs use attenuations as programmed.
1: Right channel DACs use corresponding left DAC
attenuations
4
5
REV
BCP
0
0
Output phase reverse.
BCKIN Polarity
0 : normal BCKIN polarity
1: inverted BCKIN polarity
[7:6]
8
SF[1:0]
IZD
00
0
De-Emphasis sample rate select.
Infinite zero detection circuit control and automute control
0: Infinite zero detect disabled
1: Infinite zero detect enabled
Table 8 Register Bit Descriptions
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ATTENUATION CONTROL
Each DAC channel can be attenuated digitally before being applied to the digital filter. Attenuation is 0dB by default but can be
set between 0 and 127.5dB in 0.5dB steps using the 8 Attenuation control bits. All attenuation registers are double latched
allowing new values to be pre-latched to both channels before being updated synchronously. Setting the UPDATE bit on any
attenuation write will cause all pre-latched values to be immediately applied to the DAC channels.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
A2, A1, A0
000
7:0
8
LAT[7:0]
11111111
(0dB)
Attenuation data for Left channel DACL in 0.5dB steps.
DACL
Attenuation
UPDATEL
0
Controls simultaneous update of all Attenuation Latches
0: Store DACL in intermediate latch (no change to output)
1: Store DACL and update attenuation on all channels.
Attenuation data for Right channel DACR in 0.5dB steps.
001
7:0
8
RAT[7:0]
11111111
(0dB)
DACR
Attenuation
UPDATER
0
Controls simultaneous update of all Attenuation Latches
0: Store DACR in intermediate latch (no change to output)
1: Store DACR and update attenuation on all channels.
Table 9 Attenuation Register Map
Note:
1. The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the
relevant DAC. If UPDATE=1, all pre-latched values will be applied from the next input sample.
2. Care should be used in reducing the attenuation as rapid large volume changes can introduce zipper noise.
DAC OUTPUT ATTENUATION
Registers LAT and RAT control the left and right channel attenuation. Table 10 shows how the
attenuation levels are selected from the 8-bit words.
XAT[7:0]
ATTENUATION LEVEL
00(hex)
∞dB (mute)
01(hex)
127.5dB
:
:
:
:
:
:
FE(hex)
0.5dB
0dB
FF(hex)
Table 10 Attenuation Control Levels
MUTE MODES
Setting the MUT register bit will apply a 'soft' mute to the input of the digital filters:
REGISTER ADDRESS
010
BIT
LABEL
DEFAULT
DESCRIPTION
Soft Mute select
0
MUT
0
0 : Normal Operation
DAC Control
1: Soft mute all channels
Table 11 Mute Control
DE-EMPHASIS MODE
Setting the DEEMPH register bit puts the all the digital filters into de-emphasis mode:
REGISTER ADDRESS
010
BIT
LABEL
DEFAULT
DESCRIPTION
De-emphasis mode select:
0 : De-emphasis Off
1
DEEMPH
0
DAC Control
1: De-emphasis On
Table 12 De-emphasis Control
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POWERDOWN MODE
Setting the PWDN register bit immediately connects all outputs to VMID and selects a low power
mode. All trace of the previous input samples is removed, and all register settings are cleared.
When PWDN is cleared again the first 16 input samples will be ignored as the FIR will repeat
it's power-on initialisation sequence.
REGISTER ADDRESS
010
BIT
LABEL
DEFAULT
DESCRIPTION
2
PWDN
0
Power Down Mode Select:
0 : Normal Mode
DAC Control
1: Power Down Mode
Table 13 Powerdown Control
DIGITAL AUDIO INTERFACE CONTROL REGISTERS
The WM8706 has a fully featured digital audio interface that is a superset of that contained in
the WM8716. Interface format is selected via the IW[2:0] register bits in register M2 and the I2S
register bit in M3.
REGISTER ADDRESS
010
BIT
LABEL
DEFAULT
DESCRIPTION
5:3
IW[2:0]
000
Interface format Select
DAC Control
Table 14 Interface Format Controls
REGISTER ADDRESS
011
BIT
LABEL
I2S
DEFAULT
DESCRIPTION
0
0
Interface format Select
Interface Control
Table 15 Interface Format Control
I2S
IW2
IW1
IW0
AUDIO INTERFACE DESCRIPTION **
16 bit right justified mode
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
20 bit right justified mode
24 bit right justified mode
24 bit left justified mode
16 bit I2S mode
24 bit I2S mode
20 bit I2S mode
20 bit left justified (MSB first) mode
16 bit DSP mode
20 bit DSP mode
24 bit DSP mode
32 bit DSP mode
16 bit left justified mode
Table 16 Audio Data Input Format
Note:
** In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If
the DAC is programmed to receive 16 or 20 bit data, the WM8706 pads the unused LSBs with
zeros. If the DAC is programmed into 32 bit mode, the 4 LSBs are ignored.
SELECTION OF LRCIN POLARITY
In left justified, right justified or I2S modes, the LRP register bit controls the polarity of LRCIN. If
this bit is set high, the expected polarity of LRCIN will be the opposite of that shown in Figure 4,
Figure 5 and Figure 6. Note that if this feature is used as a means of swapping the left and
right channels, a 1 sample phase difference will be introduced.
REGISTER ADDRESS
011
BIT
LABEL
DEFAULT
DESCRIPTION
1
LRP
0
LRCIN Polarity (normal)
0 : normal LRCIN polarity
1: inverted LRCIN polarity
Interface Control
Table 17 LRCIN Polarity Control
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In DSP modes, the LRCIN register bit is used to select between early and late modes:
REGISTER ADDRESS
011
BIT
LABEL
DEFAULT
DESCRIPTION
1
LRP
0
DSP Format (DSP modes)
0 : Early DSP mode
Interface Control
1: Late DSP mode
Table 18 DSP Format Control
In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that
detects a low to high transition on LRCIN. In DSP late mode, the first bit is sampled on the
BCKIN edge, which detects a low to high transition on LRCIN. No BCKIN rising edges are
allowed between the data words. The word order is DIN left, DIN right.
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both
left and right channel DACs from the next audio input sample. No update to the attenuation
registers is required for ATC to take effect.
REGISTER ADDRESS
011
BIT
LABEL
DEFAULT
DESCRIPTION
2
ATC
0
Attenuate Control Mode:
0 : Right channels use Right
attenuation
Interface Control
1: Right Channels use Left
Attenuation
Table 19 Attenuation Control Select
OUTPUT PHASE REVERSAL
The REV register bit controls the phase of the output signal. Setting the REV bit causes the
phase of the output signal to be inverted.
REGISTER ADDRESS
011
BIT
LABEL
DEFAULT
DESCRIPTION
Analogue Output Phase
0: Normal
4
REV
0
Interface Control
1: Inverted
Table 20 Output Phase Control
BCKIN POLARITY
By default, LRCIN and DIN are sampled on the rising edge of BCKIN and should ideally change
on the falling edge. Data sources which change LRCIN and DIN on the rising edge of BCKIN
can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCKIN
to the inverse of that shown in Figure 4, Figure 5, Figure 6, Figure 7 and Figure 8.
REGISTER ADDRESS
011
BIT
LABEL
DEFAULT
DESCRIPTION
BCKIN Polarity
5
BCP
0
0 : normal BCKIN polarity
1: inverted BCKIN polarity
Interface Control
Table 21 BCKIN Polarity Control
DE-EMPHASIS SAMPLE RATE SELECTION
The SF[1:0] bits are used to select the de-emphasis rate.
REGISTER ADDRESS
0011
BIT
LABEL
DEFAULT
DESCRIPTION **
7:6
SF[1:0]
00
De-Emphasis Sample Rate Selection
00 : De-Emphasis Off
01: 48kHz
Interface Control
10: 44.1kHz
11: 32kHz
Table 22 De-emphasis Control
Note:
** There is only one internal de-emphasis mode optimised for 44.1kHz. This is in contrast to
WM8716 which is individually optimised for each sample rate.
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INFINITE ZERO DETECTION
Setting the IZD register bit determines whether the device is automuted when a sequence of
more than 1024 zeros is detected.
REGISTER ADDRESS
011
BIT
LABEL
DEFAULT
DESCRIPTION
8
IZD
0
Infinite zero detection circuit control
and automute control
Interface Control
0: Infinite zero detect disabled
1: Infinite zero detect enabled
Table 23 IZD Control
DIGITAL FILTER CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
-3dB
MIN
TYP
MAX
UNIT
Passband Edge
Passband Ripple
Stopband Attenuation
0.487fs
f < 0.444fs
f > 0.555fs
±0.05
dB
dB
-60
Table 24 Digital Filter Characteristics
DAC FILTER RESPONSES
0.2
0.15
0.1
0
-20
-40
0.05
0
-60
-0.05
-0.1
-0.15
-0.2
-80
-100
-120
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
Frequency (Fs)
Figure 12 DAC Digital Filter Frequency Response
- 44.1, 48 and 96kHz
Figure 13 DAC Digital Filter Ripple - 44.1, 48 and 96kHz
0.2
0
-20
-40
-60
-80
0
-0.2
-0.4
-0.6
-0.8
-1
0
0.2
0.4
0.6
0.8
1
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
Frequency (Fs)
Figure 14 DAC Digital Filter Frequency Response
- 192kHz
Figure 15 DAC Digital Filter Ripple - 192kHz
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DIGITAL DE-EMPHASIS CHARACTERISTICS
0
1
0.5
0
-2
-4
-0.5
-1
-6
-1.5
-2
-8
-2.5
-3
-10
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Frequency (kHz)
Frequency (kHz)
Figure 16 De-Emphasis Frequency Response (32kHz)
Figure 17 De-Emphasis Error (32kHz)
0
0.4
0.3
0.2
0.1
0
-2
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
5
10
15
20
0
5
10
15
20
Frequency (kHz)
Frequency (kHz)
Figure 18 De-Emphasis Frequency Response (44.1kHz)
Figure 19 De-Emphasis Error (44.1kHz)
0
1
0.8
0.6
0.4
0.2
0
-2
-4
-6
-0.2
-0.4
-0.6
-0.8
-1
-8
-10
0
5
10
15
20
0
5
10
15
20
Frequency (kHz)
Frequency (kHz)
Figure 20 De-Emphasis Frequency Response (48kHz)
Figure 21 De-Emphasis Error (48kHz)
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RECOMMENDED EXTERNAL COMPONENTS
Figure 22 External Components Diagram
RECOMMENDED EXTERNAL COMPONENT VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1 and C5
C2 to C4
C6 and C7
C8
10µF
0.1µF
10µF
0.1µF
10µF
10µF
10kΩ
33Ω
De-coupling for DVDD and AVDD/VREFP
De-coupling for DVDD and AVDD/VREFP
Output AC coupling caps to remove midrail DC level from outputs.
Reference de-coupling capacitors for VMID pin.
C9
C10
Filtering for VREFP. Omit if AVDD low noise.
10k pull-up to DVDD.
R1
R2
Filtering for VREP. Use 0Ω if AVDD low noise.
Table 25 External Components Description
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RECOMMENDED ANALOGUE LOW PASS FILTER (OPTIONAL)
4.7kΩ
4.7k
Ω
+VS
_
51
Ω
10uF
1.8kΩ
7.5KΩ
+
+
-VS
1.0nF
680pF
47kΩ
Figure 23 Recommended Low Pass Filter (Optional)
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PACKAGE DIMENSIONS
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)
DM007.D
b
e
28
15
E1
E
GAUGE
PLANE
Θ
14
1
D
0.25
L
c
A1
L1
A A2
-C-
0.10 C
SEATING PLANE
Dimensions
(mm)
NOM
-----
Symbols
MIN
-----
0.05
1.65
0.22
0.09
9.90
MAX
A
A1
A2
b
c
D
e
E
E1
L
2.0
0.25
1.85
0.38
0.25
10.50
-----
1.75
0.30
-----
10.20
0.65 BSC
7.80
7.40
5.00
0.55
8.20
5.60
0.95
5.30
0.75
L1
θ
0.125 REF
0o
4o
8o
JEDEC.95, MO-150
REF:
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service
without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that
information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time
of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard
warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those mandated by government
requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by
the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in
life support devices or systems without the express written approval of an officer of the company. Life support devices or
systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure
to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a
significant injury to the user. A critical component is any component of a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any
license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of WM covering or relating to any combination, machine, or process in which such products or services might be or are
used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval,
license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information
with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business
practice, and WM is not responsible nor liable for any such use.
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or
service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
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相关型号：
WM8711CBLGEFL/RV
Consumer Circuit, CMOS, PQCC24, 4 X 4 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, MO-220VGGD-8, QFN-24
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