WM8711SEDS [WOLFSON]
Internet Audio DAC with Integrated Headphone Amplifier; 互联网音频DAC ，集成耳机放大器
| 型号： | WM8711SEDS |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | Internet Audio DAC with Integrated Headphone Amplifier |
| 文件： | 总47页 (文件大小：526K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8711 / WM8711L
w
Internet Audio DAC with Integrated Headphone Amplifier
DESCRIPTION
FEATURES
•
Audio Performance
The WM8711 or WM8711L (WM8711/L) is a low power
stereo DAC with an integrated headphone driver. The
WM8711/L is designed specifically for portable MP3 audio
and speech players. The WM8711/L is also ideal for MD,
CD machines and DAT players.
-
-
DAC SNR 100dB (‘A’ weighted) at AVDD = 3.3V
DAC SNR 90dB (‘A’ weighted) at AVDD = 1.8V
(WM8711L)
•
Low Power Headphone Playback
-
-
-
-
-
Down to 20mW at 3.3V
Stereo 24-bit multi-bit sigma delta DACs are used with
oversampling digital interpolation filters. Digital audio input
word lengths from 16-32 bits and sampling rates from 8KHz
to 96KHz are supported.
Down to 6mW at 1.8V (WM8711L)
1.42 – 3.6V Digital Supply Operation
2.7 – 3.6 V Analogue Supply Operation
1.8 – 3.6 V Analogue Supply Operation (‘L’ Variant)
•
•
•
DAC Sampling Frequency: 8KHz – 96KHz
2 or 3-Wire MPU Serial Control Interface
Programmable Audio Data Interface Modes
-
-
-
Stereo audio outputs are buffered for driving headphones
from a programmable volume control, line level outputs are
also provided along with anti-thump mute and power
up/down circuitry.
I2S, Left, Right Justified or DSP
16/20/24/32 bit Word Lengths
Master or Slave Clocking Mode
The device is controlled via a 2 or 3 wire serial interface.
The interface provides access to all features including
volume controls, mutes, de-emphasis and extensive power
management facilities. The device is available in a small 28-
lead SSOP package or the smaller 28-lead QFN (5x5x0.9
mm Body) package.
•
•
•
•
Stereo Audio Outputs
Output Volume and Mute Controls
Highly Efficient Headphone Driver
28-lead SSOP or 28-lead QFN (5x5x0.9 mm) package
A USB mode is provided where all audio rates can be
derived from a single 12MHz or 24MHz MCLK, saving on
the need for a PLL or multiple crystals.
APPLICATIONS
•
•
Portable MP3 Players
CD and Minidisc Players
BLOCK DIAGRAM
WOLFSON MICROELECRONICS c
Production Data, September 2006, Rev 4.3
To receive regular email updates, sigup at http://www.wolfsonmicro.com/enews/
Copyright 2006 Wolfson Microelectronics plc
Production Data
WM8711 / WM8711L
TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES............................................................................................................1
APPLICATIONS.....................................................................................................1
BLOCK DIAGRAM.................................................................................................1
PIN CONFIGURATION – 28-LEAD SSOP.............................................................3
ORDERING INFORMATION – 28-LEAD SSOP ....................................................3
PIN CONFIGURATION – 28-LEAD QFN ...............................................................4
ORDERING INFORMATION – 28-LEAD QFN.......................................................4
PIN DESCRIPTION ................................................................................................5
ABSOLUTE MAXIMUM RATINGS.........................................................................6
RECOMMENDED OPERATING CONDITIONS – WM8711...................................6
RECOMMENDED OPERATING CONDITIONS – WM8711L.................................6
ELECTRICAL CHARACTERISTICS – WM8711....................................................7
TERMINOLOGY.....................................................................................................8
POWER CONSUMPTION – WM8711 ....................................................................9
ELECTRICAL CHARACTERISTICS – WM8711L .................................................9
TERMINOLOGY...................................................................................................10
POWER CONSUMPTION – WM8711L................................................................11
WM8711L HEADPHONE SNR VS AVDD............................................................12
WM8711L ANALOGUE SUPPLY CURRENT VS AVDD .....................................12
DIGITAL AUDIO INTERFACE – MASTER MODE........................................................ 13
DIGITAL AUDIO INTERFACE – SLAVE MODE........................................................... 14
MPU INTERFACE TIMING........................................................................................... 14
DEVICE DESCRIPTION.......................................................................................16
INTRODUCTION.......................................................................................................... 16
AUDIO SIGNAL PATH ................................................................................................. 17
DEVICE OPERATION.................................................................................................. 22
AUDIO DATA SAMPLING RATES ............................................................................... 30
ACTIVATING DSP AND DIGITAL AUDIO INTERFACE............................................... 33
SOFTWARE CONTROL INTERFACE.......................................................................... 33
POWER DOWN MODES ............................................................................................. 35
REGISTER MAP.......................................................................................................... 37
DAC FILTER RESPONSES .................................................................................41
DIGITAL DE-EMPHASIS CHARACTERISTICS ..................................................42
RECOMMENDED EXTERNAL COMPONENTS..................................................44
PACKAGE DIMENSIONS - SSOP.......................................................................45
PACKAGE DIMENSIONS – QFN.........................................................................46
IMPORTANT NOTICE..........................................................................................47
ADDRESS:................................................................................................................... 47
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Production Data
WM8711 / WM8711L
PIN CONFIGURATION – 28-LEAD SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
DGND
DCVDD
XTO
DBVDD
CLKOUT
BCLK
2
3
4
XTI/MCLK
SCLK
DACDAT
DACLRC
NC
5
6
SDIN
CSB
7
NC
8
MODE
LLINEIN
RLINEIN
NC
HPVDD
LHPOUT
RHPOUT
HPGND
LOUT
9
10
11
12
13
14
NC
VMID
ROUT
AGND
AVDD
ORDERING INFORMATION – 28-LEAD SSOP
DEVICE
TEMPERATURE
RANGE
AVDD RANGE
PACKAGE
MOISTURE
SENSITIVITY LEVEL
PEAK SOLDERING
TEMPERATURE
28-lead SSOP
(Pb-free)
-25 to 85oC
-25 to 85oC
2.7 to 3.6V
MSL 1
260°C
260°C
WM8711SEDS
WM8711SEDS/R
28-lead SSOP
(Pb-free,
2.7 to 3.6V
MSL 1
tape and reel)
Note:
Reel quantity = 2,000
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WM8711 / WM8711L
PIN CONFIGURATION – 28-LEAD QFN
21 20 19 18 17 16 15
14
RHPOUT
NC 22
13 LHPOUT
12 HPVDD
11 NC
23
24
25
26
27
28
RLINEIN
LLINEIN
MODE
CSB
10 NC
9
SDIN
SCLK
DACLRC
8
DACDAT
1
2
3
4
5
6
7
ORDERING INFORMATION – 28-LEAD QFN
TEMPERATURE
MOISTURE SENSITIVITY
LEVEL
PEAK SOLDERING
TEMPERATURE
DEVICE
AVDD RANGE
2.7 to 3.6V
2.7 to 3.6V
1.8 to 3.6V
1.8 to 3.6V
PACKAGE
RANGE
28 QFN
WM8711GEFL
WM8711GEFL/R
WM8711LGEFL
WM8711LGEFL/R
-25 to 85oC
MSL1
MSL1
MSL 1
MSL 1
260°C
260°C
260°C
260°C
(lPb free)
28 QFN
-25 to 85oC
-25 to 85oC
-25 to 85oC
(Pb free, tape and
reel)
28 QFN
(Pb free)
28 QFN
(Pb free, tape and
reel)
Note:
Reel quantity = 3,500
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Production Data
WM8711 / WM8711L
PIN DESCRIPTION
28 LEAD
28 LEAD
QFN
5
NAME
TYPE
DESCRIPTION
SSOP
1
Digital Buffers VDD
DBVDD
CLKOUT
BCLK
Supply
Digital Output
Digital Input/Output
Digital Input
Digital Input/Output
NC
Buffered Clock Output
2
6
Digital Audio Bit Clock, Pull Down (see Note 1)
DAC Digital Audio Data Input
DAC Sample Rate Left/Right Clock, Pull Down (see Note 1)
No Connection
3
7
4
8
DACDAT
DACLRC
5
9
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
No Connection
7
NC
Headphone VDD
8
HPVDD
LHPOUT
RHPOUT
HPGND
LOUT
Supply
Left Channel Headphone Output
Right Channel Headphone Output
Headphone GND
9
Analogue Output
Analogue Output
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
Left Channel Line Output
Analogue Output
Analogue Output
Supply
Right Channel Line Output
Analogue VDD
ROUT
AVDD
Analogue GND
AGND
Ground
Mid-rail reference decoupling point
No Connection
VMID
Analogue Output
NC
No Connection
NC
Right Channel Line Input (AC coupled)
Left Channel Line Input (AC coupled)
Control Interface Selection, Pull up (see Note 1)
RLINEIN
LLINEIN
MODE
CSB
Analogue Input
Analogue Input
Digital Input
Digital Input
3-Wire MPU Chip Select/ 2-Wire MPU interface address
selection, active low, Pull up (see Note 1)
3-Wire MPU Data Input / 2-Wire MPU Data Input
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
Crystal Input or Master Clock Input (MCLK)
Crystal Output
23
24
25
26
27
28
27
28
1
SDIN
SCLK
Digital Input/Output
Digital Input
Digital Input
Digital Output
Supply
XTI/MCLK
XTO
2
Digital Core VDD
3
DCVDD
DGND
Digital GND
4
Ground
Note:
1. Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power.
2. It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB.
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Production Data
WM8711 / WM8711L
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
CONDITION
MIN
-0.3V
MAX
+3.63V
Digital supply voltage
Analogue supply voltage
-0.3V
+3.63V
Voltage range digital inputs
Voltage range analogue inputs
Operating temperature range, TA
Storage temperature after soldering
Notes:
DGND -0.3V
AGND -0.3V
-25°C
DVDD +0.3V
AVDD +0.3V
+85°C
-65°C
+150°C
1. Analogue and digital grounds must always be within 0.3V of each other.
2. The digital supply core voltage (DCVDD) must always be less than or equal to the analogue supply voltage (AVDD)
RECOMMENDED OPERATING CONDITIONS – WM8711
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supply range
Ground
DCVDD
DBVDD
1.42
2.7
1.5
3.3
3.3
0
3.6
3.6
3.6
V
V
V
V
AVDD, HPVDD
DGND,AGND,HPGND
2.7
RECOMMENDED OPERATING CONDITIONS – WM8711L
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supply range
Ground
DCVDD
DBVDD
1.42
1.8
1.5
3.6
3.6
3.6
V
V
V
V
AVDD, HPVDD
DGND,AGND,HPGND
1.8
0
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Production Data
WM8711 / WM8711L
ELECTRICAL CHARACTERISTICS – WM8711
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
VIH
VOL
0.3 x DBVDD
V
V
V
Input HIGH level
0.7 x DBVDD
0.9 x DBVDD
Output LOW
0.10 x
DBVDD
IOL = 1mA
Output HIGH
VOH
IOH = -1mA
V
Power On Reset Threshold (DCVDD)
DCVDD Threshold On -> Off
Hysteresis
0.9
0.3
0.6
V
V
V
DCVDD Threshold Off -> On
Analogue Reference Levels
Reference voltage (VMID)
Potential divider resistance
VVMID
RVMID
AVDD/2
50k
V
Ω
Line Output for DAC Playback Only (Load= 10KΩ. 50pF)
0dBFs Full scale output voltage
At LINE outputs
1.0 x
AVDD/3.3
100
Vrms
dB
Signal to Noise Ratio
(Note 1,2)
SNR
A-weighted,
@ fs = 48kHz
A-weighted
95
100
98
@ fs = 96kHz
A-weighted,
@ fs = 48kHz, AVDD
= 2.7V
Dynamic Range (Note 2)
Total Harmonic Distortion
A-weighted, -60dB
full scale input
DR
85
100
dB
dB
THD
1kHz, 0dBFs
1kHz, -3dBFs
1kHz 100mVpp
-86
-90
50
5
-80
Power Supply Rejection Ratio
PSRR
dB
20Hz to 20kHz
100mVpp
4
DAC channel separation
1kHz, 0dB signal
100
dB
Analogue Line Input to Line Output (Load= 10kΩ. 50pF, No Gain on Input ) Bypass Mode
0dB Full scale output voltage
1.0 x
AVDD/3.3
101
Vrms
dB
Signal to Noise Ratio
(Note 1,2)
SNR
THD
90
Total Harmonic Distortion
1kHz, 0dB
-93
-85
dB
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Production Data
WM8711 / WM8711L
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vrms
mW
Stereo Headphone Output
0dB Full scale output voltage
1.0 x
AVDD/3.3
30
Max Output Power
PO
RL = 32Ω
RL = 16Ω
55
Signal to Noise Ratio (Note 1,2)
Total Harmonic Distortion
SNR
THD
A-weighted
90
98
dB
%
1kHz, RL = 32Ω,
PO = 10mW rms
1kHz, RL = 32Ω,
PO = 20mW rms
1kHz 100mVpp
0.056
-65
0.1
-60
1.0
-40
dB
0.56
-45
Power Supply Rejection Ratio
PSRR
50
dB
20Hz to 20kHz
100mVpp
4
5
Programmable Gain
1kHz
1kHz
-73
6
1
6
dB
dB
dB
Programmable Gain Step Size
Mute attenuation
1kHz, 0dB
80
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’
weighted over a 20Hz to 20kHz bandwidth.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such
a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic
specification values.
3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally
a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.
THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
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Production Data
WM8711 / WM8711L
POWER CONSUMPTION – WM8711
MODE DESCRIPTION
CURRENT CONSUMPTION
TYPICAL
AVDD
(3.3V)
HPVDD DCVDD DBVDD UNITS
(3.3V)
(1.5V)
(3.3V)
DAC Playback, oscillator
and CLKOUT enabled
0
0
0
1
0
1
0
0
0
0
3.5
1.7
1.3
1.5
mA
mA
DAC Playback, using
external MCLK
3.5
1.7
1.3
0.1
Standby
0
1
1
1
1
1
1
1
1
1
17
0.4
0.3
0.7
0.7
0.2
0.1
µA
µA
Power Down
0.4
Table 1 Powerdown Mode Current Consumption Examples
Notes:
1. TA = +25oC. Slave Mode, fs = 48kHz, MCLK = 256fs (12.288MHz).
2. All figures are quiescent, with no signal.
3. The power dissipation in the headphone itself not included in the above table.
ELECTRICAL CHARACTERISTICS – WM8711L
Test Conditions
AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
VIH
VOL
0.3 x DBVDD
V
V
V
Input HIGH level
0.7 x DBVDD
0.9 x DBVDD
Output LOW
0.10 x
DBVDD
IOL = 1mA
Output HIGH
VOH
IOH = -1mA
V
Power On Reset Threshold (DCVDD)
DCVDD Threshold On -> Off
Hysteresis
0.9
0.3
0.6
V
V
V
DCVDD Threshold Off -> On
Analogue Reference Levels
Reference voltage (VMID)
Potential divider resistance
VVMID
RVMID
AVDD/2
50k
V
Ω
Line Output for DAC Playback Only (Load= 10KΩ. 50pF)
0dBFs Full scale output voltage
At LINE outputs
1.0 x
AVDD/3.3
90
Vrms
dB
Signal to Noise Ratio
(Note 1,2)
SNR
A-weighted,
@ fs = 48kHz
A-weighted
85
85
90
90
@ fs = 96kHz
Dynamic Range (Note 2)
Total Harmonic Distortion
A-weighted, -60dB
full scale input
DR
dB
dB
THD
1kHz, 0dBFs
1kHz, -3dBFs
1kHz 100mVpp
-81
-88
50
5
-75
Power Supply Rejection Ratio
PSRR
dB
20Hz to 20kHz
100mVpp
4
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Production Data
WM8711 / WM8711L
Test Conditions
AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC channel separation
1kHz, 0dB signal
100
dB
Analogue Line Input to Line Output (Load= 10kΩ. 50pF, No Gain on Input ) Bypass Mode
0dB Full scale output voltage
1.0 x
Vrms
dB
AVDD/3.3
101
Signal to Noise Ratio
(Note 1,2)
SNR
THD
90
Total Harmonic Distortion
Stereo Headphone Output
0dB Full scale output voltage
1kHz, 0dB
-93
-85
dB
1.0 x
Vrms
mW
dB
AVDD/3.3
Max Output Power
PO
RL = 32Ω
RL = 16Ω
A-weighted
9
18
86
Signal to Noise Ratio
(Note 1,2)
SNR
THD
80
Total Harmonic Distortion
1kHz, RL = 32Ω @ PO =
0.18
-55
%
5mW rms
dB
Power Supply Rejection Ratio
PSRR
1kHz 100mVpp
50
5
dB
20Hz to 20kHz
100mVpp
4
Programmable Gain
1kHz
1kHz
-73
6
1
6
dB
dB
dB
Programmable Gain Step Size
Mute attenuation
1kHz, 0dB
80
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally
a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.
THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
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Production Data
WM8711 / WM8711L
POWER CONSUMPTION – WM8711L
MODE DESCRIPTION
CURRENT CONSUMPTION
TYPICAL
AVDD
(1.8V)
HPVDD DCVDD DBVDD UNITS
(1.8V)
(1.5V)
(1.8V)
DAC Playback, oscillator
and CLKOUT enabled
0
0
0
1
0
1
0
0
0
0
1.7
0.5
1.2
0.8
mA
mA
DAC Playback, using
external MCLK
1.7
0.5
1.2
0.03
Standby
0
1
1
1
1
1
1
1
1
1
9
-
0.1
-
0.4
0.3
-
-
µA
µA
Power Down
Table 2 Powerdown Mode Current Consumption Examples
Notes:
1. TA = +25oC. Slave Mode, fs = 48kHz, MCLK = 256fs (12.288MHz).
2. All figures are quiescent, with no signal.
3. The power dissipation in the headphone itself not included in the above table.
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WM8711 / WM8711L
WM8711L HEADPHONE SNR VS AVDD
24-bit data; DCVDD=1.5V; DBVDD=1.8V; Load=32Ohm; fs=44.1kHz; Output=-5dBFS (sine)
SNR vs AVDD (DAC Playback to Headphone)
99
98
97
96
95
94
93
92
91
90
1.5
2
2.5
3
3.5
4
AVDD = HPVDD (V)
WM8711L ANALOGUE SUPPLY CURRENT VS AVDD
24-bit data; DCVDD=1.5V; DBVDD=1.8V; Load=16Ohm; fs=44.1kHz; Output=quiescent
Supply Current vs AVDD (DAC Playback to Headphone)
4
3.5
3
2.5
2
1.5
1
1.5
2
2.5
3
3.5
4
AVDD = HPVDD (V)
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WM8711 / WM8711L
MASTER CLOCK TIMING
tXTIL
MCLK
tXTIH
tXTIY
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width
high
tXTIH
tXTIL
tXTIY
18
18
ns
ns
MCLK System clock pulse width
low
MCLK System clock cycle time
MCLK Duty cycle
ns
54
40:60
60:40
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
(Output)
tDL
DACLRC
(Output)
tDLT
tDHT
DACDAT
Figure 2 Digital Audio Data Timing - Master Mode
Test Conditions
AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
DACLRC propagation delay
from BCLK falling edge
tDL
0
10
ns
ns
ns
DACDAT setup time to
BCLCK rising edge
tDST
tDHT
10
10
DACDAT hold time from
BCLK rising edge
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DIGITAL AUDIO INTERFACE – SLAVE MODE
tBCH
tBCL
BCLK
(Input)
tBCY
DACLRC
(Input)
tLRSU
tDS
tLRH
DACDAT
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, slave mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
DACLRC set-up time to
BCLK rising edge
tLRSU
DACLRC hold time from
BCLK rising edge
tLRH
tDS
10
10
10
ns
ns
ns
DACDAT set-up time to
BCLK rising edge
DACDAT hold time from
BCLK rising edge
tDH
MPU INTERFACE TIMING
tCSL
tCSH
CSB
tCSS
tSCY
tSCS
tSCH
tSCL
SCLK
SDIN
LSB
tDSU
tDHO
Figure 4 Program Register Input Timing - 3-Wire MPU interface Timing
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Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising
edge
tSCS
60
ns
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
80
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
CSB pulse width high
CSB rising to SCLK rising
t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t7
t1
t10
Figure 5 Program Register Input Timing – 2-Wire MPU Interface Timing
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
0
526
kHz
us
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Low Pulsewidth
SCLK High Pulsewidth
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
t1
t2
1.3
600
600
600
100
t3
t4
t5
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
t6
300
300
t7
t8
600
t10
900
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DEVICE DESCRIPTION
INTRODUCTION
The WM8711/L is a low power audio DAC designed specifically for portable audio products. Its
features, performance and low power consumption make it ideal for portable MP3, CD and mini-disc
players.
The WM8711/L includes line and headphone outputs from the on-board DAC, configurable digital
audio interface and a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal
partner for a range of industry standard microprocessors, controllers and DSPs.
The on-board digital to analogue converter (DAC) accepts digital audio from the digital audio
interface. Digital filter de-emphasis at 32kHz, 44.1kHz and 48kHz can be applied to the digital data
under software control. The DAC employs a high quality multi-bit high-order oversampling
architecture to again deliver optimum performance with low power consumption.
The DAC outputs and Line Inputs (BYPASS) are available both at line level and through a headphone
amplifier capable of efficiently driving low impedance headphones. The headphone output volume is
adjustable in the analogue domain over a range of +6dB to –73dB and can be muted.
The design of the WM8711/L minimises power consumption without compromising performance. It
includes the ability to power off selective parts of the circuitry under software control, thus conserving
power. Separate power save modes can be configured under software control including a standby
and power off mode.
Special techniques allow the audio to be muted and the device safely placed into standby, sections of
the device powered off, volume levels adjusted without any audible clicks, pops or zipper noises.
Therefore standby and power off modes may be used dynamically under software control, whenever
playback is not required.
The device caters for a number of different sampling rates including industry standard 8kHz, 32kHz,
44.1kHz, 48kHz, 88.2kHz and 96kHz. The WM8711/L has two schemes to support the programmable
sample rates: Normal industry standard 256/384fs sampling mode may be used. A special USB
mode is included, where all audio sampling rates can be generated from a 12.00MHz USB clock. The
digital filters used for playback are optimised for each sampling rate used.
The digital audio interface can support a range of audio data formats including I2S, DSP Mode (a
burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left justified
and MSB-First, right justified. The digital audio interface can operate in both master or slave modes.
The software control uses either a 2 or 3-wire MPU interface.
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AUDIO SIGNAL PATH
DAC FILTERS
The DAC filters perform true 24 bit signal processing to convert the incoming digital audio data from
the digital audio interface at the specified sample rate to multi-bit oversampled data for processing by
the analogue DAC. Figure 6 illustrates the DAC digital filter path.
FROM DIGITAL
DIGITAL
TO LINE
DIGITAL
MUTE
INTERPOLATION
AUDIO
INTERFACE
DE_EMPHASIS
OUTPUTS
FILTER
DEEMP
DACMU
Figure 6 DAC Filter Schematic
The DAC digital filter can apply digital de-emphasis under software control, as shown in Table 3. The
DAC can also perform a soft mute where the audio data is digitally brought to a mute level. This
removes any abrupt step changes in the audio that might otherwise result in audible clicks in the
audio outputs.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000101
2:1
DEEMP[1:0]
00
De-emphasis Control
(Digital)
Digital Audio
Path Control
11 = 48kHz
10 = 44.1kHz
01 = 32kHz
00 = Disable
3
DACMU
1
DAC Soft Mute Control
(Digital)
1 = Enable soft mute
0 = Disable soft mute
Table 3 DAC Software Control
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DAC
The WM8711/L employs a multi-bit sigma delta oversampling digital to analogue converter. The
scheme for the converter is illustrated in Figure 7.
FROM DAC
DIGITAL
FILTERS
TO LINE OUTPUT
Figure 7 Multi-Bit Oversampling Sigma Delta Schematic
The DAC converts the multi-level digital audio data stream from the DAC digital filters into high quality
analogue audio.
LINE OUTPUTS
The WM8711/L provides two low impedance line outputs LLINEOUT and RLINEOUT, suitable for
driving typical line loads of impedance 10K and capacitance 50pF.
The LLINEOUT and RLINEOUT outputs are only available at a line output level and are not level
adjustable in the analogue domain, having a fixed gain of 0dB. The level is fixed such that at the DAC
full scale level the output level is Vrms at AVDD = 3.3 volts. Note that the DAC full scale level tracks
directly with AVDD. The scheme is shown in Figure 8. The line output includes a low order audio low
pass filter for removing out-of band components from the sigma-delta DAC. Therefore no further
external filtering is required in most applications.
BYPASS
FROM LINE
INPUTS
DACSEL
FROM DAC
LINEOUT
VMID
TO HEADPHONE AMP
Figure 8 Line Output Schematic
The line output is muted by either muting the DAC (analogue) or Soft Muting (digital) and disabling
the BYPASS path. Refer to the DAC section for more details. Whenever the DAC is muted or the
device placed into standby mode the DC voltage is maintained at the line outputs to prevent any
audible clicks from being present.
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The software control for the line outputs is shown in Table 4.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000100
3
BYPASS
1
Bypass Switch
Analogue
Audio Path
Control
1 = Enable Bypass
0 = Disable Bypass
DAC Select
4
DACSEL
0
1 = Select DAC
0 = Don’t select DAC
Table 4 Output Software Control
The recommended external components are shown in Figure 9.
R2
LINEOUT
C1
R1
AGND
AGND
Figure 9 Line Outputs Application Drawing
Recommended values are C1 = 10µF, R1 = 47k, R2 = 100Ω
C1 forms a DC blocking capacitor to the line outputs. R1 prevents the output voltage from drifting so
protecting equipment connected to the line output. R2 forms a de-coupling resistor preventing
abnormal loads from disturbing the device. Note that poor choice of dielectric material for C1 can
have dramatic effects on the measured signal distortion at the output.
HEADPHONE AMPLIFIER
The WM8711/L has a stereo headphone output available on LHPOUT and RHPOUT. The output is
designed specifically for driving 16 or 32 ohm headphones with maximum efficiency and low power
consumption. The headphone output includes a high quality volume level adjustment and mute
function.
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The scheme of the circuit is shown in Figure 10.
FROM
DAC VIA
LINEOUT
HPOUT
VMID
Figure 10 Headphone Amplifier Schematic
LHPOUT and RHPOUT volumes can be independently adjusted under software control using the
LHPVOL[6:0] and RHPVOL[6:0] bits respectively of the headphone output control registers. The
adjustment is logarithmic with an 80dB range in 1dB steps from +6dB to –73dB.
The headphone outputs can be separately muted by writing codes less than 0110000 to LHPVOL[6:0]
or RHPVO[6:0]L bits. Whenever the headphone outputs are muted or the device placed into standby
mode, the DC voltage is maintained at the line outputs to prevent any audible clicks from being
present.
A zero cross detect circuit is provided at the input to the headphones under the control of the LZCEN
and RZCEN bits of the headphone output control register. Using these controls the volume control
values are only updated when the input signal to the gain stage is close to the analogue ground level.
This minimises and audible clicks and zipper noise as the gain values are changed or the device
muted. Note that this circuit has no time out so if only DC levels are being applied to the gain stage
input of more than approximately 20mV, then the gain will not be updated. This zero cross function is
enabled when the LZCEN and RZCEN bit is set high during a volume register write. If there is
concern that a DC level may have blocked a volume change (one made with LZCEN or RZCEN set
high) then a subsequent volume write of the same value, but with the LZCEN or RZCEN bit set low
will force a volume update, regardless of the DC level.
LHPOUT and RHPOUT volume and zero-cross setting can be changed independently. Alternatively,
the user can lock the two channels together, allowing both to be updated simultaneously, halving the
number of serial writes required, provided that the same gain is needed for both channels. This is
achieved through writing to the HPBOTH bit of the control register. Setting LRHPBOTH whilst writing
to LHPVOL and LZCEN will simultaneously update the Right Headphone controls similarly. The
corresponding effect on updating RLHPBOTH is also achieved.
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The software control is given in Table 5.
REGISTER
ADDRESS
BIT
6:0
LABEL
DEFAULT
DESCRIPTION
0000010
LHPVOL[6:0]
1111001
( 0dB )
Left Channel Headphone Output
Volume Control
Left
Headphone
Out
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
7
8
LZCEN
0
0
Left Channel Zero Cross detect
Enable
1 = Enable
0 = Disable
LRHPBOTH
Left to Right Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
LHPVOL[6:0] and LZCEN to
RHPVOL[6:0] and RZCEN
0 = Disable Simultaneous Load
0000011
6:0
RHPVOL[7:0]
1111001
( 0dB )
Right Channel Headphone Output
Volume Control
Right
Headphone
Out
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
7
8
RZCEN
0
0
Right Channel Zero Cross Detect
Enable
1 = Enable
0 = Disable
RLHPBOTH
Right to Left Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
RHPVOL[6:0] and RZCEN to
LHPVOL[6:0] and LZCEN
0 = Disable Simultaneous Load
Table 5 Headphone Output Software Control
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The recommended external components required to complete the application are shown in Figure 11.
HPOUT
C1
AGND
R1
AGND
Figure 11 Headphone Output Application Drawing
Recommended values are C1 = 220uF (10V electrolytic), R1 = 47k
C1 forms a DC blocking capacitor to isolate the dc of the HPOUT from the headphones. R1 form a
pull down resistor to discharge C1 to prevent the voltage at the connection to the headphones from
rising to a level that may damage the headphones.
DEVICE OPERATION
DEVICE RESETTING
The WM8711/L contains a power on reset circuit that resets the internal state of the device to a
known condition. The power on reset is applied as DCVDD powers on and released only after the
voltage level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum
turn on threshold voltage then the power on reset is re-applied. The threshold voltages and
associated hysteresis are shown in the Electrical Characteristics table.
The user also has the ability to reset the device to a known state under software control as shown in
the table below.
REGISTER
ADDRESS
BIT
LABEL
RESET
DEFAULT
DESCRIPTION
0001111
Reset Register
8:0
not reset
Reset Register
Writing 00000000 to register resets
device
Table 6 Software Control of Reset
When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and
released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the
ACK signal (approximately 1 SCLK period, refer to Figure 21).
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CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. To allow WM8711/L to be used in a centrally clocked system, the WM8711/L is
capable of either generating this system clock itself or receiving it from an external source as will be
discussed.
For applications where it is desirable that the WM8711/L is the system clock source, then clock
generation is achieved through the use of a suitable crystal connected between the XTI/MCLK input
and XTO output pins (see CRYSTAL OSCILLATOR section).
For applications where a component other than the WM8711/L will generate the reference clock, the
external system Master Clock can be applied directly through the XTI/MCLK input pin with no
software configuration necessary. Note that in this situation, the oscillator circuit of the WM8711/L can
be safely powered down to conserve power (see POWER DOWN section)
CORE CLOCK
The WM8711/L DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by
software as shown in Table 7 below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001000
6
CLKIDIV2
0
Core Clock divider select
Sampling
Control
1 = Core Clock is MCLK divides by 2
0 = Core Clock is MCLK
Table 7 Software Control of Core Clock
Having a programmable MCLK divider allows the device to be used in applications where higher
frequency master Clocks are available. For example the device can support 512fs master clocks
whilst fundamentally operating in a 256fs mode.
CRYSTAL OSCILLATOR
The WM8711/L includes a crystal oscillator circuit that allows the audio system’s reference clock to
be generated on the device. This is available to the rest of the audio system in buffered form on
CLKOUT. The crystal oscillator is a low radiation type, designed for low EMI. A typical application
circuit is shown Figure 12.
XTI/MCLK
XTO
Cp
Cp
DGND
DGND
Figure 12 Crystal Oscillator Application Circuit
The WM8711/L crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a
requirement for high quality audio DACs, regardless of the converter architecture. The WM8711/L
architecture is less susceptible than most converter techniques but still requires clocks with less than
approximately 1ns of jitter to maintain performance. In applications where there is more than one
source for the master clock, it is recommended that the clock is generated by the WM8711/L to
minimise such problems.
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CLOCKOUT
The Core Clock is internally buffered and made available externally to the audio system on the
CLKOUT output pin. CLKOUT provides a replication of the Core Clock, but buffered as suitable for
driving external loads.
There is no phase inversion between XTI/MCLK, the Core Clock and CLOCKOUT but there will
inevitably be some delay. The delay will be dependent on the load that CLOCKOUT drives. Refer to
Electrical Characteristics.
CLKOUT can also be divided by 2 under software control, refer to Table 8. Note that if CLKOUT is not
required then the CLKOUT buffer on the WM8711/L can be safely powered down to conserve power
(see POWER DOWN section). If the system architect has the choice between using FCLKOUT = FMCLK
or FCLKOUT = FMCLK/2 in the interface, the latter is recommended to conserve power. When the divide
by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical
Characteristics for timing information.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001000
7
CLKODIV2
0
CLKOUT divider select
Sampling
Control
1 = CLOCKOUT is Core Clock divides
by 2
0 = CLOCKOUT is Core Clock
Table 8 Programming CLKOUT
CLKOUT is disabled and set low whenever the device is in reset.
DIGITAL AUDIO INTERFACES
WM8711/L may be operated in either one of the 4 offered audio interface modes. These are:
•
•
•
•
Right justified
Left justified
I2S
DSP mode
All four of these modes are MSB first and operate with data 16 to 32 bits, except in right justified
mode where 32 bit data is not supported.
The digital audio interface receives the digital audio data for the internal DAC digital filters on the
DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters
with left and right channels multiplexed together. DACLRC is an alignment clock that controls whether
Left or Right channel data is present on DATDAT. DACDAT and DACLRC are synchronous with the
BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always an input.
BCLK and DACLRC are either outputs or inputs depending whether the device is in master or slave
mode. Refer to the MASTER/SLAVE OPERATION section
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There are four digital audio interface formats accommodated by the WM8711/L. These are shown in
the figures below. Refer to the Electrical Characteristic section for timing information.
Left Justified mode is where the MSB is available on the first rising edge of BCLK following a
DACLRC transition.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC
BCLK
DACDAT
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
Figure 13 Left Justified Mode
I2S mode is where the MSB is available on the 2nd rising edge of BCLK following a DACLRC
transition.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC
BCLK
1 BCLK
1 BCLK
DACDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 14 I2S Mode
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Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a DACLRC
transition, yet MSB is still transmitted first.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC
BCLK
DACDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 15 Right Justified Mode
In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising
edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately
follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be
unused BCLK cycles between the LSB of the right channel data and the next sample.
Figure 16 DSP/PCM Mode Audio Interface (mode A, LRP=1)
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Figure 17 DSP/PCM Mode Audio Interface (mode B, LRP=0)
In all modes DACLRC must always change on the falling edge of BCLK, refer to Figures 13,14,15
and 16. Operating the digital audio interface in DSP mode allows ease of use for supporting the
various sample rates and word lengths. The only requirement is that all data is transferred within the
correct number of BCLK cycles to suit the chosen word length.
In order for the digital audio interface to offer similar support in the three other modes (Left Justified,
I2S and Right Justified), the DACLRC and BCLK frequencies, continuity and mark-space ratios need
more careful consideration.
In Slave mode, DACLRC inputs are not required to have a 50:50 mark-space ratio. BCLK input need
not be continuous. It is however required that there are sufficient BCLK cycles for each DACLRC
transition to clock the chosen data word length. The non-50:50 requirement on the LRC is of use in
some situations such as with a USB 12MHZ clock. Here simply dividing down a 12MHz clock within
the DSP to generate LRC and BCLK will not generate the appropriate DACLRC since it will no longer
change on the falling edge of BCLK. For example, with 12MHz/32k fs mode there are 375 MCLK per
LRC. In these situations DACLRC can be made non 50:50.
In Master mode, DACLRC will be output with a 50:50 mark-space ratio with BCLK output at 64fs x
Base Frequency (ie 48kHz). The exception is in 96/88.2k mode where BCLK is MCLK and in USB
mode where BCLK is always 12MHz. So for example in 12MHz/32k fs mode there are 375 master
clocks per LRC period. Therefore the DACLRC output will have a mark space ratio of 187:188.
The DAC digital audio interface modes are software configurable as indicated in Table 8. Note that
dynamically changing the software format may result in erroneous operation of the interfaces and is
therefore not recommended.
The length of the digital audio data is programmable at 16/20/24 or 32 bits. Refer to the software
control table below. The data is signed 2’s complement. The DAC digital filters process data using 24
bits. If the DAC is programmed to receive 16 or 20 bit data, the WM8711/L packs the LSBs with
zeros. If the DAC is programmed to receive 32 bit data, then it strips the LSBs.
The DAC outputs can be swapped under software control using LRP and LRSWAP as shown in
Table 9. Stereo samples are normally generated as a Left/Right sampled pair. LRSWAP reverses the
order so that a Left sample goes to the right DAC output and a Right sample goes to the left DAC
output. LRP swaps the phasing so that a Right/Left sampled pair is expected and preserves the
correct channel phase difference, except in DSP mode, where LRP controls the positioning of the
MSB relative to the rising edge of DACLRC.
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To accommodate system timing requirements the interpretation of BCLK maybe inverted, this is
controlled via the software shown in Table 9. This is especially appropriate for DSP mode.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000111
1:0
FORMAT[1:0]
10
Audio Data Format Select
Digital Audio
Interface Format
11 = DSP Mode, frame sync + 2 data
packed words
10 = I2S Format, MSB-First left-1
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
Input Audio Data Bit Length Select
11 = 32 bits
3:2
IWL[1:0]
10
10 = 24 bits
01 = 20 bits
00 = 16 bits
4
LRP
0
DACLRC phase control (in left, right
or I2S modes)
1 = Right Channel DAC data when
DACLRC high
0 = Right Channel DAC data when
DACLRC low
(opposite phasing in I2S mode)
or
DSP mode A/B select ( in DSP mode
only)
1 = MSB is available on 2nd BCLK
rising edge after DACLRC rising
edge
0 = MSB is available on 1st BCLK
rising edge after DACLRC rising
edge
5
6
7
LRSWAP
MS
0
0
0
DAC Left Right Clock Swap
1 = Right Channel DAC Data Left
0 = Right Channel DAC Data Right
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Bit Clock Invert
BCLKINV
1 = Invert BCLK
0 = Don’t invert BCLK
Table 9 Digital Audio Interface Control
Note: If right justified 32 bit mode is selected then the WM8711/L defaults to 24 bits.
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MASTER AND SLAVE MODE OPERATION
The WM8711/L can be configured as either a master or slave mode device. As a master mode device
the WM8711/L controls sequencing of the data and clocks on the digital audio interface. As a slave
device the WM8711/L responds with data to the clocks it receives over the digital audio interface. The
mode is set with the MS bit of the control register as shown in Table 10.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
0000111
6
MS
0
Digital Audio Interface
Format
Table 10 Programming Master/Slave Modes
As a master mode device the WM8711/L controls the sequencing of data transfer (DACDAT) and
output of clocks (BCLK, DACLRC) over the digital audio interface. It uses the timing generated from
the MCLK input as the reference for the clock and data transitions. This is illustrated in Figure 18.
DACDAT is always an input to the WM8711/L independent of master or slave mode.
BCLK
DSP
DECODER
WM8711
DAC
DACLRC
DACDAT
Figure 18 Master Mode
As a slave device the WM8711/L sequences the data transfer (DACDAT) over the digital audio
interface in response to the external applied clocks (BCLK, DACLRC). This is illustrated in Figure 19.
BCLK
DSP
DECODER
WM8711
DAC
DACLRC
DACDAT
Figure 19 Slave Mode
Note that the WM8711/L relies on controlled phase relationships between audio interface BCLK,
DACLRC and the master MCLK or CLKOUT. To avoid any timing hazards, refer to the timing section
for detailed information.
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AUDIO DATA SAMPLING RATES
The WM8711/L provides for two modes of operation (normal and USB) to generate the required DAC
sampling rates. Normal and USB modes are programmed under software control according to the
table below.
In Normal mode, the user controls the sample rate by using an appropriate MCLK frequency and the
sample rate control register setting. The WM8711/L can support sample rates from 8ks/s up to
96ks/s.
In USB mode, the user must use a fixed MLCK frequency of 12MHz to generate sample rates from
8ks/s to 96ks/s. It is called USB mode since the common USB (Universal Serial Bus) clock is at
12MHz and the WM8711/L can be directly used within such systems. WM8711/L can generate all the
normal audio sample rates from this one Master Clock frequency, removing the need for different
master clocks or PLL circuits.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001000
0
USB/
0
Mode Select
NORMAL
BOSR
Sampling
Control
1 = USB mode (250/272fs)
0 = Normal mode (256/384fs)
Base Over-Sampling Rate
1
0
USB Mode
0 = 250fs
1 = 272fs
Normal Mode
96/88.2 kHz
0 = 256fs
0 = 128fs
1 = 384fs
1 = 192fs
5:2
SR[3:0]
0000
DAC sample rate control;
See USB Mode and Normal Mode
Sample Rate sections for operation
Table 11 Sample Rate Control
NORMAL MODE SAMPLE RATES
In normal mode MCLK is set up according to the desired sample rates of the DAC. For DAC sampling
rates of 8, 32, 48 or 96kHz, MCLK frequencies of either 12.288MHz (256fs) or 18.432MHz (384fs)
can be used. DAC sampling rates of 8, 44.1 or 88.2kHz from MCLK frequencies of either
11.2896MHz (256fs) or 16.9344MHz (384fs) can be used.
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The table below should be used to set up the device to work with the various sample rate
combinations. Refer to Digital Filter Characteristics section for an explanation of the different filter
types.
SAMPLING RATE
DAC
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
kHz
MHz
BOSR
SR3
0
SR2
0
SR1
0
SR0
0
48
12.288
18.432
12.288
18.432
12.288
18.432
12.288
18.432
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
0 (256fs)
1 (384fs)
0 (256fs)
1 (384fs)
0 (256fs)
1 (384fs)
0 (128fs)
1 (192fs)
0 (256fs)
1 (384fs)
0 (256fs)
1 (384fs)
0 (128fs)
1 (192fs)
1
1
1
2
1
1
2
0
0
0
0
8
32
0
0
0
1
0
0
0
1
0
1
1
0
0
1
1
0
96
0
1
1
1
0
1
1
1
44.1
1
0
0
0
1
0
0
0
8
1
0
0
1
(Note 1)
88.2
1
0
0
1
1
1
1
1
1
1
1
1
Table 12 Normal Mode Sample Rate Look-up Table
Notes:
1. 8k not exact, actual = 8.018kHz
2. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8711/L digital
signal processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at
256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the
actual audio data rate required by the DAC.
The exact sample rates achieved are defined by the relationships in Table 13 below.
TARGET
ACTUAL SAMPLING RATE
SAMPLING
RATE
BOSR=0
MCLK=11.2896
kHz
BOSR=1
MCLK=16.9344
MCLK=12.288
MCLK=18.432
kHz
kHz
kHz
8
kHz
8.018
8
8.018
8
(12.288MHz/256) x 1/6
32
(11.2896MHz/256) x 2/11
not available
(18.432MHz/384) x 1/6
32
(16.9344MHz/384) x 2/11
not available
32
(12.288MHz/256) x 2/3
not available
(18.432MHz/384) x 2/3
not available
44.1
48
44.1
44.1
11.2896MHz/256
not available
16.9344MHz /384
not available
48
48
12.288MHz/256
not available
18.432MHz/384
not available
88.2
96
88.2
88.2
(11.2896MHz/256) x 2
not available
(16.9344MHz /384) x 2
not available
96
96
(12.288MHz/256) x 2
(18.432MHz/384) x 2
Table 13 Normal Mode Actual Sample Rates
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128/192FS NORMAL MODE
The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the
WM8711/L is also capable of being clocked from a 128/192fs MCLK for application over limited
sampling rates as shown in the table below.
SAMPLING RATE
DAC
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
kHz
MHz
BOSR
SR3
SR2
SR1
SR0
48
6.144
9.216
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
44.1
5.6448
8.4672
Table 14 128/192fs Normal Mode Sample Rate Look-up Table
512/768FS NORMAL MODE
512fs and 768fs MCLK rates can be accommodated by using the CLKIDIV2 bit. The core clock to the
DSP will be divided by 2 so an external 512/768 MCLK will become 256/384fs internally and the
device otherwise operates as in Table 10 but with MCLK at twice the specified rate.
USB MODE SAMPLE RATES
In USB mode the MCLK input is 12MHz only.
SAMPLING RATE
DAC
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
kHz
MHz
BOSR
SR3
SR2
SR1
SR0
48
12.000
0
0
0
0
0
0
1
0
1
0
3
2
44.1
12.000
12.000
12.000
12.000
12.000
12.000
1
0
1
0
0
1
1
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
0
1
1
(Note 2)
8
8
(Note 1)
32
96
88.2
(Note 3)
Table 15 USB Mode Sample Rate Look-Up Table
Notes:
1. 8k not exact, actual = 8.021kHz
2. 44.1k not exact, actual = 44.118kHz
3. 88.1k not exact, actual = 88.235kHz
4. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8711/L digital
signal processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB
mode, with BOSR = 0, the base over-sampling rate is defined at 250Fs, with BOSR = 1, the base
over-sampling rate is defined at 272Fs. This can be used to determine the actual audio sampling rate
required by the DAC.
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The exact sample rates supported for all combinations are defined by the relationships in Table 16
below.
TARGET
ACTUAL SAMPLING RATE
SAMPLING
RATE
BOSR=0
BOSR=1
(272FS)
kHz
( 250FS)
kHz
kHz
8
8
8.021
12MHz/(250 x 48/8)
32
12MHz/(272 x 11/2)
not available
32
12MHz/(250 x 48/32)
not available
44.1
48
44.117
12MHz/272
not available
48
12MHz/250
not available
88.2
96
88.235
12MHz/136
not available
96
12MHz/125
Table 16 USB Mode Actual Sample Rates
ACTIVATING DSP AND DIGITAL AUDIO INTERFACE
To prevent any communication problems from arising across the Digital Audio Interface is disabled
(tristate with weak 100k pulldown) at power on. Once the Audio Interface and the Sampling Control
has been programmed it is activated by setting the ACTIVE bit under Software Control.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001001
Active Control
0
ACTIVE
0
Activate Interface
1 = Active
0 = Inactive
Table 17 Activating DSP and Digital Audio Interface
It is recommended that between changing any content of Digital Audio Interface or Sampling Control
Register that the active bit is reset then set.
SOFTWARE CONTROL INTERFACE
The software control interface may be operated using either a 3-wire or 2-wire MPU interface.
Selection of interface format is achieved by setting the state of the MODE pin.
In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and
CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is
used for the serial clock. In 2-wire mode, the state of CSB pin allows the user to select one of two
addresses.
SELECTION OF SERIAL CONTROL MODE
The serial control interface may be selected to operate in either 2 or 3-wire modes. This is achieved
by setting the state of the MODE pin.
MODE
INTERFACE
FORMAT
0
1
2 wire
3 wire
Table 18 Control Interface Mode Selection
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3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
The WM8711/L can be controlled using a 3-wire serial interface. SDIN is used for the program data,
SCLK is used to clock in the program data and CSB is use to latch in the program data. The 3-wire
interface protocol is shown in Figure 20.
CSB
SCLK
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
SDIN
Figure 20 3-Wire Serial Interface
Notes:
1.
2.
3.
B[15:9] are Control Address Bits
B[8:0] are Control Data Bits
CSB is edge sensitive not level sensitive. The data is latched on the rising edge of CSB.
2-WIRE SERIAL CONTROL MODE
The WM8711/L supports a 2-wire MPU serial interface. The device operates as a slave device only.
The WM8711/L has one of two slave addresses that are selected by setting the state of pin 22
(SSOP) / 26 (QFN), (CSB).
ACK
ACK
ACK
DATA B15-8
R ADDR
R/W
DATA B7-0
SDIN
SCLK
START
STOP
Figure 21 2-Wire Serial Interface
Notes:
1.
2.
B[15:9] are Control Address Bits
B[8:0] are Control Data Bits
CSB STATE
ADDRESS
0
1
0011010
0011011
Table 19 2-Wire MPU Interface Address Selection
To control the WM8711/L on the 2-wire bus the master control device must initiate a data transfer by
establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high.
This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond
to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB first.
The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of two
available addresses for this device (see Table 19). If the correct address is received and the R/W bit
is ‘0’, indicating a write, then the WM8711/L will respond by pulling SDIN low on the next clock pulse
(ACK). The WM8711/L is a write only device and will only respond to the R/W bit indicating a write. If
the address is not recognised the device will return to the idle condition and wait for a new start
condition and valid address.
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Once the WM8711/L has acknowledged a correct address, the controller will send eight data bits (bits
B[15]-B[8]). WM8711/L will then acknowledge the sent data by pulling SDIN low for one clock pulse.
The controller will then send the remaining eight data bits (bits B[7]-B[0]) and the WM8711/L will then
acknowledge again by pulling SDIN low.
A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a start
or stop condition is detected out of sequence at any point in the data transfer then the device will
jump to the idle condition.
After receiving a complete address and data sequence the WM8711/L returns to the idle state and
waits for another start condition. Each write to a register requires the complete sequence of start
condition, device address and R/W bit followed by the 16 register address and data bits.
POWER DOWN MODES
The WM8711/L contains power conservation modes in which various circuit blocks may be safely
powered down in order to conserve power. This is software programmable as shown in the table
below.
REGISTER
ADDRESS
BIT
LABEL
DACPD
DEFAULT
DESCRIPTION
0000110
3
4
5
6
7
1
DAC Power Down
Power Down
Control
1 = Enable Power Down
0 = Disable Power Down
Line Output Power Down
1 = Enable Power Down
0 = Disable Power Down
Oscillator Power Down
1 = Enable Power Down
0 = Disable Power Down
CLKOUT Power Down
1 = Enable Power Down
0 = Disable Power Down
Power Off Device
OUTPD
1
0
0
1
OSCPD
CLKOUTPD
POWEROFF
1 = Device Power Off
0 = Device Power On
Table 20 Power Conservation Modes Software Control
The power down control can be used to either a) permanently disable functions when not required in
certain applications or b) to dynamically power up and down functions depending on the operating
mode, e.g.: during playback or record. Please follow the special instructions below if dynamic
implementations are being used.
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DACPD: Powers down the DAC and DAC Digital Filters. If this is done dynamically then audible pops
will result unless the following guidelines are followed. In order to prevent pops, the DAC should first
be soft-muted (DACMU), the output should then be de-selected from the line and headphone output
(DACSEL), then the DAC powered down (DACPD). This is of use when the device enters Pause or
Stop modes. During DACPD the digital audio interface is remains active.
OUTPD: Powers down the Line and Headphone Outputs. If this is done dynamically then audible
pops may result unless the DAC is first soft-muted (DACMU). This is of use when the device enters
Record, Pause or Stop modes.
The device can be put into a standby mode (STANDBY) by powering down all the audio circuitry
under software control as shown in Table 20.
DESCRIPTION
STANDBY, but with Crystal Oscillator OS and CLKOUT
available
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
STANDBY, but with Crystal Oscillator OS available,
CLKOUT not-available
STANDBY, Crystal oscillator and CLKOUT not-available.
Table 21 Standby Mode
In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue
circuitry remain active. The active analogue includes the analogue VMID reference so that the
analogue line outputs and headphone outputs remain biased to VMID. This reduces any audible
effects caused by DC glitches when entering or leaving STANDBY mode.
The device can be powered off by writing to the POWEROFF bit of the Power Down register. In
POWEROFF mode the Control Interface and a small portion of the digital remain active. The
analogue VMID reference is disabled. Refer to Table 22.
DESCRIPTION
POWEROFF, but with Crystal Oscillator OS and
CLKOUT available
1
1
1
0
1
1
0
0
1
X
X
X
1
1
1
POWEROFF, but with Crystal Oscillator OS
available, CLKOUT not-available
POWEROFF, Crystal oscillator and CLKOUT
not-available.
Table 22 Poweroff Mode
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REGISTER MAP
The complete register map is shown in Table 24. The detailed description can be found in the
relevant text of the device description. There are 8 registers with 9 bits per register. These can be
controlled using either the 2 wire or 3 wire MPU interface.
REGISTER
B
B
B
B
B
B
B
9
B8
B7
B6
B5
B4
B3
B2
B1
B0
15 14 13 12 11 10
LRHP
BOTH
RLHP
BOTH
0
R2 (04h)
R3 (06h)
0
0
0
0
0
0
0
0
0
0
1
1
0
1
LZCEN
RZCEN
LHPVOL
RHPVOL
R4 (08h)
R5 (0Ah)
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
DAC SEL BYPASS
DAC MU
0
0
1
0
0
0
0
DEEMPH
POWER
OFF
BCLK
INV
CLK
OUTPD
R6 (0Ch)
R7 (0Eh)
R8 (10h)
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
0
0
0
OSCPD OUTPD DACPD
1
1
MS
LR SWAP LRP
IWL
FORMAT
CLK0
DIV2
0
CLKI
DIV2
0
USB/
NORM
ACTIVE
0
0
SR
BOSR
0
R9 (12h)
R15(1Eh)
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
RESET
ADDRESS
Table 23 Mapping of Program Registers
DATA
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000010
6:0
LHPVOL
[6:0]
1111001
( 0dB )
Left Channel Headphone Output
Volume Control
Left Headphone
Out
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
Left Channel Zero Cross detect Enable
1 = Enable
7
8
LZCEN
0
0
0 = Disable
LRHPBOTH
Left to Right Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
LHPVOL[6:0] and LZCEN to
RHPVOL[6:0] and RZCEN
0 = Disable Simultaneous Load
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000011
6:0
RHPVOL
[6:0]
1111001
( 0dB )
Right Channel Headphone Output
Volume Control
Right
Headphone Out
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
7
8
RZCEN
0
0
Right Channel Zero Cross detect
Enable
1 = Enable
0 = Disable
RLHPBOTH
Right to Left Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
RHPVOL[60] and RZCEN to
LHPVOL[6:0] and LZCEN
0 = Disable Simultaneous Load
Bypass Switch
0000100
3
BYPASS
1
Audio Path
Control
1 = Enable Bypass
0 = Disable Bypass
DAC Select (Analogue)
1 =Select DAC
4
DACSEL
0
0 = Don’t select DAC
De-emphasis Control (Digital)
11 = 48kHz
0000101
2:1
DEEMP[1:0]
00
Digital Audio
Path Control
10 = 44.1kHz
01 = 32kHz
00 = Disable
3
3
4
5
6
7
DACMU
1
1
1
0
0
1
DAC Soft Mute Control (Digital)
1 = Enable soft mute
0 = Disable soft mute
DAC Power Down
0000110
DACPD
Power Down
Control
1 = Enable Power Down
0 = Disable Power Down
Outputs Power Down
1 = Enable Power Down
0 = Disable Power Down
Oscillator Power Down
1 = Enable Power Down
0 = Disable Power Down
CLKOUT Power Down
1 = Enable Power Down
0 = Disable Power Down
POWEROFF mode
OUTPD
OSCPD
CLKOUTPD
POWEROFF
1 = Enable POWEROFF
0 = Disable POWEROFF
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000111
1:0
FORMAT[1:0]
10
Audio Data Format Select
Digital Audio
Interface Format
11 = DSP Mode, frame sync + 2 data
packed words
10 = I2S Format, MSB-First left-1
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
Input Audio Data Bit Length Select
11 = 32 bits
3:2
IWL[1:0]
10
10 = 24 bits
01 = 20 bits
00 = 16 bits
4
LRP
0
DACLRC phase control (in left, right or
I2S modes)
1 = Right Channel DAC data when
DACLRC high
0 = Right Channel DAC data when
DACLRC low
(opposite phasing in I2S mode)
or
DSP mode A/B select ( in DSP mode
only)
1 = MSB is available on 2nd BCLK
rising edge after DACLRC rising edge
0 = MSB is available on 1st BCLK
rising edge after DACLRC rising edge
5
6
7
LRSWAP
MS
0
0
0
DAC Left Right Clock Swap
1 = Right Channel DAC Data Left
0 = Right Channel DAC Data Right
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Bit Clock Invert
BCLKINV
1 = Invert BCLK
0 = Don’t invert BCLK
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REGISTER
ADDRESS
BIT
LABEL
USB/
DEFAULT
DESCRIPTION
0001000
0
0
Mode Select
NORMAL
Sampling
Control
1 = USB mode (250/272fs)
0 = Normal mode (256/384fs)
Base Over-Sampling Rate
USB Mode
1
BOSR
0
0 = 250fs
1 = 272fs
5:2
SR[3:0]
0000
DAC sample rate Normal Mode
control;
0 = 256fs
1 = 384fs
See USB Mode
and Normal
Mode Sample
Rate sections for
operation
6
CLKIDIV2
CLKODIV2
ACTIVE
0
Core Clock divider select
1 = Core Clock is MCLK divide by 2
0 = Core Clock is MCLK
CLKOUT divider select
1 = CLOCKOUT is MCLK divide by 2
0 = CLOCKOUT is MCLK
Activate Interface
7
0
0001001
0
0
Active Control
1 = Active
0 = Inactive
0001111
8:0
RESET
not reset
Reset Register
Reset Register
Writing 00000000 to register resets
device
Table 24 Register Map Description
Note:
All other bits not explicitly defined in the register table should be set to zero unless specified
otherwise.
DIGITAL FILTER CHARACTERISTICS
The DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2 and 3.
The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in
the proceeding pages.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.416fs
+/-0.03
UNIT
DAC Filter Type 0 (USB mode, 250fs operation)
Passband
+/- 0.03dB
-6dB
0
0.5fs
Passband Ripple
Stopband
dB
dB
0.584fs
-50
Stopband Attenuation
f > 0.584fs
DAC Filter Type 1 (USB mode, 272fs or Normal mode operation)
Passband
+/- 0.03dB
-6dB
0
0.4535fs
+/- 0.03
0.5fs
Passband Ripple
Stopband
dB
dB
0.5465fs
-50
Stopband Attenuation
f > 0.5465fs
Table 25 Digital Filter Characteristics
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DAC FILTER RESPONSES
0.04
0.03
0.02
0.01
0
0
-20
-40
-60
-0.01
-0.02
-0.03
-0.04
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.4
0.2
0.45
0.5
Frequency (Fs)
Frequency (Fs)
Figure 22 DAC Digital Filter Frequency Response–Type 0
Figure 23 DAC Digital Filter Ripple–Type 0
0.04
0.03
0.02
0.01
0
0
-20
-40
-60
-0.01
-0.02
-0.03
-0.04
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.45
0.5
Frequency (Fs)
Frequency (Fs)
Figure 24 DAC Digital Filter Frequency Response–Type 1
Figure 25 DAC Digital Filter Ripple–Type 1
0.02
0.01
0
0
-20
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.25
Frequency (Fs)
Frequency (Fs)
Figure 26 DAC Digital Filter Frequency Response–Type 2
Figure 27 DAC Digital Filter Ripple–Type 2
PD Rev 4.3 September 2006
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Production Data
WM8711 / WM8711L
0
0.05
0
-20
-40
-60
-80
-0.05
-0.1
-0.15
-0.2
-0.25
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
Frequency (Fs)
Frequency (Fs)
Figure 28 DAC Digital Filter Frequency Response–Type 3
Figure 29 DAC Digital Filter Ripple–Type 3
DIGITAL DE-EMPHASIS CHARACTERISTICS
0
0.4
0.3
0.2
0.1
0
-2
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
2000
4000
6000
8000
10000 12000 14000 16000
0
2000
4000
6000
8000
10000 12000 14000 16000
Frequency (Fs)
Frequency (Fs)
Figure 30 De-Emphasis Frequency Response (32kHz)
Figure 31 De-Emphasis Error (32kHz)
0
-2
0.4
0.3
0.2
0.1
0
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
5000
10000
Frequency (Fs)
15000
20000
0
5000
10000
Frequency (Fs)
15000
20000
Figure 32 De-Emphasis Frequency Response (44.1kHz)
Figure 33 De-Emphasis Error (44.1kHz)
PD Rev 4.3 September 2006
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Production Data
WM8711 / WM8711L
0
0.4
0.3
0.2
0.1
0
-2
-4
-6
-8
-0.1
-0.2
-0.3
-0.4
-10
0
5000
10000
15000
20000
0
5000
10000
15000
20000
Frequency (Fs)
Frequency (Fs)
Figure 34 De-Emphasis Frequency Response (48kHz)
Figure 35 De-Emphasis Error (48kHz)
PD Rev 4.3 September 2006
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Production Data
WM8711 / WM8711L
RECOMMENDED EXTERNAL COMPONENTS
3.3V
3.3V
1
14
DBVDD
DGND
+
AVDD
AGND
+
10µ
0.1
µ
F
F
0.1 F
µ
µ
F
10
28
15
µ
µ
10 F 0.1 F
3.3V
1.5V - 3.3V
+
8
27
HPVDD
HPGND
+
DCVDD
LLINEIN
µ
10 F
0.1µ
F
+
Ω
5.6k
20
11
µ
1 F
+
Ω
100
12
VREF
LOUT
ROUT
8711L Only
+
Ω
5.6k
19
µ
1 F
Ω
47k
RLINEIN
µ
1 F
+
13
100Ω
VREF
WM8711
DAC
µ
1 F
Ω
47k
5
4
DACLRC
DACDAT
BCLK
Audio Serial Data
I/F
3
+
9
LHPOUT
RHPOUT
µ
220 F
47k
Ω
3.3V
3-wire Interface
2-wire Interface
Ω
10k
+
21
22
10
MODE
CSB
SDIN
SCLK
DGND
3-wire or 2-
wire
MPU Interface
23
24
µ
220 F
47k
Ω
2
CLKOUT
VMID
Ω
100
16
33
+
µ
0.1 F
µ
10 F
*GND_PADDLE
XTI/MCLK XTO
26
25
X1
Cp
Cp
Note
1. Where possible, it is recommended that NPO or COG type capacitors should be used for best performance.
2. *Ground Paddle only on QFN package.
3. X1 should have a CL of around 12pF and Cp should be around 15pF.
Figure 36 External Components Diagram
PD Rev 4.3 September 2006
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Production Data
WM8711 / WM8711L
PACKAGE DIMENSIONS - SSOP
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)
DM007.E
b
e
28
15
E1
E
GAUGE
PLANE
Θ
14
1
D
0.25
L
c
A1
L1
A A2
-C-
0.10 C
SEATING PLANE
Dimensions
(mm)
NOM
-----
Symbols
MIN
-----
0.05
1.65
0.22
0.09
9.90
MAX
A
A1
A2
b
c
D
e
E
E1
L
2.0
0.25
1.85
0.38
0.25
10.50
-----
1.75
0.30
-----
10.20
0.65 BSC
7.80
7.40
5.00
0.55
8.20
5.60
0.95
5.30
0.75
L1
θ
1.25 REF
0o
4o
8o
JEDEC.95, MO-150
REF:
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
PD Rev 4.3 September 2006
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Production Data
WM8711 / WM8711L
PACKAGE DIMENSIONS – QFN
FL: 28 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH
DM023.G
SEE DETAIL A
CORNER
TIE BAR
D2
B
D2/2
27 28
D
5
22
INDEX AREA
(D/2 X E/2)
L
21
1
2
EXPOSED
GROUND
PADDLE
6
E2/2
A
A
E2
E
15
7
SEE DETAIL B
aaa
C
14 13
e
8
2 X
2 X
b
M
ccc
C
A
B
B
aaa
C
TOP VIEW
BOTTOM VIEW
DETAIL A
CORNER
TIE BAR
ccc
C
1
(A3)
1
A
28x b
5
M
bbb
C
A
B
0.08
C
A1
SEATING PLANE
C
SIDE VIEW
DETAIL B
0.210mm
EXPOSED
GROUND
PADDLE
L1
1
Dimensions (mm)
Symbols
MIN
0.85
0
NOM
0.90
MAX
1.00
0.05
NOTE
A
A1
A3
b
D
D2
E
E2
e
L
0.02
0.2 REF
0.23
5.00 BSC
3.3
0.18
3.2
0.30
3.4
1
2
2
5.00 BSC
3.3
3.2
3.4
0.5 BSC
5 0.40.4
0.35
0.1
L1
R
K
1
b(min)/2
0.20
Tolerances of Form and Position
aaa
bbb
ccc
0.15
0.10
0.10
JEDEC, MO-220, VARIATION VHHD-1
REF:
NOTES:
1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPR ESENTS TERMINAL PULL BACK FROM
PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF
ETCHING OF LEADFRAME.
2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2:
D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION
3. ALL DIMENSIONS ARE IN MILLIMETRES
4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY
6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.
PD Rev 4.3 September 2006
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Production Data
WM8711 / WM8711L
IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.
Any use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other
intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or
services might be or are used. Any provision or publication of any third party’s products or services does not constitute
Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document
belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is
not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or
accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any
reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
PD Rev 4.3 September 2006
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