WM8750L [WOLFSON]
STEREO CODEC FOR PORTABLE AUDIO APPLICATIONS; 立体声编解码器用于便携式音频应用
| 型号： | WM8750L |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | STEREO CODEC FOR PORTABLE AUDIO APPLICATIONS |
| 文件： | 总56页 (文件大小：658K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8750L
Stereo CODEC for Portable Audio Applications
DESCRIPTION
FEATURES
•
•
•
DAC SNR 98dB (‘A’ weighted), THD -95B at 48kHz, 3.3V
ADC SNR 95dB (‘A’ weighted), THD -90dB at 48kHz, 3.3V
Complete Stereo / Mono Microphone Interface
The WM8750L is a low power, high quality stereo codec
designed for portable digital audio applications.
The device integrates complete interfaces to stereo or mono
microphones and a stereo headphone. External component
requirements are drastically reduced as no separate
microphone or headphone amplifiers are required.
Advanced on-chip digital signal processing performs
graphic equaliser, 3-D sound enhancement and automatic
level control for the microphone or line input.
-
Programmable ALC / Noise Gate
•
•
On-chip 400mW BTL Speaker Driver (mono)
On-chip Headphone Driver
-
-
-
>40mW output power on 16Ω / 3.3V
THD –80dB at 20mW, SNR 90dB with 16Ω load
No DC blocking capacitors required (capless mode)
•
•
•
Separately mixed mono output
Digital Graphic Equaliser
Low Power
The WM8750L can operate as a master or a slave, with
various master clock frequencies including 12 or 24MHz for
USB devices, or standard 256fs rates like 12.288MHz and
24.576MHz. Different audio sample rates such as 96kHz,
48kHz, 44.1kHz are generated directly from the master
clock without the need for an external PLL.
-
-
7mW stereo playback (1.8V / 1.5V supplies)
14mW record & playback (1.8V / 1.5V supplies)
•
Low Supply Voltages
-
-
-
Analogue 1.8V to 3.6V
Digital core: 1.42V to 3.6V
Digital I/O: 1.8V to 3.6V
•
•
256fs / 384fs or USB master clock rates: 12MHz, 24MHz
Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48,
88.2, 96kHz generated internally from master clock
5x5x0.9mm QFN package
The WM8750L operates at supply voltages down to 1.8V,
although the digital core can operate at voltages down to
1.42V to save power, and the maximum for all supplies is
3.6 Volts. Different sections of the chip can also be powered
down under software control.
•
APPLICATIONS
The WM8750L is supplied in a very small and thin 5x5mm
QFN package, ideal for use in hand-held and portable
systems.
•
•
•
•
MP3 Player / Recorder
AAC/WMA/Multi-Format Player / Recorder
Minidisc Player / Recorder
Portable Digital Music Systems
BLOCK DIAGRAM
DGND
DCVDD
DBVDD
HPGND
HPVDD
OUT3SW
LMIXSEL
M
U
X
VREF
ROUT1
M
U
X
-1
OUT3
MONOOUT
LEFT
MIXER
LI2LO
DC MEASUREMENT
WM8750L
LD2LO
RD2LO
LD2MO
RD2MO
LD2RO
RD2RO
LINPUT1
LINPUT2
LINPUT3
LOUT1
M
U
X
PGA
+ MIC
BOOST
LOUT1VOL
MONOVOL
ROUT1VOL
RI2LO
LI2MO
DIGITAL
ADC
ADC
DAC
DAC
FILTERS
DIGITAL
FILTERS
MONO
MIXER
LINSEL
DIFF.
INPUT
L1-R1 OR
L2-R2
VOLUME
MONOOUT
(phone TX)
ANALOGUE
MONO MIX
GRAPHIC
DIGITAL
EQUALISER
MONO MIX
BASS
RINSEL
RI2MO
LI2RO
3D
BOOST
RINPUT3/
HPDETECT
RIGHT
MIXER
ENHANCE
M
U
X
PGA
+ MIC
BOOST
RINPUT2
RINPUT1
ROUT1
DC MEASUREMENT
RI2RO
M
U
X
LOUT2
ROUT2
RMIXSEL
L - (-R)
= L+R
LOUT2VOL
ROUT2VOL
ROUT2
INV
-1
MICBIAS
AUDIO
INTERFACE
CLOCK
CIRCUITRY
CONTROL
INTERFACE
50K
50K
Product Preview, May 2003, Rev 1.77
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
Copyright 2003 Wolfson Microelectronics plc
WM8750L
Product Preview
TABLE OF CONTENTS
DESCRIPTION......................................................................................................1
FEATURES ...........................................................................................................1
APPLICATIONS....................................................................................................1
BLOCK DIAGRAM................................................................................................1
PIN CONFIGURATION .........................................................................................4
ORDERING INFORMATION.................................................................................4
PIN DESCRIPTION...............................................................................................4
ABSOLUTE MAXIMUM RATINGS........................................................................5
RECOMMENDED OPERATION CONDITIONS....................................................5
ELECTRICAL CHARACTERISTICS.....................................................................6
HEADPHONE / SPEAKER OUTPUT THD VERSUS POWER......................................8
POWER CONSUMPTION...................................................................................11
SIGNAL TIMING REQUIREMENTS....................................................................12
SYSTEM CLOCK TIMING ..........................................................................................12
AUDIO INTERFACE TIMING – MASTER MODE........................................................12
AUDIO INTERFACE TIMING – SLAVE MODE...........................................................13
DEVICE DESCRIPTION......................................................................................16
INTRODUCTION ........................................................................................................16
INPUT SIGNAL PATH ................................................................................................16
AUTOMATIC LEVEL CONTROL (ALC) ......................................................................22
3D STEREO ENHANCEMENT ...................................................................................25
OUTPUT SIGNAL PATH.............................................................................................26
ANALOGUE OUTPUTS..............................................................................................31
ENABLING THE OUTPUTS........................................................................................33
HEADPHONE SWITCH..............................................................................................33
THERMAL SHUTDOWN.............................................................................................35
HEADPHONE OUTPUT..............................................................................................35
DIGITAL AUDIO INTERFACE ....................................................................................36
PP Rev 1.77 May 2003
ꢀꢁ
2
Product Preview
WM8750L
AUDIO INTERFACE CONTROL.................................................................................39
MASTER CLOCK AND AUDIO SAMPLE RATES.......................................................40
CONTROL INTERFACE .............................................................................................42
POWER SUPPLIES....................................................................................................43
POWER MANAGEMENT............................................................................................44
REGISTER MAP .................................................................................................46
DIGITAL FILTER CHARACTERISTICS..............................................................47
TERMINOLOGY .........................................................................................................47
DAC FILTER RESPONSES................................................................................48
ADC FILTER RESPONSES................................................................................49
DE-EMPHASIS FILTER RESPONSES...............................................................50
HIGHPASS FILTER ............................................................................................51
APPLICATIONS INFORMATION........................................................................52
RECOMMENDED EXTERNAL COMPONENTS .........................................................52
LINE INPUT CONFIGURATION .................................................................................53
MICROPHONE INPUT CONFIGURATION.................................................................53
MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS.......................................54
POWER MANAGEMENT EXAMPLES........................................................................54
PACKAGE DIMENSIONS...................................................................................55
IMPORTANT NOTICE........................................................................................ 54
ADDRESS: .................................................................................................................56
PP Rev 1.77 May 2003
ꢀ
3
WM8750L
Product Preview
PIN CONFIGURATION
ORDERING INFORMATION
ORDER CODE
TEMPERATURE
RANGE
PACKAGE
WM8750LEFL
-25°C to +85°C
32-pin QFN
(5x5x0.9mm)
24 23 22 21 20 19 18 17
25
16
15
14
LOUT2
ROUT2
HPGND
RINPUT2
WM8750LSEFL
WM8750LEFL/R
WM8750LSEFL/R
-25°C to +85°C
32-pin QFN
(5x5x0.9mm)
(lead free)
26
LINPUT2
27
RINPUT1
28
29
30
31
13 LOUT1
LINPUT1
MODE
ROUT1
12
11
10
9
-25°C to +85°C
-25°C to +85°C
32-pin QFN
(5x5x0.9mm)
(tape and reel)
CSB
OUT3
MONOOUT
SDIN
SCLK 32
ADCLRC
32-pin QFN
(5x5x0.9mm)
(lead free, tape and
reel)
1
2
3
4
5
6
7
8
Note:
Reel quantity = 3500
PIN DESCRIPTION
PIN #
NAME
TYPE
DESCRIPTION
1
MCLK
Digital Input
Master Clock
2
DCVDD
DBVDD
DGND
Supply
Digital Core Supply
3
Supply
Digital Buffer (I/O) Supply
4
Supply
Digital Ground (return path for both DCVDD and DBVDD)
Audio Interface Bit Clock
5
BCLK
Digital Input / Output
Digital Input
6
DACDAT
DACLRC
ADCDAT
ADCLRC
MONOOUT
OUT3
DAC Digital Audio Data
7
Digital Input / Output
Digital Output
Digital Input / Output
Analogue Output
Analogue Output
Analogue Output
Analogue Output
Supply
Audio Interface Left / Right Clock/Clock Out
ADC Digital Audio Data
8
9
Audio Interface Left / Right Clock
10
11
12
13
14
15
16
17
Mono Output
Analogue Output 3 (can be used as Headphone Pseudo Ground)
Right Output 1 (Line or Headphone)
Left Output 1 (Line or Headphone)
ROUT1
LOUT1
HPGND
ROUT2
LOUT2
Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2)
Right Output 1 (Line or Headphone or Speaker)
Left Output 1 (Line or Headphone or Speaker)
Analogue Output
Analogue Output
Supply
HPVDD
Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2,
MONOUT)
18
19
20
21
22
23
AVDD
AGND
VREF
Supply
Analogue Supply
Supply
Analogue Ground (return path for both AVDD and MVDD)
Reference Voltage Decoupling Capacitor
Midrail Voltage Decoupling Capacitor
Microphone Bias
Analogue Output
Analogue Output
Analogue Output
Analogue Input
VMID
MICBIAS
RINPUT3 /
Right Channel Input 3 or Headphone Plug-in Detection
HPDETECT
24
25
26
27
28
29
30
31
32
LINPUT3
RINPUT2
LINPUT2
RINPUT1
LINPUT1
MODE
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Digital Input
Left Channel Input 3
Right Channel Input 2
Left Channel Input 2
Right Channel Input 1
Left Channel Input 1
Control Interface Selection
Chip Select / Device Address Selection
Control Interface Data Input / 2-wire Acknowledge output
Control Interface Clock Input
CSB
Digital Input
SDIN
Digital Input/Output
Digital Input
SCLK
PP Rev 1.77 May 2003
4
ꢀꢁ
Product Preview
WM8750L
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
The WM8750L has been classified as MSL1, which has an unlimited floor life at <30oC / 85% Relative Humidity and therefore will
not be supplied in moisture barrier bags.
CONDITION
MIN
-0.3V
MAX
+3.63V
Supply voltages
Voltage range digital inputs
Voltage range analogue inputs
DGND -0.3V
AGND -0.3V
-25°C
DBVDD +0.3V
AVDD +0.3V
+85°C
Operating temperature range, TA
Storage temperature prior to soldering
Storage temperature after soldering
Package body temperature (soldering 10 seconds)
Package body temperature (soldering 2 minutes)
Notes
30°C max / 85% RH max
-65°C
+150°C
+260°C
+183°C
1. Analogue and digital grounds must always be within 0.3V of each other.
2. All digital and analogue supplies are completely independent from each other.
3. DCVDD must be less than or equal to AVDD & DBVDD.
RECOMMENDED OPERATION CONDITIONS
PARAMETER
SYMBOL
DCVDD
MIN
1.42
1.8
TYP
MAX
3.6
UNIT
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supplies range
Ground
2.0
2.0
2.0
0
V
V
V
V
DBVDD
3.6
AVDD, HPVDD
DGND,AGND, HPGND
1.8
3.6
PP Rev 1.77 May 2003
5
ꢀ
WM8750L
Product Preview
ELECTRICAL CHARACTERISTICS
Test Conditions
DCVDD = 1.5V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio
data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V rms
kΩ
Analogue Inputs (LINPUT1, RINPUT1, LINPUT2, RINPUT2, LINPUT3, RINPUT3) to ADC out
Full Scale Input Signal Level
(for ADC 0dB Input at 0dB Gain)
Input Resistance
VINFS
AVDD = 3.3V
AVDD = 1.8V
1.0
0.545
20
Selected for ADC,
PGA gain = 0dB
Selected for ADC,
PGA gain = +30dB
Selected for mixer
Input unused
12
1
1.5
TBD
TBD
10
Input Capacitance
Signal to Noise Ratio
(A-weighted)
pF
dB
SNR
THD
AVDD = 3.3V
AVDD = 1.8V
-60dBFs
90
90
95
90
Dynamic Range
95
dB
dB
%
Total Harmonic Distortion
-0.5dBFs input,
AVDD = 3.3V
-0.5dBFs input,
AVDD = 1.8V
1kHz signal
-90
-84
0.006
-74
0.003
-84
0.006
85
0.02
ADC Channel Separation
Channel Matching
dB
dB
1kHz signal
0.2
Programmable Gain Amplifier (PGA)
Programmable Gain
-17.25
0.5
30
dB
dB
dB
Programmable Gain Step Size
Channel Matching
Monotonic
0.75
0.2
1.0
1kHz signal, 0dB Fs input
Automatic Level Control (ALC)
Target Record Level
-28.5
-6
dBFS
ms
Gain Hold Time
tHLD
tDCY
tATK
0, 2.67, 5.33, 10.67, … , 43691
(time doubles with each step)
24, 48, 96, … , 2458
MCLK = 12.288MHz
Gain Ramp-Up (Decay) Time
Gain Ramp-Down (Attack) Time
ms
ms
(time doubles with each step)
6, 12, 24, … , 6140
(time doubles with each step)
DAC to Line-Out (L/ROUT2 with 10k / 50pF load)
Signal to Noise Ratio
(A-weighted)
SNR
AVDD=3.3V
AVDD=1.8V
AVDD=3.3V
AVDD=1.8V
1kHz signal
TBD
98
95
dB
dB
dB
Total Harmonic Distortion
THD
-95
-90
90
Channel Separation
Analogue Outputs (LOUT1/2, ROUT1/2, MONOOUT)
0dB Full scale output voltage
AVDD/3.3
Vrms
dB
Programmable Gain
1kHz signal
Monotonic
-67
80
+6
Programmable Gain Steps
80
85
90
steps
dB
Mute attenuation
1kHz, full scale signal
Channel Separation
dB
PP Rev 1.77 May 2003
6
ꢀꢁ
Product Preview
WM8750L
Test Conditions
DCVDD = 1.5V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio
data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Headphone Output (LOUT1/ROUT1, using capacitors)
Output Power per channel
Total Harmonic Distortion
PO
Output power is very closely correlated with THD; see below.
THD
HPVDD=1.8V, RL=32Ω
0.013
-78
%
dB
PO=5mW
HPVDD=1.8V, RL=16Ω
PO=5mW
0.013
-78
HPVDD=3.3V, RL=32Ω,
0.01
-80
0.01
-80
90
PO=20mW
HPVDD=3.3V, RL=16Ω,
PO=20mW
Signal to Noise Ratio
(A-weighted)
SNR
HPVDD = 3.3V
HPVDD = 1.8V
dB
90
Speaker Output (LOUT2/ROUT2 with 8 bridge tied load, ROUT2INV=1)
Output Power
PO
Output power is very closely correlated with THD; see below.
Total Harmonic Distortion
THD
Po=180mW, RL=8Ω,
-50
0.3
-40
1
dB
%
HPVDD=3.3V
Po=400mW, RL=8Ω
HPVDD=3.3V
Signal to Noise Ratio
(A-weighted)
SNR
90
90
dB
HPVDD=3.3V, RL=8Ω
HPVDD=2.5V, RL=8Ω
Analogue Reference Levels
Midrail Reference Voltage
Potential Divider Resistance
Buffered Reference Voltage
Microphone Bias
VMID
RVMID
VREF
–3%
–3%
–3%
AVDD/2
50
+3%
+3%
V
kΩ
V
AVDD/2
Bias Voltage
VMICBIAS
IMICBIAS
Vn
0.9×AVDD
+ 3%
3
V
Bias Current Source
Output Noise Voltage
Digital Input / Output
Input HIGH Level
mA
1K to 20kHz
15
nV/√Hz
VIH
VIL
0.7×DBVDD
0.9×DBVDD
V
V
V
V
Input LOW Level
0.3×DBVDD
0.1×DBVDD
Output HIGH Level
Output LOW Level
VOH
VOL
IOL=1mA
IOH-1mA
HPDETECT (pin 23)
Input HIGH Level
VIH
VIL
0.7×AVDD
V
V
Input LOW Level
0.3×AVDD
PP Rev 1.77 May 2003
7
ꢀ
WM8750L
Product Preview
OUTPUT PGA’S LINEARITY
10.000
0.000
Output PGA Gains
-10.000
-20.000
-30.000
-40.000
-50.000
-60.000
-70.000
LOUT1
ROUT1
LOUT2
ROUT2
MONOOUT
40
50
60
70
80
90
100
110
120
130
XXXVOL Register Setting (binary)
2.000
1.750
1.500
1.250
1.000
0.750
0.500
0.250
0.000
Output PGA Gain Step Size
LOUT1
ROUT1
LOUT2
ROUT2
MONOOUT
40
50
60
70
80
90
100
110
120
130
XXXVOL Register Setting (binary)
PP Rev 1.77 May 2003
8
ꢀꢁ
Product Preview
WM8750L
HEADPHONE OUTPUT THD VERSUS POWER
0
Headphone Power vs THD+N (32Ohm load)
-20
-40
AVDD=1.8V
AVDD=1.8V, capless
AVDD=3.3V
-60
AVDD=3.3V, capless
-80
-100
0
5
10
15
20
25
30
Power (mW)
0
-20
Headphone Power vs THD+N (16Ohm load)
AVDD=1.8V
-40
AVDD=1.8V, capless
AVDD=3.3V
-60
AVDD=3.3V, capless
-80
-100
0
10
20
30
40
50
60
Power (mW)
PP Rev 1.77 May 2003
ꢀ
9
WM8750L
Product Preview
SPEAKER OUTPUT THD VERSUS POWER
-10
-20
-30
-40
-50
AVDD=1.8V
AVDD=2.5V
AVDD=3.3V
Speaker Power vs THD+N (8Ohm BTL load)
-60
-70
0
100
200
300
400
500
Power (mW)
10
Speaker Power vs THD+N (8 Ohm BTL load)
8
6
4
2
0
AVDD=1.8V
AVDD=2.5V
AVDD=3.3V
0
100
200
300
400
500
Power (mW)
PP Rev 1.77 May 2003
10
ꢀꢁ
Product Preview
WM8750L
POWER CONSUMPTION
The power consumption of the WM8750L depends on the following factors.
•
Supply voltages: Reducing the supply voltages also reduces supply currents, and therefore results in significant power
savings, especially in the digital sections of the WM8750L.
•
Operating mode: Significant power savings can be achieved by always disabling parts of the WM8750L that are not
used (e.g. mic pre-amps, unused outputs, DAC, ADC, etc.)
Control Register
R25 (19h)
R26 (1Ah)
R24 R23
Other settings
AVDD
DCVDD
DBVDD
HPVDD
Tot. Power
Bit
V
I (mA)
V
I (mA)
V
I (mA)
V
I (mA)
mW
OFF
00
10
01
01
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
0
0
0
0
1
1
0
0
1
0
0
0
1
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
11
01
00
11
01
00
11
01
00
11
01
00
11
01
00
Clocks stopped
3.3 0.0016 3.3 0.0190 3.3 0.0080 3.3 0.0002
2.5 0.0008 2.5 0.0170 2.5 0.0050 2.5 0.0000
1.8 0.0005 1.5 0.0120 1.5 0.0029 1.8 0.0000
3.3 0.3900 3.3 0.0390 3.3 0.0080 3.3 0.0000
2.5 0.2880 2.5 0.0170 2.5 0.0050 2.5 0.0000
1.8 0.1970 1.5 0.0120 1.5 0.0030 1.8 0.0000
3.3 3.7310 3.3 5.6600 3.3 0.3000 3.3 0.2370
2.5 2.6940 2.5 3.8600 2.5 0.2200 2.5 0.2100
1.8 1.8820 1.5 2.1400 1.5 0.1240 1.8 0.1500
3.3 3.5170 3.3 4.6470 3.3 0.3000 3.3 0.9500
2.5 2.5760 2.5 3.2030 2.5 0.2200 2.5 0.6480
1.8 1.7760 1.5 1.7590 1.5 0.1240 1.8 0.4130
3.3 3.7260 3.3 5.6700 3.3 0.3000 3.3 0.9530
2.5 2.7530 2.5 3.9250 2.5 0.2200 2.5 0.6570
1.8 1.8900 1.5 2.1410 1.5 0.1240 1.8 0.4150
0.0950
0.0570
0.0233
1.4421
0.7750
0.3771
32.7624
17.4600
7.0536
31.0662
16.6175
6.7647
35.1417
18.8875
7.5465
36.4650
19.4825
7.8993
33.3696
18.1175
7.2663
9.3126
4.9850
2.4360
7.7121
4.2425
2.1156
9.9330
5.4900
2.7492
51.3579
30.5550
15.7575
37.3593
20.5925
9.5295
38.9796
21.9675
10.2333
39.9696
22.6750
10.5570
77.2563
44.7800
19.8597
59.5782
33.2325
13.9962
Standby
(500 KOhm VMID string)
Interface Stopped
Playback to Line-out
Playback to Line-out
(64x oversampling mode)
Playback to 16 Ohm Headphone 01
Playback to 16 Ohm Headphone 01
(capless mode using OUT3)
11 R24, OUT3SW=00 3.3 3.7060 3.3 5.6400 3.3 0.3000 3.3 1.4040
01
00
2.5 2.7130 2.5 3.9000 2.5 0.2200 2.5 0.9600
1.8 1.8870 1.5 2.1410 1.5 0.1240 1.8 0.6140
Playback to 8 Ohm BTL Speaker 01
11 R24, ROUT2INV=1 3.3 3.8820 3.3 5.6470 3.3 0.3000 3.3 0.2830
01
00
11
01
00
11
2.5 2.8780 2.5 3.9390 2.5 0.2200 2.5 0.2100
1.8 1.9800 1.5 2.1630 1.5 0.1240 1.8 0.1510
3.3 1.8400 3.3 0.0200 3.3 0.0080 3.3 0.9540
2.5 1.3300 2.5 0.0190 2.5 0.0050 2.5 0.6400
1.8 0.9300 1.5 0.0130 1.5 0.0030 1.8 0.4100
3.3 1.9780 3.3 0.0200 3.3 0.0080 3.3 0.3310
Headphone Amp
(line-in to 16 Ohm headphone)
01
01
01
01
01
Clocks Stopped
Speaker Amp
(line-in to 8 Ohm speaker)
Clocks Stopped
01 R24, ROUT2INV=1 2.5 1.4300 2.5 0.0190 2.5 0.0050 2.5 0.2430
00
11
01
00
11
01
00
11
01
00
1.8 0.9860 1.5 0.0130 1.5 0.0030 1.8 0.1760
3.3 2.5230 3.3 0.0370 3.3 0.0080 3.3 0.4420
2.5 1.8520 2.5 0.0190 2.5 0.0050 2.5 0.3200
1.8 1.2900 1.5 0.0130 1.5 0.0030 1.8 0.2240
3.3 8.6600 3.3 6.5700 3.3 0.3330 3.3 0.0000
2.5 7.7100 2.5 4.2800 2.5 0.2320 2.5 0.0000
1.8 6.8000 1.5 2.2100 1.5 0.1350 1.8 0.0000
3.3 5.0720 3.3 5.9100 3.3 0.3390 3.3 0.0000
2.5 4.2550 2.5 3.7500 2.5 0.2320 2.5 0.0000
1.8 3.5900 1.5 1.9100 1.5 0.1350 1.8 0.0000
Phone Call
Clocks Stopped
(mono line-in to headphone,
mic to MONOOUT)
Record from Line-in
Record from Line-in
(64x oversampling mode)
Record from mono microphone 01
11 R32, LMICBOOST=11; 3.3 4.9330 3.3 6.5400 3.3 0.3390 3.3 0.0000
01
00
R23, DATSEL=01
2.5 4.2970 2.5 4.2500 2.5 0.2400 2.5 0.0000
1.8 3.7210 1.5 2.2200 1.5 0.1370 1.8 0.0000
Record from mono microphone 01
(differential)
11 R32, LMICBOOST=11; 3.3 5.2900 3.3 6.5000 3.3 0.3220 3.3 0.0000
01
00
11
01
00
11
01
00
R23, DATSEL=01; 2.5 4.5600 2.5 4.2700 2.5 0.2400 2.5 0.0000
R32, LINSEL=11
1.8 3.9000 1.5 2.2200 1.5 0.1380 1.8 0.0000
3.3 11.927 3.3 10.870 3.3 0.3320 3.3 0.2820
2.5 10.112 2.5 7.3600 2.5 0.2340 2.5 0.2060
1.8 7.3910 1.5 4.0610 1.5 0.1320 1.8 0.1480
3.3 8.1090 3.3 9.3300 3.3 0.3330 3.3 0.2820
2.5 6.5500 2.5 6.3020 2.5 0.2340 2.5 0.2070
1.8 4.7000 1.5 3.3800 1.5 0.1320 1.8 0.1490
Stereo Record & Playback
01
01
Stereo Record & Playback
(64x oversampling mode)
Table 1 Supply Current Consumption
Notes:
1. All figures are at TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 12.288 MHz (256fs), with zero signal (quiescent)
2. The power dissipated in the headphone or speaker is not included in the above table.
PP Rev 1.77 May 2003
11
ꢀ
WM8750L
Product Preview
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
CLKDIV2=0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK duty cycle
TMCLKL
TMCLKH
TMCLKY
TMCLKDS
21
21
ns
ns
ns
54
60:40
40:60
Test Conditions
CLKDIV2=1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
TMCLKL
TMCLKH
TMCLKY
10
10
27
ns
ns
ns
AUDIO INTERFACE TIMING – MASTER MODE
BCLK
(Output)
tDL
ADCLRC/
DACLRC
(Outputs)
tDDA
ADCDAT
DACDAT
tDST
tDHT
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
PP Rev 1.77 May 2003
12
ꢀꢁ
Product Preview
WM8750L
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC/DACLRC propagation delay from BCLK falling edge
ADCDAT propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
tDL
tDDA
tDST
10
10
ns
ns
ns
ns
10
10
tDHT
AUDIO INTERFACE TIMING – SLAVE MODE
tBCH
tBCL
BCLK
tBCY
DACLRC/
ADCLRC
tLRSU
tDS
tLRH
DACDAT
tDD
tDH
ADCDAT
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
50
20
20
10
10
10
ns
ns
ns
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
ADCLRC/DACLRC set-up time to BCLK rising edge
ADCLRC/DACLRC hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
tDD
10
Note:
BCLK period should always be greater than or equal to MCLK period.
PP Rev 1.77 May 2003
13
ꢀ
WM8750L
Product Preview
CONTROL INTERFACE TIMING – 3-WIRE MODE
tCSL
tCSH
CSB
tCSS
tSCY
tSCS
tSCH
tSCL
SCLK
SDIN
LSB
tDSU
tDHO
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
tSCS
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
tps
80
200
80
80
40
40
40
40
40
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes that will be suppressed
PP Rev 1.77 May 2003
14
ꢀꢁ
Product Preview
WM8750L
CONTROL INTERFACE TIMING – 2-WIRE MODE
t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t7
t1
t9
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
0
400
kHz
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
t8
t9
tps
600
1.3
600
600
100
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
300
300
Setup Time (Stop Condition)
Data Hold Time
600
0
900
5
Pulse width of spikes that will be suppressed
PP Rev 1.77 May 2003
15
ꢀ
WM8750L
Product Preview
DEVICE DESCRIPTION
INTRODUCTION
The WM8750L is a low power audio codec offering a combination of high quality audio, advanced
features, low power and small size. These characteristics make it ideal for portable digital audio
applications such as MP3 and minidisk player / recorders.
The device includes three stereo analogue inputs that can be switched internally. Each can be used
as either a line level input, as a microphone input or be selected as a mono differential input. A
programmable gain amplifier with automatic level control (ALC) keeps the recording volume constant.
The on-chip stereo ADC and DAC are of a high quality using a multi-bit, low-order oversampling
architecture to deliver optimum performance with low power consumption.
The DAC output signal first enters an analogue mixer where an analogue input and/or the post-ALC
signal can be added to it. This mix is available on line and headphone outputs.
The WM8750L has a configurable digital audio interface where ADC data can be read and digital
audio playback data fed to the DAC. It supports a number of audio data formats including I2S, DSP
Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left
justified and MSB-First, right justified, and can operate in master or slave modes.
The WM8750L uses a unique clocking scheme that can generate many commonly used audio
sample rates from either a 12.00MHz USB clock or an industry standard 256/384 fs clock. This
feature eliminates the common requirement for an external phase-locked loop (PLL) in applications
where the master clock is not an integer multiple of the sample rate. Sample rates of 8kHz,
11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz and 96kHz can be
generated. The digital filters used for recording and playback are optimised for each sampling rate
used.
To allow full software control over all its features, the WM8750L offers a choice of 2 or 3 wire MPU
control interface. It is fully compatible and an ideal partner for a wide range of industry standard
microprocessors, controllers and DSPs.
The design of the WM8750L has given much attention to power consumption without compromising
performance. It operates at very low voltages, and includes the ability to power off parts of the
circuitry under software control, including standby and power off modes.
INPUT SIGNAL PATH
The input signal path for each channel consists of a switch to select between three analogue inputs,
followed by a PGA (programmable gain amplifier) and an optional microphone gain boost. A
differential input of either (LINPUT1 – RINPUT1) or (LINPUT2 – RINPUT2) may also be selected.
The gain of the PGA can be controlled either by the user or by the on-chip ALC function (see
Automatic Level Control).
The signal then enters an ADC where it is digitised. Alternatively, the two channels can also be
mixed in the analogue domain and digitised in one ADC while the other ADC is switched off. The
mono-mix signal appears on both digital output channels.
SIGNAL INPUTS
The WM8750L has three sets of high impedance, low capacitance AC coupled analogue inputs,
LINPUT1/RINPUT1, LINPUT2/RINPUT2 and LINPUT3/RINPUT3. The LINSEL and RINSEL control
bits select between them. These inputs can be configured as microphone or line inputs by enabling
or disabling the microphone gain boost. A differential input, either LINPUT1-RINPUT1 or LINPUT2-
RINPUT may also be selected using L/RINSEL and DS (refer to Table 4).
The signal inputs are biased internally to the reference voltage VREF. Whenever the line inputs are
muted or the device placed into standby mode, the inputs are kept biased to VREF using special
anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when changing
inputs.
PP Rev 1.77 May 2003
16
ꢀꢁ
Product Preview
WM8750L
DC MEASUREMENT
For DC measurements (for example, battery voltage monitoring), the input signal at the LINPUT1
and/or RINPUT1 pins can be taken directly into the respective ADC, bypassing both PGA and
microphone boost. The ADC output then becomes unsigned relative to AVDD, instead of being a
signed (two’s complement) number relative to VREF. Setting L/RDCM will override L/RINSEL. The
input range for dc measurement is AGND to AVDD.
REGISTER
ADDRESS
BIT
LABEL
LINSEL
DEFAULT
DESCRIPTION
R32 (20h)
7:6
00
Left Channel Input Select
00 = LINPUT1
ADC Signal
Path Control
(Left)
01 = LINPUT2
10 = LINPUT3
11 = Differential
5:4
7:6
5:4
LMICBOOST
RINSEL
00
00
00
Left Channel Microphone Gain Boost
00 = Boost off (bypassed)
01 = 13dB boost
10 = 20dB boost
11 = 29dB boost
R33 (21h)
Right Channel Input Select
00 = RINPUT1
ADC Signal
Path Control
(Right)
01 = RINPUT2
10 = RINPUT3
11 = Differential
RMICBOOST
Right Channel Microphone Gain Boost
00 = Boost off (bypassed)
01 = 13dB boost
10 = 20dB boost
11 = 29dB boost
Table 2 Input Software Control
REGISTER
ADDRESS
BIT
LABEL
RDCM
DEFAULT
DESCRIPTION
R31 (1Fh)
ADC input Mode
5
0
Right Channel DC Measurement
0 = Normal Operation, PGA Enabled
1 = Measure DC level on RINPUT1
Left Channel DC Measurement
4
LDCM
0
0 = Normal Operation, PGA Enabled
1 = Measure DC level on LINPUT1
Table 3 DC Measurement Select
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R31 (1Fh)
ADC Input Mode
8
DS
0
Differential input select
0: LINPUT1 - RINPUT1
1: LINPUT2 – RINPUT2
Table 4 Differential Input Select
PP Rev 1.77 May 2003
17
ꢀ
WM8750L
Product Preview
MONO MIXING
The stereo ADC can operate as a stereo or mono device, or the two channels can be mixed to mono,
either in the analogue domain (i.e. before the ADC) or in the digital domain (after the ADC).
MONOMIX selects the mode of operation. For analogue mono mix either the left or right channel
ADC can be used, allowing the unused ADC to be powered off or used for a dc measurement
conversion. The user also has the flexibility to select the data output from the audio interface using
DATSEL. The default is for left and right channel ADC data to be output, but the interface may also
be configured so that e.g. left channel ADC data is output as both left and right data for when an
analogue mono mix is selected.
Note:
If DC measurement is selected this overrides the MONOMIX selection.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R31 (1Fh)
7:6
MONOMIX
[1:0]
00
00: Stereo
ADC input
Mode
01: Analogue Mono Mix (using left ADC)
10: Analogue Mono Mix (using right ADC)
11: Digital Mono Mix
Table 5 Mono Mixing
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R23 (17h)
3:2
DATSEL
[1:0]
00
00: left data=left ADC; right data =right ADC
01: left data =left ADC; right data = left ADC
Additional
Control (1)
10: left data = right ADC; right data =right
ADC
11: left data = right ADC; right data = left
ADC
Table 6 ADC Data Output Configuration
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type
microphones and the associated external resistor biasing network. Refer to the Applications
Information section for recommended external components. The output can be enabled or disables
using the MICB control bit (see also the “Power Management” section).
REGISTER
ADDRESS
BIT
LABEL DEFAULT
MICB
DESCRIPTION
R25 (19h)
1
0
Microphone Bias Enable
Power
Management (1)
0 = OFF (high impedance output)
1 = ON
Table 7 Microphone Bias Control
The internal MICBIAS circuitry is shown below. Note that the is a maximum source current capability
for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the
MICBIAS current to 3mA.
VMID
MICB
MICBIAS
= 1.8 x VMID
= 0.9 X AVDD
internal
resistor
internal
resistor
AGND
Figure 6 Microphone Bias Schematic
PGA CONTROL
PP Rev 1.77 May 2003
18
ꢀꢁ
Product Preview
WM8750L
The PGA matches the input signal level to the ADC input range. The PGA gain is logarithmically
adjustable from +30dB to –17.25dB in 0.75dB steps. Each PGA can be controlled either by the user
or by the ALC function (see Automatic Level Control). When ALC is enabled for one or both
channels, then writing to the corresponding PGA control register has no effect.
The gain is independently adjustable on both Right and Left Line Inputs. Additionally, by controlling
the register bits LIVU and RIVU, the left and right gain settings can be simultaneously updated.
Setting the LZCEN and RZCEN bits enables a zero-cross detector which ensures that PGA gain
changes only occur when the signal is at zero, eliminating any zipper noise. If zero cross is enabled
a timeout is also available to update the gain if a zero cross does not occur. This function may be
enabled by setting TOEN in register R23 (17h).
The inputs can also be muted in the analogue domain under software control. The software control
registers are shown in Table 8
REGISTER
ADDRESS
BIT
LABEL
LIVU
DEFAULT
DESCRIPTION
R0 (00h)
Left Channel
PGA
8
0
Left Volume Update
0 = Store LINVOL in intermediate
latch (no gain change)
1 = Update left and right channel
gains (left = LINVOL, right =
intermediate latch)
7
6
LINMUTE
LZCEN
1
0
Left Channel Input Analogue Mute
1 = Enable Mute
0 = Disable Mute
Note: LIVU must be set to un-mute.
Left Channel Zero Cross Detector
1 = Change gain on zero cross only
0 = Change gain immediately
Left Channel Input Volume Control
111111 = +30dB
5:0
LINVOL
[5:0]
010111
( 0dB )
111110 = +29.25dB
. . 0.75dB steps down to
000000 = -17.25dB
R1 (01h)
Right Channel
PGA
8
RIVU
0
Right Volume Update
0 = Store RINVOL in intermediate
latch (no gain change)
1 = Update left and right channel
gains (right = RINVOL, left =
intermediate latch)
7
RINMUTE
RZCEN
1
0
Right Channel Input Analogue Mute
1 = Enable Mute
0 = Disable Mute
Note: RIVU must be set to un-mute.
Right Channel Zero Cross Detector
1 = Change gain on zero cross only
0 = Change gain immediately
Right Channel Input Volume Control
111111 = +30dB
6
5:0
RINVOL
[5:0]
010111
( 0dB )
111110 = +29.25dB
. . 0.75dB steps down to
000000 = -17.25dB
R23 (17h)
0
TOEN
0
Timeout Enable
Additional
Control (1)
0 : Timeout Disabled
1 : Timeout Enabled
Table 8 Input PGA Software Control
PP Rev 1.77 May 2003
19
ꢀ
WM8750L
Product Preview
ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8750L uses a multi-bit, oversampled sigma-delta ADC for each channel. The use of multi-bit
feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The
ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is
1.0 Volts r.m.s. Any voltage greater than full scale may overload the ADC and cause distortion.
ADC DIGITAL FILTER
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital
filter path is illustrated in Figure 7.
TO DIGITAL
AUDIO
INTERFACE
DIGITAL
HPF
DIGITAL
DECIMATOR
DIGITAL
FILTER
FROM ADC
ADCHPD
Figure 7 ADC Digital Filter
The ADC digital filters contain a digital high pass filter, selectable via software control. The high-pass
filter response is detailed in the Digital Filter Characteristics section. When the high-pass filter is
enabled the dc offset is continuously calculated and subtracted from the input signal. By setting
HPOR, the last calculated dc offset value is stored when the high-pass filter is disabled and will
continue to be subtracted from the input signal. If the DC offset is changed, the stored and
subtracted value will not change unless the high-pass filter is enabled. This feature can be used for
calibration purposes.
The output data format can be programmed by the user to accommodate stereo or monophonic
recording on both inputs. The polarity of the output signal can also be changed under software
control. The software control is shown in Table 9.
REGISTER
ADDRESS
BIT
6:5
LABEL
DEFAULT
00
DESCRIPTION
R5 (05h)
ADCPOL
00 = Polarity not inverted
01 = L polarity invert
ADC and DAC
Control
[1:0]
10 = R polarity invert
11 = L and R polarity invert
4
0
HPOR
0
0
Store dc offset when High Pass
Filter disabled
1 = store offset
0 = clear offset
ADCHPD
ADC High Pass Filter Enable
(Digital)
1 = Disable High Pass Filter
0 = Enable High Pass Filter
Table 9 ADC Signal Path Control
PP Rev 1.77 May 2003
20
ꢀꢁ
Product Preview
WM8750L
DIGITAL ADC VOLUME CONTROL
The output of the ADCs can be digitally amplified or attenuated over a range from –97dB to +30dB in
0.5dB steps. The volume of each channel can be controlled separately. The gain for a given eight-bit
code X is given by:
0.5 × (X-195) dB for 1 ≤ X ≤ 255;
MUTE for X = 0
The LAVU and RAVU control bits control the loading of digital volume control data. When LAVU or
RAVU are set to 0, the LADCVOL or RADCVOL control data will be loaded into the respective control
register, but will not actually change the digital gain setting. Both left and right gain settings are
updated when either LAVU or RAVU are set to 1. This makes it possible to update the gain of both
channels simultaneously.
REGISTER
ADDRESS
BIT
7:0
LABEL
DEFAULT
DESCRIPTION
R21 (15h)
LADCVOL
11000011
( 0dB )
Left ADC Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -97dB
Left ADC
Digital Volume
[7:0]
0000 0010 = -96.5dB
... 0.5dB steps up to
1111 1111 = +30dB
8
LAVU
0
Left ADC Volume Update
0 = Store LADCVOL in intermediate
latch (no gain change)
1 = Update left and right channel
gains (left = LADCVOL, right =
intermediate latch)
R22 (16h)
7:0
RADCVOL
[7:0]
11000011
( 0dB )
Right ADC Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -97dB
Right ADC
Digital Volume
0000 0010 = -96.5dB
... 0.5dB steps up to
1111 1111 = +30dB
8
RAVU
0
Right ADC Volume Update
0 = Store RADCVOL in intermediate
latch (no gain change)
1 = Update left and right channel
gains (left = intermediate latch, right
= RADCVOL)
Table 10 ADC Digital Volume Control
PP Rev 1.77 May 2003
21
ꢀ
WM8750L
Product Preview
AUTOMATIC LEVEL CONTROL (ALC)
The WM8750L has an automatic level control that aims to keep a constant recording volume
irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that
the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output
and changes the PGA gain if necessary. Note that when the ALC function is enabled, the settings of
registers 0 and 1 (LINVOL, LIVU, LIZC, RINVOL, RIVU and RIZC, but not LINMUTE and RINMUTE)
are ignored.
input
signal
PGA
gain
signal
after
ALC
ALC
target
level
hold decay
time time
attack
time
Figure 8 ALC Operation
The ALC function is enabled using the ALCSEL control bits. When enabled, the recording volume
can be programmed between –6dB and –28.5dB (relative to ADC full scale) using the ALCL register
bits. An upper limit for the PGA gain can be imposed by setting the MAXGAIN control bits.
HLD, DCY and ATK control the hold, decay and attack times, respectively:
Hold time is the time delay between the peak level detected being below target and the PGA gain
beginning to ramp up. It can be programmed in power-of-two (2n) steps, e.g. 2.67ms, 5.33ms,
10.67ms etc. up to 43.7s. Alternatively, the hold time can also be set to zero. The hold time only
applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is
above target.
Decay (Gain Ramp-Up) Time is the time that it takes for the PGA gain to ramp up across 90% of its
range (e.g. from –15B up to 27.75dB). The time it takes for the recording level to return to its target
value therefore depends on both the decay time and on the gain adjustment required. If the gain
adjustment is small, it will be shorter than the decay time. The decay time can be programmed in
power-of-two (2n) steps, from 24ms, 48ms, 96ms, etc. to 24.58s.
Attack (Gain Ramp-Down) Time is the time that it takes for the PGA gain to ramp down across 90%
of its range (e.g. from 27.75dB down to -15B gain). The time it takes for the recording level to return
to its target value therefore depends on both the attack time and on the gain adjustment required. If
the gain adjustment is small, it will be shorter than the attack time. The attack time can be
programmed in power-of-two (2n) steps, from 6ms, 12ms, 24ms, etc. to 6.14s.
When operating in stereo, the peak detector takes the maximum of left and right channel peak
values, and any new gain setting is applied to both left and right PGAs, so that the stereo image is
preserved. However, the ALC function can also be enabled on one channel only. In this case, only
one PGA is controlled by the ALC mechanism, while the other channel runs independently with its
PGA gain set through the control register.
When one ADC channel is unused or used for DC measurement, the peak detector disregards that
channel. The ALC function can also operate when the two ADC outputs are mixed to mono in the
digital domain, but not if they are mixed to mono in the analogue domain, before entering the ADCs.
PP Rev 1.77 May 2003
22
ꢀꢁ
Product Preview
WM8750L
REGISTER
ADDRESS
BIT
8:7
LABEL
ALCSEL
DEFAULT
DESCRIPTION
ALC function select
R17 (11h)
00
ALC Control 1
[1:0]
(OFF)
00 = ALC off (PGA gain set by register)
01 = Right channel only
10 = Left channel only
11 = Stereo (PGA registers unused)
Note: ensure that LINVOL and
RINVOL settings (reg. 0 and 1) are
the same before entering this mode.
6:4
3:0
MAXGAIN
[2:0]
111
(+30dB)
Set Maximum Gain of PGA
111 : +30dB
110 : +24dB
….(-6dB steps)
001 : -6dB
000 : -12dB
ALCL
[3:0]
1011
ALC target – sets signal level at ADC
input
(-12dB)
0000 = -28.5dB FS
0001 = -27.0dB FS
… (1.5dB steps)
1110 = -7.5dB FS
1111 = -6dB FS
R18 (12h)
7
ALCZC
0 (zero
cross
off)
ALC uses zero cross detection circuit.
ALC Control 2
3:0
HLD
[3:0]
0000
ALC hold time before gain is increased.
0000 = 0ms
(0ms)
0001 = 2.67ms
0010 = 5.33ms
… (time doubles with every step)
1111 = 43.691s
R19 (13h)
7:4
3:0
DCY
[3:0]
0011
ALC decay (gain ramp-up) time
0000 = 24ms
ALC Control 3
(192ms)
0001 = 48ms
0010 = 96ms
… (time doubles with every step)
1010 or higher = 24.58s
ALC attack (gain ramp-down) time
0000 = 6ms
ATK
[3:0]
0010
(24ms)
0001 = 12ms
0010 = 24ms
… (time doubles with every step)
1010 or higher = 6.14s
Table 11 ALC Control
PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a
limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is
ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below
87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.
Note:
If ATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to
prevent clipping when long attack times are used.
PP Rev 1.77 May 2003
23
ꢀ
WM8750L
Product Preview
NOISE GATE
When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise
pumping”, i.e. loud hissing noise during silence periods. The WM8750L has a noise gate function
that prevents noise pumping by comparing the signal level at the LINPUT1/2/3 and/or RINPUT1/2/3
pins against a noise gate threshold, NGTH. The noise gate cuts in when:
•
Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic Boost gain [dB]
This is equivalent to:
•
Signal level at input pin [dB] < NGTH [dB]
The ADC output can then either be muted or digitally attenuated by 18dB. Alternatively, the PGA gain
can be held constant (preventing it from ramping up as it normally would when the signal is quiet).
The table below summarises the noise gate control register. The NGTH control bits set the noise
gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 1.5dB steps.
Levels at the extremes of the range may cause inappropriate operation, so care should be taken with
set–up of the function. Note that the noise gate only works in conjunction with the ALC function, and
always operates on the same channel(s) as the ALC (left, right, both, or none).
REGISTER
ADDRESS
BIT
LABEL
NGTH
DEFAULT
DESCRIPTION
Noise gate threshold
R20 (14h)
7:3
00000
Noise Gate
Control
[4:0]
00000 -76.5dBfs
00001 -75dBfs
… 1.5 dB steps
11110 -31.5dBfs
11111 -30dBfs
2:1
0
NGG
[1:0]
00
0
Noise gate type
X0 = PGA gain held constant
01 = mute ADC output
11 = reserved (do not use this setting)
Noise gate function enable
1 = enable
NGAT
0 = disable
Table 12 Noise Gate Control
PP Rev 1.77 May 2003
24
ꢀꢁ
Product Preview
WM8750L
3D STEREO ENHANCEMENT
The WM8750L has a digital 3D enhancement option to artificially increase the separation between
the left and right channels. This effect can be used for recording or playback, but not for both
simultaneously. Selection of 3D for record or playback is controlled by register bit MODE3D.
Important:
Switching the 3D filter from record to playback or from playback to record may only be done
when ADC and DAC are disabled. The WM8750L control interface will only allow MODE3D to
be changed when ADC and DAC are disabled (i.e. bits ADCL, ADCR, DACL and DACR in reg.
26 / 1Ah are all zero).
The 3D enhancement function is activated by the 3DEN bit, and has two programmable parameters.
The 3DWIDTH setting controls the degree of stereo expansion. Additionally, one of four filter
characteristics can be selected for the 3D processing, using the 3DFILT control bits.
REGISTER
ADDRESS
BIT
LABEL
MODE3D
DEFAULT
DESCRIPTION
R16 (10h)
7
6
0
Playback/Record 3D select
0 = 3D selected for Record
1 = 3D selected for Playback
Upper Cut-off frequency
3D enhance
3DUC
3DLC
0
0 = High (2.2kHz at 48kHz
sampling)
1 = Low (1.5kHz at 48kHz sampling)
Lower Cut-off frequency
0 = Low (200Hz at 48kHz sampling)
1 = High (500Hz at 48kHz sampling)
Stereo depth
5
0
4:1
3DDEPTH
[3:0]
0000
0000: 0% (minimum 3D effect)
0001: 6.67%
....
1110: 93.3%
1111: 100% (maximum 3D effect)
3D function enable
0
3DEN
0
1: enabled
0: disabled
Table 13 3D Stereo Enhancement Function
When 3D enhancement is enabled (and/or the graphic equaliser for playback) it may be necessary to
attenuate the signal by 6dB to avoid limiting. This is a user selectable function, enabled by setting
ADCDIV2 for the record path and DACDIV2 for the playback path.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R5 (05h)
8
7
ADCDIV2
0
ADC 6dB attenuate enable
0 = disabled (0dB)
ADC and DAC
control
1 = -6dB enabled
DACDIV2
0
DAC 6dB attenuate enable
0 = disabled (0dB)
1 = -6dB enabled
Table 14 ADC and DAC 6dB Attenuation Select
PP Rev 1.77 May 2003
25
ꢀ
WM8750L
Product Preview
OUTPUT SIGNAL PATH
The WM8750L output signal paths consist of digital filters, DACs, analogue mixers and output
drivers. The digital filters and DACs are enabled when the WM8750L is in ‘playback only’ or ‘record
and playback’ mode. The mixers and output drivers can be separately enabled by individual control
bits (see Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification
provided by the WM8750L, irrespective of whether the DACs are running or not.
The WM8750L receives digital input data on the DACDAT pin. The digital filter block processes the
data to provide the following functions:
•
•
•
Digital volume control
Graphic equaliser and Dynamic Bass Boost
Sigma-Delta Modulation
Two high performance sigma-delta audio DACs convert the digital data into two analogue signals (left
and right). These can then be mixed with analogue signals from the LINPUT1/2/3 and RINPUT1/2/3
pins, and the mix is fed to the output drivers, LOUT1/ROUT1, LOUT2/ROUT2, OUT3 and
MONOOUT.
•
•
LOUT1/ROUT1/OUT3: can drive a 16Ω or 32Ω stereo headphone or stereo line output.
LOUT2/ROUT2: can drive a 16Ω or 32Ω stereo headphone or stereo line output, or an
8Ω mono speaker.
•
MONOOUT: can drive a mono line output or other load down to 10kΩ
DIGITAL DAC VOLUME CONTROL
The signal volume from each DAC can be controlled digitally, in the same way as the ADC volume
(see Digital ADC Volume Control). The gain and attenuation range is –127dB to 0dB in 0.5dB steps.
The level of attenuation for an eight-bit code X is given by:
0.5 × (X-255) dB for 1 ≤ X ≤ 255;
MUTE for X = 0
The LDVU and RDVU control bits control the loading of digital volume control data. When LDVU or
RDVU are set to 0, the LDACVOL or RDACVOL control data is loaded into an intermediate register,
but the actual gain does not change. Both left and right gain settings are updated simultaneously
when either LDVU or RDVU are set to 1.
REGISTER
ADDRESS
BIT
LABEL
LDVU
DEFAULT
DESCRIPTION
R10 (0Ah)
8
0
Left DAC Volume Update
Left Channel
Digital Volume
0 = Store LDACVOL in intermediate
latch (no gain change)
1 = Update left and right channel
gains (left = LDACVOL, right =
intermediate latch)
7:0
LDACVOL
[7:0]
11111111
( 0dB )
Left DAC Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
R11 (0Bh)
8
RDVU
0
Right DAC Volume Update
Right Channel
Digital Volume
0 = Store RDACVOL in intermediate
latch (no gain change)
1 = Update left and right channel
gains (left = intermediate latch, right
= RDACVOL)
7:0
RDACVOL
[7:0]
11111111
( 0dB )
Right DAC Digital Volume Control
similar to LDACVOL
Table 15 Digital Volume Control
PP Rev 1.77 May 2003
26
ꢀꢁ
Product Preview
WM8750L
GRAPHIC EQUALISER
The WM8750L has a digital graphic equaliser and adaptive bass boost function. This function
operates on digital audio data before it is passed to the audio DACs. Bass enhancement can take
two different forms:
•
Linear bass control: bass signals are amplified or attenuated by a user programmable
gain. This is independent of signal volume, and very high bass gains on loud signals
may lead to signal clipping.
•
Adaptive bass boost: The bass volume is amplified by a variable gain. When the bass
volume is low, it is boosted more than when the bass volume is high. This method is
recommended because it prevents clipping, and usually sounds more pleasant to the
human ear.
Treble control applies a user programmable gain, without any adaptive boost function. Bass and
treble control are completely independent with separately programmable gains and filter
characteristics.
REGISTER
ADDRESS
BIT
LABEL
BB
DEFAULT
DESCRIPTION
R12 (0Ch)
7
0
0
Bass Boost
Bass Control
0 = Linear bass control
1 = Adaptive bass boost
6
BC
Bass Filter Characteristic
0 = Low Cutoff (130Hz at 48kHz sampling)
1 = High Cutoff (200Hz at 48kHz sampling)
Bass Intensity
3:0
BASS
[3:0]
1111
(Disabled)
Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
BB=0
+9dB
BB=1
15 (max)
+9dB
14
13
12
11
10
9
+7.5dB
+6dB
+4.5dB
+3dB
+1.5dB
0dB
8
-1.5dB
-3dB
7
6
-4.5dB
-6dB
5
4
-6dB
3
-6dB
2
-6dB
1
Bypass (OFF)
R13 (0Dh)
6
TC
0
Treble Filter Characteristic
Treble Control
0 = High Cutoff (8kHz at 48kHz sampling)
1 = Low Cutoff (4kHz at 48kHz sampling)
Treble Intensity
3:0
TRBL
[3:0]
1111
(Disabled)
0000 or 0001 = +9dB
0010 = +7.5dB
… (1.5dB steps)
1011 to 1110 = -6dB
1111 = Disable
Table 16 Graphic equaliser
PP Rev 1.77 May 2003
27
ꢀ
WM8750L
Product Preview
DIGITAL TO ANALOGUE CONVERTER (DAC)
After passing through the graphic equaliser filters, digital ‘de-emphasis’ can be applied to the audio
data if necessary (e.g. when the data comes from a CD with pre-emphasis used in the recording).
De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz.
The WM8750L also has a Soft Mute function, which gradually attenuates the volume of the digital
signal to zero. When removed, the gain will ramp back up to the digital gain setting. This function is
enabled by default. To play back an audio signal, it must first be disabled by setting the DACMU bit
to zero.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
00
DESCRIPTION
R5 (05h)
2:1
DEEMP
De-emphasis Control
ADC and DAC
Control
[1:0]
11 = 48kHz sample rate
10 = 44.1kHz sample rate
01 = 32kHz sample rate
00 = No De-emphasis
Digital Soft Mute
3
DACMU
1
1 = mute
0 = no mute (signal active)
Table 17 DAC Control
The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital
interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to
high quality analogue audio signals. The multi-bit DAC architecture reduces high frequency noise and
sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and
low distortion.
In normal operation, the left and right channel digital audio data is converted to analogue in two
separate DACs. However, it is also possible to disable one channel, so that the same signal (left or
right) appears on both analogue output channels. Additionally, there is a mono-mix mode where the
two audio channels are mixed together digitally and then converted to analogue using only one DAC,
while the other DAC is switched off. The mono-mix signal can be selected to appear on both
analogue output channels.
The DAC output defaults to non-inverted. Setting DACINV will invert the DAC output phase on both
left and right channels.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R23 (17h)
5:4
DMONOMIX
[1:0]
00
DAC mono mix
Additional
Control (1)
00: stereo
01: mono ((L+R)/2) into DACL, ‘0’ into
DACR
10: mono ((L+R)/2) into DACR, ‘0’ into
DACL
11: mono ((L+R)/2) into DACL &
DACR
1
DACINV
0
DAC phase invert
0 : non-inverted
1 : inverted
Table 18 DAC Mono Mix and Phase Invert Select
PP Rev 1.77 May 2003
28
ꢀꢁ
Product Preview
WM8750L
OUTPUT MIXERS
The WM8750L provides the option to mix the DAC output signal with analogue line-in signals from
the LINPUT1/2/3, RINPUT1/2/3 pins or a mono differential input (LINPUT1 – RINPUT1) or (LINPUT2
– RINPUT2), selected by DS (see Table 4) . The level of the mixed-in signals can be controlled with
PGAs (Programmable Gain Amplifiers).
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
000
DESCRIPTION
R34 (22h)
2:0
LMIXSEL
Left Input Selection for Output Mix
000 = LINPUT1
Left Mixer (1)
001 = LINPUT2
010 = LINPUT3
011 = Left ADC Input (after PGA /
MICBOOST)
100 = Differential input
Right Input Selection for Output Mix
000 = RINPUT1
R36 (24h)
2:0
RMIXSEL
000
Right Mixer
(1)
001 = RINPUT2
010 = RINPUT3
011 = Right ADC Input (after PGA /
MICBOOST)
100 = Differential input
Table 19 Output Mixer Signal Selection
REGISTER
ADDRESS
BIT
LABEL
LD2LO
DEFAULT
DESCRIPTION
R34 (22h)
8
0
Left DAC to Left Mixer
0 = Disable (Mute)
1 = Enable Path
Left Mixer
Control (1)
7
LI2LO
0
LMIXSEL Signal to Left Mixer
0 = Disable (Mute)
1 = Enable Path
6:4
LI2LOVOL
[2:0]
101
LMIXSEL Signal to Left Mixer Volume
000 = +6dB
(-9dB)
… (3dB steps)
111 = -15dB
R35 (23h)
8
RD2LO
RI2LO
0
0
Right DAC to Left Mixer
0 = Disable (Mute)
1 = Enable Path
Left Mixer
Control (2)
7
RMIXSEL Signal to Left Mixer
0 = Disable (Mute)
1 = Enable Path
6:4
RI2LOVOL
[2:0]
101
RMIXSEL Signal to Left Mixer Volume
000 = +6dB
(-9dB)
… (3dB steps)
111 = -15dB
Table 20 Left Output Mixer Control
PP Rev 1.77 May 2003
29
ꢀ
WM8750L
Product Preview
REGISTER
ADDRESS
BIT
LABEL
LD2RO
DEFAULT
DESCRIPTION
Left DAC to Right Mixer
R36 (24h)
8
0
Right Mixer
Control (1)
0 = Disable (Mute)
1 = Enable Path
7
LI2RO
0
LMIXSEL Signal to Right Mixer
0 = Disable (Mute)
1 = Enable Path
6:4
LI2ROVOL
[2:0]
101
LMIXSEL Signal to Right Mixer Volume
000 = +6dB
(-9dB)
… (3dB steps)
111 = -15dB
R37 (25h)
8
RD2RO
RI2RO
0
0
Right DAC to Right Mixer
0 = Disable (Mute)
Right Mixer
Control (2)
1 = Enable Path
7
RMIXSEL Signal to Right Mixer
0 = Disable (Mute)
1 = Enable Path
6:4
RI2ROVOL
[2:0]
101
RMIXSEL Signal to Right Mixer Volume
000 = +6dB
(-9dB)
… (3dB steps)
111 = -15dB
Table 21 Right Output Mixer Control
REGISTER
ADDRESS
BIT
LABEL
LD2MO
DEFAULT
DESCRIPTION
R38 (26h)
8
0
Left DAC to Mono Mixer
0 = Disable (Mute)
Mono Mixer
Control (1)
1 = Enable Path
7
LI2MO
0
LMIXSEL Signal to Mono Mixer
0 = Disable (Mute)
1 = Enable Path
6:4
LI2MOVOL
[2:0]
101
LMIXSEL Signal to Mono Mixer
Volume
(-9dB)
000 = +6dB
… (3dB steps)
111 = -15dB
R39 (27h)
8
RD2MO
RI2MO
0
0
Right DAC to Mono Mixer
0 = Disable (Mute)
1 = Enable Path
Mono Mixer
Control (2)
7
RMIXSEL Signal to Mono Mixer
0 = Disable (Mute)
1 = Enable Path
6:4
RI2MOVOL
[2:0]
101
RMIXSEL Signal to Mono Mixer
Volume
(-9dB)
000 = +6dB
… (3dB steps)
111 = -15dB
Table 22 Mono Output Mixer Control
PP Rev 1.77 May 2003
30
ꢀꢁ
Product Preview
WM8750L
ANALOGUE OUTPUTS
LOUT1/ROUT1 OUTPUTS
The LOUT1 and ROUT1 pins can drive a 16Ω or 32Ω headphone or a line output (see Headphone
Output and Line Output sections, respectively). The signal volume on LOUT1 and ROUT1 can be
independently adjusted under software control by writing to LOUT1VOL and ROUT1VOL,
respectively. Note that gains over 0dB may cause clipping if the signal is large. Any gain setting
below 0101111 (minimum) mutes the output driver. The corresponding output pin remains at the
same DC level (the reference voltage on the VREF pin), so that no click noise is produced when
muting or un-muting.
A zero cross detect on the analogue output may also be enabled when changing the gain setting to
minimize audible clicks and zipper noise as the gain updates. If zero cross is enabled a timeout is
also available to update the gain if a zero cross does not occur. This function may be enabled by
setting TOEN in register R23 (17h).
REGISTER
ADDRESS
BIT
LABEL
LO1VU
DEFAULT
DESCRIPTION
R2 (02h)
LOUT1
Volume
8
0
Left Volume Update
0 = Store LOUT1VOL in intermediate
latch (no gain change)
1 = Update left and right channel gains
(left = LOUT1VOL, right =
intermediate latch)
7
LO1ZC
0
Left zero cross enable
1 = Change gain on zero cross only
0 = Change gain immediately
LOUT1 Volume
6:0
LOUT1VOL
[6:0]
1111001
(0dB)
1111111 = +6dB
… (80 steps)
0110000 = -67dB
0101111 to 0000000 = Analogue
MUTE
R3 (03h)
ROUT1
Volume
8
RO1VU
RO1ZC
0
Right Volume Update
0 = Store ROUT1VOL in intermediate
latch (no gain change)
1 = Update left and right channel gains
(left = intermediate latch, right =
ROUT1VOL)
7
0
Left zero cross enable
1 = Change gain on zero cross only
0 = Change gain immediately
ROUT1 Volume
6:0
ROUT1VOL
[6:0]
1111001
Similar to LOUT1VOL
Table 23 LOUT1/ROUT1 Volume Control
PP Rev 1.77 May 2003
31
ꢀ
WM8750L
Product Preview
LOUT2/ROUT2 OUTPUTS
The LOUT2 and ROUT2 output pins are essentially similar to LOUT1 and ROUT1, but they are
independently controlled and can also drive an 8Ω mono speaker (see Speaker Output section). For
speaker drive, the ROUT2 signal must be inverted (ROUT2INV = 1), so that the left and right channel
are mixed to mono in the speaker [L–(-R) = L+R].
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Similar to LOUT1VOL
R40 (28h)
LOUT2
6:0
LOUT2VOL
[6:0]
1111001
(0dB)
0
Volume
7
LO2ZC
Left zero cross enable
1 = Change gain on zero cross only
0 = Change gain immediately
Same as LO1VU
8
LO2VU
ROUT2VOL
[6:0]
0
R41 (29h)
ROUT2
6:0
1111001
(0dB)
0
Similar ROUT1VOL
Volume
7
RO2ZC
Left zero cross enable
1 = Change gain on zero cross only
0 = Change gain immediately
Same as RO1VU
8
4
RO2VU
0
0
R24 (18h)
ROUT2INV
ROUT2 Invert
Additional
Control (2)
0 = No Inversion (0° phase shift)
1 = Signal inverted (180° phase shift)
Table 24 LOUT2/ROUT2 Volume Control
MONO OUTPUT
The MONOOUT pin can drive a mono line output. The signal volume on MONOOUT can be adjusted
under software control by writing to MONOOUTVOL.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R42 (2Ah)
MONOOUT
Volume
6:0
MONOOUT
VOL [6:0]
1111001
(0dB)
MONOOUT Volume
1111111 = +6dB
… (80 steps)
0110000 = -67dB
0101111 to 0000000 = Analogue MUTE
MONOOUT zero cross enable
1 = Change gain on zero cross only
0 = Change gain immediately
7
MOZC
0
Table 25 MONOOUT Volume Control
OUT3 OUTPUT
The OUT3 pin can drive a 16Ω or 32Ω headphone or a line output or be used as a DC reference for a
headphone output (see Headphone Output section). It can be selected to either drive out an inverted
ROUT1 or inverted MONOOUT for e.g. an earpiece drive between OUT3 and LOUT1 or differential
output between OUT3 and MONOOUT.
OUT3SW selects the mode of operation required.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
00
DESCRIPTION
R24 (18h)
8:7
OUT3SW
[1:0]
OUT3 select
00 : VREF
Additional
Control (2)
01 : ROUT1 signal (volume controlled by
ROUT1VOL)
10 : MONOOUT
11 : right mixer output (no volume
control through ROUT1VOL)
Table 26 OUT3 Select
PP Rev 1.77 May 2003
32
ꢀꢁ
Product Preview
WM8750L
ENABLING THE OUTPUTS
Each analogue output of the WM8750L can be separately enabled or disabled. The analogue mixer
associated with each output is powered on or off along with the output pin. All outputs are disabled by
default. To save power, unused outputs should remain disabled.
Outputs can be enabled at any time, except when VREF is disabled (VR=0), as this may cause pop
noise (see “Power Management” and “Applications Information” sections)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R26 (1Ah)
6
LOUT1
0
0
0
0
0
0
LOUT1 Enable
Power
Management
(2)
5
4
3
2
1
ROUT1
LOUT2
ROUT2
MONO
OUT3
ROUT1 Enable
LOUT2 Enable
ROUT2 Enable
MONOOUT Enable
OUT3 Enable
Note: All “Enable” bits are 1 = ON, 0 = OFF
Table 27 Analogue Output Control
Whenever an analogue output is disabled, it remains connected to VREF (pin 20) through a resistor.
This helps to prevent pop noise when the output is re-enabled. The resistance between VREF and
each output can be controlled using the VROI bit in register 27. The default is low (1.5kΩ), so that
any capacitors on the outputs can charge up quickly at start-up. If a high impedance is desired for
disabled outputs, VROI can then be set to 1, increasing the resistance to about 40kΩ.
REGISTER
ADDRESS
BIT
LABEL
VROI
DEFAULT
DESCRIPTION
R27 (1Bh)
6
0
VREF to analogue output resistance
Additional (1)
0: 1.5 kΩ
1: 40 kΩ
Table 28 Disabled outputs to VREF resistance
HEADPHONE SWITCH
The RINPUT3/HPDETECT pin can be used as a headphone switch control input to automatically
disable the speaker output and enable the headphone output e.g. when a headphone is plugged into
a jack socket. In this mode, enabled by setting HPSWEN, HPDETECT switches between headphone
and speaker outputs (e.g. when the pin is connected to a mechanical switch in the headphone socket
to detect plug-in). The HPSWPOL bit reverses the pin’s polarity. Note that the LOUT1, ROUT1,
LOUT2 and ROUT2 bits in register 26 must also be set for headphone and speaker output (see
Table 29 and Table 30).
Note:
When RINPUT3/HPDETECT is used as the HPDETECT input, the thresholds become CMOS levels
(0.3 AVDD / 0.7 AVDD).
HPSWEN HPSWPOL HPDETECT L/ROUT1 L/ROUT2 Headphone
Speaker
enabled
no
(PIN23)
(reg. 26)
(reg. 26)
enabled
no
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
X
X
0
1
X
X
0
1
0
1
0
1
0
1
X
X
0
1
X
X
no
yes
no
yes
yes
no
yes
no
no
yes
no
no
yes
no
no
no
yes
no
no
no
no
yes
Table 29 Headphone Switch Operation
PP Rev 1.77 May 2003
33
ꢀ
WM8750L
Product Preview
DESCRIPTION
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R24 (18h)
6
HPSWEN
0
0
Headphone Switch Enable
Additional
Control (2)
0 : Headphone switch disabled
1 : Headphone switch enabled
Headphone Switch Polarity
5
HPSWPOL
0 : HPDETECT high = headphone
1 : HPDETECT high = speaker
Table 30 Headphone Switch
AVDD
/
HPSWEN = 1
HPSWPOL = 1
L/ROUT1 = L/ROUT2 = 1
-
-
ROUT1
LOUT1
L
R
47k
100k
Ω
headphone /
speaker
switching
Ω
HPDETECT
switch closes
on insertion
Figure TBD Example Headset Detection circuit using normally-open switch
AVDD
HPSWEN = 1
HPSWPOL = 0
L/ROUT1 = L/ROUT2 = 1
-
-
ROUT1
LOUT1
L
R
47k
100k
Ω/
headphone /
speaker
switching
Ω
switch opens
on insertion
HPDETECT
Figure TBD Example Headset Detection circuit using normally-closed switch
PP Rev 1.77 May 2003
34
ꢀꢁ
Product Preview
WM8750L
THERMAL SHUTDOWN
The speaker and headphone outputs can drive very large currents. To protect the WM8750L from
overheating a thermal shutdown circuit is included. If the device temperature reaches approximately
1500C and the thermal shutdown circuit is enabled (TSDEN = 1 ) then the speaker and headphone
amplifiers (outputs OUT1L/R, OUT2L/R & OUT3) will be disabled.
REGISTER
ADDRESS
BIT
LABEL
TSDEN
DEFAULT
DESCRIPTION
R23 (17h)
8
0
Thermal Shutdown Enable
0 : thermal shutdown disabled
1 : thermal shutdown enabled
Additional
Control (1)
Table 31 Thermal Shutdown
HEADPHONE OUTPUT
Analogue outputs LOUT1/ROUT1, LOUT2/ROUT2, and OUT3, can drive a 16Ω or 32Ω headphone
load, either through DC blocking capacitors, or DC coupled without any capacitor.
DC Coupled Headphone Output
(OUT3SW = 00)
Headphone Output using DC blocking
capacitors
C1 220uF
LOUT1/2
LOUT1/2
ROUT1/2
WM8750L
WM8750L
C2 220uF
ROUT1/2
HPGND = 0V
OUT3 = VREF
Figure 9 Recommended Headphone Output Configurations
When DC blocking capacitors are used, then their capacitance and the load resistance together
determine the lower cut-off frequency, fc. Increasing the capacitance lowers fc, improving the bass
response. Smaller capacitance values will diminish the bass response. Assuming a 16 Ohm load and
C1, C2 = 220µF:
fc = 1 / 2π RLC1 = 1 / (2π x 16Ω x 220µF) = 45 Hz
In the DC coupled configuration, the headphone “ground” is connected to the OUT3 pin, which must
be enabled by setting OUT3 = 1 and OUT3SW = 00. As the OUT3 pin produces a DC voltage of
AVDD/2 (=VREF), there is no DC offset between LOUT1/ROUT1 and OUT3, and therefore no DC
blocking capacitors are required. This saves space and material cost in portable applications.
It is recommended to connect the DC coupled headphone outputs only to headphones, and not to
the line input of another device. Although the built-in short circuit protection will prevent any damage
to the headphone outputs, such a connection may be noisy, and may not function properly if the
other device is grounded.
SPEAKER OUTPUT
LOUT2 and ROUT2 can differentially drive a mono 8Ω speaker as shown below.
LEFT
MIXER
LOUT2
LOUT2VOL
WM8750L
ROUT2INV = 1
VSPKR = L-(-R) = L+R
-1
ROUT2
RIGHT
MIXER
ROUT2VOL
Figure 10 Speaker Output Connection
The right channel is inverted by setting the ROUT2INV bit, so that the signal across the loudspeaker
is the sum of left and right channels.
PP Rev 1.77 May 2003
35
ꢀ
WM8750L
Product Preview
LINE OUTPUT
The analogue outputs, LOUT1/ROUT1 and LOUT2/ROUT2, can be used as line outputs.
Additionally, OUT3 and MONOOUT can be used as a stereo line-out by setting OUT3SW=11 (reg.
24) and ensuring the contents of registers 38 and 39 (mono-out mix) are the same as reg. 34 and 35
(left out mix). Recommended external components are shown below.
C1
R1
1uF
100 Ohm
LOUT1/2
or OUT3 (OUT3SW=11)
LINE-OUT
SOCKET
(LEFT)
AGND
AGND
WM8750L
ROUT1/2
or MONOOUT
LINE-OUT
SOCKET
(RIGHT)
C2
1uF
R2
100 Ohm
Figure 11 Recommended Circuit for Line Output
The DC blocking capacitors and the load resistance together determine the lower cut-off frequency,
fc. Assuming a 10 kOhm load and C1, C2 = 1µF:
fc = 1 / 2π (RL+R1) C1 = 1 / (2π x 10.1kΩ x 1µF) = 16 Hz
Increasing the capacitance lowers fc, improving the bass response. Smaller values of C1 and C2 will
diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage
when used improperly.
DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting DAC data into the WM8750L and outputting ADC data
from it. It uses five pins:
•
•
•
•
•
ADCDAT: ADC data output
ADCLRC: ADC data alignment clock
DACDAT: DAC data input
ADCLRC: DAC data alignment clock
BCLK: Bit clock, for synchronisation
The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8750L operates as a
master, or inputs when it is a slave (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
•
•
•
•
Left justified
Right justified
I2S
DSP mode
All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8750L can be configured as either a master or slave mode device. As a master device the
WM8750L generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data
transfer on ADCDAT and DACDAT. In slave mode, the WM8750L responds with data to clocks it
receives over the digital audio interface. The mode can be selected by writing to the MS bit (see
Table 23). Master and slave modes are illustrated below.
BCLK
ADCLRC
DACLRC
ADCDAT
DACDAT
BCLK
ADCLRC
DACLRC
ADCDAT
DACDAT
DSP
ENCODER/
DECODER
DSP
ENCODER/
DECODER
WM8750
CODEC
WM8750
CODEC
Note: The ADC and DAC can run at different sample rates
Note: The ADC and DAC can run at different sample rates
Figure 12 Master Mode
Figure 13 Slave Mode
PP Rev 1.77 May 2003
36
ꢀꢁ
Product Preview
WM8750L
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
BCLK
DACDAT/
ADCDAT
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
Input Word Length (WL)
Note: Input word length is defined by the WL register.
Timing is shown with LRP = 1
Figure 14 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
BCLK
DACDAT/
ADCDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Input Word Length (WL)
Note: Input word length is defined by the WL register.
Timing is shown with LRP = 1
Figure 15 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
BCLK
1 BCLK
1 BCLK
DACDAT/
ADCDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Input Word Length (WL)
Note: Input word length is defined by the WL register.
Timing is shown with LRP = 1
Figure 16 I2S Justified Audio Interface (assuming n-bit word length)
In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising
edge of BCLK (selectable by LRP) following a rising edge of LRCLK. Right channel data immediately
PP Rev 1.77 May 2003
37
ꢀ
WM8750L
Product Preview
follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be
unused BCLK cycles between the LSB of the right channel data and the next sample.
1/fs
1 BCLK
DACLRC/
ADCLRC
BCLK
RIGHT CHANNEL
LEFT CHANNEL
DACDAT/
ADCDAT
1
2
3
n
1
2
3
n-2 n-1
n
n-2 n-1
MSB
LSB
Input Word Length (WL)
Figure 17 DSP Mode Audio Interface (mode A, LRP=0)
1/fs
1 BCLK
DACLRC/
ADCLRC
BCLK
RIGHT CHANNEL
LEFT CHANNEL
DACDAT/
ADCDAT
1
2
3
n
1
2
3
n-2 n-1
n
n-2 n-1
MSB
LSB
Input Word Length (WL)
Figure 18 DSP Mode Audio Interface (mode B, LRP=1)
PP Rev 1.77 May 2003
38
ꢀꢁ
Product Preview
WM8750L
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised in
Table 32. MS selects audio interface operation in master or slave mode. In Master mode BCLK,
ADCLRC and DACLRC are outputs. The frequency of ADCLRC and DACLRC is set by the sample
rate control bits SR[4:0] and USB. In Slave mode BCLK, ADCLRC and DACLRC are inputs.
REGISTER
ADDRESS
BIT
LABEL
BCLKINV
DEFAULT
DESCRIPTION
R7 (07h)
7
0
BCLK invert bit (for master & slave
modes)
Digital Audio
Interface
Format
0 = BCLK not inverted
1 = BCLK inverted
6
5
MS
0
0
Master / Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Left/Right channel swap
LRSWAP
1 = swap left & right DAC data in audio
interface
0 = output left and right data as normal
right, left & i2s modes – LRCLK polarity
1 = invert LRCLK polarity
4
LRP
0
0 = normal LRCLK polarity
DSP Mode – mode A/B select
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)
3:2
1:0
WL[1:0]
10
10
Audio Data Word Length
11 = 32 bits (see Note)
10 = 24 bits
01 = 20 bits
00 = 16 bits
FORMAT[1:0]
Audio Data Format Select
11 = DSP Mode
10 = I2S Format
01 = Left justified
00 = Right justified
Table 32 Audio Data Format Control
Note: Right Justified mode does not support 32-bit data.
AUDIO INTERFACE OUTPUT TRISTATE
Register bit TRI, register 24(18h) bit[3] can be used to tristate the ADCDAT pin and switch ADCLRC,
DACLRC and BCLK to inputs. In Slave mode (MASTER=0) ADCLRC, DACLRC and BCLK are by
default configured as inputs and only ADCDAT will be tri-stated, (see Table 33).
REGISTER
ADDRESS
BIT
LABEL DEFAULT
TRI
DESCRIPTION
R24(18h)
Additional
Control (2)
3
0
Tristates ADCDAT and switches ADCLRC,
DACLRC and BCLK to inputs.
0 = ADCDAT is an output, ADCLRC, DACLRC
and BCLK are inputs (slave mode) or outputs
(master mode)
1 = ADCDATE is tristated, ADCLRC, DACLRC
and BCLK are inputs
Table 33 Tri-stating the Audio Interface
PP Rev 1.77 May 2003
39
ꢀ
WM8750L
Product Preview
MASTER MODE ADCLRC AND DACLRC ENABLE
In Master mode, by default ADCLRC is disabled when the ADC is disabled and DACLRC is disabled
when the DAC is disabled. Register bit LRCM, register 24(18h) bit[2] changes the control so that the
ADCLRC and DACLRC are disabled only when ADC and DAC are disabled. This enables the user to
use e.g. ADCLRC for both ADC and DAC LRCLK and disable the ADC when DAC only operation is
required, (see Table 34).
REGISTER
ADDRESS
BIT
LABEL DEFAULT
LRCM
DESCRIPTION
R24(18h)
Additional
Control (2)
2
0
Selects disable mode for ADCLRC and
DACLRC
0 = ADCLRC disabled when ADC disabled,
DACLRC disabled when DAC disabled
1 = ADCLRC and DACLRC disabled only when
ADC and DAC are disabled
Table 34 ADCLRC/DACLRC Enable
CLOCK OUTPUT
By default ADCLRC (pin 9) is the ADC word clock input/output. Under the control of ADCLRM[1:0],
register 27(1Bh) bits [8:7] the ADCLRC pin may be configured as a clock output. If ADCLRM is 01,
10 or 11 then ADCLRC pin is always an output even in slave mode or when TRI = ‘1’, (see Table 35).
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
R27(18h)
Additional
Control (3)
[8:7] ADCLRM
[1:0]
00
Configures ADCLRC pin
00 = ADCLRC is ADC word clock input (slave
mode) or ADCLRC output (master mode)
01 = ADCLRC pin is MCLK output
10 = ADCLRC pin is MCLK / 5.5 output
11 = ADCLRC pin is MCLK / 6 output
Table 35 ADCLRC Clock Output
CLOCKING AND SAMPLE RATES
The WM8750L supports a wide range of master clock frequencies on the MCLK pin, and can
generate many commonly used audio sample rates directly from the master clock. The ADC and
DAC do not need to run at the same sample rate; several different combinations are possible.
There are two clocking modes:
•
•
‘Normal’ mode supports master clocks of 128fs, 192fs, 256fs, 384fs, and their multiples
(Note: fs refers to the ADC or DAC sample rate, whichever is faster)
USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in
systems with a USB interface, and eliminates the need for an external PLL to generate
another clock frequency for the audio codec.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R8 (08h)
6
CLKDIV2
0
Master Clock Divide by 2
1 = MCLK is divided by 2
0 = MCLK is not divided
Sample Rate Control
Clocking Mode Select
1 = USB Mode
Clocking and
Sample Rate
Control
5:1
0
SR [4:0]
USB
0000
0
0 = ‘Normal’ Mode
Table 36 Clocking and Sample Rate Control
The clocking of the WM8750L is controlled using the CLKDIV2, USB, and SR control bits. Setting the
CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode.
Each value of SR[4:0] selects one combination of MCLK division ratios and hence one combination
of sample rates (see next page). Since all sample rates are generated by dividing MCLK, their
accuracy depends on the accuracy of MCLK. If MCLK changes, the sample rates change
proportionately.
Note that some sample rates (e.g. 44.1kHz in USB mode) are approximated, i.e. they differ from their
target value by a very small amount. This is not audible, as the maximum deviation is only 0.27%
PP Rev 1.77 May 2003
40
ꢀꢁ
Product Preview
WM8750L
(8.0214kHz instead of 8kHz in USB mode). By comparison, a half-tone step corresponds to a 5.9%
change in pitch.
MCLK
MCLK
ADC SAMPLE RATE
DAC SAMPLE RATE
USB
SR [4:0]
FILTER
TYPE
BCLK
CLKDIV2=0 CLKDIV2=1
(ADCLRC)
(DACLRC)
(MS=1)
‘Normal’ Clock Mode (‘*’ indicates backward compatibility with WM8731)
8 kHz (MCLK/1536)
8 kHz (MCLK/1536)
12 kHz (MCLK/1024)
16 kHz (MCLK/768)
24 kHz (MCLK/512)
32 kHz (MCLK/384)
48 kHz (MCLK/256)
48 kHz (MCLK/256)
96 kHz (MCLK/128)
8.0182 kHz (MCLK/1408)
8.0182 kHz (MCLK/1408)
11.025 kHz (MCLK/1024)
22.05 kHz (MCLK/512)
44.1 kHz (MCLK/256)
44.1 kHz (MCLK/256)
88.2 kHz (MCLK/128)
8 kHz (MCLK/2304)
8 kHz (MCLK/2304)
12 kHz (MCLK/1536)
16kHz (MCLK/1152)
24kHz (MCLK/768)
32 kHz (MCLK/576)
48 kHz (MCLK/384)
48 kHz (MCLK/384)
96 kHz (MCLK/192)
8.0182 kHz (MCLK/2112)
8.0182 kHz (MCLK/2112)
11.025 kHz (MCLK/1536)
22.05 kHz (MCLK/768)
44.1 kHz (MCLK/384)
44.1 kHz (MCLK/384)
88.2 kHz (MCLK/192)
8 kHz (MCLK/1536)
48 kHz (MCLK/256)
12 kHz (MCLK/1024)
16 kHz (MCLK/768)
24 kHz (MCLK/512)
32 kHz (MCLK/384)
8 kHz (MCLK/1536)
48 kHz (MCLK/256)
96 kHz (MCLK/128)
8.0182 kHz (MCLK/1408)
44.1 kHz (MCLK/256)
11.025 kHz (MCLK/1024)
22.05 kHz (MCLK/512)
8.0182 kHz (MCLK/1408)
44.1 kHz (MCLK/256)
88.2 kHz (MCLK/128)
8 kHz (MCLK/2304)
48 kHz (MCLK/384)
12 kHz (MCLK/1536)
16 kHz (MCLK/1152)
24 kHz (MCLK/768)
32 kHz (MCLK/576)
48 kHz (MCLK/384)
8 kHz (MCLK/2304)
96 kHz (MCLK/192)
8.0182 kHz (MCLK/2112)
44.1 kHz (MCLK/384)
11.025 kHz (MCLK/1536)
22.05 kHz (MCLK/768)
8.0182 kHz (MCLK/2112)
44.1 kHz (MCLK/384)
88.2 kHz (MCLK/192)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00110 *
00100 *
01000
01010
11100
01100 *
00010 *
00000 *
01110 *
10110 *
10100 *
11000
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
3
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/2
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/2
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/3
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/3
12.288 MHz 24.576 MHz
11.2896MHz 22.5792MHz
11010
10010 *
10000 *
11110 *
00111 *
00101 *
01001
18.432MHz 36.864MHz
01011
11101
01101 *
00001 *
00011 *
01111 *
10111 *
10101 *
11001
16.9344MHz 33.8688MHz
11011
10011 *
10001 *
11111 *
USB Mode (‘*’ indicates backward compatibility with WM8731)
8 kHz (MCLK/1500)
8 kHz (MCLK/1500)
8 kHz (MCLK/1500)
48 kHz (MCLK/250)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00110 *
00100 *
10111 *
10101 *
11001
01000
01010
11011
11100
01100 *
10011 *
10001 *
00010 *
00000 *
11111 *
01110 *
0
0
1
1
1
0
0
1
0
0
1
1
0
0
3
2
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
12.000MHz 24.000MHz
8.0214 kHz (MCLK/1496)
8.0214 kHz (MCLK/1496)
11.0259 kHz (MCLK/1088)
12 kHz (MCLK/1000)
16kHz (MCLK/750)
22.0588kHz (MCLK/544)
24kHz (MCLK/500)
32 kHz (MCLK/375)
44.118 kHz (MCLK/272)
44.118 kHz (MCLK/272)
48 kHz (MCLK/250)
48 kHz (MCLK/250)
88.235kHz (MCLK/136)
96 kHz (MCLK/125)
8.0214kHz (MCLK/1496)
44.118 kHz (MCLK/272)
11.0259kHz (MCLK/1088)
12 kHz (MCLK/1000)
16kHz (MCLK/750)
22.0588kHz (MCLK/544)
24kHz (MCLK/500)
32 kHz (MCLK/375)
8.0214kHz (MCLK/1496)
44.118 kHz (MCLK/272)
8 kHz (MCLK/1500)
48 kHz (MCLK/250)
88.235kHz (MCLK/136)
96 kHz (MCLK/125)
Table 37 Master Clock and Sample Rates
PP Rev 1.77 May 2003
41
ꢀ
WM8750L
Product Preview
CONTROL INTERFACE
SELECTION OF CONTROL MODE
The WM8750L is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is
accessed. The remaining 9 bits (B8 to B0) are data bits, corresponding to the 9 bits in each control
register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin
selects the interface format.
MODE
Low
INTERFACE FORMAT
2 wire
3 wire
High
Table 38 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB latches in a complete control word consisting of the last 16 bits.
latch
CSB
SCLK
SDIN
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
control register address
control register data bits
Figure 19 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8750L supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address
of each register in the WM8750L).
The WM8750L operates as a slave device only. The controller indicates the start of data transfer with
a high to low transition on SDIN while SCLK remains high. This indicates that a device address and
data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight
bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the
address of the WM8750L and the R/W bit is ‘0’, indicating a write, then the WM8750L responds by
pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’,
the WM8750L returns to the idle condition and wait for a new start condition and valid address.
Once the WM8750L has acknowledged a correct address, the controller sends the first byte of
control data (B15 to B8, i.e. the WM8750L register address plus the first bit of register data). The
WM8750L then acknowledges the first data byte by pulling SDIN low for one clock pulse. The
controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register
data), and the WM8750L acknowledges again by pulling SDIN low.
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8750L returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
DEVICE ADDRESS RD / WR
(7 BITS) BIT
ACK
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
ACK
(LOW)
CONTROL BYTE 2
(BITS 7 TO 0)
ACK
(LOW)
SDIN
SCLK
START
STOP
register address and
1st register data bit
remaining 8 bits of
register data
Figure 20 2-Wire Serial Control Interface
PP Rev 1.77 May 2003
42
ꢀꢁ
Product Preview
WM8750L
The WM8750L has two possible device addresses, which can be selected using the CSB pin.
CSB STATE
Low
DEVICE ADDRESS
0011010 (0 x 34h)
0011011 (0 x 36h)
High
Table 39 2-Wire MPU Interface Address Selection
POWER SUPPLIES
The WM8750L can use up to four separate power supplies:
•
AVDD / AGND: Analogue supply, powers all analogue functions except the headphone drivers.
AVDD can range from 1.8V to 3.6V and has the most significant impact on overall power
consumption (except for power consumed in the headphone). A large AVDD slightly improves
audio quality.
•
HPVDD / HPGND: Headphone supply, powers the headphone drivers. HPVDD can range from
1.8V to 3.6V. HPVDD is normally tied to AVDD, but it requires separate layout and decoupling
capacitors to curb harmonic distortion. With a larger HPVDD, louder headphone and speaker
outputs can be achieved with lower distortion. If HPVDD is lower than AVDD, the output signal
may be clipped.
•
•
DCVDD: Digital core supply, powers all digital functions except the audio and control
interfaces. DCVDD can range from 1.42V to 3.6V, and has no effect on audio quality. The
return path for DCVDD is DGND, which is shared with DBVDD.
DBVDD: Digital buffer supply, powers the audio and control interface buffers. This makes it
possible to run the digital core at very low voltages, saving power, while interfacing to other
digital devices using a higher voltage. DBVDD draws much less power than DCVDD, and has
no effect on audio quality. DBVDD can range from 1.8V to 3.6V. The return path for DBVDD is
DGND, which is shared with DCVDD.
It is possible to use the same supply voltage on all four. However, digital and analogue supplies
should be routed and decoupled separately to keep digital switching noise out of the analogue signal
paths.
PP Rev 1.77 May 2003
43
ꢀ
WM8750L
Product Preview
POWER MANAGEMENT
The WM8750L has two control registers that allow users to select which functions are active. For
minimum power consumption, unused functions should be disabled. To avoid any pop or click noise,
it is important to enable or disable functions in the correct order (see Applications Information).
VMIDSEL is the enable for the Vmid reference, which defaults to disabled and can be enabled as a
50kOhm potential divider or, for low power maintenance of Vref when all other blocks are disabled,
as a 500kOhm potential divider.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
00
DESCRIPTION
R25 (19h)
8:7
VMIDSEL
Vmid divider enable and select
Power
00 – Vmid disabled (for OFF mode)
Manageme
nt (1)
01 – 50kOhm divider enabled (for
playback/record)
10 – 500kOhm divider enabled (for low-power
standby)
11 – 5kOhm divider enabled (for fast start-up)
VREF (necessary for all other functions)
Analogue in PGA Left
Analogue in PGA Right
ADC Left
6
5
4
3
2
1
8
7
6
5
4
3
2
1
VREF
AINL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AINR
ADCL
ADCR
MICB
ADC Right
MICBIAS
R26 (1Ah)
DACL
DACR
LOUT1
ROUT1
LOUT2
ROUT2
MONO
OUT3
DAC Left
Power
Manageme
nt (2)
DAC Right
LOUT1 Output Buffer*
ROUT1 Output Buffer*
LOUT2 Output Buffer*
ROUT2 Output Buffer*
MONOOUT Output Buffer and Mono Mixer
OUT3 Output Buffer
Note: All control bits are 0=OFF, 1=ON
* The left mixer is enabled when LOUT1=1 or LOUT2=1. The right mixer is enabled when
ROUT1=1 or ROUT2=1.
Table 40 Power Management
STOPPING THE MASTER CLOCK
In order to minimise power consumed in the digital core of the WM8750L, the master clock should be
stopped in Standby and OFF modes. If this is cannot be done externally at the clock source, the
DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In
Standby mode with all supplies at 3.3V, setting DIGENB saves approximately 0.27mA on DCVDD
and 0.2mA on DBVDD. However, since setting DIGENB has no effect on the power consumption of
other system components external to the WM8750L, it is preferable to disable the master clock at its
source wherever possible.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R25 (19h)
1
DIGENB
0
Master clock disable
Additional Control
(1)
0: master clock enabled
1: master clock disabled
Table 41 ADC and DAC Oversampling Rate Selection
NOTE: Before DIGENB can be set, the control bits ADCL, ADCR, DACL and DACR must be set
to zero and a waiting time of 1ms must be observed. Any failure to follow this procedure may
prevent DACs and ADCs from re-starting correctly.
PP Rev 1.77 May 2003
44
ꢀꢁ
Product Preview
WM8750L
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC and DAC digital filters is in 128x oversampling mode.
Under the control of ADCOSR and DACOSR the oversampling rate may be halved. This will result in
a slight decrease in noise performance but will also reduce the power consumption of the device.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R24 (18h)
1
0
ADCOSR
0
0
ADC oversample rate select
1 = 64x (lowest power)
0 = 128x (best SNR)
Additional Control
(2)
DACOSR
DAC oversample rate select
1 = 64x (lowest power)
0 = 128x (best SNR)
Table 42 ADC and DAC Oversampling Rate Selection
SAVING POWER AT LOW SUPPLY VOLTAGES
The analogue supplies to the WM8750L can run from 1.8V to 3.6V. By default, all analogue circuitry
on the device is optimized to run at 3.3V. This set-up is also good for all other supply voltages down
to 1.8V. However, at lower voltages, it is possible to save power by reducing the internal bias
currents used in the analogue circuitry. This is controlled as shown below.
REGISTER
ADDRESS
BIT
LABEL DEFAULT
DESCRIPTION
R23 (17h)
7:6
VSEL
[1:0]
11
Analogue Bias optimization
Additional
Control(1)
00: Lowest bias current, optimized for AVDD=1.8V
01: Low bias current, optimized for AVDD=2.5V
1X: Default bias current, optimized for AVDD=3.3V
PP Rev 1.77 May 2003
45
ꢀ
WM8750L
Product Preview
REGISTER MAP
ADDRESS
REGISTER
remarks
Bit[8]
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
default
page ref
(Bit 15 – 9)
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
19
R0 (00h)
R1 (01h)
R2 (02h)
R3 (03h)
R4 (04h)
R5 (05h)
R6 (06h)
R7 (07h)
R8 (08h)
R9 (09h)
R10 (0Ah)
R11 (0Bh)
Left Input volume
Right Input volume
LOUT1 volume
ROUT1 volume
Reserved
LIVU LINMUTE LIZC
RIVU RINMUTE RIZC
LO1VU LO1ZC
LINVOL
010010111
010010111
001111001
001111001
000000000
000001000
000000000
000001010
000000000
000000000
011111111
011111111
000001111
000001111
not reset
19
RINVOL
LOUT1VOL[6:0]
ROUT1VOL[6:0]
31
31
RO1VU RO1ZC
-
0
0
0
0
0
0
0
0
0
ADCHPD
0
19,25,28
ADC & DAC Control ADCDIV2 DACDIV2
ADCPOL[1:0]
HPOR DACMU
DEEMPH[1:0]
-
Reserved
Audio Interface
Sample rate
Reserved
0
0
0
MS
0
0
0
0
0
0
39
0
BCLKINV
LRSWAP
LRP
WL[1:0]
FORMAT[1:0]
40
0
0
0
CLKDIV2
0
SR[4:0]
0
USB
0
-
0
LDVU
RDVU
0
0
0
0
26
Left DAC volume
Right DAC volume
Bass control
Treble control
Reset
LDACVOL[7:0]
26
RDACVOL[7:0]
27
R12 (0Ch) 0001100
R13 (0Dh) 0001101
BB
0
BC
TC
0
0
0
0
BASS[3:0]
TRBL[3:0]
27
0
-
R15 (0Fh)
R16 (10h)
R17 (11h)
R18 (12h)
R19 (13h)
R20 (14h)
R21 (15h)
R22 (16h)
R23 (17h)
R24 (18h)
R25 (19h)
R26 (1Ah)
R27 (1Bh)
R31 (1Fh)
R32 (20h)
R33 (21h)
R34 (22h)
R35 (23h)
R36 (24h)
R37 (25h)
R38 (26h)
R39 (27h)
R40 (28h)
R41 (29h)
R42 (2Ah)
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
writing to this register resets all registers to their default state
25
3D control
0
MODE3D 3DUC
3DLC
MAXGAIN[2:0]
0
3DDEPTH[3:0]
3DEN
000000000
001111011
000000000
000110010
000000000
011000011
011000011
011000000
000000000
000000000
000000000
000000000
000000000
000000000
000000000
001010000
001010000
001010000
001010000
001010000
001010000
001111001
001111001
001111001
23
ALC1
ALCSEL[1:0]
ALCL[3:0]
HLD[3:0]
ATK[3:0]
23
ALC2
0
0
ALCZC
0
0
23
ALC3
DCY[3:0]
NGTH[4:0]
24
Noise Gate
Left ADC volume
Right ADC volume
0
NGG[1:0]
NGAT
TOEN
21
LAVU
RAVU
LADCVOL[7:0]
RADCVOL[7:0]
21
18,19,28,35
Additional control(1) TSDEN
VSEL[1:0]
OUT3SW[1:0] HPSWEN HPSWPOL ROUT2INV
VMIDSEL[1:0] VREF AINL AINR
DACL DACR
ADCLRM[1:0]
DMONOMIX[1:0]
DATSEL[1:0]
DACINV
32, 34,45
44
Additional control(2)
Pwr Mgmt (1)
TRI
LRCM ADCOSR DACOSR
ADCL
ADCR
MICB
DIGENB
44
Pwr Mgmt (2)
LOUT1 ROUT1 LOUT2 ROUT2 MONO
OUT3
0
0
0
0
0
35
Additional Control (3)
ADC input mode
ADCL signal path
ADCR signal path
Left out Mix (1)
Left out Mix (2)
VROI
0
0
0
0
0
0
0
0
17
DS
0
MONOMIX[1:0]
LINSEL[1:0]
RINSEL[1:0]
LI2LO
RDCM
LDCM
0
0
17
LMICBOOST[1:0]
RMICBOOST[1:0]
0
0
17
0
0
0
29
LD2LO
RD2LO
LD2RO
LI2LOVOL[2:0]
0
LMIXSEL[2:0]
29
RI2LO
RI2LOVOL[2:0]
LI2ROVOL[2:0]
RI2ROVOL[2:0]
LI2MOVOL[2:0]
RI2MOVOL[2:0]
0
0
0
0
30
Right out Mix (1)
Right out Mix (2)
Mono out Mix (1)
Mono out Mix (2)
LOUT2 volume
LI2RO
0
RMIXSEL[2:0]
30
RD2RO RI2RO
LD2MO LI2MO
0
0
0
0
0
0
0
0
0
0
30
0
30
RD2MO RI2MO
LO2VU LO2ZC
RO2VU RO2ZC
0
32
LOUT2VOL[6:0]
ROUT2VOL[6:0]
MOUTVOL[6:0]
32
ROUT2 volume
MONOOUT volume
32
0
MOZC
PP Rev 1.77 May 2003
46
ꢀꢁ
Product Preview
WM8750L
DIGITAL FILTER CHARACTERISTICS
The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2
and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is
shown in the proceeding pages.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.416fs
+/- 0.05
UNIT
ADC Filter Type 0 (USB Mode, 250fs operation)
Passband
+/- 0.05dB
-6dB
0
0.5fs
Passband Ripple
Stopband
dB
dB
0.584fs
-60
Stopband Attenuation
f > 0.584fs
ADC Filter Type 1 (USB mode, 272fs or Normal mode operation)
Passband
+/- 0.05dB
-6dB
0
0.4535fs
+/- 0.05
0.5fs
Passband Ripple
Stopband
dB
0.5465fs
-60
Stopband Attenuation
f > 0.5465fs
-3dB
dB
Hz
High Pass Filter Corner
Frequency
3.7
-0.5dB
10.4
-0.1dB
21.6
DAC Filter Type 0 (USB mode, 250fs operation)
Passband
+/- 0.03dB
-6dB
0
0.416fs
+/-0.03
0.5fs
Passband Ripple
Stopband
dB
dB
0.584fs
-50
Stopband Attenuation
f > 0.584fs
DAC Filter Type 1 (USB mode, 272fs or Normal mode operation)
Passband
+/- 0.03dB
-6dB
0
0.4535fs
+/- 0.03
0.5fs
Passband Ripple
Stopband
dB
dB
0.5465fs
-50
Stopband Attenuation
f > 0.5465fs
Table 44 Digital Filter Characteristics
TERMINOLOGY
1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)
2. Pass-band Ripple – any variation of the frequency response in the pass-band region
PP Rev 1.77 May 2003
47
ꢀ
WM8750L
Product Preview
DAC FILTER RESPONSES
0.02
0.01
0
0
-20
-40
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
Figure 21 DAC Digital Filter Frequency Response – Type 0 Figure 22 DAC Digital Filter Ripple – Type 0
0.02
0
0.01
-20
-40
0
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-60
-80
-100
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Frequency (Fs)
Figure 23 DAC Digital Filter Frequency Response – Type 1 Figure 24 DAC Digital Filter Ripple – Type 1
0.02
0
0.01
-20
-40
0
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-60
-80
-100
0
0.05
0.1
0.15
0.2
0.25
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Frequency (Fs)
Figure 25 DAC Digital Filter Frequency Response – Type 2 Figure 26 DAC Digital Filter Ripple – Type 2
PP Rev 1.77 May 2003
48
ꢀꢁ
Product Preview
WM8750L
0.25
0.2
0
0.15
0.1
-20
-40
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
Frequency (Fs)
Frequency (Fs)
Figure 27 DAC Digital Filter Frequency Response – Type 3 Figure 28 DAC Digital Filter Ripple – Type 3
ADC FILTER RESPONSES
0.04
0
0.03
-20
0.02
0.01
-40
0
-60
-80
-0.01
-0.02
-0.03
-0.04
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
Frequency (Fs)
Figure 29 ADC Digital Filter Frequency Response – Type 0 Figure 30 ADC Digital Filter Ripple – Type 0
0.02
0
0.01
-20
-40
0
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-60
-80
-100
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Frequency (Fs)
Figure 31 ADC Digital Filter Frequency Response – Type 1 Figure 32 ADC Digital Filter Ripple – Type 1
PP Rev 1.77 May 2003
49
ꢀ
WM8750L
Product Preview
0.25
0.2
0
0.15
0.1
-20
-40
-60
-80
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
Frequency (Fs)
Frequency (Fs)
Figure 33 ADC Digital Filter Frequency Response – Type 2 Figure 34 ADC Digital Filter Ripple – Type 2
0.25
0
0.2
0.15
-20
0.1
0.05
-40
0
-0.05
-60
-0.1
-0.15
-80
-0.2
-0.25
-100
0
0.05
0.1
0.15
0.2
0.25
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Frequency (Fs)
Figure 35 ADC Digital Filter Frequency Response – Type 2 Figure 36 ADC Digital Filter Ripple – Type 3
DE-EMPHASIS FILTER RESPONSES
0
0.4
0.3
0.2
0.1
0
-2
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
2000
4000
6000
8000
10000 12000 14000 16000
0
2000
4000
6000
8000
10000 12000 14000 16000
Frequency (Fs)
Frequency (Fs)
Figure 37 De-emphasis Frequency Response (32kHz)
Figure 38 De-emphasis Error (32kHz)
PP Rev 1.77 May 2003
50
ꢀꢁ
Product Preview
WM8750L
0
0.4
0.3
0.2
0.1
0
-2
-4
-6
-8
-0.1
-0.2
-0.3
-0.4
-10
0
0
5000
10000
Frequency (Fs)
15000
20000
5000
10000
Frequency (Fs)
15000
20000
Figure 39 De-emphasis Frequency Response (44.1kHz)
Figure 40 De-emphasis Error (44.1kHz)
0
0.4
0.3
0.2
0.1
0
-2
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
5000
10000
Frequency (Fs)
15000
20000
0
5000
10000
Frequency (Fs)
15000
20000
Figure 41 De-emphasis Frequency Response (48kHz)
Figure 42 De-emphasis Error (48kHz)
HIGHPASS FILTER
The WM8750L has a selectable digital highpass filter in the ADC filter path to remove DC offsets. The filter response is
characterised by the following polynomial:
1 - z-1
H(z) =
1 - 0.9995z-1
0
-5
-10
-15
Figure 43 ADC Highpass Filter Response
0
0.0005
0.001
Frequency (Fs)
0.0015
0.002
PP Rev 1.77 May 2003
51
ꢀ
WM8750L
Product Preview
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
DVDD
AVDD
4
DGND
3
2
DBVDD
DCVDD
DGND
14
19
HPGND
AGND
18
17
AVDD
HPVDD
AGND
C1 C2
C4
C3
16
15
10
11
+
LOUT2
ROUT2
DGND
AGND
8 OHM
LOUDSPEAKER
1
MCLK
-
C13
+
5
9
7
6
8
BCLK
MONOOUT
OUT3
AUDIO
INTERFACE
(I2S/LJ/RJ/DSP)
ADCLRC
DACLRC
DACDAT
ADCDAT
32 OHM EAR
SPEAKER
13
12
+
C14
LOUT1
ROUT1
HIGH for 3-wire
LOW for 2-wire
29
MODE
C15
+
16 OR 32 OHM
HEADPHONES
30
31
32
CONTROL
INTERFACE
(2 OR 3-WIRE)
CSB
SDIN
SCLK
WM8750L
C7
C8
28
27
26
25
24
22
20
LINPUT1
RINPUT1
LINPUT2
RINPUT2
LINPUT3
MICBIAS
VREF
DVDD
AVDD
C20 C21
C18
C19
+
+
C9
21
C16
VMID
C5
C6
C17
+
+
+
C10
C11
C12
AGND
AGND
AGND
DGND
23 RINPUT3 /
HPDETECT
See External Components
Descriptions for details
Layout Notes:
1. C1 to C4, C16, C18 and C20 should be as close to the relative WM8750L connecting pin as possible.
2. AGND and DGND should be joined as close to the WM8750L as possible.
Recommended External Components Diagram
PP Rev 1.77 May 2003
52
ꢀꢁ
Product Preview
WM8750L
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1 – C4
C5 – C6
100nF
10uF
De-coupling for DBVDD, DCVDD, AVDD, HPVDD
Reservoir capacitor for DVDD, AVDD. Should the supplies use separate sources then
additional capacitors will be required of each additional source.
C7 – C12
C13
1uF
AC input coupling capacitors
2.2uF
220uF
Output AC coupling capacitors to remove DC level from MONOOUT
C14 & C15
Output AC coupling capacitors to remove DC level from headphone output (If used as
a line-out only, use 2.2uF caps. In capless mode using OUT3 , no caps are needed)
C16
C17
C18
C19
C20
C21
100nF
10uF
De-coupling for VMID.
Reservoir capacitor for VMID
100nF
10uF
De-coupling for VREF
Reservoir capacitor for VREF
100nF
10uF
De-coupling for MICBIAS – Not required if MICBIAS output is not used
Reservoir capacitor for MICBIAS – Not required if MICBIAS output is not used
External Components Descriptions
Note:
2
For Capacitors C5, C6, C17, C19 and C21 it is recommended that very low ESR components are used.
LINE INPUT CONFIGURATION
When LINPUT1/RINPUT1 or LINPUT2/RINPUT2 are used as line inputs, the microphone boost and
ALC functions should normally be disabled.
In order to avoid clipping, the user must ensure that the input signal does not exceed AVDD. This
may require a potential divider circuit in some applications. It is also recommended to remove RF
interference picked up on any cables using a simple first-order RC filter, as high-frequency
components in the input signal may otherwise cause aliasing distortion in the audio band. AC signals
with no DC bias should be fed to the WM8750L through a DC blocking capacitor, e.g. 1µF.
MICROPHONE INPUT CONFIGURATION
MICBIAS
R1
680 Ohm to 2.2kOhm
check microphone's specification
FROM
MICROPHONE
LINPUT1/2/3
RINPUT1/2/3
C2
1uF
AGND
R2
C1
47kOhm
220pF
AGND
AGND
Figure 44 Recommended Circuit for Line Input
For interfacing to a microphone, the ALC function should be enabled and the microphone boost
switched on. Microphones held close to a speaker’s mouth would normally use the 13dB gain setting,
while tabletop or room microphones would need a 29dB boost.
The recommended application circuit is shown above. R1 and R2 form part of the biasing network
(refer to Microphone Bias section). R1 connected to MICBIAS is necessary only for electret type
microphones that require a voltage bias. R2 should always be present to prevent the microphone
input from charging to a high voltage which may damage the microphone on connection. R1 and R2
PP Rev 1.77 May 2003
53
ꢀ
WM8750L
Product Preview
should be large so as not to attenuate the signal from the microphone, which can have source
impedance greater than 2kOhm. C1 together with the source impedance of the microphone and the
WM8750L input impedance forms an RF filter. C2 is a DC blocking capacitor to allow the microphone
to be biased at a different DC voltage to the MICIN signal.
MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS
To minimise any pop or click noise when the system is powered up or down, the following procedures
are recommended.
POWER UP
•
Switch on power supplies. By default the WM8750L is in Standby Mode, the DAC is
digitally muted and the Audio Interface, Line outputs and Headphone outputs are all OFF
(DACMU = 1 Power Management registers 1 and 2 are all zeros).
•
•
•
•
Enable Vmid and VREF, then wait for time TBD
Enable DACs as required
Enable line and / or headphone output buffers as required.
Set DACMU = 0 to soft-un-mute the audio DACs.
POWER DOWN
•
•
•
Set DACMU = 1 to soft-mute the audio DACs.
Disable all output buffers, then wait for time TBD.
Switch off the power supplies.
POWER MANAGEMENT EXAMPLES
OPERATION MODE
POWER MANAGEMENT (1)
PGAs ADCs
POWER MANAGEMENT (2)
DACs
Output Buffers
VR
1
AI
1
1
1
1
1
1
1
1
PGL PGR ADL ADR MBI DAL DAR LO1 RO1 LO2 RO2 MO HPD
Stereo Headphone Playback
Stereo Line-in Record
0
1
1
1
0
1
1
1
0
1
1
0
0
0
0
1
0
1
1
1
0
0
0
1
0
1
1
0
0
0
0
1
0
0
1
1
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
x
0
0
0
x
x
0
x
1
Stereo Microphone Record
Mono Microphone Record
Stereo Line-in to Headphone Out
Phone Call
1
1
1
1
Speaker Phone Call [ROUT2INV = 1]
1
Record Phone Call [L channel = mic with
boost, R channel = RX, enable mono mix]
1
PP Rev 1.77 May 2003
54
ꢀꢁ
Product Preview
WM8750L
PACKAGE DIMENSIONS
FL: 32 PIN QFN PLASTIC PACKAGE 5
X
5
X
0.9 mm BODY, 0.50 mm LEAD PITCH
DM030.C
SEE DETAIL A
D
CORNER
TIE BAR
D2
B
D2/2
5
25
32
L
1
24
INDEX AREA
(D/2 X E/2)
E2/2
A
E2
E
SEE DETAIL B
17
8
aaa
C
2 X
16 15
9
b
aaa
C
2 X
B
e
TOP VIEW
DETAIL A
ccc
C
(A3)
1
A
CORNER
TIE BAR
0.08
C
1
32x b
C A B
5
M
A1
bbb
C
SEATING PLANE
DETAIL B
EXPOSED
CENTRE
PAD
1
L1
Symbols
Dimensions (mm)
MIN
NOM
0.90
MAX
1.00
0.05
NOTE
A
A1
A3
b
0.85
0
0.02
0.2 REF
0.23
0.18
4.90
3.2
0.30
5.10
3.4
1
2
2
D
5.00
D2
E
3.3
5.00
5.10
3.4
4.90
3.2
E2
e
3.3
0.5 BSC
0.4
L
0.35
0.45
0.1
L1
R
1
b(min)/2
0.20
K
Tolerances of Form and Position
aaa
bbb
ccc
0.15
0.10
0.10
JEDEC, MO-220, VARIATION VKKD-2
REF:
NOTES:
1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM
PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF
ETCHING OF LEADFRAME.
2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2:
D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION
3. ALL DIMENSIONS ARE IN MILLIMETRES
4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY
PP Rev 1.77 May 2003
55
ꢀ
WM8750L
Product Preview
IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation
of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual
property right of WM covering or relating to any combination, machine, or process in which such products or services might
be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s
approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and
is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that
product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and
deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc
20 Bernard Terrace
Edinburgh
EH8 9NX
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
PP Rev 1.77 May 2003
56
ꢀꢁ
相关型号：
WM8750LEFL
STEREO CODEC FOR PORTABLE AUDIO APPLICATIONSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WOLFSON
WM8750LEFL/R
STEREO CODEC FOR PORTABLE AUDIO APPLICATIONSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WOLFSON
WM8750LSEFL
STEREO CODEC FOR PORTABLE AUDIO APPLICATIONSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WOLFSON
WM8750LSEFL/R
STEREO CODEC FOR PORTABLE AUDIO APPLICATIONSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WOLFSON
WM8750L_05
Stereo CODEC for Portable Audio ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WOLFSON
WM8751L
STEREO DAC FOR PORTABLE AUDIO APPLICATIONSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WOLFSON
WM8751LEFL
STEREO DAC FOR PORTABLE AUDIO APPLICATIONSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WOLFSON
WM8751LSEFL
STEREO DAC FOR PORTABLE AUDIO APPLICATIONSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WOLFSON
WM8751LSEFR
STEREO DAC FOR PORTABLE AUDIO APPLICATIONSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WOLFSON
WM8753
HI FI AND TELEPHONY DUAL CODECWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WOLFSON
WM8753L
HI FI AND TELEPHONY DUAL CODECWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WOLFSON
WM8753LEB/RV
HI FI AND TELEPHONY DUAL CODECWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WOLFSON
©2020 ICPDF网 联系我们和版权申明