WM8786GEDS/RV [WOLFSON]
24-Bit, 192kHz Stereo ADC; 24位， 192kHz立体声ADC
| 型号： | WM8786GEDS/RV |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | 24-Bit, 192kHz Stereo ADC |
| 文件： | 总22页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8786
w
24-Bit, 192kHz Stereo ADC
DESCRIPTION
FEATURES
•
•
•
•
•
•
SNR 111dB (‘A’ weighted @ 48kHz)
THD -102dB (at -0.1dB)
Sampling Frequency: 8 – 192kHz
Hardware Control Interface
The WM8786 is a stereo audio ADC with differential inputs
designed for high performance recordable media applications.
Data is provided as a PCM output.
Stereo 24-bit multi-bit sigma-delta ADCs are used with digital
audio output word lengths of 16 to 32 bits, and sampling rates
from 8kHz to 192kHz. The device also has a high pass filter to
remove residual DC offsets.
Master or Slave Clocking Mode
Programmable Audio Data Interface Modes
-
-
I2S, Left, Right Justified or DSP
24-Bit Word Length
•
•
Supply Voltages
The device is hardware controlled. Pin programming provides
access to all features including oversampling rate, audio format,
-
-
Analogue 4.5 to 5.5V
Digital core: 2.7V to 3.6V
powerdown, master/slave
control
and digital
signal
20-lead SSOP package
manipulation. The device is supplied in a 20-lead SSOP
package.
APPLICATIONS
•
•
•
•
Recordable DVD Players
Personal Video Recorders
High End Sound Cards
Studio Audio Processing Equipment
BLOCK DIAGRAM
Pre-Production, December 2005, Rev 3.0
WOLFSON MICROELECTRONICS plc
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Copyright 2005 Wolfson Microelectronics plc
WM8786
Pre-Production
TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
BLOCK DIAGRAM .................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
PIN DESCRIPTION ................................................................................................4
ABSOLUTE MAXIMUM RATINGS.........................................................................5
RECOMMENDED OPERATING CONDITIONS .....................................................5
ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY............................................................................................................ 7
SIGNAL TIMING REQUIREMENTS.......................................................................8
SYSTEM CLOCK TIMING ............................................................................................. 8
AUDIO INTERFACE TIMING – MASTER MODE, PCM DATA ...................................... 8
AUDIO INTERFACE TIMING – SLAVE MODE, PCM DATA ......................................... 9
POWER-ON RESET ................................................................................................... 10
DIGITAL FILTER CHARACTERISTICS...............................................................11
TERMINOLOGY.......................................................................................................... 11
FILTER RESPONSES..........................................................................................12
DEVICE DESCRIPTION.......................................................................................15
INTRODUCTION......................................................................................................... 15
DIGITAL AUDIO INTERFACE..................................................................................... 15
AUDIO INTERFACE CONTROL.................................................................................. 18
OVERSAMPLING RATIOS AND SIGMA-DELTA MODULATOR FREQUENCY.......... 18
MASTER CLOCK AND AUDIO SAMPLE RATES........................................................ 19
MLCK AND LRCLK PHASE RELATIONSHIP.............................................................. 19
APPLICATIONS INFORMATION .........................................................................20
RECOMMENDED EXTERNAL COMPONENTS.......................................................... 20
PACKAGE DIMENSIONS ....................................................................................21
IMPORTANT NOTICE..........................................................................................22
ADDRESS: .................................................................................................................. 22
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PIN CONFIGURATION
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AINL+
AINL-
AINR+
AINR-
VREF
VREFGND
AVDD
VMID
DGND
AGND
LRCLK
DVDD
OSR1
DOUT
BCLK
MCLK
MS0
OSR0
AUDIOF1
AUDIOF0
ORDERING INFORMATION
ORDER CODE
TEMPERATURE
RANGE
PACKAGE
MOISTURE SENSITIVITY
LEVEL
PEAK SOLDERING
TEMPERATURE
WM8786GEDS/V
-25°C to +85°C
20-pin SSOP
(Pb-free)
MSL3
260oC
WM8786GEDS/RV
-25°C to +85°C
20-pin SSOP,
(Pb-free, tape and reel)
MSL3
260oC
Note:
Reel quantity = 2,000
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PIN DESCRIPTION
PIN
1
NAME
AINL+
TYPE
Analogue Input
Analogue Input
Analogue Reference
Supply
DESCRIPTION
Left Channel Positive Input
2
AINL-
Left Channel Negative Input
Negative Reference Connection
Analogue Supply
3
VREFGND
AVDD
4
5
AGND
Supply
Analogue Ground (return path for AVDD)
Audio Interface Left / Right Clock
ADC Digital Audio Data
6
LRCLK
DOUT
Digital Input / Output
Digital Output
Digital Input / Output
Digital Input
7
8
BCLK
Audio Interface Bit Clock
Master Clock
9
MCLK
10
MS0
Digital Input
Master/Slave Control
(pull down pad)
0 = Slave Mode Audio Interface
1 = Master Mode Audio Interface @ 256fs (or @128fs in quad rate)
Audio Format Selection
11
12
AUDIOF0
AUDIOF1
Digital Input
Digital Input
00 = 24 bit right justified audio data format
01 = 24 bit left audio data format
10 = I2S audio data format
11 = DSP audio data format
Oversampling Rate Control
13
14
OSR0
(pull down pad)
OSR1
Digital Input
Digital Input
00 = Single rate (48kHz)
01 = Dual rate (96kHz)
10 = Quad rate (192kHz)
11 = Not valid
15
16
17
18
19
20
DVDD
DGND
VMID
Supply
Supply
Digital Supply
Digital Ground (return path for DVDD)
Midrail Voltage Decoupling Capacitor
Reference Voltage Decoupling Capacitor
Right Channel Negative Input
Right Channel Positive Input
Analogue Output
Analogue Reference
Analogue Input
Analogue Input
VREF
AINR-
AINR+
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling
and storage of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
-0.3V
MAX
+3.63V
Digital supply voltage
Analogue supply voltage
Voltage range digital inputs
Voltage range analogue inputs
Master Clock Frequency
-0.3V
+7V
DGND -0.3V
AGND -0.3V
DVDD + 0.3V
AVDD +0.3V
40MHz
Operating temperature range, TA
Storage temperature after soldering
Notes
-25°C
-65°C
+85°C
+150°C
1. Analogue and digital grounds must always be within 0.3V of each other.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Digital supply range
Analogue supply range
Ground
DVDD
AVDD
2.7
4.5
3.6
5.5
V
V
V
DGND,AGND
0
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ELECTRICAL CHARACTERISTICS
Test Conditions
DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Performance
Full Scale Input Signal Level
(for ADC 0dB Input)
Input resistance
2.0
Vrms
10
10
kΩ
pF
dB
Input capacitance
Signal to Noise Ratio (Note
1,2,4)
SNR
SNR
SNR
THD
A-weighted,
@ fs = 48kHz
Unweighted,
@ fs = 48kHz
A-weighted,
104
111
108
111
108
111
108
dB
dB
dB
dB
dB
Signal to Noise Ratio (Note
1,2,4)
@ fs = 96kHz
Unweighted,
@ fs = 96kHz
A-weighted,
Signal to Noise Ratio (Note
1,2,4)
@ fs = 192kHz
Unweighted,
@ fs = 192kHz
Total Harmonic Distortion
Total Harmonic Distortion
1kHz, -0.1dB Full Scale
@ fs = 48kHz
-102
-102
dB
dB
dB
%
1kHz, -0.1dB Full Scale
@ fs = 96kHz
1kHz, -0.1dB Full Scale
@ fs = 192kHz
-102
THD
1kHz, -0.1dB Full Scale
@ fs = 48kHz
0.0008
0.0008
0.0008
1kHz, -0.1dB Full Scale
@ fs = 96kHz
%
1kHz, -0.1dB Full Scale
@ fs = 192kHz
%
Dynamic Range
DNR
-60dBFS
104
5
111
0.1
dB
dB
Channel Level Matching
Power Supply Rejection Ratio
20kHz signal
PSRR
1kHz 100mVpp, applied
to AVDD, DVDD
0 dB
20Hz to 20kHz
100mVpp
45
dB
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
VIH
0.3 x DVDD
+1
V
V
Input HIGH level
0.7 x DVDD
-1
Input leakage current
Input capacitance
0.2
5
µA
pF
V
Output LOW
VOL
VOH
I
OL=1mA
0.1 x DVDD
Output HIGH
I
OH= -1mA
0.9 x DVDD
V
Analogue Reference Levels
Midrail Reference Voltage
VMID
RVMID
VREF
AVDD to VMID and
VMID to VREFGND
–3%
5
AVDD/2
0 k
+3%
+3%
V
Ω
V
Potential Divider Resistance
Buffered Reference Voltage
AVDD to VMID and
VMID to GND
–3%
0.8 x AVDD
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Test Conditions
DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Current
Analogue supply current
Digital supply current
Power Down
27
mA
5
mA
22
uA
Note:
1. VMID is decoupled with 10uF and 0.1uF capacitors close to the device package. Smaller capacitors may reduce
performance.
TERMINOLOGY
1. Signal-to-noise ratio (dB) – Ratio of output level with 1kHz full scale input, to the output level with all zeros into the
digital input, over a 20Hz to 20kHz bandwidth. (No Auto-zero or Automute function is employed in achieving these
results).
2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
5. All performance measurements are done with a 20kHz low pass filter, and where noted an A-weight filter, except
where noted. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings
than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although this is not
audible, it may affect dynamic specification values.
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SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Figure 1 System Clock Timing Requirements
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock cycle time
MCLK duty cycle
T
MCnLKsY 25
TMCLKDS
60:40
40:60
AUDIO INTERFACE TIMING – MASTER MODE, PCM DATA
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
LRCLK propagation delay from BCLK falling edge
DOUT propagation delay from BCLK falling edge
tDL
0
0
10
11
ns
ns
tDDA
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AUDIO INTERFACE TIMING – SLAVE MODE, PCM DATA
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY 25
ns
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DOUT propagation delay from BCLK falling edge
tLRSU
tLRH
tDD
10
10
0
ns
ns
ns
11
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POWER-ON RESET
The WM8786 has an internal power-on reset circuit. The reset sequence is entered at power-on or
power-up (DVDD). Until the internal reset is removed, DOUT is forced to zero. DOUT remains zero
for a count equal to 32 sample clocks, after power up. (This count is driven by MCLK and is
independent of any external LRCLK).
Figure 4 POR Circuit
Figure 5 POR Timing
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DIGITAL FILTER CHARACTERISTICS
The WM8786 digital filter characteristics scale with sample rate.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.454fs
+/- 0.005
UNIT
ADC Sample Rate (Single Rate - 48Hz typically)
Passband
+/- 0.005dB
0
-6dB
0.5fs
Passband Ripple
Stopband
dB
0.546fs
-85
Stopband Attenuation
Group Delay
f > 0.546fs
dB
s
32/fs
0.5fs
ADC Sample Rate (Dual Rate - 96kHz typically)
Passband
+/- 0.005dB
0
0.454fs
-6dB
Passband Ripple
Stopband
+/- 0.005
dB
0.546fs
-85
Stopband Attenuation
Group Delay
f > 0.546fs
dB
s
32/fs
ADC Sample Rate (Quad Rate - 192kHz typically)
Passband
+/- 0.005dB
-3dB
0
0.25fs
0.45fs
0.5fs
-6dB
Passband Ripple
Stopband
+/- 0.005
dB
0.75
fs
Stopband Attenuation
Group Delay
f > 0.75fs
-85
dB
s
10/fs
3.7
High Pass Filter Corner
Frequency
-3dB
Hz
-0.5dB
10.4
-0.1dB
21.6
Table 1 Digital Filter Characteristics
TERMINOLOGY
1. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band)
2. Pass-band Ripple – any variation of the frequency response in the pass-band region
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FILTER RESPONSES
SINGLE RATE 48k
0
-20
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (Fs)
Figure 6 Single Rate 48k Filter Response
0
-20
-40
-60
-80
-100
0.4
50.60.450.50.5
Frequency (Fs)
Figure 7 Single Rate 48k Filter Response
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Figure 8 Single Rate 48k Filter Response
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DUAL RATE 96k
0
-20
-40
-60
-80
-100
0
0.51
1.52
2.53
3.54
Frequency (Fs)
Figure 9 Dual Rate 96k Filter Response
0
-20
-40
-60
-80
-100
0.4
50.60.450.50.5
Frequency (Fs)
Figure 10 Dual Rate 96k Filter Response
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Figure 11 Dual Rate 96k Filter Response
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QUAD RATE 192k
0
-20
-40
-60
-80
-100
0
0.51
1.52
2.53
3.54
Frequency (Fs)
Figure 12 Quad Rate 192k Filter Response
0
-20
-40
-60
-80
-100
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (Fs)
Figure 13 Quad Rate 192k Filter Response
-2.5
-2.6
-2.7
-2.8
-2.9
-3
-3.1
-3.2
-3.3
-3.4
-3.5
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Figure 14 Quad Rate 192k Filter Response
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DEVICE DESCRIPTION
INTRODUCTION
The WM8786 is a high performance stereo audio ADC designed for demanding recording
applications such as DVD recorders, studio mixers, PVRs, and AV amplifiers. The WM8786 consists
of stereo line level inputs, followed by a sigma-delta modulator and digital filtering.
The WM8786 uses a multi-bit high-order oversampling architecture delivering high SNR operating at
oversampling ratios from 128fs to 32fs according to the sample rate. Sample rates from 8kHz to
192kHz are supported. The WM8786 supports master clock rates from 128fs to 768fs.
The digital filter is a high performance linear phase FIR filter. The digital filters are optimised for each
sample rate. Also included is a high pass filter to remove residual DC offsets from the input signal.
The output from the ADC is available on a configurable digital audio interface. It supports a number
of audio data formats including I2S, Left justified and Right justified or DSP, and can operate in
master or slave modes.
The WM8786 functionality is controlled in hardware via specific pins. It is fully compatible and an
ideal partner for a range of industry standard microprocessors, controllers and DSPs.
The WM8786 can be powered down to reduce system power consumption.
DIGITAL AUDIO INTERFACE
The digital audio interface uses three pins:
•
•
•
DOUT: ADC data output
LRCLK: ADC data alignment clock
BCLK: Bit clock, for synchronisation
The digital audio interface takes the data from the internal ADC digital filters and places it on DOUT
and LRCLK. DOUT is the formatted digital audio data stream output from the ADC digital filters with
left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left
or Right channel data is present on the DOUT line. DOUT and LRCLK are synchronous with the
BCLK signal with each data bit transition signified by a BCLK high to low transition. DOUT is always
an output. BCLK and LRCLK maybe inputs or outputs depending whether the device is in Master or
Slave mode. (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
•
•
•
•
Left justified
Right justified
I2S
DSP
They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for
timing information.
MASTER AND SLAVE MODE OPERATION
The WM8786 can be configured as either a master or slave mode device. As a master device the
WM8786 generates BCLK and LRCLK and thus controls sequencing of the data transfer on DOUT.
In slave mode, the WM8786 responds with data to clocks it receives over the digital audio interface.
The mode can be selected using the MS0 pin. Master and slave modes are illustrated below.
MS0 PIN STATUS
INTERFACE FORMAT
Slave
Low
High
High
Master (@256fs in oversampling ratio = single or dual rate)
Master (@192fs in oversampling ratio = quad rate)
Table 2 Control Interface Mode Selection
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Figure 15a Master Mode
AUDIO DATA FORMATS
Figure 15b Slave Mode
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 16 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 17 Right Justified Audio Interface (assuming n-bit word length)
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In I2S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 18 I2S Justified Audio Interface (assuming n-bit word length)
In DSP/PCM mode, the left channel MSB is available on the 2nd rising edge of BCLK following a
rising edge of LRC. Right channel data immediately follows left channel data. Depending on word
length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the
right channel data and the next sample.
In device master mode, the LRC output will resemble the frame pulse shown in Figure 19. In device
slave mode, Figure 20 it is possible to use any length of frame pulse less than 1/fs, providing the
falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the
next frame pulse.
Figure 19 DSP/PCM Mode Audio Interface (mode A, Master)
Figure 20 DSP/PCM Mode Audio Interface (mode A, Slave)
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AUDIO INTERFACE CONTROL
AUDIO INTERFACE CONTROL
The audio interface is controlled using the AUDIOF0 and AUDIOF1 pins. Dynamically changing the
audio format may cause erroneous operation of the interfaces and is therefore not recommended.
All ADC data is signed 2’s complement. The length of the digital audio data is always 24 bits.
AUDIOF1 PIN STATUS
AUDIOF0 PIN STATUS
AUDIO INTERFACE
FORMAT
Low
Low
High
High
Low
High
Low
High
24-bit right justified
24-bit left justified
24-bit I2S
24-bit DSP
Table 3 Audio Interface Format Selection
OVERSAMPLING RATIOS AND SIGMA-DELTA MODULATOR FREQUENCY
For correct operation of the device and optimal performance, the user must select the appropriate
ADC modulator oversampling ratio. The oversampling ratio is selected using the OSR0 and OSR1
pins.
OSR1 PIN STATUS
OSR0 PIN STATUS
OVERSAMPLING RATIO
CONTROL
Low
Low
High
High
Low
High
Low
High
Single Rate (128fs)
Dual Rate (64fs)
Quad Rate (32fs)
Not Valid
Table 4 Oversampling Ratio Selection
The WM8786 can operate at sample rates from 8kHz to 192kHz. The WM8786 uses a sigma-delta
modulator that operates at frequencies between 1.024MHz and 6.144MHz
SAMPLING RATE
(LRCLK)
OVERSAMPLING RATIO
SIGMA-DELTA
MODULATOR
FREQUENCY (MHZ)
8kHz
32kHz
44.1kHz
48kHz
96kHz
192kHz
Single Rate (128fs)
Single Rate (128fs)
Single Rate (128fs)
Single Rate (128fs)
Dual Rate (64fs)
1.024
4.096
5.6448
6.144
6.144
6.144
Quad Rate (32fs)
Table 5 Sigma-delta Modulator Frequency
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MASTER CLOCK AND AUDIO SAMPLE RATES
The master clock (MCLK) is used to operate the digital filters and the noise shaping circuits. The
WM8786 supports a wide range of master clock frequencies, and can generate many commonly
used audio sample rates directly from the master clock. The following tables show the recommended
Master clock frequencies for different sample rates.
In Master Mode, with oversampling ratio = single rate or dual rate, Master clock frequency of 256 is
supported.
SAMPLING RATE
(LRCLK)
OVERSAMPLING
RATIO
MASTER CLOCK FREQUENCY (MHz)
256fs
8.192
32kHz
44.1kHz
48kHz
Single Rate
Single Rate
Single Rate
Dual Rate
11.2896
12.288
24.576
96kHz
Table 6 Master Mode: Recommended Master Clock Frequency Selection
In Master Mode, with oversampling ratio = quad rate, Master clock frequency of 192 is supported.
SAMPLING RATE
(LRCLK)
OVERSAMPLING
RATIO
MASTER CLOCK FREQUENCY (MHz)
128fs
192kHz
Quad Rate
24.576
Table 7 Master Mode: Recommended Master Clock Frequency Selection
In Slave Mode, Master clock frequencies of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs are supported..
The WM8786 automatically detects the audio sample rate, in slave mode.
SAMPLING RATE
(LRCLK)
OVERSAMPLING
MASTER CLOCK FREQUENCY (MHz)
RATIO
128fs
192fs
256fs
384fs
512fs
768fs
32kHz
44.1kHz
48kHz
Single Rate
Single Rate
Single Rate
Dual Rate
-
-
8.192
11.2896
12.288
24.576
-
12.288
16.9344
18.432
36.864
-
16.384
24.576
-
-
22.5792
33.8688
-
-
24.576
36.864
96kHz
-
-
-
-
-
-
192kHz
Quad Rate
24.576
36.864
Table 8 Slave Mode: Recommended Master Clock Frequency Selection
MLCK AND LRCLK PHASE RELATIONSHIP
The WM8786 does not require a specific phase relationship between MLCK and LRCLK. If the
relationship between MCLK and LRCLK changes by more than +/-8 BCLKs in a 64 BLCK frame, the
WM8786 will attempt to re-synchronise During re-synchronisation, data samples may be dropped or
duplicated.
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WM8786
Pre-Production
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Notes:
1. AGND and DGND should be connected as close to the WM8786 as possible.
2. C1 to C6 should be placed as close to the WM8786 device as possible.
3. Capacitor types should be chosen carefully. Capacitors with very low ESR are recommended for optimum performance, such as X7R. VMID and VREF decoupling
capacitors must be high quality electrolytic capacitors to achieve datasheet performance; ceramic capacitors are not acceptable.
4. An active input filter is required to achieve datasheet performance. The circuit shown is a tested inverting reference example.
Figure 21 External Component Diagram
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Pre-Production
WM8786
PACKAGE DIMENSIONS
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
DM0015.C
b
e
20
11
E1
E
GAUGE
PLANE
Θ
1
10
D
0.25
L
c
A1
A A2
L
1
-C-
C
0.10
SEATING PLANE
Dimensions
(mm)
Symbols
MIN
NOM
MAX
A
A1
A2
b
c
D
e
E
E1
L
-----
0.05-----
1.651.751.85
0.22
0.09
-----
2.0
-----
0.30
-----
7.20
0.38
0.25
7.50
6.90
0.65 BSC
7.80
7.40
5.00
50.7500..955
8.20
5.60
5.30
L1
θ
1.25 REF
4o
0o
8o
-
JEDEC.95, MO 150
REF:
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8786
Pre-Production
IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation
of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical
components in life support devices or systems without the express written approval of an officer of the company. Life
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or
sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be
reasonably expected to result in a significant injury to the user. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual
property right of WM covering or relating to any combination, machine, or process in which such products or services might
be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s
approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and
is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that
product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and
deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
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相关型号：
WM8786GEDS/V
Consumer Circuit, CMOS, PDSO20, 7.20 X 5.30 MM, 1.75 MM HEIGHT, MO-150AE, SSOP-20
CIRRUS
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