X25401S [XICOR]
SPI Serial AUTOSTORE⑩ NOVRAM; 串行SPI ™自动存储NOVRAM
| 型号： | X25401S |
| 厂家： | 
XICOR INC. |
| 描述： | SPI Serial AUTOSTORE⑩ NOVRAM |
| 文件： | 总14页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTE
A V A I L A B L E
AN56
256 Bit
X25401
16 x 16 Bit
SPI Serial AUTOSTORE™ NOVRAM
FEATURES
DESCRIPTION
• 1MHz Clock Rate
The Xicor X25401 is a serial 256 bit NOVRAM featuring
a static RAM configured 16 x 16, overlaid bit-by-bit with
a nonvolatile E PROM array. The X25401 features a
• AUTOSTORE™ NOVRAM
2
—Automatically Performs a Store Operation
Upon Loss of V
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signalsareaclockinput(SCK)plusseparatedatain(SI)
and data out (SO) lines. Access to the device is con-
trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.
CC
• Single 5 Volt Supply
• Ideal for use with Single Chip Microcomputers
—Minimum I/O Interface
—SPI Mode (0,0 & 1,1) Serial Port Compatible
—Easily Interfaced to Microcontroller Ports
• Software and Hardware Control of Nonvolatile
Functions
TheXicorNOVRAMdesignallowsdatatobetransferred
between the two memory arrays by means of software
commands or external hardware inputs. A store opera-
• Auto Recall on Power-Up
• TTL and CMOS Compatible
• Low Power Dissipation
2
tion (RAM data to E PROM) is completed in 5ms or less
2
and a recall operation (E PROM data to RAM) is com-
—Active Current: 10mA
pleted in 2µs or less.
—Standby Current: 50µA
• 8-Lead PDIP and 8-Lead SOIC Packages
The X25401 also includes the AUTOSTORE feature, a
user selectable feature that automatically performs a
• High Reliability
—Store Cycles: 1,000,000
—Data Retention: 100 Years
storeoperationwhenV fallsbelowapresetthreshold.
CC
Xicor NOVRAMs are designed for unlimited write opera-
2
tionstoRAM,eitherfromthehostorrecallsfromE PROM
andaminimum1,000,000storeoperations. Inherentdata
retention is specified to be greater than 100 years.
FUNCTIONAL DIAGRAM
NONVOLATILE
2
E PROM
ORE
ST
STATIC
RAM
256-BIT
RECALL (6)
AS (7)
CONTROL
LOGIC
RECALL
ROW
DECODE
CS (1)
INSTRUCTION
SI (3)
COLUMN
DECODE
SO (4)
REGISTER
SCK (2)
INSTRUCTION
DECODE
4-BIT
COUNTER
2051 FHD F01
AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
COPS is a trademark of National Semiconductor Corp.
© Xicor, Inc. 1992, 1995, 1996 Patents Pending
2051-1.5 8/1/97 T0/C0/D2 SH
Characteristics subject to change without notice
1
X25401
PIN DESCRIPTIONS
PIN CONFIGURATION
Chip Select (CS)
The Chip Select input must be LOW to enable all read/
write operations. CS must remain LOW following a
Read or Write command until the data transfer is com-
plete. CS HIGH places the X25401 in the low power
standby mode and resets the instruction register. There-
fore, CS must be brought HIGH after the completion of
an operation in order to reset the instruction register in
preparation for the next command.
DIP/SOIC
CS
SCK
SI
1
2
3
4
8
7
6
5
V
CC
AS
X25401
RECALL
SO
V
SS
Serial Clock (SCK)
2051 FHD F02
The Serial Clock input is used to clock all data into and
out of the device.
Serial Data In (SI)
SI is the serial data input.
PIN NAMES
Serial Data Out (SO)
Symbol
CS
SCK
SI
Description
Chip Enable
SO is the serial data output. It is in the high impedance
state except during data output cycles in response to a
READ instruction.
Serial Clock
Serial Data In
Serial Data Out
Recall Input
AUTOSTORE Output
+5V
AUTOSTORE Output (AS)
SO
AS is an open drain output which, when asserted indi-
RECALL
AS
cates V has fallen below the AUTOSTORE thresh-
CC
old (V
). AS may be wire-ORed with multiple open
ASTH
V
V
CC
SS
drain outputs and used as an interrupt input to a micro-
controller or as an input to a low power reset circuit.
Ground
2051 PGM T01
RECALL
RECALL LOW will initiate an internal transfer of data
2
from E PROM to the RAM array.
2
X25401
DEVICE OPERATION
reset upon power-up and must be intentionally set by
the user to enable any write or store operations. Al-
though a recall operation is performed upon power-up,
the previous recall latch is not set by this operation.
The X25401 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising edge of SCK. CS must be LOW during the
entire data transfer operation.
WRDS and WREN
Internally the X25401 contains a “write enable” latch.
This latch must be set for either writes to the RAM or
store operations to the E PROM. The WREN instruction
Table 1 contains a list of the instructions and their
operation codes. The most significant bit (MSB) of all
instructions is a logic one (HIGH), bits 6 through 3 are
either RAM address bits (A) or don’t cares (X) and bits
2 through 0 are the operation codes. The X25401
requires the instruction to be shifted in with the MSB
first.
2
sets the latch and the WRDS instruction resets the latch,
2
disabling both RAM writes and E PROM stores, effec-
tively protecting the nonvolatile data from corruption. The
write enable latch is automatically reset on power-up.
STO
After CS is LOW, the X25401 will not begin to interpret
the data stream until a logic “1” has been shifted in on
SI. Therefore, CS may be brought LOW with SCK
running and SI LOW. SI must then go HIGH to indicate
the start condition of an instruction before the X25401
will begin any action.
The software STO instruction will initiate a transfer of
data from RAM to E PROM. In order to safeguard
against unwanted store operations, the following con-
ditions must be true:
2
• STO instruction issued.
In addition, the SCK clock is totally static. The user can
completely stop the clock and data shifting will be
stopped. Restarting the clock will resume shifting of
data.
• The internal “write enable” latch must be set
(WREN instruction issued).
• The “previous recall” latch must be set (either a
software or hardware recall operation).
RCL and RECALL
Once the store cycle is initiated, all other device func-
tions are inhibited. Upon completion of the store cycle,
the write enable latch is reset. Refer to Figure 4 for a
state diagram description of enabling/disabling condi-
tions for store operations.
Either a software RCL instruction or a LOW on the
RECALL input will initiate a transfer of E PROM data
into RAM. This software or hardware recall operation
sets an internal “previous recall” latch. This latch is
2
TABLE 1. INSTRUCTION SET
Instruction
Format, I I I
Operation
2 1 0
WRDS (Figure 3)
STO (Figure 3)
ENAS
1XXXX000
1XXXX001
1XXXX010
1AAAA011
1XXXX100
1XXXX101
1AAAA11X
Reset Write Enable Latch (Disables Writes and Stores)
2
Store RAM Data in E PROM
Enable AUTOSTORE Feature
WRITE (Figure 2)
WREN (Figure 3)
RCL (Figure 3)
READ (Figure 1)
Write Data into RAM Address AAAA
Set Write Enable Latch (Enables Writes and Stores)
2
Recall E PROM Data into RAM
Read Data from RAM Address AAAA
2051 PGM T11
X = Don’t Care
A = Address
3
X25401
WRITE
AUTOSTORE Feature
The WRITE instruction contains the 4-bit address of
the word to be written. The write instruction is immedi-
ately followed by the 16-bit word to be written. CS must
remain LOW during the entire operation. CS must go
HIGH before the next rising edge of SCK. If CS is
brought HIGH prematurely (after the instruction but
before 16 bits of data are transferred), the instruction
register will be reset and the data that was shifted-in
will be written to RAM.
The AUTOSTORE instruction (ENAS) sets the
“AUTOSTORE enable” latch, allowing the X25401 to
automatically perform a store operation when V falls
CC
below the AUTOSTORE threshold (V
).
ASTH
WRITE PROTECTION
The X25401 provides two software write protection
mechanisms to prevent inadvertent stores of unknown
data.
Power-Up Condition
If CS is kept LOW for more than 24 SCK clock cycles
(8-bit instruction plus 16-bit data), the data already
shifted-in will be overwritten.
Upon power-up the “write enable” and “AUTOSTORE
enable” latches are in the reset state, disabling any
store operation.
READ
Unknown Data Store
The READ instruction contains the 4-bit address of the
word to be accessed. Unlike the other six instructions,
The “previous recall” latch must be set after power-up.
It may be set only by performing a software or hard-
ware recall operation, which assures that data in all
RAM locations is valid.
I of the instruction word is a “don’t care”. This provides
0
two advantages. In a design that ties both SI and SO
together, the absence of an eighth bit in the instruction
allows the host time to convert an I/O line from an
output to an input. Secondly, it allows for valid data
output during the ninth SCK clock cycle.
SYSTEM CONSIDERATIONS
Power-Up Recall
All data bits are clocked by the falling edge of SCK
(refer to Read Cycle Diagram).
The X25401 performs a power-up recall that transfers
the E PROM contents to the RAM array. Although the
2
data may be read from the RAM array, this recall does
not set the “previous recall” latch. During this power-up
recall operation, all commands are ignored. Therefore,
the host should delay any operations with the X25401
LOW POWER MODE
When CS is HIGH, non-critical internal devices are
powered-down, placing the device in the standby power
mode, thereby minimizing power consumption.
a minimum of t
after V is stable.
PUR
CC
4
X25401
Figure 1. RAM Read
CS
SCK
SI
1
1
2
3
4
5
6
7
8
9
10
11
12
22
23
24
A
A
A
A
1
1
X*
HIGH Z
SO
D
D
D
D
D
D
D
D
0
1
2
3
13
14
15
0
*Bit 8 of Read Instructions is Don’t Care
2051 FHD F09.1
Figure 2. RAM Write
CS
SK
DI
1
1
2
3
4
5
6
7
8
9
10
11
21
22
23
24
A
A
A
A
0
1
1
D
D
D
D
D
D
D
0
1
2
12
13
14
15
2051 FHD F10.1
Figure 3. Non-Data Operations
CS
SCK
SI
1
2
3
4
5
6
7
8
1
X
X
X
X
I2
I1
I0
2051 FHD F11.1
5
X25401
Figure 4. X25401 State Diagram
POWER
ON
POWER-UP
RECALL
POWER
OFF
RAM READ
RAM
READ
ENABLED
RCL COMMAND
OR RECALL
AUTOSTORE
POWER DOWN
RAM READ
RAM
READ
ENABLED
STO OR
WRDS CMD
STO OR
WREN
WRDS CMD
COMMAND
RAM
READ & WRITE
ENABLED
RAM READ
OR WRITE
RAM
READ & WRITE
ENABLED
RAM READ
OR WRITE
ENAS COMMAND
STORE ENABLED
STORE
ENABLED
AUTOSTORE
ENABLED
WREN
COMMAND
2051 FHD F12.1
6
X25401
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicatedintheoperationalsectionsofthisspecificationis
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Respect to V
....................................... –1V to +7V
SS
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
Industrial
Military
0°C
+70°C
+85°C
+125°C
X25401
5V ±10%
2051 PGM T03.2
–40°C
–55°C
2051 PGM T02.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
l
V
CC
Supply Current
10
mA
SCK = 0.4V/2.4V Levels @ 1MHz,
CC1
(TTL Inputs)
SO = Open, All Other Inputs = V
IH
I
I
I
V
Supply Current
2
1
mA
mA
µA
All Inputs = V , CS = V
IH IL
CC2
SB1
SB2
CC
(During AUTOSTORE)
SO = Open, V = 4.3V
CC
V
CC
Standby Current
SO = Open, CS = V ,
IL
(TTL Inputs)
All Other Inputs = V
IH
V
CC
Standby Current
50
SO = Open, CS = V
SS
(CMOS Inputs)
All Other Inputs = V – 0.3V
CC
I
I
Input Load Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage (AS)
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V
CC
LO
OUT
SS
(1)
V
V
V
V
V
–1
2
0.8
lL
(1)
V
+ 1
CC
V
IH
0.4
V
I
I
I
= 4.2mA
OL
OL
2.4
V
= –2mA
OH
OH
0.4
V
= 1mA
OL (AS)
OL(AS)
2051 PGM T04.3
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
100,000
1,000,000
100
Data Changes Per Bit
Store Cycles
Years
Store Cycles
Data Retention
2051 PGM T05
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Parameter
Max.
Units
Test Conditions
= 0V
(2)
C
OUT
Output Capacitance
Input Capacitance
8
6
pF
pF
V
OUT
(2)
C
IN
V
IN
= 0V
2051 PGM T06.2
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
(2) This parameter is periodically sampled and not 100% tested.
7
X25401
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
5V
Input Pulse Levels
0V to 3V
Input Rise and
Fall Times
919Ω
10ns
1.5V
Input and Output
Timing Levels
OUTPUT
2051 PGM T07.1
100pF
497Ω
2051 FHD F03
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Read and Write Cycle Limits
Symbol
Parameter
Min.
Max.
Units
(3)
F
SCK Frequency
1
MHz
ns
ns
ns
ns
ns
ns
µs
ns
ns
SK
SCKH
SCKL
DS
t
t
t
t
t
t
t
t
t
t
SCK Positive Pulse Width
SCK Negative Pulse Width
Data Setup Time
400
400
400
80
Data Hold Time
DH
SCK to Data Bit 0 Valid
SCK to Data Valid
375
375
1
PD1
PD
Chip Select to Output High Z
Chip Select Setup
Z
800
350
800
CSS
CSH
CDS
Chip Select Hold
Chip Deselect
ns
2051 PGM T08.1
POWER-UP TIMING
Symbol
Parameter
Max.
Units
(4)
t
t
Power-up to Read Operation
200
5
µs
PUR
(4)
Power-up to Write or Store Operation
ms
PUW
2051 PGM T09
Notes: (3) SCK rise and fall times must be less than 50ns.
(4) t and t are the delays required from the time V is stable until the specified operation can be initiated. These parameters
PUR
PUW
CC
are periodically sampled and not 100% tested.
8
X25401
Write Cycle
1/F
SCK
SCK CYCLE #
SCK
t
t
SCKH
SCKL
2
X
1
n
t
t
CDS
t
CSH
CSS
CS
SI
t
t
DH
DS
2051 FHD F04.1
Read Cycle
SK CYCLE #
6
7
8
9
10
n
SCK
CS
t
PD
12
I1
SI
DON’T CARE
t
PD1
t
Z
HIGH Z
HIGH Z
SO
D0
D1
Dn
2051 FHD F05.1
9
X25401
NONVOLATILE OPERATIONS
Previous
Recall Latch
State
Software
Instruction
Write Enable
Latch State
Operation
RECALL
(5)
Hardware Recall
Software Recall
Software Store
0
1
1
NOP
X
X
X
X
RCL
STO
SET
SET
2051 PGM T10
ARRAY RECALL LIMITS
Symbol
Parameter
Min.
Max.
Units
t
t
t
Recall Cycle Time
Recall Pulse Width
2
µs
ns
ns
RCC
RCP
RCZ
(6)
500
Recall to Output in High Z
500
2051 PGM T11
Recall Timing
t
RCC
t
RCP
RECALL
SO
t
RCZ
HIGH Z
2051 FHD F06
SOFTWARE STORE CYCLE LIMITS
Symbol Parameter
(7)
Typ.
Min.
Max.
Units
t
ST
Store Time After Clock 8 of STO Command
2
5
ms
2051 PGM T12.1
Notes: (5) NOP designates when the X25401 is not currently executing an instruction.
(6) Recall rise time must be <10µs.
(7) Typical values are for T = 25°C and nominal supply voltage.
A
10
X25401
AUTOSTORE Cycle Limits
Symbol
Parameter
Min.
Max.
Units
V
V
V
AUTOSTORE Cycle Time
5
ms
V
ASTO
AUTOSTORE Threshold Voltage
AUTOSTORE Cycle End Voltage
4.0
3.5
4.3
ASTH
V
ASEND
2051 PGM T13
AUTOSTORE Cycle Timing Diagrams
V
5
4
3
2
1
CC
V
ASTH
AUTOSTORE CYCLE IN PROGRESS
V
ASEND
t
ASTO
STORE TIME
TIME (ms)
CC
V
t
V
ASTH
0V
t
PUR
t
PUR
ASTO
AS
2051 FHD F08
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
11
X25401
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F01
12
X25401
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.050" TYPICAL
X 45°
0.020 (0.50)
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
13
X25401
ORDERING INFORMATION
X25401
P
T
-V
V
Limits
Device
CC
Blank = 5V ±10%
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 8-Lead Plastic DIP
S = 8-Lead SOIC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967;
4,883,976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. Acriticalcomponentisanycomponentofalifesupportdeviceorsystemwhosefailuretoperformcanbereasonablyexpectedtocausethefailure
of the life support device or system, or to affect its satety or effectiveness.
14
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