X55620V20I-2.7 [XICOR]
Power Supply Management Circuit, Adjustable, 2 Channel, PDSO20, PLASTIC, TSSOP-20;
| 型号： | X55620V20I-2.7 |
| 厂家： | 
XICOR INC. |
| 描述： | Power Supply Management Circuit, Adjustable, 2 Channel, PDSO20, PLASTIC, TSSOP-20 光电二极管 |
| 文件： | 总23页 (文件大小：400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
256K
X55620
Dual Voltage Monitor with Integrated System Battery Switch and EEPROM
FEATURES
• Minimize EEPROM programming time
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 10MHz SPI interface modes (0,0 & 1,1)
• 2.7V to 5.5V power supply operation
• Available packages — 20-lead TSSOP
• Dual voltage monitoring
• Active high and active low reset outputs
• Four standard reset threshold voltages
(4.6/2.9, 4.6/2.6, 2.9/1.6, 2.6/1.6)
—User programmable thresholds
• Lowline Output — Zero delayed POR
• Reset signal valid to V = 1V
CC
DESCRIPTION
• System battery switch-over circuitry
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<30µA max standby current, watchdog off
• Selectable watchdog timer
This device combines power-on reset control, battery
switch circuit, watchdog timer, supply voltage supervi-
sion, secondary voltage supervision, block lock protect
and serial EEPROM in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
—(0.15s, 0.4s, 0.8s, off)
• 256Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
programmable Block Lock™ protection
—In circuit programmable ROM mode
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
BLOCK DIAGRAM
V
OUT
V2FAIL
+
V2MON
V
TRIP2
V2 Monitor
Logic
-
WDO
Watchdog Transition
Detector
Watchdog
Timer Reset
WP
Protect Logic
Data
Register
SO
SI
RESET
Status
Register
Command
Decode, Test
& Control
Logic
Reset &
Watchdog
Timebase
EEPROM Array
512 X 512
SCK
CS
BATT-ON
RESET/MR
LOWLINE
System
Battery
Switch
V
OUT
Power On,
V
V
BATT
OUT
Low Voltage
Reset
Generation
V
+
CC
V
TRIP1
(V1MON)
V
Monitor
-
CC
Logic
Characteristics subject to change without notice. 1 of 23
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X55620 – Preliminary Information
A system battery switch circuit compares V (V1MON)
allow the threshold for either voltage monitor to be
reprogrammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
CC
with V
input and connects V
to whichever is
BATT
OUT
higher. This provides voltage to external SRAM or other
circuits in the event of main power failure. The X55620
can drive 50mA from V
and 250µA from V
. The
ORDERING INFORMATION
X55620
CC
BATT
device switches to V
when V drops below the low
BATT
CC
V
voltage threshold and V
> V
.
CC
BATT
CC
Suffix
V20-4.5A
V20I-4.5A
V20-4.5
Vtrip1 Vtrip2 Temp Range
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
0°C to 70°C
4.6
4.6
2.9
2.6
2.6
2.9
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
V20I-4.5
V20-2.7A
V20I-2.7A
V20-2.7
1.65
1.65
The device’s low V
detection circuitry protects the
CC
user’s system from low voltage conditions, resetting the
system when V (V1MON) falls below the minimum
CC
V20I-2.7
V
V
trip point (V
). RESET/RESET is asserted until
CC
CC
TRIP1
returns to proper operating level and stabilizes. A
second voltage monitor circuit tracks the unregulated
supply or monitors a second power supply voltage to
provide a power fail warning. Xicor’s unique circuits
PIN CONFIGURATION
20-Pin TSSOP
V
(V1MON)
1
20
CS/WDI
NC
CC
WDO
2
3
19
18
SO
RESET/MR
BATT-ON
RESET
LOWLINE
V2FAIL
V2MON
WP
4
5
17
16
V
OUT
V
6
7
15
14
BATT
SCK
NC
NC
SI
8
13
12
11
NC
9
VSS
10
Characteristics subject to change without notice. 2 of 23
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X55620 – Preliminary Information
PIN DESCRIPTION
Pin
Name
Function
1
CS/WDI
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any opera-
tion after power up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET
going active.
2
3
NC
SO
No internal connections
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin.The
falling edge of the serial clock (SCK) clocks the data out.
4
5
6
RESET
Reset Output. RESET is an active HIGH, open drain output which is the inverse of the RESET
output.
LOWLINE Low V Detect. This open drain output signal goes LOW when V < V and
TRIP1
CC
CC
immediately goes HIGH when V > V
. This pin goes LOW 250ns before RESET pin.
CC
TRIP1
V2FAIL
V2MON
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V
TRIP2
and goes HIGH when V2MON exceeds V
pin.
. There is no power up reset delay circuitry on this
TRIP2
7
8
V2 Voltage Monitor Input. When the V2MON input is less than the V
voltage, V2FAIL goes
TRIP2
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V or V
when not used.
SS
CC
WP
NC
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits.
9
No internal connections
Ground
10
11
V
SS
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on
this pin.The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
12
13
14
NC
NC
No internal connections
No internal connections
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.The rising
edge of SCK latches in the opcode, address, or data bits present on the SI pin.The falling edge of
SCK changes the data output on the SO pin.
15
V
Battery Supply Voltage. This input provides a backup supply in the event of a failure of the pri-
BATT
mary V voltage. The V
voltage typically provides the supply voltage necessary to main-
CC
BATT
tain the contents of SRAM and also powers the internal logic to “stay awake.” If unused connect
to ground.
V
BATT
Characteristics subject to change without notice. 3 of 23
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X55620 – Preliminary Information
PIN DESCRIPTION (CONTINUED)
Pin
Name
Function
16
V
Output Voltage. V
= V if V > V
.
OUT
OUT
CC
CC
TRIP1
IF V < V
, then,
CC
TRIP1
V
V
= V if V > V
+0.03
OUT
CC
CC
BATT
= V
if V < V
-0.03
OUT
BATT
CC
BATT
Note: There is hysteresis around V
0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.
BATT
17
18
BATT-ON Battery On. This open drain output goes HIGH when the V switches to V and goes
OUT
BATT
LOW when V
switches to V . It is used to drive an external PNP pass transistor when V
=
OUT
CC
CC
V
and current requirements are greater than 50mA.
OUT
The purpose of this output is to drive an external transistor to get higher operating currents when
the V supply is fully functional. In the event of a V failure, the battery voltage is applied to
CC
OUT
CC
the V
pin and the external transistor is turned off. In this “backup condition,” the battery only
needs to supply enough voltage and current to keep SRAM devices from losing their data-there
is no communication at this time.
RESET
/MR
Output/Manual Reset Input. This is an Input/Output pin.
RESET Output. This is an active LOW, open drain output which goes active whenever V falls
CC
below the minimum V sense level. When RESET is active communication to the device is inter-
CC
rupted. RESET remains active until V rises above the minimum V sense level for 150ms.
CC
CC
RESET also goes active on power up and remains active for 150ms after the power supply
stabilizes.
MR Input. This is an active LOW debounced input. When MR is active, the RESET/RESET pins
are asserted. When MR is released, the RESET/RESET remains asserted for t
released.
, and then
PURST
19
20
WDO
Watchdog Output. WDO is an active low, open drain output which goes active whenever the
watchdog timer goes active. WDO remains active for 150ms, then returns to the inactive state.
V
Supply Voltage/V1 Voltage Monitor Input. When the V1MON input is less than the VTRIP1
voltage, RESET and RESET go ACTIVE.
CC
(V1MON)
PRINCIPLES OF OPERATION
Power On Reset
operating in a power fail or brownout condition. The
RESET signal remains active until the voltage drops
below 1V. These also remain active until V
returns
CC
and exceeds V
for t
.
TRIP1
PURST
Application of power to the X55620 activates a Power
On Reset Circuit. This circuit goes active at about 1V
and pulls the RESET/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
Low V2MON Voltage Monitoring
The X55620 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
of the oscillator. When V
exceeds the device V
mum V
. The V2FAIL signal is either ORed with
CC
TRIP1
TRIP2
value for 150ms (nominal) the circuit releases RESET/
RESET, allowing the processor to begin executing
code.
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. V2FAIL remains active until V2MON
Low V
(V1MON) Voltage Monitoring
returns and exceeds V
.
CC
TRIP2
During operation, the X55620 monitors the V
level
CC
The V2MON voltage sensor is powered by V
. If
OUT
and asserts RESET/RESET if supply voltage falls
below a preset minimum V . During this time the
V
and V
go away (i.e. V
goes away), then
CC
BATT
OUT
TRIP1
V2MON cannot be monitored.
communication to the device is interrupted.The RESET/
RESET signal also prevents the microprocessor from
Characteristics subject to change without notice. 4 of 23
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X55620 – Preliminary Information
Figure 1. Two Uses of Dual Voltage Monitoring
V
OUT
V
OUT
X55620
X55620
Unregulated
Supply
Unregulated
Supply
5V
5V
V
CC
V
Reg
System
Reset
CC
Reg
RESET
RESET
R1
R2
V2MON
System
Interrupt
System
Reset
V2FAIL
V2MON
V2FAIL
V2
3.3V
Reg
R1 and R2 selected so V2 = V2MON threshold when
Unregulated supply reaches 6V.
Notice: No external components required to monitor
two voltages.
Watchdog Timer
the static RAM during a power failure. Typically, when
V
has failed, the SRAMs go into a lower power state
CC
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the CS/WDI pin. The micro-
processor must toggle the CS/WDI pin HIGH to LOW
periodically prior to the expiration of the watchdog time
out period to prevent the WDO signal going active. The
state of two nonvolatile control bits in the Status Regis-
ter determines the watchdog timer period. The micro-
processor can change these watchdog bits by writing
to the status register. The factory default setting dis-
ables the watchdog timer.
and draw much less current than in their active mode.
When V returns, V switches back to V when
V
sis around this battery switch threshold to prevent
oscillations between supplies.
CC
exceeds V
OUT
CC
+ 0.03V. There is a 60mV hystere-
CC
BATT
While V
is connected to V
the BATT-ON pin is
CC
OUT
pulled LOW. The signal can drive an external PNP
transistor to provide additional current to the external
circuits during normal operation.
The Watchdog Timer oscillator stops when in battery
Operation
backup mode. It re-starts when V returns.
CC
The device is in normal operation with V
as long as
CC
System Battery Switch
V
> V
. It switches to the battery backup mode
CC
TRIP1
when V goes away.
CC
As long as V
exceeds the low voltage detect thresh-
CC
old V
, V
is connected to V
through a 5
TRIP1
OUT
CC
Condition
Mode of Operation
Normal Operation.
Ohm (typical) switch. When the V
has fallen below
CC
V
> V
V
, then V
is applied to V
if V
is equal to or
drops to less
CC
TRIP1
TRIP
CC
OUT
CC
greater than V
than V
+ 0.03V. When V
V
V
> V
&
Normal Operation without battery
back up capability.
BATT
CC
CC
TRIP1
= 0
- 0.03V, then V
is connected to V
BATT
BATT
OUT BATT
through an 80 Ohm (typical) switch. V
supplies the system static RAM voltage, so the
switchover circuit operates to protect the contents of
typically
OUT
0 ≤ V
V
Battery Backup Mode; RESET
signal is asserted. No communica-
tion to the device is allowed.
CC TRIP1
and V < V
CC
BATT
Characteristics subject to change without notice. 5 of 23
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X55620 – Preliminary Information
Manual Reset
be same voltage as V2MON). Next, tie the WP pin to
the programming voltage V . Then, send the WREN
command and write to address 01h or to address 0Bh
P
By connecting a push-button from MR to ground or
driven by logic, the designer adds manual system reset
capability. The RESET/RESET pins are asserted when
the push-button is closed and remain asserted for
to program V
or V
, respectively (followed by
TRIP1
TRIP2
data byte 00h). The CS going high after a valid write
operation initiates the programming sequence. Bring
WP LOW to complete the operation.
t
after the push-button is released. This pin is
PURST
debounced so a push-button connected directly to the
device will have both clean falling and rising edges on
MR.
To check if the V
has been set, apply a voltage
TRIPX
higher than V
to the VXMON (x = 1, 2) pin. Dec-
TRIPX
rement VXMON in small steps and observe where the
output switches. The voltage at which this occurs is the
V
(V1MON), V2MON Threshold Programming
CC
Procedure
V
(actual).
TRIPX
The X55620 is shipped with standard V
(V1MON)
CC
and V2MON threshold (V
, V
) voltages.These
CASE A
TRIP1 TRIP2
values will not change over normal operating and stor-
age conditions. However, in applications where the stan-
dard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X55620
trip points may be adjusted. The procedure is described
below, and uses the application of a high voltage control
signal.
If the V
(actual) is lower than the V
TRIPX
TRIPX
TRIPX
TRIPX
(desired), then add the difference between V
(desired) and V (actual) to the original V
(desired). This is your new V
be applied to VXMON and the whole sequence
repeated again (see Fig 6).
TRIPX
voltage that should
TRIPX
CASE B
Setting the V
Voltage
TRIP
If the V
(actual) is higher than the V
TRIPX
This procedure is used to set the V
or V
to a
TRIP2
TRIPX
TRIP1
(desired), perform the reset sequence as described in
the next section. The new V
to VXMON will now be: V
lower or higher voltage value. It is necessary to reset
the trip point before setting the new value to a lower
level.
voltage to be applied
TRIPX
TRIPX
(desired) – (V
TRIPX
(desired) – V
(actual)).
TRIPX
To set the new voltage, apply the desired V
TRIP1
voltage
should
Note: This operation will not alter the contents of the
EEPROM.
threshold voltage to the V
pin or the V
CC
TRIP2
to the V2MON pin (when setting V
, V
TRIP2
CC
Figure 2. Example System Connection
PNP transistor
or P-channel FET
Unregulated
Supply
5V
Reg
V
V
CC
BATT-ON
SRAM
V
OUT
V
OUT
BATT
Address
Decode
V2MON
+
V2FAIL
RESET
Enable
Addr
NMI
V
CC
RESET
µC
SPI
CS, SCK
SI, SO
V
SS
Characteristics subject to change without notice. 6 of 23
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X55620 – Preliminary Information
Resetting the V
Voltage
00h). The CS going LOW to HIGH after a valid write
operation initiates the programming sequence. Bring
WP LOW to complete the operation.
TRIP
To reset V
, apply greater than 3V to V
TRIP1
CC
(V1MON). To reset V
, apply greater than 3V to
TRIP2
both V
and V2MON. Next, tie the WP pin to the
CC
Note: This operation does not change the contents of
the EEPROM array.
programming voltage V . Then send the WREN
command and write to address 03h or 0Dh to reset the
P
V
or V
respectively (followed by data byte
TRIP1
TRIP2
Figure 3. Set V
Level Sequence
TRIPX
V
= 10-15V
P
WP
CS
0
1
2
3
4
5
6
7
0
1
2
3
4 5
6
7
8
9 10
20 21 22 23
SCK
16 Bits
SI
02h
WRITE
0001h/000Bh
ADDRESS
00h
DATA
06h
WREN
Addr 01h: Set V
Addr 0Bh: Set V
TRIP1
TRIP2
Figure 4. Reset V
Level Sequence
TRIPX
V
= 10-15V
P
WP
CS
0
1
2
3
4
5
6
7
0
1
2
3
4 5
6
7
8
9 10
20 21 22 23
SCK
SI
16 Bits
02h
WRITE
0003h/000Dh
ADDRESS
00h
DATA
06h
WREN
Addr 03h: Reset V
TRIP1
Addr 0Dh: Reset V
TRIP2
Characteristics subject to change without notice. 7 of 23
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X55620 – Preliminary Information
Figure 5. Sample V
Circuit
TRIP
4.7K
X55620
V
RESET
µC
P
V
CS
SO
WP
CC
Adjust
Run
RESET
SCK
SCK
SI
V
TRIP
V
SI
Adj.
SS
SO
CS
Figure 6. V
Programming Sequence Flow Chart
TRIP
Vx = VxMON
Note: X = 1, 2
V
Programming
TRIPX
Let: MDE = Maximum Desired Error
Desired
TRIPX
No
V
<
MDE+
Acceptable
Present Value?
Desired Value
YES
Error Range
MDE–
Execute
Reset Sequence
V
TRIPX
Error = Actual - Desired
Set
V
= desired V
Execute
X
TRIPX
New V applied =
X
New V applied =
X
Set Higher
Sequence
V
Old V applied - | Error |
Old V applied + | Error |
TRIPX
X
X
Apply V and Voltage
Execute Reset V
TRIPX
CC
Sequence
> Desired V
to
V
TRIPX
X
NO
Decrease
V
X
Output Switches?
YES
V
Error < MDE–
Error > MDE+
Actual
TRIPX -
V
Desired
TRIPX
| Error | < | MDE |
DONE
Characteristics subject to change without notice. 8 of 23
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X55620 – Preliminary Information
SPI SERIAL MEMORY
Write Enable Latch
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction sets the latch and the WRDI instruc-
tion resets the latch (Figure 9). This latch is automati-
cally reset upon a power-up condition and after the
completion of a valid Write Cycle.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time,
even during a Write Cycle. The Status Register is for-
matted as follows:
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
7
6
5
4
3
2
1
0
WPEN WD1 WD0 PUP BL1 BL0 WEL WIP
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a non-
volatile write operation is in progress. When set to a
“0”, no write is in progress.
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
WRDI
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch
RSDR
WRSR
READ
WRITE
Read Status Register
Write Status Register (Watchdog, block lock, WPEN)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix
WREN CMD Status Register Device Pin
Block
Block
Status Register
WPEN, BL0, BL1,
PUP, WD0, WD1
WEL
WPEN
WP
X
Protected Block Unprotected Block
0
1
1
1
X
1
0
X
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Protected
Writable
Writable
0
X
1
Characteristics subject to change without notice. 9 of 23
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X55620 – Preliminary Information
The Write Enable Latch (WEL) bit indicates the Status
of the Write Enable Latch. When WEL = 1, the latch is
set HIGH and when WEL = 0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time-out Period. These nonvolatile bits are
programmed with the WRSR instruction.
Status Register Bits
Watchdog Time Out
WD1
WD0
(Typical)
0
0
1
1
0
1
0
1
800 milliseconds
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are programmed
using the WRSR instruction and allow the user to pro-
tect one quarter, one half, all or none of the EEPROM
array. Any portion of the array that is block lock pro-
tected can be read but not written. It will remain pro-
tected until the BL bits are altered to disable block lock
protection of that portion of memory.
400 milliseconds
150 milliseconds
disabled (factory setting)
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with
the WP pin to provide an In-Circuit Programmable
Status Register Bits Array Addresses Protected
ROM function (Table 2). WP tied to V and WPEN bit
SS
programmed HIGH disables all Status Register Write
Operations.
BL1
BL0
X55620
None (factory setting)
6000h–7FFFh
0
0
1
1
0
1
0
1
Note 1. Watchdog timer is shipped disabled.
2. The t
time is set to 150ms at the factory.
PURST
4000h–7FFFh
0000h–7FFFh
In Circuit Programmable ROM Mode
This mechanism protects the block lock and Watchdog
bits from inadvertent corruption.
The power on reset time (t
initial power or reset time.There are two standard
settings.
) bit, PUP sets the
PURST
In the locked state (Programmable ROM Mode) the
WP pin is LOW and the nonvolatile bit WPEN is “1”.
This mode disables nonvolatile writes to the device’s
Status Register.
PUP
Time
0
1
150 milliseconds (factory settings)
800 milliseconds
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.
Figure 7. Read EEPROM Array Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
Instruction
16 Bit Address
15 14 13
3
2
1
0
Data Out
High Impedance
7
6
5
4
3
2
1
0
SO
MSB
Characteristics subject to change without notice. 10 of 23
REV 1.13 9/30/02
www.xicor.com
X55620 – Preliminary Information
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting
the WPEN bit in the Status Register to “0” blocks the
WP pin function, allowing writes to the Status Register
when WP is HIGH or LOW. Setting the WPEN bit to “1”
while the WP pin is LOW activates the Programmable
ROM mode, thus requiring a change in the WP pin
prior to subsequent Status Register changes. This
allows manufacturing to install the device in a system
with WP pin grounded and still be able to program the
Status Register. Manufacturing can then load Configu-
ration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to
be protected by setting the block lock bits, and finally
set the “OTP mode” by setting the WPEN bit. Data
changes to protected areas of the device now require a
hardware change.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be “0’s”. The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation.
If the address counter reaches the end of a page and
the clock continues, the counter will roll back to the first
address of the page and overwrite any data that may
have been previously written.
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation will
not be completed (Figure 10).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 11).
Read Sequence
While the write is in progress following a Status Regis-
ter or EEPROM Sequence, the Status Register may be
read to check the WIP bit. During this time the WIP bit
will be high. Refer to Serial Input timing on page 17.
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequen-
tially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation is
terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 7).
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The Write Enable Latch is reset.
– Reset Signal is active for t
.
PURST
To read the Status Register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the Status Register are shifted out on the SO line.
Refer to the Read Status Register Sequence (Figure 8).
Refer to the Serial Output Timing on page 18.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the Write
Enable Latch.
– A valid write command and address must be sent to
the device.
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 9). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the
Write Operation without taking CS HIGH after issuing
the WREN instruction, the Write Operation will be
ignored.
– CS must come HIGH after a multiple of 8 data bits in
order to start a nonvolatile write cycle.
Characteristics subject to change without notice. 11 of 23
REV 1.13 9/30/02
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X55620 – Preliminary Information
Figure 8. Read Status Register Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
Instruction
SI
Data Out
High Impedance
SO
7
6
5
4
3
2
1
0
MSB
Figure 9. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
High Impedance
SO
Characteristics subject to change without notice. 12 of 23
REV 1.13 9/30/02
www.xicor.com
X55620 – Preliminary Information
Figure 10. Write Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
16 Bit Address
15 14 13
Data Byte 1
3
2
1
0
7
6
5
4
3
2
1
0
SI
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Figure 11. Status Register Write Sequence
CS
0
1
2
3
4
5
6
7
8
7
9
10 11 12 13 14 15
SCK
Instruction
Data Byte
6
5
4
3
2
1
0
SI
High Impedance
SO
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Characteristics subject to change without notice. 13 of 23
REV 1.13 9/30/02
www.xicor.com
X55620 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ...................–65°C to +135°C
Storage temperature ........................–65°C to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
respect to V ......................................–1.0V to +7V
SS
D.C. output current
(all output pins except V
) ............................ 5mA
OUT
D.C. Output Current V
.................................. 50mA
OUT
Lead temperature (soldering, 10 seconds).........300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
–40°C
+85°C
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise specified. (V
= 2.7V to 5.5V))
CC
Limits
Symbol
Parameter
Min.
Typ.(5)
Max.
Unit
Test Conditions
(1)
I
V
Supply Current (Active)
mA SCK = V x 0.1/V
x
CC
CC1
CC
CC
0.9 @ 10MHz
(Excludes I
(Excludes I
Memory
) Read Memory array
) Write nonvolatile
1.5
3.0
OUT
OUT
(2)
I
V
Supply Current (Passive)
µA CS = V , Any Input =
CC
CC2
CC
V
or V , V
,
(Excludes I
(Excludes I
(Excludes I
) WDT on, 5V
) WDT on, 2.7V
) WDT off, 5V
50.0
40.0
30.0
90.0
60.0
50.0
SS
CC OUT
OUT
OUT
OUT
RESET, RESET,
LOWLINE = Open
(1)
I
V
Current (Battery Backup Mode)
1
µA
V
V
= 2V, V
= 2.8V,
CC3
CC
CC
BATT
, RESET = Open
(Excludes I
)
OUT
OUT
(3)(7)
(7)
I
V
Current (Excludes I
)
)
1
µA
µA
V
= V
= V
BATT1
BATT
BATT
OUT
OUT
BATT
I
V
Current (Excludes I
0.4
1.0
V
V
,
BATT2
OUT
OUT
BATT
(Battery Backup Mode)
= 2.8V
BATT
V
, RESET = Open
OUT
(7)
(7)
V
V
Output Voltage (V > V
+ 0.03V
– 0.03V
V
V
– 0.05
V
V
-0.02
V
V
I
I
= -5mA
= -50mA
OUT1
CC
BATT
BATT
CC
CC
OUT
OUT
or V > V
)
– 0.5
-0.2
CC
TRIP1
CC
CC
Output Voltage (V < V
V
– 0.2
V
V
I
= -250µA
OUT2
CC
TRIP1
BATT
OUT
and V < V
) {Battery Backup}
CC
V
V
Output (BATT-ON) LOW Voltage
0.4
V
I
I
= 3.0mA (5V)
= 1.0mA (3V)
OLB
OL
OL
Battery Switch Hysteresis
30
-30
mV Power Up
mV Power Down
BSH
(V < V
)
CC
TRIP1
Characteristics subject to change without notice. 14 of 23
REV 1.13 9/30/02
www.xicor.com
X55620 – Preliminary Information
D.C. OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions unless otherwise specified. (V
= 2.7V to 5.5V))
CC
Limits
Symbol
Parameter
Min.
Typ.(5)
Max.
Unit
Test Conditions
RESET/RESET/LOWLINE/WDO
(6)
V
V
Reset Trip Point Voltage
4.5
4.62
4.75
3.0
V
V
V
V
-4.5A and -4.5 versions
-2.7A version
TRIP1
CC
2.85
2.55
2.75
0.4
-2.7 version
V
Output (RESET, RESET, LOWLINE,
WDO) LOW Voltage
I
I
= 3.0mA (5V)
= 1.0mA (3V)
OLR
OL
OL
Second Supply Monitor
(6)
V
V2MON Reset Trip Point Voltage
2.85
2.55
1.6
3.0
2.7
1.7
0.4
V
V
V
V
-4.5 version
TRIP2
-4.5A version
-2.7A and -2.7 version
V
Output (V2FAIL) LOW Voltage
I
I
= 3.0mA (5V)
= 1.0mA (3V)
OLx
OL
OL
SPI Interface
(4)
V
Input (CS, SI, SCK, WP) LOW Voltage
Input (CS, SI, SCK, WP) HIGH Voltage
-0.5
V
x 0.3
V
V
ILx
CC
(4)
V
V
x 0.7
V
+
IHx
CC
CC
0.5
I
Input Leakage Current (CS, SI,
SCK, WP)
10
µA
V
LIx
V
Output (SO) LOW Voltage
0.4
I
I
= 3.0mA (5V)
= 1.0mA (3V)
OLS
OHS
OL
OL
V
Output (SO) HIGH Voltage
V
– 0.8
V
I
= -1.0mA (5V)
OUT
OH
Notes: (1) The device enters the Active state after any start, and remains active until 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or t after a stop ending a write operation.
WC
(2) The device goes into Standby: 200ns after any Stop, except those that initiate a high voltage write cycle; t
after a stop that
WC
initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(3) Negative number indicate charging current, Positive numbers indicate discharge current.
(4) V min. and V max. are for reference only and are not tested.
IL
IH
(5) V = 5V at 25°C.
CC
(6) V
and V
are programmable. See page 22 and 23 for programming specifications and pages 6, 7 and 8 for programming
TRIP1
TRIP2
procedure. For custom programmed levels, contact factory.
(7) Based on characterization data only.
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Test
Max.
8
Unit Conditions
(1)
C
Output Capacitance (SO, RESET, V2FAIL, RESET, LOWLINE, BATT-ON,
WDO)
pF
V
= 0V
OUT
OUT
(1)
C
Input Capacitance (SCK, SI, CS, WP)
6
pF
V
= 0V
IN
IN
Note: (1) This parameter is periodically sampled and not 100% tested.
Characteristics subject to change without notice. 15 of 23
REV 1.13 9/30/02
www.xicor.com
X55620 – Preliminary Information
EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
A.C. TEST CONDITIONS
CC
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
V
V
OUT
OUT
Input rise and fall times
Input and output timing level
10ns
V
x0.5
CC
1.53KΩ
2.06KΩ
RESET/RESET
BATT-ON/LOWLINE/
V2FAIL, WDO
SO
3.03KΩ
30pF
30pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Serial Input Timing
V
= 2.7–5.5V
CC
Symbol
Parameter
Clock Frequency
Min.
Max.
Unit
MHz
ns
f
10
SCK
CYC
t
Cycle Time
100
50
t
CS Lead Time
CS Lag Time
ns
LEAD
t
200
40
ns
LAG
t
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Write Cycle Time
ns
WH
t
40
ns
WL
t
10
ns
SU
t
10
ns
H
(3)
t
t
20
20
ns
RI
(3)
ns
FI
t
50
ns
CS
(4)
t
10
ms
WC
Characteristics subject to change without notice. 16 of 23
REV 1.13 9/30/02
www.xicor.com
X55620 – Preliminary Information
Serial Input Timing
t
CS
CS
t
t
LAG
LEAD
SCK
SI
t
t
t
t
FI
SU
H
RI
MSB IN
LSB IN
High Impedance
SO
Serial Output Timing
Symbol
2.7–5.5V
Parameter
Clock Frequency
Min.
Max.
10
Unit
MHz
ns
f
SCK
t
Output Disable Time
Output Valid from Clock Low
Output Hold Time
50
DIS
t
40
ns
V
t
0
ns
HO
(3)
t
t
Output Rise Time
25
25
ns
RO
(3)
Output Fall Time
ns
FO
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
WC
write cycle.
Characteristics subject to change without notice. 17 of 23
REV 1.13 9/30/02
www.xicor.com
X55620 – Preliminary Information
Serial Output Timing
CS
t
t
t
LAG
CYC
WH
SCK
t
t
t
t
DIS
V
HO
WL
SO
SI
MSB Out
MSB–1 Out
LSB Out
ADDR
LSB IN
Power-Up and Power-Down Timing
V
TRIP1
V
BATT
V
CC
0V
t
RPD
t
t
PURST
PURST
RESET
V
V
CC
BAT
V
OUT
0V
V
V
OUT
OUT
RESET
t
t
VB2
VB1
BATT-ON
Characteristics subject to change without notice. 18 of 23
REV 1.13 9/30/02
www.xicor.com
X55620 – Preliminary Information
V
to LOWLINE Timings
CC
V
V
TRIP
TRIP1
V
CC
t
RPD
t
F
0V
t
RPD
t
R
V
OH
LOWLINE
V
OL
V
TRIP1
V
BATT
0V
V2MON to V2FAIL Timings
V
TRIP2
V2MON
0V
t
RPD2
t
t
RPD2
F
t
R
V
OUT
V2FAIL
RESET/RESET/LOWLINE Output Timing
Symbol Parameter
RESET/RESET Time-out Period
Min.
Typ.(3) Max.
Unit
t
PURST
PUP = 0
PUP = 1
75
500
150
800
250
1200
ms
(1)
t
V
V
to RESET/RESET (Power down only) V
to LOWLINE
TRIP1
10
10
250(4)
20
20
µs
µs
ns
µs
µs
V
RPD
TRIP1
(1)
t
to V2FAIL
RPD2
TRIP2
t
LOWLINE to RESET/RESET delay (Power down only)
100
800
LR
(2)
t
V
V
/V2MON Fall Time
/V2MON Rise Time
1000
1000
1
F
CC
(2)
t
R
CC
V
Reset Valid V
CC
RVALID
t
V
V
+ 0.03 v to BATT-ON (logical 0)
- 0.03 v to BATT-ON (logical 1)
20(4)
20(4)
µs
µs
VB1
BATT
BATT
t
VB2
Notes: (1) This parameter is not 100% tested.
(2) This measurement is from 10% to 90% of the supply voltage.
(3) V = 5V at 25°C.
CC
(4) Based on characterization data only.
Characteristics subject to change without notice. 19 of 23
REV 1.13 9/30/02
www.xicor.com
X55620 – Preliminary Information
CS/WDI vs. WDO Timing
CS/WDI
t
CST
WDO
t
t
RST
t
t
RST
WDO
WDO
RESET/RESET Output Timing
Symbol
Parameter
Min.
Typ.(1)
Max.
Unit
t
Watchdog Time Out Period,
WD1 = 1, WD0 = 0
WDO
75
200
500
150
400(2)
800(2)
250
600
1200
ms
ms
ms
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
t
CS Pulse Width to Reset the Watchdog
Reset Time Out
400
75
ns
CST
t
150
250
ms
RST
Notes: (1) V = 5V at 25°C.
CC
(2) Based on characterization data only.
V
Set/Reset Conditions
TRIP
V
TRIPX
V
/V2MON
CC
t
TSU
t
THD
V
P
WP
t
VPH
t
VPS
t
PCS
t
VPO
CS
t
WC
8
clocks
SCK
0n
SI
* 0001h Set V
* 0003h Set V
* 000Bh Reset V
* 000Dh Reset V
* all others reserved
06h
02h
TRIP1
TRIP2
X = 1, 2
TRIP1
TRIP2
Characteristics subject to change without notice. 20 of 23
REV 1.13 9/30/02
www.xicor.com
X55620 – Preliminary Information
V
, V
Programming Specifications V = 2.7-5.5V; Temperature = 25°C
TRIP1 TRIP2
CC
Parameter
Description
Min. Max. Unit
t
WP V
WP V
Program Voltage Setup time
Program Voltage Hold time
10
10
10
10
µs
µs
µs
ms
ms
ms
V
VPS
VPH
TRIPX
t
TRIPX
t
V
V
V
Level Setup time
TSU
THD
TRIPX
TRIPX
TRIPX
t
Level Hold (stable) time
Write Cycle Time
t
10
WC
t
WP V
Program Voltage Off time before next cycle
1
VPO
TRIPX
V
Programming Voltage
10
15
5.0
+25
P
V
V
Programed Voltage Range
2.5
-25
V
TRAN
TRIPX
TRIPX
V
V
Program variation after programming (0–75°C). (Programmed at 25°C
mV
tv
according to the procedure defined on pages 6, 7 and 8.)
V
programming parameters are periodically sampled and are not 100% tested.
TRIPX
Characteristics subject to change without notice. 21 of 23
REV 1.13 9/30/02
www.xicor.com
X55620 – Preliminary Information
PACKAGING INFORMATION
20-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 22 of 23
REV 1.13 9/30/02
www.xicor.com
X55620 – Preliminary Information
Part Mark Information
X55620
YYww
W
X
V20 = 20-Lead TSSOP
Date
Code
Part
V
V
Operating
TRIP1
TRIP2
Mark
Range
Range
Temperature Range
Part Number
X55620V20-4.5A
X55620V20I-4.5A
X55620V20-4.5
X55620V20I-4.5
X55620V20-2.7A
X55620V20I-2.7A
X55620V20-2.7
X55620V20I-2.7
Blank
I
4.5–4.75V
2.55–2.7V
0°C–70°C
-40°C–85°C
0°C–70°C
AL
AM
F
4.5–4.75V
2.85–3.0V
2.55–2.75V
2.85–3.0V
1.6–1.7V
1.6–1.7V
-40°C–85°C
0°C–70°C
G
-40°C–85°C
0°C–70°C
AN
AP
-40°C–85°C
©Xicor, Inc. 2001 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 23 of 23
REV 1.13 9/30/02
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