X84041SI-3 [XICOR]
Micro Port Saver E2PROM; 微型端口节电器E2PROM
| 型号： | X84041SI-3 |
| 厂家： | 
XICOR INC. |
| 描述： | Micro Port Saver E2PROM |
| 文件： | 总13页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTES AND DEVELOPMENT SYSTEM
A V A I L A B L E
AN10 • AN17 • AN57 • XK84
™ 2
4K
X84041
MPS E PROM
Micro Port Saver E2PROM
FEATURES
DESCRIPTION
• Direct Interface to Micros
The X84041 Micro Port Saver is a 4096-bit CMOS
E PROM designed for a direct interface to port limited
2
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminatesneedforparalleltoserialconverters
• 3.3Mbps data transfer rate
• Low Power CMOS
microcontroller or I/O limited microprocessor designs.
The X84041 provides all of the benefits of serial memo-
ries, such as low cost, low power, low voltage operation,
and small package size, while featuring higher data
transferratesandreducedinterfacecoderequirements—
without the need for a dedicated serial bus. The X84041
is organized as a 512 x 8, but is also suitable in 16-bit or
32-bit environments, due to the bit serial nature of the
interface.
—2.7V to 5.5V Operation
—Standby Current Less than 50µA
—Active Current Less than 1mA
• 45ns Read Access Time
• 8-Byte Page Write Mode
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• 8-Lead PDIP, 8-Lead SOIC, and
14-Lead TSSOP Packages
The X84041 directly connects to the processor bus and
communicates over a single data line using a sequence
of standard bus read and write operations. This elimi-
nates the need for dedicated port pins, parallel to serial
converters,complicatedASICimplementations,orother
glue logic, lowering system cost.
PIN CONFIGURATION
BLOCK DIAGRAM
WP
H.V. GENERATION
TIMING & CONTROL
DIP/SOIC
1
2
3
4
8
7
6
5
CE
I/O
V
CC
NC
OE
WE
X84041
CE
OE
WE
I/O
WP
COMMAND
DECODE
AND
CONTROL
LOGIC
EEPROM
ARRAY
V
SS
X
DEC
2704 ILL F01.2
512 x 8
TSSOP
X84041
1
14
Y DECODE
DATA REGISTER
2704 ILL F02
CE
V
CC
2
3
4
5
6
7
13
12
11
10
9
I/O
NC
NC
NC
WP
NC
NC
NC
NC
OE
WE
PIN NAMES
I/O
Data Input/Output
Chip Enable Input
Output Enable Input
Write Enable Input
Write Protect Input
Supply Voltage
Ground
CE
OE
WE
WP
8
V
SS
2704 ILL F02a.1
V
CC
V
SS
NC
No Connect
2704 PGM T01
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
2704-4.4 6/12/96 T3/C1/D0 NS
Characteristics subject to change without notice
1
X84041
A Write Protect (WP) pin provides hardware protection
Read Sequence
against inadvertent writes to the memory.
A read sequence consists of sending a 16-bit address
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and CE
LOW, OE HIGH) to the part without a read cycle be-
tweenthewritecycles.Theaddressissentserially,most
significant bit first, over the I/O line. Note that this
sequence is fully static, with no special timing restric-
tions, andtheprocessorisfreetoperformothertaskson
the bus whenever the X84041 CE pin is HIGH. Once the
16 address bits are sent, a byte of data can be read on
the I/O line by issuing 8 separate read cycles (OE and
CE LOW, WE HIGH). At this point, issuing a reset
sequence will terminate the read sequence, otherwise
the X84041 will await further reads in the sequential
read mode.
2
Xicor E PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is dese-
lected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
X84041 is in the standby power mode.
Output Enable (OE)
Sequential Read
The Output Enable input must be LOW to enable the
output buffer and to read data from the X84041 on the
I/O line.
The byte address is automatically incremented to the
next higher address after each byte of data is read. The
data stored in the memory at the next address can be
read sequentially by continuing to issue read cycles.
When the highest address is reached ($1FF), the ad-
dress counter rolls over to address $000 and reading
may be continued indefinitely.
Write Enable (WE)
TheWriteEnableinputmustbeLOWtowriteeitherdata
or command sequences to the X84041.
Data In/Data Out (I/O)
Data and command sequences are serially written to or
serially read from the X84041 through the I/O pin.
Reset Sequence
The reset sequence resets the X84041 and sets an
internalwriteenablelatch.Aresetsequencecanbesent
at any time by performing a read/write “0”/read se-
quence (see Figs. 1 and 2). This sequence breaks the
multiple read or write cycle sequences that are normally
used when reading from or writing to the part. This
sequence can be used at any time to interrupt or end a
sequential read or page load. As soon as the write “0”
cycle is complete, the part is reset (unless a nonvolatile
write cycle is in progress). The second read cycle in this
sequence, and any further read cycles, will read a HIGH
on the l/O pin until a valid read sequence is issued. The
reset sequence must be issued at the beginning of both
read and write sequences to be sure the X84041
initiates these operations properly.
Write Protect (WP)
When the Write Protect input is LOW, nonvolatile writes
to the X84041 are disabled. When WP is HIGH, all
functions,includingnonvolatilewrites,operatenormally.
Ifanonvolatilewritecycleisinprogress, WP goingLOW
will have no effect on the cycle already underway, but
will inhibit any additional nonvolatile write cycles.
DEVICE OPERATION
2
The X84041 is a serial 512 x 8 bit E PROM designed to
interfacedirectlywithmostmicroprocessorbuses.Stan-
dard CE, OE, and WE signals control the read and write
operations, and a single l/O line is used to send and
receive data and commands serially.
Data Timing
Data input on the l/O line is latched on the rising edge of
either WE or CE, whichever occurs first. Data output on
thel/OlineisactivewheneverbothOE andCEareLOW.
Care should be taken to ensure that WE and OE are
never both LOW while CE is LOW.
2
X84041
Figure 1. Read Sequence
CE
OE
WE
"0"
I/O (IN)
X
X
X
X
X
X
X A8 A7 A6 A5 A4 A3 A2 A1 A0
I/O (OUT)
D7 D6 D5 D4 D3 D2 D1 D0
RESET
LOAD ADDRESS
READ DATA
2704 ILL F03
Write Sequence
where data loading can continue. For this reason, send-
ing more than 64 consecutive data bits will result in
overwriting previous data. A nonvolatile write cycle will
not start if a partial or incomplete write sequence is
issued. The internal write enable latch is reset when the
nonvolatile write cycle is completed to prevent inadvert-
ent writes. Note that this sequence is fully static, with no
special timing restrictions. The processor is free to
perform other tasks on the bus whenever the chip
enable pin (CE) is HIGH.
Anonvolatilewritesequenceconsistsofsendingareset
sequence, a 16-bit address (the first 7 of which are don’t
cares), up to 8 bytes of data, and then a special “start
nonvolatile write cycle” command sequence. The reset
sequence is issued first (as described in the Reset
Sequence section) to set the internal write enable latch.
The address is written serially by issuing 16 separate
write cycles (WE and CE LOW, OE HIGH) to the part
without any read cycles between the writes. The ad-
dress is sent serially, most significant bit first, on the l/O
pin. Uptoeightbytesofdataarewrittenbyissuingeither
8, 16, 24, 32, 40, 48, 56, or 64 separate write cycles.
Again, no read cycles are allowed between writes. The
nonvolatile write cycle is initiated by issuing a special
read/write “1”/read sequence. The first read cycle ends
thepageload, thenthewrite“1”followedbyareadstarts
the nonvolatile write cycle. The X84041 recognizes 8-
bytepagesbeginningataddressesXXXXXX000. When
sending data to the part, attempts to exceed the upper
address of the page will result in the address counter
“wrapping-around” to the first address on the page,
Nonvolatile Write Status
Thestatusofanonvolatilewritecyclecanbedetermined
at any time by simply reading the state of the l/O pin on
the X84041. This pin is read when OE and CE are LOW
and WE is HIGH. During a nonvolatile write cycle the l/
O pin is LOW. When the nonvolatile write cycle is
complete, the l/O pin goes HIGH. A reset sequence can
also be issued during a nonvolatile write cycle with the
same result: I/O is LOW as long as a nonvolatile write
cycle is in progress, and l/O is HIGH when the nonvola-
tile write cycle is done.
3
X84041
Figure 2. Write Sequence
CE
OE
WE
"0"
I/O (IN)
X
X
X
X
X
X
X A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
"1"
"0"
I/O (OUT)
RESET
LOAD ADDRESS
LOAD DATA
START
NONVOLATILE
WRITE
2704 ILL F04
Write Protection
SYMBOL TABLE
The following circuitry has been included to prevent
inadvertent nonvolatile writes:
WAVEFORM
INPUTS
OUTPUTS
— The internal Write Enable latch is reset upon
power-up.
Must be
steady
Will be
steady
May change
from LOW to
HIGH
Will change
from LOW to
HIGH
— A reset sequence must be issued to set the internal
write enable latch before starting a write sequence.
May change
Will change
— A special “start nonvolatile write” command
sequence is required to start a nonvolatile write
cycle.
from HIGH to from HIGH to
LOW
LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
— The internal Write Enable latch is reset automatically
at the end of a nonvolatile write cycle.
N/A
Center Line
is High
Impedance
— The internal Write Enable latch is reset and remains
reset as long as the WP pin is LOW, which blocks all
nonvolatile write cycles.
4
X84041
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Terminal Voltage with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this speci-
fication is not implied. Exposure to absolute maximum
ratingconditionsforextendedperiodsmayaffectdevice
reliability.
Respect to V
....................................... –1V to +7V
SS
DC Output Current ............................................... 5mA
Lead Temperature (Soldering, 10 seconds)...... 300°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
X84041
Limits
5V ±10%
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
–40°C
+85°C
X84041 – 3
3V ±10%
†
2704 PGM T02.2
X84041 – 2.7
2.7V to 5.5V
2704 PGM T03.2
† Contact factory for availability.
D.C. OPERATING CHARACTERISTICS (VCC = 5V ±10%)
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol Parameter
Min.
Max.
Units Test Conditions
I
I
I
V
V
V
Supply Current (Read)
Supply Current (Write)
Standby Current
1
mA
mA
µA
OE = V , WE = V ,
IL IH
I/O = Open, CE clocking @ 2MHz
CC1
CC2
SB
CC
CC
CC
3
I
CC
During Nonvolatile Write Cycle
All Inputs at CMOS Levels
50
CE = V , Other Inputs = V or V
CC CC SS
V
V
V
= 5V ±10%
CC
I
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
= V to V
SS CC
LI
IN
= V to V
CC
LO
OUT
SS
V
V
V
V
(1)
(1)
–1
V
x 0.3
lL
CC
CC
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
V
x 0.7
V
+ 0.5
V
IH
OL
CC
0.4
V
I
I
= 2.1mA, V = 5V ±10%
OL CC
– 0.8
V
= –1mA, V = 5V ±10%
OH CC
OH
CC
2704 PGM T04.3
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
5
X84041
D.C. OPERATING CHARACTERISTICS (VCC = 3V ±10%)
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol Parameter
Min.
Max.
Units Test Conditions
I
I
I
V
V
V
Supply Current (Read)
Supply Current (Write)
Standby Current
250
µA
mA
µA
OE = V , WE = V ,
IL IH
I/O = Open, CE clocking @ 2MHz
CC1
CC2
SB1
CC
CC
CC
1
I
CC
During Nonvolatile Write Cycle
All Inputs at CMOS Levels
10
CE = V , Other Inputs = V or V
CC CC SS
V
V
V
= 3V ±10%
CC
I
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
= V to V
SS CC
LI
IN
= V to V
CC
LO
OUT
SS
(1)
V
V
V
V
–1
V
x 0.3
lL
CC
CC
(1)
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
V
x 0.7
V
+ 0.5
V
IH
CC
0.4
V
I
I
= 1mA, V = 3V ±10%
OL CC
OL
OH
– 0.4
V
= –400µA, V = 3V ±10%
OH CC
CC
2704 PGM T05.2
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
CAPACITANCE
TA = +25°C, f = 1MHz, VCC = 5V
Symbol
Parameter
Max.
Units
pF
Test Conditions
(2)
C
C
Input/Output Capacitance
Input Capacitance
8
6
V
V
= 0V
= 0V
I/O
I/O
IN
(2)
pF
IN
2704 PGM T06.2
Notes: (2) Periodically sampled, but not 100% tested.
POWER-UP TIMING
Symbol
Parameter
Max.
Units
(3)
t
t
Power-up to Read Operation
Power-up to Write Operation
2
5
ms
ms
PUR
(3)
PUW
2704 PGM T07
Notes: (3) Time delays required from the time the V is stable until the specific operation can be initiated.
CC
Periodically sampled, but not 100% tested.
A.C. CONDITIONS OF TEST
Input Pulse Levels
V
CC
x 0.1 to V x 0.9
CC
Input Rise and Fall Times
5ns
Input and Output
Timing Levels
V
x 0.5
CC
2704 PGM T08.1
6
X84041
EQUIVALENT A.C. LOAD CIRCUITS
3V
5V
2.39KΩ
2.06KΩ
OUTPUT
4.58KΩ
OUTPUT
3.03KΩ
30pF
30pF
2704 ILL F05a.3
2704 ILL F05.2
A.C. CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits – X84041
V
CC
= 5V ±10%
V
= 3V ±10%
CC
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
ns
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
300
300
RC
CE Access Time
OE Access Time
CE LOW Time
CE HIGH Time
CE LOW to Output In Low Z
CE HIGH to Output In High Z
OE LOW to Output In Low Z
OE HIGH to Output In High Z
Output Hold from CE or OE HIGH
WE HIGH Setup Time
WE HIGH Hold Time
45
45
65
65
ns
CE
ns
OE
70
70
0
70
70
0
ns
LOW
HIGH
ns
(4)
ns
LZ
(4)
HZ
0
30
30
0
35
35
ns
(4)
0
0
ns
OLZ
OHZ
OH
(4)
0
0
ns
0
0
ns
25
25
25
25
ns
WES
WEH
ns
2704 PGM T09.3
Notes: (4) Periodically sampled, but not 100% tested. t and t
are measured from the point where CE or OE goes
OHZ
HZ
HIGH (whichever occurs first) to the time when I/O is no longer being driven into a 5pF load.
7
X84041
Read Cycle
t
RC
t
t
HIGH
LOW
t
CE
CE
WE
OE
t
WES
t
OE
t
WEH
t
OHZ
HIGH Z
I/O
DATA
t
OH
t
t
OLZ
LZ
t
2704 ILL F06
HZ
Write Cycle Limits – X84041
V
= 5V ±10%
Max.
V
= 3V ±10%
Max.
CC
CC
Symbol
Parameter
Min.
Min.
Units
ms
ns
(5)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Nonvolatile Write Cycle Time
Write Cycle Time
10
10
NVWC
300
30
300
30
WC
WE Pulse Width
WE HIGH Recovery Time
Write Setup Time
ns
WP
200
0
200
0
ns
WPH
CS
ns
Write Hold Time
0
0
ns
CH
CE Pulse Width
30
30
ns
CP
CE HIGH Recovery Time
OE HIGH Setup Time
OE HIGH Hold Time
Data Setup Time
200
50
200
50
ns
CPH
OES
OEH
ns
50
50
ns
(6)
30
30
ns
DS
(6)
Data Hold Time
5
5
ns
DH
(7)
(7)
(7)
WP HIGH Before CE
WP HIGH After CE
WP HIGH Before WE
WP HIGH After WE
500
500
500
500
500
500
500
500
ns
WPCS
WPCH
ns
ns
WPWS
WPWH
(7)
ns
2704 PGM T10.3
Notes: (5) t
is the time from the falling edge of OE or CE (whichever occurs last) of the second read cycle in the
NVWC
“start nonvolatile write cycle” sequence until the self-timed, internal nonvolatile write cycle is completed.
(6) Data is latched into the X84041 on the rising edge of CE or WE, whichever occurs first.
(7) Periodically sampled, but not 100% tested.
8
X84041
CE Controlled Write Cycle
t
CPH
t
CP
CE
t
t
OEH
OES
OE
WE
WP
I/O
t
CS
t
CH
t
WP
t
WPH
t
t
WPCS
WPCH
t
t
DS
DH
HIGH Z
DATA
2704 ILL F07
t
WC
WE Controlled Write Cycle
t
CPH
t
CP
CE
t
OES
t
OE
WE
WP
I/O
CS
t
CH
t
OEH
t
WPH
t
WP
t
WPWH
t
WPWS
t
t
DS
DH
HIGH Z
DATA
2704 ILL F08
t
WC
9
X84041
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F01
10
X84041
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.050" TYPICAL
X 45°
0.020 (0.50)
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
11
X84041
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.002 (.05)
.0118 (.30)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F32
12
X84041
ORDERING INFORMATION
X84041
X
X
-X
V
CC
Range
Device
Blank = 4.5V to 5.5V
3 = 2.7V to 3.3V
2.7 = 2.7V to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
P = 8-Lead Plastic DIP
S = 8-Lead SOIC
V = 14-Lead TSSOP
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
13
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