X9421WV-2.7 [XICOR]
Single Digitally Controlled (XDCP) Potentiometer; 单数控（ XDCP ）电位计
| 型号： | X9421WV-2.7 |
| 厂家： | 
XICOR INC. |
| 描述： | Single Digitally Controlled (XDCP) Potentiometer |
| 文件： | 总21页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTES
A V A I L A B L E
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Noise/Low Power/SPI Bus
X9421
Single Digitally Controlled (XDCP) Potentiometer
FEATURES
DESCRIPTION
• Single Voltage Potentiometer
The X9421 integrates a single digitally controlled
• 64 Resistor Taps
potentiometer (XDCP) on
integrated circuit.
a
monolithic CMOS
• SPI Serial Interface for write, read, and transfer
operations of the potentiometer
• Wiper Resistance, 150Ω Typical at 5V
• 4 Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads SavedWiper Position on
Power Up.
The digital controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and a four non-
volatile Data Registers that can be directly written to
and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
• Standby Current < 5µA Max
• V
: 2.7V to 5.5V Operation
CC
• 2.5KΩ, 10KΩ End to End Resistance
• 100 yr. Data Retention
• Endurance: 100, 000 Data Changes per Bit per
Register
• 14-Lead TSSOP, 16-Lead SOIC
• Low Power CMOS
The XDCP can be used as
a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
V
R /V
CC
H
H
write
read
10KΩ
transfer
inc / dec
address
data
status
Power On Recall
64-taps
wiper
Wiper Counter
Register (WCR)
Bus
Interface &
Control
POT
SPI
bus
interface
Data Registers
4 Bytes
control
R
/V
W
V
R /V
W
SS
L
L
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X9421
DETAILED FUNCTIONAL DIAGRAM
V
CC
Power On Recall
WIPER
10KΩ
64--taps
DR0
DR1
R /V
H
H
HOLD
COUNTER
REGISTER
(WCR)
DR2 DR3
Control
DATA
R /V
L
CS
SCK
SO
L
INTERFACE
AND
CONTROL
R
/V
W
W
CIRCUITRY
SI
A0
WP
V
SS
CIRCUIT LEVEL APPLICATIONS
SYSTEM LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF
wireless systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Trim offset and gain errors in artificial intelligent
systems
• Provide a control variable (I, V, or R) in feedback
circuits
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X9421
PIN CONFIGURATION
TSSOP
SOIC
V
S0
NC
NC
CC
14
13
12
11
10
1
2
3
4
5
6
7
V
CC
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R /V
NC
L
L
SO
NC
R /V
L
R /V
L
H
H
R
/V
R /V
H
CS
CS
W
W
H
X9421
X9421
SCK
SCK
SI
R /V
W W
HOLD
A0
HOLD
A0
SI
9
8
VSS
WP
NC
VSS
WP
PIN ASSIGNMENTS
TSSOP pin
SOIC pin
Symbol
SO
Brief Description
1
2
2
3
Serial Data Output
No Connect
NC
3
NC
No Connect
4
4
5
CS
Chip Select
5
SCK
SI
Serial Clock
6
6
Serial Data Input
System Ground
Hardware Write Protect
Device Address
7
8
V
SS
8
9
WP
A0
9
10
11
12
13
14
16
1
10
11
12
13
14
HOLD
Device select. Pause the serial bus.
Wiper Terminal of the Potentiometer.
High Terminal of the Potentiometer.
Low Terminal of the Potentiometer.
System Supply Voltage
No Connect
R
/ V
W
W
H
L
R / V
H
R / V
L
V
CC
NC
NC
NC
7
No Connect
15
No Connect
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X9421
PIN DESCRIPTIONS
Potentiometer Pins
V /R , V /R
L
Host Interface Pins
H
H
L
The V /R and V /R inputs are equivalent to the
terminal connections on either end of a mechanical
H
H
L
L
Serial Output (SO)
potentiometer.
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
V /R
W
W
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the potentiometer
and pot register are input on this pin. Data is latched by
the rising edge of the serial clock.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers. Writing to the Wiper Counter
Register is not restricted.
Serial Clock (SCK)
System/Digital Supply (V
)
The SCK input is used to clock data into and out of the
X9421.
CC
V
V
is the supply voltage for the system/digital section.
is the system ground.
CC
SS
Chip Select (CS)
PRINCIPLES OF OPERATION
The X9421 is highly integrated microcircuit
incorporating a resistor array and associated registers
and counter and the serial interface logic providing
direct communication between the host and the XDCP
potentiometer.
When CS is HIGH, the X9421 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9421, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
a
Serial Interface
Hold (HOLD)
The X9421 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
Device Address (A )
The X9421 is comprised of one resistor array
containing 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V /R and V /R inputs).
0
The address input is used to set the least significant bit
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address
input in order to initiate communication with the X9421.
A maximum of 2 devices may occupy the SPI serial
bus.
H
H
L
L
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X9421
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
Data Registers
The potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the WCR. It should be noted all
operations changing data in one of the Data Registers is
a nonvolatile operation and will take a maximum of 10ms.
(V /R ) output. Within the individual array only one
W
W
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches. The
block diagram of the potentiometer is shown in Figure 1.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Wiper Counter Register (WCR)
The X9421 contains a Wiper Counter Register. The
WCR can be envisioned as a 6-bit parallel and serial
load counter with its outputs decoded to select one of
sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (DR0) upon power-up.
Register Descriptions
Table 1. Data Registers, (6-bit), Nonvolatile
0
0
D5
D4
D3
D2
D1
D0
(MSB)
(LSB)
There are four 6-bit Data Registers associated with the
potentiometer.
– {D5~D0}: These bits are for general purpose Nonvol-
atile data storage or for storage of up to four different
wiper values.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9421 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Table 2. Wiper Counter Register, (6-bit), Volatile
0
0
WP5 WP4 WP3 WP2 WP1 WP0
(MSB)
(LSB)
– {WP5~WP0}:These bits specify the wiper position of
the potentiometer.
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X9421
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
V
Serial
Bus
Input
H
From Interface
Circuitry
C
O
U
N
T
Register 0
Register 1
8
6
Parallel
Bus
Input
E
R
Wiper
D
E
C
O
D
E
REGISTER 2
REGISTER 3
Counter
Register
(WCR)
INC/DEC
Logic
IF WCR = 00[H] THEN V = V
W
L
UP/DN
IF WCR = 3F[H] THEN V = V
UP/DN
W
H
V
V
L
Modified SCK
CLK
W
Write in Process
Figure 2. Address/Identification Byte Format
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command.
Device Type
Identifier
0
1
0
1
1
1
0
A0
Device Address
INSTRUCTIONS
Instruction Byte
Address/Identification (ID) Byte
The next byte sent to the X9421 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next two
bits point to one of four Data Registers. The format is
shown below in Figure 3.
The first byte sent to the X9421 from the host, following
a CS going HIGH to LOW, is called the Address or
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9421 this is fixed as 0101[B] (refer to Figure 2).
The least significant bit in the ID byte selects one of
two devices on the bus. The physical device address is
Figure 3. Instruction Byte Format
Register
Select
defined by the state of the A input pin. The X9421
0
compares the serial data stream with the address input
state; a successful compare of the address bit is
required for the X9421 to successfully continue the
I3
I2
I1
I0
R1 R0
0
0
command sequence. The A input can be actively
0
driven by a CMOS input signal or tied to V or V
.
CC
SS
Instructions
The remaining three bits in the ID byte must be set to
110.
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X9421
The four high order bits of the instruction byte specify
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9421; either between the host and one
of the Data Registers or directly between the host and
the WCR.These instructions are:
the operation. The next two bits (R and R ) select one
1
0
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
are defined as 0.
Two of the eight instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– Read Wiper Counter Register—read the current
wiper position of the pot,
– Write Wiper Counter Register—change current wiper
position of the pot,
– XFR Data Register to Wiper Counter Register —This
instruction transfers the contents of one specified
Data Register to the Wiper Counter Register.
– Read Data Register—read the contents of the
selected data register;
– XFR Wiper Counter Register to Data Register—This
instruction transfers the contents of the Wiper
Counter Register to the specified associated Data
Register.
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
wiper to this action will be delayed by t
. A transfer
WRL
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t
to complete. The transfer can occur
capability to the host. For each SCK clock pulse (t
)
WR
HIGH
between the potentiometer and one of its associated
registers.
while SI is HIGH, the selected wiper will move one
resistor segment towards the V /R terminal. Similarly,
H
H
for each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the
V /R terminal. A detailed illustration of the sequence
L
L
and timing for this operation are shown in Figure 7 and
Figure 8.
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
1
0
1
1
1
0
A0 I3 I2
I1 I0 R1 R0
0
0
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X9421
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
1
1
0
1
0
1
0
A0
I3 I2
I1 I0 R1 R0
0
0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
Don’t Care
1
1
0
1
0
1
0
A0
I3 I2
I1 I0 R1 R0
0
0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
0
1
0
1
1
1
0
A0
I3 I2
I1 I0
0
0
0
0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Figure 8. Increment/Decrement Timing Limits
t
WRID
SCK
SI
Voltage Out
V
W
INC/DEC CMD Issued
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X9421
Table 3. Instruction Set
Instruction Set
Instruction
I
I
I
I
R
R
0
Operation
3
2
1
0
1
Read Wiper Counter
Register
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
Read the contents of the Wiper Counter Register
Write Wiper Counter
Register
0
0
Write new value to the Wiper Counter Register
Read the contents of the Data Register pointed to
Read Data Register
Write Data Register
1/0 1/0
1/0 1/0
by R –R
1
0
Write new value to the Data Register pointed to by
R –R
1
0
XFR Data Register to
Wiper Counter
Register
Transfer the contents of the Data Register pointed
to by R –R to the Wiper Counter Register
1
1
1
1
0
1
1
0
1/0 1/0
1/0 1/0
0
0
0
0
1
0
XFR Wiper Counter
Register to Data
Register
Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by R –R
1
0
Increment/Decrement
Wiper Counter
Register
Enable Increment/decrement of the WiperCounter
Register
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
1
Read the status of the internal write cycle, by
checking the WIP bit.
Read Status (WIP bit)
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X9421
Instruction Format
Notes: (1) “A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Wiper Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
wiper position
(sent by X9421 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A
0
0
1
0
1
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
5
4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
instruction
opcode
Data Byte
(sent by Host on SI)
addresses
CS
Falling
Edge
CS
Rising
Edge
W W W W W W
0 P P P P P P
A
0
0
1
0
1
1
1
0
1
0
1
0
0
5
4 3 2 1 0
Read Data Register (DR)
Read the contents of the Register pointed to by R1-R0.
device type
identifier
device
addresses
instruction
opcode
register
addresses
Data Byte
(sent by X9421 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 0 0 P P P P P P
A
0
R R
0
1
0
1
1
1
0
1
0
1
1
1
0
5
4 3 2 1 0
Write Data Register (DR)
Write a new value to the Register pointed to by R1-R0.
device type
identifier
device
addresses
instruction
opcode
register
addresses
Data Byte
(sent by host on SI)
W W W W W W
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A
0
R R
1 0
0 1 0 1 1 1 0
1 1 0 0
0 0 0 0 P P P P P P
5 4 3 2 1 0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of the Register pointed to by R1-R0 to the WCR.
device type
identifier
device
addresses
instruction
opcode
register
addresses
CS
Falling
Edge
CS
Rising
Edge
A
0
R R
0 0
1 0
0 1 0 1 1 1 0
1 1 0 1
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X9421
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction
opcode
register
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A
0
R R
0 0
1 0
0 1 0 1 1 1 0
1 1 1 0
Increment/Decrement Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
increment/decrement
(sent by master on SDA)
CS
Falling
Edge
CS
Rising
Edge
A
0
0
1
0
1
1
1
0
0
0
1
0
0
0
0
0 I/D I/D
.
.
.
.
I/D I/D
Read Status
device type
identifier
device
addresses
instruction
opcode
Data Byte
(sent by X9421 on SO)
CS
CS
Falling
Edge
Rising
Edge
W
I
P
A
0
0
1
0
1
1
1
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
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X9421
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias. . . . . . . . . . . . –65°C to +135°C
Storage temperature . . . . . . . . . . . . . . –65°C to +150°C
Voltage on SCK any address input
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
with respect to V . . . . . . . . . . . . . . . . . –1V to +7V
SS
∆V = | (V – V ) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
H
L
Lead temperature (soldering, 10 seconds) . . . . . . 300°C
I
(10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
W
Any V /R , V /R , V /R . . . . . . . . . . . . V to V
H
H
L
L
W
W
SS
CC
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
0°C
Max.
+70°C
+85°C
Device
X9421
Supply Voltage (V ) Limits
CC
Commercial
Industrial
5V ±10%
–40°C
X9421-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to End Resistance Tolerance
Power Rating
Min.
Typ.
Max. Units
Test Conditions
25°C, each pot
±20
50
%
mW
mA
Ω
I
Wiper Current
±3
W
R
Wiper Resistance
150
400
250
Wiper Current = ± 1mA,
= 5V
W
V
CC
1000
Ω
Wiper Current = ± 1mA,
V
= 3V
CC
V
Voltage on any V /R , V /R , V /R
V
V
V
V
= 0V
TERM
H
H
L
L
W
W
SS
CC
SS
Noise
Resolution(4)
-120
1.6
dBV
%
Ref: 1kHz
See Note 5
Absolute Linearity(1)
Relative Linearity(2)
±1
MI(3)
MI(3)
V
– V
w(n)(actual)
w(n)(expected)
]
±0.2
V
– [V
w(n + 1) w(n) + MI
Temperature Coefficient of R
±300
ppm/°C See Note 5
±20 ppm/°C See Note 5
TOTAL
Ratiometric Temperature
Coefficient
C /C /C
Potentiometer Capacitances
Rh, RI, Rw leakage current
10/10/25
0.1
pF
µA
See Circuit #3
H
L
W
I
10
Vin = Vss to Vcc. Device is in
stand-by mode.
AL
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when
used as a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (V –V )/63, single pot
H
L
(4) Typical = Individual array resolution.
Characteristics subject to change without notice. 12 of 21
REV 1.1.6 8/1/02
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X9421
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
V
Supply Current
400
µA
f = 2MHz, SO = Open,
SCK
CC1
CC
(Active)
Other Inputs = V
SS
I
V
Supply Current
1
mA
f
= 2MHz, SO = Open,
CC2
CC
SCK
(Non-volatile Write)
Other Inputs = V
SS
I
V
Current (Standby)
1
µA
µA
µA
V
SCK = SI = V , Addr. = V
SS SS
SB
CC
I
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
10
10
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
+ 0.5
IH
CC
CC
V
–0.5
V
x 0.1
V
IL
CC
V
Output LOW Voltage
0.4
V
I
= 3mA
OL
OL
ENDURANCE AND DATA RETENTION
Parameter
Minimum Endurance
Data Retention
Min.
Units
100,000
100
Data Changes per Bit per Register
Years
CAPACITANCE
Symbol
Test
Max.
Units
pF
Test Conditions
= 0V
(5)
OUT
C
Output Capacitance (SO)
8
6
V
OUT
(5)
IN
C
Input Capacitance (A0, SI, and SCK)
pF
V
= 0V
IN
POWER-UP TIMING
Symbol
Parameter
Max.
0.2
Max.
50
Units
V/msec
(5)
t V
V
Power up Ramp
R CC
CC
POWER UP REQUIREMENTS (Power up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V and then the potentiometer pins, R , R , and R .
CC
H
L
W
Voltage should not be applied to the potentiometer pins before V
is applied. The V
ramp rate specification
CC
CC
should be met, and any glitches or slope changes in the V
line should be held to <100mV if possible. Also, V
CC
CC
should not reverse polarity by more than 0.5V. Recall of wiper position will not be complete until V
final value.
reaches its
CC
Notes: (5) This parameter is periodically sampled and not 100% tested.
A.C. TEST CONDITIONS
V
0.9
x 0.1 to V x
CC
CC
Input pulse levels
Input rise and fall times
10ns
Input and output timing level
V
CC
x 0.5
Characteristics subject to change without notice. 13 of 21
REV 1.1.6 8/1/02
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X9421
EQUIVALENT A.C. LOAD CIRCUIT
Circuit #3 SPICE Macro Model
5V
2.7V
R
TOTAL
R
R
L
H
C
L
1533Ω
C
H
C
W
10pF
SDA Output
10pF
25pF
100pF
100pF
R
W
AC TIMING
Symbol
Parameter
Min.
Max.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
f
SSI/SPI Clock Frequency
SSI/SPI Clock Cycle Time
SSI/SPI Clock High Time
SSI/SPI Clock Low Time
Lead Time
2.0
SCK
CYC
t
500
200
200
250
250
50
t
WH
t
WL
t
LEAD
t
Lag Time
LAG
t
SI, SCK, HOLD and CS Input Setup Time
SI, SCK, HOLD and CS Input Hold Time
SI, SCK, HOLD and CS Input Rise Time
SI, SCK, HOLD and CS Input Fall Time
SO Output Disable Time
SU
t
50
H
t
2
RI
t
2
FI
t
0
0
500
100
DIS
t
SO Output Valid Time
V
t
SO Output Hold Time
HO
t
SO Output Rise Time
50
50
RO
t
SO Output Fall Time
FO
t
HOLD Time
400
100
100
HOLD
t
HOLD Setup Time
HSU
t
HOLD Hold Time
HH
t
HOLD Low to Output in High Z
HOLD High to Output in Low Z
100
100
20
HZ
t
LZ
T
Noise Suppression Time Constant at SI, SCK, HOLD and CS inputs
CS Deselect Time
I
t
2
0
0
CS
WPASU
t
WP, A0 and A1 Setup Time
t
WP, A0 and A1 Hold Time
WPAH
Characteristics subject to change without notice. 14 of 21
REV 1.1.6 8/1/02
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X9421
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Units
t
High-voltage Write Cycle Time (Store Instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Units
t
Wiper Response Time After The Third (Last) Power Supply Is Stable
Wiper Response Time After Instruction Issued (All Load Instructions)
10
10
µs
µs
WRPO
t
WRL
Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement
Instruction)
t
450
ns
WRID
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Characteristics subject to change without notice. 15 of 21
REV 1.1.6 8/1/02
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X9421
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
t
CYC
SCK
...
WH
t
t
FI
t
RI
t
t
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
SI
Hold Timing
CS
t
t
HH
HSU
SCK
SO
...
t
t
FO
RO
t
t
LZ
HZ
SI
t
HOLD
HOLD
Characteristics subject to change without notice. 16 of 21
REV 1.1.6 8/1/02
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X9421
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
V
W
High Impedance
SO
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
t
WRID
...
V
W
...
ADDR
Inc/Dec
SI
Inc/Dec
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
Characteristics subject to change without notice. 17 of 21
REV 1.1.6 8/1/02
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X9421
APPLICATIONS INFORMATION
Electronic potentiometers provide three powerful application advantages: (1) the variability and reliability of a solid-
state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile
memory used for the storage of multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
V
R
V
R
V
H
V
W
V
L
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Basic Circuits
Buffered Reference Voltage
Cascading Techniques
Noninverting Amplifier
R
+5V
1
+V
+V
+V
LM308A
V
+
–
S
+5V
V
O
X
V
OP-07
W
+
–
V
–5V
W
V
= V
W
OUT
V
W
R
2
+V
–5V
R
1
V
W
V
= (1+R /R )V
2 1 S
(a)
(b)
O
Offset Voltage Adjustment
Comparator with Hysterisis
Voltage Regulator
R
R
2
1
V
–
+
S
V
V (REG)
O
317
IN
V
V
S
O
100KΩ
R
1
–
+
V
O
I
adj
TL072
R
R
1
2
R
2
10KΩ
10KΩ
+12V
V
V
= {R /CR +R } V (max)
1 1 2 O
= {R /CR +R } V (min)
UL
LL
10KΩ
-12V
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
1
1
2
O
O
2
1
Characteristics subject to change without notice. 18 of 21
REV 1.1.6 8/1/02
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X9421
PACKAGING INFORMATION
16-Lead Plastic SOIC (300 Mil Body) Package Type S
0.290 (7.37)
0.299 (7.60)
0.393 (10.00)
0.420 (10.65)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.51)
0.403 (10.2 )
0.413 ( 10.5)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" Typical
X 45°
0° – 8°
0.050"
Typical
0.0075 (0.19)
0.010 (0.25)
0.420"
0.015 (0.40)
0.050 (1.27)
0.030" Typical
16 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 19 of 21
REV 1.1.6 8/1/02
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X9421
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 20 of 21
REV 1.1.6 8/1/02
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X9421
ORDERING INFORMATION
X9421
Y
P
T
V
V
Limits
CC
Device
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
S = 16-Lead SOIC
V = 14-Lead TSSOP
Potentiometer Organization
W =10KΩ
Y =2.5KΩ
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 21 of 21
REV 1.1.6 8/1/02
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