5962R9957201QZC [XILINX]
Field Programmable Gate Array, 322970 Gates, 6912-Cell, CMOS, CQFP228, QFP-228;
| 型号： | 5962R9957201QZC |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 322970 Gates, 6912-Cell, CMOS, CQFP228, QFP-228 栅 |
| 文件： | 总17页 (文件大小：603K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
17
QPro Virtex 2.5V Radiation-Hardened FPGAs
DS028 (v2.1) November 5, 2010
Product Specification
Features
•
•
•
0.22 µm 5-layer epitaxial process
•
Supported by FPGA Foundation™ and Alliance
Development Systems
QML certified
•
Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
Radiation-hardened FPGAs for space and satellite
applications
•
Wide selection of PC and workstation platforms
•
•
•
Guaranteed total ionizing dose to 100K Rad(si)
•
•
SRAM-based in-system configuration
2
Latch-up immune to LET = 125 MeV cm /mg
•
•
Unlimited reprogrammability
Four programming modes
SEU immunity achievable with recommended
redundancy implementation
•
•
Guaranteed over the full military temperature range
(–55°C to +125°C)
Available to Standard Microcircuit Drawings. Contact
Defense Supply Center Columbus (DSCC) for more
information at http://www.dscc.dla.mil
Fast, high-density Field-Programmable Gate Arrays
•
•
•
5962-99572 for XQVR300
5962-99573 for XQVR600
5962-99574 for XQVR1000
•
•
•
Densities from 100k to 1M system gates
System performance up to 200 MHz
Hot-swappable for Compact PCI
•
•
Multi-standard SelectIO™ interfaces
Description
•
•
16 high-performance interface standards
Connects directly to ZBTRAM devices
The QPro™ Virtex® family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 5-layer-metal 0.22 µm CMOS process. These
advances make QPro Virtex FPGAs powerful and flexible
alternatives to mask-programmed gate arrays. The Virtex
radiation-hardened family comprises the three members
shown in Table 1.
Built-in clock-management circuitry
•
Four dedicated delay-locked loops (DLLs) for
advanced clock control
•
Four primary low-skew global clock distribution
nets, plus 24 secondary global nets
•
•
Hierarchical memory system
•
•
•
LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the QPro Virtex family delivers a high-speed
and high-capacity programmable logic solution that
Configurable synchronous dual-ported 4k-bit
RAMs
Fast interfaces to external high-performance RAMs
Flexible architecture that balances speed and density
•
•
•
•
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
enhances design flexibility while reducing time-to-market.
Refer to the Virtex 2.5V FPGA commercial data sheet at
http://www.xilinx.com/support/documentation/virtex.htm for
more information on device architecture and timing
specifications.
Cascade chain for wide-input functions
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
•
•
•
Internal 3-state bussing
IEEE 1149.1 boundary-scan logic
Die-temperature sensing device
© Copyright 2001–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS028 (v2.1) November 5, 2010
www.xilinx.com
Product Specification
1
QPro Virtex 2.5V Radiation-Hardened FPGAs
Table 1: QPro Virtex FPGA Radiation-Hardened FPGA Family Members
Device
XQVR300
XQVR600
XQVR1000
System Gates CLB Array Logic Cells Maximum Available I/O Block RAM Bits Maximum Select RAM Bits
322,970
661,111
32x48
48x72
64x96
6,912
15,552
27,648
162
162
404
65,536
98,304
131,072
98,304
221,184
393,216
1,124,022
Radiation Specifications
(1)
Table 2: Radiation Specifications
Symbol
Description
Min
Max
Units
TID
Total Ionizing Dose
100
–
krad(Si)
Method 1019, Dose Rate ~9.0 rad(Si)/sec
SEL
Single Event Latch-up Immunity
Heavy Ion Saturation Cross Section
LET > 125 MeV cm2/mg
–
0
(cm2/Device)
SEUFH
SEUCH
SEUCP
SEUBH
Single Event Upset CLB Flip-flop
Heavy Ion Saturation Cross Section
–
–
–
–
6.5E – 8
8.0E – 8
2.2E – 14
1.6E – 7
(cm2/Bit)
(cm2/Bit)
(cm2/Bit)
(cm2/Bit)
Single Event Upset Configuration Latch
Heavy Ion Saturation Cross Section
Single Event Upset Configuration Latch
Proton (63 MeV) Saturation Cross Section
Single Event Upset Block RAM Bit
Heavy Ion Saturation Cross Section
Notes:
1. For more information, refer to “Radiation Test Results of the Virtex FPGA for Space Based Reconfigurable Computing” and “SEU Mitigation
Techniques for Virtex FPGAs in Space Applications” at http://www.xilinx.com/esp/aero_def/aero_def_app.htm.
Virtex FPGA Electrical Characteristics
Based on preliminary characterization. Further changes are not expected.
All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters
included are common to popular designs and typical applications. Contact the factory for design considerations requiring
more detailed information.
DS028 (v2.1) November 5, 2010
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Product Specification
2
QPro Virtex 2.5V Radiation-Hardened FPGAs
Virtex FPGA DC Characteristics
Absolute Maximum Ratings
Table 3: Absolute Maximum Ratings
Symbol
VCCINT
VCCO
Description
Min/Max
–0.5 to 3.0
–0.5 to 4.0
–0.5 to 3.6
–0.5 to 3.6
–0.5 to 5.5
–0.5 to 5.5
50
Units
V
Supply voltage relative to GND
Supply voltage relative to GND
Input reference voltage
V
VREF
V
(3)
VIN
Input voltage relative to GND
Using VREF
V
Internal threshold
V
VTS
VCC
TSTG
TJ
Voltage applied to 3-state output
Longest supply voltage rise time from 1V to 2.375V
Storage temperature (ambient)
Junction temperature
V
ms
C
C
–65 to +150
+150
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. Power supplies can turn on in any order.
3. For protracted periods (e.g., longer than a day), V should not exceed V
by more that 3.6V.
CCO
IN
Recommended Operating Conditions
Table 4: Recommended Operating Conditions
Symbol
VCCINT
VCCO
TIN
Description
Supply voltage relative to GND
Device
Min
Max
Units
V
2.5 – 5% 2.5 + 5%
Supply voltage relative to GND
Input signal transition time
1.2
–
3.6
250
V
ns
TIC
Initialization temperature range(4)
XQVR300
XQVR600
XQVR1000
XQVR300
XQVR600
XQVR1000
XQVR300
XQVR600
XQVR1000
XQVR300
XQVR600
XQVR1000
–55
–55
–40
–55
–55
–55
–
+125
+125
+125
+125
+125
+125
150
C
C
C
TOC
Operational temperature range(5)
Quiescent VCCINT supply current
C
C
C
ICCINTQ
mA
mA
mA
mA
mA
mA
–
200
–
200
ICCCCOQ Quiescent VCCO supply current
–
4.0
–
4.0
–
4.0
Notes:
1. Correct operation is guaranteed with a minimum V
of 2.25V (Nominal V
CCINT
– 10%). Below the minimum value stated above, all delay
CCINT
CCINT
parameters increase by 3% for each 50 mV reduction in V
below the specified range.
2. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C.
3. Input and output measurement threshold is ~50% of V
.
CC
4. Initialization occurs from the moment of V ramp-up to the rising transition of the INIT pin.
CC
5. The device is operational after the INIT pin has transitioned High.
DS028 (v2.1) November 5, 2010
www.xilinx.com
Product Specification
3
QPro Virtex 2.5V Radiation-Hardened FPGAs
QPro Virtex FPGA Pinouts
Device/Package Combinations and Maximum User I/O
Table 5: Device/Package Combinations and Maximum User I/O
Maximum User I/O (Excluding Dedicated Clock Pins)
Package
XQVR300
XQVR600
XQVR1000
CB228
162
–
162
–
–
CG560(1)
404
Notes:
1. Obsolete package. CG560 is no longer available. It is listed for information purposes only.
Pinout Tables
Table 6 and Table 7 list the locations of special-purpose and power-supply pins. Pins not listed are user I/Os.
Table 6: Virtex FPGA Ceramic Column Grid (CG560) Pinout for the XQVR1000
(1)
Pin Name
CG560
GCK0
GCK1
GCK2
GCK3
M0
AL17
AJ17
D17
A17
AJ29
AK30
AN32
C4
M1
M2
CCLK
PROGRAM
DONE
INIT
AM1
AJ5
AH5
D4
BUSY/DOUT
D0/DIN
D1
E4
K3
D2
L4
D3
P3
D4
W4
D5
AB5
AC4
AJ4
D6
D6
D7
WRITE
CS
A2
TDI
D5
TDO
TMS
TCK
E6
B33
E29
AK29
DXN
DS028 (v2.1) November 5, 2010
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Product Specification
4
QPro Virtex 2.5V Radiation-Hardened FPGAs
Table 6: Virtex FPGA Ceramic Column Grid (CG560) Pinout for the XQVR1000 (Cont’d)
(1)
Pin Name
CG560
DXP
AJ28
VCCINT
A21, B12, B14, B18, B28, C22, C24, E9, E12, F2, H30, J1, K32, M3, N1, N29, N33,
U5, U30, Y2, Y31, AB2, AB32, AD2, AD32, AG3, AG31, AJ13, AK8, AK11, AK17,
AK20, AL14, AL22, AL27, AN25
VCCINT pins are listed incrementally. Connect all
pins listed for both the required device and all
smaller devices listed in the same package.
V
CCO, Bank 0
CCO, Bank 1
A22, A26, A30, B19, B32
V
A10, A16, B13, C3, E5
VCCO, Bank 2
VCCO, Bank 3
B2, D1, H1, M1, R2
V1, AA2, AD1, AK1, AL2
V
CCO, Bank 4
AM2, AM15, AN4, AN8, AN12
AL31, AM21, AN18, AN24, AN30
W32, AB33, AF33, AK33, AM32
C32, D33, K33, N32, T33
VCCO, Bank 5
VCCO, Bank 6
VCCO, Bank 7
VREF, Bank 0
A19, D20, D26, D29, E21, E23, E24, E27
Within each bank, if input reference voltage is not
required, all VREF pins are general I/O.
VREF, Bank 1
A6, D7, D10, D11, D13, D16, E7, E15
Within each bank, if input reference voltage is not
required, all VREF pins are general I/O.
VREF, Bank 2
B3, G5, H4, K5, L5, N5, P4, R1
Within each bank, if input reference voltage is not
required, all VREF pins are general I/O.
VREF, Bank 3
Within each bank, if input reference voltage is not
required, all VREF pins are general I/O.
V4, W5, AA4, AD3, AE5, AF1, AH4, AK2
AK13, AL7, AL9, AL10, AL16, AM4, AM14, AN3
AJ18, AJ25, AK28, AL20, AL24, AL29, AM26, AN23
V29, Y32, AA30,AD31, AE29, AK32, AE31, AH30
D31, E31, G31, H32, K31, P31, T31, L33
VREF, Bank 4
Within each bank, if input reference voltage is not
required, all VREF pins are general I/O.
VREF, Bank 5
Within each bank, if input reference voltage is not
required, all VREF pins are general I/O.
VREF, Bank 6
Within each bank, if input reference voltage is not
required, all VREF pins are general I/O.
VREF, Bank 7
Within each bank, if input reference voltage is not
required, all VREF pins are general I/O.
GND
A1, A7, A12, A14, A18, A20, A24, A29, A32, A33, B1, B6, B9, B15, B23, B27, B31,
C2, E1, F32, G2, G33, J32, K1, L2, M33, P1, P33, R32, T1, V33, W2, Y1, Y33,
AB1, AC32, AD33, AE2, AG1, AG32, AH2, AJ33, AL32, AM3, AM7, AM11, AM19,
AM25, AM28, AM33, AN1, AN2, AN5, AN10, AN14, AN16, AN20, AN22, AN27,
AN33
No Connect
C31, AC2, AK4, AL3
Notes:
1. Obsolete package. CG560 is no longer available. It is listed for information purposes only.
DS028 (v2.1) November 5, 2010
www.xilinx.com
Product Specification
5
QPro Virtex 2.5V Radiation-Hardened FPGAs
Table 7: CQFP Package (CB228)
Function
Pin #
Bank #
GND
1
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
TMS
2
IO
3
IO
4
IO_VREF_7
5
IO
6
IO
7
GND
8
IO
9
IO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
IO
IO_VREF_7
IO
GND
VCCINT
IO
IO
VCCO
IO
IO
IO_VREF_7
IO
IO
IO
IO
IO_IRDY
GND
VCCO
IO_TRDY
VCCINT
IO
IO
IO
IO_VREF_6
IO
IO
VCCO
IO
IO
IO
DS028 (v2.1) November 5, 2010
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Product Specification
6
QPro Virtex 2.5V Radiation-Hardened FPGAs
Table 7: CQFP Package (CB228) (Cont’d)
Function
Pin #
Bank #
VCCINT
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GND
IO
IO_VREF_6
IO
IO
IO_VREF_6
GND
IO
IO
IO_VREF_6
IO
IO
IO
M1
GND
M0
VCCO
M2
IO
IO
IO
IO_VREF_5
IO
IO
GND
IO_VREF_5
IO
IO
IO_VREF5
IO
GND
VCCINT
IO
IO
VCCO
IO
IO
IO_VREF_5
IO
DS028 (v2.1) November 5, 2010
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Product Specification
7
QPro Virtex 2.5V Radiation-Hardened FPGAs
Table 7: CQFP Package (CB228) (Cont’d)
Function
Pin #
Bank #
IO
81
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
IO
82
VCCINT
83
GCK1
84
VCCO
85
GND
86
GCKO
87
IO
88
IO
89
IO
90
IO
91
IO_VREF_4
92
IO
93
IO
94
VCCO
95
IO
96
IO
97
IO
98
VCCINT
GND
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
IO
IO_VREF_4
IO
IO
IO_VREF_4
GND
IO
IO
IO_VREF_4
IO
IO
IO
GND
DONE
VCCO
PROGRAM
IO_INIT
IO_D7
IO
IO_VREF_3
DS028 (v2.1) November 5, 2010
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Product Specification
8
QPro Virtex 2.5V Radiation-Hardened FPGAs
Table 7: CQFP Package (CB228) (Cont’d)
Function
Pin #
Bank #
IO
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO
GND
IO_VREF_3
IO
IO
IO_VREF_3
IO_D6
GND
VCCINT
IO_D5
IO
VCCO
IO
IO
IO_VREF_3
IO_D4
IO
IO
VCCINT
IO_TRDY
VCCO
GND
IO_IRDY
IO
IO
IO
IO_D3
IO_VREF_2
IO
IO
VCCO
IO
IO
IO_D2
VCCINT
GND
IO_D1
IO_VREF_2
IO
DS028 (v2.1) November 5, 2010
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Product Specification
9
QPro Virtex 2.5V Radiation-Hardened FPGAs
Table 7: CQFP Package (CB228) (Cont’d)
Function
Pin #
Bank #
IO
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_VREF_2
GND
IO
IO
IO_VREF_2
IO
IO_DIN_D0
IO_DOUT_BUSY
CCLK
VCCO
TDO
GND
TDI
IO_CS
IO_WRITE
IO
IO_VREF_1
IO
GND
IO_VREF_1
IO
IO
IO_VREF_1
IO
GND
VCCINT
IO
IO
IO
VCCO
IO
IO
IO_VREF_1
IO
IO
IO
IO
GCK2
GND
DS028 (v2.1) November 5, 2010
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Product Specification
10
QPro Virtex 2.5V Radiation-Hardened FPGAs
Table 7: CQFP Package (CB228) (Cont’d)
Function
Pin #
Bank #
VCCO
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GCK3
VCCINT
IO
IO
IO
IO_VREF_0
IO
IO
VCCO
IO
IO
IO
VCCINT
GND
IO
IO_VREF_0
IO
IO
IO_VREF_0
GND
IO
IO
IO_VREF_0
IO
IO
TCK
VCCO
GND
1, 8, 14, 27, 42, 48, 56, 66, 72, 86, 100,
106, 113, 123, 129, 143, 157, 163,
173, 180, 186, 200, 215, 221
–
VCCINT
VCCO
15, 30, 41, 73, 83, 99, 130, 140, 156,
187, 203, 214
–
–
18, 28, 37, 58, 76, 85, 95, 115, 133,
142, 152, 171, 191, 201, 210, 228
DS028 (v2.1) November 5, 2010
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Product Specification
11
QPro Virtex 2.5V Radiation-Hardened FPGAs
Pinout Diagrams
The following diagrams illustrate the locations of special-purpose pins on Virtex FPGAs. Table 8 lists the symbols used in
these diagrams. The diagrams also show I/O-bank boundaries.
Table 8: Pinout Diagram Symbols
Symbol
Pin Function
S
General I/O
d
Device-dependent general I/O, n/c on smaller devices
V
VCCINT
v
Device-dependent VCCINT, n/c on smaller devices
O
VCCO
R
VREF
r
Device-dependent VREF, remains I/O on smaller devices
G
Ground
Ø, 1, 2, 3
❿, ❶, ❷
Global Clocks
M0, M1, M2
➉, ➀, ➁, ➂,
➃, ➄, ➅, ➆
D0/DIN, D1, D2, D3, D4, D5, D6, D7
B
D
P
I
DOUT/BUSY
DONE
PROGRAM
INIT
K
W
S
T
+
–
CCLK
WRITE
CS
Boundary-scan test access port
Temperature diode, anode
Temperature diode, cathode
No connect
n
DS028 (v2.1) November 5, 2010
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Product Specification
12
QPro Virtex 2.5V Radiation-Hardened FPGAs
CG560 Pin Function Diagram
Note: CG560 is an obsolete package and is no longer available. It is listed for information purposes only.
X-Ref Target - Figure 1
✳ ✳ ✳
✳ ✳
✳ ✳
G
✳
✳ ✳
✳
✳
✳
G
✳
✳
✳ ✳ ✳
✳ ✳
✳
G O
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
G S
G O r
R G
G
O
G
G
O 3 G R G V O
✳ ✳ ✳ ✳ ✳
G
O
G G
G O T
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
✳ ✳
✳ ✳
✳ ✳ ✳ ✳ ✳ ✳
v O V G
V O
G V
✳
O
G
✳
✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳
✳
G O K
✳ ✳
✳ ✳ ➉
v
V
n O
r
R
✳ ✳
✳
✳
✳ ✳
✳ ✳
✳ ✳ ✳ ✳ ✳
✳ ✳ ✳ ✳ ✳
✳ ✳
✳
✳
✳
✳
✳ ✳
B T W R
r R
✳ ✳
r
✳ ✳
R 2
R
R
✳ ✳
r
T
O
✳
O T r
V
V
R
r
R r
Bank 0
R
✳ ✳ ✳
✳ ✳
✳ ✳ ✳
✳ ✳
✳
G
✳
✳
V
G
✳
r
Bank 1
✳
G
✳ ✳
R
✳
R
✳
✳ ✳ ✳
✳
O
V
R
V
✳ ✳ ✳ ✳
✳ ➀ ✳
G
✳ ✳
G
✳
r
R V O
Bank 2
Bank 7
✳ ➁
✳ ✳ ✳ ✳
✳ ✳ ✳ ✳
G
R
✳ ✳
r
G
O V
✳
O
V
v
✳ ✳ ✳
✳ ✳
r
v
✳ ✳
✳ ➂
✳
✳ ✳ ✳
✳
G
✳
G
R O
R
R
G
✳
O
✳ ✳ ✳
✳ ✳
CG560
✳ ✳ ✳ ✳
(Top View)
G
✳ ✳ ✳ ✳
R
✳
✳ ✳ ✳
G
V
✳
R
V
✳ ✳ ✳
U
V
W
Y
AA
✳ ✳
G
V
W
Y
O
✳
R
✳ ➃
R
✳ ✳ ✳
✳
O
✳ ✳ ✳
✳ ✳
✳
G V
V R G
✳ ✳ ✳
✳
✳
✳
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
O
r
r
✳ ✳ ➄
✳ ➅ ✳
✳ ✳ ✳
✳ ✳ ✳
G v
v O AB
✳
✳
n
G
AC
Bank 3
Bank 6
✳ ✳
✳ ✳
O V R
R V G AD
✳
✳ ✳
✳ ✳ ✳ ✳
✳
✳ ✳ ✳ ✳
✳ ✳
r AE
G
R
R
r
G
✳
O AF
✳
✳
✳ ✳
I
✳ ✳
✳
r
❿ ✳ ✳ ✳
V
✳
V G
✳ ✳ ✳
AG
AH
Bank 4
✳ ✳ ✳ ✳ ✳ ✳ ✳
Bank 5
✳ ✳ ✳ ✳ ✳ ✳
G
r
✳ ✳ ✳ ➆
✳
✳ ✳ ✳
✳ ✳ ✳
✳ ✳
✳ ✳ ✳ ✳ ✳ ✳ ✳
D
✳ ✳ ✳
v
r
1 R
R
+
G AJ
✳ ✳
✳
✳ ✳
✳ ✳
❶ ✳
O R
✳
n
✳ ✳ ✳
V
V
V
R Ø
V
R
✳
G
r – R O AK
✳
✳ ✳ ✳
✳ ✳ ✳
✳
✳
O
✳
✳
✳ ✳ ✳
✳ ✳
G r
✳
✳
✳
O n
R
G
✳ ✳
r R
V
v
R
V
✳
G
R
O G
AL
O G AM
✳ ❷
✳ ✳
✳ ✳
✳
✳ ✳ ✳
✳
✳ ✳ ✳
P O G R
G
R O
G
✳
G
✳ ✳
✳
✳
✳
✳
G G r O G
O
G
O
G
G
O
G r O V
O
G AN
Figure 1: CG560 Pin Function Diagram
DS028 (v2.1) November 5, 2010
www.xilinx.com
Product Specification
13
QPro Virtex 2.5V Radiation-Hardened FPGAs
Package Drawing CG560 Ceramic Column Grid
Note: CG560 is an obsolete package and is no longer available. It is listed for information purposes only.
X-Ref Target - Figure 2
DS028_01_011900
Figure 2: Package Drawing CG560 Ceramic Column Grid
DS028 (v2.1) November 5, 2010
www.xilinx.com
Product Specification
14
QPro Virtex 2.5V Radiation-Hardened FPGAs
Device/Package Combinations and Maximum User I/O
Table 9: Device/Package Combinations and Maximum User I/O
Maximum User I/O (Excluding Dedicated Clock Pins)
Package
XQVR300
XQVR600
XQVR1000
CB228
162
–
162
–
–
CG560(1)
404
Notes:
1. Obsolete package. CG560 is no longer available. It is listed for information purposes only.
Ordering Information
X-Ref Target - Figure 3
Example: XQVR600 -4 CB 228 V
Manufacturing Grade
Device Type
Speed Grade(1)
Number of Pins
Package Type
DS028_03_102610
Note 1: -4 is the only supported speed grade.
Figure 3: Example Ordering Information
Device Ordering Options
Table 10: Device Ordering Options
Device Type
Package
228-pin Ceramic Quad Flat Package
CG560(2) 560-column Ceramic Column Grid Package
Grade
XQVR300
XQVR600
XQVR1000
CB228
M
V
Military Ceramic
QPro Plus
TC = –55°C to +125°C
TC = –55°C to +125°C
Q
MIL-PRF-38535(3) TC = –55°C to +125°C
Notes:
1. -4 is the only supported speed grade.
2. Obsolete package. CG560 is no longer available. It is listed for information purposes only.
3. Class Q must be ordered with the SMD number.
Device Ordering Combinations
Table 11: Device Ordering Combinations
M Grade
V Grade
XQVR300-4CB228M
XQVR600-4CB228M
XQVR1000-4CG560M(1)
XQVR300-4CB228V
XQVR600-4CB228V
XQVR1000-4CG560V(1)
Notes:
1. Obsolete package. CG560 is no longer available. It is listed for information purposes only.
DS028 (v2.1) November 5, 2010
www.xilinx.com
Product Specification
15
QPro Virtex 2.5V Radiation-Hardened FPGAs
SMD (Class Q) Ordering Options
X-Ref Target - Figure 4
Example: 5962 R 9957201 QY C
Lead Finish
Generic Standard
Microcircuit Drawing (SMD)
Package Type
Radiation Hardened
QML Certified MIL_PRF-38535
Device Type
DS028_04_102610
Figure 4: SMD (Class Q) Ordering Options
Valid SMD Combinations
Table 12: Valid SMD Combinations
SMD Number
Device
Package Markings
Lead Finish
Gold Plate
5962R9957201QYC
XQVR300-4CB228B
XQVR300-4CB228B
XQVR600-4CB228B
XQVR600-4CB228B
XQVR1000-4CG560B(1)
Base
Lid
5962R9957201QZC
Gold Plate
5962R9957301QYC
Base
Lid
Gold Plate
5962R9957301QZC
Gold Plate
5962R9957401QXA
–
Solder Column
Notes:
1. Obsolete package. CG560 is no longer available. It is listed for information purposes only.
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revisions
04/25/00
02/13/01
11/05/01
01/04/10
Initial Xilinx release.
1.1
Updated Temperature Specifications.
1.2
Updated Temperature Specifications for V600. Added Class V option and SMD. Updated format.
2.0
Changed document classification from Preliminary Product Specification to Product Specification.
Added notes indicating that CG560 is obsolete. In Table 1, changed the Maximum Available I/O values
to 162 for XQVR300 and XQVR600. Changed the example in Ordering Information. In the Valid SMD
Combinations Table 12, changed the last digit of the device numbers to B in the Device column and
changed 5962R9957401QXC to 5962R9957401QXA in the SMD Number column.
11/05/10
2.1
In the Valid SMD Combinations Table 12, updated the package markings for all the devices.
DS028 (v2.1) November 5, 2010
www.xilinx.com
Product Specification
16
QPro Virtex 2.5V Radiation-Hardened FPGAs
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A
VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL
APPLICATIONS.
DS028 (v2.1) November 5, 2010
www.xilinx.com
Product Specification
17
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