5962R9957201QZX [XILINX]
Field Programmable Gate Array, 1536 CLBs, 322970 Gates, CMOS, CQFP228, CERAMIC, QFP-228;
| 型号： | 5962R9957201QZX |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 1536 CLBs, 322970 Gates, CMOS, CQFP228, CERAMIC, QFP-228 栅 可编程逻辑 |
| 文件： | 总14页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
QPro Virtex 2.5V Radiation
Hardened FPGAs
0
2
DS028 (v1.2) November 5, 2001
Preliminary Product Specification
-
Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
Features
•
•
•
0.22 µm 5-layer epitaxial process
-
Wide selection of PC and workstation platforms
QML certified
•
•
SRAM-based in-system configuration
Radiation hardened FPGAs for space and satellite
applications
-
-
Unlimited reprogrammability
Four programming modes
•
•
•
Guaranteed total ionizing dose to 100K Rad(si)
Available to Standard Microcircuit Drawings. Contact
Defense Supply Center Columbus (DSCC) for more
information at http://www.dscc.dla.mil
2
Latch-up immune to LET = 125 MeV cm /mg
SEU immunity achievable with recommended
redundancy implementation
-
-
-
5962-99572 for XQVR300
5962-99573 for XQVR600
5962-99574 for XQVR1000
•
•
Guaranteed over the full military temperature range
(–55°C to +125°C)
Fast, high-density Field-Programmable Gate Arrays
-
-
-
Densities from 100k to 1M system gates
System performance up to 200 MHz
Hot-swappable for Compact PCI
Description
The QPro™ Virtex™ FPGA family delivers high-perfor-
mance, high-capacity programmable logic solutions. Dra-
matic increases in silicon efficiency result from optimizing
the new architecture for place-and-route efficiency and
exploiting an aggressive 5-layer-metal 0.22 µm CMOS pro-
cess. These advances make QPro Virtex FPGAs powerful
and flexible alternatives to mask-programmed gate arrays.
The Virtex radiation hardened family comprises the three
members shown in Table 1.
•
•
Multi-standard SelectI/O™ interfaces
-
-
16 high-performance interface standards
Connects directly to ZBTRAM devices
Built-in clock-management circuitry
-
Four dedicated delay-locked loops (DLLs) for
advanced clock control
-
Four primary low-skew global clock distribution
nets, plus 24 secondary global nets
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the QPro Virtex family delivers a high-speed
and high-capacity programmable logic solution that
enhances design flexibility while reducing time-to-market.
•
•
Hierarchical memory system
-
-
-
LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
Configurable synchronous dual-ported 4k-bit
RAMs
Fast interfaces to external high-performance RAMs
Refer to the “Virtex™ 2.5V Field Programmable Gate
Arrays” commercial data sheet for more information on
device architecture and timing specifications.
Flexible architecture that balances speed and density
-
-
-
-
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
-
-
-
Internal 3-state bussing
IEEE 1149.1 boundary-scan logic
Die-temperature sensing device
•
Supported by FPGA Foundation™ and Alliance
Development Systems
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS028 (v1.2) November 5, 2001
www.xilinx.com
1
Preliminary Product Specification
1-800-255-7778
R
QPro Virtex 2.5V Radiation Hardened FPGAs
Table 1: QPro Virtex Radiation Hardened Field-Programmable Gate Array Family Members.
Maximum
Available I/O
Max Select
RAM Bits
Device
XQVR300
XQVR600
XQVR1000
System Gates CLB Array
Logic Cells
6,912
Block RAM Bits
65,536
322,970
661,111
32x48
48x72
64x96
316
316
404
98,304
221,184
393,216
15,552
98,304
1,124,022
27,648
131,072
Radiation Specifications(1)
Symbol
Description
Total Ionizing Dose
Min
Max
Units
TID
100
-
krad(Si)
Method 1019, Dose Rate ~9.0 rad(Si)/sec
2
SEL
Single Event Latch-up Immunity
-
0
(cm /Device)
Heavy Ion Saturation Cross Section
2
LET > 125 MeV cm /mg
2
SEU
SEU
SEU
SEU
Single Event Upset CLB Flip-flop
Heavy Ion Saturation Cross Section
-
-
-
-
6.5E – 8
8.0E – 8
2.2E – 14
1.6E – 7
(cm /Bit)
FH
CH
CP
BH
2
Single Event Upset Configuration Latch
Heavy Ion Saturation Cross Section
(cm /Bit)
2
Single Event Upset Configuration Latch
Proton (63 MeV) Saturation Cross Section
(cm /Bit)
2
Single Event Upset BRAM Bit
(cm /Bit)
Heavy Ion Saturation Cross Section
Notes:
1. For more information, refer to "Radiation Test Results of the Virtex FPGA for Space Based Reconfigurable Computing" and "SEU
Mitigation Techniques for Virtex FPGAs in Space Applications" at http://www.xilinx.com/products/hirel_qml.htm.
2
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DS028 (v1.2) November 5, 2001
1-800-255-7778
Preliminary Product Specification
R
QPro Virtex 2.5V Radiation Hardened FPGAs
Virtex Electrical Characteristics
Based on preliminary characterization. Further changes are not expected.
All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters
included are common to popular designs and typical applications. Contact the factory for design considerations requiring
more detailed information.
Virtex DC Characteristics
Absolute Maximum Ratings
Symbol
Description
Min/Max
–0.5 to 3.0
–0.5 to 4.0
–0.5 to 3.6
–0.5 to 3.6
–0.5 to 5.5
–0.5 to 5.5
50
Units
V
V
Supply voltage relative to GND
Supply voltage relative to GND
Input reference voltage
CCINT
V
V
CCO
V
V
REF
(3)
V
Input voltage relative to GND
Using V
V
IN
REF
Internal threshold
V
V
Voltage applied to 3-state output
V
TS
V
Longest supply voltage rise time from 1V to 2.375V
Storage temperature (ambient)
ms
°C
°C
CC
T
–65 to +150
+150
STG
T
Junction temperature
J
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Power supplies may turn on in any order.
3. For protracted periods (e.g., longer than a day), V should not exceed V
by more that 3.6V.
IN
CCO
Recommended Operating Conditions
Symbol
Description
Supply voltage relative to GND
Device
Min
Max
Units
V
V
2.5 – 5% 2.5 + 5%
CCINT
V
Supply voltage relative to GND
Input signal transition time
1.2
3.6
250
V
CCO
T
T
-
–55
–55
–40
–55
–55
–55
-
ns
IN
(4)
Initialization temperature range
XQVR300
XQVR600
XQVR1000
XQVR300
XQVR600
XQVR1000
XQVR300
XQVR600
XQVR1000
XQVR300
XQVR600
XQVR1000
+125
+125
+125
+125
+125
+125
150
°C
IC
°C
°C
(5)
T
Operational temperature range
°C
OC
°C
°C
ICC
Quiescent V
Quiescent V
supply current
CCINT
mA
mA
mA
mA
mA
mA
INTQ
-
200
-
200
ICC
supply current
CCO
-
4.0
CCOQ
-
4.0
-
4.0
Notes:
1. Correct operation is guaranteed with a minimum V
of 2.25V (Nominal V
– 10%). Below the minimum value stated above,
CCINT
CCINT
all delay parameters increase by 3% for each 50 mV reduction in V
below the specified range.
CCINT
2. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
3. Input and output measurement threshold is ~50% of V
.
CC
4. Initialization occurs from the moment of V ramp-up to the rising transition of the INIT pin.
CC
5. The device is operational after the INIT pin has transitioned high.
DS028 (v1.2) November 5, 2001
www.xilinx.com
3
Preliminary Product Specification
1-800-255-7778
R
QPro Virtex 2.5V Radiation Hardened FPGAs
QPro Virtex Pinouts
Device/Package Combinations and Maximum I/O
Maximum User I/O (excluding dedicated clock pins)
Package
CB228
XQVR300
XQVR600
XQVR1000
162
-
162
-
-
CG560
404
Pinout Tables
See the Xilinx WebLINX web site (http://www.xil-
inx.com/partinfo/databook.htm) for updates or additional
pinout information. For convenience, Table 2 and Table 3 list
the locations of special-purpose and power-supply pins.
Pins not listed are user I/Os.
Table 2: Virtex Ceramic Column Grid (CG560) Pinout
(Continued)
Pin Name
Device
CG560
E6
TDO
TMS
TCK
DXN
DXP
XQVR1000
B33
Table 2: Virtex Ceramic Column Grid (CG560) Pinout
E29
Pin Name
GCK0
GCK1
GCK2
GCK3
M0
Device
CG560
AL17
AJ17
D17
A17
AJ29
AK30
AN32
C4
AK29
AJ28
XQVR1000
V
A21, B12,
B14, B18,
B28, C22,
C24, E9,
CCINT
(V
pins are listed
CCINT
incrementally. Connect
all pins listed for both the
required device and all
smaller devices listed in
the same package.)
E12, F2,
M1
H30, J1,
M2
K32, M3,
CCLK
PROGRAM
DONE
INIT
N1, N29,
AM1
AJ5
AH5
D4
N33, U5,
U30, Y2,
Y31, AB2,
AB32, AD2,
AD32, AG3,
AG31, AJ13,
AK8, AK11,
AK17, AK20,
AL14, AL22,
AL27, AN25
BUSY/DOUT
D0/DIN
D1
E4
K3
D2
L4
D3
P3
D4
W4
D5
AB5
AC4
AJ4
D6
V
V
V
, Bank 0
, Bank 1
, Bank 2
A22, A26,
CCO
CCO
CCO
D6
A30, B19, B32
D7
A10, A16,
WRITE
CS
B13, C3, E5
A2
B2, D1,
TDI
D5
H1, M1, R2
4
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DS028 (v1.2) November 5, 2001
1-800-255-7778
Preliminary Product Specification
R
QPro Virtex 2.5V Radiation Hardened FPGAs
Table 2: Virtex Ceramic Column Grid (CG560) Pinout
Table 2: Virtex Ceramic Column Grid (CG560) Pinout
(Continued)
(Continued)
Pin Name
Device
CG560
Pin Name
, Bank 6
REF
Device
CG560
V
V
, Bank 3
XQVR1000
V1, AA2,
V
XQVR1000
V29, Y32,
AA30,AD31,
AE29, AK32,
AE31, AH30
CCO
AD1, AK1, AL2
Within each bank, if input
reference voltage is not
, Bank 4
, Bank 5
, Bank 6
, Bank 7
AM2, AM15,
CCO
required, all V
pins
REF
AN4, AN8,
AN12
are general I/O.
V
, Bank 7
D31, E31,
G31, H32,
K31, P31,
T31, L33
REF
V
V
AL31, AM21,
CCO
CCO
CCO
Within each bank, if input
reference voltage is not
AN18, AN24,
AN30
required, all V
pins
REF
are general I/O.
W32, AB33,
GND
A1, A7, A12,
A14, A18, A20,
AF33, AK33,
AM32
A24, A29,
A32, A33,
B1, B6,
V
V
C32, D33,
K33, N32, T33
, Bank 0
A19, D20,
D26, D29,
E21, E23,
E24, E27,
REF
B9, B15,
Within each bank, if input
reference voltage is not
B23, B27,
B31, C2,
required, all V
pins
REF
are general I/O.
E1, F32,
V
, Bank 1
A6, D7,
D10, D11,
D13, D16,
E7, E15
REF
G2, G33,
Within each bank, if input
reference voltage is not
required, all V
J32, K1,
L2, M33,
pins
REF
are general I/O.
P1, P33,
R32, T1,
V
, Bank 2
B3, G5,
H4, K5,
L5, N5,
P4, R1
REF
V33, W2,
Within each bank, if input
reference voltage is not
required, all V
Y1, Y33,
pins
REF
AB1, AC32,
AD33, AE2,
AG1, AG32,
AH2, AJ33,
AL32, AM3,
AM7, AM11,
AM19, AM25,
AM28, AM33,
AN1, AN2,
AN5, AN10,
AN14, AN16,
AN20, AN22,
AN27, AN33
are general I/O.
V
, Bank 3
V4, W5,
AA4, AD3,
AE5, AF1,
AH4, AK2
REF
Within each bank, if input
reference voltage is not
required, all V
pins
REF
are general I/O.
V
, Bank 4
AK13, AL7,
AL9, AL10,
AL16, AM4,
AM14,AN3
REF
Within each bank, if input
reference voltage is not
required, all V
pins
REF
are general I/O.
V
, Bank 5
AJ18, AJ25,
AK28, AL20,
AL24, AL29,
AM26, AN23
REF
Within each bank, if input
reference voltage is not
required, all V
pins
REF
No Connect
XQVR1000 C31, AC2, AK4,
AL3
are general I/O.
DS028 (v1.2) November 5, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
5
R
QPro Virtex 2.5V Radiation Hardened FPGAs
Table 3: CQFP Package (CB228) (Continued)
Table 3: CQFP Package (CB228)
Function
Pin #
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
Bank #
Function
Pin #
1
Bank #
V
6
GND
7
CCO
IO_TRDY
TMS
2
V
IO
3
CCINT
IO
IO
4
IO
IO_VREF_7
5
IO
IO
6
IO_VREF_6
IO
7
IO
IO
GND
8
IO
9
V
IO
IO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
CCO
IO
IO
IO
IO_VREF_7
IO
V
GND
CCINT
GND
V
CCINT
IO
IO
IO_VREF_6
IO
IO
V
CCO
IO
IO
IO_VREF_6
IO
GND
IO_VREF_7
IO
IO
IO
IO
IO_VREF_6
IO
IO
IO
IO
IO_IRDY
GND
IO
M1
GND
M0
6
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DS028 (v1.2) November 5, 2001
Preliminary Product Specification
R
QPro Virtex 2.5V Radiation Hardened FPGAs
Table 3: CQFP Package (CB228) (Continued)
Table 3: CQFP Package (CB228) (Continued)
Function
Pin #
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
Bank #
Function
Pin #
83
Bank #
V
5
V
4
CCO
CCINT
M2
GCK1
84
IO
VCCO
85
IO
GND
86
IO
GCKO
87
IO_VREF_5
IO
88
IO
IO
IO
89
IO
90
GND
IO
91
IO_VREF_5
IO
IO_VREF_4
92
IO
IO
93
IO
94
IO_VREF5
IO
V
95
CCO
IO
96
GND
IO
IO
97
V
98
CCINT
IO
V
99
CCINT
IO
GND
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
V
IO
CCO
IO
IO_VREF_4
IO
IO
IO_VREF_5
IO
IO
IO
IO
IO_VREF_4
GND
IO
IO
IO_VREF_4
IO
IO
IO
GND
DONE
V
CCO
DS028 (v1.2) November 5, 2001
Preliminary Product Specification
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R
QPro Virtex 2.5V Radiation Hardened FPGAs
Table 3: CQFP Package (CB228) (Continued)
Table 3: CQFP Package (CB228) (Continued)
Function
PROGRAM
IO_INIT
IO_D7
IO
Pin #
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
Bank #
Function
Pin #
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
Bank #
3
GND
2
IO_IRDY
IO
IO
IO_VREF_3
IO
IO
IO_D3
IO_VREF_2
IO
IO
GND
IO_VREF_3
IO
IO
V
CCO
IO
IO
IO_VREF_3
IO_D6
GND
IO
IO_D2
V
CCINT
V
GND
IO_D1
CCINT
IO_D5
IO
IO_VREF_2
IO
V
CCO
IO
IO
IO
IO_VREF_2
GND
IO_VREF_3
IO_D4
IO
IO
IO
IO
IO_VREF_2
IO
V
CCINT
IO_TRDY
IO_DIN_D0
IO_DOUT_BUSY
CCLK
V
CCO
V
CCO
8
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DS028 (v1.2) November 5, 2001
Preliminary Product Specification
R
QPro Virtex 2.5V Radiation Hardened FPGAs
Table 3: CQFP Package (CB228) (Continued)
Table 3: CQFP Package (CB228) (Continued)
Function
TDO
Pin #
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
Bank #
Function
Pin #
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
Bank #
1
GCK3
0
GND
V
CCINT
TDI
IO
IO_CS
IO_WRITE
IO
IO
IO
IO_VREF_0
IO_VREF_1
IO
IO
IO
GND
V
CCO
IO_VREF_1
IO
IO
IO
IO
IO
IO_VREF_1
IO
V
CCINT
GND
GND
IO
V
IO_VREF_0
CCINT
IO
IO
IO
IO
IO
IO_VREF_0
V
GND
CCO
IO
IO
IO
IO
IO_VREF_1
IO_VREF_0
IO
IO
IO
IO
IO
TCK
IO
V
CCO
GCK2
GND
V
CCO
DS028 (v1.2) November 5, 2001
Preliminary Product Specification
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9
R
QPro Virtex 2.5V Radiation Hardened FPGAs
Table 3: CQFP Package (CB228) (Continued)
Table 4: Pinout Diagram Symbols (Continued)
Function
Pin #
Bank #
Symbol
Pin Function
GND
1, 8, 14, 27, 42,
48, 56, 66, 72,
86, 100, 106,
113, 123, 129,
143, 157, 163,
173, 180, 186,
200, 215, 221
-
v
Device-dependent V , n/c on smaller
devices
CCINT
O
R
r
V
V
CCO
REF
Device-dependent V , remains I/O on
REF
smaller devices
V
15, 30, 41, 73,
83, 99, 130,
140, 156, 187,
203, 214
-
-
CCINT
G
Ground
Ø, 1, 2, 3
❿, ❿,❿❿
Global Clocks
M0, M1, M2
V
18, 28, 37, 58,
76, 85, 95, 115,
133, 142, 152,
171, 191, 201,
210, 228
CCO
❿, ❿, ❿, ❿, D0/DIN, D1, D2, D3, D4, D5, D6, D7
❿, ❿, ❿, ❿
B
D
P
I
DOUT/BUSY
DONE
Pinout Diagrams
PROGRAM
The following diagrams illustrate the locations of spe-
cial-purpose pins on Virtex FPGAs. Table 4 lists the sym-
bols used in these diagrams. The diagrams also show
I/O-bank boundaries.
INIT
K
W
S
T
+
–
CCLK
WRITE
Table 4: Pinout Diagram Symbols
CS
Symbol
Pin Function
Boundary-scan test access port
Temperature diode, anode
Temperature diode, cathode
No connect
S
d
General I/O
Device-dependent general I/O, n/c on
smaller devices
n
V
V
CCINT
10
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DS028 (v1.2) November 5, 2001
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Preliminary Product Specification
R
QPro Virtex 2.5V Radiation Hardened FPGAs
CG560 Pin Function Diagram
❿ ❿ ❿
❿ ❿
❿
❿
❿
❿
❿
❿ ❿
G V
❿
G O
A
B
G S
R G
G
O
G
G
O 3 G R G V O
G
O
G G
A
B
❿ ❿ ❿ ❿ ❿ ❿
❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿
❿ ❿
G O r
G
v O V G
V O
G
G O T
❿
O
G
❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿
❿
❿ ❿ ❿ ❿ ❿ ❿
❿
n O
C
D
E
G O K
❿ ❿
❿ ❿ ❿
v
V
C
D
E
❿ ❿
❿
❿ ❿
❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿
❿
❿
❿
O
B T W R
r R
r
R 2
R
R
❿ ❿
r
T
r
❿
❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿
❿
❿
❿ ❿
O T r
V
V
R
r
R r
R
R
❿
❿
O
❿ ❿ ❿
❿ ❿ ❿
❿
G
❿
❿
F
G
H
J
V
G
G
❿
r
F
G
H
J
Bank 1
Bank 0
❿ ❿
❿ ❿
R
R
❿ ❿
❿
❿
❿
R
V
❿ ❿ ❿ ❿
❿ ❿ ❿
V
G
❿ ❿ ❿
❿ ❿
R V O
K
L
M
G
❿
O
r
R
K
L
M
Bank 2
Bank 7
❿ ❿
❿ ❿ ❿ ❿
❿ ❿ ❿ ❿
G
r
G
❿
❿ ❿
v
❿ ❿ ❿
❿ ❿
O V
N
V
r
v
N
❿ ❿
❿
❿ ❿
❿ ❿ ❿
❿ ❿
❿
G
❿
P
R
T
G
R
R
G
❿
O
P
R
T
❿ ❿ ❿
R O
CG560
❿ ❿ ❿ ❿
(Top View)
G
R
❿ ❿ ❿ ❿
❿
❿ ❿ ❿
V
U
V
U
❿ ❿
❿
❿ ❿ ❿
V
O
R
R
G
V
❿
G V
❿ ❿
❿ ❿ ❿
❿ ❿ ❿
❿ ❿
V R G
❿
W
Y
G
R
O
W
Y
❿
G v
❿
O V R
❿
r
G
❿
❿
❿ ❿ ❿
❿ ❿ ❿
❿
❿
❿ ❿ ❿
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
O
r
r
AA
❿ ❿ ❿
❿ ❿ ❿
Bank 6
v O AB
❿
AC
n
G
Bank 3
❿ ❿
❿ ❿
R V G AD
R
❿ ❿ ❿ ❿
O AF
❿ ❿
❿ ❿
❿ ❿ ❿ ❿
❿
❿ ❿
r AE
G
R
❿
G
❿ ❿
❿
V G
❿ ❿ ❿
V
❿
AG
AH
Bank 4
Bank 5
❿
r
r
I
D
❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿
O R
❿
P O G R
G G r O G
❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿
v
r
1 R
V
R
+
G AJ
❿
O n
❿ ❿ ❿ ❿ ❿
❿
❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿ ❿
❿ ❿
r – R O AK
n
V
V
V
❿ ❿ ❿
❿
❿ ❿ ❿
❿
R O
❿ ❿
❿
O
❿
❿
❿ ❿
❿
G
❿
❿
R
r R
V
R Ø
R
❿
G
v
R
V
❿
G
R
O G
AL
❿ ❿ ❿ ❿ ❿ ❿ ❿
❿ ❿ ❿
❿ ❿ ❿
❿ ❿ ❿
G
G
❿
G
❿
G r
O G AM
❿ ❿
❿
❿
❿
❿
❿
❿ ❿ ❿ ❿
O G AN
O
G
O
G
G
O
G r O V
DS028 (v1.2) November 5, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
11
R
QPro Virtex 2.5V Radiation Hardened FPGAs
Package Drawing CG560 Ceramic Column Grid
DS028_01_011900
12
www.xilinx.com
DS028 (v1.2) November 5, 2001
1-800-255-7778
Preliminary Product Specification
R
QPro Virtex 2.5V Radiation Hardened FPGAs
Device/Package Combinations and Maximum I/O
Maximum User I/O (excluding dedicated clock pins)
Package
CB228
XQVR300
XQVR600
XQVR1000
162
-
162
-
-
CG560
404
Ordering Information
Example:
XQVR1000 -4 CG 560 V
Device Type
Manufacturing Grade
Number of Pins
Package Type
(1)
Speed Grade
Device Ordering Options
Device Type
XQVR300
XQVR600
XQVR1000
Notes:
Package
228-pin Ceramic Quad Flat Package
CG560 560-column Ceramic Column Grid Package
Grade
CB228
Military Ceramic
QPro Plus
T = –55°C to +125°C
M
V
C
T = –55°C to +125°C
C
(2)
Q
MIL-PRF-38535
T = –55°C to +125°C
C
1. -4 only supported speed grade.
2. Class Q must be ordered with SMD number.
Device Ordering Combinations
M Grade
V Grade
XQVR300-4CB228M
XQVR600-4CB228M
XQVR1000-4CG560M
XQVR300-4CB228V
XQVR600-4CB228V
XQVR1000-4CG560V
DS028 (v1.2) November 5, 2001
www.xilinx.com
13
Preliminary Product Specification
1-800-255-7778
R
QPro Virtex 2.5V Radiation Hardened FPGAs
SMD (Class Q) Odering Options
5962 R 9957201 Q Y C
Generic Standard
Microcircuit Drawing (SMD)
Lead Finish
Package Type
Radiation Hardened
Device Type
QML Certified MIL-PRF-38535
Valid SMD Combinations
SMD Number
Device
Pkg Markings
Lead Finish
Gold Plate
5962R9957201QYC
5962R9957201QZC
5962R9957301QYC
5962R9957301QZC
5962R9957401QXC
XQVR300-4CB228Q
XQVR300-4CB228Q
XQVR600-4CB228Q
XQVR600-4CB228Q
XQVR1000-4CG560Q
Lid
Base
Lid
Gold Plate
Gold Plate
Base
-
Gold Plate
Solder Column
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
04/25/00
02/13/01
11/05/01
Initial Xilinx release.
1.1
Updated TemperatureSpecifications.
1.2
Updated Temp specifications for V600, Added Class V option and SMD. Updated format.
14
www.xilinx.com
DS028 (v1.2) November 5, 2001
1-800-255-7778
Preliminary Product Specification
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