XA3S50-4VQ100Q [XILINX]
Field Programmable Gate Array, 192 CLBs, 50000 Gates, 125MHz, 1728-Cell, PQFP100, VQFP-100;
| 型号： | XA3S50-4VQ100Q |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 192 CLBs, 50000 Gates, 125MHz, 1728-Cell, PQFP100, VQFP-100 时钟 栅 可编程逻辑 |
| 文件： | 总6页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
06
Spartan-3 Automotive XA FPGA
Family:
Introduction and Ordering
Advance Product Specification
R
0
0
DS314-1 (v1.1) December 20, 2004
-
-
-
-
-
-
622 Mb/s data transfer rate per I/O
Introduction
Seventeen single-ended signal standards
Seven differential signal standards including LVDS
Termination by Digitally Controlled Impedance
Signal swing ranging from 1.14V to 3.45V
Double Data Rate (DDR) support
The Xilinx Automotive (XA) Spartan™-3 family of Field-Pro-
grammable Gate Arrays is specifically designed to meet the
needs of high volume, cost-sensitive automotive consumer
electronic applications. The four-member family offers den-
sities ranging from 50,000 to one million system gates, as
shown in Table 1.
•
Logic resources
-
-
-
-
-
Abundant logic cells with shift register capability
Wide multiplexers
Fast look-ahead carry logic
Dedicated 18 x 18 multipliers
JTAG logic compatible with IEEE 1149.1/1532
XA devices are available in both the extended-temperature
Q-grade (-40°C to +125°C) and industrial I-grade (-40°C to
+100°C) and are qualified to the industry-recognized
AEC-Q100 standard.
The XA Spartan-3 family builds on the success of the earlier
XA Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. Numerous
enhancements derive from state-of-the-art Virtex™-II tech-
nology. These Spartan-3 enhancements, combined with
advanced process technology, deliver more functionality
and bandwidth per dollar than was previously possible, set-
ting new standards in the programmable logic industry.
•
•
SelectRAM™ hierarchical memory
-
-
Up to 432 Kbits of total block RAM
Up to 120 Kbits of total distributed RAM
Digital Clock Manager (up to four DCMs)
-
-
Clock skew elimination
Frequency synthesis
•
•
Fully supported by Xilinx ISE development system
Synthesis, mapping, placement and routing
-
MicroBlaze™ processor, CAN, LIN, PCI, and other
cores
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of advanced automotive
electronics modules and systems ranging from the latest
driver assistance and infotainment systems to reconfig-
urable instrument clusters and ECU gateways.
•
•
Pb-free packaging options
Xilinx and all of our production partners are qualified to
QS-9000, moving to TS16949 in 2005.
•
Please refer to the Spartan-3 complete data sheet
(DS099) for a full product description, AC and DC
specifications, and package pinout descriptions.
The Spartan-3 family is a superior alternative to mask pro-
grammed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
Features
•
AEC-Q100 device qualification and full PPAP support
available in both extended temperature Q-grade and
I-grade.
•
Guaranteed to meet full electrical specification up to
TJ=-40°C to +125°C.
•
•
Revolutionary 90-nanometer process technology
Very low cost, high-performance logic solution for
high-volume, automotive applications
-
Three power rails: for core (1.2V), I/Os (1.2V to
3.0V), and auxiliary purposes (2.5V)
•
SelectIO™ signaling
Up to 333 I/O pins
-
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS314-1 (v1.1) December 20, 2004
www.xilinx.com
1
Advance Product Specification
R
Spartan-3 Automotive XA FPGA Family: Introduction and Ordering Information
.
Table 1: Summary of Spartan-3 FPGA Attributes
CLB Array
(One CLB = Four Slices)
Maximum
Maximum Differential
System
Gates
Logic
Cells
Distributed BlockRAM
Dedicated
Multipliers
Device
XA3S50
Rows Columns Total CLBs RAM (bits1)
(bits1)
DCMs
User I/O
I/O Pairs
50K
200K
400K
1M
1,728
4,320
8,064
17,280
16
24
32
48
12
20
28
40
192
480
12K
30K
72K
4
2
4
4
4
63
56
XA3S200
XA3S400
XA3S1000
Notes:
216K
288K
432K
12
16
24
173
76
896
56K
173
76
1,920
120K
333
149
1. By convention, one Kb is equivalent to 1,024 bits.
Architectural Overview
The Spartan-3 family architecture consists of five funda-
mental programmable functional elements:
•
•
Multiplier blocks accept two 18-bit binary numbers as
inputs and calculate the product.
Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase shifting clock
signals.
•
Configurable Logic Blocks (CLBs) contain RAM-based
Look-Up Tables (LUTs) to implement logic and storage
elements that can be used as flip-flops or latches.
CLBs can be programmed to perform a wide variety of
logical functions as well as to store data.
These elements are organized as shown in Figure 1. A ring
of IOBs surrounds a regular array of CLBs. The XA3S50
has a single column of block RAM embedded in the array.
Those devices ranging from the XA3S200 to the XA3S1000
have two columns of block RAM. Each column is made up
of several 18K-bit RAM blocks; each block is associated
with a dedicated multiplier. The DCMs are positioned at the
ends of the block RAM columns.
•
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Twenty-four different signal
standards,
including
seven
high-performance
differential standards, are available as shown in
Table 2. Double Data-Rate (DDR) registers are
included. The Digitally Controlled Impedance (DCI)
feature provides automatic on-chip terminations,
simplifying board designs.
The Spartan-3 family features a rich network of traces and
switches that interconnect all five functional elements,
transmitting signals among them. Each functional element
has an associated switch matrix that permits multiple con-
nections to the routing.
•
Block RAM provides data storage in the form of 18-Kbit
dual-port blocks.
2
6
www.xilinx.com
DS314-1 (v1.1) December 20, 2004
Advance Product Specification
R
Spartan-3 Automotive XA FPGA Family: Introduction and Ordering Information
DS099-1_01_102204
Notes:
1. The XA3S50 has only the block RAM column on the far left.
Figure 1: Spartan-3 Family Architecture
DS314-1 (v1.1) December 20, 2004
www.xilinx.com
3
Advance Product Specification
R
Spartan-3 Automotive XA FPGA Family: Introduction and Ordering Information
which includes the XCF00S PROMs for serial configuration
and the higher density XCF00P PROMs for parallel or serial
configuration.
Configuration
Spartan-3 FPGAs are programmed by loading configuration
data into robust static memory cells that collectively control
all functional elements and routing resources. Before pow-
ering on the FPGA, configuration data is stored externally in
a PROM or some other nonvolatile medium either on or off
the board. After applying power, the configuration data is
written to the FPGA using any of five different modes: Mas-
ter Parallel, Slave Parallel, Master Serial, Slave Serial and
Boundary Scan (JTAG). The Master and Slave Parallel
modes use an 8-bit wide SelectMAP™ port.
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports 17 sin-
gle-ended standards and seven differential standards as
listed in Table 2. Many standards support the DCI feature,
which uses integrated terminations to eliminate unwanted
signal reflections. Table 3 shows the number of user I/Os as
well as the number of differential I/O pairs available for each
device/package combination.
The recommended memory for storing the configuration
data is the low-cost Xilinx Platform Flash PROM family,
Table 2: Signal Standards Supported by the Spartan-3 Family
Standard
Category
V
DCI
Option
CCO
Description
Gunning Transceiver Logic
High-Speed Transceiver Logic
(V)
N/A
1.5
1.8
Class
Symbol
Single-Ended
GTL
Terminated
GTL
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Plus
GTLP
HSTL
I
III
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
I
II
III
LVCMOS
Low-Voltage CMOS
1.2
1.5
1.8
2.5
3.3
3.3
3.0
1.8
2.5
N/A
N/A
N/A
N/A
N/A
N/A
33 MHz
N/A
I
Yes
Yes
Yes
Yes
No
LVTTL
PCI
Low-Voltage Transistor-Transistor Logic
Peripheral Component Interconnect
Stub Series Terminated Logic
PCI33_3
No
SSTL
SSTL18_I
SSTL2_I
Yes
Yes
Yes
II
SSTL2_II
Differential
LDT
(ULVDS)
Lightning Data Transport
(HyperTransport™)
2.5
N/A
LDT_25
No
LVDS
Low-Voltage Differential Signaling
Standard
Bus
LVDS_25
Yes
No
BLVDS_25
LVDSEXT_25
LVPECL_25
Extended Mode
N/A
Yes
No
LVPECL
RSDS
Low-Voltage Positive Emitter-Coupled
Logic
2.5
2.5
Reduced-Swing Differential Signaling
N/A
RSDS_25
No
4
6
www.xilinx.com
DS314-1 (v1.1) December 20, 2004
Advance Product Specification
R
Spartan-3 Automotive XA FPGA Family: Introduction and Ordering Information
Table 3: Spartan-3 XA I/O Chart
Available User I/Os and Differential (Diff) I/O
Pairs
VQG100
PQG208 FTG256
FGG456
Device
XA3S50
User Diff User Diff User Diff User Diff
63
63
-
29
29
-
124
141
141
-
56
62
62
-
-
-
-
-
-
-
-
-
XA3S200
XA3S400
XA3S1000
Notes:
173
173
-
76
76
-
-
-
333 149
1. All device options listed in a given package column are
pin-compatible.
Ordering Information
Spartan-3 FPGAs are available in Pb-free packaging options for all device/package combinations. The Pb-free packages
include a special ’G’ character in the ordering code.
Pb-Free Packaging
For additional information on Pb-free packaging, see XAPP427: Xilinx Lead Free Packages.
Example: XA3S50 -4 PQ G 208 Q
Device Type
Speed Grade
Package Type
Temperature Range:
Q = Automotive Extended (T = -40
˚
C to +125
˚
C)
I = Automotive Industrial (TJJ= -40
˚
C to +100 C)
˚
Number of Pins
Pb-free
DS099-1_02b_100804
Device
Speed Grade
Package Type / Number of Pins
Temperature Range (TJ)
XA3S50
-4 Standard Performance VQ(G)100 100-pin Very Thin Quad Flat Pack (VQFP)
I
Automotive Industrial
(–40°C to +100°C)
XA3S200
PQ(G)208 208-pin Plastic Quad Flat Pack (PQFP)
Q Automotive Extended
(–40°C to +125°C)
XA3S400
FT(G)256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
FG(G)456 456-ball Fine-Pitch Ball Grid Array (FBGA)
XA3S1000
Revision History
Date
Version No.
Description
10/18/04
12/20/04
1.0
1.1
Initial Xilinx release.
Multiple text edits throughout.
DS314-1 (v1.1) December 20, 2004
www.xilinx.com
5
Advance Product Specification
R
Spartan-3 Automotive XA FPGA Family: Introduction and Ordering Information
The Spartan-3 Family Data Sheet
DS099-1, Spartan-3 FPGA Family: Introduction and Ordering Information (Module 1)
DS099-2, Spartan-3 FPGA Family: Functional Description (Module 2)
DS099-3, Spartan-3 FPGA Family: DC and Switching Characteristics (Module 3)
DS099-4, Spartan-3 FPGA Family: Pinout Descriptions (Module 4)
6
6
www.xilinx.com
DS314-1 (v1.1) December 20, 2004
Advance Product Specification
相关型号：
XA3S50-4VQG100I
Field Programmable Gate Array, 192 CLBs, 50000 Gates, 125MHz, 1728-Cell, PQFP100, LEAD FREE, VQFP-100
XILINX
XA3S50-4VQG100Q
Field Programmable Gate Array, 192 CLBs, 50000 Gates, 125MHz, 1728-Cell, PQFP100, LEAD FREE, VQFP-100
XILINX
XA3S500E-4CPG132Q
Field Programmable Gate Array, 1164 CLBs, 500000 Gates, 572MHz, 10476-Cell, CMOS, PBGA132, LEAD FREE, CSP-132
XILINX
XA3S500E-4FGG400I
Field Programmable Gate Array, 1164 CLBs, 500000 Gates, 572MHz, CMOS, PBGA400, 21 X 21MM, LEAD FREE, FBGA-400
XILINX
XA3S500E-4FGG400Q
Field Programmable Gate Array, 1164 CLBs, 500000 Gates, 572MHz, CMOS, PBGA400, 21 X 21MM, LEAD FREE, FBGA-400
XILINX
XA3S500E-4FGG484I
Field Programmable Gate Array, 1164 CLBs, 500000 Gates, 572MHz, CMOS, PBGA484, 23 X 23 MM, LEAD FREE, FBGA-484
XILINX
XA3S500E-4FGG484Q
Field Programmable Gate Array, 1164 CLBs, 500000 Gates, 572MHz, CMOS, PBGA484, 23 X 23 MM, LEAD FREE, FBGA-484
XILINX
XA3S500E-4FTG256I
Field Programmable Gate Array, 1164 CLBs, 500000 Gates, 572MHz, 10476-Cell, CMOS, PBGA256, LEAD FREE, FTBGA-256
XILINX
XA3S500E-4FTG256Q
Field Programmable Gate Array, 1164 CLBs, 500000 Gates, 572MHz, 10476-Cell, CMOS, PBGA256, LEAD FREE, FTBGA-256
XILINX
XA3S500E-4PQG208I
Field Programmable Gate Array, 1164 CLBs, 500000 Gates, 572MHz, 10476-Cell, CMOS, PQFP208, LEAD FREE, PLASTIC, QFP-208
XILINX
©2020 ICPDF网 联系我们和版权申明