XC4005 [XILINX]
Logic Cell Array Family; 逻辑单元阵列系列
| 型号： | XC4005 |
| 厂家： | 
XILINX, INC |
| 描述： | Logic Cell Array Family |
| 文件： | 总22页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XC4000
Logic Cell Array Family
Product Specifications
Description
Features
The XC4000 family of Field-Programmable Gate Arrays
(FPGAs) provides the benefits of custom CMOS VLSI,
while avoiding the initial cost, time delay, and inherent risk
of a conventional masked gate array.
•
Third Generation Field-Programmable Gate Arrays
– Abundant flip-flops
– Flexible function generators
– On-chip ultra-fast RAM
– Dedicated high-speed carry-propagation circuit
– Wide edge decoders (four per edge)
– Hierarchy of interconnect lines
– Internal 3-state bus capability
– Eight global low-skew clock or signal distribution
network
Flexible Array Architecture
– Programmable logic blocks and I/O blocks
– Programmable interconnects and wide decoders
The XC4000 family provides a regular, flexible, program-
mable architecture of Configurable Logic Blocks (CLBs),
interconnected by a powerful hierarchy of versatile routing
resources, and surrounded by a perimeter of program-
mable Input/Output Blocks (IOBs).
XC4000 devices have generous routing resources to ac-
commodate the most complex interconnect patterns. They
are customized by loading configuration data into the inter-
nal memory cells. The FPGA can either actively read its
configuration data out of external serial or byte-parallel
PROM (master modes), or the configuration data can be
written into the FPGA (slave and peripheral modes).
•
•
•
Sub-micron CMOS Process
– High-speed logic and Interconnect
– Low power consumption
The XC4000 family is supported by powerful and sophisti-
cated software, covering every aspect of design: from
schematic entry, to simulation, to automatic block place-
ment and routing of interconnects, and finally the creation
of the configuration bit stream.
Systems-Oriented Features
– IEEE 1149.1-compatible boundary-scan logic support
– Programmable output slew rate (2 modes)
– Programmable input pull-up or pull-down resistors
– 12-mA sink current per output
Since Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
waremustbeadaptedtodifferentuserapplications.FPGAs
are ideal for shortening the design and development cycle,
but they also offer a cost-effective solution for production
rates well beyond 1000 systems per month.
– 24-mA sink current per output pair
•
•
Configured by Loading Binary File
– Unlimited reprogrammability
– Six programming modes
XACT Development System runs on ’386/’486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700
series
– Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
– Fully automatic partitioning, placement and routing
– Interactive design editor for design optimization
– 288 macros, 34 hard macros, RAM/ROM compiler
For a detailed description of the device features, architec-
ture, configuration methods and pin descriptions, see
pages 2-9 through 2-45.
Table 1. The XC4000 Family of Field-Programmable Gate Arrays
Device
XC4003
XC4005
XC4006
XC4008 XC4010/10D XC4013
XC4020
XC4025
Appr. Gate Count
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs (per side)
Max RAM Bits
3,000
10 x 10
100
360
30
5,000
14 x 14
196
616
42
6,000
16 x 16
256
768
48
8,000
18 x 18
324
936
54
10,000
20 x 20
400
1,120
60
13,000
24 x 24
576
1,536
72
20,000
28 x 28
784
2,016
84
25,000
32 x 32
1,024
2,560
96
3,200
80
6,272
112
8,192
128
10,368
144
12,800*
160
18,432
192
25,088
224
32,768
256
Number of IOBs
*XC4010D has no RAM
2-47
XC4000 Logic Cell Array Family
Absolute Maximum Ratings
Symbol
VCC
Description
Units
V
Supply voltage relative to GND
Input voltage with respect to GND
Voltage applied to 3-state output
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
Junction temperature
–0.5 to +7.0
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–65 to + 150
+ 260
VIN
V
VTS
V
TSTG
TSOL
TJ
°C
°C
°C
+ 150
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings
conditions for extended periods of time may affect device reliability.
Operating Conditions
Symbol
Description
Min
4.75
4.5
Max Units
VCC
Supply voltage relative to GND Commercial 0°C to 85°C junction
Supply voltage relative to GND Industrial -40°C to 100°C junction
Supply voltage relative to GND Military –55°C to 125°C case
High-level input voltage (XC4000 has TTL-like input thresholds)
Low-level input voltage (XC4000 has TTL-like input thresholds)
Input signal transition time
5.25
5.5
V
V
4.5
5.5
V
VIH
VIL
TIN
2.0
VCC
0.8
V
0
V
250
ns
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
DC Characteristics Over Operating Conditions
Symbol
VOH
VOL
Description
Min
Max
Units
V
High-level output voltage @ IOH = –4.0 mA, VCC min
Low-level output voltage @ IOL = 12.0 mA, VCC min (Note 1)
Quiescent LCA supply current (Note 2)
Leakage current
2.4
0.4
10
V
ICCO
IIL
mA
µA
pF
–10
+10
15
CIN
Input capacitance (sample tested)
IRIN
Pad pull-up (when selected) @ VIN = 0V (sample tested)
Horizontal Long Line pull-up (when selected) @ logic Low
0.02
0.2
0.25 mA
2.5 mA
IRLL
Note: 1. With 50% of the outputs simultaneously sinking 12 mA.
2. With no output current loads, no active input or longline pull-up resistors, all package pins at VCC or GND, and
the LCA configured with a MakeBits tie option.
2-48
Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
-4
Description
Symbol
Device
Max
Max
Max
Units
Full length, both pull-ups,
inputs from IOB I-pins
TWAF
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
9.0
10.0
11.0
12.0
13.0
15.0
21.0
8.0
9.0
5.0
6.0
7.0
8.0
9.0
ns
ns
ns
ns
ns
ns
ns
10.0
11.0
12.0
14.0
19.0
11.0
17.0
Full length, both pull-ups
inputs from internal logic
TWAFL
TWAO
TWAOL
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
12.0
13.0
14.0
15.0
16.0
18.0
24.0
11.0
12.0
13.0
14.0
15.0
17.0
23.0
7.0
8.0
9.0
10.0
11.0
13.0
20.0
ns
ns
ns
ns
ns
ns
ns
Half length, one pull-up
inputs from IOB I-pins
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
9.0
10.0
11.0
12.0
13.0
15.0
21.0
8.0
9.0
6.0
7.0
8.0
ns
ns
ns
ns
ns
ns
ns
10.0
11.0
12.0
14.0
19.0
9.0
10.0
12.0
18.0
Half length, one pull-up
inputs from internal logic
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
12.0
13.0
14.0
15.0
16.0
18.0
24.0
11.0
12.0
13.0
14.0
15.0
17.0
23.0
8.0
9.0
ns
ns
ns
ns
ns
ns
ns
10.0
11.0
12.0
14.0
21.0
Note: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (TPID
)
and output delay (TOPF or TOPS), as listed on page 2-52.
PRELIMINARY
2-49
XC4000 Logic Cell Array Family
Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
-4
Description
Symbol
Device
Max
Max
Max
Units
Global Signal Distribution
From pad through primary buffer, to any clock K
TPG
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
7.8
8.0
8.2
8.6
9.0
5.8
6.0
6.2
6.6
7.0
5.1
5.5
5.7
6.1
6.5
ns
ns
ns
ns
ns
ns
ns
10.0
17.0
8.0
15.0
7.5
14.5
From pad through secondary buffer, to any clock K
TSG
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
8.8
9.0
9.2
6.8
7.0
7.2
7.6
8.0
6.3
6.7
6.9
7.3
7.7
ns
ns
ns
ns
ns
ns
ns
9.6
10.0
11.0
18.0
9.0
16.0
8.7
15.7
Horizontal Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
-4
Description
Symbol
TIO1
Device
Max
Max
Max
Units
TBUF driving a Horizontal Longline (L.L.)
I going High or Low to L.L. going High or Low,
while T is Low, i.e. buffer is constantly active
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
8.8
10.0
10.6
11.1
11.7
13.0
20.0
6.2
7.0
7.5
8.0
8.5
4.4
5.5
6.0
6.5
7.0
7.5
14.5
ns
ns
ns
ns
ns
ns
ns
9.5
16.5
I going Low to L.L. going from resistive pull-up
TIO2
XC4003
9.3
6.7
5.0
ns
High to active Low, (TBUF configured as open drain)
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
10.5
11.1
11.6
12.2
13.5
23.5
7.5
8.0
8.5
9.0
10.0
20.0
6.0
6.5
7.0
7.5
8.0
ns
ns
ns
ns
ns
ns
18.0
T going Low to L.L. going from resistive pull-up or
floating High to active Low, (TBUF configured as
open drain or active buffer with I = Low)
TON
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
10.7
12.0
12.6
13.2
13.8
15.1
23.0
9.0
10.0
10.5
11.0
11.5
12.6
20.5
7.2
8.0
8.5
9.0
9.5
ns
ns
ns
ns
ns
ns
ns
11.1
19.0
T going High to TBUF going inactive, not driving L.L.
TOFF
TPUS
All devices
3.0
2.0
1.8
ns
T going High to L.L. going from Low to High,
pulled up by a single resistor
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
24.0
26.0
28.0
30.0
32.0
36.0
52.0
20.0
22.0
24.0
26.0
28.0
32.0
48.0
14.0
16.0
18.0
20.0
22.0
26.0
42.0
ns
ns
ns
ns
ns
ns
ns
T going High to L.L. going from Low to High,
pulled up by two resistors
TPUF
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
11.6
12.0
13.0
14.0
15.0
17.0
24.0
9.0
10.0
11.0
12.0
13.0
15.0
22.0
7.0
8.0
9.0
10.0
11.0
13.0
20.0
ns
ns
ns
ns
ns
ns
ns
PRELIMINARY
2-50
Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be derived
indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a
discrepancy between these two methods, the values listed below should be used, and the derived values must be ignored.
Speed Grade
-6
-5
-4
Description
Symbol
Device
Units
Global Clock to Output (fast) using OFF
TICKOF
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
15.1
15.5
15.7
16.1
16.5
17.5
25.5
12.5
13.0
13.2
13.6
14.0
15.0
22.0
11.6
12.0
12.2
12.6
13.0
14.0
21.0
ns
ns
ns
ns
ns
ns
ns
.
.
.
.
.
T
OFF
PG
(Max)
Global Clock-to-Output Delay
X3202
Global Clock to Output (slew limited) using OFF
TICKO
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
19.9
20.5
20.7
21.1
21.5
22.5
29.5
15.2
16.0
16.2
16.6
17.0
18.0
25.0
14.4
15.0
15.2
15.6
16.0
17.0
24.0
ns
ns
ns
ns
ns
ns
ns
.
.
.
.
.
T
OFF
PG
(Max)
Global Clock-to-Output Delay
Input Set-up Time, using IFF (no delay)
X3202
TPSUF
(Min)
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
2.4
2.0
1.8
1.4
1.0
0.5
0
2.0
1.5
1.3
0.9
0.5
0
1.6
1.2
1.0
0.6
0.2
0
ns
ns
ns
ns
ns
ns
ns
D
Input
Set-Up
&
Hold
Time
T
IFF
PG
X3201
0
0
Input Hold time, using IFF (no delay)
TPHF
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
5.1
5.5
5.7
6.1
6.5
4.0
4.5
4.7
5.1
5.5
4.0
4.5
4.7
5.1
5.5
ns
ns
ns
ns
ns
ns
ns
D
Input
Set-Up
&
Hold
Time
T
IFF
PG
(Min)
7.5
18.0
6.5
16.0
6.5
15.5
X3201
Input Set-up Time, using IFF (with delay)
TPSU
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
21.5
21.0
20.8
20.4
20.0
19.0
18.0
18.5
18.0
17.8
17.4
17.0
16.0
15.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
ns
ns
ns
ns
ns
ns
ns
D
Input
Set-Up
&
Hold
Time
T
IFF
PG
(Min)
X3201
Input Hold Time, using IFF (with delay)
TPH
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
D
Input
Set-Up
&
Hold
Time
T
IFF
PG
(Min)
X3201
Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). When testing fast outputs, only one
output switches. When testing slew-rate limited outputs, half the number of outputs on one side of the device are switching. These
parameter values are tested and guaranteed for worst-case conditions of supply voltage and temperature, and also with the most
unfavorable clock polarity choice.
T
for -4 Speed Grade
T
for -4 Speed Grade
PICKD
PDLI
XC4003 15.6 ns
XC4003 17.6 ns
XC4005 17.9 ns
XC4006 18.0 ns
XC4008 18.3 ns
XC4010 18.6 ns
XC4013 19.3 ns
XC4025 23.5 ns
Pad to I1, I2
via transparent
latch, with delay
Input set-up time
pad to clock (IK)
with delay
XC4005 15.9 ns
XC4006 16.0 ns
XC4008 16.3 ns
XC4010 16.6 ns
XC4013 17.3 ns
XC4025 22.5 ns
X6082
See page 2-52
PRELIMINARY
2-51
XC4000 Logic Cell Array Family
IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
-4
Description
Symbol Min Max
Min Max Min Max Units
Input
Propagation Delays
Pad to I1, I2
TPID
TPLI
TPDLI
TIKRI
TIKLI
4.0
8.0
26.0
8.0
3.0
7.0
24.0
7.0
2.8
6.0
**
6.0
6.0
ns
ns
ns
ns
ns
Pad to I1, I2, via transparent latch (no delay)
Pad to I1, I2, via transparent latch (with delay)
Clock (IK) toI1, I2, (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
8.0
7.0
Set-up Time (Note 3)
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
TPICK
TPICKD
7.0
25.0
6.0
24.0
4.0
**
ns
ns
Hold Time (Note 3)
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
TIKPI
TIKPID
1.0
neg
1.0
neg
1.0
neg
ns
ns
Output
Propagation Delays
Clock (OK) to Pad
same
Output (O) to Pad
same
3-state to Pad begin hi-Z (slew-rate independent)
3-state to Pad active and valid (fast)
same
(fast)
(slew rate limited)
(fast)
TOKPOF
TOKPOS
TOPF
7.5
11.5
9.0
13.0
9.0
7.0
10.0
7.0
10.0
7.0
6.5 ns
9.5 ns
5.5 ns
8.5 ns
6.5 ns
9.5 ns
12.5 ns
(slew-rate limited)
TOPS
TTSHZ
TTSONF
TTSONS
13.0
17.0
10.0
13.0
(slew -rate limited)
Set-up and Hold Times
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
TOOK
TOKO
8.0
0
6.0
0
5.5
0
ns
ns
Clock
Clock High or Low time
T
CH/TCL
5.0
4.5
4.0
ns
Global Set/Reset
Delay from GSR net through Q to I1, I2
Delay from GSR net to Pad
GSR width*
TRRI
TRPO
TMRW
14.5
18.0
13.5
17.0
13.5 ns
14.0 ns
ns
21.0
18.0
18.0
* Timing is based on the XC4005. For other devices see XACT timing calculator.
** See preceding page
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Slew rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on
ground bounce, see pages 8-8 through 8-10.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up or pull-down resistor or alternatively configured as a driven output or be driven from an external source.
3. Input pad setup times and hold times are specified with respect to the internal clock (IK). To calculate system setup time,
subtract clock delay (clock pad to IK) from the specified input pad setup time value, but do not subtract below zero.
Negative hold time means that the delay in the input data is adequate for the external system hold time to be zero,
provided the input clock uses the Global signal distribution from pad to IK.
2-52
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Symbol
-6
-5
-4
Description
Min Max Min Max Min Max Units
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
C inputs via H’ to X/Y outputs
TILO
TIHO
THHO
6.0
8.0
7.0
4.5
7.0
5.0
4.0 ns
6.0 ns
4.5 ns
CLB Fast Carry Logic
Operand inputs (F1,F2,G1,G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1,F3) to COUT
CIN through function generators to X/Y outputs
CIN to COUT, bypass function generators.
TOPCY
TASCY
TINCY
TSUM
TBYP
7.0
8.0
6.0
8.0
2.0
5.5
6.0
4.0
6.0
1.5
5.0 ns
5.5 ns
3.5 ns
5.5 ns
1.5 ns
Sequential Delays
Clock K to outputs Q
TCKO
5.0
3.0
3.0 ns
Set-up Time before Clock K
F/G inputs
TICK
6.0
8.0
7.0
4.0
7.0
6.0
8.0
4.5
6.0
5.0
3.0
4.0
4.5
6.0
7.5
4.5
6.0
5.0
3.0
3.0
4.0
5.5
7.3
ns
ns
ns
ns
ns
ns
ns
ns
F/G inputs via H’
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F'/G'
CIN input via F'/G' and H'
TIHCK
THHCK
TDICK
TECCK
TRCK
TCCK
TCHCK 10.0
Hold Time after Clock K
F/G inputs
TCKI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
F/G inputs via H’
C inputs via H1
C inputs via DIN
C inputs via EC
TCKIH
TCKHH
TCKDI
TCKEC
TCKR
C inputs via S/R, going Low (inactive)
Clock
Clock High time
Clock Low time
TCH
TCL
5.0
5.0
4.5
4.5
4.0
4.0
ns
ns
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
TRPW
TRIO
5.0
4.0
4.0
ns
7.0 ns
9.0
8.0
Master Set/Reset*
Width (High or Low)
Delay from Global Set/Reset net to Q
TMRW 21.0
TMRQ
18.0
18.0
ns
33.0
31.0
28.0 ns
*
Timing is based on the XC4005. For other devices see XACT timing calculator.
2-53
XC4000 Logic Cell Array Family
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
CLB RAM Option
Description
Speed Grade
Symbol
-6
-5
-4
Min Max Min Max Min Max Units
Write Operation
Address write cycle time
16 x 2
TWC
TWCT
TWP
TWPT
TAS
TAST
TAH
TAHT
TDS
9.0
9.0
5.0
5.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
both
Write Enable pulse width (High)
Address set-up time before beginning of WE
Address hold time after end of WE
DIN set-up time before end of WE
DIN hold time after end of WE
TDST
TDHT
Read Operation
Address read cycle time
16 x 2
32 x 1
16 x 2
32 x 1
TRC
7.0
10.0
5.5
7.5
5.0
7.0
ns
ns
4.0 ns
6.0 ns
TRCT
TILO
TIHO
Data valid after address change
(no Write Enable)
6.0
8.0
4.5
7.0
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K
16 x 2
32 x 1
TICK
TIHCK
6.0
8.0
4.5
6.0
4.5
6.0
ns
ns
Read During Write
Data valid after WE going active
(DIN stable before WE)
Data valid after DIN
16 x 2
32 x 1
16 x 2
32 x 1
TWO
TWOT
TDO
12.0
15.0
11.0
14.0
10.0
12.0
9.0
9.0 ns
11.0 ns
8.5 ns
(DIN change during WE)
TDOT
11.0
11.0 ns
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K
16 x 2
32 x 1
16 x 2
32 x 1
TWCK
12.0
10.0
12.0
9.0
9.5
11.5
9.0
ns
ns
ns
ns
TWCKT 15.0
TDCK 11.0
TDCKT 14.0
Data setup time before clock K
11.0
11.0
Note: Timing for the 16 x 1 RAM option is identical to 16 x 2 RAM timing
2-54
CLB RAM Timing Characteristics
T
WC
ADDRESS
WRITE
T
AS
T
T
WP
AH
T
WRITE ENABLE
T
DH
DS
DATA IN
REQUIRED
T
ILO
READ
X,Y OUTPUTS
VALID
VALID
READ, CLOCKING DATA INTO FLIP-FLOP
T
ICK
T
CH
CLOCK
T
CKO
VALID
(OLD)
VALID
(NEW)
XQ,YQ OUTPUTS
READ DURING WRITE
T
WP
WRITE ENABLE
T
DH
DATA IN
(stable during WE)
T
WO
X,Y OUTPUTS
VALID
VALID
DATA IN
(changing during WE)
OLD
NEW
T
T
DO
WO
VALID
(PREVIOUS)
VALID
(OLD)
VALID
(NEW)
X,Y OUTPUTS
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
T
WP
WRITE ENABLE
T
WCK
T
DCK
DATA IN
CLOCK
T
CKO
XQ,YQ OUTPUTS
X2640
2-55
XC4000 Logic Cell Array Family
XC4003 Pinouts
Pin
Description
Bound
PC84 PQ100 PG120 Scan
Pin
Description
Bound
PC84 PQ100 PG120 Scan
VCC
2
3
92
93
94
95
96
97
98
–
G3
G1
–
32
35
38
41
44
47
–
GND
43
44
45
–
41
42
43
44
45
46
47
48
49
–
G11
G13
H13
J13
H12
H11
K13
J12
L13
K12*
J11*
M13
L12
K11
L11
L10
M12
M11
N13
N12*
L9*
M10
N11
M9
N10
L8
–
157
160
163
166
169
172
175
178
–
I/O (A8)
I/O
I/O (A9)
4
F1
I/O
I/O
–
E1
I/O
I/O
–
F2
I/O
–
I/O (A10)
5
F3
I/O
46
47
48
49
–
I/O (A11)
6
D1
I/O
–
–
E2*
C1
I/O
I/O (A12)
7
99
100
–
50
53
–
I/O
I/O (A13)
8
D2
–
–
–
E3*
B1*
C2
–
–
–
–
–
–
–
–
I/O
50
51
52
53
54
55
56
57
–
50
51
52
53
54
55
56
57
–
181
184
–
I/O (A14)
9
1
56
59
–
SGCK3 (I/O)
SGCK1 (A15,I/O)
10
11
12
13
14
–
2
D3
GND
VCC
3
C3
DONE
–
GND
4
C4
–
VCC
–
PGCK1 (A16, I/O)
5
B2
62
65
–
–
PROG
I/O (A17)
6
B3
I/O (D7)
187
190
–
–
–
A1*
A2*
C5
PGCK3 (I/O)
–
–
–
–
–
I/O (TDI)
15
16
–
7
68
71
–
–
–
–
–
I/O (TCK)
8
B4
I/O (D6)
58
–
58
59
60
61
62
63
64
65
66
67
68
69
70
–
193
196
199
202
205
208
211
214
–
–
–
A3*
B5
I/O
I/O (TMS)
17
18
–
9
74
77
80
83
86
89
–
I/O (D5)
59
60
–
I/O
10
–
A4
I/O (CS0)
I/O
C6
I/O
I/O
–
11
12
13
14
15
16
17
18
–
A5
I/O
–
N9
I/O
19
20
21
22
23
24
–
B6
I/O (D4)
61
62
63
64
65
66
–
M8
N8
I/O
A6
I/O
GND
B7
VCC
M7
L7
VCC
C7
–
GND
–
I/O
A7
92
95
98
101
104
107
110
113
–
I/O (D3)
N7
217
220
223
226
229
232
235
238
–
I/O
A8
I/O (RS)
N6
I/O
A9
I/O
N5
I/O
–
B8
I/O
–
M6
L6
I/O
25
26
27
–
19
20
21
22
–
C8
I/O (D2)
67
68
69
70
–
71
72
73
74
–
I/O
A10
B9
I/O
N4
I/O
I/O (D1)
M5
N3
I/O
A11
B10*
C9
I/O (RCLK-BUSY/RDY)
–
I/O
–
–
–
M4*
L5*
N2
28
29
30
31
32
33
34
35
36
–
23
24
25
26
27
28
29
30
31
–
116
119
122
–
–
–
–
SGCK2 (I/O)
O (M1)
GND
A12
B11
C10
C11
D11
B12
C12
A13
B13*
E11*
D12
C13
E12
D13
F11
E13
F12
F13
G12
I/O (D0, DIN)
SGCK4 (DOUT, I/O)
CCLK
71
72
73
74
75
76
77
78
–
75
76
77
78
79
80
81
82
–
241
244
–
M3
L4
I (M0)
VCC
125†
VCC
L3
–
–
O (TDO)
GND
M2
K3
–
I (M2)
PGCK2 (I/O)
I/O (HDC)
–
126†
127
130
–
–
I/O (A0, WS)
PGCK4 (A1, I/O)
–
L2
2
N1
5
M1*
J3*
K2
–
–
–
–
–
–
–
–
–
I/O
–
32
33
34
35
36
37
38
39
40
133
136
139
142
145
148
151
154
–
I/O (CS1, A2)
I/O (A3)
I/O (A4)
I/O (A5)
I/O
79
80
81
82
–
83
84
85
86
87
88
89
90
91
8
I/O (LDC)
I/O
37
38
39
–
L1
11
14
17
20
23
26
29
–
J2
I/O
K1
I/O
H3
I/O
–
I/O
–
J1
I/O
40
41
42
I/O (A6)
I/O (A7)
GND
83
84
1
H2
I/O (ERR, INIT)
VCC
H1
G2
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 247 = BSCANT.UPD
2-56
XC4005 Pinouts
Pin
Description
VCC
Bound
Pin
Description
I/O
Bound
PC84 PQ160 PQ208 PG156 Scan
Pin
Description
Bound
PC84 PQ160 PQ208 PG156 Scan
PC84 PQ160 PQ208 PG156 Scan
2
3
4
–
–
–
142
143
144
145
146
–
183
184
185
186
187
188*
H3
H1
G1
G2
G3
–
–
–
35
–
45
–
C12
–
161
–
I/O
–
–
–
–
–
–
–
88
89*
89*
901
–
114
T13
274
–
I/O (A8)
I/O (A9)
I/O
44
47
50
53
–
–
–
115* R12*
115* R12*
116* T12*
117*
118*
I/O
28
29
30
31
36
37
38
39
46
47
48
49
B13
B14
A15
C13
164
167
170
–
–
–
SGCK2 (I/O)
O (M1)
GND
–
–
I/O
–
–
–
–
–
–
–
–
GND
I/O
–
–
5
6
–
–
–
189*
190
191
192
193
–
–
I (M0)
32
–
40
–
50
A16
–
173†
–
–
91
92
93
94
95
119
120
121
122
123
P11
R11
T11
T10
P10
–
I/O (A10)
I/O (A11)
I/O
147
148
149
150
F1
F2
E1
E2
56
59
62
65
–
51*
52*
53*
54*
55
56
57
58
59
–
–
–
–
–
277
280
283
286
–
–
–
–
I/O
–
–
–
–
–
I/O (D5)
I/O (CS0)
59
60
I/O
–
VCC
–
–
–
GND
–
–
–
–
–
7
151
–
194
195*
196*
F3
–
–
–
33
34
35
36
–
41
42
43
44
45
–
C14
B15
B16
D14
C15
–
–
174†
175
178
181
–
–
–
–
–
–
124*
125*
126
–
–
–
–
I (M2)
PGCK2 (I/O)
I/O (HDC)
I/O
–
–
–
–
–
–
I/O
–
96
97
98
99
R10
T9
R9
P9
289
292
295
298
–
–
152* 197*
153* 198*
D1*
D2*
E3
–
I/O
–
127
–
I/O (D4)
I/O
61
62
128
I/O (A12)
154
199
68
–
–
129
VCC
I/O (A13)
8
155
200
C1
71
I/O
–
46
47
60
D15
184
63
100
130
R8
–
GND
I/O (D3)
I/O (RS)
I/O
–
–
–
–
–
–
–
I/O
–
37
–
61
62
E14
C16
E15*
D16*
–
187
190
–
64
65
66
–
101
102
103
104
105
131
132
133
134
135
P8
T8
T7
T6
R7
–
I/O
156
157
158
159
201
202
203
204
C2
D3
B1
B2
74
77
80
83
I/O (LDC)
48
301
304
307
310
I/O
–
–
–
–
49*
50*
–
63*
64*
65*
I/O (A14)
9
–
–
SGCK1 (A15, I/O)
10
–
–
I/O
–
VCC
–
–
11
–
160
–
205
206*
207*
208*
1*
C3
–
–
–
–
–
–
–
–
GND
I/O
–
–
–
66*
67
68
69
70
71
–
–
–
–
–
–
136*
137*
138
–
–
51
52
53
54
55
F14
F15
E16
F16
G14
–
–
–
–
–
–
–
–
–
193
196
199
202
I/O (D2)
67
68
–
106
107
108
109
P7
T5
R6
T4
313
316
319
322
–
–
–
–
I/O
–
I/O
139
–
–
–
–
I/O
38
39
I/O
140
GND
12
1
2
C4
I/O
I/O
–
141
GND
–
–
13
14
–
–
2
3
4
5
–
3*
4
–
–
–
–
–
–
72*
73*
74
–
–
–
–
110
–
142
143*
144*
P6
–
–
–
PGCK1 (A16, I/O)
B3
A1
A2
C5
–
86
89
92
95
–
–
–
–
–
–
I/O (A17)
5
I/O
–
56
57
58
59
G15
G16
H16
H15
205
208
211
214
–
–
–
–
–
I/O
I/O
–
6
I/O
I/O
–
75
–
–
–
111* 145*
112* 146*
R5*
–
–
–
7
40
41
76
–
–
–
–
I/O (ERR, INIT)
VCC
77
I/O (D1)
69
113
147
T3
325
I/O (TDI)
15
6
8
B4
98
42
60
78
H14
–
I/(ORCLK-BUSY/RDY)
70
114
148
P5
328
GND
I/O
I/O (TCK)
16
–
7
8*
9*
–
9
A3
A4*
–
101
–
43
44
45
–
61
62
63
64
65
79
80
81
82
83
J14
J15
J16
K16
K15
–
I/O
–
–
115
–
149
–
R4
–
331
–
–
–
10*
11*
12*
13*
217
220
223
226
–
–
–
I/O
I/O
–
116
117
118
150
151
152
R3
P4
T2
334
337
340
–
–
–
–
I/O
I/O (D0, DIN)
SGCK4 (DOUT, I/O)
71
72
–
–
–
–
–
I/O
–
GND
–
10
14
C6
–
–
–
–
84*
–
–
CCLK
73
119
153
R2
–
VCC
I/O
–
–
11
12
13
14
–
15
16
B5
B6
A5
C7
–
104
107
110
113
–
–
I/O
–
46
47
–
–
85*
86
87
88
89
–
–
74
–
120
–
154
P3
–
–
–
–
–
–
I/O
I/O (TMS)
I/O
66
67
68
69
K14
L16
M16
L15
229
232
235
238
–
–
–
–
155*
156*
157*
158*
17
18
–
17
I/O
–
–
–
18
I/O
–
–
–
–
19*
I/O
–
–
–
–
GND
–
–
–
20*
–
–
–
70
90
L14
–
O (TDO)
75
121
159
T1
–
GND
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
–
–
–
15
16
17
18
19
20
21
22
23
24
–
21
22
23
24
25
26
27
28
29
30
31*
32*
B7
A6
A7
A8
C8
B8
C9
B9
A9
B10
–
116
119
122
125
–
–
–
–
–
–
91*
92*
93*
94*
95
–
–
–
76
77
78
–
122
123
124
125
–
160
161
162
163
–
N3
R1
P2
N2
–
–
2
–
–
I/O (A0,WS)
19
20
21
22
23
24
–
–
–
71*
72*
73
74
75
76
77
78
79
–
N16*
M15*
P16
M14
N15
P15
N14
R16
P14
–
–
PGCK4 (A1,I/O)
5
–
–
–
I/O
8
I/O
48
49
–
241
244
247
250
253
256
–
–
–
–
–
I/O
96
I/O
–
126
127
128
164
165
166
M3
P1
N1
M2*
M1*
–
11
14
17
–
128
131
134
137
–
I/O
97
I/O (CS1,A2)
79
80
–
I/O
–
98
I/O (A3)
I/O
SGCK3 (I/O)
GND
50
51
52
–
99
–
–
129* 167*
130* 168*
–
100
101
102*
–
–
–
–
–
–
169*
170*
–
–
–
–
–
–
–
–
–
–
–
–
–
GND
I/O
I/O
I/O
I/O
I/O
25
26
–
25
26
27
33
34
35
C10
A10
A11
140
143
146
DONE
53
–
80
–
103
R15
–
–
–
–
–
–
–
131
132
133
171
172
173
L3
L2
L1
–
–
104*
105*
20
23
–
–
–
–
VCC
I/O
GND
–
–
–
28
29
–
36
37
B11
C11
–
149
–
54
–
81
–
106
107*
108
109
110
111
–
P13
–
–
–
I/O (A4)
I/O (A5)
–
81
82
–
134
135
–
174
175
K3
K2
–
26
29
–
–
PROG
I/O (D7)
PGCK3 (I/O)
I/O
–
38*
39*
40*
41*
42
–
55
56
57
–
82
83
84
85
–
R14
T16
T15
R13
–
–
176*
–
–
–
–
–
259
262
265
–
–
–
136* 177*
–
–
–
–
30*
31*
32
33
A12*
–
–
I/O
–
137
138
139
140
178
179
180
181
K1
J1
J2
J3
32
35
38
41
–
–
–
I/O
–
I/O
I/O
27
–
B12
A13
152
155
–
–
I/O (A6)
I/O (A7)
GND
83
84
43
I/O
–
86
112
P12
268
I/O
–
34
44
A14
158
I/O (D6)
58
87
113
T14
271
1
141
182
H2
–
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 343 = BSCANT.UPD
2-57
XC4000 Logic Cell Array Family
XC4006 Pinouts
PQ
PQ
Pin
Description
PC
84
PG
156
PQ
208
Boundary
Pin
Description
PC
84
PG
156
PQ
160
Boundary
160
208
Scan Order
Scan Order
V C C
I/O (A8)
I/O (A9)
I/O
I/O
-
-
I/O (A10)
I/O (A11)
I/O
I/O
GND
-
2
3
4
-
-
-
H3
H1
G1
G2
G3
-
142
143
144
145
146
-
183
184
185
186
187
188*
189*
190
191
192
193
194
195*
196*
197
198
199
200
201
202
203
204
205
206*
207*
208*
1*
2
3*
4
5
6
7
8
9
10
11
12*
13*
14
15
16
17
18
-
50
53
56
59
-
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/O
GND
-
-
23
24
-
-
-
C9
B9
A9
B10
-
-
C10
A10
A11
B11
C11
-
21
22
23
24
-
27
28
29
30
31*
32*
33
34
35
36
37
38*
39*
40
41
42
43
44
45
46
47
48
49
50
51*
52*
53*
54*
55
56
57
58
59
60
61
62
63
64
65*
66*
67
68
69
70
71
72*
73*
74
75
76
77
78
146
149
152
155
-
-
-
-
-
-
-
-
25
26
-
-
-
-
-
-
-
25
26
27
28
29
-
158
161
164
167
-
5
6
-
-
-
-
-
-
-
F1
F2
E1
E2
F3
-
147
148
149
150
151
-
62
65
68
71
-
-
-
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
A12
-
30
31
32
33
34
35
36
37
38
39
40
-
170
173
176
179
182
185
188
191
194
-
197†
-
-
-
-
I/O
I/O
I/O (A12)
I/O (A13)
D1
D2
E3
C1
C2
D3
B1
B2
C3
-
152
153
154
155
156
157
158
159
160
-
-
-
-
1
-
2
3
4
5
6
7
8
9
-
-
10
11
12
13
14
-
74
77
80
83
86
89
92
95
-
-
-
-
-
27
-
-
B12
A13
A14
C12
B13
B14
A15
C13
A16
-
7
8
-
I/O
I/O
I/O
I/O
-
-
28
29
30
31
32
-
-
-
-
33
34
35
36
-
-
-
37
-
-
I/O (A14)
SGCK1 (A15, I/O)
9
10
11
-
-
-
-
12
-
13
14
-
SGCK2 (I/O)
O
M
(M
GND
I ( 0)
1
1)
V C C
-
-
-
M
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
-
PGCK1 (A16, I/O)
C4
-
-
-
V C C
C14
B15
B16
D14
C15
D15
E14
C16
E15
D16
-
41
42
43
44
45
46
47
48
49
50
-
-
I (M2)
B3
A1
A2
C5
B4
A3
A4
-
98
101
104
107
110
113
116
119
-
2
198†
199
202
205
208
211
214
217
220
-
I/O (A17)
PGCK2 (I/O)
I/O (HDC)
I/O
I/O
I/O (TDI)
I/O (TCK)
-
I/O
I/O
I/O
15
16
-
-
-
-
-
-
-
17
18
-
-
-
I/O
I/O
-
-
I/O (LDC)
I/O
I/O
-
-
GND
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
-
-
-
-
-
-
-
-
GND
I/O
I/O
I/O (TMS)
I/O
C6
B5
B6
A5
C7
-
-
-
-
-
122
125
128
131
-
F14
F15
E16
F16
G14
-
51
52
53
54
55
-
223
226
229
232
-
-
38
39
-
-
-
-
-
19*
20*
21
22
23
24
25
26
-
-
-
I/O
I/O
I/O
I/O
GND
V C C
B7
A6
A7
A8
C8
B8
15
16
17
18
19
20
134
137
140
143
-
-
-
-
-
G15
G16
H16
H15
H14
56
57
58
59
60
235
238
241
244
-
19
20
21
22
-
40
41
42
I/O (ERR,INIT)
V C C
-
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
2-58
XC4006 Pinouts (continued)
PQ1
60
PG
PQ
160
PC
84
PG
156
PQ
208
Boundary
Pin
Description
PC
84
PQ
208
Boundary
Pin
Description
156
Scan Order
Scan Order
GND
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/O
GND
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
43
44
45
-
-
-
J14
J15
J16
K16
K15
-
61
62
63
64
65
-
79
80
81
82
83
84*
85*
86
87
88
89
90
91*
92*
93
94
95
96
97
-
247
250
253
256
-
GND
I/O (D3)
I/O (RS)
I/O
I/O
-
-
I/O (D2)
I/O
I/O
I/O
GND
-
-
64
65
66
-
-
-
P8
T8
T7
T6
R7
-
101
102
103
104
105
-
131
132
133
134
135
136*
137*
138
139
140
141
142
143*
144*
145
146
147
148
149
150
151
152
153
154
155*
156*
157*
158*
159
160
161
162
163
164
165
166
167
168
169*
170*
171
172
173
174
175
176*
177*
178
179
180
181
182
-
343
346
349
352
-
-
-
-
-
-
-
-
-
46
47
-
-
-
-
-
-
-
K14
L16
M16
L15
L14
-
66
67
68
69
70
-
259
262
265
268
-
67
68
-
-
-
-
-
-
-
P7
T5
R6
T4
P6
-
-
R5
-
T3
P5
R4
R3
P4
T2
R2
P3
-
106
107
108
109
110
-
355
358
361
364
-
-
-
-
-
-
-
-
N16
M15
P16
M14
N15
P15
N14
R16
P14
-
R15
-
-
P13
-
R14
T16
T15
R13
P12
T14
T13
R12
T12
-
71
72
73
74
75
76
77
78
79
-
80
-
-
81
-
82
83
84
85
86
87
88
89
90
-
271
274
277
280
283
286
289
292
-
-
-
-
-
I/O
I/O
I/O (D1)
111
112
113
114
115
116
117
118
119
120
-
367
370
373
376
379
382
385
388
-
-
-
-
-
-
-
-
2
5
8
48
49
-
69
70
-
I/O (RCLK-BUSY/RDY)
I/O
I/O
-
98
99
-
50
51
52
-
53
-
-
54
-
55
56
57
-
-
58
-
-
-
-
-
-
-
-
I/O (D0, DIN)
SGCK4 (DOUT, I/O)
71
72
73
74
-
-
-
-
75
76
77
78
-
SGCK3 (I/O)
100
101
102*
103
104*
105*
106
107*
108
109
110
111
112
113
114
115
116
117*
118*
119
120
121
122
123
124*
125*
126
127
128
129
130
GND
-
DONE
CCLK
V C C
-
-
-
-
-
-
-
-
-
-
-
-
V C C
-
PROG
I/O (D7)
-
-
-
TDO
GND
I/O (A0, WS)
PGCK4 (I/O, A1)
T1
N3
R1
P2
N2
M3
P1
N1
M2
M1
-
121
122
123
124
125
126
127
128
129
130
-
295
298
301
304
307
310
313
316
-
PGCK3 (I/O)
I/O
I/O
I/O (D6)
I/O
I/O
I/O
I/O
I/O
-
11
14
17
20
23
-
I/O (CS1,A2)
I/O (A3)
I/O
79
80
-
-
-
-
-
-
-
81
82
-
-
-
I/O
-
-
GND
I/O
I/O
I/O (A4)
I/O (A5)
-
-
-
-
-
-
-
-
-
-
-
GND
I/O
I/O
I/O (D5)
I/O (CS0)
-
P11
R11
T11
T10
P10
-
91
92
93
94
95
-
L3
L2
L1
K3
K2
-
131
132
133
134
135
-
136*
137
138
139
140
141
319
322
325
328
-
26
29
32
35
-
59
60
-
-
-
-
-
-
-
-
-
-
I/O
I/O
I/O (D4)
I/O
V C C
R10
T9
R9
P9
R8
96
97
98
99
100
331
334
337
340
-
I/O
I/O
I/O (A6)
I/O (A7)
GND
K1
J1
J2
J3
H2
38
41
44
47
-
-
-
61
62
63
83
84
1
* Indicates unconnected package pins.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 391 = BSCAN.UPD
2-59
XC4000 Logic Cell Array Family
XC4008 Pinouts
Pin
Description
V C C
I/O (A8)
I/O (A9)
I/O
I/O
I/O
I/O
I/O (A10)
I/O (A11)
I/O
I/O
GND
–
Boundary
84160Scan Order
Pin
Description
Boundary
PG
191
PQ
208
PC
PQ
PQ
PC
PQ
PG
208Scan Order
84
22
23
24
–
–
–
–
25
26
–
–
–
–
–
–
–
160
20
21
22
23
24
–
191
D10
C10
B10
A9
2
3
4
–
–
–
–
5
6
–
–
–
–
–
–
–
7
142
143
144
145
146
–
J4
J3
J2
J1
H1
H2
H3
G1
G2
F1
E1
G3
F2*
D1*
C1
E2
F3
D2
B1
–
183
184
185
186
187
188
189
190
191
192
193
194
195*
196*
197
198
199
200
201
–
–
56
59
62
65
68
71
74
77
80
83
–
V C C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
–
–
I/O
I/O
I/O
I/O
26
27
28
29
30
31
32
33
34
35
36
37
38*
39*
40
41
42
43
44
45
46
47
48
49
50
51*
52*
53*
54*
55
56
57
58
–
–
164
167
170
173
176
179
182
185
188
191
–
A10
A11
C11
B11
A12
B12
A13
C12
B13*
A14*
A15
C13
B14
A16
B15
C14
A17
B16
C15
D15
A18
–
–
–
147
148
149
150
151
–
25
26
27
28
29
–
–
–
–
–
–
I/O
I/O
–
–
152
153
154
155
156
–
86
89
92
95
98
–
30
31
32
33
34
35
36
37
38
39
40
–
–
–
–
41
42
43
44
–
194
197
200
203
206
209
212
215
218
–
221†
–
–
–
–
I/O (A12)
I/O (A13)
27
–
–
8
–
–
I/O
–
I/O
I/O
I/O
I/O
–
–
9
10
11
–
–
–
–
157
158
159
160
–
–
–
–
E3
C2
B2
D3
–
–
–
–
202
203
204
205
206*
207*
208*
1*
101
104
107
–
–
–
28
29
30
31
32
–
–
–
–
33
34
35
36
–
I/O (A14)
SGCK1 (A15, I/O)
SGCK2 (I/O)
O (M1)
V C C
–
–
–
GND
I (M0)
–
–
–
–
–
–
–
–
D16
C16
B17
E16
–
–
GND
–
PGCK1 (A16, I/O)
12
–
1
–
D4
–
2
3*
–
–
–
V C C
–
13
14
–
2
3
4
–
C3
C4
B3
–
4
5
6
–
110
113
116
–
222†
223
226
–
I (M2)
I/O (A17)
I/O
PGCK2 (I/O)
I/O (HDC)
–
–
–
I/O
–
5
6
7
8
9
–
–
10
11
12
13
14
–
C5
A2
B4
C6
A3
B5*
B6*
C7
A4
A5
B7
A6
C8
A7
B8
A8
B9
C9
D9
7
8
9
10
119
122
125
128
131
–
I/O
I/O
I/O
–
–
–
37
–
–
–
–
–
–
–
38
39
–
–
–
–
45
46
47
48
49
50
–
C17
D17
B18
E17
F16
C18
D18*
F17*
G16
E18
F18
G17
G18
H16
H17
H18
J18
J17
J16
J15
59
60
61
62
63
64
65*
66*
67
68
69
70
71
72
73
74
75
76
77
78
229
232
235
238
241
244
–
I/O (TDI)
I/O (TCK)
I/O
15
16
–
–
–
–
–
–
–
17
18
–
–
–
I/O (LDC)
I/O
–
–
11
I/O
I/O
–
–
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
12*
13*
14
15
16
17
18
19
20
21
22
23
24
–
–
GND
I/O
I/O
I/O (TMS)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
–
–
–
134
137
140
143
146
149
152
155
158
161
–
51
52
53
54
55
–
247
250
253
256
259
262
265
268
271
274
–
–
15
16
17
18
19
–
–
56
57
58
59
60
19
20
21
I/O
40
41
42
25
I/O (ERR, INIT)
V C C
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
2-60
XC4008 Pinouts (continued)
Pin
Description
Boundary
84160191208Scan Order
Pin
Description
I/O (D3)
I/O (RS)
I/O
I/O
I/O
I/O
I/O (D2)
I/O
Boundary
84160191208Scan Order
PC
PQ
PG
PQ
PC
PQ
PG
PQ
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
–
–
I/O
I/O
43
44
45
–
–
–
61
62
63
64
65
–
K15
K16
K17
K18
L18
L17
L16
M18
M17
N18
P18
M16
N17*
R18*
T18
P17
N16
T17
R17
P16
U18
T16
R16
–
79
80
81
82
83
84
85
86
87
88
89
90
91*
92*
93
94
95
–
277
280
283
286
289
292
295
298
301
304
–
65
66
–
–
–
102
103
104
105
–
T9
U9
V9
V8
U8
T8
V7
U7
V6
U6
T7
V5*
V4*
U5
T6
V3
V2
U4
T5
U3
T4
V1
R4
–
132
133
134
135
136
137
138
139
140
141
142
143*
144*
145
146
147
148
149
150
151
152
153
154
155*
156*
157*
158*
159
160
161
162
–
385
388
391
394
397
400
403
406
409
412
–
–
–
–
–
67
68
–
–
–
–
–
–
–
106
107
108
109
110
–
46
47
–
–
–
–
–
–
–
66
67
68
69
70
–
I/O
I/O
GND
–
–
–
–
–
–
–
–
I/O
I/O
111
112
113
114
115
116
117
118
119
120
–
–
–
–
121
122
123
124
–
415
418
421
424
427
430
433
436
–
–
–
–
–
–
–
–
2
5
–
71
72
73
74
75
76
77
78
79
–
80
–
–
81
–
82
83
84
–
307
310
313
316
319
322
325
328
–
–
–
–
–
–
–
–
331
334
–
I/O (D1)
I/O (RCLK-BUSY/RDY) 70
69
I/O
I/O
I/O
I/O
48
49
–
96
97
98
99
I/O
I/O
–
–
–
I/O (D0, DIN)
SGCK4 (DOUT, I/O)
71
72
73
74
–
–
–
–
75
76
77
78
–
I/O
50
51
52
–
53
–
–
54
–
55
56
57
–
SGCK3 (I/O)
100
101
102*
103
104*
105*
106
107*
108
109
110
–
CCLK
V C C
–
–
–
–
GND
–
DONE
–
U17
–
–
R15
–
V18
T15
U16
–
–
–
–
U2
R3
T3
U1
–
–
V C C
–
PROG
I/O (D7)
PGCK3 (I/O)
–
I/O
I/O
I/O (D6)
I/O
I/O
TD0
GND
I/O (A0, WS)
PGCK4 (I/O,A1)
–
I/O
I/O
–
–
79
80
–
–
–
–
–
–
–
81
82
–
–
–
–
125
126
127
128
129
130
–
P3
R2
T2
N3
P2
T1
R1*
N2*
M3
P1
N1
M2
M1
L3
L2
L1
K1
K2
K3
K4
163
164
165
166
167
168
169*
170*
171
172
173
174
175
176
177
178
179
180
181
182
8
–
–
58
–
–
–
–
–
–
–
–
59
60
–
–
–
–
85
86
87
88
89
90
–
T14
U15
V17
V16
T13
U14
V15*
V14*
T12
U13
V13
U12
V12
T11
U11
V11
V10
U10
T10
R10
R9
111
112
113
114
115
116
117*
118*
119
120
121
122
123
124
125
126
127
128
129
130
131
337
340
343
346
349
352
–
11
14
17
20
23
–
I/O (CS1, A2)
I/O (A3)
I/O
I/O
–
–
GND
I/O
I/O
I/O (A4)
I/O (A5)
I/O
I/O
I/O
I/O
I/O (A6)
I/O (A7)
GND
I/O
–
–
–
–
–
–
–
–
131
132
133
134
135
–
136
137
138
139
140
141
GND
I/O
I/O
I/O (D5)
I/O (CSO)
I/O
I/O
I/O
I/O
I/O (D4)
I/O
91
92
93
94
95
–
26
29
32
35
38
41
44
47
50
53
–
355
358
361
364
367
370
373
376
379
382
–
96
97
98
99
100
101
83
84
1
61
62
63
64
V C C
GND
* Indicates unconnected package pins.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 439 = BSCAN.UPD
2-61
XC4000 Logic Cell Array Family
XC4010/XC4010D Pinouts
Pin
Description
***
Boundary
Pin
Description
***
Boundary
††
PC84 PQ160 PG191 PQ208 BG225 Scan Order
PC84 PQ160 PG191 PQ208 BG225 Scan Order
V C C
2
3
4
-
142
143
144
145
146
-
J4
J3
J2
J1
H1
H2
H3
G1
G2
F1
E1
G3
F2
D1
C1
E2
F3
D2
B1
E3
C2
B2
D3
-
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206*
207*
208*
1*
D8
E8
B7
A7
C7
D7
E7
A6
B6
A5
B5
**
-
I/O
I/O
-
-
24
-
A10
A11
C11
B11
A12
B12
A13
C12
B13
A14
A15
C13
B14
A16
B15
C14
A17
B16
C15
D15
A18
-
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51*
52*
53*
54*
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
7 2
7 3
7 4
7 5
7 6
7 7
78
79
80
81
82
83
J1
J3
J4
K2
K3
J6
L1
**
191
194
197
200
203
206
209
-
I/O (A8)
62
I/O (A9)
65
I/O
-
-
I/O
68
I/O
25
26
-
25
26
27
28
29
-
I/O
-
71
I/O
I/O
-
74
I/O
I/O
-
-
77
I/O
-
I/O (A10)
5
6
-
147
148
149
150
151
-
80
GND
I/O
-
I/O (A11)
83
-
L3
M1
K5
M2
L4
N1
M3
N2
K6
P1
N3
**
212
215
218
221
224
227
230
233
236
239
242
-
I/O
86
I/O
-
-
I/O
-
89
I/O
-
30
31
32
33
34
35
36
37
38
39
40
-
GND
-
-
I/O
-
I/O
-
D6
C5
A4
E6
B4
D5
B3
F6
A2
C3
B2
-
92
I/O
27
-
I/O
-
-
96
I/O
I/O
-
152
153
154
155
156
157
158
159
160
-
98
I/O
-
I/O
-
101
104
107
110
113
116
119
-
I/O
-
I/O (A12)
7
8
-
I/O
28
29
30
31
32
-
I/O (A13)
SGCK2 (I/O)
O (M1)
I/O
I/O
-
GND
I (M0)
I/O (A14)
9
10
11
-
P2
-
245†
-
SGCK1 (A15, I/O)
-
V C C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V C C
I (M2)
33
34
35
36
-
41
42
43
44
45
46
47
48
49
50
-
D16
C16
B17
E16
C17
D17
B18
E17
F16
C18
D18
F17
G16
E18
F18
G17
G18
H16
H17
H18
J18
J17
J16
J15
K15
K16
K17
K18
L18
R1
M4
R2
P3
L5
N4
R3
P4
K7
M5
R4
N5
**
-
-
-
-
-
-
-
246†
247
250
253
256
259
262
265
268
271
274
-
GND
12
-
1
D4
-
2
A1
-
-
PGCK2 (I/O)
-
-
3*
-
I/O (HDC)
PGCK1 (A16, I/O)
13
14
-
2
C3
C4
B3
C5
A2
B4
C6
A3
B5
B6
C7
A4
A5
B7
A6
C8
A7
B8
A8
B9
C9
D9
D10
C10
B10
A9
4
D4
B1
C2
E5
D3
C1
D2
G6
E4
D1
**
122
125
128
131
134
137
140
143
146
149
-
I/O
I/O
I/O (A17)
I/O
3
5
-
4
6
I/O
-
I/O
-
5
7
I/O (LDC)
I/O
37
-
I/O (TDI)
I/O (TCK)
I/O
15
16
-
6
8
7
9
I/O
-
8
10
I/O
-
I/O
-
9
11
I/O
-
-
I/O
-
-
12
GND
I/O
-
51
52
53
54
55
-
I/O
-
-
13
-
R5
M6
N6
P6
R6
M7
R7
L7
N8
P8
R8
M8
L8
P9
R9
N9
277
280
283
286
289
291
295
298
301
304
-
GND
I/O
-
10
11
12
13
14
-
14
I/O
-
-
15
F5
E1
F4
F3
G4
G3
G2
G1
G5
H3
H2
H1
H4
H5
J2
152
155
158
161
164
167
170
173
176
179
-
I/O
38
39
-
I/O
-
16
I/O
I/O (TMS)
I/O
17
18
-
17
I/O
18
I/O
-
-
I/O
19
I/O
-
56
57
58
59
60
61
62
63
64
65
I/O
-
-
20
I/O
-
I/O
-
15
16
17
18
19
20
21
22
23
21
I/O
40
41
42
43
44
45
-
I/O
-
22
I/O (ERR, INIT)
V C C
GND
I/O
I/O
19
20
21
22
23
24
-
23
I/O
24
-
GND
V C C
I/O
25
307
310
313
316
26
-
I/O
27
182
185
188
I/O
I/O
28
I/O
-
I/O
29
I/O
I/O
I/O
-
-
46
-
-
66
L17
L16
M18
84
85
86
M9
L9
N10
319
322
325
*
Indicates unconnected package pins.
** The following BGA225 balls are connected to ground:
F8, G7, G8, G9, H6, H7, H8, H9, H10, J7, J8, J9, K8
*** The following BG225 balls are unconnected:
E3, E2, F1, F2, J5, K1, L2, K4, P5, L6, N7, P7, R10, P10, M10,
N11, N15, M14, L15, K12, G10, E15, E14, F12, F9, D11, C10,
B10, C6, F7, A3, C4
† Contributes only one bit (.i) to the boundary scan register.
†† XC4010 only. PG191 package not available for XC4010D
2-62
XC4010/XC4010D Pinouts (continued)
Pin
Description
***
Boundary
Pin
Description
***
Boundary
††
PC84 PQ160 PG191 PQ208 BG225 Scan Order
PC84 PQ160 PG191 PQ208 BG225 Scam Order
I/O
I/O
47
-
67
68
69
70
-
M17
N18
P18
M16
N17
R18
T18
P17
N16
T17
R17
P16
U18
T16
R16
-
87
88
K9
R11
P11
**
328
331
334
-
I/O
-
-
-
V4
U5
T6
V3
V2
U4
T5
U3
T4
V1
R4
-
144
145
146
147
148
149
150
151
152
153
154
155*
156*
157*
158*
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
D15
F11
D14
E12
C15
D13
C14
F10
B15
C13
B14
-
460
463
466
469
472
475
478
481
484
-
I/O
111
112
113
114
115
116
117
118
119
120
-
I/O
-
89
I/O
-
GND
I/O
-
90
I/O (D1)
69
70
-
-
91
R12
L10
P12
M11
R13
N12
P13
K10
R14
N13
**
337
340
343
346
349
352
355
358
361
364
-
I/O (RCLK-BUSY/RDY
I/O
-
-
92
I/O
I/O
-
71
72
73
74
75
76
77
78
79
-
93
I/O
-
I/O
-
94
I/O (D0, DIN)
71
72
73
74
-
I/O
48
49
-
95
SGCK4 (DOUT, I/O)
I/O
96
CCLK
I/O
97
V C C
-
I/O
-
98
-
-
I/O
50
51
52
-
99
-
-
-
-
-
-
SGCK3 (I/O)
GND
-
100
101
102*
103
104*
105*
106
107*
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
-
-
-
-
-
-
-
TD0
-
-
-
-
-
-
-
75
76
77
78
-
121
122
123
124
125
126
127
128
129
130
-
U2
R3
T3
U1
P3
R2
T2
N3
P2
T1
R1
N2
M3
P1
N1
M2
M1
L3
L2
L1
K1
K2
K3
K4
A15
D12
A14
B13
E11
C12
A13
B12
A12
C11
B11
E10
**
-
DONE
-
53
-
80
-
U17
-
P14
-
-
GND
-
-
I/O (A0, WS)
PGCK4 (I/O, A1)
I/O
2
-
-
-
-
-
-
5
V C C
-
54
-
81
-
R15
-
R15
-
-
8
-
I/O
-
11
14
17
20
23
26
29
-
PROG
I/O (D7)
PGCK3 (I/O)
I/O
55
56
57
-
82
83
84
85
86
87
88
89
90
-
V18
T15
U16
T14
U15
V17
V16
T13
U14
V15
V14
T12
U13
V13
U12
V12
T11
U11
V11
V10
U10
T10
R10
R9
M12
P15
N14
L11
M13
J10
L12
M15
L13
L14
K11
**
-
I/O (CS1, A2)
I/O (A3)
I/O
79
80
-
367
370
373
376
379
382
385
388
391
394
-
I/O
-
I/O
-
I/O
-
I/O (D6)
I/O
58
-
I/O
-
-
GND
-
131
132
133
134
135
-
I/O
-
I/O
-
A11
D10
A10
D9
32
35
38
41
44
47
50
53
56
59
-
I/O
-
I/O
-
I/O
-
I/O (A4)
I/O (A5)
I/O
81
82
-
I/O
-
-
GND
I/O
-
91
92
93
94
95
-
C9
-
K13
K14
K15
J12
J13
J14
J15
J11
H13
H14
H15
**
397
400
403
406
409
412
415
418
421
424
-
I/O
-
136
137
138
139
140
141
B9
I/O
-
I/O
-
A9
I/O (D5)
I/O (CSO)
I/O
59
60
-
I/O
-
E9
I/O (A6)
I/O (A7)
GND
83
84
1
C8
B8
I/O
-
-
A8
I/O
-
96
97
98
99
100
101
102
103
104
105
-
I/O
-
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 487 = BSCAN.UPD
I/O (D4)
I/O
61
62
63
64
65
66
-
V C C
GND
I/O (D3)
I/O (RS)
I/O
-
T9
H12
H11
G14
G15
G13
G12
G11
F15
F14
427
430
433
436
439
442
445
448
451
U9
V9
I/O
-
V8
I/O
-
U8
I/O
-
-
T8
I/O (D2)
I/O
67
68
-
106
107
108
V7
U7
I/O
V6
I/O
GND
I/O
-
-
-
109
110
-
U6
T7
V5
141
142
143
F13
**
E13
454
-
457
*
Indicates unconnected package pins.
** The following BGA225 balls are connected to ground:
F8, G7, G8, G9, H6, H7, H8, H9, H10, J7, J8, J9, K8
*** The following BG225 balls are unconnected:
E3, E2, F1, F2, J5, K1, L2, K4, P5, L6, N7, P7, R10, P10, M10,
N11, N15, M14, L15, K12, G10, E15, E14, F12, F9, D11, C10,
B10, C6, F7, A3, C4
†† XC4010 only. PG 191 package not available for XC4010D
2-63
XC4000 Logic Cell Array Family
XC4013/XC4013D Pinouts
Boundary
Boundary
Scan Order
218
Pin
Pin
Scan Order
Description
PQ160 MQ208 PG223 BG225 PQ240
Description
PQ160 MQ208 PG223 BG225 PQ240
V C C
142
143
144
145
146
-
183
184
185
186
187
188
189
-
J4
J3
J2
J1
H1
H2
H3
-
A10
E8
F8
B7
A7
G7
E7
-
212
213
214
215
216
217
218
219*
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
-
-
I/O
21
22
23
24
-
27
28
29
30
31
32
-
C10
B10
A9
H6
H3
J6
H4
J1
J5
-
31
32
33
34
35
36
37*
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
-
74
77
80
83
86
89
221
I/O (A8)
I/O
224
I/O (A9)
I/O
227
I/O
I/O
A10
A11
C11
-
230
I/O
I/O
233
I/O
I/O
-
I/O
-
-
-
-
236
239
-
-
-
92
95
I/O
-
-
D11
D12
-
J2
J7
K1
J3
K2
K5
K3
L1
K6
L2
J4
M2
L5
M1
H3
L3
M4
N1
N2
K4
L4
41
P1
-
I/O (A10)
147
148
-
190
191
-
G1
G2
-
F7
C7
-
I/O
-
-
I/O (A11)
V C C
-
-
-
242
245
248
251
V C C
-
98
I/O
25
26
27
28
29
-
33
34
35
36
37
-
B11
A12
B12
A13
C12
D13
D14
B13
A14
A15
C13
B14
A16
B15
C14
A17
B16
C15
D15
A18
-
I/O
-
-
H4
G4
F1
E1
G3
F2
D1
C1
E2
F3
D2
F4
E4
B1
E3
C2
B2
D3
-
B6
E6
D7
F6
A5
B5
D5
C5
C6
A4
D4
B4
C3
A3
C2
D6
A2
A6
-
I/O
101
104
107
I/O
-
-
I/O
I/O
149
150
151
-
192
193
194
195
196
197
198
199
200
-
I/O
I/O
GND
-
254
257
260
263
266
269
272
275
278
281
284
287
290
GND
-
I/O
110
113
116
119
122
125
128
131
134
137
140
143
I/O
I/O
-
-
I/O
-
I/O
-
38
39
40
41
42
43
44
45
46
47
48
49
50
51*
52*
53*
54*
55
56
57
58
59
60
61
62
63
64
65
66
-
I/O
152
153
154
155
-
I/O
-
I/O
I/O
30
31
32
33
34
35
36
37
38
39
40
-
I/O (A12)
I/O
I/O (A13)
I/O
I/O
I/O
I/O
-
-
I/O
I/O
156
157
158
159
160
-
201
202
203
204
205
206*
207*
208*
1*
I/O
I/O
I/O
I/O (A14)
SGCK2 (I/O)
SGCK1 (A15, I/O)
O (M1)
V C C
-
GND
-
293†
-
-
I (M0)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
1
2
D4
-
A1
-
1
-
-
-
-
-
-
-
-
-
3*
-
-
V C C
41
42
43
44
45
46
47
48
49
50
-
D16
C16
B17
E16
C17
D17
B18
E17
F16
C18
D18
F17
E15
F15
G16
E18
F18
G17
G18
-
R6
R2
P3
M6
P2
R3
N3
N5
N4
R4
P4
N6
P5
M5
R5
M7
P6
L6
N7
-
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83*
84
85
86
87
88
89
90
-
146
149
152
155
158
161
164
167
170
173
176
179
294†
295
298
301
304
307
310
313
316
319
322
325
328
PGCK1 (A16,I/O)
2
4
C3
C4
B3
C5
A2
B4
C6
A3
B5
B6
D5
D6
C7
A4
A5
B7
A6
-
B1
B3
C4
B2
C1
E3
D2
D3
D1
E5
F4
E2
E1
E4
F3
F2
F5
F1
G4
G2
-
2
I (M2)
I/O (A17)
I/O
3
5
3
PGCK2 (I/O)
4
6
4
I/O (HDC)
I/O
5
7
5
I/O
I/O (TDI)
I/O (TCK)
I/O
6
8
6
I/O
7
9
7
I/O
8
10
11
12
13
-
8
I/O (LDC)
I/O
9
9
I/O
I/O
-
10
I/O
I/O
-
11
I/O
I/O
-
12
I/O
-
I/O
-
-
13
I/O
-
GND
I/O
10
11
12
13
14
-
14
15
16
17
18
-
14
-
I/O
-
-
182
185
188
191
15
GND
51
52
53
54
55
-
67
68
69
70
71
-
-
331
334
337
340
I/O
16
I/O
I/O (TMS)
I/O
17
I/O
18
I/O
V C C
I/O
19
-
I/O
194
197
-
-
D7
D8
-
20
V C C
-
343
346
I/O
-
-
21
I/O
-
72
73
-
H16
H17
-
P7
M8
-
-
-
-
22*
23
-
I/O
-
200
203
206
209
212
215
I/O
-
19
20
21
22
23
24
25
26
C8
A7
B8
A8
B9
C9
D9
D10
G3
G6
G5
G1
H5
H7
H1
H2
-
-
-
349
352
355
358
361
364
I/O
-
24
I/O
-
-
G15
H15
H18
J18
J17
J16
J15
K7
L7
R7
N8
J8
P8
R10
I/O
15
16
17
18
19
20
25
I/O
-
-
I/O
26
I/O
I/O
56
57
58
59
60
74
75
76
77
78
I/O
27
I/O
28
I/O
GND
V C C
29
-
-
I/O (ERR, INIT)
V C C
30
-
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
2-64
XC4013/XC4013D Pinouts (continued)
Boundary
Boundary
Pin
Description
GND
I/O
Pin
Description
GND
I/O (D3)
I/O (RS)
I/O
Scan Order
Scan Order
PQ160 MQ208 PG223 BG225 PQ240
PQ160 MQ208 PG223 BG225 PQ240
61
62
63
64
65
-
79
80
K15
K16
K17
K18
L18
L17
L16
-
R8
L8
91
92
-
101
102
103
104
105
-
131
132
133
134
135
136
137
-
R9
T9
U9
V9
V8
U8
T8
-
H15
H10
G12
G14
G15
G9
151
152
153
154
155
156
157
158*
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
-
-
367
370
373
376
379
382
511
514
517
520
523
526
I/O
81
M9
P9
93
I/O
82
94
I/O
83
R9
95
I/O
I/O
84
K8
96
I/O
I/O
-
85
L9
97
I/O
-
G11
-
-
-
-
-
98*
99
-
-
-
-
385
388
529
532
I/O
-
-
L15
M15
-
K9
I/O (D2)
I/O
106
107
-
138
139
-
V7
U7
-
G10
G13
-
I/O
-
-
N9
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
-
V C C
I/O
-
-
-
-
V C C
I/O
-
391
394
397
400
535
538
541
544
66
67
68
69
70
-
86
M18
M17
N18
P18
M16
N15
P15
N17
R18
T18
P17
N16
T17
R17
P16
U18
T16
R16
-
P10
L10
N10
K10
R11
N11
P11
M10
P12
R12
N12
K12
P13
R13
P14
K13
M13
R15
-
108
109
-
140
141
-
V6
U6
R8
R7
T7
R6
R5
V5
V4
U5
T6
V3
V2
U4
T5
U3
T4
V1
R4
-
F14
F11
F13
F10
E15
E14
F12
D14
E12
D15
D13
E13
C13
C15
C14
D10
C11
B15
F15
-
I/O
87
I/O
I/O
88
I/O
I/O
89
I/O
-
-
GND
I/O
90
-
GND
I/O
110
-
142
-
-
403
406
409
412
415
418
421
424
427
430
433
0
547
550
553
556
559
562
565
568
571
574
577
580
-
I/O
-
-
I/O
-
-
I/O
-
91
I/O
-
143
144
145
146
147
148
149
150
151
152
153
154
155*
156*
157*
158*
159
160
161
162
163
164
165
166
-
I/O
-
92
I/O
-
I/O
71
72
73
74
75
76
77
78
79
-
93
I/O
111
112
113
I/O
94
I/O
I/O
95
I/O (D1)
I/O
96
I/O (RCLK-BUSY/RDY) 114
I/O
97
I/O
115
116
117
118
119
120
-
I/O
98
I/O
I/O
99
I/O (D0, DIN)
SGCK3 (I/O)
GND
-
100
101
102*
103
104*
105*
106
107*
108
109
110
111
112
-
SGCK4 (DOUT, I/O)
-
CCLK
-
-
-
V C C
DONE
-
80
-
U17
-
R14
-
120
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V C C
-
81
-
R15
-
K15
-
121
-
-
-
-
-
-
-
-
-
TD0
121
122
123
124
125
126
127
128
-
U2
R3
T3
U1
P3
R2
T2
N3
P4
N4
P2
T1
R1
N2
-
A14
A15
C12
C10
B14
A13
B13
B12
D12
A12
E11
D9
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195*
196
197
198
199
200
201
202
203
204*
205
206
207
208
209
210
211
-
PROG
I/O (D7)
PGCK3 (I/O)
I/O
82
83
84
85
86
-
V18
T15
U16
T14
U15
R14
R13
V17
V16
T13
U14
V15
V14
T12
R12
R11
U13
V13
-
P15
N14
L13
N13
N15
M11
M14
M12
M15
L11
J12
L14
L12
L15
J13
K14
K11
H11
-
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143*
144
145
146
147
148
149
150
-
GND
-
2
439
442
445
448
451
454
457
460
463
466
469
472
I/O (A0, WS)
5
PGCK4 (I/O, A1)
8
I/O
I/O
11
14
17
20
23
26
29
32
35
I/O
I/O
I/O (CS1, A2)
I/O (A3)
I/O
I/O
-
-
I/O (D6)
I/O
87
88
89
90
-
113
114
115
116
117
118
119
-
I/O
-
-
I/O
I/O
129
130
-
167
168
169
170
-
I/O
I/O
I/O
I/O
B11
D11
-
I/O
-
I/O
-
GND
I/O
91
-
-
-
-
-
475
478
481
484
GND
I/O
131
132
133
-
171
172
173
-
M3
P1
N1
M4
L4
-
A11
C9
-
38
41
44
47
I/O
-
-
I/O
92
93
-
120
121
-
I/O
B10
E10
D8
I/O
I/O
V C C
I/O (D5)
I/O (CSO)
-
-
I/O
-
-
487
490
94
95
-
122
123
-
U12
V12
-
J14
H12
-
V C C
I/O (A4)
I/O (A5)
-
-
-
-
-
50
53
134
135
-
174
175
-
M2
M1
-
B9
-
C8
493
496
499
502
505
508
I/O
-
124
125
126
127
128
129
130
T11
U11
V11
V10
U10
T10
R10
J10
J11
J15
H13
J9
-
-
56
59
62
65
68
71
I/O
-
I/O
-
176
177
178
179
180
181
182
L3
L2
L1
K1
K2
K3
K4
F9
I/O
96
97
98
99
100
I/O
136
137
138
139
140
141
E9
I/O
I/O
A9
I/O (D4)
I/O
I/O
B8
H9
I/O (A6)
I/O (A7)
GND
H8
V C C
H14
-
G8
A8
-
*
Indicates unconnected package pins.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 583 = BSCAN.UPD
2-65
XC4000 Logic Cell Array Family
XC4020 Pinouts
Pin
Description
VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O
I/O
I/O (A10)
I/O (A11)
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O (A12)
I/O (A13)
I/O
I/O
I/O
I/O
I/O
I/O
I/O (A14)
Bound
HQ208 HQ240 PG233 PG299 Scan
Pin
Description
I/O
I/O
I/O
GND
I/O
I/O
Bound
HQ208 HQ240 PG233 PG299 Scan
Pin
Description
I/O
Bound
HQ208 HQ240 PG233 PG299 Scan
183
184
185
186
187
188
189
190
191
-
212
213
214
215
216
217
218
220
221
-
J4
J3
J2
J1
H1
H2
H3
G1
G2
-
K1
K2
K3
K5
K4
J1
J2
H1
J3
H2
G1
E1
H3
G2
H4
F2
-
86
89
92
95
98
34
35
36
37
-
42
43
44
45
46
47
48
49
50
51
-
A12
B12
A13
C12
D13
D14
B13
A14
A15
C13
-
C13
B14
D13
A15
C14
A17
D14
B16
C15
E14
A18
D15
C16
B17
B18
E15
D16
C17
A20
A19
C18
B20
D17
B19
C19
F16
E17
D18
C20
F17
G16
D19
E18
D20
G17
F18
H16
E20
H17
G18
G19
H18
F20
J16
287
290
293
-
-
-
95
96
97
98
99
100
101
103
106
108
109
110
111
112
-
-
-
-
-
R17
T18
U19
V19
R16
T17
U18
X20
W20
V18
X19
U17
W19
W18
T15
U16
V17
X18
U15
T14
W17
V16
X17
U14
V15
T13
X16
U13
V14
W14
V13
X15
T12
X14
X13
V12
W12
T11
X12
U11
V11
W11
X10
X11
W10
V10
T10
U10
X9
W9
X8
V9
W8
X7
X5
V8
W7
U8
W6
X6
X4
U7
W5
V6
T7
X3
U6
V5
W4
W3
T6
487
490
493
496
499
502
505
508
-
I/O
I/O
I/O
I/O
I/O
I/O
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
-
N16
T17
R17
P16
U18
T16
R16
U17
R15
V18
T15
U16
T14
U15
R14
R13
-
296
299
302
305
308
311
314
317
320
323
326
329
332
335
338
-
-
101
104
107
110
113
-
116
119
122
125
-
128
131
134
137
140
143
146
149
152
155
158
161
164
167
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
38
39
40
41
-
SGCK3 (I/O)
GND
DONE
VCC
PROG
I/O (D7)
PGCK3 (I/O)
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D6)
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O (D5)
I/O (CS0)
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D2)
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
-
-
-
-
-
-
-
222
223
224
225
226
227
228
229
230
231
232
233
-
-
-
-
H4
G4
F1
E1
G3
F2
D1
C1
E2
F3
D2
-
42
43
44
45
46
47
48
49
50
55
56
57
58
59
60
61
62
-
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
-
B14
A16
B15
C14
A17
B16
C15
D15
A18
D16
C16
B17
E16
C17
D17
B18
E17
-
511
514
517
520
523
526
529
532
535
538
541
544
547
550
-
553
556
559
562
-
565
568
571
574
577
580
583
586
589
592
-
192
193
194
195
196
197
198
199
200
-
I/O
I/O
I/O
F1
D1
G4
E2
F3
G5
C1
F4
E3
D2
C2
F5
E4
D3
C3
SCGK2 (I/O)
O (M1)
GND
I (M0)
VCC
I (M2)
PGCK2 (I/O)
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
-
-
-
-
-
341
-
113
114
115
116
117
118
119
-
129
130
131
132
133
134
135
136
137
138
139
140
141
142
-
V17
V16
T13
U14
V15
V14
T12
R12
R11
U13
V13
-
342
343
346
349
352
355
358
361
364
367
370
373
376
379
382
-
385
388
391
394
-
397
400
403
406
409
412
415
418
421
424
-
-
-
-
-
-
234
235
236
237
238
239
240
1
2
3
4
5
F4
E4
B1
E3
C2
B2
D3
D4
C3
C4
B3
C5
A2
B4
-
201
202
203
204
205
2
4
5
6
7
-
120
121
-
122
123
-
SGCK1(A15,I/O)
-
-
-
VCC
GND
PGCK1 (A16,I/O)
A2
B1
D4
B2
B3
E6
D5
C4
A3
D6
E7
B4
C5
A4
D7
C6
A5
B6
D8
C7
B7
A6
C8
E9
B8
A8
C9
B9
E10
A9
D10
C10
A10
A11
B10
B11
C11
E11
D11
A12
B12
A13
E12
B13
A16
A14
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
63
64
65
66
-
69
70
71
72
73
74
75
76
77
78
79
80
81
82
-
F16
C18
D18
F17
E15
F15
G16
E18
F18
G17
G18
-
-
U12
V12
-
170
173
176
179
182
185
188
191
194
197
200
203
206
209
-
I/O (A17)
I/O
I/O
I/O (TDI)
I/O (TCK)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O (TMS)
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
-
124
125
126
127
128
129
130
131
132
133
134
135
136
137
-
144
145
146
147
148
149
150
151
152
153
154
155
156
157
-
T11
U11
V11
V10
U10
T10
R10
R9
T9
U9
V9
V8
U8
T8
8
9
-
6
7
-
67
68
69
70
71
-
72
73
-
-
-
-
10
11
12
13
-
8
9
C6
A3
B5
B6
D5
D6
C7
A4
A5
B7
A6
-
10
11
12
13
14
15
16
17
18
19
20
21
-
H16
H17
-
-
G20
H20
J18
J19
K16
J20
595
598
601
604
607
610
613
616
619
622
-
625
628
631
634
-
637
640
643
646
-
649
652
655
658
661
664
667
670
673
-
-
-
-
-
-
-
14
15
16
17
18
-
-
-
-
84
85
86
87
88
89
90
91
92
93
94
95
96
97
-
G15
H15
H18
J18
J17
J16
J15
K15
K16
K17
K18
L18
L17
L16
-
212
215
218
221
-
I/O
I/O
I/O
74
75
76
77
78
79
80
81
82
83
84
85
-
K17
K18
K19
L20
K20
L19
L18
L16
L17
M20
M19
N20
M18
N19
P20
T20
N18
P19
N17
R19
R20
U20
P17
T19
R18
P16
V20
-
-
-
-
I/O (ERR, INIT)
VCC
GND
I/O
138
139
-
140
141
-
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
-
V7
U7
-
V6
U6
R8
R7
T7
R6
R5
V5
V4
U5
T6
V3
V2
-
-
U4
T5
U3
T4
V1
R4
U2
D7
D8
-
224
227
230
233
236
239
242
245
248
251
-
-
427
430
433
436
439
442
445
448
451
454
-
457
460
463
466
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
19
20
21
22
23
24
25
26
27
28
29
30
31
32
-
23
24
25
26
27
28
29
30
31
32
33
34
35
36
-
C8
A7
B8
A8
B9
C9
D9
D10
C10
B10
A9
A10
A11
C11
-
-
142
-
-
143
144
145
146
147
148
-
-
-
-
-
86
87
88
89
90
-
-
-
99
100
101
102
103
104
105
106
107
108
109
110
111
112
L15
M15
-
-
254
257
260
263
266
269
272
275
278
281
-
M18
M17
N18
P18
M16
N15
P15
N17
R18
T18
P17
I/O (D1)
I/O (RCLK-BUSY/RDY)
I/O
I/O
I/O
-
-
149
150
151
175
176
177
178
179
180
181
469
472
475
478
481
484
I/O
U5
V4
X1
V3
W1
U4
I/O
I/O
I/O
VCC
I/O
-
-
-
-
-
-
-
I/O (D0, DIN)
SGCK4 (DOUT, I/O) 152
38
39
40
41
D11
D12
-
91
92
93
94
I/O
I/O
I/O
CCLK
VCC
TDO
153
154
159
-
-
33
B11
284
† Contributes only one bit (.i) to the boundary scan register.
2-66
XC4020 Pinouts (continued)
Pin
Description
GND
I/O (A0, WS)
PGCK4 (I/O, A1) 162
Bound
Pin
Description
I/O
I/O
I/O
I/O
GND
I/O
Bound
Pin
Description
I/O
I/O (A4)
I/O (A5)
I/O
I/O
I/O
I/O
I/O (A6)
I/O (A7)
GND
Bound
HQ208 HQ240 PG233 PG299 Scan
HQ208 HQ240 PG233 PG299 Scan
HQ208 HQ240 PG233 PG299 Scan
160
161
182
183
184
185
186
187
188
-
R3
T3
U1
P3
R2
T2
N3
-
X2
W2
V2
R5
T4
U3
V1
R4
P5
U2
T3
-
2
5
8
11
14
17
20
23
26
29
167
168
169
170
171
172
173
-
191
192
193
194
196
197
198
199
200
201
-
P2
T1
R1
N2
M3
P1
N1
M4
L4
-
U1
P4
R3
N5
T1
N4
P3
P2
N3
R1
M5
32
35
38
41
-
44
47
50
53
-
-
-
-
P1
N1
M3
M2
L5
M1
L4
L3
59
62
65
68
71
74
77
80
83
-
174
175
176
177
178
179
180
181
182
202
203
205
206
207
208
209
210
211
M2
M1
L3
L2
L1
K1
K2
K3
K4
I/O
163
164
165
166
-
-
-
-
I/O
I/O (CS1, A2)
I/O (A3)
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
-
-
P4
N4
-
-
-
L2
L1
189
190
-
56
XC4025 Pinouts
Pin
Description
VCC
I/O (A8)
I/O (A9)
I/O
PG MQ PG HQ Bound
223 240 299 304 Scan Description 223 240 299 304 Scan
Pin
PG MQ PG HQ Bound
Pin
Description
I/O
I/O
I/O (LDC)
I/O
PG MQ PG HQ Bound
223 240 299 304 Scan Description 223 240 299 304 Scan
D17 6 6 E17 2 2 3 4 0 0
B18 6 7 D18 2 2 2 4 0 3
E17 6 8 C20 2 2 1 4 0 6
Pin
PG MQ PG HQ Bound
J 4 2 1 2 K1 3 8
J 3 2 1 3 K2 3 7
-
VCC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I / O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
1 9 A6
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P17 1 1 2 V20 1 6 3 5 5 6
9 8
D7 2 0 C8 2 8 0 2 5 4
D8 2 1 E9 2 7 9 2 5 7
-
-
R17 1 6 2 5 5 9
T18 1 6 1 5 6 2
J 2 2 1 4 K3 3 6 1 0 1
J 1 2 1 5 K5 3 5 1 0 4
H1 2 1 6 K4 3 4 1 0 7
H2 2 1 7 J 1 3 3 1 1 0
H3 2 1 8 J 2 3 2 1 1 3
-
-
-
-
-
-
-
2 2
-
-
-
-
-
-
-
F17 2 2 0 4 0 9
G16 2 1 9 4 1 2
N16 1 1 3 U19 1 6 0 5 6 5
T17 1 1 4 V19 1 5 9 5 6 8
R17 1 1 5 R16 1 5 8 5 7 1
P16 1 1 6 T17 1 5 7 5 7 4
U18 1 1 7 U18 1 5 6 5 7 7
I/O
I/O
I/O
-
-
-
-
A7 2 7 8 2 6 0
D9 2 7 7 2 6 3
B8 2 7 6 2 6 6
A8 2 7 5 2 6 9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I / O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
F16 6 9 D19 2 1 8 4 1 5
C18 7 0 E18 2 1 7 4 1 8
D18 7 1 D20 2 1 6 4 2 1
F17 7 2 G17 2 1 5 4 2 4 SGCK3 (I/O) T16 1 1 8 X20 1 5 5 5 8 0
E15 7 3 F18 2 1 4 4 2 7
F15 7 4 H16 2 1 3 4 3 0
GND
I/O (A10)
I/O (A11)
I/O
I / O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
-
2 1 9
-
-
-
G1 2 2 0 H1 3 1 1 1 6
G2 2 2 1 J 3 3 0 1 1 9
C8 2 3 C9 2 7 4 2 7 2
A7 2 4 B9 2 7 3 2 7 5
B8 2 5 E10 2 7 2 2 7 8
A8 2 6 A9 2 7 1 2 8 1
B9 2 7 D10 2 7 0 2 8 4
C9 2 8 C10 2 6 9 2 8 7
VCC
GND
DONE
VCC
PROG
R16
-
-
T16 1 5 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J 4 2 9 1 2 2
J 5 2 8 1 2 5
H2 2 7 1 2 8
G1 2 6 1 3 1
1 1 9 W20
-
-
-
-
-
E 1 9 2 1 2 4 3 3
F19 2 1 1 4 3 6
U 1 7 1 2 0 V 1 8 1 5 3
R15 1 2 1 X19 1 5 2
V 1 8 1 2 2 U 1 7 1 5 1
G16 7 5 E 2 0 2 1 0
-
2 2 2 E1 2 5
-
D9 2 9 A10 2 6 8
D10 3 0 A11 2 6 7
-
-
E18 7 6 H17 2 0 9 4 3 9
F18 7 7 G18 2 0 8 4 4 2 PGCK3 (I/O) U16 1 2 4 W18 1 4 9 5 8 6
G17 7 8 G19 2 0 7 4 4 5
G18 7 9 H18 2 0 6 4 4 8
I/O (D7)
T15 1 2 3 W19 1 5 0 5 8 3
H4 2 2 3 H3 2 3 1 3 4
G4 2 2 4 G2 2 2 1 3 7
F1 2 2 5 H4 2 1 1 4 0
E1 2 2 6 F2 2 0 1 4 3
C10 3 1 B10 2 6 6 2 9 0
B10 3 2 B11 2 6 5 2 9 3
A9 3 3 C11 2 6 4 2 9 6
A10 3 4 E11 2 6 3 2 9 9
A11 3 5 D11 2 6 2 3 0 2
C11 3 6 A12 2 6 1 3 0 5
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D6)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O (D5)
I/O (CS0)
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
T14 1 2 5 T15 1 4 8 5 8 9
U15 1 2 6 U16 1 4 7 5 9 2
R14 1 2 7 V17 1 4 6 5 9 5
R13 1 2 8 X18 1 4 5 5 9 8
-
8 0 F20 2 0 4
-
G3 2 2 7 F1 1 9
-
H16 8 1 J16 2 0 3 4 5 1
H17 8 2 G20 2 0 2 4 5 4
-
-
-
-
H5 1 8 1 4 6
G3 1 7 1 4 9
-
-
-
-
U15 1 4 4 6 0 1
T14 1 4 3 6 0 4
-
-
-
-
-
8 3
-
-
-
F2 2 2 8 D1 1 6 1 5 2
D1 2 2 9 G4 1 5 1 5 5
C1 2 3 0 E2 1 4 1 5 8
E2 2 3 1 F3 1 3 1 6 1
F3 2 3 2 G5 1 2 1 6 4
D2 2 3 3 C1 1 0 1 6 7
-
-
-
-
-
-
-
-
B12 2 6 0 3 0 8
A13 2 5 9 3 1 1
C12 2 5 8 3 1 4
D12 2 5 7 3 1 7
-
-
-
-
J17 2 0 1 4 5 7
H19 2 0 0 4 6 0
H20 1 9 9 4 6 3
J18 1 9 8 4 6 6
V17 1 2 9 W17 1 4 2 6 0 7
V16 1 3 0 V16 1 4 1 6 1 0
T13 1 3 1 X17 1 4 0 6 1 3
U14 1 3 2 U14 1 3 9 6 1 6
V15 1 3 3 V15 1 3 8 6 1 9
V14 1 3 4 T13 1 3 7 6 2 2
I/O
I/O
I/O (A12)
I/O (A13)
I/O
-
3 7
-
-
-
G15 8 4 J19 1 9 7 4 6 9
H15 8 5 K16 1 9 6 4 7 2
H18 8 6 J20 1 9 5 4 7 5
J18 8 7 K17 1 9 4 4 7 8
J17 8 8 K18 1 9 3 4 8 1
D11 3 8 E12 2 5 6 3 2 0
D12 3 9 B13 2 5 5 3 2 3
-
-
-
-
F4
E3
9
8
7
6
5
4
3
2
1
1 7 0
1 7 3
1 7 6
1 7 9
1 8 2
1 8 5
1 8 8
1 9 1
-
-
-
-
-
W16 1 3 6 6 2 5
W15 1 3 5 6 2 8
I/O
I/O
I/O
I/O
-
4 0 A16
-
-
F4 2 3 4 D2
E4 2 3 5 C2
B1 2 3 6 F5
E3 2 3 7 E4
C2 2 3 8 D3
B11 4 1 A14 2 5 2 3 2 6
A12 4 2 C13 2 5 1 3 2 9 I/O (ERR, INIT) J16 8 9 K19 1 9 2 4 8 4
B12 4 3 B14 2 5 0 3 3 2
A13 4 4 D13 2 4 9 3 3 5
T12 1 3 5 X16 1 3 4
-
R12 1 3 6 U13 1 3 3 6 3 1
R11 1 3 7 V14 1 3 2 6 3 4
U13 1 3 8 W14 1 3 1 6 3 7
V13 1 3 9 V13 1 3 0 6 4 0
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
J15 9 0 L20 1 9 1
K15 9 1 K20 1 9 0
-
-
I/O
I/O (A14)
SGCK1 (A15, I/O) B2 2 3 9 C3
C12 4 5 A15 2 4 8
-
K16 9 2 L19 1 8 9 4 8 7
K17 9 3 L18 1 8 8 4 9 0
K18 9 4 L16 1 8 8 4 9 3
L18 9 5 L17 1 8 7 4 9 6
L17 9 6 M20 1 8 5 4 9 9
L16 9 7 M19 1 8 4 5 0 2
-
-
-
-
B15 2 4 7 3 3 8
E13 2 4 6 3 4 1
-
1 4 0 X15
-
-
VCC
GND
D3 2 4 0 A2
U12 1 4 1 T12 1 2 7 6 4 3
V12 1 4 2 X14 1 2 6 6 4 6
D4
1
2
-
B1 3 0 4
-
D13 4 6 C14 2 4 5 3 4 4
D14 4 7 A17 2 4 4 3 4 7
B13 4 8 D14 2 4 3 3 5 0
A14 4 9 B16 2 4 2 3 5 3
A15 5 0 C15 2 4 1 3 5 6
C13 5 1 E14 2 4 0 3 5 9
PGCK1 (A16, I/O) C3
D4 3 0 3 1 9 4
E5
-
-
1 4 3
-
-
-
VCC
I/O (A17)
I/O
-
-
-
-
-
-
-
U12 1 2 5 6 4 9
W13 1 2 4 6 5 2
X13 1 2 3 6 5 5
V12 1 2 2 6 5 8
C4
B3
C5
A2
B4
-
-
C6
A3
3
4
5
6
7
-
-
8
9
B2 3 0 2 1 9 7
B3 3 0 1 2 0 0
E6 3 0 0 2 0 3
D5 2 9 9 2 0 6
C4 2 9 8 2 0 9
A3 2 9 7 2 1 2
D6 2 9 6 2 1 5
E7 2 9 5 2 1 8
B4 2 9 4 2 2 1
-
-
-
-
-
-
-
-
N20 1 8 3 5 0 5
M18 1 8 2 5 0 8
M17 1 8 1 5 1 1
M16 1 8 0 5 1 4
-
-
-
I/O
I/O (TDI)
I/O (TCK)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O (TMS)
I/O
-
-
-
-
A18 2 3 9 3 6 2
D15 2 3 8 3 6 5
T11 1 4 4 W12 1 2 1 6 6 1
U11 1 4 5 T11 1 2 0 6 6 4
V11 1 4 6 X12 1 1 9 6 6 7
V10 1 4 7 U11 1 1 8 6 7 0
U10 1 4 8 V11 1 1 7 6 7 3
T10 1 4 9 W11 1 1 6 6 7 6
L15 9 8
-
1 7 9
-
B14 5 2 C16 2 3 7 3 6 8
A16 5 3 B17 2 3 6 3 7 1
B15 5 4 B18 2 3 5 3 7 4
C14 5 5 E15 2 3 4 3 7 7
A17 5 6 D16 2 3 3 3 8 0
M15 9 9 N19 1 7 8 5 1 7
-
-
1 0 0
1 0 1 T20 1 7 7
-
-
5 2 0
-
M18 1 0 2 N18 1 7 5 5 2 3
M17 1 0 3 P19 1 7 4 5 2 6
N18 1 0 4 N17 1 7 3 5 2 9
P18 1 0 5 R19 1 7 2 5 3 2
B5 1 0 C5 2 9 3 2 2 4
B6 1 1 A4 2 9 2 2 2 7 SCGK2 (I/O) B16 5 7 C17 2 3 2 3 8 3
D5 1 2 D7 2 9 1 2 3 0
D6 1 3 C6 2 9 0 2 3 3
R10 1 5 0 X10 1 1 5
R9 1 5 1 X11 1 1 4
-
-
O
(M1)
GND
(M0)
VCC
(M2)
C15 5 8 A20 2 3 1 3 8 6
D15 5 9 A19 2 3 0
A18 6 0 C18 2 2 9 389†
D16 6 1 B20 2 2 8
C16 6 2 D17 2 2 7 390†
T9 1 5 2 W10 1 1 3 6 7 9
U9 1 5 3 V10 1 1 2 6 8 2
V9 1 5 4 T10 1 1 1 6 8 5
V8 1 5 5 U10 1 1 0 6 8 8
U8 1 5 6 X9 1 0 9 6 9 1
T8 1 5 7 W9 1 0 8 6 9 4
-
M16 1 0 6 R20 1 7 1
-
-
-
-
-
E8 2 8 9 2 3 6
B5 2 8 8 2 3 9
I
I
-
-
-
-
N16 1 7 0 5 3 5
P18 1 6 9 5 3 8
-
I/O
I/O
I/O
I/O
I/O
I/O
C7 1 4 A5 2 8 7
-
N15 1 0 7 U20 1 6 8 5 4 1
P15 1 0 8 P17 1 6 7 5 4 4
N17 1 0 9 T19 1 6 6 5 4 7
R18 1 1 0 R18 1 6 5 5 5 0
T18 1 1 1 P16 1 6 4 5 5 3
A4 1 5 B6 2 8 6 2 4 2 PGCK2 (I/O) B17 6 3 B19 2 2 6 3 9 1
A5 1 6 D8 2 8 5 2 4 5
B7 1 7 C7 2 8 4 2 4 8
A6 1 8 B7 2 8 3 2 5 1
I/O (HDC) E16 6 4 C19 2 2 5 3 9 4
GND
I/O
-
-
-
-
-
-
X8 1 0 7 6 9 7
V9 1 0 6 7 0 0
U9 1 0 5 7 0 3
-
-
E16
-
-
C17 6 5 F16 2 2 4 3 9 7
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 775 = BSCAN.UPD
2-67
XC4000 Logic Cell Array Family
XC4025 Pinouts (continued)
Pin
PG MQ PG HQ Bound
Pin
Description
I/O
PG
MQ
PG
HQ Bound
Pin
Description
PG
MQ
PG
HQ
Bound
Scan
1 1
1 4
1 7
2 0
2 3
2 6
2 9
3 2
3 5
3 8
4 1
4 4
4 7
-
Pin
Description
I/O
VCC
I/O
I/O
I/O
I/O
I/O (A4)
I/O (A5)
GND
I / O
I/O
PG
MQ
PG
HQ Bound
Description 223 240 299 304 Scan
I/O
GND
223 240 299 304 Scan
T6
V3
223 240 299 304
223 240 299 304 Scan
L4
-
-
-
T9 1 0 4 7 0 6
1 7 2
1 7 3 U6
1 7 4
-
X3
8 7
8 6
8 5
7 4 5
7 4 8
7 5 1
7 5 4
7 5 7
7 6 0
7 6 3
7 6 6
7 6 9
-
I/O
R2
T2
N3
-
1 8 6
1 8 7 U3
1 8 8
-
-
1 8 9 U2
1 9 0 T3
1 9 1 U1
1 9 2 P4
1 9 3 R3
1 9 4 N5
T4
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
2 0 0 N3
2 0 1 R1
-
-
-
-
5 4
5 2
5 9
-
1 5 8
-
-
-
I/O (D1)
I/O (CS1, A2)
I/O (A3)
I/O
-
-
-
-
-
I/O (D2) V7 1 5 9 W8 1 0 3 7 0 9 I/O (RCLK-BUSY/RDY) V2
V5
V1
R4
P5
M5
5 1
6 2
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
U7 1 6 0 X7 1 0 2 7 1 2
1 6 1 X5
I/O
I/O
I/O
-
-
W4
W3
T6
8 4
8 3
8 2
8 1
8 0
7 9
7 8
-
P1
M4
N2
5 0
4 9
4 8
4 7
4 6
-
6 5
6 8
7 1
7 4
7 7
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I / O
I/O
I/O
I/O
GND
I/O
I/O
I/O
-
V6 1 6 2 V8 9 9 7 1 5
U6 1 6 3 W7 9 8 7 1 8
R8 1 6 4 U8 9 7 7 2 1
R7 1 6 5 W6 9 6 7 2 4
U4
T5
U3
T4
V1
-
R4
U2
R3
T3
U1
P3
1 7 5
1 7 6 U5
P4
N4
P2
T1
R1
N2
-
I/O
I/O (D0, DIN)
SGCK4 (DOUT, I/O)
CCLK
M2 2 0 2 N1
M3 2 0 3 M3
-
L 3
L2
L1
K1
K2
K3
K4
1 7 7
1 7 8
1 7 9
-
1 8 0 W1
1 8 1 U4
1 8 2
1 8 3 W2
1 8 4 V2
1 8 5 R5
V4
X1
V3
T5
2 0 4
2 0 5 M 2
2 0 6 L5
2 0 7 M1
2 0 8
2 0 9
2 1 0
2 1 1
-
T 7 1 6 6 X6 9 5
-
4 5
4 4
4 3
4 2
4 1
4 0
3 9
8 0
8 3
8 6
8 9
9 2
9 5
-
-
-
-
-
T8 9 4 7 2 7
V7 9 3 7 3 0
GND
VCC
TDO
GND
-
7 7
7 6
7 5
7 4
7 3
7 2
-
1 9 5
-
T2
R2
T1
I/O
I/O
I/O (A6)
I/O (A7)
GND
R6 1 6 7 X4 9 2 7 3 3
R5 1 6 8 U7 9 1 7 3 6
V5 1 6 9 W5 9 0 7 3 9
V4 1 7 0 V6 8 9 7 4 2
-
L4
L3
L2
L1
X2
-
M3 1 9 6
P1
N1
I/O (A0, WS)
PGCK4 (I/O, A1)
I/O
2
5
8
1 9 7 N4
1 9 8 P3
5 0
5 3
5 6
U5 1 7 1 T7 8 8
-
M4 1 9 9 P2
For a detailed description of the device architecture, see pages 2-9 through 2-31.
For a detailed description of the configuration modes and their timing, see pages 2-32 through 2-55.
For detailed lists of package pinouts, see pages 2-57 through 2-67.
For package physical dimensions and thermal data, see Section 4.
Ordering Information
Example:
Device Type
Speed Grade
XC4010-5PG191C
Temperature Range
Number of Pins
Package Type
Component Availability
PINS
84
100
120
144
156
160
164
TOP
191
196
TOP
208
223
225
240
299
304
TOP
TYPE
PLAST. PLAST. PLAST. BRAZED CERAM. PLAST. CERAM PLAST. BRAZED CERAM. BRAZED PLAST. METAL CERAM. PLAST. PLAST. METAL CERAM. CERAM.
PLCC PQFP VQFP CQFP PGA TQFP PGA PQFP CQFP PGA CQFP PQFP PQFP PGA BGA PQFP PQFP PGA PGA
CODE
PC84 PQ100 VQ100 CB100 PG120 TQ144 PG156 PQ160 CB164 PG191 CB196 PQ208 MQ208 PG223 BG225 PQ240 MQ240 PG299 HQ304
-6
-5
-4
-10
-6
-5
-4
-6
-5
-4
-6
-5
-4
-10
-6
-5
-4
-6
-5
-4
-6
-5
-4
-6
-5
-4
-6
-5
-4
-6
-5
-4
C I
C
C I
C
C I
C
XC4003
C
C
C
M B
C I M B
C I
M B
M B
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
XC4005
XC4006
XC4008
XC4010
C
C I
C I
C
C I
C I
C I
C
C I
C I
C
C I
C
C I
C I
C
C I
C I
C
C I
C
C I
C I
C
C I
C I
C
C
M B
C I M B
C I
M B
M B
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
C
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
XC4010D
XC4013
XC4013D
XC4020
XC4025
C I
C I
C
C I
C I
C
C I
C I
C
C I (M B)
C I
C I
C
C I
C I
C
C I
C I
C
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
C I
C I
C
(C I)
(C I)
(C)
(C I)
(C I)
(C)
(C I)
(C I)
(C)
(C I)
(C I)
(C)
C I
C I
C I
C I
C
C
C I
C I
C = Commercial = 0° to +85° C
I = Industrial = -40° to +100° C
M = Mil Temp = -55° to +125° C
B = MIL-STD-883C Class B
Parentheses indicates future product plans
2-68
相关型号：
XC4005-10CB164B
Field Programmable Gate Array, 196 CLBs, 4000 Gates, CMOS, CQFP164, TOP BRAZED, CERAMIC, QFP-164
XILINX
XC4005-10CB164M
Field Programmable Gate Array, 196 CLBs, 4000 Gates, CMOS, CQFP164, TOP BRAZED, CERAMIC, QFP-164
XILINX
XC4005-10PG156B
Field Programmable Gate Array, 196 CLBs, 4000 Gates, CMOS, CPGA156, CERAMIC, PGA-156
XILINX
XC4005-10PG156M
Field Programmable Gate Array, 196 CLBs, 4000 Gates, CMOS, CPGA156, CERAMIC, PGA-156
XILINX
XC4005-4PC84C
Field Programmable Gate Array, 196 CLBs, 4000 Gates, 133.3MHz, 196-Cell, CMOS, PQCC84, PLASTIC, LCC-84
XILINX
XC4005-4PG156C
Field Programmable Gate Array, 196 CLBs, 4000 Gates, 133.3MHz, 196-Cell, CMOS, CPGA156, CERAMIC, PGA-156
XILINX
XC4005-4PQ160C
Field Programmable Gate Array, 196 CLBs, 4000 Gates, 133.3MHz, 196-Cell, CMOS, PQFP160, PLASTIC, QFP-160
XILINX
XC4005-5PC84C
Field Programmable Gate Array, 196 CLBs, 4000 Gates, 133.3MHz, 196-Cell, CMOS, PQCC84, PLASTIC, LCC-84
XILINX
XC4005-5PG156B
Field Programmable Gate Array, 196 CLBs, 3000 Gates, CPGA156, CERAMIC, PGA-156
XILINX
XC4005-5PG156C
Field Programmable Gate Array, 196 CLBs, 4000 Gates, 133.3MHz, 196-Cell, CMOS, CPGA156, CERAMIC, PGA-156
XILINX
XC4005-5PG156I
Field Programmable Gate Array, 196 CLBs, 4000 Gates, 133.3MHz, 196-Cell, CMOS, CPGA156, CERAMIC, PGA-156
XILINX
©2020 ICPDF网 联系我们和版权申明