XC7A200T-2FBG484C [XILINX]
Field Programmable Gate Array, 16825 CLBs, 1286MHz, 215360-Cell, CMOS, PBGA484, FBGA-484;
| 型号： | XC7A200T-2FBG484C |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 16825 CLBs, 1286MHz, 215360-Cell, CMOS, PBGA484, FBGA-484 时钟 栅 可编程逻辑 |
| 文件： | 总64页 (文件大小：1094K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Artix-7 FPGAs Data Sheet:
DC and AC Switching Characteristics
DS181 (v1.25) June 18, 2018
Product Specification
Introduction
Artix®-7 FPGAs are available in -3, -2, -1, -1LI, and -2L
speed grades, with -3 having the highest performance. The
Artix-7 FPGAs predominantly operate at a 1.0V core voltage.
The -1LI and -2L devices are screened for lower maximum
static power and can operate at lower core voltages for
lower dynamic power than the -1 and -2 devices,
speed grade military device are the same as for a -1C speed
grade commercial device). However, only selected speed
grades and/or devices are available in each temperature
range. For example, -1M is only available in the
defense-grade Artix-7Q family and -1Q is only available in
XA Artix-7 FPGAs.
respectively. The -1LI devices operate only at
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The parameters
included are common to popular designs and typical
applications.
V
= V
= 0.95V and have the same speed
CCINT
CCBRAM
specifications as the -1 speed grade. The -2L devices can
operate at either of two V voltages, 0.9V and 1.0V and
CCINT
are screened for lower maximum static power. When
operated at V = 1.0V, the speed specification of a -2L
Available device and package combinations can be found in
:
CCINT
device is the same as the -2 speed grade. When operated at
= 0.9V, the -2L static and dynamic power is reduced.
•
•
•
7 Series FPGAs Overview (DS180)
V
CCINT
Defense-Grade 7 Series FPGAs Overview (DS185)
XA Artix-7 FPGAs Overview (DS197)
Artix-7 FPGA DC and AC characteristics are specified in
commercial, extended, industrial, expanded (-1Q), and
military (-1M) temperature ranges. Except the operating
temperature range or unless otherwise noted, all the DC
and AC electrical parameters are the same for a particular
speed grade (that is, the timing characteristics of a -1M
This Artix-7 FPGA data sheet, part of an overall set of
documentation on the 7 series FPGAs, is available on the
Xilinx website at www.xilinx.com/documentation.
DC Characteristics
Table 1: Absolute Maximum Ratings
(1)
Symbol
FPGA Logic
VCCINT
Description
Min
Max
Units
Internal supply voltage
–0.5
–0.5
–0.5
–0.5
–0.5
–0.4
–0.4
1.1
2.0
V
V
V
V
V
V
V
Auxiliary supply voltage
VCCAUX
Supply voltage for the block RAM memories
Output drivers supply voltage for HR I/O banks
Input reference voltage
1.1
VCCBRAM
VCCO
3.6
2.0
VREF
I/O input voltage
VCCO + 0.55
2.625
(2)(3)(4)
VIN
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards
except TMDS_33(5)
Key memory battery backup supply
–0.5
2.0
V
VCCBATT
GTP Transceiver
VMGTAVCC
VMGTAVTT
VMGTREFCLK
VIN
Analog supply voltage for the GTP transmitter and receiver circuits
Analog supply voltage for the GTP transmitter and receiver termination circuits
Reference clock absolute input voltage
–0.5
–0.5
–0.5
–0.5
1.1
V
V
V
V
1.32
1.32
1.26
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
© 2011– 2018 Xilinx, Inc. XILINX, the Xilinx logo, Artix, Virtex, Kintex, Zynq, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the
United States and other countries. All other trademarks are the property of their respective owners.
DS181 (v1.25) June 18, 2018
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Product Specification
1
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
(1)
Table 1: Absolute Maximum Ratings (Cont’d)
Symbol
IDCIN-FLOAT
IDCIN-MGTAVTT
IDCIN-GND
Description
Min
–
Max
14
Units
mA
DC input current for receiver input pins DC coupled RX termination = floating
DC input current for receiver input pins DC coupled RX termination = VMGTAVTT
DC input current for receiver input pins DC coupled RX termination = GND
DC output current for transmitter pins DC coupled RX termination = floating
DC output current for transmitter pins DC coupled RX termination = VMGTAVTT
–
12
mA
–
6.5
14
mA
–
IDCOUT-FLOAT
IDCOUT-MGTAVTT
XADC
mA
–
12
mA
XADC supply relative to GNDADC
–0.5
–0.5
2.0
2.0
V
V
VCCADC
XADC reference input relative to GNDADC
VREFP
Temperature
TSTG
Storage temperature (ambient)
–65
–
150
°C
°C
°C
°C
Maximum soldering temperature for Pb/Sn component bodies(6)
Maximum soldering temperature for Pb-free component bodies(6)
Maximum junction temperature(6)
+220
+260
+125
TSOL
–
–
Tj
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. The lower absolute voltage specification always applies.
3. For I/O operation, refer to 7 Series FPGAs SelectIO Resources User Guide (UG471).
4. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4.
5. See Table 9 for TMDS_33 specifications.
6. For soldering guidelines and thermal considerations, see 7 Series FPGA Packaging and Pinout Specification (UG475).
(1)(2)
Table 2: Recommended Operating Conditions
Symbol
Description
Min
Typ
Max
Units
FPGA Logic
For -3, -2, -2LE (1.0V), -1, -1Q, -1M devices: internal supply voltage
For -1LI (0.95V) devices: internal supply voltage
For -2LE (0.9V) devices: internal supply voltage
Auxiliary supply voltage
0.95
0.92
0.87
1.71
0.95
1.00
0.95
0.90
1.80
1.00
1.05
0.98
0.93
1.89
1.05
V
V
V
V
V
(3)
VCCINT
VCCAUX
For -3, -2, -2LE (1.0V), -2LE (0.9V), -1, -1Q, -1M devices: block RAM supply
voltage
(3)
VCCBRAM
For -1LI (0.95V) devices: block RAM supply voltage
Supply voltage for HR I/O banks
I/O input voltage
0.92
1.14
0.95
0.98
3.465
V
V
V
V
(4)(5)
VCCO
–
–
–
–0.20
–0.20
VCCO + 0.20
2.625
(6)
VIN
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards
except TMDS_33(7)
Maximum current through any pin in a powered or unpowered bank when
forward biasing the clamp diode.
–
–
–
10
mA
V
(8)
IIN
(9)
VCCBATT
Battery voltage
1.0
1.89
GTP Transceiver
(10)
VMGTAVCC
Analog supply voltage for the GTP transmitter and receiver circuits
0.97
1.17
1.0
1.2
1.03
1.23
V
V
(10)
VMGTAVTT
Analog supply voltage for the GTP transmitter and receiver termination circuits
XADC
VCCADC
XADC supply relative to GNDADC
1.71
1.80
1.89
V
DS181 (v1.25) June 18, 2018
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Product Specification
2
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
(1)(2)
Table 2: Recommended Operating Conditions
Symbol Description
VREFP Externally supplied reference voltage
(Cont’d)
Min
Typ
Max
Units
1.20
1.25
1.30
V
Temperature
Junction temperature operating range for commercial (C) temperature devices
Junction temperature operating range for extended (E) temperature devices
Junction temperature operating range for industrial (I) temperature devices
Junction temperature operating range for expanded (Q) temperature devices
Junction temperature operating range for military (M) temperature devices
0
–
–
–
–
–
85
°C
°C
°C
°C
°C
0
100
100
125
125
Tj
–40
–40
–55
Notes:
1. All voltages are relative to ground.
2. For the design of the power distribution system consult 7 Series FPGAs PCB Design and Pin Planning Guide (UG483).
3. If V and V are operating at the same voltage, V and V should be connected to the same supply.
CCINT
CCBRAM
CCINT
CCBRAM
4. Configuration data is retained even if V
drops to 0V.
CCO
5. Includes V
of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, and 3.3V at 5ꢀ.
CCO
6. The lower absolute voltage specification always applies.
7. See Table 9 for TMDS_33 specifications.
8. A total of 200 mA per bank should not be exceeded.
9.
V
is required only when using bitstream encryption. If battery is not used, connect V
to either ground or V
.
CCBATT
CCBATT
CCAUX
10. Each voltage listed requires the filter circuit described in 7 Series FPGAs GTP Transceiver User Guide (UG482).
Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol
VDRINT
Description
Data retention VCCINT voltage (below which configuration data might be lost)
Data retention VCCAUX voltage (below which configuration data might be lost)
VREF leakage current per pin
Min
0.75
1.5
–
Typ(1)
Max
–
Units
V
–
–
VDRI
IREF
IL
–
V
–
15
µA
µA
pF
µA
µA
µA
µA
µA
µA
mA
nA
Ω
Input or output leakage current per pin (sample-tested)
Die input capacitance at the pad
–
–
15
(2)
CIN
–
–
8
Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V
Pad pull-down (when selected) @ VIN = 3.3V
90
68
34
23
12
68
–
–
330
250
220
150
120
330
25
–
IRPU
–
–
–
IRPD
–
ICCADC
Analog supply current, analog circuits in powered up state
Battery supply current
–
(3)
IBATT
–
–
150
55
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_40)
28
40
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_50)
35
44
50
60
65
83
Ω
Ω
(4)
RIN_TERM
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_60)
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Product Specification
3
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 3: DC Characteristics Over Recommended Operating Conditions (Cont’d)
Symbol Description
Min
–
Typ(1)
1.010
2
Max
Units
n
r
Temperature diode ideality factor
Temperature diode series resistance
–
–
–
–
Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. This measurement represents the die capacitance at the pad, not including the package.
3. Maximum value specified for worst case process at 25°C.
4. Termination resistance to a V
/2 level.
CCO
(1)(2)
Table 4: V Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks
IN
AC Voltage Overshoot
% of UI @–55°C to 125°C
AC Voltage Undershoot
% of UI @–55°C to 125°C
–0.40
–0.45
–0.50
–0.55
–0.60
–0.65
–0.70
–0.75
–0.80
–0.85
–0.90
–0.95
100
61.7
25.8
11.0
4.77
2.10
0.94
0.43
0.20
0.09
0.04
0.02
VCCO + 0.55
100
VCCO + 0.60
46.6
21.2
9.75
4.55
2.15
1.02
0.49
0.24
VCCO + 0.65
V
CCO + 0.70
CCO + 0.75
V
VCCO + 0.80
V
CCO + 0.85
CCO + 0.90
V
VCCO + 0.95
Notes:
1. A total of 200 mA per bank should not be exceeded.
2. The peak voltage of the overshoot or undershoot, and the duration above V
in this table.
+ 0.20V or below GND – 0.20V, must not exceed the values
CCO
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Product Specification
4
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Speed Grade
Table 5: Typical Quiescent Supply Current
Symbol
Description
Device
1.0V
0.95V
-1LI
43
0.9V
-2LE
38
Units
-3
48
-2
48
95
48
95
95
155
155
328
48
95
48
95
95
155
155
95
155
328
1
-2LE
48
-1
48
95
48
95
95
155
155
328
48
95
48
95
95
155
155
95
155
328
1
ICCINTQ
Quiescent VCCINT supply current
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
95
95
58
66
48
48
43
38
95
95
58
66
95
95
58
66
155
155
328
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
155
155
328
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
96
108
108
232
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
96
203
N/A
N/A
N/A
N/A
N/A
N/A
N/A
58
96
203
1
ICCOQ
Quiescent VCCO supply current
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
1
1
1
1
1
1
1
4
4
4
4
1
1
4
4
4
5
5
5
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Product Specification
5
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Speed Grade
Table 5: Typical Quiescent Supply Current (Cont’d)
Symbol
Description
Device
1.0V
0.95V
-1LI
13
0.9V
-2LE
13
Units
-3
-2
13
22
13
22
22
36
36
73
13
22
13
22
22
36
36
22
36
73
-2LE
13
-1
13
22
13
22
22
36
36
73
13
22
13
22
22
36
36
22
36
73
ICCAUXQ
Quiescent VCCAUX supply current
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
13
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
22
22
19
22
13
13
13
13
22
22
19
22
22
22
19
22
36
36
32
36
36
36
32
36
73
73
65
73
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
19
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
32
65
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Product Specification
6
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Speed Grade
Table 5: Typical Quiescent Supply Current (Cont’d)
Symbol
Description
Device
1.0V
0.95V
-1LI
1
0.9V
-2LE
1
Units
-3
1
-2
1
-2LE
1
-1
1
ICCBRAMQ Quiescent VCCBRAM supply current XC7A12T
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
2
2
2
2
1
2
1
1
1
1
1
1
2
2
2
2
1
2
2
2
2
2
1
2
4
4
4
4
2
4
4
4
4
4
2
4
11
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
11
1
11
11
1
6
11
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
2
2
1
1
2
2
2
2
4
4
4
4
2
2
4
4
2
11
11
6
Notes:
1. Typical values are specified at nominal voltage, 85°C junction temperature (T) with single-ended SelectIO resources.
j
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to estimate static power consumption for
conditions other than those specified.
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Product Specification
7
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Power-On/Off Power Supply Sequencing
The recommended power-on sequence is V
, V
, V
, and V
to achieve minimum current draw and ensure
CCO
CCINT CCBRAM CCAUX
that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If
and V have the same recommended voltage levels then both can be powered by the same supply and ramped
V
CCINT
CCBRAM
simultaneously. If V
and V
have the same recommended voltage levels then both can be powered by the same
CCAUX
CCO
supply and ramped simultaneously.
For V voltages of 3.3V in HR I/O banks and configuration bank 0:
CCO
•
•
The voltage difference between V
and V
must not exceed 2.625V for longer than T
for each
CCO
CCAUX
VCCO2VCCAUX
power-on/off cycle to maintain device reliability levels.
The T time can be allocated in any percentage between the power-on and power-off ramps.
VCCO2VCCAUX
The recommended power-on sequence to achieve minimum current draw for the GTP transceivers is V
, V
,
CCINT MGTAVCC
V
OR V
, V
, V
. Both V
and V
can be ramped simultaneously. The recommended
MGTAVTT
MGTAVCC CCINT MGTAVTT
MGTAVCC
CCINT
power-off sequence is the reverse of the power-on sequence to achieve minimum current draw.
If these recommended sequences are not met, current drawn from V
up and power-down.
can be higher than specifications during power-
MGTAVTT
•
When V
is powered before V
and V
– V
MGTAVCC
MGTAVCC
> 150 mV and V
< 0.7V, the V
MGTAVTT
MGTAVCC
MGTAVTT
MGTAVCC
MGTAVCC MGTAVTT
current draw can increase by 460 mA per transceiver during V
ramp up. The duration of the current draw can be
up to 0.3 x T
(ramp time from GND to 90% of V
). The reverse is true for power-down.
MGTAVCC
•
When V
is powered before V
and V
– V
CCINT
> 150 mV and V
< 0.7V, the V
current
MGTAVTT
CCINT
MGTAVTT
CCINT
CCINT
MGTAVTT
draw can increase by 50 mA per transceiver during V
ramp up. The duration of the current draw can be up to
0.3 x T
(ramp time from GND to 90% of V
). The reverse is true for power-down.
VCCINT
CCINT
There is no recommended sequence for supplies not shown.
Table 6 shows the minimum current, in addition to I , that is required by Artix-7 devices for proper power-on and
CCQ
configuration. If the current minimums shown in Table 5 and Table 6 are met, the device powers on after all four supplies
have passed through their power-on reset threshold voltages. The FPGA must not be configured until after V is applied.
CCINT
Once initialized and configured, use the Xilinx Power Estimator (XPE) tools to estimate current drain on these supplies.
Table 6: Power-On Current for Artix-7 Devices
Device
XC7A12T
ICCINTMIN
ICCAUXMIN
ICCOMIN
ICCBRAMMIN
ICCBRAMQ + 60
ICCBRAMQ + 60
ICCBRAMQ + 60
ICCBRAMQ + 60
ICCBRAMQ + 60
ICCBRAMQ + 60
ICCBRAMQ + 60
ICCBRAMQ + 80
ICCBRAMQ + 60
ICCBRAMQ + 60
ICCBRAMQ + 60
ICCBRAMQ + 60
ICCBRAMQ + 60
ICCBRAMQ + 60
ICCBRAMQ + 60
ICCBRAMQ + 60
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ICCINTQ + 120
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 50
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCAUXQ + 40
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
I
CCINTQ + 120
ICCINTQ + 120
CCINTQ + 120
I
ICCINTQ + 120
ICCINTQ + 170
I
CCINTQ + 170
ICCINTQ + 340
ICCINTQ + 120
I
CCINTQ + 120
ICCINTQ + 120
ICCINTQ + 120
ICCINTQ + 120
I
CCINTQ + 170
ICCINTQ + 170
ICCINTQ + 120
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Product Specification
8
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 6: Power-On Current for Artix-7 Devices (Cont’d)
Device
XQ7A100T
XQ7A200T
ICCINTMIN
ICCAUXMIN
ICCAUXQ + 40
ICCAUXQ + 50
ICCOMIN
ICCBRAMMIN
ICCBRAMQ + 60
ICCBRAMQ + 80
Units
mA
ICCINTQ + 170
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
I
CCINTQ + 340
mA
Table 7: Power Supply Ramp Time
Symbol
Description
Conditions
Min
0.2
0.2
0.2
0.2
–
Max
50
Units
ms
TVCCINT
TVCCO
TVCCAUX
TVCCBRAM
Ramp time from GND to 90ꢀ of VCCINT
Ramp time from GND to 90ꢀ of VCCO
Ramp time from GND to 90ꢀ of VCCAUX
Ramp time from GND to 90ꢀ of VCCBRAM
50
ms
50
ms
50
ms
TJ = 125°C(1)
300
500
800
50
TVCCO2VCCAUX
Allowed time per power cycle for VCCO – VCCAUX > 2.625V
TJ = 100°C(1)
TJ = 85°C(1)
–
ms
–
TMGTAVCC
TMGTAVTT
Ramp time from GND to 90ꢀ of VMGTAVCC
Ramp time from GND to 90ꢀ of VMGTAVTT
0.2
0.2
ms
ms
50
Notes:
1. Based on 240,000 power cycles with nominal V
of 3.3V or 36,500 power cycles with worst case V
of 3.465V.
CCO
CCO
DC Input and Output Levels
Values for V and V are recommended input voltages. Values for I and I are guaranteed over the recommended
IL
IH
OL
OH
operating conditions at the V and V test points. Only selected standards are tested. These are chosen to ensure that all
OL
OH
standards meet their specifications. The selected standards are tested at a minimum V
voltage levels shown. Other standards are sample tested.
with the respective V and V
CCO
OL OH
(1)(2)
Table 8: SelectIO DC Input and Output Levels
VIL
V, Max
VIH
VOL
V, Max
0.400
0.400
0.400
0.400
VOH
IOL
IOH
I/O Standard
V, Min
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.400
–0.300
–0.300
–0.300
V, Min
V, Max
V, Min
mA, Max mA, Min
HSTL_I
VREF – 0.100
VREF – 0.100
VREF – 0.100
VREF – 0.100
VREF + 0.100 VCCO + 0.300
VREF + 0.100 VCCO + 0.300
VREF + 0.100 VCCO + 0.300
VREF + 0.100 VCCO + 0.300
VREF + 0.130 VCCO + 0.300
VCCO – 0.400
VCCO – 0.400
VCCO – 0.400
VCCO – 0.400
80ꢀ VCCO
VCCO – 0.400
75ꢀ VCCO
VCCO – 0.450
VCCO – 0.400
VCCO – 0.400
2.400
8.00
8.00
–8.00
–8.00
HSTL_I_18
HSTL_II
16.00
16.00
0.10
–16.00
–16.00
–0.10
HSTL_II_18
HSUL_12
V
REF – 0.130
20ꢀ VCCO
0.400
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
35ꢀ VCCO
35ꢀ VCCO
35ꢀ VCCO
0.7
65ꢀ VCCO
65ꢀ VCCO
65ꢀ VCCO
1.700
VCCO + 0.300
VCCO + 0.300
VCCO + 0.300
VCCO + 0.300
3.450
Note 3
Note 4
Note 5
Note 4
Note 4
Note 5
0.10
Note 3
Note 4
Note 5
Note 4
Note 4
Note 5
–0.10
25ꢀ VCCO
0.450
0.400
0.8
2.000
0.400
0.8
2.000
3.450
0.400
MOBILE_DDR
PCI33_3
20ꢀ VCCO
30ꢀ VCCO
80ꢀ VCCO
50ꢀ VCCO
VCCO + 0.300
VCCO + 0.500
10ꢀ VCCO
10ꢀ VCCO
90ꢀ VCCO
90ꢀ VCCO
1.50
–0.50
SSTL135
V
REF – 0.090
VREF – 0.090
VREF – 0.100
VREF + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 13.00
VREF + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 8.90
VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175 13.00
–13.00
–8.90
SSTL135_R
SSTL15
–13.00
DS181 (v1.25) June 18, 2018
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Product Specification
9
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
(1)(2)
Table 8: SelectIO DC Input and Output Levels
(Cont’d)
VIL
VIH
VOL
VOH
IOL
IOH
I/O Standard
V, Min
–0.300
–0.300
–0.300
V, Max
V, Min
V, Max
V, Max
V, Min
mA, Max mA, Min
SSTL15_R
SSTL18_I
SSTL18_II
VREF – 0.100
VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175
VREF + 0.125 VCCO + 0.300 VCCO/2 – 0.470 VCCO/2 + 0.470
8.90
8.00
–8.90
–8.00
V
REF – 0.125
VREF – 0.125
VREF + 0.125 VCCO + 0.300 VCCO/2 – 0.600 VCCO/2 + 0.600 13.40
–13.40
Notes:
1. Tested according to relevant specifications.
2. 3.3V and 2.5V standards are only supported in HR I/O banks.
3. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks.
4. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks.
5. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks.
6. For detailed interface specific DC voltage levels, see 7 Series FPGAs SelectIO Resources User Guide (UG471).
Table 9: Differential SelectIO DC Input and Output Levels
(1)
(2)
(3)
(4)
VICM
V, Min V, Typ V, Max V, Min V, Typ V, Max
0.300 1.200 1.425 0.100
VID
VOCM
VOD
I/O Standard
V, Min
–
V, Typ
1.250
1.200
0.950
1.200
V, Max
–
V, Min V, Typ V, Max
Note 5
BLVDS_25
–
–
MINI_LVDS_25 0.300 1.200 VCCAUX 0.200 0.400 0.600
1.000
0.500
1.000
1.400
1.400
1.400
0.300 0.450 0.600
0.100 0.250 0.400
0.100 0.350 0.600
PPDS_25
RSDS_25
TMDS_33
0.200 0.900 VCCAUX 0.100 0.250 0.400
0.300 0.900
2.700 2.965
1.500
3.230
0.100 0.350 0.600
0.150 0.675 1.200
V
CCO–0.405 VCCO–0.300 VCCO–0.190 0.400 0.600 0.800
Notes:
1.
2.
3.
4.
5.
V
V
V
V
V
is the input common mode voltage.
is the input differential voltage (Q – Q).
ICM
ID
is the output common mode voltage.
OCM
is the output differential voltage (Q – Q).
for BLVDS will vary significantly depending on topology and loading.
OD
OD
Table 10: Complementary Differential SelectIO DC Input and Output Levels
(1)
(2)
(3)
(4)
VICM
V, Min V,Typ V, Max V,Min V, Max
VID
VOL
VOH
IOL
mA, Max
8.00
IOH
mA, Min
–8.00
–8.00
–16.00
–16.00
–0.100
–0.100
–13.0
–8.9
I/O Standard
V, Max
0.400
V, Min
DIFF_HSTL_I
0.300 0.750 1.125 0.100
0.300 0.900 1.425 0.100
0.300 0.750 1.125 0.100
0.300 0.900 1.425 0.100
0.300 0.600 0.850 0.100
–
–
–
–
–
–
–
–
–
–
–
VCCO–0.400
VCCO–0.400
DIFF_HSTL_I_18
DIFF_HSTL_II
0.400
8.00
0.400
V
CCO–0.400
16.00
16.00
0.100
0.100
13.0
DIFF_HSTL_II_18
DIFF_HSUL_12
0.400
VCCO–0.400
80ꢀ VCCO
90ꢀ VCCO
20ꢀ VCCO
10ꢀ VCCO
DIFF_MOBILE_DDR 0.300 0.900 1.425 0.100
DIFF_SSTL135
DIFF_SSTL135_R
DIFF_SSTL15
0.300 0.675 1.000 0.100
0.300 0.675 1.000 0.100
0.300 0.750 1.125 0.100
0.300 0.750 1.125 0.100
0.300 0.900 1.425 0.100
(VCCO/2) – 0.150 (VCCO/2) + 0.150
(VCCO/2) – 0.150 (VCCO/2) + 0.150
(VCCO/2) – 0.175 (VCCO/2) + 0.175
(VCCO/2) – 0.175 (VCCO/2) + 0.175
(VCCO/2) – 0.470 (VCCO/2) + 0.470
8.9
13.0
–13.0
–8.9
DIFF_SSTL15_R
DIFF_SSTL18_I
8.9
8.00
–8.00
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Product Specification
10
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 10: Complementary Differential SelectIO DC Input and Output Levels (Cont’d)
(1)
(2)
(3)
(4)
VICM
V, Min V,Typ V, Max V,Min V, Max
0.300 0.900 1.425 0.100
VID
VOL
V, Max
(VCCO/2) – 0.600 (VCCO/2) + 0.600
VOH
IOL
mA, Max
13.4
IOH
I/O Standard
V, Min
mA, Min
–13.4
DIFF_SSTL18_II
–
Notes:
1.
2.
3.
4.
V
V
V
V
is the input common mode voltage.
is the input differential voltage (Q – Q).
is the single-ended low-output voltage.
ICM
ID
OL
OH
is the single-ended high-output voltage.
LVDS DC Specifications (LVDS_25)
(1)
Table 11: LVDS_25 DC Specifications
Symbol
VCCO
VOH
DC Parameter
Supply Voltage
Conditions
Min
Typ
2.500
–
Max
Units
2.375
–
2.625
1.675
–
V
V
Output High Voltage for Q and Q
Output Low Voltage for Q and Q
RT = 100 Ω across Q and Q signals
RT = 100 Ω across Q and Q signals
RT = 100 Ω across Q and Q signals
VOL
0.700
247
–
V
VODIFF
Differential Output Voltage:
(Q – Q), Q = High
350
600
mV
(Q – Q), Q = High
VOCM
VIDIFF
Output Common-Mode Voltage
RT = 100 Ω across Q and Q signals
1.000
100
1.250
350
1.425
600
V
Differential Input Voltage:
(Q – Q), Q = High
mV
(Q – Q), Q = High
VICM
Input Common-Mode Voltage
0.300
1.200
1.500
V
Notes:
1. Differential inputs for LVDS_25 can be placed in banks with V
levels that are different from the required level for outputs. Consult the
CCO
7 Series FPGAs SelectIO Resources User Guide (UG471) for more information.
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Product Specification
11
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
AC Switching Characteristics
All values represented in this data sheet are based on the speed specifications from the ISE® Design Suite and
Vivado® Design Suite as outlined in Table 12.
Table 12: Artix-7 FPGA Speed Specification Version By Device
Version In:
Typical VCCINT
(Table 2)
1.0V
Device
ISE 14.7 Vivado 2018.2
N/A
N/A
1.22
1.22
XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T
0.95V
XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T, XC7A100T,
XC7A200T
N/A
1.10
1.07
N/A
1.14
1.22
1.14
1.15
1.15
1.11
1.11
0.9V
1.0V
0.9V
1.0V
1.0V
1.0V
1.0V
XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T
XC7A100T, XC7A200T
XC7A100T, XC7A200T
XA7A12T, XA7A15T, XA725T, XA7A35T, XA7A50T, XA7A75T
1.07
1.06
N/A
XA7A100T
XQ7A100T, XQ7A200T
XQ7A50T
Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or
Production. Each designation is defined as follows:
Advance Product Specification
These specifications are based on simulations only and are typically available soon after device design specifications are
frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting
might still occur.
Preliminary Product Specification
These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with
this designation are intended to give a better indication of the expected performance of production silicon. The probability
of under-reporting delays is greatly reduced as compared to Advance data.
Production Product Specification
These specifications are released once enough production silicon of a particular device family member has been
characterized to provide full correlation between specifications and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest
speed grades transition to Production before faster speed grades.
Testing of AC Switching Characteristics
Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are
representative of worst-case supply voltage and junction temperature conditions.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and
back-annotate to the simulation net list. Unless otherwise noted, values apply to all Artix-7 FPGAs.
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Product Specification
12
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Speed Grade Designations
Since individual family members are produced at different times, the migration from one category to another depends
completely on the status of the fabrication process for each device. Table 13 correlates the current status of each Artix-7
device on a per speed grade basis.
Table 13: Artix-7 Device Speed Grade Designations
Speed Grade Designations
Device
Advance
Preliminary
Production
-3, -2, -1, -1LI (0.95V), and -2LE (0.9V)
-3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)
-3, -2, -1, -1LI (0.95V), and -2LE (0.9V)
-3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)
-3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)
-3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)
-3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)
-3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)
-2I, -1I, and -1Q
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
-2I, -1I, and -1Q
-2I, -1I, and -1Q
-2I, -1I, and -1Q
-2I, -1I, and -1Q
-2I, -1I, and -1Q
-2I, -1I, and -1Q
-2I, -1I, -1LI (0.95V), and -1M
-2I, -1I, -1LI (0.95V), and -1M
-2I, -1I, -1LI (0.95V), and -1M
Production Silicon and Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is
released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent
speed specification releases.
Table 14 lists the production released Artix-7 device, speed grade, and the minimum corresponding supported speed
specification version and software revisions. The software and speed specifications listed are the minimum releases required
for production. All subsequent releases of software and speed specifications are valid.
Table 14: Artix-7 Device Production Software and Speed Specification Release
Speed Grade
Device
1.0V
0.95V
-1LI
0.9V
-2LE
-3
-2
-2LE
-1
-1Q
-1M
XC7A12T
XC7A15T
XC7A25T
XC7A35T
Vivado tools
2018.2 v1.22
Vivado tools 2017.4 v1.20
N/A
N/A
Vivado tools
2017.4 v1.20 2018.1 v1.14
Vivado tools
Vivado tools 2014.4 v1.14
Vivado tools 2017.4 v1.20
Vivado tools 2013.4 v1.11
N/A
N/A
N/A
N/A
N/A
N/A
Vivado tools Vivado tools
2014.4 v1.14 2014.4 v1.10
Vivado tools Vivado tools
Vivado tools
2018.2 v1.22
2017.4 v1.20 2018.1 v1.14
Vivado tools Vivado tools
2014.4 v1.14 2013.4 v1.08
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Product Specification
13
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 14: Artix-7 Device Production Software and Speed Specification Release (Cont’d)
Speed Grade
Device
1.0V
0.95V
-1LI
0.9V
-2LE
-3
-2
-2LE
-1
-1Q
-1M
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
Vivado tools 2013.4 v1.11
N/A
N/A
Vivado tools
2014.4 v1.14 2013.4 v1.08
Vivado tools
Vivado tools 2013.3 v1.10
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Vivado tools Vivado tools
2014.4 v1.14 2013.3 v1.07
ISE tools 14.4 or Vivado tools 2012.4 with the
14.4/2012.4 device pack v1.07
Vivado tools
2014.4 v1.14
ISE tools 14.5
or Vivado
tools 2013.1
Vivado tools
2014.4 v1.14
ISE tools 14.4 or Vivado tools 2012.4 with the
14.4/2012.4 device pack v1.07
v1.05
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Vivado tools
2018.1 v1.15
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Vivado tools 2018.1 v1.15
Vivado tools 2014.4 v1.14
Vivado tools 2018.1 v1.15
Vivado tools 2014.1 v1.09
Vivado tools 2014.1 v1.09
Vivado tools 2014.1 v1.09
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Vivado tools
2014.4 v1.14
Vivado tools
2018.1 v1.15
Vivado tools
2014.1 v1.09
Vivado tools
2014.1 v1.09
Vivado tools
2014.1 v1.09
ISE tools 14.5
or Vivado tools
2013.1 v1.05
ISE tools 14.5 ISE tools 14.6
or Vivado tools or Vivado tools
2013.1 v1.05
2013.2 v1.06
XQ7A50T
N/A
N/A
Vivado tools
2014.2 v1.08
N/A
N/A
Vivado tools
2014.2 v1.08
N/A
Vivado tools
2014.2 v1.08 2015.4 v1.11
Vivado tools
N/A
N/A
XQ7A100T
ISE tools 14.5
or Vivado tools
2013.1 v1.04
ISE tools 14.5
or Vivado tools
2013.1 v1.04
N/A
N/A
ISE tools 14.6 Vivado tools
orVivadotools 2015.4 v1.11
2013.2 v1.05
XQ7A200T
N/A
ISE tools 14.5
or Vivado tools
2013.1 v1.04
N/A
ISE tools 14.5
or Vivado tools
2013.1 v1.04
ISE tools 14.6
orVivadotools 2015.4 v1.11
2013.2 v1.05
Vivado tools
N/A
Selecting the Correct Speed Grade and Voltage in the Vivado Tools
It is important to select the correct device speed grade and voltage in the Vivado tools for the device that you are selecting.
To select the 1.0V speed specifications in the Vivado tools, select the Artix-7, XA Artix-7, or Defense Grade Artix-7Q
sub-family, and then select the part name that is the device name followed by the package name followed by the speed
grade. For example, select the xc7a100tfgg676-3 part name for the XC7A100T device in the FGG676 package and -3 (1.0V)
speed grade or select the xc7a100tfgg676-2L part name for the XC7A100T device in the FGG676 package and -2LE (1.0V)
speed grade.
To select the -1LI (0.95V) speed specifications in the Vivado tools, select the Artix-7 sub-family and then select the part
name that is the device name followed by an “i” followed by the package name followed by the speed grade. For example,
select the xc7a100tifgg676-1L part name for the XC7A100T device in the FGG676 package and -1LI (0.95V) speed grade.
The -1LI (0.95V) speed specifications are not supported in the ISE tools.
To select the -2LE (0.9V) speed specifications in the Vivado tools, select the Artix-7 Low Voltage sub-family and then select
the part name that is the device name followed by an “l” followed by the package name followed by the speed grade. For
example, select the xc7a100tlfgg676-2L part name for the XC7A100T device in the FGG676 package and -2LE (0.9V) speed
grade.
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Product Specification
14
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
A similar part naming convention applies to the speed specifications selection in the ISE tools for supported devices. See
Table 14 for the subset of 7 series FPGAs supported in the ISE tools.
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Artix-7
devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to
the same guidelines as the AC Switching Characteristics, page 12.
Table 15: Networking Applications Interface Performances
Speed Grade
Description
1.0V
-2/-2LE
680
0.95V
-1LI
600
0.9V
-2LE
600
Units
-3
-1
SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8)
DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14)
SDR LVDS receiver (SFI-4.1)(1)
680
600
950
600
950
Mb/s
Mb/s
Mb/s
Mb/s
1250
680
1250
680
950
950
600
600
DDR LVDS receiver (SPI-4.2)(1)
1250
1250
950
950
Notes:
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate
deterministic performance.
Table 16: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
(1)(2)
Generator
Speed Grade
Memory Standard
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1Q/-1M
4:1 Memory Controllers
DDR3
1066(3)
800
800
800
800
800
667
667
667
N/A
533
800
667
667
800
667
667
Mb/s
Mb/s
Mb/s
DDR3L
DDR2
800
2:1 Memory Controllers
DDR3
800
800
800
667
700
700
700
667
620
620
620
533
620
N/A
533
400
620
620
620
533
620
620
620
533
Mb/s
Mb/s
Mb/s
Mb/s
DDR3L
DDR2
LPDDR2
Notes:
1.
V
tracking is required. For more information, see 7 Series FPGAs Memory Interface Solutions User Guide (UG586).
REF
2. When using the internal V
, the maximum data rate is 800 Mb/s (400 MHz).
REF
3. The maximum PHY rate is 800 Mb/s in the CPG238 package.
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Product Specification
15
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
IOB Pad Input/Output/3-State
Table 17 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based
on standard) and 3-state delays.
•
•
•
T
is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies
IOPI
depending on the capability of the SelectIO input buffer.
T
is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies
IOOP
depending on the capability of the SelectIO output buffer.
T
is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is
IOTP
disabled. The delay varies depending on the SelectIO capability of the output buffer. In HR I/O banks, the IN_TERM
termination turn-on time is always faster than T when the INTERMDISABLE pin is used.
IOTP
Table 17: IOB High Range (HR) Switching Characteristics
T
T
T
IOTP
IOPI
IOOP
Speed Grade
1.0V
Speed Grade
1.0V
Speed Grade
1.0V
I/O Standard
Units
0.95V 0.9V
0.95V 0.9V
0.95V 0.9V
-1LI -2LE
-2/
-1Q/
-1M
-2/
-1Q/
-1M
-2/
-1Q/
-1M
-3
-1
-1LI -2LE -3
-1
-1LI -2LE -3
-1
-2LE
-2LE
-2LE
LVTTL_S4
LVTTL_S8
LVTTL_S12
LVTTL_S16
LVTTL_S24
LVTTL_F4
LVTTL_F8
LVTTL_F12
LVTTL_F16
LVTTL_F24
LVDS_25
1.26 1.34 1.41 1.53 1.41 1.58 3.80 3.93 4.18 4.18 4.18 4.41 3.82 3.96 4.20 4.20 4.20 4.05 ns
1.26 1.34 1.41 1.53 1.41 1.58 3.54 3.66 3.92 3.92 3.92 4.15 3.56 3.69 3.93 3.93 3.93 3.78 ns
1.26 1.34 1.41 1.53 1.41 1.58 3.52 3.65 3.90 3.90 3.90 4.13 3.54 3.68 3.91 3.91 3.91 3.77 ns
1.26 1.34 1.41 1.53 1.41 1.58 3.07 3.19 3.45 3.45 3.45 3.68 3.09 3.22 3.46 3.46 3.46 3.31 ns
1.26 1.34 1.41 1.53 1.41 1.58 3.29 3.41 3.67 3.67 3.67 3.90 3.31 3.44 3.68 3.68 3.68 3.53 ns
1.26 1.34 1.41 1.53 1.41 1.58 3.26 3.38 3.64 3.64 3.64 3.86 3.28 3.41 3.65 3.65 3.65 3.50 ns
1.26 1.34 1.41 1.53 1.41 1.58 2.74 2.87 3.12 3.12 3.12 3.35 2.76 2.90 3.13 3.13 3.13 2.99 ns
1.26 1.34 1.41 1.53 1.41 1.58 2.73 2.85 3.10 3.10 3.10 3.33 2.74 2.88 3.12 3.12 3.12 2.97 ns
1.26 1.34 1.41 1.53 1.41 1.58 2.56 2.68 2.93 2.93 2.93 3.16 2.57 2.71 2.95 2.95 2.95 2.80 ns
1.26 1.34 1.41 1.53 1.41 1.58 2.52 2.65 2.90 3.23 2.90 3.22 2.54 2.68 2.91 3.24 2.91 2.86 ns
0.73 0.81 0.88 0.89 0.88 0.90 1.29 1.41 1.67 1.67 1.67 1.86 1.31 1.44 1.68 1.68 1.68 1.50 ns
MINI_LVDS_25 0.73 0.81 0.88 0.89 0.88 0.90 1.27 1.40 1.65 1.65 1.65 1.88 1.29 1.43 1.66 1.66 1.66 1.52 ns
BLVDS_25
0.73 0.81 0.88 0.88 0.88 0.90 1.84 1.96 2.21 2.76 2.21 2.44 1.85 1.99 2.23 2.77 2.23 2.08 ns
0.73 0.81 0.88 0.89 0.88 0.90 1.27 1.40 1.65 1.65 1.65 1.88 1.29 1.43 1.66 1.66 1.66 1.52 ns
RSDS_25 (point
to point)
PPDS_25
TMDS_33
PCI33_3
0.73 0.81 0.88 0.89 0.88 0.90 1.29 1.41 1.67 1.67 1.67 1.88 1.31 1.44 1.68 1.68 1.68 1.52 ns
0.73 0.81 0.88 0.92 0.88 0.90 1.41 1.54 1.79 1.79 1.79 1.99 1.43 1.57 1.80 1.80 1.80 1.63 ns
1.24 1.32 1.39 1.52 1.39 1.57 3.10 3.22 3.48 3.48 3.48 3.71 3.12 3.25 3.49 3.49 3.49 3.34 ns
0.67 0.75 0.82 0.88 0.82 0.87 1.81 1.93 2.18 2.18 2.18 2.41 1.82 1.96 2.20 2.20 2.20 2.05 ns
0.67 0.75 0.82 0.88 0.82 0.87 1.29 1.41 1.67 1.67 1.67 1.90 1.31 1.44 1.68 1.68 1.68 1.53 ns
HSUL_12_S
HSUL_12_F
DIFF_HSUL_
12_S
0.68 0.76 0.83 0.86 0.83 0.88 1.81 1.93 2.18 2.18 2.18 2.21 1.82 1.96 2.20 2.20 2.20 1.84 ns
0.68 0.76 0.83 0.86 0.83 0.88 1.29 1.41 1.67 1.67 1.67 1.79 1.31 1.44 1.68 1.68 1.68 1.42 ns
0.76 0.84 0.91 0.91 0.91 0.96 1.68 1.80 2.06 2.06 2.06 2.24 1.70 1.83 2.07 2.07 2.07 1.88 ns
0.76 0.84 0.91 0.91 0.91 0.96 1.38 1.51 1.76 1.76 1.76 1.97 1.40 1.54 1.77 1.77 1.77 1.61 ns
0.70 0.78 0.85 0.85 0.85 0.87 1.70 1.82 2.07 2.07 2.07 2.24 1.71 1.85 2.09 2.09 2.09 1.88 ns
0.70 0.78 0.85 0.85 0.85 0.87 1.45 1.57 1.82 1.82 1.82 2.00 1.46 1.60 1.84 1.84 1.84 1.64 ns
DIFF_HSUL_
12_F
MOBILE_
DDR_S
MOBILE_
DDR_F
DIFF_MOBILE_
DDR_S
DIFF_MOBILE_
DDR_F
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Product Specification
16
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 17: IOB High Range (HR) Switching Characteristics (Cont’d)
T
T
T
IOTP
IOPI
IOOP
Speed Grade
1.0V
Speed Grade
1.0V
Speed Grade
1.0V
I/O Standard
Units
0.95V 0.9V
0.95V 0.9V
0.95V 0.9V
-1LI -2LE
-2/
-1Q/
-1M
-2/
-1Q/
-1M
-2/
-1Q/
-1M
-3
-1
-1LI -2LE -3
-1
-1LI -2LE -3
-1
-2LE
-2LE
-2LE
HSTL_I_S
0.67 0.75 0.82 0.86 0.82 0.87 1.62 1.74 1.99 1.99 1.99 2.19 1.63 1.77 2.01 2.01 2.01 1.83 ns
0.65 0.73 0.80 0.86 0.80 0.85 1.41 1.54 1.79 1.79 1.79 1.99 1.43 1.57 1.80 1.81 1.80 1.63 ns
0.67 0.75 0.82 0.88 0.82 0.87 1.29 1.41 1.67 1.67 1.67 1.86 1.31 1.44 1.68 1.68 1.68 1.50 ns
0.66 0.75 0.81 0.88 0.81 0.87 1.41 1.54 1.79 1.79 1.79 1.97 1.43 1.57 1.80 1.80 1.80 1.61 ns
HSTL_II_S
HSTL_I_18_S
HSTL_II_18_S
DIFF_HSTL_I_S 0.68 0.76 0.83 0.86 0.83 0.85 1.59 1.71 1.96 1.96 1.96 2.13 1.60 1.74 1.98 1.98 1.98 1.77 ns
DIFF_HSTL_
0.68 0.76 0.83 0.86 0.83 0.85 1.51 1.63 1.88 1.88 1.88 2.07 1.52 1.66 1.90 1.90 1.90 1.70 ns
II_S
DIFF_HSTL_
0.71 0.79 0.86 0.86 0.86 0.87 1.38 1.51 1.76 1.76 1.76 1.96 1.40 1.54 1.77 1.77 1.77 1.59 ns
I_18_S
DIFF_HSTL_
0.70 0.78 0.85 0.88 0.85 0.87 1.46 1.58 1.84 1.84 1.84 2.00 1.48 1.61 1.85 1.85 1.85 1.64 ns
II_18_S
HSTL_I_F
0.67 0.75 0.82 0.86 0.82 0.87 1.10 1.22 1.48 1.49 1.48 1.69 1.12 1.25 1.49 1.51 1.49 1.33 ns
0.65 0.73 0.80 0.86 0.80 0.85 1.12 1.24 1.49 1.49 1.49 1.71 1.13 1.27 1.51 1.51 1.51 1.34 ns
0.67 0.75 0.82 0.88 0.82 0.87 1.13 1.26 1.51 1.54 1.51 1.72 1.15 1.29 1.52 1.56 1.52 1.36 ns
0.66 0.75 0.81 0.88 0.81 0.87 1.12 1.24 1.49 1.51 1.49 1.71 1.13 1.27 1.51 1.52 1.51 1.34 ns
HSTL_II_F
HSTL_I_18_F
HSTL_II_18_F
DIFF_HSTL_I_F 0.68 0.76 0.83 0.86 0.83 0.85 1.18 1.30 1.56 1.56 1.56 1.77 1.20 1.33 1.57 1.57 1.57 1.41 ns
DIFF_HSTL_
0.68 0.76 0.83 0.86 0.83 0.85 1.21 1.33 1.59 1.59 1.59 1.77 1.23 1.36 1.60 1.60 1.60 1.41 ns
II_F
DIFF_HSTL_
0.71 0.79 0.86 0.86 0.86 0.87 1.21 1.33 1.59 1.59 1.59 1.77 1.23 1.36 1.60 1.60 1.60 1.41 ns
I_18_F
DIFF_HSTL_
0.70 0.78 0.85 0.88 0.85 0.87 1.21 1.33 1.59 1.59 1.59 1.77 1.23 1.36 1.60 1.60 1.60 1.41 ns
II_18_F
LVCMOS33_S4 1.26 1.34 1.41 1.52 1.41 1.62 3.80 3.93 4.18 4.18 4.18 4.41 3.82 3.96 4.20 4.20 4.20 4.05 ns
LVCMOS33_S8 1.26 1.34 1.41 1.52 1.41 1.62 3.52 3.65 3.90 3.90 3.90 4.13 3.54 3.68 3.91 3.91 3.91 3.77 ns
LVCMOS33_S12 1.26 1.34 1.41 1.52 1.41 1.62 3.09 3.21 3.46 3.46 3.46 3.69 3.10 3.24 3.48 3.48 3.48 3.33 ns
LVCMOS33_S16 1.26 1.34 1.41 1.52 1.41 1.62 3.40 3.52 3.77 3.78 3.77 4.00 3.42 3.55 3.79 3.79 3.79 3.64 ns
LVCMOS33_F4 1.26 1.34 1.41 1.52 1.41 1.62 3.26 3.38 3.64 3.64 3.64 3.86 3.28 3.41 3.65 3.65 3.65 3.50 ns
LVCMOS33_F8 1.26 1.34 1.41 1.52 1.41 1.62 2.74 2.87 3.12 3.12 3.12 3.35 2.76 2.90 3.13 3.13 3.13 2.99 ns
LVCMOS33_F12 1.26 1.34 1.41 1.52 1.41 1.62 2.56 2.68 2.93 2.93 2.93 3.16 2.57 2.71 2.95 2.95 2.95 2.80 ns
LVCMOS33_F16 1.26 1.34 1.41 1.52 1.41 1.62 2.56 2.68 2.93 3.06 2.93 3.16 2.57 2.71 2.95 3.07 2.95 2.80 ns
LVCMOS25_S4 1.12 1.20 1.27 1.38 1.27 1.43 3.13 3.26 3.51 3.51 3.51 3.72 3.15 3.29 3.52 3.52 3.52 3.36 ns
LVCMOS25_S8 1.12 1.20 1.27 1.38 1.27 1.43 2.88 3.01 3.26 3.26 3.26 3.49 2.90 3.04 3.27 3.27 3.27 3.13 ns
LVCMOS25_S12 1.12 1.20 1.27 1.38 1.27 1.43 2.48 2.60 2.85 2.85 2.85 3.08 2.49 2.63 2.87 2.87 2.87 2.72 ns
LVCMOS25_S16 1.12 1.20 1.27 1.38 1.27 1.43 2.82 2.94 3.20 3.20 3.20 3.43 2.84 2.97 3.21 3.21 3.21 3.06 ns
LVCMOS25_F4 1.12 1.20 1.27 1.38 1.27 1.43 2.74 2.87 3.12 3.12 3.12 3.35 2.76 2.90 3.13 3.13 3.13 2.99 ns
LVCMOS25_F8 1.12 1.20 1.27 1.38 1.27 1.43 2.18 2.30 2.56 2.56 2.56 2.79 2.20 2.33 2.57 2.57 2.57 2.42 ns
LVCMOS25_F12 1.12 1.20 1.27 1.38 1.27 1.43 2.16 2.29 2.54 2.54 2.54 2.77 2.18 2.32 2.55 2.56 2.55 2.41 ns
LVCMOS25_F16 1.12 1.20 1.27 1.38 1.27 1.43 2.01 2.13 2.39 2.63 2.39 2.61 2.03 2.16 2.40 2.65 2.40 2.25 ns
LVCMOS18_S4 0.74 0.83 0.89 0.97 0.89 0.94 1.62 1.74 1.99 1.99 1.99 2.19 1.63 1.77 2.01 2.01 2.01 1.83 ns
LVCMOS18_S8 0.74 0.83 0.89 0.97 0.89 0.94 2.18 2.30 2.56 2.56 2.56 2.79 2.20 2.33 2.57 2.57 2.57 2.42 ns
LVCMOS18_S12 0.74 0.83 0.89 0.97 0.89 0.94 2.18 2.30 2.56 2.56 2.56 2.79 2.20 2.33 2.57 2.57 2.57 2.42 ns
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Product Specification
17
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 17: IOB High Range (HR) Switching Characteristics (Cont’d)
T
T
T
IOTP
IOPI
IOOP
Speed Grade
1.0V
Speed Grade
1.0V
Speed Grade
1.0V
I/O Standard
Units
0.95V 0.9V
0.95V 0.9V
0.95V 0.9V
-1LI -2LE
-2/
-1Q/
-1M
-2/
-1Q/
-1M
-2/
-1Q/
-1M
-3
-1
-1LI -2LE -3
-1
-1LI -2LE -3
-1
-2LE
-2LE
-2LE
LVCMOS18_S16 0.74 0.83 0.89 0.97 0.89 0.94 1.52 1.65 1.90 1.90 1.90 2.13 1.54 1.68 1.91 1.91 1.91 1.77 ns
LVCMOS18_S24 0.74 0.83 0.89 0.97 0.89 0.94 1.60 1.72 1.98 2.40 1.98 2.21 1.62 1.75 1.99 2.41 1.99 1.84 ns
LVCMOS18_F4 0.74 0.83 0.89 0.97 0.89 0.94 1.45 1.57 1.82 1.82 1.82 2.05 1.46 1.60 1.84 1.84 1.84 1.69 ns
LVCMOS18_F8 0.74 0.83 0.89 0.97 0.89 0.94 1.68 1.80 2.06 2.06 2.06 2.29 1.70 1.83 2.07 2.07 2.07 1.92 ns
LVCMOS18_F12 0.74 0.83 0.89 0.97 0.89 0.94 1.68 1.80 2.06 2.06 2.06 2.29 1.70 1.83 2.07 2.07 2.07 1.92 ns
LVCMOS18_F16 0.74 0.83 0.89 0.97 0.89 0.94 1.40 1.52 1.77 1.78 1.77 2.00 1.42 1.55 1.79 1.79 1.79 1.64 ns
LVCMOS18_F24 0.74 0.83 0.89 0.97 0.89 0.94 1.34 1.46 1.71 2.28 1.71 1.94 1.35 1.49 1.73 2.29 1.73 1.58 ns
LVCMOS15_S4 0.77 0.86 0.93 0.96 0.93 0.98 2.05 2.18 2.43 2.43 2.43 2.50 2.07 2.21 2.45 2.45 2.45 2.14 ns
LVCMOS15_S8 0.77 0.86 0.93 0.96 0.93 0.98 2.09 2.21 2.46 2.46 2.46 2.69 2.10 2.24 2.48 2.48 2.48 2.33 ns
LVCMOS15_S12 0.77 0.86 0.93 0.96 0.93 0.98 1.59 1.71 1.96 1.96 1.96 2.19 1.60 1.74 1.98 1.98 1.98 1.83 ns
LVCMOS15_S16 0.77 0.86 0.93 0.96 0.93 0.98 1.59 1.71 1.96 1.96 1.96 2.19 1.60 1.74 1.98 1.98 1.98 1.83 ns
LVCMOS15_F4 0.77 0.86 0.93 0.96 0.93 0.98 1.85 1.97 2.23 2.23 2.23 2.27 1.87 2.00 2.24 2.24 2.24 1.91 ns
LVCMOS15_F8 0.77 0.86 0.93 0.96 0.93 0.98 1.60 1.72 1.98 1.98 1.98 2.21 1.62 1.75 1.99 1.99 1.99 1.84 ns
LVCMOS15_F12 0.77 0.86 0.93 0.96 0.93 0.98 1.35 1.47 1.73 1.73 1.73 1.96 1.37 1.50 1.74 1.74 1.74 1.59 ns
LVCMOS15_F16 0.77 0.86 0.93 0.96 0.93 0.98 1.34 1.46 1.71 2.07 1.71 1.94 1.35 1.49 1.73 2.09 1.73 1.58 ns
LVCMOS12_S4 0.87 0.95 1.02 1.19 1.02 1.08 2.57 2.69 2.95 2.95 2.95 3.18 2.59 2.72 2.96 2.96 2.96 2.81 ns
LVCMOS12_S8 0.87 0.95 1.02 1.19 1.02 1.08 2.09 2.21 2.46 2.46 2.46 2.69 2.10 2.24 2.48 2.48 2.48 2.33 ns
LVCMOS12_S12 0.87 0.95 1.02 1.19 1.02 1.08 1.79 1.91 2.17 2.17 2.17 2.40 1.81 1.94 2.18 2.18 2.18 2.03 ns
LVCMOS12_F4 0.87 0.95 1.02 1.19 1.02 1.08 1.98 2.10 2.35 2.35 2.35 2.58 1.99 2.13 2.37 2.37 2.37 2.22 ns
LVCMOS12_F8 0.87 0.95 1.02 1.19 1.02 1.08 1.54 1.66 1.92 1.92 1.92 2.15 1.56 1.69 1.93 1.93 1.93 1.78 ns
LVCMOS12_F12 0.87 0.95 1.02 1.19 1.02 1.08 1.38 1.51 1.76 1.76 1.76 1.97 1.40 1.54 1.77 1.77 1.77 1.61 ns
SSTL135_S
SSTL15_S
0.67 0.75 0.82 0.88 0.82 0.87 1.35 1.47 1.73 1.73 1.73 1.93 1.37 1.50 1.74 1.74 1.74 1.56 ns
0.60 0.68 0.75 0.75 0.75 0.80 1.30 1.43 1.68 1.71 1.68 1.88 1.32 1.46 1.69 1.73 1.69 1.52 ns
0.67 0.75 0.82 0.86 0.82 0.87 1.67 1.79 2.04 2.04 2.04 2.24 1.68 1.82 2.06 2.06 2.06 1.88 ns
0.67 0.75 0.82 0.88 0.82 0.85 1.31 1.43 1.68 1.68 1.68 1.91 1.32 1.46 1.70 1.70 1.70 1.55 ns
SSTL18_I_S
SSTL18_II_S
DIFF_SSTL135_
S
0.68 0.76 0.83 0.88 0.83 0.87 1.35 1.47 1.73 1.73 1.73 1.93 1.37 1.50 1.74 1.74 1.74 1.56 ns
0.68 0.76 0.83 0.88 0.83 0.87 1.30 1.43 1.68 1.71 1.68 1.88 1.32 1.46 1.69 1.73 1.69 1.52 ns
0.71 0.79 0.86 0.88 0.86 0.87 1.68 1.80 2.06 2.06 2.06 2.24 1.70 1.83 2.07 2.07 2.07 1.88 ns
0.71 0.79 0.86 0.88 0.86 0.87 1.38 1.51 1.76 1.76 1.76 1.94 1.40 1.54 1.77 1.77 1.77 1.58 ns
DIFF_SSTL15_
S
DIFF_SSTL18
_I_S
DIFF_SSTL18
_II_S
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18
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 17: IOB High Range (HR) Switching Characteristics (Cont’d)
T
T
T
IOTP
IOPI
IOOP
Speed Grade
1.0V
Speed Grade
1.0V
Speed Grade
1.0V
I/O Standard
Units
0.95V 0.9V
0.95V 0.9V
0.95V 0.9V
-1LI -2LE
-2/
-1Q/
-1M
-2/
-1Q/
-1M
-2/
-1Q/
-1M
-3
-1
-1LI -2LE -3
-1
-1LI -2LE -3
-1
-2LE
-2LE
-2LE
SSTL135_F
SSTL15_F
0.67 0.75 0.82 0.88 0.82 0.87 1.12 1.24 1.49 1.49 1.49 1.71 1.13 1.27 1.51 1.51 1.51 1.34 ns
0.60 0.68 0.75 0.75 0.75 0.80 1.07 1.19 1.45 1.45 1.45 1.68 1.09 1.22 1.46 1.46 1.46 1.31 ns
0.67 0.75 0.82 0.86 0.82 0.87 1.12 1.24 1.49 1.53 1.49 1.72 1.13 1.27 1.51 1.54 1.51 1.36 ns
0.67 0.75 0.82 0.88 0.82 0.85 1.12 1.24 1.49 1.51 1.49 1.71 1.13 1.27 1.51 1.52 1.51 1.34 ns
SSTL18_I_F
SSTL18_II_F
DIFF_SSTL135
_F
0.68 0.76 0.83 0.88 0.83 0.87 1.12 1.24 1.49 1.49 1.49 1.71 1.13 1.27 1.51 1.51 1.51 1.34 ns
DIFF_SSTL15_F 0.68 0.76 0.83 0.88 0.83 0.87 1.07 1.19 1.45 1.45 1.45 1.68 1.09 1.22 1.46 1.46 1.46 1.31 ns
DIFF_SSTL18_I
0.71 0.79 0.86 0.88 0.86 0.87 1.23 1.35 1.60 1.60 1.60 1.80 1.24 1.38 1.62 1.62 1.62 1.44 ns
_F
DIFF_SSTL18_II
0.71 0.79 0.86 0.88 0.86 0.87 1.21 1.33 1.59 1.59 1.59 1.79 1.23 1.36 1.60 1.60 1.60 1.42 ns
_F
Table 18 specifies the values of T
output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). T
and T
. T
is described as the delay from the T pin to the IOB pad through the
IOTPHZ
IOIBUFDISABLE IOTPHZ
is described as the IOB delay from
IOIBUFDISABLE
IBUFDISABLE to O output. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster than T
INTERMDISABLE pin is used.
when the
IOTPHZ
Table 18: IOB 3-state Output Switching Characteristics
Speed Grade
Symbol
Description
1.0V
-2/-2LE
0.95V
-1LI
0.9V
Units
-3
-1
-1Q/-1M
2.37
-2LE
2.03
2.17
TIOTPHZ
TIOIBUFDISABLE
T input to pad high-impedance
2.06
2.11
2.19
2.30
2.37
2.60
2.37
2.60
ns
ns
IBUF turn-on time from IBUFDISABLE to O
output
2.60
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 19 shows the test setup parameters used for measuring input delay.
Table 19: Input Delay Measurement Methodology
VMEAS
VREF
(1)
(1)
Description
I/O Standard Attribute
VL
VH
(3)(5)
(2)(4)
LVCMOS, 1.2V
LVCMOS, 1.5V
LVCMOS, 1.8V
LVCMOS, 2.5V
LVCMOS, 3.3V
LVTTL, 3.3V
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
0.1
1.1
0.6
0.75
0.9
–
–
0.1
0.1
1.4
1.7
2.4
3.2
3.2
1.7
3.2
–
0.1
1.25
1.65
1.65
0.9
–
0.1
–
0.1
–
MOBILE_DDR, 1.8V
PCI33, 3.3V
MOBILE_DDR
PCI33_3
0.1
–
0.1
1.65
VREF
–
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12
V
REF – 0.5
VREF + 0.5
0.60
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 19: Input Delay Measurement Methodology (Cont’d)
Description I/O Standard Attribute
HSTL, Class I & II, 1.5V
VMEAS
VREF
(1)
(1)
VL
VH
(3)(5)
(2)(4)
HSTL_I, HSTL_II
HSTL_I_18, HSTL_II_18
HSUL_12
VREF – 0.65
VREF – 0.8
VREF + 0.65
VREF + 0.8
VREF + 0.5
VREF + 0.5
VREF
VREF
VREF
VREF
VREF
VREF
VREF
0(5)
0.75
0.90
0.60
0.60
0.675
0.75
0.90
–
HSTL, Class I & II, 1.8V
HSUL (High-Speed Unterminated Logic), 1.2V
SSTL (Stub Terminated Transceiver Logic), 1.2V
SSTL, 1.35V
V
REF – 0.5
VREF – 0.5
SSTL12
SSTL135, SSTL135_R
SSTL15, SSTL15_R
SSTL18_I, SSTL18_II
DIFF_MOBILE_DDR
DIFF_HSTL_I_12
VREF – 0.575 VREF + 0.575
SSTL, 1.5V
VREF – 0.65
REF – 0.8
VREF + 0.65
VREF + 0.8
0.9 + 0.125
0.6 + 0.125
SSTL, Class I & II, 1.8V
V
DIFF_MOBILE_DDR, 1.8V
DIFF_HSTL, Class I, 1.2V
DIFF_HSTL, Class I & II,1.5V
0.9 – 0.125
0.6 – 0.125
0(5)
–
DIFF_HSTL_I,
DIFF_HSTL_II
0.75 – 0.125 0.75 + 0.125
0(5)
–
DIFF_HSTL, Class I & II, 1.8V
DIFF_HSTL_I_18,
DIFF_HSTL_II_18
0.9 – 0.125
0.6 – 0.125
0.9 + 0.125
0.6 + 0.125
0(5)
–
DIFF_HSUL, 1.2V
DIFF_HSUL_12
0(5)
0(5)
–
–
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V
DIFF_SSTL135,
0.675 – 0.125 0.675 + 0.125
DIFF_SSTL135_R
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V
DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V
DIFF_SSTL15,
DIFF_SSTL15_R
0.75 – 0.125 0.75 + 0.125
0(5)
0(5)
–
–
DIFF_SSTL18_I,
DIFF_SSTL18_II
0.9 – 0.125
1.2 – 0.125
0.9 + 0.125
1.2 + 0.125
LVDS_25, 2.5V
BLVDS_25, 2.5V
MINI_LVDS_25, 2.5V
PPDS_25
LVDS_25
0(5)
0(5)
0(5)
0(5)
0(5)
0(5)
–
–
–
–
–
–
BLVDS_25
MINI_LVDS_25
PPDS_25
1.25 – 0.125 1.25 + 0.125
1.25 – 0.125 1.25 + 0.125
1.25 – 0.125 1.25 + 0.125
1.25 – 0.125 1.25 + 0.125
RSDS_25
RSDS_25
TMDS_33
TMDS_33
3 – 0.125
3 + 0.125
Notes:
1. Input waveform switches between V and V .
L
H
2. Measurements are made at typical, minimum, and maximum V
values listed are typical.
values. Reported delays reflect worst case of these measurements. V
REF
REF
3. Input voltage level from which measurement starts.
4. This is an input voltage reference that bears no relation to the V
5. The value given is the differential input voltage.
/ V
parameters found in IBIS models and/or noted in Figure 1.
REF
MEAS
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20
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Output Delay Measurements
Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay
of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the
generalized test setups shown in Figure 1 and Figure 2.
X-Ref Target - Figure 1
VREF
RREF
FPGA Output
VMEAS
(Voltage Level When Taking
Delay Measurement)
CREF
(Probe Capacitance)
DS181_04_090514
Figure 1: Single-Ended Test Setup
X-Ref Target - Figure 2
FPGA Output
+
CREF
RREF VMEAS
–
DS181_05_090514
Figure 2: Differential Test Setup
Parameters V , R , C , and V
fully describe the test conditions for each I/O standard. The most accurate prediction
MEAS
REF REF REF
of propagation delay in any given application can be obtained through IBIS simulation, using this method:
1. Simulate the output driver of choice into the generalized test setup using values from Table 20.
2. Record the time to V
.
MEAS
3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance
value to represent the load.
4. Record the time to V
.
MEAS
5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the
PCB trace.
Table 20: Output Delay Measurement Methodology
(1)
RREF CREF
VMEAS VREF
Description
I/O Standard Attribute
LVCMOS12
(Ω)
1M
1M
1M
1M
1M
1M
25
(pF)
0
(V)
(V)
LVCMOS, 1.2V
LVCMOS, 1.5V
LVCMOS, 1.8V
LVCMOS, 2.5V
LVCMOS, 3.3V
LVTTL, 3.3V
0.6
0
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
0
0.75
0.9
0
0
0
0
1.25
1.65
1.65
1.65
0
0
0
0
0
PCI33, 3.3V
PCI33_3
10
0
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 20: Output Delay Measurement Methodology (Cont’d)
Description I/O Standard Attribute
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12
(1)
RREF CREF
VMEAS VREF
(Ω)
50
50
25
50
25
50
50
50
50
50
(pF)
(V)
(V)
0
0
0
0
0
0
0
0
0
0
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
0.6
HSTL, Class I, 1.5V
HSTL_I
0.75
0.75
0.9
HSTL, Class II, 1.5V
HSTL_II
HSTL, Class I, 1.8V
HSTL_I_18
HSTL, Class II, 1.8V
HSTL_II_18
0.9
HSUL (High-Speed Unterminated Logic), 1.2V
SSTL12, 1.2V
HSUL_12
0.6
SSTL12
0.6
SSTL135/SSTL135_R, 1.35V
SSTL15/SSTL15_R, 1.5V
SSTL135, SSTL135_R
SSTL15, SSTL15_R
SSTL18_I, SSTL18_II
0.675
0.75
0.9
SSTL (Stub Series Terminated Logic),
Class I & Class II, 1.8V
DIFF_MOBILE_DDR, 1.8V
DIFF_HSTL, Class I, 1.2V
DIFF_HSTL, Class I & II, 1.5V
DIFF_HSTL, Class I & II, 1.8V
DIFF_HSUL_12, 1.2V
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V
DIFF_SSTL18, Class I & II, 1.8V
LVDS, 2.5V
DIFF_MOBILE_DDR
DIFF_HSTL_I_12
50
50
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
0(2)
0.9
0.6
0.75
0.9
0.6
0.675
0.75
0.9
0
DIFF_HSTL_I, DIFF_HSTL_II
DIFF_HSTL_I_18, DIFF_HSTL_II_18
DIFF_HSUL_12
50
50
50
DIFF_SSTL135, DIFF_SSTL135_R
DIFF_SSTL15, DIFF_SSTL15_R
DIFF_SSTL18_I, DIFF_SSTL18_II
LVDS_25
50
50
50
100
100
100
100
100
50
BLVDS (Bus LVDS), 2.5V
Mini LVDS, 2.5V
BLVDS_25
0(2)
0
MINI_LVDS_25
0(2)
0
PPDS_25
PPDS_25
0(2)
0
RSDS_25
RSDS_25
0(2)
0
TMDS_33
TMDS_33
0(2)
3.3
Notes:
1.
C
is the capacitance of the probe, nominally 0 pF.
REF
2. The value given is the differential output voltage.
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Input/Output Logic Switching Characteristics
Table 21: ILOGIC Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1Q/-1M
Setup/Hold
TICE1CK
TICKCE1
/
CE1 pin setup/hold with respect to
CLK
0.48/0.02 0.54/0.02 0.76/0.02 0.76/0.02 0.76/0.02 0.50/–0.07
0.60/0.01 0.70/0.01 1.13/0.01 1.13/0.01 1.13/0.01 0.88/–0.35
ns
ns
ns
ns
TISRCK
TICKSR
/
SR pin setup/hold with respect to
CLK
TIDOCK
/
D pin setup/hold with respect to CLK 0.01/0.27 0.01/0.29 0.01/0.33 0.01/0.33 0.01/0.33 0.01/0.33
without Delay
TIOCKD
TIDOCKD
TIOCKDD
/
DDLY pin setup/hold with respect to 0.02/0.27 0.02/0.29 0.02/0.33 0.02/0.33 0.02/0.33 0.01/0.33
CLK (using IDELAY)
Combinatorial
TIDI
D pin to O pin propagation delay, no
Delay
0.11
0.11
0.11
0.12
0.13
0.14
0.13
0.14
0.13
0.14
0.14
0.15
ns
ns
TIDID
DDLY pin to O pin propagation delay
(using IDELAY)
Sequential Delays
TIDLO
TIDLOD
TICKQ
D pin to Q1 pin using flip-flop as a
latch without Delay
0.41
0.41
0.44
0.44
0.51
0.51
0.51
0.51
0.51
0.51
0.54
0.55
ns
ns
DDLY pin to Q1 pin using flip-flop as
a latch (using IDELAY)
CLK to Q outputs
0.53
0.96
0.57
1.08
0.66
1.32
0.66
1.32
0.66
1.32
0.71
1.32
ns
ns
TRQ_
SR pin to OQ/TQ out
ILOGIC
TGSRQ_
Global set/reset to Q outputs
7.60
7.60
10.51
10.51
10.51
11.39
ns
ILOGIC
Set/Reset
TRPW_
Minimum pulse width, SR inputs
0.61
0.72
0.72
0.72
0.72
0.72
ns, Min
ILOGIC
Table 22: OLOGIC Switching Characteristics
Speed Grade
Symbol
Description
1.0V
-2/-2LE
0.95V
-1LI
0.9V
-2LE
Units
-3
-1
-1Q/-1M
Setup/Hold
TODCK
/
D1/D2 pins setup/hold with respect 0.67/–0.11 0.71/–0.11 0.84/–0.11 0.84/–0.06 0.84/–0.11 0.64/0.03
to CLK
ns
ns
TOCKD
TOOCECK
TOCKOCE
/
OCE pin setup/hold with respect to
CLK
0.32/0.58 0.34/0.58 0.51/0.58 0.51/0.58 0.51/0.58 0.28/0.01
TOSRCK
/
SR pin setup/hold with respect to
CLK
0.37/0.21 0.44/0.21 0.80/0.21 0.80/0.21 0.80/0.21 0.62/–0.25 ns
TOCKSR
TOTCK
TOCKT
/
T1/T2 pins setup/hold with respect to 0.69/–0.14 0.73/–0.14 0.89/–0.14 0.89/–0.11 0.89/–0.14 0.66/0.02
CLK
ns
ns
TOTCECK
TOCKTCE
/
TCE pin setup/hold with respect to
CLK
0.32/0.01 0.34/0.01 0.51/0.01 0.51/0.10 0.51/0.01 0.24/0.05
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 22: OLOGIC Switching Characteristics (Cont’d)
Speed Grade
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1Q/-1M
Combinatorial
TODQ
D1 to OQ out or T1 to TQ out
0.83
0.96
1.16
1.16
1.16
1.36
ns
Sequential Delays
TOCKQ
CLK to OQ/TQ out
SR pin to OQ/TQ out
0.47
0.72
7.60
0.49
0.80
7.60
0.56
0.95
0.56
0.95
0.56
0.95
0.63
1.12
ns
ns
ns
TRQ_OLOGIC
TGSRQ_OLOGIC Global set/reset to Q outputs
Set/Reset
10.51
10.51
10.51
11.39
TRPW_OLOGIC Minimum pulse width, SR inputs
0.64
0.74
0.74
0.74
0.74
0.74
ns,
Min
Input Serializer/Deserializer Switching Characteristics
Table 23: ISERDES Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1Q/-1M
Setup/Hold for Control Lines
TISCCK_BITSLIP
/
BITSLIP pin setup/hold with
respect to CLKDIV
0.01/0.14 0.02/0.15 0.02/0.17 0.02/0.17 0.02/0.17 0.02/0.21
ns
ns
ns
TISCKC_BITSLIP
TISCCK_CE
TISCKC_CE
/
CE pin setup/hold with respect to 0.45/–0.01 0.50/–0.01 0.72/–0.01 0.72/–0.01 0.72/–0.01 0.45/–0.11
CLK (for CE1)
(2)
TISCCK_CE2
/
CE pin setup/hold with respect to –0.10/0.33 –0.10/0.36 –0.10/0.40 –0.10/0.40 –0.10/0.40 –0.17/0.40
CLKDIV (for CE2)
(2)
TISCKC_CE2
Setup/Hold for Data Lines
TISDCK_D
/
D pin setup/hold with respect to –0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.02/0.17 –0.04/0.19
CLK
ns
ns
ns
ns
TISCKD_D
TISDCK_DDLY
TISCKD_DDLY
/
DDLYpin setup/holdwith respect –0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.02/0.17 –0.03/0.19
to CLK (using IDELAY)(1)
TISDCK_D_DDR
TISCKD_D_DDR
/
D pin setup/hold with respect to –0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.02/0.17 –0.04/0.19
CLK at DDR mode
TISDCK_DDLY_DDR
TISCKD_DDLY_DDR CLK at DDR mode (using
/
D pin setup/hold with respect to 0.12/0.12 0.14/0.14 0.17/0.17 0.17/0.17 0.17/0.17 0.19/0.19
IDELAY)(1)
Sequential Delays
TISCKO_Q
CLKDIV to out at Q pin
D input to DO output pin
0.53
0.11
0.54
0.11
0.66
0.13
0.66
0.13
0.66
0.13
0.67
0.14
ns
ns
Propagation Delays
TISDO_DO
Notes:
1. Recorded at 0 tap value.
2. and T
T
are reported as T
/T
in the timing report.
ISCCK_CE2
ISCKC_CE2
ISCCK_CE ISCKC_CE
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 24: OSERDES Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1Q/-1M
Setup/Hold
TOSDCK_D
TOSCKD_D
/
D input setup/hold with respect to
CLKDIV
0.42/0.03 0.45/0.03 0.63/0.03 0.63/0.08 0.63/0.03 0.44/–0.02 ns
TOSDCK_T
/
T input setup/hold with respect to 0.69/–0.13 0.73/–0.13 0.88/–0.13 0.88/–0.13 0.88/–0.13 0.66/–0.25 ns
CLK
(1)
TOSCKD_T
TOSDCK_T2
/
T input setup/hold with respect to 0.31/–0.13 0.34/–0.13 0.39/–0.13 0.39/–0.13 0.39/–0.13 0.46/–0.25 ns
CLKDIV
(1)
TOSCKD_T2
TOSCCK_OCE
TOSCKC_OCE
/
OCE input setup/hold with respect 0.32/0.58 0.34/0.58 0.51/0.58 0.51/0.58 0.51/0.58 0.28/–0.04 ns
to CLK
TOSCCK_S
SR (reset) input setup with respect
to CLKDIV
0.47
0.52
0.85
0.85
0.85
0.70
ns
TOSCCK_TCE
/
TCE input setup/hold with respect 0.32/0.01 0.34/0.01 0.51/0.01 0.51/0.10 0.51/0.01 0.24/0.00
to CLK
ns
TOSCKC_TCE
Sequential Delays
TOSCKO_OQ
TOSCKO_TQ
Combinatorial
TOSDO_TTQ
Clock to out from CLK to OQ
0.40
0.47
0.42
0.49
0.48
0.56
0.48
0.56
0.48
0.56
0.54
0.63
ns
ns
Clock to out from CLK to TQ
T input to TQ Out
0.83
0.92
1.11
1.11
1.11
1.18
ns
Notes:
1.
T
and T
are reported as T
/T
in the timing report.
OSDCK_T2
OSCKD_T2
OSDCK_T OSCKD_T
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25
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Input/Output Delay Switching Characteristics
Table 25: Input/Output Delay Switching Characteristics
Speed Grade
Symbol
Description
1.0V
-2/-2LE
0.95V
-1LI
0.9V
-2LE
Units
-3
-1
-1Q/-1M
IDELAYCTRL
TDLYCCO_RDY
FIDELAYCTRL_REF
Reset to ready for IDELAYCTRL
3.67
3.67
3.67
3.67
3.67
3.67
µs
Attribute REFCLK
200.00
200.00
200.00
200.00
200.00
200.00
MHz
frequency = 200.00(1)
Attribute REFCLK
300.00
400.00
300.00
400.00
300.00
N/A
300.00
N/A
300.00
N/A
300.00
N/A
MHz
MHz
frequency = 300.00(1)
Attribute REFCLK
frequency = 400.00(1)
IDELAYCTRL_REF_
PRECISION
REFCLK precision
10
10
10
10
10
10
MHz
ns
TIDELAYCTRL_RPW
IDELAY
Minimum Reset pulse width
59.28
59.28
59.28
59.28
59.28
59.28
TIDELAYRESOLUTION
IDELAY chain delay resolution
1/(32 x 2 x FREF
)
µs
Pattern dependent period jitter in
delay chain for clock pattern.(2)
0
5
0
5
0
0
0
5
0
5
ps
per tap
Pattern dependent period jitter in
delay chain for random data
pattern (PRBS 23)(3)
5
5
ps
per tap
TIDELAYPAT_JIT
Pattern dependent period jitter in
delay chain for random data
pattern (PRBS 23)(4)
9
9
9
9
9
9
ps
per tap
TIDELAY_CLK_MAX
Maximum frequency of CLK input
to IDELAY
680.00
680.00
600.00
600.00
600.00
520.00
MHz
ns
TIDCCK_CE
TIDCKC_CE
/
CE pin setup/hold with respect to 0.12/0.11 0.16/0.13 0.21/0.16 0.21/0.16 0.21/0.16 0.14/0.16
C for IDELAY
TIDCCK_INC
TIDCKC_INC
/
INC pin setup/hold with respect to 0.12/0.16 0.14/0.18 0.16/0.22 0.16/0.23 0.16/0.22 0.10/0.23
C for IDELAY
ns
TIDCCK_RST
/
RST pin setup/hold with respect 0.15/0.09 0.16/0.11 0.18/0.14 0.18/0.14 0.18/0.14 0.22/0.19
to C for IDELAY
ns
TIDCKC_RST
TIDDO_IDATAIN
Propagation delay through
IDELAY
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
ps
Notes:
1. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.
2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
3. When HIGH_PERFORMANCE mode is set to TRUE.
4. When HIGH_PERFORMANCE mode is set to FALSE.
5. Delay depends on IDELAY tap setting. See the timing report for actual values.
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Product Specification
26
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Speed Grade
Table 26: IO_FIFO Switching Characteristics
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1Q/-1M
IO_FIFO Clock to Out Delays
TOFFCKO_DO
TCKO_FLAGS
Setup/Hold
RDCLK to Q outputs
0.55
0.55
0.60
0.61
0.68
0.77
0.68
0.77
0.68
0.77
0.81
0.79
ns
ns
Clock to IO_FIFO flags
T
CCK_D/TCKC_D
D inputs to WRCLK
WREN to WRCLK
0.47/0.02 0.51/0.02 0.58/0.02 0.58/0.18 0.58/0.02 0.76/0.09
0.42/–0.01 0.47/–0.01 0.53/–0.01 0.53/–0.01 0.53/–0.01 0.70/–0.05
ns
ns
TIFFCCK_WREN
TIFFCKC_WREN
/
TOFFCCK_RDEN
/
RDEN to RDCLK
0.53/0.02 0.58/0.02 0.66/0.02 0.66/0.02 0.66/0.02 0.79/–0.02
ns
TOFFCKC_RDEN
Minimum Pulse Width
TPWH_IO_FIFO RESET, RDCLK, WRCLK
TPWL_IO_FIFO RESET, RDCLK, WRCLK
Maximum Frequency
1.62
1.62
2.15
2.15
2.15
2.15
2.15
2.15
2.15
2.15
2.15
2.15
ns
ns
FMAX
RDCLK and WRCLK
266.67
200.00
200.00
200.00
200.00
200.00
MHz
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
CLB Switching Characteristics
Table 27: CLB Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1Q/-1M
Combinatorial Delays
TILO
An – Dn LUT address to A
0.10
0.27
0.11
0.30
0.13
0.36
0.13
0.36
0.13
0.36
0.15
0.41
ns, Max
ns, Max
TILO_2
An – Dn LUT address to
AMUX/CMUX
TILO_3
TITO
An – Dn LUT address to BMUX_A
An – Dn inputs to A – D Q outputs
AX inputs to AMUX output
AX inputs to BMUX output
AX inputs to CMUX output
AX inputs to DMUX output
BX inputs to BMUX output
BX inputs to DMUX output
CX inputs to CMUX output
CX inputs to DMUX output
DX inputs to DMUX output
0.42
0.94
0.62
0.58
0.60
0.68
0.51
0.62
0.42
0.53
0.52
0.46
1.05
0.69
0.66
0.68
0.75
0.57
0.69
0.48
0.59
0.58
0.55
1.27
0.84
0.83
0.82
0.90
0.69
0.82
0.58
0.71
0.70
0.55
1.27
0.84
0.83
0.82
0.90
0.69
0.82
0.58
0.71
0.70
0.55
1.27
0.84
0.83
0.82
0.90
0.69
0.82
0.58
0.71
0.70
0.65
1.51
1.01
0.98
0.98
1.08
0.82
0.99
0.69
0.86
0.84
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
TAXA
TAXB
TAXC
TAXD
TBXB
TBXD
TCXC
TCXD
TDXD
Sequential Delays
TCKO
Clock to AQ – DQ outputs
Clock to AMUX – DMUX outputs
0.40
0.47
0.44
0.53
0.53
0.66
0.53
0.66
0.53
0.66
0.62
0.73
ns, Max
ns, Max
TSHCKO
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
AN – DN input to CLK on A – D
flip-flops
0.07/0.12 0.09/0.14 0.11/0.18 0.11/0.28 0.11/0.18
T
AS/TAH
0.11/0.22 ns, Min
0.09/0.33 ns, Min
0.97/0.15 ns, Min
AX – DX input to CLK on A – D
flip-flops
0.06/0.19 0.07/0.21 0.09/0.26 0.09/0.35 0.09/0.26
TDICK
TCKDI
/
AX – DX input through MUXs and/or 0.59/0.08 0.66/0.09 0.81/0.11 0.81/0.20 0.81/0.11
carry logic to CLK on A – D
flip-flops
CE input to CLK on A – D flip-flops 0.15/0.00 0.17/0.00 0.21/0.01 0.21/0.13 0.21/0.01
TCECK_CLB
/
0.34/–0.01 ns, Min
0.62/0.19 ns, Min
TCKCE_CLB
SR input to CLK on A – D flip-flops 0.38/0.03 0.43/0.04 0.53/0.05 0.53/0.18 0.53/0.05
TSRCK
/
TCKSR
Set/Reset
TSRMIN
TRQ
SR input minimum pulse width
0.52
0.53
0.78
0.59
1.04
0.71
1.04
0.71
1.04
0.71
0.95
0.83
ns, Min
ns, Max
Delay from SR input to AQ – DQ
flip-flops
TCEO
FTOG
Delay from CE input to AQ – DQ
flip-flops
0.52
0.58
0.70
0.70
0.70
0.83
ns, Max
MHz
Toggle frequency (for export
control)
1412
1286
1098
1098
1098
1098
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28
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 28: CLB Distributed RAM Switching Characteristics
Speed Grade
Symbol
Description
1.0V
-2/-2LE
0.95V
-1LI
0.9V
-2LE
Units
-3
-1
-1Q/-1M
Sequential Delays
TSHCKO
Clock to A – B outputs
0.98
1.37
1.09
1.53
1.32
1.86
1.32
1.86
1.32
1.86
1.54
2.18
ns, Max
ns, Max
TSHCKO_1
Clock to AMUX – BMUX outputs
Setup and Hold Times Before/After Clock CLK
TDS_LRAM
/
A – D inputs to CLK
0.54/0.28 0.60/0.30 0.72/0.35 0.72/0.37 0.72/0.35 0.96/0.40 ns, Min
TDH_LRAM
TAS_LRAM
/
Address An inputs to clock
0.27/0.55 0.30/0.60 0.37/0.70 0.37/0.71 0.37/0.70 0.43/0.71 ns, Min
0.69/0.18 0.77/0.21 0.94/0.26 0.94/0.35 0.94/0.26 1.11/0.31 ns, Min
TAH_LRAM
Address An inputs through MUXs
and/or carry logic to clock
TWS_LRAM
/
WE input to clock
0.38/0.10 0.43/0.12 0.53/0.17 0.53/0.17 0.53/0.17 0.62/0.13 ns, Min
0.39/0.10 0.44/0.11 0.53/0.17 0.53/0.17 0.53/0.17 0.63/0.12 ns, Min
TWH_LRAM
TCECK_LRAM
TCKCE_LRAM
/
CE input to CLK
Clock CLK
TMPW_LRAM
TMCP
Minimum pulse width
Minimum clock period
1.05
2.10
1.13
2.26
1.25
2.50
1.25
2.50
1.25
2.50
1.61
3.21
ns, Min
ns, Min
Notes:
1.
T
also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.
SHCKO
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 29: CLB Shift Register Switching Characteristics
Speed Grade
Symbol
Description
1.0V
-2/-2LE
0.95V
-1LI
0.9V
-2LE
Units
-3
-1
-1Q/-1M
Sequential Delays
TREG
Clock to A – D outputs
1.19
1.58
1.12
1.33
1.77
1.23
1.61
2.15
1.46
1.61
2.15
1.46
1.61
2.15
1.46
1.89
2.53
1.68
ns, Max
ns, Max
ns, Max
TREG_MUX
TREG_M31
Clock to AMUX – DMUX output
Clock to DMUX output via M31
output
Setup and Hold Times Before/After Clock CLK
0.37/0.10 0.41/0.12 0.51/0.17 0.51/0.17 0.51/0.17
0.37/0.10 0.42/0.11 0.52/0.17 0.52/0.17 0.52/0.17
0.33/0.34 0.37/0.37 0.44/0.43 0.44/0.44 0.44/0.43
TWS_SHFREG
/
WE input
0.59/0.13 ns, Min
0.60/0.12 ns, Min
0.54/0.55 ns, Min
TWH_SHFREG
TCECK_SHFREG
TCKCE_SHFREG
/
CE input to CLK
A – D inputs to CLK
TDS_SHFREG
/
TDH_SHFREG
Clock CLK
TMPW_SHFREG
Minimum pulse width
0.77
0.86
0.98
0.98
0.98
1.22
ns, Min
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29
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 30: Block RAM and FIFO Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1Q/-1M
Block RAM and FIFO Clock-to-Out Delays
TRCKO_DO and
TRCKO_DO_REG
Clock CLK to DOUT
output (without output
register)(2)(3)
1.85
2.13
2.46
2.46
0.89
3.84
0.94
3.30
1.46
2.46
0.89
3.84
0.94
3.30
1.46
2.87
1.02
5.30
1.11
3.76
1.56
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
(1)
Clock CLK to DOUT
output (with output
register)(4)(5)
0.64
2.77
0.73
2.61
1.16
0.74
3.04
0.81
2.88
1.28
0.89
3.84
0.94
3.30
1.46
TRCKO_DO_ECC and
TRCKO_DO_ECC_REG
Clock CLK to DOUT
output with ECC (without
output register)(2)(3)
Clock CLK to DOUT
output with ECC (with
output register)(4)(5)
TRCKO_DO_CASCOUT and Clock CLK to DOUT
output with cascade
TRCKO_DO_CASCOUT_REG
(without output register)(2)
Clock CLK to DOUT
output with cascade (with
output register)(4)
TRCKO_FLAGS
Clock CLK to FIFO flags
outputs(6)
0.76
0.94
0.78
2.56
0.68
0.75
0.87
1.02
0.85
2.81
0.76
0.88
1.05
1.15
0.94
3.55
0.89
1.07
1.05
1.15
0.94
3.55
0.89
1.07
1.05
1.15
0.94
3.55
0.89
1.07
1.14
1.30
1.10
4.90
1.05
1.15
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
TRCKO_POINTERS
TRCKO_PARITY_ECC
Clock CLK to FIFO
pointers outputs(7)
ClockCLKtoECCPARITY
in ECC encode only mode
TRCKO_SDBIT_ECC and
TRCKO_SDBIT_ECC_REG
Clock CLK to BITERR
(without output register)
Clock CLK to BITERR
(with output register)
TRCKO_RDADDR_ECC and Clock CLK to RDADDR
TRCKO_RDADDR_ECC_REG output with ECC (without
output register)
Clock CLK to RDADDR
output with ECC (with
output register)
0.84
0.93
1.08
1.08
1.08
1.29
ns, Max
Setup and Hold Times Before/After Clock CLK
TRCCK_ADDRA
/
ADDR inputs(8)
0.45/0.31 0.49/0.33 0.57/0.36 0.57/0.52 0.57/0.36 0.77/0.45 ns, Min
TRCKC_ADDRA
TRDCK_DI_WF_NC
TRCKD_DI_WF_NC
/
Data input setup/hold time 0.58/0.60 0.65/0.63 0.74/0.67 0.74/0.67 0.74/0.67 0.92/0.76 ns, Min
when block RAM is
configured in
WRITE_FIRST or
NO_CHANGE mode(9)
TRDCK_DI_RF
/
Data input setup/hold time 0.20/0.29 0.22/0.34 0.25/0.41 0.25/0.50 0.25/0.41 0.29/0.38 ns, Min
TRCKD_DI_RF
when block RAM is
configured in
READ_FIRST mode(9)
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30
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 30: Block RAM and FIFO Switching Characteristics (Cont’d)
Speed Grade
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1Q/-1M
TRDCK_DI_ECC
TRCKD_DI_ECC
/
DIN inputs with block RAM 0.50/0.43 0.55/0.46 0.63/0.50 0.63/0.50 0.63/0.50 0.78/0.54 ns, Min
ECC in standard mode(9)
TRDCK_DI_ECCW
/
DIN inputs with block RAM 0.93/0.43 1.02/0.46 1.17/0.50 1.17/0.50 1.17/0.50 1.38/0.48 ns, Min
ECC encode only(9)
TRCKD_DI_ECCW
TRDCK_DI_ECC_FIFO
/
DIN inputs with FIFO ECC 1.04/0.56 1.15/0.59 1.32/0.64 1.32/0.64 1.32/0.64 1.55/0.77 ns, Min
in standard mode(9)
TRCKD_DI_ECC_FIFO
TRCCK_INJECTBITERR
TRCKC_INJECTBITERR
/
Inject single/double bit
error in ECC mode
0.58/0.35 0.64/0.37 0.74/0.40 0.74/0.52 0.74/0.40 0.92/0.48 ns, Min
TRCCK_EN/TRCKC_EN
Block RAM enable (EN)
input
0.35/0.20 0.39/0.21 0.45/0.23 0.45/0.41 0.45/0.23 0.57/0.26 ns, Min
TRCCK_REGCE
/
CE input of output register 0.24/0.15 0.29/0.15 0.36/0.16 0.36/0.39 0.36/0.16 0.40/0.19 ns, Min
TRCKC_REGCE
TRCCK_RSTREG
TRCKC_RSTREG
/
Synchronous RSTREG
input
0.29/0.07 0.32/0.07 0.35/0.07 0.35/0.17 0.35/0.07 0.41/0.07 ns, Min
0.32/0.42 0.34/0.43 0.36/0.46 0.36/0.57 0.36/0.46 0.40/0.47 ns, Min
0.44/0.18 0.48/0.19 0.54/0.20 0.54/0.42 0.54/0.20 0.64/0.23 ns, Min
0.46/0.30 0.46/0.35 0.47/0.43 0.47/0.43 0.47/0.43 0.77/0.44 ns, Min
0.42/0.30 0.43/0.35 0.43/0.43 0.43/0.62 0.43/0.43 0.71/0.50 ns, Min
TRCCK_RSTRAM
TRCKC_RSTRAM
/
Synchronous RSTRAM
input
TRCCK_WEA
/
Write enable (WE) input
(block RAM only)
TRCKC_WEA
TRCCK_WREN
/
WREN FIFO inputs
TRCKC_WREN
TRCCK_RDEN
TRCKC_RDEN
/
RDEN FIFO inputs
Reset Delays
TRCO_FLAGS
Reset RST to FIFO
flags/pointers(10)
0.90
0.98
1.10
1.10
1.10
1.25
ns, Max
TRREC_RST
/
FIFO reset recovery and 1.87/–0.81 2.07/–0.81 2.37/–0.81 2.37/–0.58 2.37/–0.81 2.44/–0.71 ns, Max
removal timing(11)
TRREM_RST
Maximum Frequency
FMAX_BRAM_WF_NC
Block RAM (write first and
no change modes) when
not in SDP RF mode
509.68
509.68
460.83
460.83
388.20
388.20
388.20
388.20
388.20
388.20
315.66
315.66
MHz
MHz
FMAX_BRAM_RF_
PERFORMANCE
Block RAM (read first,
performance mode) when
in SDP RF mode but no
address overlap between
port A and port B
FMAX_BRAM_RF_
DELAYED_WRITE
Block RAM (read first,
delayed write mode) when
in SDP RF mode and
there is possibility of
447.63
404.53
339.67
339.67
339.67
268.96
MHz
overlap between port A
and port B addresses
DS181 (v1.25) June 18, 2018
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Product Specification
31
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 30: Block RAM and FIFO Switching Characteristics (Cont’d)
Speed Grade
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1Q/-1M
FMAX_CAS_WF_NC
Block RAM cascade (write
first, no change mode)
when cascade but not in
RF mode
467.07
418.59
345.78
345.78
345.78
273.30
MHz
FMAX_CAS_RF_
PERFORMANCE
Block RAM cascade (read
first, performance mode)
when in cascade with RF
mode and no possibility of
address overlap/one port
is disabled
467.07
405.35
418.59
362.19
345.78
297.35
345.78
345.78
297.35
273.30
226.60
MHz
MHz
FMAX_CAS_RF_
DELAYED_WRITE
When in cascade RF
mode and there is a
possibility of address
overlap between port A
and port B
297.35
FMAX_FIFO
FMAX_ECC
FIFO in all modes without
ECC
509.68
410.34
460.83
365.10
388.20
297.53
388.20
297.53
388.20
297.53
315.66
215.38
MHz
MHz
Block RAM and FIFO in
ECC configuration
Notes:
1. The timing report shows all of these parameters as T
.
RCKO_DO
2.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. includes T as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
T
includes T
, T
, and T
as well as the B port equivalent timing parameters.
RCKO_DOR
RCKO_DOW RCKO_DOPR
RCKO_DOPW
T
RCKO_DO
RCKO_DOP
6.
7.
T
T
includes the following parameters: T
, T , T , T , T , T
RCKO_FLAGS
RCKO_AEMPTY RCKO_AFULL RCKO_EMPTY RCKO_FULL RCKO_RDERR RCKO_WRERR.
includes both T
and T
RCKO_POINTERS
RCKO_RDCOUNT
RCKO_WRCOUNT.
8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible.
9. These parameters include both A and B inputs as well as the parity inputs of A and B.
10. T
includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
RCO_FLAGS
11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the
slowest clock (WRCLK or RDCLK).
DS181 (v1.25) June 18, 2018
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Product Specification
32
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DSP48E1 Switching Characteristics
Table 31: DSP48E1 Switching Characteristics
Speed Grade
1.0V
-2/-2LE
Symbol
Description
0.95V 0.9V Units
-3
Setup and Hold Times of Data/Control Pins to the Input Register Clock
-1
-1Q/-1M -1LI
-2LE
TDSPDCK_A_AREG
/
A input to A register CLK
B input to B register CLK
C input to C register CLK
D input to D register CLK
ACIN input to A register CLK
BCIN input to B register CLK
0.26/
0.12
0.30/
0.13
0.37/
0.14
0.37/
0.28
0.37/
0.14
0.45/
0.14
ns
ns
ns
ns
ns
ns
TDSPCKD_A_AREG
TDSPDCK_B_BREG
TDSPCKD_B_BREG
/
0.33/
0.15
0.38/
0.16
0.45/
0.18
0.45/
0.25
0.45/
0.18
0.60/
0.19
TDSPDCK_C_CREG
TDSPCKD_C_CREG
/
/
0.17/
0.17
0.20/
0.19
0.24/
0.21
0.24/
0.26
0.24/
0.21
0.34/
0.29
TDSPDCK_D_DREG
TDSPCKD_D_DREG
0.25/
0.25
0.32/
0.27
0.42/
0.27
0.42/
0.42
0.42/
0.27
0.54/
0.23
TDSPDCK_ACIN_AREG
TDSPCKD_ACIN_AREG
/
/
0.23/
0.12
0.27/
0.13
0.32/
0.14
0.32/
0.17
0.32/
0.14
0.36/
0.14
TDSPDCK_BCIN_BREG
TDSPCKD_BCIN_BREG
0.25/
0.15
0.29/
0.16
0.36/
0.18
0.36/
0.18
0.36/
0.18
0.41/
0.19
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_ A, B _MREG_MULT
/
{A, B} input to M register CLK
using multiplier
2.40/
–0.01
2.76/
–0.01
3.29/
–0.01
3.29/
–0.01
3.29/
–0.01 –0.07
4.31/
ns
ns
{
}
TDSPCKD_{A, B}_MREG_MULT
TDSPDCK_ A, D _ADREG
/
{A, D} input to AD register CLK
1.29/
–0.02
1.48/
–0.02
1.76/
–0.02
1.76/
–0.02
1.76/ 2.29/
–0.02 –0.27
{
}
TDSPCKD_{A, D}_ADREG
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{A, B}_PREG_MULT
/
{A, B} input to P register CLK
using multiplier
4.02/
–0.28
4.60/
–0.28
5.48/
–0.28
5.48/
–0.28
5.48/
–0.28 –0.48
6.95/
ns
ns
ns
ns
ns
TDSPCKD_{A, B} _PREG_MULT
TDSPDCK_D_PREG_MULT
TDSPCKD_D_PREG_MULT
/
D input to P register CLK using
multiplier
3.93/
–0.73
4.50/
–0.73
5.35/
–0.73
5.35/
–0.73
5.35/ 6.73/
–0.73 –1.68
TDSPDCK_{A, B} _PREG
/
A or B input to P register CLK
not using multiplier
1.73/
–0.28
1.98/
–0.28
2.35/
–0.28
2.35/
–0.28
2.35/ 2.80/
TDSPCKD_{A, B} _PREG
–0.28 –0.48
2.10/ 2.54/
TDSPDCK_C_PREG
TDSPCKD_C_PREG
/
C input to P register CLK not
using multiplier
1.54/
–0.26
1.76/
–0.26
2.10/
–0.26
2.10/
–0.26
–0.26 –0.45
TDSPDCK_PCIN_PREG
/
PCIN input to P register CLK
1.32/
–0.15
1.51/
–0.15
1.80/
–0.15
1.80/
–0.15
1.80/ 2.13/
–0.15 –0.25
TDSPCKD_PCIN_PREG
Setup and Hold Times of the CE Pins
TDSPDCK_{CEA;CEB}_{AREG;BREG}
/
{CEA; CEB} input to {A; B}
register CLK
0.35/
0.06
0.42/
0.08
0.52/
0.11
0.52/
0.11
0.52/
0.11
0.64/
0.11
ns
ns
ns
ns
ns
TDSPCKD_{CEA;CEB}_{AREG;BREG}
TDSPDCK_CEC_CREG
/
/
CEC input to C register CLK
CED input to D register CLK
CEM input to M register CLK
CEP input to P register CLK
0.28/
0.10
0.34/
0.11
0.42/
0.13
0.42/
0.13
0.42/
0.13
0.49/
0.16
TDSPCKD_CEC_CREG
TDSPDCK_CED_DREG
TDSPCKD_CED_DREG
0.36/
–0.03
0.43/
–0.03
0.52/
–0.03
0.52/
–0.03
0.52/
–0.03
0.68/
0.14
TDSPDCK_CEM_MREG
TDSPCKD_CEM_MREG
/
0.17/
0.18
0.21/
0.20
0.27/
0.23
0.27/
0.23
0.27/
0.23
0.45/
0.29
TDSPDCK_CEP_PREG
/
0.36/
0.01
0.43/
0.01
0.53/
0.01
0.53/
0.01
0.53/
0.01
0.63/
0.00
TDSPCKD_CEP_PREG
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33
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 31: DSP48E1 Switching Characteristics (Cont’d)
Speed Grade
1.0V
Symbol
Description
0.95V 0.9V Units
-3
-2/-2LE
-1
-1Q/-1M -1LI
-2LE
Setup and Hold Times of the RST Pins
TDSPDCK_{RSTA; RSTB}_{AREG; BREG}
/
{RSTA, RSTB} input to {A, B}
register CLK
0.41/
0.11
0.46/
0.13
0.55/
0.15
0.55/
0.24
0.55/
0.15
0.63/
0.40
ns
ns
ns
ns
ns
TDSPCKD_{RSTA; RSTB}_{AREG; BREG}
TDSPDCK_RSTC_CREG
/
/
RSTC input to C register CLK
RSTD input to D register CLK
RSTM input to M register CLK
RSTP input to P register CLK
0.07/
0.10
0.08/
0.11
0.09/
0.12
0.09/
0.25
0.09/
0.12
0.13/
0.11
TDSPCKD_RSTC_CREG
TDSPDCK_RSTD_DREG
TDSPCKD_RSTD_DREG
0.44/
0.07
0.50/
0.08
0.59/
0.09
0.59/
0.09
0.59/
0.09
0.67/
0.08
TDSPDCK_RSTM_MREG
/
0.21/
0.22
0.23/
0.24
0.27/
0.28
0.27/
0.28
0.27/
0.28
0.28/
0.35
TDSPCKD_RSTM_MREG
TDSPDCK_RSTP_PREG
/
0.27/
0.01
0.30/
0.01
0.35/
0.01
0.35/
0.03
0.35/
0.01
0.43/
0.00
TDSPCKD_RSTP_PREG
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_A_CARRYOUT_MULT
TDSPDO_D_P_MULT
TDSPDO_B_P
A input to CARRYOUT output
using multiplier
3.79
3.72
1.53
1.33
4.35
4.26
1.75
1.53
5.18
5.07
2.08
1.82
5.18
5.07
2.08
1.82
5.18
5.07
2.08
1.82
6.61
6.41
2.48
2.22
ns
ns
ns
ns
D input to P output using
multiplier
B input to P output not using
multiplier
TDSPDO_C_P
C input to P output
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{A; B}_{ACOUT; BCOUT}
{A, B}inputto{ACOUT, BCOUT} 0.55
output
0.63
4.65
0.74
5.54
0.74
5.54
0.74
5.54
0.87
7.03
ns
ns
TDSPDO_{A, B}_CARRYCASCOUT_MULT {A, B} input to
CARRYCASCOUT output using
4.06
multiplier
TDSPDO_D_CARRYCASCOUT_MULT
TDSPDO_{A, B}_CARRYCASCOUT
D input to CARRYCASCOUT
output using multiplier
3.97
1.77
4.54
2.03
5.40
2.41
5.40
2.41
5.40
2.41
6.81
2.88
ns
ns
{A, B} input to
CARRYCASCOUT output not
using multiplier
TDSPDO_C_CARRYCASCOUT
C input to CARRYCASCOUT
output
1.58
1.81
2.15
2.15
2.15
2.62
ns
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_ACIN_P_MULT
ACIN input to P output using
multiplier
3.65
1.37
4.19
1.57
5.00
1.88
5.00
1.88
5.00
1.88
6.40
2.44
ns
ns
TDSPDO_ACIN_P
ACIN input to P output not using
multiplier
TDSPDO_ACIN_ACOUT
ACIN input to ACOUT output
0.38
3.90
0.44
4.47
0.53
5.33
0.53
5.33
0.53
5.33
0.63
6.79
ns
ns
TDSPDO_ACIN_CARRYCASCOUT_MULT
ACIN input to
CARRYCASCOUT output using
multiplier
TDSPDO_ACIN_CARRYCASCOUT
ACIN input to
CARRYCASCOUT output not
using multiplier
1.61
1.85
2.21
2.21
2.21
2.84
ns
TDSPDO_PCIN_P
PCIN input to P output
1.11
1.36
1.28
1.56
1.52
1.85
1.52
1.85
1.52
1.85
1.82
2.21
ns
ns
TDSPDO_PCIN_CARRYCASCOUT
PCIN input to
CARRYCASCOUT output
DS181 (v1.25) June 18, 2018
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Product Specification
34
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 31: DSP48E1 Switching Characteristics (Cont’d)
Speed Grade
1.0V
Symbol
Description
0.95V 0.9V Units
-3
-2/-2LE
-1
-1Q/-1M -1LI
-2LE
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_P_PREG
CLK PREG to P output
0.33
0.52
0.37
0.59
0.44
0.69
0.44
0.69
0.44
0.69
0.54
0.84
ns
ns
TDSPCKO_CARRYCASCOUT_PREG
CLK PREG to
CARRYCASCOUT output
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_P_MREG
CLK MREG to P output
1.68
1.92
1.93
2.21
2.31
2.64
2.31
2.64
2.31
2.64
2.73
3.12
ns
ns
TDSPCKO_CARRYCASCOUT_MREG
CLK MREG to
CARRYCASCOUT output
TDSPCKO_P_ADREG_MULT
CLK ADREG to P output using
multiplier
2.72
2.96
3.10
3.38
3.69
4.02
3.69
4.02
3.69
4.02
4.60
4.99
ns
ns
TDSPCKO_CARRYCASCOUT_ADREG_
CLK ADREG to
CARRYCASCOUT output using
multiplier
MULT
Clock to Outs from Input Register Clock to Output Pins
CLK AREG to P output using
TDSPCKO_P_AREG_MULT
3.94
1.64
1.69
3.91
4.51
1.87
1.93
4.48
5.37
2.22
2.30
5.32
5.37
2.22
2.30
5.32
5.37
2.22
2.30
5.32
6.84
2.65
2.81
6.77
ns
ns
ns
ns
multiplier
TDSPCKO_P_BREG
CLK BREG to P output not using
multiplier
TDSPCKO_P_CREG
CLK CREG to P output not
using multiplier
TDSPCKO_P_DREG_MULT
CLK DREG to P output using
multiplier
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUT; BCOUT}_{AREG;
BREG}
CLK (ACOUT, BCOUT) to {A,B}
register output
0.64
4.19
0.73
4.79
0.87
5.70
0.87
5.70
0.87
5.70
1.02
7.24
ns
ns
TDSPCKO_CARRYCASCOUT_{AREG,
BREG}_MULT
CLK (AREG, BREG) to
CARRYCASCOUT output using
multiplier
TDSPCKO_CARRYCASCOUT_ BREG
CLK BREG to
CARRYCASCOUT output not
using multiplier
1.88
4.16
1.94
2.15
4.76
2.21
2.55
5.65
2.63
2.55
5.65
2.63
2.55
5.65
2.63
3.04
7.17
3.20
ns
ns
ns
TDSPCKO_CARRYCASCOUT_
DREG_MULT
CLK DREG to
CARRYCASCOUT output using
multiplier
TDSPCKO_CARRYCASCOUT_ CREG
CLK CREG to
CARRYCASCOUT output
Maximum Frequency
FMAX
With all registers used
With pattern detector
628.93 550.66 464.25 464.25 464.25 363.77 MHz
531.63 465.77 392.93 392.93 392.93 310.08 MHz
349.28 305.62 257.47 257.47 257.47 210.44 MHz
FMAX_PATDET
FMAX_MULT_NOMREG
Two register multiply without
MREG
FMAX_MULT_NOMREG_PATDET
Two register multiply without
MREG with pattern detect
317.26 277.62 233.92 233.92 233.92 191.28 MHz
FMAX_PREADD_MULT_NOADREG
Without ADREG
397.30 346.26 290.44 290.44 290.44 223.26 MHz
397.30 346.26 290.44 290.44 290.44 223.26 MHz
FMAX_PREADD_MULT_NOADREG_
PATDET
Without ADREG with pattern
detect
DS181 (v1.25) June 18, 2018
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Product Specification
35
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 31: DSP48E1 Switching Characteristics (Cont’d)
Speed Grade
1.0V
-2/-2LE
Symbol
Description
0.95V 0.9V Units
-1Q/-1M -1LI -2LE
-3
-1
FMAX_NOPIPELINEREG
Without pipeline registers
(MREG, ADREG)
260.01 227.01 190.69 190.69 190.69 150.13 MHz
FMAX_NOPIPELINEREG_PATDET
Without pipeline registers
(MREG, ADREG) with pattern
detect
241.72 211.15 177.43 177.43 177.43 140.10 MHz
Clock Buffers and Networks
Table 32: Global Clock Switching Characteristics (Including BUFGCTRL)
Speed Grade
Symbol
Description
1.0V
-2/-2LE
0.95V
-1LI
0.9V
-2LE
Units
-3
-1
-1Q/-1M
TBCCCK_CE
/
CE pins setup/hold
0.12/0.39 0.13/0.40 0.16/0.41 0.16/0.83 0.16/0.41 0.31/0.67
ns
ns
ns
(1)
TBCCKC_CE
TBCCCK_S
/
S pins setup/hold
0.12/0.39 0.13/0.40 0.16/0.41 0.16/0.83 0.16/0.41 0.31/0.67
(1)
TBCCKC_S
(2)
TBCCKO_O
BUFGCTRL delay from I0/I1 to O
0.08
0.09
0.10
0.10
0.10
0.14
Maximum Frequency
FMAX_BUFG
Global clock tree (BUFG)
628.00
628.00
464.00
464.00
464.00
394.00
MHz
Notes:
1.
T
and T
must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
BCCCK_CE
BCCKC_CE
parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are
optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
2.
T
(BUFG delay from I0 to O) values are the same as T
values.
BGCKO_O
BCCKO_O
Table 33: Input/Output Clock Switching Characteristics (BUFIO)
Speed Grade
Symbol
Description
1.0V
-2/-2LE
0.95V
-1LI
0.9V
-2LE
1.56
Units
ns
-3
-1
-1Q/-1M
TBIOCKO_O
Clock to out delay from I to O
1.11
1.26
1.54
1.54
1.54
Maximum Frequency
FMAX_BUFIO I/O clock tree (BUFIO)
680.00
680.00
600.00
600.00
600.00
600.00
MHz
Table 34: Regional Clock Buffer Switching Characteristics (BUFR)
Speed Grade
Symbol
Description
1.0V
-2/-2LE
0.95V
-1LI
0.9V
-2LE
1.24
0.72
Units
-3
-1
-1Q/-1M
TBRCKO_O
TBRCKO_O_BYP
TBRDO_O
Clock to out delay from I to O
0.64
0.34
0.76
0.39
0.99
0.52
0.99
0.52
0.99
0.52
ns
ns
Clock to out delay from I to O with
Divide Bypass attribute set
Propagation delay from CLR to O
0.81
0.85
1.09
1.09
1.09
0.96
ns
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Product Specification
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 34: Regional Clock Buffer Switching Characteristics (BUFR) (Cont’d)
Speed Grade
Symbol
Description
1.0V
-2/-2LE
0.95V
-1LI
0.9V
-2LE
Units
-3
-1
-1Q/-1M
Maximum Frequency
(1)
FMAX_BUFR
Regional clock tree (BUFR)
420.00
375.00
315.00
315.00
315.00
315.00
MHz
Notes:
1. The maximum input frequency to the BUFR and BUFMR is the BUFIO F
frequency.
MAX
Table 35: Horizontal Clock Buffer Switching Characteristics (BUFH)
Speed Grade
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
0.16
Units
-3
-2/-2LE
-1
-1Q/-1M
TBHCKO_O
TBHCCK_CE
BUFH delay from I to O
CE pin setup and hold
0.10
0.11
0.13
0.13
0.13
ns
ns
/
0.19/0.13 0.22/0.15 0.28/0.21 0.28/0.42 0.28/0.21 0.35/0.25
TBHCKC_CE
Maximum Frequency
FMAX_BUFH Horizontal clock buffer (BUFH)
628.00
628.00
464.00
464.00
464.00
394.00
MHz
Table 36: Duty Cycle Distortion and Clock-Tree Skew
Speed Grade
Symbol
Description
Device
1.0V
-2/-2LE
0.95V
0.9V
-2LE
0.25
Units
-3
-1
-1Q/-1M
-1LI
TDCD_CLK
TCKSKEW
Global clock tree duty-cycle
distortion(1)
All
0.20
0.20
0.20
N/A
0.20
ns
Global clock tree skew(2)
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
0.26
0.26
0.26
0.26
0.26
0.27
0.27
0.40
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.14
0.26
0.26
0.26
0.26
0.26
0.33
0.33
0.48
0.26
0.26
0.26
0.26
0.26
0.33
0.33
0.26
0.33
0.48
0.14
0.26
0.26
0.26
0.26
0.26
0.36
0.36
0.54
0.26
0.26
0.26
0.26
0.26
0.36
0.36
0.26
0.36
0.54
0.14
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.26
0.26
0.26
0.26
0.26
0.36
0.36
0.26
0.36
0.54
0.14
0.26
0.26
0.26
0.26
0.26
0.36
0.36
0.54
N/A
0.33
0.33
0.33
0.33
0.33
0.48
0.48
0.69
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.14
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
N/A
N/A
N/A
N/A
N/A
N/A
0.26
0.36
0.54
0.14
TDCD_BUFIO I/O clock tree duty cycle distortion All
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 36: Duty Cycle Distortion and Clock-Tree Skew (Cont’d)
Speed Grade
Symbol
Description
Device
1.0V
-2/-2LE
0.95V
-1LI
0.9V
-2LE
0.03
Units
-3
-1
-1Q/-1M
TBUFIOSKEW I/O clock tree skew across one
clock region
All
All
0.03
0.03
0.03
0.03
0.03
ns
ns
TDCD_BUFR
Regional clock tree duty cycle
distortion
0.18
0.18
0.18
0.18
0.18
0.18
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to
calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.
2. The T
value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
CKSKEW
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer
tools to evaluate clock skew specific to your application.
MMCM Switching Characteristics
Table 37: MMCM Specification
Speed Grade
Symbol
Description
1.0V
-2/-2LE
800.00
10.00
0.95V
-1LI
0.9V
-2LE
Units
-3
-1
MMCM_FINMAX
MMCM_FINMIN
MMCM_FINJITTER
MMCM_FINDUTY
Maximum input clock frequency
Minimum input clock frequency
Maximum input clock period jitter
800.00
10.00
800.00
10.00
800.00
10.00
800.00
10.00
MHz
MHz
< 20ꢀ of clock input period or 1 ns Max
Allowable input duty cycle:
10—49 MHz
25
30
35
40
25
30
35
40
25
30
35
40
25
30
35
40
25
30
35
40
ꢀ
ꢀ
ꢀ
ꢀ
Allowable input duty cycle:
50—199 MHz
Allowable input duty cycle:
200—399 MHz
Allowable input duty cycle:
400—499 MHz
Allowable input duty cycle: > 500 MHz
45
45
45
45
45
ꢀ
MMCM_FMIN_PSCLK
MMCM_FMAX_PSCLK
Minimum dynamic phase-shift clock
frequency
0.01
0.01
0.01
0.01
0.01
MHz
Maximum dynamic phase-shift clock
frequency
550.00
500.00
450.00
450.00
450.00
MHz
MMCM_FVCOMIN
MMCM_FVCOMAX
MMCM_FBANDWIDTH
Minimum MMCM VCO frequency
Maximum MMCM VCO frequency
Low MMCM bandwidth at typical(1)
High MMCM bandwidth at typical(1)
600.00
600.00
600.00
600.00
600.00
MHz
MHz
MHz
MHz
ns
1600.00 1440.00 1200.00 1200.00 1200.00
1.00
4.00
0.12
1.00
4.00
0.12
1.00
4.00
0.12
1.00
4.00
0.12
1.00
4.00
0.12
MMCM_TSTATPHAOFFSET Static phase offset of the MMCM
outputs(2)
MMCM_TOUTJITTER
MMCM_TOUTDUTY
MMCM output jitter
Note 3
MMCM output clock duty-cycle
precision(4)
0.20
0.20
0.20
0.20
0.25
ns
MMCM_TLOCKMAX
MMCM_FOUTMAX
MMCM_FOUTMIN
MMCM maximum lock time
100.00
800.00
4.69
100.00
800.00
4.69
100.00
800.00
4.69
100.00
800.00
4.69
100.00
800.00
4.69
µs
MMCM maximum output frequency
MMCM minimum output frequency(5)(6)
MHz
MHz
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Speed Grade
Table 37: MMCM Specification (Cont’d)
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
MMCM_TEXTFDVAR
MMCM_RSTMINPULSE
MMCM_FPFDMAX
External clock feedback variation
Minimum reset pulse width
< 20ꢀ of clock input period or 1 ns Max
5.00
5.00
5.00
5.00
5.00
ns
Maximum frequency at the phase
frequency detector
550.00
500.00
450.00
450.00
450.00
MHz
MMCM_FPFDMIN
Minimum frequency at the phase
frequency detector
10.00
10.00
10.00
10.00
10.00
MHz
MMCM_TFBDELAY
Maximum delay in the feedback path
3 ns Max or one CLKIN cycle
MMCM Switching Characteristics Setup and Hold
TMMCMDCK_PSEN
/
Setup and hold of phase-shift enable
1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00
1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00
ns
ns
ns
TMMCMCKD_PSEN
TMMCMDCK_PSINCDEC
TMMCMCKD_PSINCDEC
/
Setup and hold of phase-shift
increment/decrement
TMMCMCKO_PSDONE
Phase shift clock-to-out of PSDONE
0.59
0.68
0.81
0.81
0.78
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
TMMCMDCK_DADDR
TMMCMCKD_DADDR
/
DADDR setup/hold
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 2.40/0.00 ns, Min
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
TMMCMDCK_DI
TMMCMCKD_DI
/
DI setup/hold
TMMCMDCK_DEN
/
DEN setup/hold
DWE setup/hold
TMMCMCKD_DEN
TMMCMDCK_DWE
/
TMMCMCKD_DWE
TMMCMCKO_DRDY
FDCK
CLK to out of DRDY
DCLK frequency
0.65
0.72
0.99
0.99
0.99
ns, Max
200.00
200.00
200.00
200.00
100.00 MHz, Max
Notes:
1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
4. Includes global clock buffer.
5. Calculated as F
/128 assuming output duty cycle is 50ꢀ.
VCO
6. When CLKOUT4_CASCADE = TRUE, MMCM_F
is 0.036 MHz.
OUTMIN
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
PLL Switching Characteristics
Table 38: PLL Specification
Speed Grade
Symbol
Description
1.0V
-2/-2LE
800.00
19.00
0.95V
-1LI
0.9V
-2LE
Units
-3
-1
PLL_FINMAX
PLL_FINMIN
Maximum input clock frequency
800.00
19.00
800.00
19.00
800.00
19.00
800.00
19.00
MHz
MHz
Minimum input clock frequency
PLL_FINJITTER
PLL_FINDUTY
Maximum input clock period jitter
Allowable input duty cycle: 19—49 MHz
Allowable input duty cycle: 50—199 MHz
Allowable input duty cycle: 200—399 MHz
Allowable input duty cycle: 400—499 MHz
Allowable input duty cycle: >500 MHz
Minimum PLL VCO frequency
< 20ꢀ of clock input period or 1 ns Max
25
30
25
30
25
30
25
30
25
30
ꢀ
ꢀ
35
35
35
35
35
ꢀ
40
40
40
40
40
ꢀ
45
45
45
45
45
ꢀ
PLL_FVCOMIN
800.00
800.00
800.00
800.00
800.00
MHz
MHz
MHz
MHz
ns
PLL_FVCOMAX
PLL_FBANDWIDTH
Maximum PLL VCO frequency
2133.00 1866.00 1600.00 1600.00 1600.00
Low PLL bandwidth at typical(1)
1.00
4.00
0.12
1.00
4.00
0.12
1.00
4.00
0.12
1.00
4.00
0.12
1.00
4.00
0.12
High PLL bandwidth at typical(1)
PLL_TSTATPHAOFFSET Static phase offset of the PLL outputs(2)
PLL_TOUTJITTER
PLL_TOUTDUTY
PLL_TLOCKMAX
PLL_FOUTMAX
PLL_FOUTMIN
PLL output jitter
Note 3
PLL output clock duty-cycle precision(4)
PLL maximum lock time
0.20
100.00
800.00
6.25
0.20
100.00
800.00
6.25
0.20
0.20
100.00
800.00
6.25
0.25
100.00
800.00
6.25
ns
µs
100.00
800.00
6.25
PLL maximum output frequency
PLL minimum output frequency(5)
External clock feedback variation
Minimum reset pulse width
MHz
MHz
PLL_TEXTFDVAR
PLL_RSTMINPULSE
PLL_FPFDMAX
< 20ꢀ of clock input period or 1 ns Max
5.00
5.00
5.00
5.00
5.00
ns
Maximum frequency at the phase
frequency detector
550.00
500.00
450.00
450.00
450.00
MHz
PLL_FPFDMIN
PLL_TFBDELAY
Minimum frequency at the phase
frequency detector
19.00
19.00
19.00
19.00
19.00
MHz
Maximum delay in the feedback path
3 ns Max or one CLKIN cycle
Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK
TPLLDCK_DADDR
/
Setup and hold of D address
Setup and hold of D input
Setup and hold of D enable
Setup and hold of D write enable
CLK to out of DRDY
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 2.40/0.00 ns, Min
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
TPLLCKD_DADDR
TPLLDCK_DI
/
TPLLCKD_DI
TPLLDCK_DEN
/
TPLLCKD_DEN
TPLLDCK_DWE
TPLLCKD_DWE
/
TPLLCKO_DRDY
0.65
0.72
0.99
0.99
0.99
ns, Max
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Speed Grade
Table 38: PLL Specification (Cont’d)
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
200.00
-1
FDCK
DCLK frequency
200.00
200.00
200.00
100.00 MHz, Max
Notes:
1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any PLL outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
4. Includes global clock buffer.
5. Calculated as F
/128 assuming output duty cycle is 50ꢀ.
VCO
Device Pin-to-Pin Output Parameter Guidelines
(1)
Table 39: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)
Speed Grade
Symbol
Description
Device
1.0V
-2/-2LE
0.95V
-1LI
0.9V Units
-2LE
-3
-1
-1M/-1Q
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
TICKOF
Clock-capable clock input and OUTFF at XC7A12T
4.97
5.10
4.97
5.10
5.10
5.14
5.14
5.47
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
5.55
5.70
5.55
5.70
5.70
5.74
5.74
6.11
5.55
5.70
5.55
5.70
5.70
5.74
5.74
5.70
5.74
6.11
6.44
6.61
6.44
6.61
6.61
6.72
6.72
7.16
6.44
6.61
6.44
6.61
6.61
6.72
6.72
6.61
6.72
7.16
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
6.44
6.61
6.44
6.61
6.61
6.72
6.72
6.61
6.72
7.16
6.44
6.61
6.44
6.61
6.61
6.72
6.72
7.16
N/A
7.38
7.56
7.38
7.56
7.56
7.62
7.62
8.08
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pins/banks closest to the BUFGs without
XC7A15T
MMCM/PLL (near clock region)(2)
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
N/A
N/A
N/A
N/A
N/A
N/A
6.61
6.72
7.16
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of 7 Series FPGA Packaging and Pinout Specification (UG475).
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
(1)
Table 40: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)
Speed Grade
Symbol
Description
Device
1.0V
-2/-2LE
0.95V
-1LI
0.9V Units
-2LE
-3
-1
-1M/-1Q
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
TICKOFFAR Clock-capable clock input and OUTFF XC7A12T
at pins/banks farthest from the BUFGs
4.97
5.10
4.97
5.10
5.10
5.38
5.38
6.17
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
5.55
5.70
5.55
5.70
5.70
6.01
6.01
6.89
5.55
5.70
5.55
5.70
5.70
6.01
6.01
5.70
6.01
6.89
6.44
6.61
6.44
6.61
6.61
7.02
7.02
8.05
6.44
6.61
6.44
6.61
6.61
7.02
7.02
6.61
7.02
8.05
N/A
N/A
6.44
6.61
6.44
6.61
6.61
7.02
7.02
8.05
N/A
7.38
7.57
7.38
7.57
7.57
7.94
7.94
9.03
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC7A15T
without MMCM/PLL (far clock region)(2)
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
N/A
N/A
N/A
N/A
N/A
N/A
6.44
6.61
6.44
6.61
6.61
7.02
7.02
6.61
7.02
8.05
N/A
N/A
N/A
N/A
N/A
N/A
6.61
7.02
8.05
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of 7 Series FPGA Packaging and Pinout Specification (UG475).
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 41: Clock-Capable Clock Input to Output Delay With MMCM
Speed Grade
Symbol
Description
Device
1.0V
-2/-2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.
0.95V
-1LI
0.9V
-2LE
Units
-3
-1
-1M/-1Q
TICKOFMMCMCC
Clock-capable clock input and
OUTFF with MMCM
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.01
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.02
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.02
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.04
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.04
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.04
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.04
N/A
1.78
1.78
1.78
1.78
1.78
1.79
1.79
1.84
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
N/A
N/A
N/A
N/A
N/A
N/A
1.00
1.00
1.04
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. MMCM output jitter is already included in the timing calculation.
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 42: Clock-Capable Clock Input to Output Delay With PLL
Speed Grade
Symbol
Description
Device
1.0V
-2/-2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL.
0.95V
-1LI
0.9V Units
-2LE
-3
-1
-1M/-1Q
TICKOFPLLCC
Clock-capable clock input and
OUTFF with PLL
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
0.83
0.82
0.83
0.82
0.82
0.82
0.82
0.81
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.83
0.82
0.83
0.82
0.82
0.82
0.82
0.81
0.83
0.82
0.83
0.82
0.82
0.82
0.82
0.82
0.82
0.81
0.83
0.82
0.83
0.82
0.82
0.82
0.82
0.81
0.83
0.82
0.83
0.82
0.82
0.82
0.82
0.82
0.82
0.81
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.83
0.82
0.83
0.82
0.82
0.82
0.82
0.82
0.82
0.81
0.83
0.82
0.83
0.82
0.82
0.82
0.82
0.81
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.38
1.39
1.38
1.39
1.39
1.40
1.40
1.45
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.82
0.82
0.81
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is already included in the timing calculation.
Table 43: Pin-to-Pin, Clock-to-Out using BUFIO
Speed Grade
Symbol
Description
1.0V
-2/-2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO.
0.95V
-1LI
0.9V
-2LE
Units
-3
-1
-1M/-1Q
TICKOFCS
Clock to out of I/O clock
5.01
5.61
6.64
6.64
6.64
7.32
ns
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44
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Values are expressed in nanoseconds unless otherwise noted.
Table 44: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks
Speed Grade
Symbol
Description
Device
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1M/-1Q
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)
TPSFD
/
Full delay (legacy delay XC7A12T
or default delay)
2.49/–0.37 2.67/–0.37 3.12/–0.37
2.47/–0.29 2.65/–0.29 3.10/–0.29
2.49/–0.37 2.67/–0.37 3.12/–0.37
2.47/–0.29 2.65/–0.29 3.10/–0.29
2.47/–0.29 2.65/–0.29 3.10/–0.29
2.69/–0.34 2.89/–0.34 3.34/–0.34
2.69/–0.34 2.89/–0.34 3.34/–0.34
3.03/–0.36 3.27/–0.36 3.79/–0.36
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.12/–0.37 5.13/–0.54
3.10/–0.29 5.10/–0.44
3.12/–0.37 5.13/–0.54
3.10/–0.29 5.10/–0.44
3.10/–0.29 5.10/–0.44
3.34/–0.34 5.66/–0.51
3.34/–0.34 5.66/–0.51
3.79/–0.36 6.66/–0.55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPHFD
XC7A15T
global clock input and
IFF(2) without
MMCM/PLL with
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
ZHOLD_DELAY on HR
I/O banks
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
2.67/–0.37 3.12/–0.37 3.12/–0.37
2.65/–0.29 3.10/–0.29 3.10/–0.29
2.67/–0.37 3.12/–0.37 3.12/–0.37
2.65/–0.29 3.10/–0.29 3.10/–0.29
2.65/–0.29 3.10/–0.29 3.10/–0.29
2.89/–0.34 3.34/–0.34 3.34/–0.34
2.89/–0.34 3.34/–0.34 3.34/–0.34
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
2.65/–0.29 3.10/–0.29 3.10/–0.29 3.10/–0.29
2.89/–0.34 3.34/–0.34 3.34/–0.34 3.34/–0.34
3.27/–0.36 3.79/–0.36 3.79/–0.36 3.79/–0.36
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global
clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input
signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch.
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45
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 45: Clock-Capable Clock Input Setup and Hold With MMCM
Speed Grade
Symbol
Description
Device
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1M/-1Q
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)
TPSMMCMCC
TPHMMCMCC
/
No delay clock-
capable clock input
and IFF(2) with
MMCM
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
2.37/–0.61 2.69/–0.61 3.21/–0.61
2.46/–0.62 2.80/–0.62 3.35/–0.62
2.37/–0.61 2.69/–0.61 3.21/–0.61
2.46/–0.62 2.80/–0.62 3.35/–0.62
2.46/–0.62 2.80/–0.62 3.35/–0.62
2.47/–0.62 2.81/–0.62 3.36/–0.62
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.21/–0.61 2.00/–0.47
3.35/–0.62 2.14/–0.48
3.21/–0.61 2.00/–0.47
3.35/–0.62 2.14/–0.48
3.35/–0.62 2.14/–0.48
3.36/–0.62 2.15/–0.48
3.36/–0.62 2.15/–0.48
3.52/–0.63 2.32/–0.51
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC7A100T 2.47/–0.62 2.81/–0.62 3.36/–0.62
XC7A200T 2.59/–0.63 2.95/–0.63 3.52/–0.63
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
2.69/–0.61 3.21/–0.61 3.21/–0.61
2.80/–0.62 3.35/–0.62 3.35/–0.62
2.69/–0.61 3.21/–0.61 3.21/–0.61
2.80/–0.62 3.35/–0.62 3.35/–0.62
2.80/–0.62 3.35/–0.62 3.35/–0.62
2.81/–0.62 3.36/–0.62 3.36/–0.62
2.81/–0.62 3.36/–0.62 3.36/–0.62
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
2.80/–0.62 3.35/–0.62 3.35/–0.62 3.35/–0.62
2.81/–0.62 3.36/–0.62 3.36/–0.62 3.36/–0.62
2.95/–0.63 3.52/–0.63 3.52/–0.63 3.52/–0.63
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global
clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 46: Clock-Capable Clock Input Setup and Hold With PLL
Speed Grade
Symbol
Description
Device
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1M/-1Q
Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1)
TPSPLLCC
/
Nodelayclock-capable XC7A12T
2.68/–0.19 3.04/–0.19 3.64/–0.19
2.77/–0.20 3.15/–0.20 3.77/–0.20
2.68/–0.19 3.04/–0.19 3.64/–0.19
2.77/–0.20 3.15/–0.20 3.77/–0.20
2.77/–0.20 3.15/–0.20 3.77/–0.20
2.78/–0.20 3.15/–0.20 3.78/–0.20
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.64/–0.19 2.32/–0.57
3.77/–0.20 2.46/–0.59
3.64/–0.19 2.32/–0.57
3.77/–0.20 2.46/–0.59
3.77/–0.20 2.46/–0.59
3.78/–0.20 2.47/–0.59
3.78/–0.20 2.47/–0.59
3.94/–0.21 2.64/–0.62
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPHPLLCC clock input and IFF(2)
with PLL
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T 2.78/–0.20 3.15/–0.20 3.78/–0.20
XC7A200T 2.91/–0.21 3.29/–0.21 3.94/–0.21
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.04/–0.19 3.64/–0.19 3.64/–0.19
3.15/–0.20 3.77/–0.20 3.77/–0.20
3.04/–0.19 3.64/–0.19 3.64/–0.19
3.15/–0.20 3.77/–0.20 3.77/–0.20
3.15/–0.20 3.77/–0.20 3.77/–0.20
3.15/–0.20 3.78/–0.20 3.78/–0.20
3.15/–0.20 3.78/–0.20 3.78/–0.20
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.15/–0.20 3.77/–0.20 3.77/–0.20 3.77/–0.20
3.15/–0.20 3.78/–0.20 3.78/–0.20 3.78/–0.20
3.29/–0.21 3.94/–0.21 3.94/–0.21 3.94/–0.21
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global
clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 47: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
Speed Grade
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
-1M/-1Q
Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.
TPSCS/TPHCS
Setup and hold of I/O clock
–0.38/1.31 –0.38/1.46 –0.38/1.76 –0.38/1.76 –0.38/1.76 –0.16/1.89
ns
Table 48: Sample Window
Speed Grade
Symbol
Description
1.0V
-2/-2LE
0.64
0.95V
-1LI
0.9V
-2LE
0.70
Units
-3
-1
-1M/-1Q
TSAMP
Sampling error at receiver pins(1)
0.59
0.70
0.70
0.70
ns
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Speed Grade
Table 48: Sample Window (Cont’d)
Symbol
Description
1.0V
-2/-2LE
0.40
0.95V
-1LI
0.9V
-2LE
0.46
Units
-3
-1
-1M/-1Q
TSAMP_BUFIO
Sampling error at receiver pins using
BUFIO(2)
0.35
0.46
0.46
0.46
ns
Notes:
1. This parameter indicates the total sampling error of the Artix-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of the Artix-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of
operation. These measurements do not include package or clock tree skew.
Additional Package Parameter Guidelines
The parameters in this section provide the necessary values for calculating timing budgets for Artix-7 FPGA clock transmitter
and receiver data-valid windows.
Table 49: Package Skew
Symbol
TPKGSKEW
Description
Device
XC7A12T
Package
CPG238
CSG325
CPG236
CSG324
CSG325
FTG256
FGG484
CPG238
CSG325
CPG236
CSG324
CSG325
FTG256
FGG484
CPG236
CSG324
CSG325
FTG256
FGG484
CSG324
FTG256
FGG484
FGG676
Value
55
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Package skew(1)
76
48
XC7A15T
104
142
98
97
55
XC7A25T
XC7A35T
76
48
104
142
98
97
48
XC7A50T
XC7A75T
104
142
98
97
113
120
144
153
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 49: Package Skew (Cont’d)
Symbol Description
TPKGSKEW
Package skew(1)
Device
XC7A100T
Package
CSG324
FTG256
FGG484
FGG676
SBG484
FBG484
FBG676
FFG1156
CSG325
CPG238
CPG236
CSG324
CSG325
CSG325
CPG238
CPG236
CSG324
CSG325
CPG236
CSG324
CSG325
CSG324
FGG484
CSG324
FGG484
CS325
Value
113
120
144
153
111
109
121
151
76
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
XC7A200T
XA7A12T
XA7A15T
55
48
104
142
76
XA7A25T
XA7A35T
55
48
104
142
48
XA7A50T
104
142
113
144
113
144
142
97
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
FG484
CS324
113
144
111
109
121
FG484
RS484
RB484
RB676
Notes:
1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die
pad to ball.
2. Package delay information is available for these device/package combinations. This information can be used to deskew the package.
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49
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
GTP Transceiver Specifications
GTP Transceiver DC Input and Output Levels
Table 50 summarizes the DC output specifications of the GTP transceivers in Artix-7 FPGAs. Consult 7 Series FPGAs GTP
Transceiver User Guide (UG482) for further details.
Table 50: GTP Transceiver DC Specifications
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
Differential peak-to-peak output Transmitter output swing is set to
1000
–
–
mV
DVPPOUT
voltage(1)
maximum setting
DC common mode output
voltage
Equation based
VMGTAVTT – DVPPOUT/4
mV
VCMOUTDC
ROUT
Differential output resistance
–
100
–
Ω
mV
ps
VCMOUTAC
Common mode output voltage: AC coupled
1/2 VMGTAVTT
–
Transmitter output pair (TXP and TXN) intra-pair skew
(FF, FB, SB packages)
–
–
10
12
TOSKEW
Transmitter output pair (TXP and TXN) intra-pair skew
(FG, FT, CS, CP packages)
–
ps
Differential peak-to-peak input External AC coupled
voltage
150
–
2000
mV
DVPPIN
VIN
Single-ended input voltage(2)
Common mode input voltage
Differential input resistance
DC coupled VMGTAVTT = 1.2V
DC coupled VMGTAVTT = 1.2V
–200
–
2/3 VMGTAVTT
100
VMGTAVTT mV
VCMIN
RIN
–
–
–
–
–
–
mV
Ω
CEXT
Recommended external AC coupling capacitor(3)
100
nF
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in 7 Series FPGAs GTP Transceiver User Guide
(UG482) and can result in values lower than reported in this table.
2. Voltage measured at the pin referenced to ground.
3. Other values can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 3
+V
0
P
N
Single-Ended
Peak-to-Peak
Voltage
ds181_01_062014
Figure 3: Single-Ended Peak-to-Peak Voltage
X-Ref Target - Figure 4
+V
0
Differential
Peak-to-Peak
Voltage
P–N
–V
ds181_02_062014
Figure 4: Differential Peak-to-Peak Voltage
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50
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Note: In Figure 4, differential peak-to-peak voltage = single-ended peak-to-peak voltage x 2.
Table 51 summarizes the DC specifications of the clock input of the GTP transceiver. Consult 7 Series FPGAs GTP Transceiver
User Guide (UG482) for further details.
Table 51: GTP Transceiver Clock DC Input Level Specification
Symbol
VIDIFF
DC Parameter
Differential peak-to-peak input voltage
Min
350
–
Typ
–
Max
2000
–
Units
mV
Ω
RIN
Differential input resistance
100
100
CEXT
Required external AC coupling capacitor
–
–
nF
GTP Transceiver Switching Characteristics
Consult 7 Series FPGAs GTP Transceiver User Guide (UG482) for further information.
Table 52: GTP Transceiver Performance
Speed Grade
-1 (1.0V)
-2 (1.0V)
-2LE (1.0V)
-1LI (0.95V)
-1Q (1.0V)
-1M (1.0V)
-3 (1.0V)
-2LE (0.9V)
Output
Divider
Symbol
Description
Units
Package Type
FF
FB
SB
RB
RS
FF
FG
FB
FT
FG
FG
FT
CS
CP
FG
FF
FB
SB
FF
FT
FB
CS
SB
CP
FT
CS
CP
SB
CS
RB
CP
RS
FGTPMAX
Maximum GTP transceiver data rate
6.6
6.25
6.6
6.25
3.75
3.75
3.75
3.75
Gb/s
FGTPMIN
Minimum GTP transceiver data rate
1
0.500
0.500
0.500
0.500
0.500
0.500
0.500
0.500 Gb/s
3.2–6.6
3.2–6.6
3.2–3.75
3.2–3.75
1.6–3.2
Gb/s
Gb/s
Gb/s
Gb/s
GHz
2
1.6–3.3
0.8–1.65
0.5–0.825
1.6–3.3
1.6–3.3
0.8–1.65
0.5–0.825
1.6–3.3
1.6–3.2
0.8–1.6
0.5–0.8
1.6–3.3
FGTPRANGE
PLL line rate range
4
0.8–1.6
0.5–0.8
1.6–3.3
8
FGTPPLLRANGE GTP transceiver PLL frequency
range
Table 53: GTP Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Speed Grade
Symbol
Description
1.0V
-2/-2LE
175
0.95V
-1LI
0.9V
-2LE
125
Units
-3
-1
FGTPDRPCLK
GTPDRPCLK maximum frequency
175
156
156
MHz
Table 54: GTP Transceiver Reference Clock Switching Characteristics
All Speed Grades
Symbol
Description
Conditions
Units
Min
60
–
Typ
–
Max
660
–
FGCLK
TRCLK
TFCLK
TDCREF
Reference clock frequency range
Reference clock rise time
Reference clock fall time
MHz
ps
20ꢀ – 80ꢀ
200
200
–
80ꢀ – 20ꢀ
–
–
ps
Reference clock duty cycle
Transceiver PLL only
40
60
ꢀ
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51
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
X-Ref Target - Figure 5
TRCLK
80%
20%
TFCLK
Figure 5: Reference Clock Timing Parameters
Table 55: GTP Transceiver PLL/Lock Time Adaptation
ds181_03_062811
All Speed Grades
Symbol
Description
Initial PLL lock
Conditions
Units
Min
Typ
Max
TLOCK
–
–
1
ms
After the PLL is locked to the
reference clock, this is the time it
takes to lock the clock data
recovery (CDR) to the data
present at the input.
Clock recovery phase acquisition and
adaptation time.
TDLOCK
–
50,000
2.3 x106
UI
(1)
Table 56: GTP Transceiver User Clock Switching Characteristics
Speed Grade
Symbol
Description
Conditions
1.0V
0.95V
-1LI
0.9V
Units
-3
-2/-2LE
412.500
412.500
412.500
412.500
412.500
412.500
-1
-2LE
FTXOUT
TXOUTCLK maximum frequency
412.500
412.500
412.500
412.500
412.500
412.500
234.375
234.375
234.375
234.375
234.375
234.375
234.375
234.375
234.375
234.375
234.375
234.375
234.375
234.375
234.375
234.375
234.375
234.375
MHz
MHz
MHz
MHz
MHz
MHz
FRXOUT RXOUTCLK maximum frequency
FTXIN
TXUSRCLK maximum frequency
RXUSRCLK maximum frequency
16-bit data path
16-bit data path
FRXIN
FTXIN2
FRXIN2
TXUSRCLK2 maximum frequency 16-bit data path
RXUSRCLK2 maximum frequency 16-bit data path
Notes:
1. Clocking must be implemented as described in 7 Series FPGAs GTP Transceiver User Guide (UG482).
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 57: GTP Transceiver Transmitter Switching Characteristics
Symbol
Description
Serial data rate range
Condition
Min
Typ
–
Max
FGTPMAX
–
Units
Gb/s
ps
ps
ps
mV
ns
UI
FGTPTX
TRTX
0.500
–
TX rise time
20ꢀ–80ꢀ
80ꢀ–20ꢀ
50
50
–
TFTX
TX fall time
–
–
TLLSKEW
TX lane-to-lane skew(1)
Electrical idle amplitude
Electrical idle transition time
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
–
500
VTXOOBVDPP
TTXOOBTRANSITION
TJ6.6
–
–
20
–
–
140
–
–
0.30
0.15
0.30
0.15
0.30
0.15
0.30
0.15
0.2
6.6 Gb/s
5.0 Gb/s
DJ6.6
–
–
UI
TJ5.0
–
–
UI
DJ5.0
–
–
UI
TJ4.25
–
–
UI
4.25 Gb/s
3.75 Gb/s
3.20 Gb/s(4)
3.20 Gb/s(5)
2.5 Gb/s(6)
1.25 Gb/s(7)
500 Mb/s
DJ4.25
TJ3.75
–
–
UI
–
–
UI
DJ3.75
TJ3.2
–
–
UI
–
–
UI
DJ3.2
–
–
0.1
UI
TJ3.2L
–
–
0.32
0.16
0.20
0.08
0.15
0.06
0.1
UI
DJ3.2L
TJ2.5
–
–
UI
–
–
UI
DJ2.5
–
–
UI
TJ1.25
–
–
UI
DJ1.25
TJ500
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
–
–
UI
–
–
UI
DJ500
–
–
0.03
UI
Notes:
1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTP Quad).
2. Using PLL[0/1]_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
-12
3. All jitter values are based on a bit-error ratio of 1e
4. PLL frequency at 3.2 GHz and TXOUT_DIV = 2.
5. PLL frequency at 1.6 GHz and TXOUT_DIV = 1.
6. PLL frequency at 2.5 GHz and TXOUT_DIV = 2.
7. PLL frequency at 2.5 GHz and TXOUT_DIV = 4.
.
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 58: GTP Transceiver Receiver Switching Characteristics
Symbol Description
RX oversampler not enabled
Min
0.500
–
Typ
–
Max
FGTPMAX
–
Units
Gb/s
ns
FGTPRX
TRXELECIDLE
RXOOBVDPP
Serial data rate
Time for RXELECIDLE to respond to loss or restoration of data
OOB detect threshold peak-to-peak
10
–
60
150
mV
Receiver spread-spectrum
Modulated @ 33 kHz
tracking(1)
–5000
–
5000
ppm
RXSST
RXRL
Run length (CID)
–
–
–
512
UI
RXPPMTOL
SJ Jitter Tolerance(2)
JT_SJ6.6
Data/REFCLK PPM offset tolerance
–1250
1250
ppm
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
6.6 Gb/s
0.44
0.44
0.44
0.44
0.45
0.45
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
UI
UI
UI
UI
UI
UI
UI
UI
UI
JT_SJ5.0
5.0 Gb/s
JT_SJ4.25
JT_SJ3.75
JT_SJ3.2
4.25 Gb/s
3.75 Gb/s
3.2 Gb/s(4)
3.2 Gb/s(5)
2.5 Gb/s(6)
1.25 Gb/s(7)
500 Mb/s
JT_SJ3.2L
JT_SJ2.5
JT_SJ1.25
JT_SJ500
0.5
0.4
SJ Jitter Tolerance with Stressed Eye(2)
JT_TJSE3.2
3.2 Gb/s
6.6 Gb/s
3.2 Gb/s
6.6 Gb/s
0.70
0.70
0.1
–
–
–
–
–
–
–
–
UI
UI
UI
UI
Total Jitter with Stressed Eye(8)
JT_TJSE6.6
JT_SJSE3.2
JT_SJSE6.6
Sinusoidal Jitter with Stressed
Eye(8)
0.1
Notes:
1. Using RXOUT_DIV = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 1e
–12
.
3. The frequency of the injected sinusoidal jitter is 10 MHz.
4. PLL frequency at 3.2 GHz and RXOUT_DIV = 2.
5. PLL frequency at 1.6 GHz and RXOUT_DIV = 1.
6. PLL frequency at 2.5 GHz and RXOUT_DIV = 2.
7. PLL frequency at 2.5 GHz and RXOUT_DIV = 4.
8. Composite jitter.
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
GTP Transceiver Protocol Jitter Characteristics
For Table 59 through Table 63, the 7 Series FPGAs GTP Transceiver User Guide (UG482) contains recommended settings for
optimal usage of protocol specific characteristics.
Table 59: Gigabit Ethernet Protocol Characteristics
Description
Line Rate (Mb/s)
Min
–
Max
0.24
–
Units
UI
Gigabit Ethernet Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
1250
Gigabit Ethernet Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
1250
0.749
UI
Table 60: XAUI Protocol Characteristics
Description
Line Rate (Mb/s)
3125
Min
–
Max
0.35
–
Units
UI
XAUI Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
XAUI Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
3125
0.65
UI
(1)
Table 61: PCI Express Protocol Characteristics
Standard
Description
Line Rate (Mb/s)
Min
Max
Units
PCI Express Transmitter Jitter Generation
PCI Express Gen 1
PCI Express Gen 2
Total transmitter jitter
Total transmitter jitter
2500
5000
–
–
0.25
0.25
UI
UI
PCI Express Receiver High Frequency Jitter Tolerance
PCI Express Gen 1
Total receiver jitter tolerance
Receiver inherent timing error
2500
5000
0.65
0.40
0.30
–
–
–
UI
UI
UI
PCI Express Gen 2(2)
Receiver inherent deterministic timing error
Notes:
1. Tested per card electromechanical (CEM) methodology.
2. Using common REFCLK.
Table 62: CEI-6G Protocol Characteristics
Description
Line Rate (Mb/s)
Interface
Min
Max
Units
UI
CEI-6G Transmitter Jitter Generation
Total transmitter jitter(1)
4976–6375
CEI-6G-SR
CEI-6G-SR
–
0.3
–
CEI-6G Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance(1)
4976–6375
0.6
UI
Notes:
1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 63: CPRI Protocol Characteristics
Description
Line Rate (Mb/s)
Min
Max
Units
CPRI Transmitter Jitter Generation
614.4
1228.8
2457.6
3072.0
4915.2
6144.0
–
–
–
–
–
–
0.35
0.35
0.35
0.35
0.3
UI
UI
UI
UI
UI
UI
Total transmitter jitter
0.3
CPRI Receiver Frequency Jitter Tolerance
Total receiver jitter tolerance
614.4
1228.8
0.65
0.65
0.65
0.65
0.60
0.60
–
–
–
–
–
–
UI
UI
UI
UI
UI
UI
2457.6
3072.0
4915.2(1)
6144.0(1)
Notes:
1. Tested to CEI-6G-SR.
Integrated Interface Block for PCI Express Designs Switching Characteristics
More information and documentation on solutions for PCI Express designs can be found at:
www.xilinx.com/products/technology/pci-express.html
Table 64: Maximum Performance for PCI Express Designs
Speed Grade
Symbol
Description
1.0V
0.95V
-1LI
0.9V
Units
-3
-2/-2LE
250.00
250.00
250.00
250.00
-1
-2LE
FPIPECLK
Pipe clock maximum frequency
User clock maximum frequency
User clock 2 maximum frequency
DRP clock maximum frequency
250.00
250.00
250.00
250.00
250.00
250.00
250.00
250.00
250.00
250.00
250.00
250.00
250.00
250.00
250.00
250.00
MHz
MHz
MHz
MHz
FUSERCLK
FUSERCLK2
FDRPCLK
Notes:
1. Refer to PG054, 7 Series FPGAs Integrated Block for PCI Express Product Guide for specific supported core configurations.
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
XADC Specifications
Table 65: XADC Specifications
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
VCCADC = 1.8V 5ꢀ, VREFP = 1.25V, VREFN = 0V, ADCCLK = 26 MHz, –55°C ≤ Tj ≤ 125°C, Typical values at Tj=+40°C
ADC Accuracy(1)
Resolution
12
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
–
–
Bits
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
ꢀ
Integral Nonlinearity(2)
INL
–40°C ≤ Tj ≤ 100°C
2
–55°C ≤ Tj < –40°C; 100°C < Tj ≤ 125°C
No missing codes, guaranteed monotonic
–40°C ≤ Tj ≤ 100°C
–
3
1
Differential Nonlinearity
Offset Error
DNL
–
Unipolar
–
8
–55°C ≤ Tj < –40°C; 100°C < Tj ≤ 125°C
–55°C ≤ Tj ≤ 125°C
–
12
4
Bipolar
–
Gain Error
–
0.5
4
Offset Matching
Gain Matching
Sample Rate
–
LSBs
ꢀ
–
0.3
1
–
MS/s
dB
Signal to Noise Ratio(2)
RMS Code Noise
SNR
THD
FSAMPLE = 500KS/s, FIN = 20 kHz
External 1.25V reference
60
–
–
2
LSBs
LSBs
dB
On-chip reference
–
–
Total Harmonic Distortion(2)
Analog Inputs(3)
FSAMPLE = 500KS/s, FIN = 20 kHz
70
–
ADC Input Ranges
Unipolar operation
0
–
–
–
–
–
1
V
V
V
V
V
Bipolar operation
–0.5
0
+0.5
Unipolar common mode range (FS input)
Bipolar common mode range (FS input)
+0.5
+0.5
–0.1
+0.6
Maximum External Channel Input Ranges
Adjacent analog channels set within these
ranges should not corrupt measurements on
adjacent channels
VCCADC
Auxiliary Channel Full
Resolution Bandwidth
FRBW
250
–
–
kHz
On-Chip Sensors
Temperature Sensor Error
–40°C ≤ Tj ≤ 100°C
–
–
–
–
–
–
–
–
4
6
1
2
°C
°C
ꢀ
–55°C ≤ Tj < –40°C; 100°C < Tj ≤ 125°C
–40°C ≤ Tj ≤ 100°C
Supply Sensor Error
–55°C ≤ Tj < –40°C; 100°C < Tj ≤ 125°C
ꢀ
Conversion Rate(4)
Conversion Time - Continuous tCONV
Number of ADCCLK cycles
Number of CLK cycles
DRP clock frequency
Derived from DCLK
26
–
–
–
–
–
–
32
21
Cycles
Cycles
MHz
MHz
ꢀ
Conversion Time - Event
DRP Clock Frequency
ADC Clock Frequency
DCLK Duty Cycle
tCONV
DCLK
8
250
26
ADCCLK
1
40
60
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 65: XADC Specifications (Cont’d)
Parameter
XADC Reference(5)
External Reference
On-Chip Reference
Symbol
Comments/Conditions
Min
Typ
Max
Units
VREFP
Externally supplied reference voltage
1.20
1.25
1.30
V
V
Ground VREFP pin to AGND,
–40°C ≤ Tj ≤ 100°C
1.2375 1.25
1.2625
Ground VREFP pin to AGND,
1.225 1.25
1.275
V
–55°C ≤ Tj < –40°C; 100°C < Tj ≤ 125°C
Notes:
1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature
is enabled.
2. Only specified for bitstream option XADCEnhancedLinearity = ON.
3. See the ADC chapter in the 7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter (UG480) for a
detailed description.
4. See the Timing chapter in the 7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter (UG480) for
a detailed description.
5. Any variation in the reference voltage from the nominal V
= 1.25V and V
= 0V will result in a deviation from the ideal transfer
REFN
REFP
function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing reference to vary by 4ꢀ is permitted.
Configuration Switching Characteristics
Table 66: Configuration Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
-1
Power-up Timing Characteristics
(1)
TPL
Program latency
5.00
10/50
10/35
250.00
5.00
10/50
10/35
250.00
5.00
10/50
10/35
250.00
5.00
10/50
10/35
250.00
5.00
ms, Max
(1)
TPOR
Power-on reset (50 ms ramp rate time)
Power-on reset (1 ms ramp rate time)
Program pulse width
10/50 ms, Min/Max
10/35 ms, Min/Max
TPROGRAM
250.00
ns, Min
CCLK Output (Master Mode)
TICCK
Master CCLK output delay
150.00
40/60
40/60
100.00
50.00
3.00
150.00
40/60
40/60
100.00
50.00
3.00
150.00
40/60
40/60
100.00
50.00
3.00
150.00
40/60
40/60
100.00
50.00
3.00
150.00
40/60
40/60
70.00
35.00
3.00
ns, Min
ꢀ, Min/Max
ꢀ, Min/Max
MHz, Max
MHz, Max
MHz, Typ
ꢀ, Max
TMCCKL
TMCCKH
FMCCK
Master CCLK clock Low time duty cycle
Master CCLK clock High time duty cycle
Master CCLK frequency
Master CCLK frequency for AES encrypted x16
FMCCK_START Master CCLK frequency at start of configuration
FMCCKTOL
Frequency tolerance, master mode with respect
to nominal CCLK
50
50
50
50
50
CCLK Input (Slave Modes)
TSCCKL
TSCCKH
FSCCK
Slave CCLK clock minimum Low time
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
ns, Min
ns, Min
Slave CCLK clock minimum High time
Slave CCLK frequency
100.00
100.00
100.00
100.00
70.00
MHz, Max
EMCCLK Input (Master Mode)
TEMCCKL
TEMCCKH
FEMCCK
External master CCLK Low time
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
ns, Min
ns, Min
External master CCLK High time
External master CCLK frequency
100.00
100.00
100.00
100.00
70.00
MHz, Max
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 66: Configuration Switching Characteristics (Cont’d)
Speed Grade
-1
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
Internal Configuration Access Port
FICAPCK Internal configuration access port (ICAPE2)
100.00
100.00
100.00
100.00
70.00
MHz, Max
clock frequency
Master/Slave Serial Mode Programming Switching
TDCCK
/
DIN setup/hold
4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00
8.00 8.00 8.00 8.00 9.00
ns, Min
ns, Max
TCCKD
TCCO
DOUT clock to out
SelectMAP Mode Programming Switching
TSMDCCK
/
D[31:00] setup/hold
4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00
4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00
10.00/0.00 10.00/0.00 10.00/0.00 10.00/0.00 12.00/0.00
ns, Min
ns, Min
ns, Min
ns, Max
TSMCCKD
TSMCSCCK
TSMCCKCS
/
CSI_B setup/hold
TSMWCCK
TSMCCKW
/
RDWR_B setup/hold
TSMCKCSO
CSO_B clock to out (330 Ω pull-up resistor
required)
7.00
7.00
7.00
7.00
8.00
TSMCO
D[31:00] clock to out in readback
Readback frequency
8.00
8.00
8.00
8.00
10.00
70.00
ns, Max
FRBCCK
100.00
100.00
100.00
100.00
MHz, Max
Boundary-Scan Port Timing Specifications
TTAPTCK
/
TMS and TDI setup/hold
3.00/2.00 3.00/2.00 3.00/2.00 3.00/2.00 3.00/2.00
ns, Min
TTCKTAP
TTCKTDO
FTCK
TCK falling edge to TDO output
TCK frequency
7.00
7.00
7.00
7.00
8.50
ns, Max
66.00
66.00
66.00
66.00
50.00
MHz, Max
BPI Flash Master Mode Programming Switching
(2)
TBPICCO
A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B,
ADV_B clock to out
8.50
8.50
8.50
8.50
10.00
ns, Max
ns, Min
TBPIDCC
TBPICCD
/
D[15:00] setup/hold
4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00
SPI Flash Master Mode Programming Switching
TSPIDCC
/
D[03:00] setup/hold
3.00/0.00 3.00/0.00 3.00/0.00 3.00/0.00 3.00/0.00
ns, Min
TSPICCD
TSPICCM
MOSI clock to out
FCS_B clock to out
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
9.00
9.00
ns, Max
ns, Max
TSPICCFC
STARTUPE2 Ports
TUSRCCLKO STARTUPE2 USRCCLKO input to CCLK output 0.50/6.00 0.50/6.70 0.50/7.50 0.50/7.50 0.50/7.50
ns,
Min/Max
FCFGMCLK
STARTUPE2 CFGMCLK output frequency
65.00
50
65.00
50
65.00
50
65.00
50
65.00
50
MHz, Typ
ꢀ, Max
FCFGMCLKTOL STARTUPE2 CFGMCLK output frequency
tolerance
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 66: Configuration Switching Characteristics (Cont’d)
Speed Grade
-1
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
Device DNA Access Port
FDNACK
DNA access port (DNA_PORT)
100.00
100.00
100.00
100.00
70.00
MHz, Max
Notes:
1. To support longer delays in configuration, use the design solutions described in 7 Series FPGA Configuration User Guide (UG470).
2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
eFUSE Programming Conditions
Table 67 lists the programming conditions specifically for eFUSE. For more information, see 7 Series FPGA Configuration User
Guide (UG470).
(1)
Table 67: eFUSE Programming Conditions
Symbol
Description
Min
–
Typ
–
Max
115
125
Units
mA
IFS
Tj
VCCAUX supply current
Temperature range
15
–
°C
Notes:
1. The FPGA must not be configured during eFUSE programming.
Revision History
The following table shows the revision history for this document:
Date
Version
1.0
Description
09/26/2011
11/07/2011
Initial Xilinx release.
1.1
Revised the VOCM specification in Table 11. Updated the AC Switching Characteristics based upon the
ISE 13.3 software v1.02 speed specification throughout document including Table 13 and Table 14.
Added MMCM_TFBDELAY while adding MMCM_ to the symbol names of a few specifications in
Table 37 and PLL to the symbol names in Table 38. In Table 39 through Table 46, updated the pin-to-
pin description with the SSTL15 standard. Updated units in Table 46.
02/13/2012
1.2
Updated the Artix-7 family of devices listed throughout the entire data sheet. Updated the AC Switching
Characteristics based upon the ISE 13.4 software v1.03 for the -3, -2, and -1 speed grades and v1.00
for the -2L speed grade.
Updated summary description on page 1. In Table 2, revised VCCO for the 3.3V HR I/O banks and
updated Tj. Updated the notes in Table 5. Added MGTAVCC and MGTAVTT power supply ramp times
to Table 7. Rearranged Table 8, added Mobile_DDR, HSTL_I_18, HSTL_II_18, HSUL_12,
SSTL135_R, SSTL15_R, and SSTL12 and removed DIFF_SSTL135, DIFF_SSTL18_I,
DIFF_SSTL18_II, DIFF_HSTL_I, and DIFF_HSTL_II. Added Table 9 and Table 10. Revised the
specifications in Table 11. Revised VIN in Table 50. Updated the eFUSE Programming Conditions
section and removed the endurance table. Added the table. Revised FTXIN and FRXIN in Table 56.
Revised ICCADC and updated Note 1 in Table 65. Revised DDR LVDS transmitter data width in
Table 15. Removed notes from Table 27 as they are no longer applicable. Updated specifications in
Table 66. Updated Note 1 in Table 36.
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Description
Date
Version
06/01/2012
1.3
Reorganized entire data sheet including adding Table 43 and Table 47.
UpdatedTSOLin Table 1. UpdatedIBATT andaddedRIN_TERM to Table 3. UpdatedPower-On/OffPower
Supply Sequencing section with regards to GTP transceivers. In Table 8, updated many parameters
including SSTL135 and SSTL135_R. Removed VOX column and added DIFF_HSUL_12 to Table 10.
Updated VOL in Table 11. Updated Table 15 and removed notes 2 and 3. Updated Table 16.
Updated the AC Switching Characteristics based upon the ISE 14.1 software v1.03 for the -3, -2, -2L
(1.0V), -1, and v1.01 for the -2L (0.9V) speed specifications throughout the document.
In Table 30, updated Reset Delays section including Note 10 and Note 11. In Table 56, replaced
F
TXOUT with FGLK. Updated many of the XADC specifications in Table 65 and added Note 2. Updated
and moved Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK section from
Table 66 to Table 37 and Table 38.
09/20/2012
1.4
In Table 1, updated the descriptions, changed VIN and Note 2, and added Note 4. In Table 2, changed
descriptions and notes. Updated parameters in Table 3. Added Table 4. Revised the Power-On/Off
Power Supply Sequencing section. Updated standards and specifications in Table 8, Table 9, and
Table 10. Removed the XC7A350T device from data sheet.
Updated the AC Switching Characteristics section to the ISE 14.2 speed specifications throughout the
document. Updated the IOB Pad Input/Output/3-State discussion and changed Table 18 by adding
T
IOIBUFDISABLE. Removed many of the combinatorial delay specifications and TCINCK/TCKCIN from
Table 27.Changed FPFDMAX conditions in Table 37 and Table 38. Updated the GTP Transceiver
Specifications section, moved the GTP Transceiver DC characteristics section to the overall DC
Characteristics section, and added the GTP Transceiver Protocol Jitter Characteristics section. In
Table 65, updated Note 1. In Table 66, updated TPOR
.
02/01/2013
1.5
Updated the AC Switching Characteristics based upon the 14.4/2012.4 device pack for ISE 14.4 and
Vivado 2012.4, both at v1.07 for the -3, -2, -2L (1.0V), -1 speed specifications, and v1.05 for the -2L
(0.9V) speed specifications throughout the document. Production changes to Table 13 and Table 14
for -3, -2, -2L (1.0V), -1 speed specifications.
Revised IDCIN and IDCOUT and added Note 5 in Table 1. Added Note 2 to Table 2. Updated Table 5.
Added minimum current specifications to Table 6. Removed SSTL12 and HSTL_I_12 from Table 8.
Removed DIFF_SSTL12 from Table 10. Updated Table 13. Added a 2:1 memory controller section to
Table 16. Updated Note 1 in Table 34. Revised Table 36. Updated Note 1 and Note 2 in Table 49.
Updated DVPPIN in Table 50. Updated VIDIFF in Table 51. Removed TLOCK and TPHASE and revised
F
V
GCLK in Table 54. Updated TDLOCK in Table 55. Updated Table 56. In Table 57, updated TRTX, TFTX,
TXOOBVDPP , and revised Note 1 through Note 7. In Table 58, updated RXSST and RXPPMTOL and
revised Note 4 through Note 7. In Table 63, revised and added Note 1.
Revised the maximum external channel input ranges in Table 65. In Table 66, revised FMCCK and
added the Internal Configuration Access Port section.
04/17/2013
1.6
Updated the AC Switching Characteristics based upon v1.07 of the ISE 14.5 and Vivado 2013.1 for the
-3, -2, -2L (1.0V), and -1 speed specifications, and v1.05 for the -2L (0.9V) speed specifications.
Production changes to Table 13 and Table 14 for -2L (0.9V) speed specifications.
In Table 1, revised VIN (I/O input voltage) to match values in Table 4 and combined Note 4 with old Note
5 and then added new Note 5. Revised VIN description, removed Note 10, and added Note 7 in Table 2.
Updated first 3 rows in Table 4. Also revised PCI33_3 voltage minimum in Table 8 to match values in
Table 1 and Table 4. Added Note 1to Table 11. RemovedNote 1 from Table 14. Updated Table 16 title.
Throughout the data sheet (Table 28, Table 29, and Table 44) removed the obvious note “A Zero “0”
Hold Time listing indicates no hold time or a negative hold time.”
09/04/2013
11/27/2013
1.7
1.8
Added new Artix-7 devices (XC7A35T, XC7A50T, and XC7A75T) throughout. In Table 1, updated IDCIN
and IDCOUT for cases when floating, at VMGTAVTT, or GND. Added back Note 1 to Table 14. Added CPG
package to Table 50 and Table 52.
Added automotive and expanded temperature range Artix-7 devices throughout. Added -1M and -1Q
speed grades throughout. Added reference to 7 Series FPGAs Overview, Defense-Grade 7 Series
FPGAs Overview, and XA Artix-7 FPGAs Overview in Introduction. In Table 2, added junction
temperature operating ranges for expanded (Q) and military (M) devices, and added Note 3. In Table 3,
removed commercial (C), industrial (I), and extended (E) from descriptions of RIN_TERM. Updated
temperature ranges in Table 4. Removed notes from Table 6. Added TJ = 125°C to Conditions column
for TVCCO2VCCAUX in Table 7. In AC Switching Characteristics, updated first paragraph, added
Table 12, and added -1Q/-1M speed grades to other tables in this section. In Table 52, added RB and
RS packages, and updated FGTPMAX. In Table 65, updated ADC Accuracy, On-Chip Sensors, XADC
Reference sections and notes. Added TUSRCCLKO and FDNACK to Table 66.
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Description
Date
Version
01/07/2014
1.9
In Table 13, promoted all XC7A75T speed grades from Advance to Production and all XQ7A50T speed
grades from Preliminary to Advance. In Table 14, inserted “Vivado tools 2013.3” for the production
XC7A75T speed grades.
01/23/2014
1.10
Updated the AC Switching Characteristics based upon ISE 14.7 and Vivado 2013.4. Updated Note 5
in Table 2. Removed pad pull-down @ VIN = 1.8V for IRPD in Table 3. Added Note 2 to Table 4.
Removed XQ7A50T fromTable 12, Table 13, and Table 14. In Table 13, changed speed grades for XA
Artix-7 FPGAs and defense-grade Artix-7Q family from -2 to -2I and -1 to -1I, and moved all speed
grades of XA7A100T, and -1I and -2I speed grades of XQ7A100T from Preliminary to Production. In
Table 14, updated production software for XA7A100T and XQ7A100T. Added HSUL_12_F,
DIFF_HSUL_12_F, MOBILE_DDR_S, MOBILE_DDR_F, DIFF_MOBILE_DDR_S, and
DIFF_MOBILE_DDR_F to Table 17. Removed introductory text in Device Pin-to-Pin Output Parameter
Guidelines.
03/04/2014
03/28/2014
1.11
1.12
Updated Note 2 in Table 4. In Table 13, moved XQ7A100T -1M speed grade from Preliminary to
Production. In Table 14, added production software for XQ7A100T -1M speed grade.
In Table 5, added ICCINTQ, ICCOQ, ICCAUXQ, and ICCBRAMQ values for XC7A35T, XC7A50T, XA7A35T,
XA7A50T, and XQ7A50T devices. In Table 6, added power-on current values for XC7A35T, XC7A50T,
XA7A35T, XA7A50T, and XQ7A50T devices. In Table 12, added row for XC7A35T, XC7A50T, and
XC7A75T devices. In Table 13, moved all speed grades of XC7A35T and XC7A50T devices from
Advance to Production, and added XQ7A50T. In Table 14, added XQ7A50T and production software
for XC7A35T and XC7A50T -3, -2, -2L (1.0V), -1, and -2L (0.9V) speed grades. For FIDELAYCTRL_REF
in Table 25, updated REFCLK frequency of 300 MHz, added REFCLK frequency of 400 MHz, and
updated Note 1. In Table 36, added TCKSKEW data for XC7A35T and XC7A50T devices. In Table 39,
updated TICKOF data for -1 and -2L (0.9V) speed grades of XC7A35T and XC7A50T devices. In
Table 40, updated TICKOFFAR data for -1 and -2L (0.9V) speed grades of XC7A35T and XC7A50T
devices. In Table 41, added TICKOFMMCMCC data for -2L (0.9V) speed grade of XC7A35T and
XC7A50T devices. In Table 42, added TICKOFPLLCC data for -2L (0.9V) speed grade of XC7A35T and
XC7A50T devices. In Table 44, updated TPSFD/TPHFD data for -2/-2L, -1, and -2L (0.9V) speed grades
of XC7A35T and XC7A50T devices. In Table 45, updated TPSMMCMCC/TPHMMCMCC data for -1 and -2L
(0.9V) speed grades of XC7A35T and XC7A50T devices. In Table 46, updated TPSPLLCC/TPHPLLCC
data for -1 and -2L (0.9V) speed grades of XC7A35T and XC7A50T devices. In Table 49, added
package skew values for XC7A35T, XC7A50T, XA7A35T, XA7A50T, and XQ7A50T devices.
05/13/2014
07/01/2014
1.13
1.14
In AC Switching Characteristics, updated to Vivado 2014.1. In Table 12, updated Vivado 2014.1
version numbers and consolidated rows. In Table 13, moved all XA7A75T speed grades from Advance
to Preliminary and all XQ7A200T speed grades from Preliminary to Production. In Table 14, added
production software for XQ7A200T -2, -1, and -1M speed grades. Added timing data for XA7A35T,
XA7A50T, XA7A75T, and XQ7A50T devices to Table 39, Table 40, Table 41, Table 42, Table 44,
Table 45, and Table 46.
Updated Note 2 in Table 4 per the customer notice XCN14014: 7 Series FPGA and Zynq-7000 AP SoC
I/O Undershoot Voltage Data Sheet Update. In Power-On/Off Power Supply Sequencing, added
sentence about there being no recommended sequence for supplies not shown. In AC Switching
Characteristics, updated to Vivado 2014.2. In Table 12, added row for XQ7A50T. In Table 13, moved
all XQ7A50T speed grades from Advance to Production. In Table 14, added production software for
XQ7A50T -2, -1, and -1M speed grades. In Table 36, added TCKSKEW values for XA7A35T, XA7A50T,
and XQ7A50T. Updated description of TICKOF in Table 39 and added Note 2. Updated description of
T
ICKOFFAR in Table 40 and added Note 2. In Table 50, moved DVPPOUT value of 1000 mV from Max to
Min column, updated VIN DC parameter description, and added Note 2. Added “peak-to-peak” to labels
in Figure 3 and Figure 4. Added note after Figure 4. Added Note 1 to Table 64. In Table 66, replaced
USRCCLK Output with STARTUPE2 Ports and added FCFGMCLK and FCFGMCLKTOL
.
09/23/2014
10/09/2014
1.15
1.16
Removed 3.3V as descriptor of HR I/O banks throughout. Updated Note 3 in Table 5. In Table 13,
moved all XA7A35T and XA7A50T speed grades from Advance to Production, and all XA7A75T speed
gradesfromPreliminarytoProduction. In Table 14, addedproductionsoftwareforXA7A35T, XA7A50T,
and XA7A75T -2, -1, and -1Q speed grades, and removed Note 2. Added I/O Standard Adjustment
Measurement Methodology.
Added XC7A15T and XA7A15T devices. Added -1LI speed grade throughout. Updated Introduction.
Added -1LI (0.95V) to description of VCCINT and VCCBRAM in Table 2. Updated Note 1 and added
Note 2 to Table 14.
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Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Date
Version
Description
11/19/2014
1.17
Replaced -2L speed grade with -2LE throughout. Updated descriptions of VCCINT and VCCBRAM in
Table 2. Updated the AC Switching Characteristics based upon Vivado 2014.4. In Table 12, updated
Vivado software version and added a row for VCCINT = 0.95V. In Table 13, moved all speed grades for
all devices from Advance to Production. In Table 14, added Vivado 2014.4 software version to -1LI
(0.95V) speed grade column for commercial devices and applicable speed grades for XC7A15T and
XA7A15T devices, and removed table notes. Added Selecting the Correct Speed Grade and Voltage
in the Vivado Tools. In Table 16, moved LPDDR2 row to end of 2:1 Memory Controllers section.
Updated speed grade heading row in Table 52.
03/18/2015
09/24/2015
1.18
1.19
In Table 11, changed maximum VICM value from 1.425V to 1.500V. Removed LVDS 1.8V standard from
Table 19 and Table 20. Removed minimum sample rate specification from Table 65.
Updated first paragraph in Introduction. Assigned quiescent supply currents to -1LI speed grade
Artix-7Q devices in Table 5. In Table 14, changed -1LI speed grade Artix-7Q device cells from N/A to
blank and added Note 1. Removed DIFF_SSTL12 standard from Table 19 and Table 20. Changed -1LI
speedgradeArtix-7QdevicecellsfromN/AtoblankinTable 36, Table 39, Table 40, Table 41, Table 42,
Table 44, Table 45, and Table 46. Added SBV484, FBV484, FBV676, and FFV1156 packages to
Table 49. Removed Pb-free G suffix from packages in Table 50 and Table 52.
11/24/2015
1.20
In AC Switching Characteristics, updated to Vivado 2015.4. In Table 13, added -1LI (0.95V) speed
gradetoProductioncolumnforXQ7A50T, XQ7A100T, andXQ7A200T. InTable 14, removedtablenote
and added Vivado 2015.4 software version to -1LI (0.95V) speed grade column for XQ7A50T,
XQ7A100T, and XQ7A200T. In Table 36, added TCKSKEW for XQ7A50T, XQ7A100T, and XQ7A200T
at -1LI (0.95V) speed grade. Updated device pin-to-pin output parameter tables (Table 39 to Table 42)
and input parameter tables (Table 44 to Table 46) for XQ7A50T, XQ7A100T, and XQ7A200T at -1LI
(0.95V) speed grade.
09/27/2016
04/13/2017
1.21
1.22
Added XC7A12T and XC7A25T devices. Updated the AC Switching Characteristics based upon
Vivado 2016.3. In Table 19, updated VMEAS values for LVCMOS 3.3V, LVTTL 3.3V, and PCI33 3.3V,
and removed note 1. Removed LVDCI_15, HSLVDCI_15, LVDCI_15, and HSLVDCI_18 I/O standards
from Table 20.
Added 1.35V to Note 5 in Table 2. Updated the AC Switching Characteristics based upon Vivado
2016.4. In Table 13, added -2LE (0.9V) speed grade to Advance column for XC7A12T and XC7A25T.
In Table 25, changed TIDELAYRESOLUTION units from ps to µs. In Table 36, updated TCKSKEW for
XC7A12T and XC7A25T devices at -2LE (0.9V) speed grade. Updated device pin-to-pin output
parametertables(Table 39toTable 42)andinputparametertables(Table 44to Table 46)forXC7A12T
and XC7A25T devices at -2LE (0.9V) speed grade. Removed SBV484, FBV484, FBV676, and
FFV1156 packages from Table 49 per the customer notice XCN16022: Cross-ship of Lead-free Bump
and Substrates in Lead-free (FFG/FBG/SBG) Packages.
12/21/2017
1.23
Updated the AC Switching Characteristics based upon Vivado 2017.4. For XC7A12T and XC7A25T in
Table 13, moved -3 and -2LE (0.9V) speed grades to Preliminary column and -2, -1, and -1LI (0.95V)
speed grades to Production column. In Table 14, added Vivado 2017.4 software version to -2, -2LE, -1,
and -1LI (0.95V) speed grade columns for XC7A12T and XC7A25T. In Table 44, updated TPSFD/ TPHFD
for XC7A12T and XC7A25T at -3, -2/-2LE, -1 and -1LI (0.95V) speed grades. In Table 46, updated
T
PSPLLCC for XC7A12T and XC7A25T at -1 and -1LI (0.95V) speed grades. In Table 49, added
package skew values for XC7A12T and XC7A25T.
04/04/2018
06/18/2018
1.24
1.25
Added XA7A12T and XA7A25T devices. Updated the AC Switching Characteristics based upon
Vivado 2018.1. In Table 13, for XC7A12T and XC7A25T moved -2LE (0.9V) speed grade to Production
column and added XA7A12T and XA7A25T with -2I, -1I, and -1Q speed grades in Production column.
Added Note 3 to Table 16.
Updated the AC Switching Characteristics based upon Vivado 2018.2. In Table 13, for XC7A12T and
XC7A25T moved -3 speed grade to Production. In Table 14, added Vivado 2018.2 software version to
-3 speed grade for XC7A12T and XC7A25T and removed note.
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63
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
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