XC95144XL-7TQG144I [XILINX]
Flash PLD, 7.5ns, 144-Cell, CMOS, PQFP144, LEAD FREE, TQFP-144;
| 型号： | XC95144XL-7TQG144I |
| 厂家： | 
XILINX, INC |
| 描述： | Flash PLD, 7.5ns, 144-Cell, CMOS, PQFP144, LEAD FREE, TQFP-144 输入元件 可编程逻辑 |
| 文件： | 总12页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XC95144XL High Performance
CPLD
0
0
DS056 (v2.0) April 3, 2007
Product Specification
54V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 5 ns. See Figure 2 for overview.
Features
•
•
•
•
5 ns pin-to-pin logic delays
Power Estimation
System frequency up to 178 MHz
144 macrocells with 3,200 usable gates
Available in small footprint packages
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
-
-
-
-
100-pin TQFP (81 user I/O pins)
144-pin TQFP (117 user I/O pins)
144-CSP (117 user I/O pins)
Pb-free available for all packages
•
•
Optimized for high-performance 3.3V systems
-
-
Low power operation
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
For a general estimate of ICC, the following equation may be
used:
I
CC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP
+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f
-
-
3.3V or 2.5V output capability
Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
where:
MCHS = # macrocells in high-speed configuration
PTHS = average number of high-speed product terms
per macrocell
MCLP = # macrocells in low power configuration
PTLP = average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
Advanced system features
-
-
In-system programmable
Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin with local
inversion
Input hysteresis on all user and boundary-scan pin
inputs
-
-
-
-
-
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
-
-
Bus-hold circuitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
•
•
•
•
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
Endurance exceeding 10,000 program/erase
cycles
-
-
20 year data retention
ESD protection exceeding 2,000V
•
Pin-compatible with 5V-core XC95144 device in the
100-pin TQFP package
WARNING: Programming temperature range of
TA = 0° C to +70° C
Description
The XC95144XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of eight
© 1998-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS056 (v2.0) April 3, 2007
www.xilinx.com
1
Product Specification
R
XC95144XL High Performance CPLD
application note XAPP114, “Understanding XC9500XL
CPLD Power.”
250
178 MHz
200
150
104 MHz
100
50
0
100
Clock Frequency (MHz)
200
50
150
Figure 1: Typical ICC vs. Frequency for XC95144XL
2
www.xilinx.com
DS056 (v2.0) April 3, 2007
Product Specification
R
XC95144XL High Performance CPLD
3
JTAG
In-System Programming Controller
1
JTAG Port
Controller
54
54
54
54
Function
Block 1
18
18
18
18
I/O
Macrocells
1 to 18
I/O
I/O
I/O
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
Function
Block 3
Macrocells
1 to 18
I/O
I/O
3
I/O/GCK
I/O/GSR
I/O/GTS
Function
Block 4
1
4
Macrocells
1 to 18
54
Function
Block 8
18
Macrocells
1 to 18
DS056_02_101300
Figure 2: XC95144XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
DS056 (v2.0) April 3, 2007
www.xilinx.com
3
Product Specification
R
XC95144XL High Performance CPLD
(2)
Absolute Maximum Ratings
Symbol
Description
Value
–0.5 to 4.0
–0.5 to 5.5
–0.5 to 5.5
–65 to +150
+150
Units
V
VCC
VIN
Supply voltage relative to GND
Input voltage relative to GND(1)
Voltage applied to 3-state output(1)
Storage temperature (ambient)(3)
Junction temperature
V
VTS
TSTG
TJ
V
oC
oC
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA. External I/O voltage may not exceed VCCINT by 4.0V.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free
packages, see XAPP427.
Recommended Operation Conditions
Symbol
Parameter
Supply voltage for internal logic
and input buffers
Min
3.0
3.0
3.0
2.3
0
Max
3.6
Units
VCCINT
Commercial TA = 0oC to 70oC
Industrial TA = –40oC to +85oC
V
V
V
V
V
V
V
3.6
VCCIO
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Low-level input voltage
3.6
2.7
VIL
VIH
VO
0.80
5.5
High-level input voltage
2.0
0
Output voltage
VCCIO
Quality and Reliability Characteristics
Symbol
Parameter
Min
20
Max
Units
TDR
Data Retention
-
-
-
Years
Cycles
Volts
NPE
Program/Erase Cycles (Endurance)
Electrostatic Discharge (ESD)
10,000
2,000
VESD
DC Characteristic Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
IOH = –4.0 mA
OH = –500 μA
IOL = 8.0 mA
OL = 500 μA
Min
Max
Units
V
VOH
Output high voltage for 3.3V outputs
Output high voltage for 2.5V outputs
Output low voltage for 3.3V outputs
Output low voltage for 2.5V outputs
Input leakage current
2.4
-
I
90% VCCIO
-
V
VOL
-
-
-
-
0.4
0.4
±10
±10
V
I
V
IIL
VCC = Max; VIN = GND or VCC
VCC = Max; VIN = GND or VCC
μA
μA
IIH
I/O high-Z leakage current
4
www.xilinx.com
DS056 (v2.0) April 3, 2007
Product Specification
R
XC95144XL High Performance CPLD
Symbol
Parameter
Test Conditions
Min
Max
Units
IIH
I/O high-Z leakage current
VCC = Max; VCCIO = Max;
-
±10
μA
VIN = GND or 3.6V
V
CC Min < VIN < 5.5V
-
-
±50
10
μA
pF
CIN
ICC
I/O capacitance
VIN = GND; f = 1.0 MHz
Operating supply current
(low power mode, active)
VIN = GND, No load; f = 1.0 MHz
45 (Typical)
mA
AC Characteristics
XC95144XL-5
XC95144XL-7
XC95144XL-10
Symbol
Parameter
Min
Max
5.0
-
Min
Max
7.5
-
Min
Max
10.0
-
Units
ns
TPD
TSU
TH
I/O to output valid
-
-
-
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
3.7
4.8
6.5
ns
0
-
0
-
0
-
ns
TCO
-
3.5
178.6
-
-
4.5
125.0
-
-
5.8
100.0
-
ns
fSYSTEM Multiple FB internal operating frequency
-
-
-
MHz
ns
TPSU
TPH
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
1.7
1.6
2.1
2.0
-
3.2
-
4.4
-
ns
TPCO
TOE
-
5.5
4.0
4.0
7.0
7.0
10.0
10.5
-
-
7.7
5.0
5.0
9.5
9.5
12.0
12.6
-
-
10.2
7.0
7.0
11.0
11.0
14.5
15.3
-
ns
GTS to output valid
-
-
-
ns
TOD
GTS to output disable
-
-
-
ns
TPOE
TPOD
TAO
Product term OE to output enabled
Product term OE to output disabled
GSR to output valid
-
-
-
-
-
-
ns
ns
-
-
-
ns
TPAO
TWLH
P-term S/R to output valid
-
-
-
ns
GCK pulse width (High or Low)
2.8
5.0
4.0
6.5
4.5
7.0
ns
TAPRPW Asynchronous preset/reset pulse width
(High or Low)
-
-
-
ns
TPLH
P-term clock pulse width (High or Low)
5.0
-
6.5
-
7.0
-
ns
V
TEST
R
1
2
Output Type
V
V
R
R
C
L
CCIO
TEST
1
2
Device Output
3.3V
3.3V
2.5V
320 Ω
250 Ω
360 Ω
660 Ω
35 pF
35 pF
2.5V
C
L
R
DS058_03_081500
Figure 3: AC Load Circuit
DS056 (v2.0) April 3, 2007
www.xilinx.com
5
Product Specification
R
XC95144XL High Performance CPLD
Internal Timing Parameters
XC95144XL-5
XC95144XL-7
XC95144XL-10
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
Buffer Delays
TIN
Input buffer delay
GCK buffer delay
-
-
-
-
-
-
1.5
1.1
2.0
4.0
2.0
0
-
-
-
-
-
-
2.3
1.5
3.1
5.0
2.5
0
-
-
-
-
-
-
3.5
1.8
4.5
7.0
3.0
0
ns
ns
ns
ns
ns
ns
TGCK
TGSR
TGTS
TOUT
TEN
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable
delay
Product Term Control Delays
TPTCK Product term clock delay
TPTSR Product term set/reset delay
-
-
-
1.6
1.0
5.5
-
-
-
2.4
1.4
7.2
-
-
-
2.7
1.8
7.5
ns
ns
ns
TPTTS
Product term 3-state delay
Internal Register and Combinatorial Delays
TPDI
TSUI
THI
Combinatorial logic propagation delay
Register setup time
-
2.3
1.4
2.3
1.4
-
0.5
-
2.6
2.2
2.6
2.2
-
1.3
-
3.0
3.5
3.0
3.5
-
1.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
Register hold time
TECSU Register clock enable setup time
TECHO Register clock enable hold time
-
-
-
-
-
-
TCOI
TAOI
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
0.4
6.0
0.5
6.4
1.0
7.0
-
-
-
TRAI
5.0
-
7.5
-
10.0
-
TLOGI
1.0
5.0
1.4
6.4
1.8
7.3
TLOGILP Internal low power logic delay
-
-
-
Feedback Delays
TF
Fast CONNECT II feedback delay
-
1.9
-
3.5
-
4.2
ns
Time Adders
TPTA
Incremental product term allocator delay
-
-
0.7
3.0
-
-
0.8
4.0
-
-
1.0
4.5
ns
ns
TSLEW Slew-rate limited delay
6
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DS056 (v2.0) April 3, 2007
Product Specification
R
XC95144XL High Performance CPLD
(2)
XC95144XL I/O Pins
Function Macro-
BScan
TQ100 TQ144 CS144 Order
Function Macro-
BScan
Block
cell
Block
cell
TQ100 TQ144 CS144 Order
1
1
-
11
12
-
23
16
17
25
19
20
-
H3
F1
G2
J1
429
426
423
420
417
414
411
408
405
402
399
396
393
390
387
384
381
378
375
372
369
366
363
360
357
354
351
348
345
342
339
336
333
330
327
324
3
1
-
23(1)
-
39
32(1)
41
M3
L1(1)
K4
N4
L2
L3
L5
N2(1)
N3
N5
M4
K5
-
321
318
315
312
309
306
303
300
297
294
291
288
285
282
279
276
273
270
267
264
261
258
255
252
249
246
243
240
237
234
231
228
225
222
219
216
1
2
3
2(1)
3
1
3
3
1
4
3
4
-
44
1
5
13
14
-
G3
G4
-
3
5
24
25
-
27(1)
28
-
33
1
6
3
6
34
1
7
3
7
8(1)
46
38(1)
1
8
15
16
-
21
22
31
24
26
-
H1
H2
K3
H4
J2
3
1
9
3
9
40
1
10
11
12
13
14
15
16
17(1)
18
1
3
10
11
12
13
14
15
16
17
18
1
48
1
17
18
-
3
29
30
-
43
1
3
45
1
-
3
-
1
19
20
-
27
28
35
30(1)
-
J3
3
32
33
-
49
K6
L6
-
1
J4
3
50
1
M1
K2(1)
-
3
-
1
22(1)
3
34
-
51
M6
-
1
-
3
-
2
-
142
143(1)
-
C3
A2(1)
-
4
-
118
126
133
-
C9
A7
A5
-
2
2(1)
99(1)
4
2
87
-
2
3
-
4
3
2
4
-
4
C1
B1(1)
C2(1)
-
4
4
-
2
5(1)
6(1)
7
1(1)
2(1)
-
3(1)
4(1)
-
2(1)
3(1)
-
5(1)
6(1)
7
4
5
89
90
-
128
129
-
D7
A6
-
2
4
6
2
4
7
2
8(1)
9(1)
10
11
12
13
14
15
16
17
18
D4(1)
D3(1)
D2
E4
E3
E1
E2
F4
F3
F2
-
4
8
91
92
-
130
131
135
132
134
137
136
138
139
140
-
B6
C6
C5
D6
B5
A4
D5
B4
C4
A3
-
2
4
9
2
4
10
11
12
13
14
15
16
17
18
2
6
9
4
93
94
-
2
7
10
12
11
13
14
15
-
4
2
-
4
2
8
4
95
96
-
2
9
4
2
-
4
2
10
-
4
97
-
2
4
Notes:
1. Global control pin.
2. The pin-outs are the same for Pb-free versions of packages.
DS056 (v2.0) April 3, 2007
www.xilinx.com
7
Product Specification
R
XC95144XL High Performance CPLD
XC95144XL (Continued)
Function Macro-
BScan
TQ100 TQ144 CS144 Order
Function Macro-
BScan
Block
cell
Block
cell
TQ100 TQ144 CS144 Order
5
1
-
-
-
N6
L8
-
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
7
1
-
50
-
-
-
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
5
2
35
-
52
59
-
7
2
71
75
-
N12
L12
-
5
3
7
3
5
4
-
7
4
-
5
5
36
37
-
53
54
66
56
57
68
58
60
70
61
64
-
M7
N7
M10
K7
N8
N11
M8
K8
L11
N9
K9
-
7
5
52
53
-
74
76
77
78
80
79
82
85
81
86
87
83
88
-
M13
L13
K10
K11
K13
K12
J11
H10
J10
H11
H12
J12
H13
-
5
6
7
6
5
7
7
7
5
8
39
40
–-
41
42
-
7
8
54
55
-
5
9
7
9
5
10
11
12
13
14
15
16
17
18
1
7
10
11
12
13
14
15
16
17
18
1
5
7
56
58
-
5
7
5
7
5
43
46
-
7
59
60
-
5
7
5
7
5
49
-
69
-
M11
-
7
61
-
5
7
6
-
-
-
8
-
-
-
6
2
74
-
106
-
C11
-
8
2
63
-
91
95
97
92
93
-
G11
F11
E13
G10
F13
-
6
3
8
3
6
4
-
111
110
112
-
B11
A12
A11
-
8
4
-
6
5
76
77
-
8
5
64
65
-
6
6
8
6
6
7
8
7
6
8
78
79
-
113
116
115
119
120
-
D10
A10
B10
B9
A9
-
8
8
66
67
-
94
96
101
98
100
103
102
104
107
105
-
F12
F10
D13
E12
E10
D11
D12
C13
B13
C12
-
6
9
8
9
6
10
11
12
13
14
15
16
17
18
8
10
11
12
13
14
15
16
17
18
6
80
81
-
8
68
70
-
6
8
6
8
6
82
85
-
121
124
117
125
-
D8
A8
D9
B7
-
8
71
72
-
6
8
6
8
6
6
86
-
8
73
-
3
6
8
0
Notes:
1. The pin-outs are the same for Pb-free versions of packages.
8
www.xilinx.com
DS056 (v2.0) April 3, 2007
Product Specification
R
XC95144XL High Performance CPLD
(1)
XC95144XL Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GTS3
I/O/GTS4
I/O/GSR
TCK
TQ100
TQ144
30
32
38
5
CS144
22
K2
23
L1
27
N2
3
D4
4
6
D3
1
2
B1
2
3
C2
99
143
67
63
122
65
A2
48
L10
TDI
45
83
L9
TDO
C8
N10
TMS
47
V
CCINT 3.3V
CCIO 2.5V/3.3V
GND
5, 57, 98
26, 38, 51, 88
8, 42, 84, 141
B3, D1, J13, L4
A1, A13, C7, L7, N1, N13
V
1, 37, 55, 73, 109, 127
21, 31, 44, 62, 69, 75, 84, 100 18, 29, 36, 47, 62, 72, 89, 90, 99, B2, B8, B12, C10, E11, G1, G12,
108, 114, 123, 144
G13, K1, M2, M5, M9, M12
No Connects
-
–
–
Notes:
1. The pin-outs are the same for Pb-free versions of packages.
DS056 (v2.0) April 3, 2007
www.xilinx.com
9
Product Specification
R
XC95144XL High Performance CPLD
Device Part Marking and Ordering Combination Information.
R
Device Type
Package
XC95xxxXL
TQ144
This line not
related to device
part number
Speed
7C
Operating Range
1
Sample package with part marking.
Speed
Device Ordering and
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins
Operating
Range(1)
Part Marking Number
XC95144XL-5TQ100C
XC95144XL-5TQ144C
XC95144XL-5CS144C
XC95144XL-7TQ100C
XC95144XL-7TQ144C
XC95144XL-7CS144C
XC95144XL-7TQ100I
XC95144XL-7TQ144I
XC95144XL-7CS144I
XC95144XL-10TQ100C
XC95144XL-10TQ144C
XC95144XL-10CS144C
XC95144XL-10TQ100I
XC95144XL-10TQ144I
XC95144XL-10CS144I
XC95144XL-5TQG100C
XC95144XL-5TQG144C
XC95144XL-5CSG144C
XC95144XL-7TQG100C
XC95144XL-7TQG144C
XC95144XL-7CSG144C
XC95144XL-7TQG100I
XC95144XL-7TQG144I
XC95144XL-7CSG144I
Package Type
5 ns
5 ns
TQ100 100-pin
TQ144 144-pin
CS144 144-ball
TQ100 100-pin
TQ144 144-pin
CS144 144-ball
TQ100 100-pin
TQ144 144-pin
CS144 144-ball
TQ100 100-pin
TQ144 144-pin
CS144 144-ball
TQ100 100-pin
TQ144 144-pin
CS144 144-ball
TQG100 100-pin
TQG144 144-pin
CSG144 144-ball
TQG100 100-pin
TQG144 144-pin
CSG144 144-ball
TQG100 100-pin
TQG144 144-pin
CSG144 144-ball
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP)
C
C
C
C
C
C
I
5 ns
Chip Scale Package (CSP)
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
5 ns
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP)
Chip Scale Package (CSP)
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP)
I
Chip Scale Package (CSP)
I
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP)
C
C
C
I
Chip Scale Package (CSP)
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP)
I
Chip Scale Package (CSP)
I
Thin Quad Flat Pack (TQFP); Pb-free
Thin Quad Flat Pack (TQFP); Pb-free
Chip Scale Package (CSP); Pb-free
Thin Quad Flat Pack (TQFP); Pb-free
Thin Quad Flat Pack (TQFP); Pb-free
Chip Scale Package (CSP); Pb-free
Thin Quad Flat Pack (TQFP); Pb-free
Thin Quad Flat Pack (TQFP); Pb-free
Chip Scale Package (CSP); Pb-free
C
C
C
C
C
C
I
5 ns
5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
I
I
10
www.xilinx.com
DS056 (v2.0) April 3, 2007
Product Specification
R
XC95144XL High Performance CPLD
Operating
Speed
(pin-to-pin
delay)
Device Ordering and
Part Marking Number
Pkg.
Symbol
No. of
Pins
Package Type
Range(1)
XC95144XL-10TQG100C
XC95144XL-10TQG144C
XC95144XL-10CSG144C
XC95144XL-10TQG100I
XC95144XL-10TQG144I
XC95144XL-10CSG144I
Notes:
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
TQG100 100-pin
TQG144 144-pin
CSG144 144-ball
TQG100 100-pin
TQG144 144-pin
CSG144 144-ball
Thin Quad Flat Pack (TQFP); Pb-free
Thin Quad Flat Pack (TQFP); Pb-free
Chip Scale Package (CSP); Pb-free
Thin Quad Flat Pack (TQFP); Pb-free
Thin Quad Flat Pack (TQFP); Pb-free
Chip Scale Package (CSP); Pb-free
C
C
C
I
I
I
1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C
Pb-
-4 TQ
G
144
C
XC95144XL
Free Example:
Standard Example: XC95144XL -4 TQ 144
C
Device
Device
Speed Grade
Package Type
Speed Grade
Package Type
Number of Pins
Temperature Range
-Free
Pb
Number of Pins
Temperature Range
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Further Reading
The following Xilinx links go to relevant XC9500XL CPLD documentation, including XAPP111, Using the XC9500XL Timing
Model, and XAPP784, Bulletproof CPLD Design Practices. Simply click on the link and scroll down.
Data Sheets, Application Notes, and White Papers.
Packaging
DS056 (v2.0) April 3, 2007
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11
Product Specification
R
XC95144XL High Performance CPLD
Revision History
The following table shows the revision history for this document.
Date
Version
1.1
Revision
Minor corrections to CS144 pinout table.
10/30/98
11/13/98
06/20/02
1.2
V1.2 minor correction in CS144 pinout table.
1.3
Updated ICC equation, page 1. Updated DC Characteristics: ICC to 45 (typical). Updated
Component Availability chart.Added additional IIH test conditions and measurements to DC
Characteristics table.
06/20/03
08/21/03
07/15/04
09/15/04
07/15/05
03/22/06
04/03/07
1.4
1.5
1.6
1.7
1.8
1.9
2.0
Updated TSOL from 260 to 220oC. Added Part Marking and updated Ordering Information.
Updated Package Device Marking Pin 1 orientation.
Added Pb-free documentation
Added TAPRPW specification to AC Characteristics.
Move to Product Specification
Add Warranty Disclaimer.
Add programming temperature range warning on page 1.
12
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DS056 (v2.0) April 3, 2007
Product Specification
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