XC9572-7PCG84C [XILINX]
Flash PLD, 7.5ns, 72-Cell, CMOS, PQCC84, LEAD FREE, PLASTIC, LCC-84;
| 型号： | XC9572-7PCG84C |
| 厂家： | 
XILINX, INC |
| 描述： | Flash PLD, 7.5ns, 72-Cell, CMOS, PQCC84, LEAD FREE, PLASTIC, LCC-84 时钟 输入元件 可编程逻辑 |
| 文件： | 总10页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XC9536XL High Performance
CPLD
0
0
DS058 (v1.9) April 3, 2007
Product Specification
54V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for architecture
overview.
Features
•
•
•
•
5 ns pin-to-pin logic delays
System frequency up to 178 MHz
36 macrocells with 800 usable gates
Available in small footprint packages
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
-
-
-
-
-
44-pin PLCC (34 user I/O pins)
44-pin VQFP (34 user I/O pins)
48-pin CSP (36 user I/O pins)
64-pin VQFP (36 user I/O pins)
Pb-free available for all packages
•
•
Optimized for high-performance 3.3V systems
-
-
Low power operation
5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V
signals
For a general estimate of ICC, the following equation may be
used:
I
CC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP
+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f
-
-
3.3V or 2.5V output capability
Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
where:
MCHS = # macrocells in high-speed configuration
Advanced system features
PTHS = average number of high-speed product terms
per macrocell
MCLP = # macrocells in low power configuration
PTLP = average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
-
-
In-system programmable
Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
-
-
-
-
-
Individual output enable per output pin
Input hysteresis on all user and boundary-scan pin
inputs
Bus-hold circuitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
-
-
•
•
•
•
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
Endurance exceeding 10,000 program/erase
cycles
-
-
20 year data retention
ESD protection exceeding 2,000V
•
Pin-compatible with 5V-core XC9536 device in the
44-pin PLCC package and the 48-pin CSP package
WARNING: Programming temperature range of
TA = 0° C to +70° C
Description
The XC9536XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of two
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS058 (v1.9) April 3, 2007
www.xilinx.com
1
Product Specification
R
XC9536XL High Performance CPLD
application note XAPP114, “Understanding XC9500XL
CPLD Power.”
70
60
178 MHz
rmance
50
40
rfo
Pe
ow
gh
i
H
wer
o
30
20
P
125 MHz
L
10
0
100
Clock Frequency (MHz)
200
250
50
150
DS058_01_121501
Figure 1: Typical ICC vs. Frequency for XC9536XL
3
JTAG
In-System Programming Controller
1
JTAG Port
Controller
54
Function
18
18
Block 1
I/O
Macrocells
1 to 18
I/O
I/O
I/O
54
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
I/O
I/O
3
I/O/GCK
I/O/GSR
I/O/GTS
1
2
DS058_02_081500
Figure 2: XC9536XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
2
www.xilinx.com
DS058 (v1.9) April 3, 2007
Product Specification
R
XC9536XL High Performance CPLD
(2)
Absolute Maximum Ratings
Symbol
Description
Value
–0.5 to 4.0
–0.5 to 5.5
–0.5 to 5.5
–65 to +150
+150
Units
V
VCC
VIN
Supply voltage relative to GND
Input voltage relative to GND(1)
Voltage applied to 3-state output(1)
Storage temperature (ambient)(3)
Junction temperature
V
VTS
TSTG
TJ
V
oC
oC
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA. External I/O voltage may not exceed VCCINT by 4.0V.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free
packages, see XAPP427.
Recommended Operation Conditions
Symbol
Parameter
Supply voltage for internal logic
and input buffers
Min
3.0
3.0
3.0
2.3
0
Max
3.6
Units
VCCINT
Commercial TA = 0oC to 70oC
Industrial TA = –40oC to +85oC
V
V
V
V
V
V
V
3.6
VCCIO
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Low-level input voltage
3.6
2.7
VIL
VIH
VO
0.80
5.5
High-level input voltage
2.0
0
Output voltage
VCCIO
Quality and Reliability Characteristics
Symbol
Parameter
Min
20
Max
Units
TDR
Data Retention
-
-
-
Years
Cycles
Volts
NPE
Program/Erase Cycles (Endurance)
Electrostatic Discharge (ESD)
10,000
2,000
VESD
DC Characteristic Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
IOH = –4.0 mA
OH = –500 μA
IOL = 8.0 mA
OL = 500 μA
VCC = Max; VIN = GND or VCC
VCC = Max; VIN = GND or VCC
VCC = Max; VCCIO = Max;
Min
Max
Units
V
VOH
Output high voltage for 3.3V outputs
Output high voltage for 2.5V outputs
Output low voltage for 3.3V outputs
Output low voltage for 2.5V outputs
Input leakage current
2.4
-
I
90% VCCIO
-
V
VOL
-
-
-
-
-
0.4
0.4
±10
±10
±10
V
I
V
IIL
IIH
IIH
μA
μA
μA
I/O high-Z leakage current
I/O high-Z leakage current
VIN = GND or 3.6V
V
CC Min < VIN < 5.5V
-
-
±50
10
μA
pF
CIN
ICC
I/O capacitance
VIN = GND; f = 1.0 MHz
Operating supply current
(low power mode, active)
VIN = GND, No load; f = 1.0 MHz
10 (Typical)
mA
DS058 (v1.9) April 3, 2007
www.xilinx.com
3
Product Specification
R
XC9536XL High Performance CPLD
AC Characteristics
XC9536XL-5
XC9536XL-7
XC9536XL-10
Symbol
TPD
Parameter
Min
Max
5.0
-
Min
Max
7.5
-
Min
Max Units
I/O to output valid
-
-
-
10.0
-
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSU
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
3.7
4.8
6.5
TH
0
-
0
-
0
-
TCO
-
3.5
178.6
-
-
4.5
125
-
-
5.8
100
-
fSYSTEM Multiple FB internal operating frequency
TPSU I/O setup time before p-term clock input
-
1.7
2.0
-
-
1.6
3.2
-
-
2.1
4.4
-
TPH
I/O hold time after p-term clock input
-
-
-
TPCO P-term clock output valid
5.5
4.0
4.0
7.0
7.0
10.0
10.5
-
7.7
5.0
5.0
9.5
9.5
12.0
12.6
-
10.2
7.0
7.0
11.0
11.0
14.5
15.3
-
TOE
TOD
GTS to output valid
-
-
-
GTS to output disable
-
-
-
TPOE Product term OE to output enabled
TPOD Product term OE to output disabled
-
-
-
-
-
-
TAO
GSR to output valid
-
-
-
TPAO P-term S/R to output valid
-
-
-
TWLH GCK pulse width (High or Low)
2.8
5.0
5.0
4.0
6.5
6.5
4.5
7.0
7.0
TAPRPW Asynchronous preset/reset pulse width (High or Low)
TPLH P-term clock pulse width (High or Low)
-
-
-
-
-
-
V
TEST
R
1
2
Output Type
V
V
R
R
C
CCIO
TEST
1
2
L
Device Output
3.3V
2.5V
3.3V
2.5V
320 Ω
250 Ω
360 Ω
660 Ω
35 pF
35 pF
C
L
R
DS058_03_081500
Figure 3: AC Load Circuit
4
www.xilinx.com
DS058 (v1.9) April 3, 2007
Product Specification
R
XC9536XL High Performance CPLD
Internal Timing Parameters
XC9536XL-5
XC9536XL-7
XC9536XL-10
Symbol
Parameter
Min
Max
Min
Max
Min
Max Units
Buffer Delays
TIN
Input buffer delay
-
-
-
-
-
-
1.5
1.1
2.0
4.0
2.0
0
-
-
-
-
-
-
2.3
1.5
3.1
5.0
2.5
0
-
-
-
-
-
-
3.5
1.8
4.5
7.0
3.0
0
ns
ns
ns
ns
ns
ns
TGCK GCK buffer delay
TGSR GSR buffer delay
TGTS GTS buffer delay
TOUT Output buffer delay
TEN
Output buffer enable/disable delay
Product Term Control Delays
TPTCK Product term clock delay
TPTSR Product term set/reset delay
TPTTS Product term 3-state delay
Internal Register and Combinatorial Delays
TPDI Combinatorial logic propagation delay
TSUI Register setup time
-
-
-
1.6
1.0
5.5
-
-
-
2.4
1.4
7.2
-
-
-
2.7
1.8
7.5
ns
ns
ns
-
2.3
1.4
2.3
1.4
-
0.5
-
2.6
2.2
2.6
2.2
-
1.3
-
3.0
3.5
3.0
3.5
-
1.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
THI
Register hold time
TECSU Register clock enable setup time
TECHO Register clock enable hold time
TCOI Register clock to output valid time
TAOI Register async. S/R to output delay
TRAI Register async. S/R recover before clock
TLOGI Internal logic delay
-
-
-
-
-
-
0.4
6.0
0.5
6.4
1.0
7.0
-
-
-
5.0
-
7.5
-
10.0
-
1.0
5.0
1.4
6.4
1.8
7.3
TLOGILP Internal low power logic delay
Feedback Delays
-
-
-
TF
Fast CONNECT II feedback delay
-
1.9
-
3.5
-
4.2
ns
Time Adders
TPTA Incremental product term allocator delay
TSLEW Slew-rate limited delay
-
-
0.7
3.0
-
-
0.8
4.0
-
-
1.0
4.5
ns
ns
DS058 (v1.9) April 3, 2007
www.xilinx.com
5
Product Specification
R
XC9536XL High Performance CPLD
(2)
XC9536XL I/O Pins
Function Macro-
BScan
PC44 VQ44 CS48 VQ64 Order
Function Macro-
BScan
Block
cell
Block
cell
PC44 VQ44 CS48 VQ64 Order
1
1
2
3
5(1)
40
41
D6
C7
9
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
2
1
1
39
38
D7
E5
8
7
5(1)
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
1
2
10
2
2
44
1
3
43(1) B7(1) 15(1)
42 C6 11
44(1) B6(1) 16(1)
2
3
42(1) 36(1) E6(1)
43 37 E7
40(1) 34(1) F6(1)
1
4
4
2
4
6
2(1)
1
5
6(1)
8
7(1)
2
5
1
6
2
1(1)
3
A6
19
2
6
39(1) 33(1) G7(1) 64(1)
1
7
A7(1) 17(1)
2
7
38
37
36
35
34
33
29
28
27
26
25
-
32
31
30
29
28
27
23
22
21
20
19
-
G6
F5
G5
F4
G4
E3
F2
G1
F1
E2
E1
E4
63
62
61
60
57
56
50
48
45
44
43
49
1
8
9
C5
B5
A4
B4
A3
B2
B1
C2
C3
D2
D3
20
22
24
25
27
33
35
36
38
42
39
2
8
1
9
11
12
13
14
18
19
20
22
24
-
5
2
9
1
10
11
12
13
14
15
16
17
18
6
2
10
11
12
13
14
15
16
17
18
1
7
2
1
8
2
1
12
13
14
16
18
-
2
1
2
1
2
1
2
6
1
2
3
1
2
0
Notes:
1. Global control pin.
2. The pin-outs are the same for Pb-free versions of packages.
(1)
XC9536XL Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR
TCK
PC44
VQ44
43
CS48
B7
VQ64
5
15
6
44
B6
16
7
1
A7
17
42
36
E6
5
40
34
F6
2
64
39
33
G7
17
11
A1
30
TDI
15
9
B3
28
TDO
30
24
G2
53
TMS
16
21, 41
32
10
A2
29
V
CCINT 3.3V
CCIO 2.5V/3.3V
GND
15, 35
26
C1, F7
G3
3, 37
55
V
10, 23, 31
-
4, 17, 25
-
A5, D1, F3
C4, D4
21, 41, 54
No Connects
1, 4, 12, 13, 14, 18,
23, 26, 31, 32, 34, 40,
46, 47, 51, 52, 58, 59
Notes:
1. The pin-outs are the same for Pb-free versions of packages.
6
www.xilinx.com
DS058 (v1.9) April 3, 2007
Product Specification
R
XC9536XL High Performance CPLD
Device Part Marking and Ordering Combination Information
R
Device Type
Package
XC95xxxXL
TQ144
This line not
related to device
part number
Speed
7C
Operating Range
1
Sample package with part marking.
Notes:
1. Due to the small size of chip scale packages, part marking on these packages does not follow the above
sample and the complete part number cannot be included in the marking. Part marking on chip scale
packages by line:
·
·
·
·
Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 95xxxXL.
Line 2 = Not related to device part number.
Line 3 = Not related to device part number.
Line 4 = Package code, speed, operating temperature, three digits not related to part
number. Package codes: C1 = CS48, C2 = CSG48.
Speed
Device Ordering and
Part Marking Number
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins
Operating
Range(1)
Package Type
Plastic Lead Chip Carrier (PLCC)
Quad Flat Pack (VQFP)
XC9536XL-5PC44C
XC9536XL-5VQ44C
XC9536XL-5CS48C
XC9536XL-5VQ64C
XC9536XL-7PC44C
XC9536XL-7VQ44C
XC9536XL-7CS48C
XC9536XL-7VQ64C
XC9536XL-7PC44I
XC9536XL-7VQ44I
XC9536XL-7CS48I
XC9536XL-7VQ64I
XC9536XL-10PC44C
XC9536XL-10VQ44C
XC9536XL-10CS48C
XC9536XL-10VQ64C
XC9536XL-10PC44I
XC9536XL-10VQ44I
XC9536XL-10CS48I
XC9536XL-10VQ64I
XC9536XL-5PCG44C
XC9536XL-5VQG44C
5 ns
5 ns
PC44
VQ44
CS48
VQ64
PC44
VQ44
CS48
VQ64
PC44
VQ44
CS48
VQ64
PC44
VQ44
CS48
VQ64
PC44
VQ44
CS48
VQ64
PCG44
44-pin
44-pin
48-ball
64-pin
44-pin
44-pin
48-ball
64-pin
44-pin
44-pin
48-ball
64-pin
44-pin
44-pin
48-ball
64-pin
44-pin
44-pin
48-ball
64-pin
44-pin
C
C
C
C
C
C
C
C
I
5 ns
Chip Scale Package (CSP)
Quad Flat Pack (VQFP)
5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
5 ns
Plastic Lead Chip Carrier (PLCC)
Quad Flat Pack (VQFP)
Chip Scale Package (CSP)
Quad Flat Pack (VQFP)
Plastic Lead Chip Carrier (PLCC)
Quad Flat Pack (VQFP)
I
Chip Scale Package (CSP)
Quad Flat Pack (VQFP)
I
I
Plastic Lead Chip Carrier (PLCC)
Quad Flat Pack (VQFP)
C
C
C
C
I
Chip Scale Package (CSP)
Quad Flat Pack (VQFP)
Plastic Lead Chip Carrier (PLCC)
Quad Flat Pack (VQFP)
I
Chip Scale Package (CSP)
Quad Flat Pack (VQFP)
I
I
Plastic Lead Chip Carrier (PLCC); Pb-free
Quad Flat Pack (VQFP); Pb-free
C
C
5 ns
VQG44 44-pin
DS058 (v1.9) April 3, 2007
www.xilinx.com
7
Product Specification
R
XC9536XL High Performance CPLD
Speed
Device Ordering and
Part Marking Number
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins
Operating
Range(1)
Package Type
XC9536XL-5CSG48C
XC9536XL-5VQG64C
XC9536XL-7PCG44C
XC9536XL-7VQG44C
XC9536XL-7CSG48C
XC9536XL-7VQG64C
XC9536XL-7PCG44I
XC9536XL-7VQG44I
XC9536XL-7CSG48I
XC9536XL-7VQG64I
XC9536XL-10PCG44C
XC9536XL-10VQG44C
XC9536XL-10CSG48C
XC9536XL-10VQG64C
XC9536XL-10PCG44I
XC9536XL-10VQG44I
XC9536XL-10CSG48I
XC9536XL-10VQG64I
Notes:
5 ns
CSG48 48-ball
VQG64 64-pin
Chip Scale Package (CSP); Pb-free
Quad Flat Pack (VQFP); Pb-free
Plastic Lead Chip Carrier (PLCC); Pb-free
Quad Flat Pack (VQFP); Pb-free
Chip Scale Package (CSP); Pb-free
Quad Flat Pack (VQFP); Pb-free
Plastic Lead Chip Carrier (PLCC); Pb-free
Quad Flat Pack (VQFP); Pb-free
Chip Scale Package (CSP); Pb-free
Quad Flat Pack (VQFP); Pb-free
Plastic Lead Chip Carrier (PLCC); Pb-free
Quad Flat Pack (VQFP); Pb-free
Chip Scale Package (CSP); Pb-free
Quad Flat Pack (VQFP); Pb-free
Plastic Lead Chip Carrier (PLCC); Pb-free
Quad Flat Pack (VQFP); Pb-free
Chip Scale Package (CSP); Pb-free
Quad Flat Pack (VQFP); Pb-free
C
C
C
C
C
C
I
5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
PCG44
44-pin
VQG44 44-pin
CSG48 48-ball
VQG64 64-pin
PCG44
44-pin
VQG44 44-pin
CSG48 48-ball
VQG64 64-pin
I
I
I
PCG44
44-pin
C
C
C
C
I
VQG44 44-pin
CSG48 48-ball
VQG64 64-pin
PCG44
44-pin
VQG44 44-pin
CSG48 48-ball
VQG64 64-pin
I
I
I
1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C.
Pb-
XC9536XL -4 TQ
G
144
C
Free Example:
Standard Example: XC9536XL -4 TQ 144
C
Device
Device
Speed Grade
Package Type
Speed Grade
Package Type
Number of Pins
Temperature Range
-Free
Pb
Number of Pins
Temperature Range
8
www.xilinx.com
DS058 (v1.9) April 3, 2007
Product Specification
R
XC9536XL High Performance CPLD
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Further Reading
The following Xilinx links go to relevant XC9500XL CPLD documentation, including XAPP111, Using the XC9500XL Timing
Model, and XAPP784, Bulletproof CPLD Design Practices. Simply click on the link and scroll down.
Data Sheets, Application Notes, and White Papers.
Packaging
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
09/28/98
08/28/00
06/20/02
Initial Xilinx release.
1.1
Added VQ44 package.
1.2
Updated ICC equation, page 1. Removed -4 device. Added industrial availability to -7
device. Added additional IIH test conditions and measurements to DC Characteristics table.
06/18/03
1.3
Updated TSOL from 260 to 220oC. Added Device Part Marking and updated Ordering
Information.
08/21/03
07/15/04
09/15/04
07/15/05
03/22/06
04/03/07
1.4
1.5
1.6
1.7
1.8
1.9
Updated Package Device Marking Pin 1 orientation.
Added Pb-free documentation
Added TAPRPW specification to AC Characteristics.
Move to Product Specification
Add Warranty Disclaimer.
Add programming temperature range warning on page 1.
DS058 (v1.9) April 3, 2007
www.xilinx.com
9
Product Specification
R
XC9536XL High Performance CPLD
10
www.xilinx.com
DS058 (v1.9) April 3, 2007
Product Specification
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