XCF32PVG_技术文档

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Platform Flash In-System Programmable

Configuration PROMS

0

DS123 (v2.6) March 14, 2005

Preliminary Product Specification

Features

•

In-System Programmable PROMs for Configuration of

Xilinx FPGAs

•

XCF01S/XCF02S/XCF04S

-

3.3V supply voltage

•

Low-Power Advanced CMOS NOR FLASH Process

Endurance of 20,000 Program/Erase Cycles

Serial FPGA configuration interface (up to 33 MHz)

Available in small-footprint VO20 and VOG20

packages.

Operation over Full Industrial Temperature Range

(–40°C to +85°C)

XCF08P/XCF16P/XCF32P

-

1.8V supply voltage

Serial or parallel FPGA configuration interface

(up to 33 MHz)

Available in small-footprint VO48, VOG48, FS48,

and FSG48 packages

Design revision technology enables storing and

accessing multiple design revisions for

configuration

•

IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)

Support for Programming, Prototyping, and Testing

JTAG Command Initiation of Standard FPGA

Configuration

-

•

Cascadable for Storing Longer or Multiple Bitstreams

Dedicated Boundary-Scan (JTAG) I/O Power Supply

(V_CCJ

)

•

I/O Pins Compatible with Voltage Levels Ranging From

1.5V to 3.3V

-

Built-in data decompressor compatible with Xilinx

advanced compression technology

Design Support Using the Xilinx Alliance ISE and

Foundation ISE Series Software Packages

Table 1: Platform Flash PROM Features

JTAG ISP

Serial Parallel

Design

Density

V

Range

V Range

CCJ

Packages

Compression

CCINT

CCO

Programming Config. Config. Revisioning

XCF01S 1 Mbit

XCF02S 2 Mbit

XCF04S 4 Mbit

3.3V

VO20/VOG20

1.8V - 3.3V 2.5V - 3.3V

√

VO48/VOG48

FS48/FSG48

XCF08P 8 Mbit

XCF16P 16 Mbit

XCF32P 32 Mbit

1.8V

1.5V - 3.3V 2.5V - 3.3V

√

VO48/VOG48

FS48/FSG48

1.5V - 3.3V

2.5V - 3.3V

VO48/VOG48

FS48/FSG48

1.5V - 3.3V 2.5V - 3.3V

Description

Xilinx introduces the Platform Flash series of in-system pro-

grammable configuration PROMs. Available in 1 to 32

Megabit (Mbit) densities, these PROMs provide an

easy-to-use, cost-effective, and reprogrammable method

for storing large Xilinx FPGA configuration bitstreams. The

Platform Flash PROM series includes both the 3.3V

XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS

version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that

support Master Serial and Slave Serial FPGA configuration

modes (Figure 1). The XCFxxP version includes 32-Mbit,

16-Mbit, and 8-Mbit PROMs that support Master Serial,

Slave Serial, Master SelectMAP, and Slave SelectMAP

FPGA configuration modes (Figure 2). A summary of the

Platform Flash PROM family members and supported fea-

tures is shown in Table 1.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS123 (v2.6) March 14, 2005

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Preliminary Product Specification

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Platform Flash In-System Programmable Configuration PROMS

CLK CE

OE/RESET

TCK

TMS

TDI

Data

Control

and

JTAG

CEO

Serial

Memory

Interface

Data

DATA (D0)

Serial Mode

Address

Interface

TDO

CF

ds123_01_30603

Figure 1: XCFxxS Platform Flash PROM Block Diagram

FI

CLK CE

EN_EXT_SEL

OE/RESET BUSY

CLKOUT

CEO

OSC

Control

and

JTAG

Serial

or

Parallel

Interface

TCK

TMS

TDI

Data

Memory

DATA (D0)

(Serial/Parallel Mode)

Address

TDO

Interface

Data

Decompressor

D[1:7]

(Parallel Mode)

ds123_19_050604

CF

REV_SEL [1:0]

Figure 2: XCFxxP Platform Flash PROM Block Diagram

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. With CF High, a

short access time after CE and OE are enabled, data is

available on the PROM DATA (D0) pin that is connected to

the FPGA DIN pin. New data is available a short access

time after each rising clock edge. The FPGA generates the

appropriate number of clock pulses to complete the config-

uration.

CF High, after CE and OE are enabled, data is available on

the PROMs DATA (D0-D7) pins. New data is available a

short access time after each rising clock edge. The data is

clocked into the FPGA on the following rising edge of the

CCLK. A free-running oscillator can be used in the Slave

Parallel /Slave SelecMAP mode.

The XCFxxP version of the Platform Flash PROM provides

additional advanced features. A built-in data decompressor

supports utilizing compressed PROM files, and design revi-

sioning allows multiple design revisions to be stored on a

single PROM or stored across several PROMs. For design

revisioning, external pins or internal control bits are used to

select the active design revision.

When the FPGA is in Slave Serial mode, the PROM and the

FPGA are both clocked by an external clock source, or

optionally, for the XCFxxP PROM only, the PROM can be

used to drive the FPGA’s configuration clock.

The XCFxxP version of the Platform Flash PROM also sup-

ports Master SelectMAP and Slave SelectMAP (or Slave

Parallel) FPGA configuration modes. When the FPGA is in

Master SelectMAP mode, the FPGA generates a configura-

tion clock that drives the PROM. When the FPGA is in Slave

SelectMAP Mode, either an external oscillator generates

the configuration clock that drives the PROM and the

FPGA, or optionally, the XCFxxP PROM can be used to

drive the FPGA’s configuration clock. With BUSY Low and

Multiple Platform Flash PROM devices can be cascaded to

support the larger configuration files required when target-

ing larger FPGA devices or targeting multiple FPGAs daisy

chained together. When utilizing the advanced features for

the XCFxxP Platform Flash PROM, such as design revi-

sioning, programming files which span cascaded PROM

devices can only be created for cascaded chains containing

only XCFxxP PROMs. If the advanced XCFxxP features are

DS123 (v2.6) March 14, 2005

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2

Preliminary Product Specification

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Platform Flash In-System Programmable Configuration PROMS

not enabled, then the cascaded chain can include both

XCFxxP and XCFxxS PROMs.

Table 2: Xilinx FPGAs and Compatible Platform Flash

PROMs (Continued)

Configuration

Bitstream

Platform Flash

PROM⁽¹⁾

The Platform Flash PROMs are compatible with all of the

existing FPGA device families. A reference list of Xilinx

FPGAs and the respective compatible Platform Flash

PROMs is given in Table 2. A list of Platform Flash PROMs

and their capacities is given in Table 3.

FPGA

XC2V250

1,697,184

2,761,888

4,082,592

5,659,296

7,492,000

10,494,368

15,659,936

21,849,504

29,063,072

XCF02S

XCF04S

XCF08P

XCF16P

XCF32P

XC2V500

XC2V1000

XC2V1500

XC2V2000

XC2V3000

XC2V4000

XC2V6000

XC2V8000

Virtex-E

XCV50E

Table 2: Xilinx FPGAs and Compatible Platform Flash

PROMs

Configuration

Bitstream

Platform Flash

PROM⁽¹⁾

FPGA

Virtex-4 LX

XC4VLX15

XC4VLX25

XC4VLX40

XC4VLX60

XC4VLX80

XC4VLX100

XC4VLX160

XC4VLX200

Virtex-4 FX

XC4VFX12

XC4VFX20

XC4VFX40

XC4VFX60

XC4VFX100

XC4VFX140

Virtex-4 SX

XC4VSX25

XC4VSX35

XC4VSX55

Virtex-II Pro X

XC2VPX20

XC2VPX70

Virtex-II Pro

XC2VP2

XCF08P

4,765,185

7,819,520

XCF16P

12,259,328

17,717,248

23,290,624

30,711,296

40,346,624

48,722,432

630,048

863,840

XCF01S

XCF02S

XCF04S

XCF08P

XCF16P

XCF32P

XCV100E

XCV200E

XCV300E

XCV400E

XCV405E

XCV600E

XCV812E

XCV1000E

XCV1600E

XCV2000E

XCV2600E

XCV3200E

Virtex

XCF32P

1,442,016

1,875,648

2,693,440

3,430,400

3,961,632

6,519,648

6,587,520

8,308,992

10,159,648

12,922,336

16,283,712

XCF32P

XCF32P+XCF08P

XCF32P+XCF16P

XCF08P

4,765,184

7,242,240

XCF16P

13,550,336

21,002,496

33,065,024

47,856,512

XCF32P

XCF32P+XCF16P

XCV50

559,200

781,216

XCF01S

XCF02S

XCF04S

XCF08P

XCF16P

XCF32P

9,147,264

13,669,904

22,744,832

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

XCV1000

Spartan-3E

1,040,096

1,335,840

1,751,808

2,546,048

3,607,968

4,715,616

6,127,744

XCF08P

XCF32P

8,214,560

26,098,976

1,305,376

3,006,496

4,485,408

8,214,560

11,589,920

15,868,192

19,021,344

26,098,976

34,292,768

XCF02S

XCF04S

XCF08P

XCF16P

XCF32P

XCF32P⁽²⁾

XC2VP4

XC2VP7

XCF01S

XCF02S

XCF04S

XCF08P

XC3S100E

XC3S250E

XC3S500E

XC3S1200E

XC3S1600E

Spartan-3L

XC3S1000L

XC3S1500L

XC3S5000L

581,344

1,352,192

2,267,136

3,832,320

5,957,760

XC2VP20

XC2VP30

XC2VP40

XC2VP50

XC2VP70

XC2VP100

Virtex-II ⁽³⁾

XC2V40

XCF04S

XCF08P

XCF16P

3,223,488

5,214,784

13,271,936

360,096

635,296

XCF01S

XC2V80

DS123 (v2.6) March 14, 2005

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Preliminary Product Specification

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Platform Flash In-System Programmable Configuration PROMS

Table 2: Xilinx FPGAs and Compatible Platform Flash

PROMs (Continued)

programming data sequence is delivered to the device

using either Xilinx iMPACT software and a Xilinx download

cable,

a

third-party JTAG development system,

a

Configuration

Bitstream

Platform Flash

PROM⁽¹⁾

JTAG-compatible board tester, or a simple microprocessor

interface that emulates the JTAG instruction sequence. The

iMPACT software also outputs serial vector format (SVF)

files for use with any tools that accept SVF format, including

automatic test equipment. During in-system programming,

the CEO output is driven High. All other outputs are held in

a high-impedance state or held at clamp levels during

in-system programming. In-system programming is fully

supported across the recommended operating voltage and

temperature ranges.

FPGA

Spartan-3

XC3S50

439,264

1,047,616

1,699,136

3,223,488

5,214,784

7,673,024

11,316,864

13,271,936

XCF01S

XCF02S

XCF04S

XCF08P

XCF16P

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

Spartan-IIE

XC2S50E

XC2S100E

XC2S150E

XC2S200E

XC2S300E

XC2S400E

XC2S600E

Spartan-II

XC2S15

630,048

863,840

XCF01S

XCF02S

XCF04S

1,134,496

1,442,016

1,875,648

2,693,440

3,961,632

(a)

(b)

DS026_02_082703

197,696

336,768

XCF01S

XCF02S

XC2S30

Figure 3: JTAG In-System Programming Operation

(a) Solder Device to PCB

XC2S50

559,200

(b) Program Using Download Cable

XC2S100

XC2S150

XC2S200

Notes:

781,216

1,040,096

1,335,840

OE/RESET

The 1/2/4 Mbit XCFxxS Platform Flash PROMs in-system

programming algorithm results in issuance of an internal

device reset that causes OE/RESET to pulse Low.

1. If design revisioning or other advanced feature support is required,

the XCFxxP can be used as an alternative to the XCF01S, XCF02S,

or XCF04S.

2. Assumes compression used.

3. The largest possible Virtex-II bitstream sizes are specified. Refer to

the Virtex-II User Guide for information on bitgen options which

affect bitstream size.

External Programming

Xilinx reprogrammable PROMs can also be programmed by

the Xilinx MultiPRO Desktop Tool or a third-party device

programmer. This provides the added flexibility of using

pre-programmed devices with an in-system programmable

option for future enhancements and design changes.

Table 3: Platform Flash PROM Capacity

Platform

Flash PROM

Configuration

Bits

Platform Flash

PROM

Configuration

Bits

XCF01S

XCF02S

XCF04S

1,048,576 XCF08P

8,388,608

16,777,216

33,554,432

Reliability and Endurance

2,097,152 XCF16P

4,194,304 XCF32P

Xilinx in-system programmable products provide a guaran-

teed endurance level of 20,000 in-system program/erase

cycles and a minimum data retention of 20 years. Each

device meets all functional, performance, and data retention

specifications within this endurance limit.

Programming

In-System Programming

In-System Programmable PROMs can be programmed

individually, or two or more can be daisy-chained together

and programmed in-system via the standard 4-pin JTAG

protocol as shown in Figure 3. In-system programming

offers quick and efficient design iterations and eliminates

unnecessary package handling or socketing of devices. The

Design Security

The Xilinx in-system programmable Platform Flash PROM

devices incorporate advanced data security features to fully

protect the FPGA programming data against unauthorized

reading via JTAG. The XCFxxP PROMs can also be pro-

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Preliminary Product Specification

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Platform Flash In-System Programmable Configuration PROMS

grammed to prevent inadvertent writing via JTAG. Table 4

and Table 5 show the security settings available for the

XCFxxS PROM and XCFxxP PROM, respectively.

Write Protection

The XCFxxP PROM device also allows the user to write

protect (or lock) a particular design revision to prevent inad-

vertent erase or program operations. Once set, the write

protect security bit for an individual design revision must be

reset (using the UNLOCK command followed by

ISC_ERASE command) before an erase or program opera-

tion can be performed.

Read Protection

The read protect security bit can be set by the user to pre-

vent the internal programming pattern from being read or

copied via JTAG. Read protection does not prevent write

operations. For the XCFxxS PROM, the read protect secu-

rity bit is set for the entire device, and resetting the read pro-

tect security bit requires erasing the entire device. For the

XCFxxP PROM the read protect security bit can be set for

individual design revisions, and resetting the read protect

bit requires erasing the particular design revision.

Table 4: XCFxxS Device Data Security Options

Read/Verify

Inhibited

Program

Inhibited

Erase

Inhibited

Read Protect

Reset (default)

Set

√

Table 5: XCFxxP Design Revision Data Security Options

Read/Verify

Inhibited

Program

Inhibited

Read Protect

Reset (default)

Write Protect

Reset (default)

Set

Erase Inhibited

Reset (default)

√

Set

Reset (default)

Set

√

IEEE 1149.1 Boundary-Scan (JTAG)

The Platform Flash PROM family is IEEE Standard 1532

in-system programming compatible, and is fully compliant

with the IEEE Std. 1149.1 Boundary-Scan, also known as

JTAG, which is a subset of IEEE Std. 1532 Boundary-Scan.

A Test Access Port (TAP) and registers are provided to sup-

port all required boundary scan instructions, as well as

many of the optional instructions specified by IEEE Std.

1149.1. In addition, the JTAG interface is used to implement

in-system programming (ISP) to facilitate configuration, era-

sure, and verification operations on the Platform Flash

PROM device. Table 6 lists the required and optional

boundary-scan instructions supported in the Platform Flash

PROMs. Refer to the IEEE Std. 1149.1 specification for a

complete description of boundary-scan architecture and the

required and optional instructions.

XCFxxS Instruction Register (8 bits wide)

The Instruction Register (IR) for the XCFxxS PROM is eight

bits wide and is connected between TDI and TDO during an

instruction scan sequence. The detailed composition of the

instruction capture pattern is illustrated in Figure 4. The

instruction capture pattern shifted out of the XCFxxS device

includes IR[7:0]. IR[7:5] are reserved bits and are set to a

logic "0". The ISC Status field, IR[4], contains logic "1" if the

device is currently in In-System Configuration (ISC) mode;

otherwise, it contains logic "0". The Security field, IR[3],

contains logic "1" if the device has been programmed with

the security option turned on; otherwise, it contains logic

"0". IR[2] is unused, and is set to '0'. The remaining bits

IR[1:0] are set to '01' as defined by IEEE Std. 1149.1.

XCFxxP Instruction Register (16 bits wide)

Instruction Register

The Instruction Register (IR) for the XCFxxP PROM is six-

teen bits wide and is connected between TDI and TDO dur-

ing an instruction scan sequence. The detailed composition

of the instruction capture pattern is illustrated in Figure 5.

The Instruction Register (IR) for the Platform Flash PROM

is connected between TDI and TDO during an instruction

scan sequence. In preparation for an instruction scan

sequence, the instruction register is parallel loaded with a

fixed instruction capture pattern. This pattern is shifted out

onto TDO (LSB first), while an instruction is shifted into the

instruction register from TDI.

The instruction capture pattern shifted out of the XCFxxP

device includes IR[15:0]. IR[15:9] are reserved bits and are

set to a logic "0". The ISC Error field, IR[8:7], contains a "10"

when an ISC operation is a success; otherwise a "01" when

an In-System Configuration (ISC) operation fails. The

Erase/Program (ER/PROG) Error field, IR[6:5], contains a

"10" when an erase or program operation is a success; oth-

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Preliminary Product Specification

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Platform Flash In-System Programmable Configuration PROMS

erwise a "01" when an erase or program operation fails. The

Erase/Program (ER/PROG) Status field, IR[4], contains a

logic "1" when the device is busy performing an erase or

programming operation; otherwise, it contains a logic "0".

The ISC Status field, IR[3], contains logic "1" if the device is

currently in In-System Configuration (ISC) mode; otherwise,

it contains logic "0". The DONE field, IR[2], contains logic

"1" if the sampled design revision has been successfully

programmed; otherwise, a logic "0" indicates incomplete

programming. The remaining bits IR[1:0] are set to '01' as

defined by IEEE Std. 1149.1

.

Table 6: Platform Flash PROM Boundary Scan Instructions

XCFxxS IR[7:0] XCFxxP IR[15:0]

Boundary-Scan Command

Required Instructions

BYPASS

(hex)

Instruction Description

Enables BYPASS

FF

01

00

FFFF

0001

0000

Enables boundary-scan SAMPLE/PRELOAD operation

Enables boundary-scan EXTEST operation

SAMPLE/PRELOAD

EXTEST

Optional Instructions

CLAMP

Enables boundary-scan CLAMP operation

FA

FC

00FA

00FC

Places all outputs in high-impedance state

simultaneously

HIGHZ

Enables shifting out 32-bit IDCODE

IDCODE

FE

FD

00FE

00FD

Enables shifting out 32-bit USERCODE

USERCODE

PlatformFlashPROMSpecific

Instructions

Initiates FPGA configuration by pulsing CF pin Low

once. (For the XCFxxP this command also resets the

selected design revision based on either the external

REV_SEL[1:0] pins or on the internal design revision

selection bits.)⁽¹⁾

CONFIG

EE

00EE

Notes:

1. For more information see Initiating FPGA Configuration.

IR[7:5]

IR[4]

IR[3]

Security

IR[2]

IR[1:0]

TDI →

→ TDO

Reserved

ISC Status

0

0 1

Figure 4: XCFxxS Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence

IR[15:9]

IR[8:7]

IR[6:5]

ER/PROG ER/PROG

Error Status

IR[4]

IR[3]

IR[2]

IR[1:0]

TDI →

→ TDO

Reserved

ISC Error

ISC Status

DONE

0 1

Figure 5: XCFxxP Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence

Boundary Scan Register

The boundary-scan register is used to control and observe

the state of the device pins during the EXTEST, SAM-

PLE/PRELOAD, and CLAMP instructions. Each output pin

on the Platform Flash PROM has two register stages which

contribute to the boundary-scan register, while each input

pin has only one register stage. The bidirectional pins have

a total of three register stages which contribute to the

boundary-scan register. For each output pin, the register

stage nearest to TDI controls and observes the output state,

and the second stage closest to TDO controls and observes

the High-Z enable state of the output pin. For each input pin,

a single register stage controls and observes the input state

of the pin. The bidirectional pin combines the three bits, the

input stage bit is first, followed by the output stage bit and

finally the output enable stage bit. The output enable stage

bit is closest to TDO.

DS123 (v2.6) March 14, 2005

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Preliminary Product Specification

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Platform Flash In-System Programmable Configuration PROMS

See the XCFxxS/XCFxxP Pin Names and Descriptions

Tables in the Pinouts and Pin Descriptions section for the

boundary-scan bit order for all connected device pins, or

see the appropriate BSDL file for the complete bound-

ary-scan bit order description under the "attribute

BOUNDARY_REGISTER" section in the BSDL file. The bit

assigned to boundary-scan cell "0" is the LSB in the bound-

ary-scan register, and is the register bit closest to TDO.

USERCODE Register

The USERCODE instruction gives access to a 32-bit user

programmable scratch pad typically used to supply informa-

tion about the device's programmed contents. By using the

USERCODE instruction, a user-programmable identifica-

tion code can be shifted out for examination. This code is

loaded into the USERCODE register during programming of

the Platform Flash PROM. If the device is blank or was not

loaded during programming, the USERCODE register con-

tains FFFFFFFFh.

Identification Registers

IDCODE Register

Customer Code Register

The IDCODE is a fixed, vendor-assigned value that is used

to electrically identify the manufacturer and type of the

device being addressed. The IDCODE register is 32 bits

wide. The IDCODE register can be shifted out for examina-

tion by using the IDCODE instruction. The IDCODE is avail-

able to any other system component via JTAG. Table 7 lists

the IDCODE register values for the Platform Flash PROMs.

For the XCFxxP Platform Flash PROM, in addition to the

USERCODE, a unique 32-byte Customer Code can be

assigned to each design revision enabled for the PROM.

The Customer Code is set during programming, and is typ-

ically used to supply information about the design revision

contents. A private JTAG instruction is required to read the

Customer Code. If the PROM is blank, or the Customer

Code for the selected design revision was not loaded during

programming, or if the particular design revision is erased,

the Customer Code will contain all ones.

The IDCODE register has the following binary format:

vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1

where

v = the die version number

f = the PROM family code

a = the specific Platform Flash PROM product ID

c = the Xilinx manufacturer's ID

Platform Flash PROM TAP

Characteristics

The Platform Flash PROM family performs both in-system

programming and IEEE 1149.1 boundary-scan (JTAG) test-

ing via a single 4-wire Test Access Port (TAP). This simpli-

fies system designs and allows standard Automatic Test

Equipment to perform both functions. The AC characteris-

tics of the Platform Flash PROM TAP are described as fol-

lows.

The LSB of the IDCODE register is always read as logic "1"

as defined by IEEE Std. 1149.1.

Table 7: IDCODES Assigned to Platform Flash PROMs

Device

XCF01S

XCF02S

XCF04S

XCF08P

XCF16P

XCF32P

IDCODE⁽¹⁾(hex)

<v>5044093

<v>5045093

<v>5046093

<v>5057093

<v>5058093

<v>5059093

TAP Timing

Figure 6 shows the timing relationships of the TAP signals.

These TAP timing characteristics are identical for both

boundary-scan and ISP operations.

Notes:

1. The <v> in the IDCODE field represents the device’s revision

code (in hex), and may vary.

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Preliminary Product Specification

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Platform Flash In-System Programmable Configuration PROMS

T

CKMIN

TCK

TMS

T

MSS

MSH

T

DIS

DIH

TDI

T

DOV

TDO

DS026_04_020300

Figure 6: Test Access Port Timing

TAP AC Parameters

Table 8 shows the timing parameters for the TAP waveforms shown in Figure 6.

Table 8: Test Access Port Timing Parameters

Symbol

T_CKMIN

Description

TCK minimum clock period when V_CCJ= 2.5V or 3.3V

TMS setup time when V_CCJ= 2.5V or 3.3V

TMS hold time when V_CCJ= 2.5V or 3.3V

TDI setup time when V_CCJ= 2.5V or 3.3V

TDI hold time when V_CCJ= 2.5V or 3.3V

Min

100

10

25

10

25

-

Max

Units

ns

-

T_MSS

T_MSH

T_DIS

ns

-

ns

-

ns

T_DIH

-

ns

T_DOV

TDO valid delay when V_CCJ= 2.5V or 3.3V

30

ns

The CLKOUT signal is enabled during programming, and is

active when CE is Low and OE/RESET is High. When dis-

abled, the CLKOUT pin is put into a high-impedance state

and should be pulled High externally to provide a known

state.

Additional Features for the XCFxxP

Internal Oscillator

The 8/16/32 Mbit XCFxxP Platform Flash PROMs include

an optional internal oscillator which can be used to drive the

CLKOUT and DATA pins on FPGA configuration interface.

The internal oscillator can be enabled during device pro-

gramming, and can be set to either the default frequency or

to a slower frequency (AC Characteristics Over Operat-

ing Conditions When Cascading).

When cascading Platform Flash PROMs with CLKOUT

enabled, after completing it's data transfer, the first PROM

disables CLKOUT and releases the CEO pin enabling the

next PROM in the PROM chain. The next PROM will begin

driving the CLKOUT signal once that PROM is enabled and

data is available for transfer.

CLKOUT

During high-speed parallel configuration without compres-

sion, the FPGA drives the BUSY signal on the configuration

interface. When BUSY is asserted High, the PROMs inter-

nal address counter stops incrementing, and the current

data value is held on the data outputs. While BUSY is High,

the PROM will continue driving the CLKOUT signal to the

FPGA, clocking the FPGA’s configuration logic. When the

FPGA deasserts BUSY, indicating that it is ready to receive

additional configuration data, the PROM will begin driving

new data onto the configuration interface.

The 8/16/32 Mbit XCFxxP Platform Flash PROMs include

the programmable option to enable the CLKOUT signal

which allows the PROM to provide a source synchronous

clock aligned to the data on the configuration interface. The

CLKOUT signal is derived from one of two clock sources:

the CLK input pin or the internal oscillator. The input clock

source is selected during the PROM programming

sequence. Output data is available on the rising edge of

CLKOUT.

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8

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

OUT) must be used as the clock signal for the configuration

interface, driving the target FPGA's configuration clock

Decompression

The 8/16/32 Mbit XCFxxP Platform Flash PROMs include a

built-in data decompressor compatible with Xilinx advanced

compression technology. Compressed Platform Flash

PROM files are created from the target FPGA bitstream(s)

using the iMPACT software. Only Slave Serial and Slave

SelectMAP (parallel) configuration modes are supported for

FPGA configuration when using a XCFxxP PROM pro-

grammed with a compressed bitstream. Compression rates

will vary depending on several factors, including the target

device family and the target design contents.

input pin (CCLK). Either the PROM's CLK input pin or the

internal oscillator must be selected as the source for CLK-

OUT. Any target FPGA connected to the PROM must oper-

ate as slave in the configuration chain, with the

configuration mode set to Slave Serial mode or Slave

SelectMap (parallel) mode.

When decompression is enabled, the CLKOUT signal

becomes a controlled clock output with a reduced maximum

frequency. When decompressed data is not ready, the CLK-

OUT pin is put into a high-Z state and must be pulled High

externally to provide a known state.

The decompression option is enabled during the PROM

programming sequence. The PROM decompresses the

stored data before driving both clock and data onto the

FPGA's configuration interface. If Decompression is

enabled, then the Platform Flash clock output pin (CLK-

The BUSY input is automatically disabled when decom-

pression is enabled.

Design Revisioning

Design Revisioning allows the user to create up to four

unique design revisions on a single PROM or stored across

multiple cascaded PROMs. Design Revisioning is sup-

ported for the 8/16/32 Mbit XCFxxP Platform Flash PROMs

in both serial and parallel modes. Design Revisioning can

be used with compressed PROM files, and also when the

CLKOUT feature is enabled. The PROM programming files

along with the revision information files (.cfi) are created

using the iMPACT software. The .cfi file is required to

enable design revision programming in iMPACT.

cading one 16-Mbit PROM and one 8-Mbit PROM, there are

24 Mbits of available space, and therefore up to three sepa-

rate design revisions can be stored: one 24-Mbit design

revision, two 8-Mbit design revisions, or three 8-Mbit design

revisions.

See Figure 7 for a few basic examples of how multiple revi-

sions can be stored. The design revision partitioning is han-

dled automatically during file generation in iMPACT.

During the PROM file creation, each design revision is

assigned a revision number:

A single design revision is composed of from 1 to n 8-Mbit

memory blocks. If a single design revision contains less

than 8 Mbits of data, then the remaining space is padded

with all ones. A larger design revision can span several

8-Mbit memory blocks, and any space remaining in the last

8-Mbit memory block is padded with all ones.

Revision 0 = '00'

Revision 1 = '01'

Revision 2 = '10'

Revision 3 = '11'

After programming the Platform Flash PROM with a set of

design revisions, a particular design revision can be

selected using the external REV_SEL[1:0] pins or using the

internal programmable design revision control bits. The

EN_EXT_SEL pin determines if the external pins or internal

bits are used to select the design revision. When

EN_EXT_SEL is Low, design revision selection is controlled

by the external Revision Select pins, REV_SEL[1:0]. When

EN_EXT_SEL is High, design revision selection is con-

trolled by the internal programmable Revision Select control

bits. During power up, the design revision selection inputs

(pins or control bits) are sampled internally. After power up,

when CE is asserted (Low) enabling the PROM inputs, the

design revision selection inputs are sampled again after the

rising edge of the CF pulse. The data from the selected

design revision is then presented on the FPGA configura-

tion interface.

•

A single 32-Mbit PROM contains four 8-Mbit memory

blocks, and can therefore store up to four separate

design revisions: one 32-Mbit design revision, two

16-Mbit design revisions, three 8-Mbit design revisions,

four 8-Mbit design revisions, and so on.

Because of the 8-Mbit minimum size requirement for

each revision, a single 16-Mbit PROM can only store

up to two separate design revisions: one 16-Mbit

design revision, one 8-Mbit design revision, or two

8-Mbit design revisions.

A single 8-Mbit PROM can store only one 8-Mbit

design revision.

Larger design revisions can be split over several cascaded

PROMs. For example, two 32-Mbit PROMs can store up to

four separate design revisions: one 64-Mbit design revision,

two 32-Mbit design revisions, three 16-Mbit design revi-

sions, four 16-Mbit design revisions, and so on. When cas-

DS123 (v2.6) March 14, 2005

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9

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

PROM 0

REV 0

(8 Mbits)

REV 0

(16 Mbits)

REV 1

(8 Mbits)

REV 0

(32 Mbits)

REV 1

REV 2

(8 Mbits)

(24 Mbits)

REV 2

REV 1

(16 Mbits)

REV 3

(8 Mbits)

4 Design Revisions 3 Design Revisions

2 Design Revisions

1 Design Revision

PROM 0

(a) Design Revision storage examples for a single XCF32P PROM

PROM 0

REV 0

(16 Mbits)

REV 0

(32 Mbits)

REV 1

(16 Mbits)

PROM 1

REV 2

(16 Mbits)

REV 2

REV 1

REV 0

(32 Mbits)

REV 3

(16 Mbits)

4 Design Revisions 3 Design Revisions

2 Design Revisions

1 Design Revision

ds123_20_102103

(b) Design Revision storage examples spanning two XCF32P PROMs

Figure 7: Design Revision Storage Examples

PROM to FPGA Configuration Mode and Connections Summary

The FPGA's I/O, logical functions, and internal interconnec-

tions are established by the configuration data contained in

FPGA Master Serial Mode

In Master Serial mode, the FPGA automatically loads the

the FPGA’s bitstream. The bitstream is loaded into the

FPGA either automatically upon power up, or on command,

depending on the state of the FPGA's mode pins. Xilinx

Platform Flash PROMs are designed to download directly to

the FPGA configuration interface. FPGA configuration

modes which are supported by the XCFxxS Platform Flash

PROMs include: Master Serial and Slave Serial. FPGA con-

figuration modes which are supported by the XCFxxP Plat-

form Flash PROMs include: Master Serial, Slave Serial,

Master SelectMAP, and Slave SelectMAP. Below is a short

summary of the supported FPGA configuration modes. See

the respective FPGA data sheet for device configuration

details, including which configuration modes are supported

by the targeted FPGA device.

configuration bitstream in bit-serial form from external mem-

ory synchronized by the configuration clock (CCLK) gener-

ated by the FPGA. Upon power-up or reconfiguration, the

FPGA's mode select pins are used to select the Master

Serial configuration mode. Master Serial Mode provides a

simple configuration interface. Only a serial data line, a

clock line, and two control lines (INIT and DONE) are

required to configure an FPGA. Data from the PROM is

read out sequentially on a single data line (DIN), accessed

via the PROM's internal address counter which is incre-

mented on every valid rising edge of CCLK. The serial bit-

stream data must be set up at the FPGA’s DIN input pin a

short time before each rising edge of the FPGA's internally

generated CCLK signal.

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Preliminary Product Specification

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Platform Flash In-System Programmable Configuration PROMS

Typically, a wide range of frequencies can be selected for

the FPGA’s internally generated CCLK which always starts

at a slow default frequency. The FPGA’s bitstream contains

configuration bits which can switch CCLK to a higher fre-

quency for the remainder of the Master Serial configuration

sequence. The desired CCLK frequency is selected during

bitstream generation.

•

The CEO output of a PROM drives the CE input of the

next PROM in a daisy chain (if any).

The OE/RESET pins of all PROMs are connected to

the INIT_B (or INIT) pins of all FPGA devices. This

connection assures that the PROM address counter is

reset before the start of any (re)configuration.

•

The PROM CE input can be driven from the DONE pin.

The CE input of the first (or only) PROM can be driven

by the DONE output of all target FPGA devices,

provided that DONE is not permanently grounded. CE

can also be permanently tied Low, but this keeps the

DATA output active and causes an unnecessary I_CC

Connecting the FPGA device to the configuration PROM for

Master Serial Configuration Mode (Figure 8):

•

The DATA output of the PROM(s) drive the DIN input of

the lead FPGA device.

The Master FPGA CCLK output drives the CLK input(s)

of the PROM(s)

active supply current (DC Characteristics Over

Operating Conditions).

The CEO output of a PROM drives the CE input of the

next PROM in a daisy chain (if any).

•

The PROM CF pin is typically connected to the FPGA's

PROG_B (or PROGRAM) input. For the XCFxxP only,

the CF pin is a bidirectional pin. If the XCFxxP CF pin is

not connected to the FPGA's PROG_B (or PROGRAM)

input, then the pin should be tied High.

The OE/RESET pins of all PROMs are connected to

the INIT_B pins of all FPGA devices. This connection

assures that the PROM address counter is reset before

the start of any (re)configuration.

•

The PROM CE input can be driven from the DONE pin.

The CE input of the first (or only) PROM can be driven

by the DONE output of all target FPGA devices,

provided that DONE is not permanently grounded. CE

can also be permanently tied Low, but this keeps the

DATA output active and causes an unnecessary I_CC

Serial Daisy Chain

Multiple FPGAs can be daisy-chained for serial configura-

tion from a single source. After a particular FPGA has been

configured, the data for the next device is routed internally

to the FPGA’s DOUT pin. Typically the data on the DOUT

pin changes on the falling edge of CCLK, although for some

devices the DOUT pin changes on the rising edge of CCLK.

Consult the respective device data sheets for detailed infor-

mation on a particular FPGA device. For clocking the

daisy-chained configuration, either the first FPGA in the

chain can be set to Master Serial, generating the CCLK,

with the remaining devices set to Slave Serial (Figure 10),

or all the FPGA devices can be set to Slave Serial and an

externally generated clock can be used to drive the FPGA's

configuration interface.

active supply current (DC Characteristics Over

Operating Conditions).

•

The PROM CF pin is typically connected to the FPGA's

PROG_B (or PROGRAM) input. For the XCFxxP only,

the CF pin is a bidirectional pin. If the XCFxxP CF pin is

not connected to the FPGA's PROG_B (or PROGRAM)

input, then the pin should be tied High.

FPGA Slave Serial Mode

In Slave Serial mode, the FPGA loads the configuration bit-

stream in bit-serial form from external memory synchro-

nized by an externally supplied clock. Upon power-up or

reconfiguration, the FPGA's mode select pins are used to

select the Slave Serial configuration mode. Slave Serial

Mode provides a simple configuration interface. Only a

serial data line, a clock line, and two control lines (INIT and

DONE) are required to configure an FPGA. Data from the

PROM is read out sequentially on a single data line (DIN),

accessed via the PROM's internal address counter which is

incremented on every valid rising edge of CCLK. The serial

bitstream data must be set up at the FPGA’s DIN input pin a

short time before each rising edge of the externally provided

CCLK.

(1)

FPGA Master SelectMAP (Parallel) Mode

In Master SelectMAP mode, byte-wide data is written into

the FPGA, typically with a BUSY flag controlling the flow of

data, synchronized by the configuration clock (CCLK) gen-

erated by the FPGA. Upon power-up or reconfiguration, the

FPGA's mode select pins are used to select the Master

SelectMAP configuration mode. The configuration interface

typically requires a parallel data bus, a clock line, and two

control lines (INIT and DONE). In addition, the FPGA’s Chip

Select, Write, and BUSY pins must be correctly controlled to

enable SelectMAP configuration. The configuration data is

read from the PROM byte by byte on pins [D0..D7],

accessed via the PROM's internal address counter which is

incremented on every valid rising edge of CCLK. The bit-

stream data must be set up at the FPGA’s [D0..D7] input

Connecting the FPGA device to the configuration PROM for

Slave Serial Configuration Mode (Figure 9):

•

The DATA output of the PROM(s) drive the DIN input of

the lead FPGA device.

1. The Master SelectMAP (Parallel) FPGA configuration mode is sup-

ported only by the XCFxxP Platform Flash PROM. This mode is not

supported by the XCFxxS Platform Flash PROM.

•

The PROM CLKOUT (for XCFxxP only) or an external

clock source drives the FPGA's CCLK input.

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Preliminary Product Specification

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Platform Flash In-System Programmable Configuration PROMS

pins a short time before each rising edge of the FPGA's

internally generated CCLK signal. If BUSY is asserted

(High) by the FPGA, the configuration data must be held

until BUSY goes Low. An external data source or external

pull-down resistors must be used to enable the FPGA's

active Low Chip Select (CS or CS_B) and Write (WRITE or

RDWR_B) signals to enable the FPGA's SelectMAP config-

uration process.

data, synchronized by an externally supplied configuration

clock (CCLK). Upon power-up or reconfiguration, the

FPGA's mode select pins are used to select the Slave

SelectMAP configuration mode. The configuration interface

typically requires a parallel data bus, a clock line, and two

control lines (INIT and DONE). In addition, the FPGA’s Chip

Select, Write, and BUSY pins must be correctly controlled to

enable SelectMAP configuration. The configuration data is

read from the PROM byte by byte on pins [D0..D7],

accessed via the PROM's internal address counter which is

incremented on every valid rising edge of CCLK. The bit-

stream data must be set up at the FPGA’s [D0..D7] input

pins a short time before each rising edge of the provided

CCLK. If BUSY is asserted (High) by the FPGA, the config-

uration data must be held until BUSY goes Low. An external

data source or external pull-down resistors must be used to

enable the FPGA's active Low Chip Select (CS or CS_B)

and Write (WRITE or RDWR_B) signals to enable the

FPGA's SelectMAP configuration process.

The Master SelectMAP configuration interface is clocked by

the FPGA’s internal oscillator. Typically, a wide range of fre-

quencies can be selected for the internally generated CCLK

which always starts at a slow default frequency. The FPGA’s

bitstream contains configuration bits which can switch

CCLK to a higher frequency for the remainder of the Master

SelectMAP configuration sequence. The desired CCLK fre-

quency is selected during bitstream generation.

After configuration, the pins of the SelectMAP port can be

used as additional user I/O. Alternatively, the port can be

retained using the persist option.

After configuration, the pins of the SelectMAP port can be

used as additional user I/O. Alternatively, the port can be

retained using the persist option.

Connecting the FPGA device to the configuration PROM for

Master SelectMAP (Parallel) Configuration Mode

(Figure 11):

Connecting the FPGA device to the configuration PROM for

•

The DATA outputs of the PROM(s) drive the [D0..D7]

input of the lead FPGA device.

Slave

SelectMAP

(Parallel)

Configuration

Mode

(Figure 12):

The Master FPGA CCLK output drives the CLK input(s)

of the PROM(s)

•

The DATA outputs of the PROM(s) drives the [D0..D7]

inputs of the lead FPGA device.

The CEO output of a PROM drives the CE input of the

next PROM in a daisy chain (if any).

The PROM CLKOUT (for XCFxxP only) or an external

clock source drives the FPGA's CCLK input

The OE/RESET pins of all PROMs are connected to

the INIT_B pins of all FPGA devices. This connection

assures that the PROM address counter is reset before

the start of any (re)configuration.

The CEO output of a PROM drives the CE input of the

next PROM in a daisy chain (if any).

The OE/RESET pins of all PROMs are connected to

the INIT_B pins of all FPGA devices. This connection

assures that the PROM address counter is reset before

the start of any (re)configuration.

•

The PROM CE input can be driven from the DONE pin.

The CE input of the first (or only) PROM can be driven

by the DONE output of all target FPGA devices,

provided that DONE is not permanently grounded. CE

can also be permanently tied Low, but this keeps the

DATA output active and causes an unnecessary I_CC

•

The PROM CE input can be driven from the DONE pin.

The CE input of the first (or only) PROM can be driven

by the DONE output of all target FPGA devices,

provided that DONE is not permanently grounded. CE

can also be permanently tied Low, but this keeps the

DATA output active and causes an unnecessary I_CC

active supply current (DC Characteristics Over

Operating Conditions).

•

For high-frequency parallel configuration, the BUSY

pins of all PROMs are connected to the FPGA's BUSY

output. This connection assures that the next data

transition for the PROM is delayed until the FPGA is

ready for the next configuration data byte.

active supply current (DC Characteristics Over

Operating Conditions).

•

For high-frequency parallel configuration, the BUSY

pins of all PROMs are connected to the FPGA's BUSY

output. This connection assures that the next data

transition for the PROM is delayed until the FPGA is

ready for the next configuration data byte.

The PROM CF pin is typically connected to the FPGA's

PROG_B (or PROGRAM) input. For the XCFxxP only,

the CF pin is a bidirectional pin. If the XCFxxP CF pin is

not connected to the FPGA's PROG_B (or PROGRAM)

input, then the pin should be tied High.

The PROM CF pin is typically connected to the FPGA's

(1)

FPGA Slave SelectMAP (Parallel) Mode

1. The Slave SelectMAP (Parallel) FPGA configuration mode is sup-

ported only by the XCFxxP Platform Flash PROMs.This mode is

not supported by the XCFxxS Platform Flash PROM.

In Slave SelectMAP mode, byte-wide data is written into the

FPGA, typically with a BUSY flag controlling the flow of

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Preliminary Product Specification

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Platform Flash In-System Programmable Configuration PROMS

PROG_B (or PROGRAM) input. For the XCFxxP only,

the CF pin is a bidirectional pin. If the XCFxxP CF pin is

not connected to the FPGA's PROG_B (or PROGRAM)

input, then the pin should be tied High.

a high-impedance state. The second PROM recognizes the

Low level on its CE input and immediately enables its out-

puts.

After configuration is complete, address counters of all cas-

caded PROMs are reset if the PROM OE/RESET pin goes

Low or CE goes High.

(1)

FPGA SelectMAP (Parallel) Device Chaining

Multiple Virtex-II FPGAs can be configured using the

SelectMAP mode, and be made to start up simultaneously.

To configure multiple devices in this way, wire the individual

CCLK, DONE, INIT, Data ([D0..D7]), Write (WRITE or

RDWR_B), and BUSY pins of all the devices in parallel. If all

devices are to be configured with the same bitstream, read-

back is not being used, and the CCLK frequency selected

does not require the use of the BUSY signal, the CS_B pins

can be connected to a common line so all of the devices are

configured simultaneously (Figure 13).

When utilizing the advanced features for the XCFxxP Plat-

form Flash PROM, including the clock output (CLKOUT)

option, decompression option, or design revisioning, pro-

gramming files which span cascaded PROM devices can

only be created for cascaded chains containing only

XCFxxP PROMs. If the advanced features are not used,

then cascaded PROM chains can contain both XCFxxP and

XCFxxS PROMs.

Initiating FPGA Configuration

With additional control logic, the individual devices can be

loaded separately by asserting the CS_B pin of each device

in turn and then enabling the appropriate configuration data.

The PROM can also store the individual bitstreams for each

FPGA for SelectMAP configuration in separate design revi-

sions. When design revisioning is utilized, additional control

logic can be used to select the appropriate bitstream by

asserting the EN_EXT_SEL pin, and using the

REV_SEL[1:0] pins to select the required bitstream, while

asserting the CS_B pin for the FPGA the bitstream is target-

ing (Figure 14).

The options for initiating FPGA configuration via the Plat-

form Flash PROM include:

1. Automatic configuration on power up

2. Applying an external PROG_B (or PROGRAM) pulse

3. Applying the JTAG CONFIG instruction

Following the FPGA’s power-on sequence or the assertion

of the PROG_B (or PROGRAM) pin the FPGA’s configura-

tion memory is cleared, the configuration mode is selected,

and the FPGA is ready to accept a new configuration bit-

stream. The FPGA’s PROG_B pin can be controlled by an

external source, or alternatively, the Platform Flash PROMs

incorporate a CF pin that can be tied to the FPGA’s

PROG_B pin. Executing the CONFIG instruction through

JTAG pulses the CF output Low once for 300-500 ns, reset-

ting the FPGA and initiating configuration. The iMPACT

software can issue the JTAG CONFIG command to initiate

FPGA configuration by setting the "Load FPGA" option.

For clocking the parallel configuration chain, either the first

FPGA in the chain can be set to Master SelectMAP, gener-

ating the CCLK, with the remaining devices set to Slave

SelectMAP, or all the FPGA devices can be set to Slave

SelectMAP and an externally generated clock can be used

to drive the configuration interface. Again, the respective

device data sheets should be consulted for detailed infor-

mation on a particular FPGA device, including which config-

uration modes are supported by the targeted FPGA device.

When using the XCFxxP Platform Flash PROM with design

revisioning enabled, the CF pin should always be con-

nected to the PROG_B (or PROGRAM) pin on the FPGA to

ensure that the current design revision selection is sampled

when the FPGA is reset. The XCFxxP PROM samples the

current design revision selection from the external

REV_SEL pins or the internal programmable Revision

Select bits on the rising edge of CF. When the JTAG CON-

FIG command is executed, the XCFxxP will sample the new

design revision before initiating the FPGA configuration

sequence. When using the XCFxxP Platform Flash PROM

without design revisioning, if the CF pin is not connected to

the FPGA PROG_B (or PROGRAM) pin, then the XCFxxP

CF pin should be tied High.

Cascading Configuration PROMs

When configuring multiple FPGAs in a serial daisy chain,

configuring multiple FPGAs in a SelectMAP parallel chain,

or configuring a single FPGA requiring a larger configura-

tion bitstream, cascaded PROMs provide additional mem-

ory (Figure 10, Figure 13, Figure 14, and Figure 15).

Multiple Platform Flash PROMs can be concatenated by

using the CEO output to drive the CE input of the down-

stream device. The clock signal and the data outputs of all

Platform Flash PROMs in the chain are interconnected.

After the last data from the first PROM is read, the first

PROM asserts its CEO output Low and drives its outputs to

1. The SelectMAP (Parallel) FPGA configuration modes are supported only by the XCFxxP Platform Flash PROM.These modes are not sup-

ported by the XCFxxS Platform Flash PROM.

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Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

Configuration PROM to FPGA Device Interface Connection Diagrams

(2)

V

CCO

(1)

V

CCO CCINT

CCJ

(1)

V

D0

DIN

MODE PINS

CCINT

(2)

CCO

(2)

DIN

CCLK

CCJ

...OPTIONAL

Slave FPGAs

with identical

configurations

Xilinx FPGA

Master Serial

Platform Flash

PROM

DONE

INIT_B

PROG_B

CLK

CE

CCLK

DONE

...OPTIONAL

Daisy-chained

Slave FPGAs

with different

configurations

CEO

DOUT

DIN

CCLK

OE/RESET

INIT_B

(3)

TDI

CF

PROG_B

DONE

TMS

TCK

TDO

TMS

TCK

INIT_B

PROG_B

TDO

TDI

GND

TMS

TCK

TDO

GND

Notes:

1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.

2 For compatible voltages, refer to the appropriate data sheet.

3 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin.

ds123_11_100804

Figure 8: Configuring in Master Serial Mode

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Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

(2)

V

CCO

(3)

External

Oscillator

(1)

V

CCJ CCO CCINT

(1)

V

D0

DIN

MODE PINS

CCINT

(2)

CCO

(2)

DIN

CCLK

CCJ

...OPTIONAL

Slave FPGAs

with identical

configurations

Xilinx FPGA

Slave Serial

Platform Flash

PROM

DONE

INIT_B

PROG_B

(3)

CLK

CCLK

DONE

CE

CEO

...OPTIONAL

Daisy-chained

Slave FPGAs

with different

configurations

DOUT

DIN

CCLK

OE/RESET

INIT_B

(4)

TDI

TMS

TCK

TDO

TDI

CF

PROG_B

DONE

TMS

TCK

INIT_B

PROG_B

TDO

TDI

GND

TMS

TCK

TDO

GND

Notes:

1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.

2 For compatible voltages, refer to the appropriate data sheet.

3 In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or

optionally—for the XCFxxP Platform Flash PROM only—the CLKOUT signal can be used to drive

the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used, then it

must be tied to a 4.7KΩ resistor pulled up to V

.

CCO

ds123_12_100804

4 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin.

Figure 9: Configuring in Slave Serial Mode

DS123 (v2.6) March 14, 2005

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15

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

(2)

V

CCO

CCJ

CCO

CCINT

CCJ

CCO

CCINT

(1)

V

D0

DIN

MODE PINS

DOUT

MODE PINS

V

D0

CCINT

(2)

CCINT

(2)

DIN

CCO

(2)

CCO

(2)

CCJ

Platform Flash

PROM

Xilinx FPGA

Master Serial

Xilinx FPGA

Slave Serial

Platform Flash

PROM

First

PROM

(PROM 0)

Cascaded

PROM

(PROM 1)

CLK

CE

CCLK

DONE

CCLK

DONE

CLK

CE

CEO

OE/RESET

INIT_B

OE/RESET

(3)

TDI

TMS

TCK

TDO

CF

PROG_B

TDI

CF

TMS

TCK

TDI

TDO

TMS

TCK

TDO

TDI

TDO

TDI

TMS

TCK

TMS

TCK

GND

TDO

GND

Notes:

1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.

2 For compatible voltages, refer to the appropriate data sheet.

3 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin.

ds123_13_100804

Figure 10: Configuring Multiple Devices Master/Slave Serial Mode

DS123 (v2.6) March 14, 2005

Preliminary Product Specification

www.xilinx.com

16

R

Platform Flash In-System Programmable Configuration PROMS

(2)

V

CCO

(1)

V

CCO CCINT

CCJ

(3)

I/O

(1)

V

D[0:7]

MODE PINS

RDWR_B

CS_B

CCINT

(2)

(3)

I/O

CCO

(2)

CCJ

1KΩ

XCFxxP

Xilinx FPGA

Platform Flash

PROM

Master SelectMAP

CLK

CCLK

DONE

CE

CEO

D[0:7]

CCLK

...OPTIONAL

Slave FPGAs

with identical

configurations

OE/RESET

INIT_B

DONE

(5)

TDI

CF

PROG_B

INIT_B

PROG_B

(4)

TMS

TCK

TDO

TMS

TCK

BUSY

(4)

BUSY

TDO

TDI

GND

TMS

TCK

TDO

GND

Notes:

1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.

2 For compatible voltages, refer to the appropriate data sheet.

3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.

4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for

high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.

5 For the XCFxxP the CF pin is a bidirectional pin.

ds123_14_100804

Figure 11: Configuring in Master SelectMAP Mode

DS123 (v2.6) March 14, 2005

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17

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

(2)

V

CCO

(5)

External

Oscillator

(1)

V

CCO CCINT

CCJ

(3)

I/O

(1)

V

D[0:7]

MODE PINS

RDWR_B

CS_B

CCINT

(2)

(3)

I/O

CCO

(2)

CCJ

1KΩ

XCFxxP

Xilinx FPGA

Platform Flash

PROM

Slave SelectMAP

(5)

CLK

CCLK

DONE

CE

CEO

D[0:7]

CCLK

...OPTIONAL

Slave FPGAs

with identical

configurations

OE/RESET

INIT_B

DONE

(6)

TDI

CF

PROG_B

INIT_B

PROG_B

(4)

TMS

TCK

TDO

TMS

TCK

BUSY

(4)

BUSY

TDO

TDI

GND

TMS

TCK

TDO

GND

Notes:

1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.

2 For compatible voltages, refer to the appropriate data sheet.

3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.

4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for

high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.

5 If the XCFxxP Platform Flash PROM is not used with CLKOUT enabled to drive CCLK, then an external clock is required

for Slave SelectMAP (or Slave Parallel) modes. If CLKOUT is used, then it must be tied to a 4.7KΩ resistor pulled up

to V

.

CCO

6 For the XCFxxP the CF pin is a bidirectional pin.

ds123_15_100804

Figure 12: Configuring in Slave SelectMAP Mode

DS123 (v2.6) March 14, 2005

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18

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

(2)

V

CCJ

V

CCO

V

CCINT

V

CCJ

V

CCO

V

CCINT

V

CCO

(1)

MODE PINS

V

D[0:7]

MODE PINS

D[0:7]

V

D[0:7]

CCINT

(2)

CCINT

(2)

(3)

I/O

CCO

(2)

RDWR_B

CS_B

RDWR_B

CS_B

CCJ

XCFxxP

Platform Flash

PROM

Platform Flash

PROM

Xilinx FPGA

Master SelectMAP

Xilinx FPGA

Slave SelectMAP

First

PROM

(PROM 0)

CLK

CCLK

DONE

CCLK

DONE

CLK

Cascaded

PROM

(PROM 1)

CE

CEO

OE/RESET

INIT_B

OE/RESET

(5)

TDI

TMS

TCK

TDO

CF

PROG_B

TDI

CF

(4)

BUSY

TMS

TCK

BUSY

TDI

TDO

TMS

TCK

GND

TDO

TDI

TMS

TCK

TMS

GND

TCK

TDO

GND

Notes:

1

2

3

4

For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.

For compatible voltages, refer to the appropriate data sheet.

CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.

The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for

high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.

For the XCFxxP the CF pin is a bidirectional pin.

ds123_16_100804

5

Figure 13: Configuring Multiple Devices with Identical Patterns in Master/Slave SelectMAP Mode

DS123 (v2.6) March 14, 2005

www.xilinx.com

19

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

(2)

V

CCO

CCJ

CCO

CCINT

CCJ

CCO

CCINT

(3)

External

Oscillator

(1)

MODE PINS

(1)

D0

V

D0

DIN

MODE PINS

V

CCINT

(2)

CCINT

(2)

DOUT

DIN

CCO

(2)

CCO

(2)

CCJ

XCFxxP

Platform Flash

PROM

Platform Flash

PROM

Xilinx FPGA

Slave Serial

Xilinx FPGA

Slave Serial

(3)

CLK

(3)

CLK

CCLK

DONE

CCLK

DONE

First

PROM

(PROM 0)

Cascaded

PROM

(PROM 1)

CE

CEO

OE/RESET

INIT_B

(4)

TDI

TMS

TCK

TDO

CF

PROG_B

TDI

TMS

TCK

TDO

TDI

TMS

TCK

TDO

TDI

TMS

TCK

TMS

TCK

EN_EX_SEL

TDO

EN_EX_SEL

REV_SEL[1:0]

GND

REV_SEL[1:0]

GND

EN_EXT_SEL

REV_SEL[1:0]

DONE

Design

Revision

Control

Logic

CF / PROG_B

1. For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.

2

3

For compatible voltages, refer to the appropriate data sheet.

In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or

optionally the CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK).

If the XCFxxP PROM's CLKOUT signal is used, then it must be tied to a 4.7KΩ resistor pulled

up to V

.

CCO

For the XCFxxP the CF pin is a bidirectional pin.

4

ds123_17_100804

Figure 14: Configuring Multiple Devices with Design Revisioning in Slave Serial Mode

DS123 (v2.6) March 14, 2005

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20

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

(2)

V

CCO

CCJ

CCO CCINT

CCJ

CCO CCINT

(5)

External

Oscillator

(1)

VCCINT

(2)

V

D[0:7]

MODE PINS

D[0:7]

MODE PINS

CCINT

(2)

V

RDWR_B

CS_B

RDWR_B

CS_B

CCO

(3)

(2)

I/O

V

CCJ

XCFxxP

Platform Flash

PROM

XCFxxP

Platform Flash

PROM

Xilinx FPGA

Slave SelectMAP

Xilinx FPGA

Slave SelectMAP

(5)

CLK

First

PROM

(PROM 0)

Cascaded

PROM

(PROM 1)

CLK

CE

CEO

CCLK

DONE

CCLK

DONE

CE

CEO

OE/RESET

INIT_B

(6)

TDI

CF

PROG_B

(4)

TMS

TCK

TDO

TMS

TCK

BUSY

TDI

TDO

TMS

TCK

TDO

TDI

TDO

TDI

TMS

TCK

TMS

EN_EX_SEL

TCK

TDO

REV_SEL[1:0]

GND

EN_EXT_SEL

REV_SEL[1:0]

CF

Design

Revision

Control

Logic

DONE

PROG_B

CS_B[1:0]

Notes:

1

2

3

4

For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.

For compatible voltages, refer to the appropriate data sheet.

RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.

The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only

required for high frequency SelectMAP mode configuration. For BUSY pin requirements, refer to

the appropriate FPGA data sheet.

5

In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or

optionally the CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK).

If the XCFxxP PROM's CLKOUT signal is used, then it must be tied to a 4.7KΩ resistor pulled

up to V

.

CCO

For the XCFxxP the CF pin is a bidirectional pin.

6

ds123_18_100804

Figure 15: Configuring Multiple Devices with Design Revisioning in Slave SelectMAP Mode

DS123 (v2.6) March 14, 2005

www.xilinx.com

21

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

Reset and Power-On Reset Activation

At power up, the device requires the V_CCINTpower supply

to monotonically rise to the nominal operating voltage within

the specified V_CCINTrise time. If the power supply cannot

meet this requirement, then the device might not perform

power-on reset properly. During the power-up sequence,

OE/RESET is held Low by the PROM. Once the required

supplies have reached their respective POR (Power On

Reset) thresholds, the OE/RESET release is delayed (T_OER

minimum) to allow more margin for the power supplies to

stabilize before initiating configuration. The OE/RESET pin

is connected to an external 4.7kΩ pull-up resistor and also

to the target FPGA's INIT pin. For systems utilizing slow-ris-

ing power supplies, an additional power monitoring circuit

can be used to delay the target configuration until the sys-

tem power reaches minimum operating voltages by holding

the OE/RESET pin Low. When OE/RESET is released, the

FPGA’s INIT pin is pulled High allowing the FPGA's config-

uration sequence to begin. If the power drops below the

power-down threshold (V_CCPD), the PROM resets and

OE/RESET is again held Low until the after the POR thresh-

old is reached. OE/RESET polarity is not programmable.

These power-up requirements are shown graphically in

Figure 16.

For a fully powered Platform Flash PROM, a reset occurs

whenever OE/RESET is asserted (Low) or CE is deas-

serted (High). The address counter is reset, CEO is driven

High, and the remaining outputs are placed in a high-imped-

ance state.

Notes:

1. The XCFxxS PROM only requires V_CCINTto rise above

its POR threshold before releasing OE/RESET.

2. The XCFxxP PROM requires both V_CCINTto rise above

its POR threshold and for V_CCOto reach the

recommended operating voltage level before releasing

OE/RESET.

V_CCINT

Recommended Operating Range

Delay or Restart

Configuration

50 ms ramp

200 µs ramp

V_CCPOR

V_CCPD

A slow-ramping V

supply may still

CCINT

be below the minimum operating

voltage when OE/RESET is released.

In this case, the configuration

sequence must be delayed until both

V

and V

have reached their

CCINT

CCO

TIME (ms)

recommended operating conditions.

T_OER

T_RST

ds123_21_103103

Figure 16: Platform Flash PROM Power-Up Requirements

I/O Input Voltage Tolerance and Power

Sequencing

The I/Os on each re-programmable Platform Flash PROM

are fully 3.3V-tolerant. This allows 3V CMOS signals to con-

nect directly to the inputs without damage. The core power

supply (V_CCINT), JTAG pin power supply (V_CCJ), output

power supply (V_CCO), and external 3V CMOS I/O signals

can be applied in any order.

Standby Mode

The PROM enters a low-power standby mode whenever CE

is deasserted (High). In standby mode, the address counter

is reset, CEO is driven High, and the remaining outputs are

placed in a high-impedance state regardless of the state of

the OE/RESET input. For the device to remain in the

low-power standby mode, the JTAG pins TMS, TDI, and

TDO must not be pulled Low, and TCK must be stopped

(High or Low).

Additionally, for the XCFxxS PROM only, when V_CCOis sup-

plied at 2.5V or 3.3V and V_CCINTis supplied at 3.3V, the

I/Os are 5V-tolerant. This allows 5V CMOS signals to con-

nect directly to the inputs on a powered XCFxxS PROM

without damage. Failure to power the PROM correctly while

supplying a 5V input signal may result in damage to the

XCFxxS device.

When using the FPGA DONE signal to drive the PROM CE

pin High to reduce standby power after configuration, an

external pull-up resistor should be used. Typically a 330Ω

pull-up resistor is used, but refer to the appropriate FPGA

data sheet for the recommended DONE pin pull-up value. If

the DONE circuit is connected to an LED to indicate FPGA

DS123 (v2.6) March 14, 2005

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22

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

configuration is complete, and is also connected to the

PROM CE pin to enable low-power standby mode, then an

external buffer should be used to drive the LED circuit to

ensure valid transitions on the PROM’s CE pin. If low-power

standby mode is not required for the PROM, then the CE pin

should be connected to ground.

Table 9: Truth Table for XCFxxS PROM Control Inputs

Control Inputs

Outputs

OE/RESET

CE

Internal Address

If address < TC⁽²⁾: increment

If address = TC⁽²⁾: don't change

Held reset

DATA

Active

High-Z

CEO

High

Low

ICC

Active

High

Low

Reduced

Active

Low

X⁽¹⁾

Low

High

Held reset

Standby

Notes:

1. X = don’t care.

2. TC = Terminal Count = highest address value. TC + 1 = address 0.

Table 10: Truth Table for XCFxxP PROM Control Inputs

Control Inputs

Outputs

OE/RESET

CE

CF

BUSY⁽⁵⁾

Internal Address

DATA

CEO

CLKOUT

ICC

If address < TC⁽²⁾and

Active

High-Z

High

Low

High

Active

address < EA⁽³⁾: increment

If address < TC⁽²⁾and

address = EA⁽³⁾: don't change

High

Low

High

Low

High-Z

Active

Reduced

Active

Else

If address = TC⁽²⁾: don't change

Active and

Unchanged

High

Low

High

Unchanged

High

Low

X

Low

High

↑

X⁽¹⁾

X

Reset⁽⁴⁾

Active

High-Z

High

Active

High-Z

Active

X

Held reset⁽⁴⁾

X

Standby

Notes:

1. X = don’t care.

2. TC = Terminal Count = highest address value. TC + 1 = address 0.

3. For the XCFxxP with Design Revisioning enabled, EA = end address (last address in the selected design revision).

4. For the XCFxxP with Design Revisioning enabled, Reset = address reset to the beginning address of the selected bank. If Design Revisioning is not

enabled, then Reset = address reset to address 0.

5. The BUSY input is only enabled when the XCFxxP is programmed for parallel data output and decompression is not enabled.

DC Electrical Characteristics

This data sheet is a Preliminary data sheet. The DC characteristics are based on characterization rather than simulation.

Further characteristic changes are not expected.

•Absolute Maximum Ratings, page 24

•Supply Voltage Requirements for Power-On Reset and Power-Down, page 24

•Recommended Operating Conditions, page 25

•Quality and Reliability Characteristics, page 25

•DC Characteristics Over Operating Conditions, page 26

DS123 (v2.6) March 14, 2005

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23

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

AC Electrical Characteristics

This data sheet is a Preliminary data sheet. The AC characteristics are based on characterization rather than simulation.

Further characteristic changes are not expected.

•AC Characteristics Over Operating Conditions, page 28

•AC Characteristics Over Operating Conditions When Cascading, page 32

Absolute Maximum Ratings

XCF01S, XCF02S,

XCF04S

XCF08P, XCF16P,

XCF32P

Symbol

V_CCINT

V_CCO

Description

Internal supply voltage relative to GND

I/O supply voltage relative to GND

JTAG I/O supply voltage relative to GND

Units

V

–0.5 to +4.0

–0.5 to +3.6

–0.5 to +5.5

–0.5 to +3.6

–0.5 to +5.5

–65 to +150

+125

–0.5 to +2.7

–0.5 to +4.0

–0.5 to +3.6

–65 to +150

+125

V

V_CCJ

V

V_CCO< 2.5V

V_CCO≥ 2.5V

V_CCO< 2.5V

V_CCO≥ 2.5V

V

V_IN

Input voltage with respect to GND

Voltage applied to High-Z output

V

V_TS

V

T_STG

T_J

Storage temperature (ambient)

Junction temperature

°C

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins can

undershoot to –2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to

200 mA.

2. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to

Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.

3. For soldering guidelines, see the information on "Packaging and Thermal Characteristics" at www.xilinx.com.

Supply Voltage Requirements for Power-On Reset and Power-Down

XCF01S, XCF02S,

XCF04S

XCF08P, XCF16P,

XCF32P

Symbol

T_VCC

Description

Min

0.2

1

Max

Min

0.2

0.5

-

Max

50

-

Units

ms

V

V_CCINTrise time from 0V to nominal voltage⁽²⁾

POR threshold for the V_CCINTsupply

OE/RESET release delay following POR⁽³⁾

Power-down threshold for V_CCINTsupply

50

-

V_CCPOR

T_OER

0.5

-

3

30

0.5

ms

V

V_CCPD

1

Time required to trigger a device reset when the V_CCINT

supply drops below the maximum V_CCPDthreshold

T_RST

10

-

10

-

ms

Notes:

1.

V

, V

, and V

supplies may be applied in any order.

CCJ

CCINT CCO

2. At power up, the device requires the V

power supply to monotonically rise to the nominal operating voltage within the specified T

rise time.

VCC

CCINT

If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See Figure 16, page 22.

3. If the V and V

supplies do not reach their respective recommended operating conditions before the OE/RESET pin is released, then the

CCO

CCINT

configuration data from the PROM will not be available at the recommended threshold levels. The configuration sequence must be delayed until both

and V have reached their recommended operating conditions.

V

CCINT

CCO

DS123 (v2.6) March 14, 2005

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24

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

Recommended Operating Conditions

XCF01S, XCF02S, XCF04S

XCF08P, XCF16P, XCF32P

Symbol

Description

Min

3.0

2.3

1.7

-

Typ

Max

3.6

Min

Typ

Max

2.0

Units

V

V_CCINT

Internal voltage supply

3.3

1.65

1.8

3.3V Operation

3.3

3.6

3.0

3.3

3.6

V

Supply voltage

for output

drivers

2.5V Operation

1.8V Operation

1.5V Operation

3.3V Operation

2.5V Operation

3.3V Operation

2.5V Operation

1.8V Operation

1.5V Operation

3.3V Operation

2.5V Operation

2.5

2.7

2.3

2.5

2.7

V

V_CCO

V_CCJ

V_IL

1.8

1.9

1.7

1.8

1.9

V

-

TBD

1.5

TBD

3.6

V

3.0

2.3

0

3.3

3.6

3.0

3.3

V

Supply voltage

for JTAG

output drivers

2.5

2.7

2.3

2.5

2.7

V

-

0.8

0

-

0.8

V

0

0.8

0

0.8

V

Low-level input

voltage

-

20% V_CCO

-

20% V_CCO

TBD

3.6

V

-

0

V

2.0

1.7

5.5

2.0

V

5.5

1.7

3.6

V

High-levelinput

voltage

V_IH

1.8V Operation 70% V_CCO

3.6

70% V_CCO

3.6

V

1.5V Operation

-

TBD

-

3.6

V

T_IN

V_O

Input signal transition time⁽¹⁾

Output voltage

500

V_CCO

85

500

V_CCO

85

ns

V

0

T_A

Operating ambient temperature

–40

°C

Notes:

1. Input signal transition time measured between 10% V_CCOand 90% V_CCO

.

Quality and Reliability Characteristics

Symbol

T_DR

Description

Min

Max

Units

Years

Cycles

Volts

Data retention

20

-

N_PE

Program/erase cycles (Endurance)

Electrostatic discharge (ESD)

20,000

2,000

V_ESD

DS123 (v2.6) March 14, 2005

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25

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

DC Characteristics Over Operating Conditions

XCF01S, XCF02S,

XCF04S

XCF08P, XCF16P,

XCF32P

Test

Symbol

Description

Conditions Min Max Conditions Min Max Units

High-level output voltage for 3.3V outputs

I_OH= –4 mA

2.4

-

I_OH= –4 mA

2.4

-

V

V_CCO

– 0.4

V_CCO

– 0.4

High-level output voltage for 2.5V outputs

High-level output voltage for 1.8V outputs

I_OH= –500 µA

-

I

_OH= –500 µA

-

V

V_OH

V_CCO

– 0.4

V_CCO

– 0.4

I

_OH= –50 µA

-

I

_OH= –50 µA

-

V

High-level output voltage for 1.5V outputs

Low-level output voltage for 3.3V outputs

Low-level output voltage for 2.5V outputs

Low-level output voltage for 1.8V outputs

Low-level output voltage for 1.5V outputs

Internal voltage supply current, active mode

Output driver supply current, active serial mode

Output driver supply current, active parallel mode

JTAG supply current, active mode

-

0.4

-

I_OH= TBD

I_OL= 4 mA

TBD

-

0.4

TBD

10

40

5

V

I_OL= 4 mA

-

I_OL= 500 µA

I_OL= 50 µA

-

I_OL= 500 µA

I_OL= 50 µA

I_OL= TBD

33 MHz

V

V_OL

V

I_CCINT

33 MHz

-

10

-

mA

33 MHz

(1)

I_CCO

33 MHz

I_CCJ

Note (2)

Note (3)

5

Note (2)

I_CCINTS

I_CCOS

I_CCJS

Internal voltage supply current, standby mode

Output driver supply current, standby mode

JTAG supply current, standby mode

5

Note (3)

5

1

Note (3)

1

Note (3)

1

V_CCJ= max

V_IN= GND

V_CCJ= max

V_IN= GND

I_ILJ

-

100

10

-

100

10

µA

JTAG pins TMS, TDI, and TDO pull-up current

V_CCINT= max

V_CCO= max

V_CCINT= max

V_CCO= max

I_IL

Input leakage current

–10

µA

V_IN= GND or

V_CCO

V_IN= GND or

V_CCO

V_CCINT= max

V_CCO= max

V_CCINT= max

V_CCO= max

I_IH

–10

10

–10

10

100

-

µA

Input and output High-Z leakage current

V_IN= GND or

V_CCO

V_IN= GND or

V_CCO

V_CCINT= max

Source current through internal pull-ups on

EN_EXT_SEL, REV_SEL0, REV_SEL1

V_CCO= max

I_ILP

-

V_IN= GND or

V_CCO

V_CCINT= max

V_CCO= max

I_IHP

Sink current through internal pull-down on BUSY

-

-100

V_IN= GND or

V_CCO

DS123 (v2.6) March 14, 2005

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26

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

XCF01S, XCF02S,

XCF04S

XCF08P, XCF16P,

XCF32P

Test

Symbol

Description

Conditions Min Max Conditions Min Max Units

V_IN= GND

f = 1.0 MHz

V_IN= GND

f = 1.0 MHz

C_IN

Input capacitance

-

8

-

8

pF

V_IN= GND

f = 1.0 MHz

V_IN= GND

f = 1.0 MHz

C_OUT

Output capacitance

14

Notes:

1. Output driver supply current specification based on no load conditions.

2. TDI/TMS/TCK non-static (active).

3. CE High, OE Low, and TMS/TDI/TCK static.

DS123 (v2.6) March 14, 2005

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27

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

AC Characteristics Over Operating Conditions

T

SCE

CE

OE/RESET

CLK

T

HCE

HOE

T

CYC

LC

HC

T

CLKO

CLKOUT

(optional)

T

CEC

T

HB

SB

T

OEC

CDD

COH

T

DF

OH

BUSY

(optional)

T

CAC

OE

CE

T

DATA

T

OH

CF

EN_EXT_SEL

T

HXT

SXT

T

HRV

REV_SEL[1:0]

SRV

ds123_22_110403

XCF01S, XCF02S,

XCF04S

XCF08P, XCF16P,

XCF32P

Symbol

Description

Min

Max

10

Min

Max

25

Units

ns

OE/RESET to data delay⁽⁶⁾when V_CCO= 3.3V or 2.5V

OE/RESET to data delay⁽⁶⁾when V_CCO= 1.8V

CE to data delay⁽⁵⁾when V_CCO= 3.3V or 2.5V

CE to data delay⁽⁵⁾when V_CCO= 1.8V

-

T_OE

30

25

ns

15

25

ns

T_CE

30

25

ns

CLK to data delay⁽⁷⁾when V_CCO= 3.3V or 2.5V

CLK to data delay⁽⁷⁾when V_CCO= 1.8V

15

25

ns

T_CAC

30

25

ns

Data hold from CE, OE/RESET, or CLK

when V_CCO= 3.3V or 2.5V

0

-

5

-

ns

T_OH

Data hold from CE, OE/RESET, or CLK

when V_CCO= 1.8V

-

CE or OE/RESET to data float delay⁽²⁾

when V_CCO= 3.3V or 2.5V

25

30

45

T_DF

CE or OE/RESET to data float delay⁽²⁾

when V_CCO= 1.8V

-

Clock period⁽⁷⁾(serial mode) when V_CCO= 3.3V or 2.5V

Clock period⁽⁷⁾(serial mode) when V_CCO= 1.8V

Clock period⁽⁷⁾(parallel mode) when V_CCO= 3.3V or 2.5V

Clock period⁽⁷⁾(parallel mode) when V_CCO= 1.8V

30

67

-

25

30

-

ns

T_CYC

-

DS123 (v2.6) March 14, 2005

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28

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

XCF01S, XCF02S,

XCF04S

XCF08P, XCF16P,

XCF32P

Symbol

T_LC

Description

Min

10

Max

Min

12

Max

Units

ns

CLK Low time⁽³⁾when V_CCO= 3.3V or 2.5V

CLK Low time⁽³⁾when V_CCO= 1.8V

CLK High time⁽³⁾when V_CCO= 3.3V or 2.5V

CLK High time⁽³⁾when V_CCO= 1.8V

-

15

12

ns

10

12

ns

T_HC

15

12

ns

CE setup time to CLK (guarantees proper counting)⁽³⁾

when V_CCO= 3.3V or 2.5V

20

30

-

30

-

ns

T_SCE

CE setup time to CLK (guarantees proper counting)⁽³⁾

when V_CCO= 1.8V

30

CE hold time (guarantees counters are reset)⁽⁵⁾

when V_CCO= 3.3V or 2.5V

250

-

2000

T_HCE

CE hold time (guarantees counters are reset)⁽⁵⁾

when V_CCO= 1.8V

OE/RESET hold time (guarantees counters are reset)⁽⁶⁾

when V_CCO= 3.3V or 2.5V

T_HOE

OE/RESET hold time (guarantees counters are reset)⁽⁶⁾

when V_CCO= 1.8V

BUSY setup time to CLK when V_CCO= 3.3V or 2.5V

BUSY setup time to CLK when V_CCO= 1.8V

BUSY hold time to CLK when V_CCO= 3.3V or 2.5V

BUSY hold time to CLK when V_CCO= 1.8V

-

12

8

-

ns

T_SB

T_HB

8

CLK input to CLKOUT output delay

when V_CCO= 3.3V or 2.5V

-

35

1

ns

µs

CLK input to CLKOUT output delay

when V_CCO= 1.8V

T_CLKO

CLK input to CLKOUT output delay

-

when V_CCO= 3.3V or 2.5V with decompression⁽¹²⁾

CLK input to CLKOUT output delay

-

when V_CCO= 1.8V with decompression⁽¹²⁾

CE to CLKOUT delay⁽⁸⁾with CLKOUT sourced from

internal oscillator, when V_CCO= 3.3V or 2.5V

0

CE to CLKOUT delay⁽⁸⁾with CLKOUT sourced from

internal oscillator, when V_CCO= 1.8V

1

T_CEC

CE to CLKOUT delay⁽⁸⁾with CLKOUT sourced from

external CLK input, when V_CCO= 3.3V or 2.5V

2 CLK

cycles

-

0

-

CE to CLKOUT delay⁽⁸⁾with CLKOUT sourced from

external CLK input, when V_CCO= 1.8V

2 CLK

cycles

OE/RESET to CLKOUT delay⁽⁸⁾with CLKOUT sourced

from internal oscillator, when V_CCO= 3.3V or 2.5V

-

0

1

µs

OE/RESET to CLKOUT delay⁽⁸⁾with CLKOUT sourced

from internal oscillator, when V_CCO= 1.8V

T_OEC

OE/RESET to CLKOUT delay⁽⁸⁾with CLKOUT sourced

from external CLK input , when V_CCO= 3.3V or 2.5V

2 CLK

cycles

0

-

OE/RESET to CLKOUT delay⁽⁸⁾with CLKOUT sourced

from external CLK input, when V_CCO= 1.8V

2 CLK

cycles

DS123 (v2.6) March 14, 2005

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29

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

XCF01S, XCF02S,

XCF04S

XCF08P, XCF16P,

XCF32P

Symbol

Description

Min

Max

Min

Max

22

Units

ns

CLKOUT to data delay when V_CCO= 3.3V or 2.5V⁽⁹⁾

CLKOUT to data delay when V_CCO= 1.8V⁽⁹⁾

-

T_CDD

22

ns

Data setup time to CLKOUT

5

-

ns

when V_CCO= 3.3V or 2.5V with decompression^(9)(12)

T_DDC

Data setup time to CLKOUT

when V_CCO= 1.8V with decompression^(9)(12)

Data hold from CLKOUT

when V_CCO= 3.3V or 2.5V

3

-

Data hold from CLKOUT

when V_CCO= 1.8V

3

T_COH

Data hold from CLKOUT

3

when V_CCO= 3.3V or 2.5V with decompression⁽¹²⁾

Data hold from CLKOUT

3

when V_CCO= 1.8V with decompression⁽¹²⁾

EN_EXT_SEL setup time to CF (rising edge)

when V_CCO= 3.3V or 2.5V

300

T_SXT

T_HXT

T_SRV

EN_EXT_SEL setup time to CF (rising edge)

when V_CCO= 1.8V

EN_EXT_SEL hold time from CF (rising edge)

when V_CCO= 3.3V or 2.5V

EN_EXT_SEL hold time from CF (rising edge)

when V_CCO= 1.8V

REV_SEL setup time to CF (rising edge)

when V_CCO= 3.3V or 2.5V

REV_SEL setup time to CF (rising edge)

when V_CCO= 1.8V

REV_SEL hold time from CF (rising edge)

when V_CCO= 3.3V or 2.5V

T_HRV

REV_SEL hold time from CF (rising edge)

when V_CCO= 1.8V

-

300

25

-

ns

CLKOUT default (fast) frequency⁽¹⁰⁾

50

25

MHz

F_F

CLKOUT default (fast) frequency

with decompression⁽¹²⁾

12.5

DS123 (v2.6) March 14, 2005

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30

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

XCF01S, XCF02S,

XCF04S

XCF08P, XCF16P,

XCF32P

Symbol

Description

Min

Max

Min

Max

Units

CLKOUT alternate (slower) frequency⁽¹¹⁾

-

12.5

25

MHz

F_S

CLKOUT alternate (slower) frequency

with decompression⁽¹²⁾

-

6

12.5

MHz

Notes:

1. AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30pF for XCF08P/XCF16P/XCF32P.

2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady-state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0V and V = 3.0V.

IL

IH

5. If T

6. If T

High < 2 µs, T = 2 µs.

HCE

CE

Low < 2 µs, T = 2 µs.

HOE

OE

7. This is the minimum possible T

. Actual T

= T

CCO

+ FPGA Data setup time.

CYC

CAC

Example: With the XCF32P in serial mode with V

at 3.3V, if FPGA Data setup time = 15 ns, then the actual T

= 25 ns +15 ns = 40 ns.

CYC

8. The delay before the enabled CLKOUT signal begins clocking data out of the device is dependent on the clocking configuration. The delay before

CLKOUT is enabled will increase if decompression is enabled.

9. Slower CLK frequency option may be required to meet the FPGA data sheet setup time.

10. Typical CLKOUT default (fast) period = 25 ns (40 MHz)

11. Typical CLKOUT alternate (slower) period = 50 ns (20 MHz)

12. When decompression is enabled, the CLKOUT signal becomes a controlled clock output. When decompressed data is available, CLKOUT will toggle

at ½ the source clock frequency (either ½ the selected internal clock frequency or ½ the external CLKIN frequency). When decompressed data is not

available, CLKOUT remains High.

DS123 (v2.6) March 14, 2005

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31

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

AC Characteristics Over Operating Conditions When Cascading

OE/RESET

CE

CLK

CLKOUT

(optional)

T

CDF

CODF

DATA

CEO

Last Bit

First Bit

T

OCE

OOE

T

OCK

COCE

ds123_23_102203

XCF01S, XCF02S,

XCF04S

XCF08P, XCF16P,

XCF32P

Symbol

Description

Min

Max

Min

Max

Units

CLK to output float delay^(2,3)

when V_CCO= 2.5V or 3.3V

-

25

-

20

ns

T_CDF

CLK to output float delay^(2,3)when V_CCO= 1.8V

-

35

20

35

20

35

20

35

-

20

80

20

ns

CLK to CEO delay^(3,5)when V_CCO= 2.5V or 3.3V

CLK to CEO delay^(3,5)when V_CCO= 1.8V

T_OCK

T_OCE

T_OOE

T_COCE

CE to CEO delay^(3,6)when V_CCO= 2.5V or 3.3V

CE to CEO delay^(3,6)when V_CCO= 1.8V

OE/RESET to CEO delay⁽³⁾when V_CCO= 2.5V or 3.3V

OE/RESET to CEO delay⁽³⁾when V_CCO= 1.8V

CLKOUT to CEO delay when V_CCO= 2.5V or 3.3V

CLKOUT to CEO delay when V_CCO= 1.8V

-

CLKOUT to output float delay

when V_CCO= 2.5V or 3.3V

-

25

ns

T_CODF

CLKOUT to output float delay when V_CCO= 1.8V

Notes:

1. AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30 pF for XCF08P/XCF16P/XCF32P.

2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V = 0.0V and V = 3.0V.

IL

IH

5. For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins are set to persist as configuration pins, the minimum period is increased

based on the CLK to CEO and CE to data propagation delays:

- T

minimum = T

+ T + FPGA Data setup time.

CYC

CAC

OCK CE

OCK

maximum = T

+ T

CE

6. For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins become general I/O pins after configuration; to allow for the disable to

propagate to the cascaded PROMs and to avoid contention on the data lines following configuration, the minimum period is increased based on the

CE to CEO and CE to data propagation delays:

- T

minimum = T

+ T

CYC

CAC

OCE CE

OCK

maximum = T

+ T

CE

DS123 (v2.6) March 14, 2005

Preliminary Product Specification

www.xilinx.com

32

R

Platform Flash In-System Programmable Configuration PROMS

Pinouts and Pin Descriptions

The XCFxxS Platform Flash PROM is available in the VO20 and VOG20 packages. The XCFxxP Platform Flash PROM is

available in the VO48, VOG48, FS48, and FSG48 packages. This section includes:

•

Table 11, XCFxxS Pin Names and Descriptions, page 33

Figure 17, VO20/VOG20 Pinout Diagram (Top View) with Pin Names, page 34

Table 12, XCFxxP Pin Names and Descriptions, page 35

Figure 18, VO48/VOG48 Pinout Diagram (Top View) with Pin Names, page 36

Table 13, FS48/FSG48 Pin Number/Name Reference, page 38

Figure 19, FS48/FSG48 Pinout Diagram (Top View), page 38

Notes:

1. VO20/VOG20 denotes a 20-pin (TSSOP) Plastic Thin Shrink Small Outline Package

2. VO48/VOG48 denotes a 48-pin (TSOP) Plastic Thin Small Outline Package.

3. FS48/FSG48 denotes a 48-pin (TFBGA) Plastic Thin Fine Pitch Ball Grid Array (0.8 mm pitch).

XCFxxS Pinouts and Pin Descriptions

Table 11 provides a list of the pin names and descriptions for the XCFxxS 20-pin VO20/VOG20 package.

Table 11: XCFxxS Pin Names and Descriptions

Boundary

20-pin TSSOP

(VO20/VOG20)

Pin Name Scan Order Scan Function

Pin Description

D0 is the DATA output pin to provide data for configuring an

FPGA in serial mode. The D0 output is set to a

high-impedance state during ISPEN (when not clamped).

4

3

Data Out

D0

1

3

Output Enable

Configuration Clock Input. Each rising edge on the CLK input

increments the internal address counter if the CLK input is

selected, CE is Low, and OE/RESET is High.

CLK

0

Data In

20

19

18

Data In

Data Out

Output Enable/Reset (Open-Drain I/O). When Low, this input

holds the address counter reset and the DATA output is in a

high-impedance state. This is a bidirectional open-drain pin

that is held Low while the PROM is reset. Polarity is not

programmable.

OE/RESET

8

Output Enable

Chip Enable Input. When CE is High, the device is put into

low-power standby mode, the address counter is reset, and

the DATA pins are put in a high-impedance state.

CE

CF

15

Data In

10

7

Configuration Pulse (Open-Drain Output). Allows JTAG

CONFIG instruction to initiate FPGA configuration without

powering down FPGA. This is an open-drain output that is

pulsed Low by the JTAG CONFIG command.

22

21

Data Out

Output Enable

Chip Enable Output. Chip Enable Output (CEO) is connected

to the CE input of the next PROM in the chain. This output is

Low when CE is Low and OE/RESET input is High, AND the

internal address counter has been incremented beyond its

Terminal Count (TC) value. CEO returns to High when

OE/RESET goes Low or CE goes High.

12

11

Data Out

CEO

13

Output Enable

JTAG Mode Select Input. The state of TMS on the rising edge

of TCK determines the state transitions at the Test Access

Port (TAP) controller. TMS has an internal 50KΩ resistive

pull-up to V_CCJto provide a logic "1" to the device if the pin is

not driven.

TMS

TCK

Mode Select

Clock

5

6

JTAG Clock Input. This pin is the JTAG test clock. It

sequences the TAP controller and all the JTAG test and

programming electronics.

DS123 (v2.6) March 14, 2005

Preliminary Product Specification

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33

R

Platform Flash In-System Programmable Configuration PROMS

Table 11: XCFxxS Pin Names and Descriptions (Continued)

Boundary Boundary

Pin Name Scan Order Scan Function

20-pin TSSOP

(VO20/VOG20)

Pin Description

JTAG Serial Data Input. This pin is the serial input to all JTAG

instruction and data registers. TDI has an internal 50KΩ

resistive pull-up to V_CCJto provide a logic "1" to the device if

the pin is not driven.

TDI

Data In

4

JTAG Serial Data Output. This pin is the serial output for all

JTAG instruction and data registers. TDO has an internal

50KΩ resistive pull-up to V_CCJto provide a logic "1" to the

system if the pin is not driven.

TDO

Data Out

17

VCCINT

VCCO

+3.3V Supply. Positive 3.3V supply voltage for internal logic.

18

19

+3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V

supply voltage connected to the output voltage drivers and

input buffers.

+3.3V, 2.5V, or 1.8V JTAG I/O Supply. Positive 3.3V, 2.5V, or

1.8V supply voltage connected to the TDO output voltage

driver and TCK, TMS, and TDI input buffers.

VCCJ

20

GND

DNC

Ground

11

Do not connect. (These pins must be left unconnected.)

2, 9, 12, 14, 15, 16

XCFxxS Pinout Diagram

1

2

3

4

5

6

7

8

9

10

20

19

18

17

D0

(DNC)

CLK

VCCJ

VCCO

VCCINT

TDO

TDI

VO20/VOG20

16

15

14

13

12

11

TMS

(DNC)

CEO

Top View

TCK

CF

OE/RESET

(DNC)

CE

(DNC)

GND

ds123_02_071304

Figure 17: VO20/VOG20 Pinout Diagram (Top View)

with Pin Names

DS123 (v2.6) March 14, 2005

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34

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

XCFxxP Pinouts and Pin Descriptions

Table 12 provides a list of the pin names and descriptions for the XCFxxP 48-pin VO48/VOG48 and 48-pin FS48/FSG48

packages.

Table 12: XCFxxP Pin Names and Descriptions

48-pin

TSOP

(VO48/

48-pin

TFBGA

(FS48/

Boundary

Scan

Boundary

Scan

Pin Name

D0

Order

Function

Pin Description

VOG48) FSG48)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

Data Out

Output Enable

Data Out

28

29

32

33

43

44

47

48

H6

H5

E5

D5

C5

B5

A5

A6

D1

D2

D3

D4

D5

D6

D7

Output Enable

Data Out

D0 is the DATA output pin to provide data for configuring an

FPGA in serial mode.

Output Enable

Data Out

D0-D7 are the DATA output pins to provide parallel data for

configuring a Xilinx FPGA in SelectMap (parallel) mode.

Output Enable

Data Out

The D0 output is set to a high-impedance state during ISPEN

(when not clamped).

The D1-D7 outputs are set to a high-impedance state during

ISPEN (when not clamped) and when serial mode is selected

for configuration. The D1-D7 pins can be left unconnected

when the PROM is used in serial mode.

Output Enable

Data Out

Output Enable

Data Out

Output Enable

Data Out

Output Enable

Configuration Clock Input. An internal programmable control

bit selects between the internal oscillator and the CLK input

pin as the clock source to control the configuration sequence.

Each rising edge on the CLK input increments the internal

address counter if the CLK input is selected, CE is Low,

OE/RESET is High, BUSY is Low (parallel mode only), and

CF is High.

CLK

01

Data In

12

B3

Output Enable/Reset (Open-Drain I/O).

04

03

02

Data In

Data Out

When Low, this input holds the address counter reset and the

DATA and CLKOUT outputs are placed in a high-impedance

state. This is a bidirectional open-drain pin that is held Low

while the PROM is reset. Polarity is not programmable.

OE/RESET

CE

11

13

A3

B4

Output Enable

Chip Enable Input. When CE is High, the device is put into

low-power standby mode, the address counter is reset, and

the DATA and CLKOUT outputs are placed in a

high-impedance state.

00

Data In

Configuration Pulse (Open-Drain I/O). As an output, this pin

allows the JTAG CONFIG instruction to initiate FPGA

11

10

Data In

configuration without powering down the FPGA. This is an

open-drain signal that is pulsed Low by the JTAG CONFIG

command. As an input, on the rising edge of CF, the current

design revision selection is sampled and the internal address

counter is reset to the start address for the selected revision.

If unused, the CF pin should be pulled High using an external

Data Out

CF

6

D1

09

Output Enable

4.7KΩ pull-up to V_CCO

.

DS123 (v2.6) March 14, 2005

Preliminary Product Specification

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35

R

Platform Flash In-System Programmable Configuration PROMS

Table 12: XCFxxP Pin Names and Descriptions (Continued)

48-pin

TSOP

(VO48/

48-pin

TFBGA

(FS48/

Boundary

Scan

Boundary

Scan

Pin Name

Order

Function

Pin Description

VOG48) FSG48)

Chip Enable Output. Chip Enable Output (CEO) is connected

to the CE input of the next PROM in the chain. This output is

Low when CE is Low and OE/RESET input is High, AND the

internal address counter has been incremented beyond its

Terminal Count (TC) value. CEO returns to High when

OE/RESET goes Low or CE goes High.

06

05

Data Out

CEO

10

25

D2

H4

Output Enable

Enable External Selection Input. When this pin is Low, design

revision selection is controlled by the Revision Select pins.

When this pin is High, design revision selection is controlled

by the internal programmable Revision Select control bits.

EN_EXT_SEL has an internal 50KΩ resistive pull-up to V_CCO

to provide a logic "1" to the device if the pin is not driven.

EN_EXT_SEL

31

Data In

Revision Select[1:0] Inputs. When the EN_EXT_SEL is Low,

the Revision Select pins are used to select the design

revision to be enabled, overriding the internal programmable

Revision Select control bits. The Revision Select[1:0] inputs

have an internal 50KΩ resistive pull-up to VCCO to provide a

logic "1" to the device if the pins are not driven.

REV_SEL0

REV_SEL1

30

29

Data In

26

27

G3

G4

Busy Input. The BUSY input is enabled when parallel mode

is selected for configuration. When BUSY is High, the internal

address counter stops incrementing and the current data

remains on the data pins. On the first rising edge of CLK after

BUSY transitions from High to Low, the data for the next

address is driven on the data pins. When serial mode or

decompression is enabled during device programming, the

BUSY input is disabled. BUSY has an internal 50KΩ resistive

pull-down to GND to provide a logic "0" to the device if the pin

is not driven.

BUSY

12

Data In

5

C1

Configuration Clock Output. An internal Programmable

control bit enables the CLKOUT signal, which is sourced from

either the internal oscillator or the CLK input pin. Each rising

edge of the selected clock source increments the internal

address counter if data is available, CE is Low, and

OE/RESET is High. Output data is available on the rising

edge of CLKOUT. CLKOUT is disabled if CE is High or

OE/RESET is Low. If decompression is enabled, CLKOUT is

disabled when decompressed data is not ready. When

CLKOUT is disabled, the CLKOUT pin is put into a high-Z

state. If CLKOUT is used, then it must be pulled High

08

07

Data Out

CLKOUT

9

C2

Output Enable

externally using a 4.7KΩ pull-up to V_CCO

.

JTAG Mode Select Input. The state of TMS on the rising edge

of TCK determines the state transitions at the Test Access

Port (TAP) controller. TMS has an internal 50KΩ resistive

pull-up to V_CCJto provide a logic "1" to the device if the pin is

not driven.

TMS

Mode Select

21

E2

JTAG Clock Input. This pin is the JTAG test clock. It

sequences the TAP controller and all the JTAG test and

programming electronics.

TCK

TDI

Clock

20

19

H3

G1

JTAG Serial Data Input. This pin is the serial input to all JTAG

instruction and data registers. TDI has an internal 50KΩ

resistive pull-up to V_CCJto provide a logic "1" to the device if

the pin is not driven.

Data In

DS123 (v2.6) March 14, 2005

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36

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Platform Flash In-System Programmable Configuration PROMS

Table 12: XCFxxP Pin Names and Descriptions (Continued)

48-pin

TSOP

(VO48/

48-pin

TFBGA

(FS48/

Boundary

Scan

Boundary

Scan

Pin Name

Order

Function

Pin Description

VOG48) FSG48)

JTAG Serial Data Output. This pin is the serial output for all

JTAG instruction and data registers. TDO has an internal

50KΩ resistive pull-up to V_CCJto provide a logic "1" to the

system if the pin is not driven.

TDO

Data Out

22

E6

4, 15,

34

B1, E1,

G6

VCCINT

VCCO

+1.8V Supply. Positive 1.8V supply voltage for internal logic.

+3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V

supply voltage connected to the output voltage drivers and

input buffers.

8, 30,

38, 45

B2, C6,

D6, G5

+3.3V, 2.5V, or 1.8V JTAG I/O Supply. Positive 3.3V, 2.5V, or

1.8V supply voltage connected to the TDO output voltage

driver and TCK, TMS, and TDI input buffers.

VCCJ

GND

24

H2

2, 7,

17, 23,

31, 36,

46

A1, A2,

B6, F1,

F5, F6,

H1

Ground

1, 3,

14, 16,

18, 35,

37, 39,

40, 41,

42

A4, C3,

C4, D3,

D4, E3,

E4, F2,

F3, F4,

G2

DNC

Do Not Connect. (These pins must be left unconnected.)

XCFxxP Pinout Diagrams

DNC

1

GND

2

DNC

3

48

47

46

45

44

43

42

41

40

39

D7

D6

GND

VCCO

D5

D4

DNC

VCCJ

VCCINT

4

BUSY

5

CF

6

GND

7

VCCO

8

CLKOUT

9

CEO

10

DNC

OE/RESET

11

38

37

36

35

VCCO

DNC

GND

VO48/VOG48

CLK

12

CE

13

DNC

14

Top

View

DNC

VCCINT

15

34

33

32

31

30

29

28

27

26

25

VCCINT

D3

D2

GND

VCCO

D1

DNC

16

GND

17

DNC

18

TDI

19

TCK

20

TMS

21

TDO

22

GND

23

D0

REV_SEL1

REV_SEL0

EN_EXT_SEL

24

Figure 18: VO48/VOG48 Pinout Diagram (Top View) with Pin Names

DS123 (v2.6) March 14, 2005

Preliminary Product Specification

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37

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Platform Flash In-System Programmable Configuration PROMS

Table 13: FS48/FSG48 Pin Number/Name Reference

Number

Pin Name

CF

Pin Name

GND

Pin Name

GND

Pin Name

VCCINT

TMS

D1

D2

D3

D4

D5

D6

H1

H2

H3

H4

H5

H6

A1

A2

A3

A4

A5

A6

B1

B2

B3

B4

B5

B6

C1

C2

C3

C4

C5

C6

E1

E2

E3

E4

E5

E6

F1

F2

F3

F4

F5

F6

G1

G2

G3

G4

G5

G6

CEO

VCCJ

GND

DNC

TCK

OE/RESET

DNC

EN_EXT_SEL

D1

DNC

D3

D6

D2

VCCO

D0

D7

TDO

VCCINT

VCCO

CLK

GND

DNC

FS48/FSG48

Top View

DNC

CE

DNC

1

2

3

4

5

6

D5

GND

A

B

C

D

E

F

BUSY

CLKOUT

DNC

TDI

DNC

REV_SEL0

REV_SEL1

VCCO

VCCINT

DNC

D4

G

H

VCCO

ds121_01_071604

DS123 (v2.6) March 14, 2005

Preliminary Product Specification

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38

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Platform Flash In-System Programmable Configuration PROMS

Ordering Information

XCF04S VO20 C

Device Number

Operating Range/Processing

XCF01S

XCF02S

XCF04S

C = (T_A= –40°C to +85°C)

Package Type

VO20 = 20-pin TSSOP Package

VOG20 = 20-pin TSSOP Package, Pb-free

XCF32P FS48 C

Device Number

Operating Range/Processing

XCF08P

XCF16P

XCF32P

C = (T_A= –40°C to +85°C)

Package Type

VO48 = 48-pin TSOP Package

VOG48 = 48-pin TSOP Package, Pb-free

FS48 = 48-pin TFBGA Package

FSG48 = 48-pin TFBGA Package, Pb-free

Valid Ordering Combinations

XCF01SVO20 C XCF08PVO48 C XCF08PFS48 C XCF01SVOG20 C XCF08PVOG48 C

XCF02SVO20 C XCF16PVO48 C XCF16PFS48 C XCF02SVOG20 C XCF16PVOG48 C

XCF04SVO20 C XCF32PVO48 C XCF32PFS48 C XCF04SVOG20 C XCF32PVOG48 C

XCF08PFSG48 C

XCF16PFSG48 C

XCF32PFSG48 C

Marking Information

XCF04S-V

Device Number

Operating Range/Processing

C = (T_A= –40°C to +85°C)

XCF01S

XCF02S

XCF04S

XCF08P

XCF16P

XCF32P

Package Type

V = 20-pin TSSOP Package (VO20)

VG = 20-pin TSSOP Package, Pb-free (VOG20)

VO48 = 48-pin TSOP Package (VO48)

VOG48 = 48-pin TSOP Package, Pb-free (VOG48)

F48 = 48-pin TFBGA Package (FS48)

FG48 = 48-pin TFBGA Package, Pb-free (FSG48)

DS123 (v2.6) March 14, 2005

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39

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

Revision History

The following table shows the revision history for this document.

Date

Version

1.0

Revision

04/29/03

06/03/03

11/05/03

11/18/03

Xilinx Initial Release.

Made edits to all pages.

Major revision.

1.1

2.0

2.1

Pinout corrections as follows:

•

Table 12:

-

For VO48 package, removed 38 from VCCINT and added it to VCCO.

For FS48 package, removed pin D6 from VCCINT and added it to VCCO.

Table 13 (FS48 package):

-

For pin D6, changed name from VCCINT to VCCO.

For pin A4, changed name from GND to DNC.

Figure 18 (VO48 package): For pin 38, changed name from VCCINT to VCCO.

12/15/03

05/07/04

2.2

2.3

•

Added specification (4.7kΩ) for recommended pull-up resistor on OE/RESET pin to

section Reset and Power-On Reset Activation, page 22.

•

Added paragraph to section Standby Mode, page 22, concerning use of a pull-up

resistor and/or buffer on the DONE pin.

•

Section Features, page 1: Added package styles and 33 MHz configuration speed

limit to itemized features.

•

Section Description, page 1 and following: Added state conditions for CF and

BUSY to the descriptive text.

•

Table 2, page 3: Updated Virtex-II configuration bitstream sizes.

Section Design Revisioning, page 9: Rewritten.

Section PROM to FPGA Configuration Mode and Connections Summary,

page 10 and following, five instances: Added instruction to tie CF High if it is not tied

to the FPGA’s PROG_B (PROGRAM) input.

•

Figure 8, page 14, through Figure 15, page 21: Added footnote indicating the

directionality of the CF pin in each configuration.

•

Section I/O Input Voltage Tolerance and Power Sequencing, page 22: Rewritten.

Table 10, page 23: Added CF column to truth table, and added an additional row to

document the Low state of CF.

•

Section Absolute Maximum Ratings, page 24: Revised V_INand V_TSfor ’P’

devices.

Section Supply Voltage Requirements for Power-On Reset and Power-Down,

page 24:

-

Revised footnote callout number on T_OERfrom Footnote (4) to Footnote (3).

Added Footnote (2) callout to T_VCC

.

•

Section Recommended Operating Conditions, page 25:

-

Added Typical (Typ) parameter columns and parameters for V_CCINTand

_CCO/V_CCJ

V

.

-

Added 1.5V operation parameter row to V_ILand V_IH, ’P’ devices.

Revised V_IHMin, 2.5V operation, from 2.0V to 1.7V.

Added parameter row T_INand Max parameters

•

(Continued on next page)

DS123 (v2.6) March 14, 2005

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40

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

05/07/04

(cont’d)

2.3

(cont’d)

•

Section DC Characteristics Over Operating Conditions, page 26:

-

Added parameter row and parameters for parallel configuration mode, ’P’

devices, to I_CCO

.

-

Added Footnote (1) and Footnote (2) with callouts in the Test Conditions column

for I_CCJ, I_CCINTS, I_CCOS, and I_CCJS, to define active and standby mode

requirements.

Section AC Characteristics Over Operating Conditions, page 28:

-

Corrected description for second T_CACparameter line to show parameters for

1.8V V_CCO

.

-

Revised Footnote (7) to indicate V_CCO= 3.3V.

Applied Footnote (7) to second T_CYCparameter line.

•

Section AC Characteristics Over Operating Conditions When Cascading,

page 32: Revised Footnote (5)T_CYCMin and T_CACMin formulas.

Table 12, page 35:

-

Added additional state conditions to CLK description.

Added function of resetting the internal address counter to CF description.

07/20/04

10/18/04

2.4

2.5

•

Added Pb-free package options VOG20, FSG48, and VOG48.

Figure 8, page 14, and Figure 9, page 15: Corrected connection name for FPGA

DOUT (OPTIONAL Daisy-chained Slave FPGAs with different configurations) from

DOUT to DIN.

•

Section Absolute Maximum Ratings, page 24: Removed parameter T_SOLfrom

table. (T_SOLinformation can be found in Package User Guide.)

•

Table 2, page 3: Removed reference to XC2VP125 FPGA.

Table 1, page 1: Broke out V_CCO/ V_CCJinto two separate columns.

Table 7, page 7: Added clarification of ID code die revision bits.

•

Table 8, page 8: Deleted T_CKMIN2(bypass mode) and renamed T_CKMIN1to T_CKMIN

.

•

Table Recommended Operating Conditions, page 25: Separated V_CCOand V_CCJ

parameters.

•

Table DC Characteristics Over Operating Conditions, page 26:

-

Added most parameter values for XCF08P, XCF16P, XCF32P devices.

Added Footnote (1) to I_CCOspecifying no-load conditions.

•

Table AC Characteristics Over Operating Conditions, page 28:

-

Added most parameter values for XCF08P, XCF16P, XCF32P devices.

Expanded Footnote (1) to include XCF08P, XCF16P, XCF32P devices.

Added Footnote (8) through (11) relating to CLKOUT conditions for various

parameters.

-

Added rows to T_CYCspecifying parameters for parallel mode.

Added rows specifying parameters with decompression for T_CLKO, T_COH, T_FF,

T_SF.

-

Added T_DDC(setup time with decompression).

•

Table AC Characteristics Over Operating Conditions When Cascading,

page 32:

-

Added most parameter values for XCF08P, XCF16P, XCF32P devices.

Separated Footnote (5) into Footnotes (5) and (6) to specify different

derivations of T_CYC, depending on whether dual-purpose configuration pins

persist as configuration pins, or become general I/O pins after configuration.

DS123 (v2.6) March 14, 2005

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41

Preliminary Product Specification

R

Platform Flash In-System Programmable Configuration PROMS

03/14/05

2.6

•

Added Virtex-4 LX/FX/SX configuration data to Table 2.

Corrected Virtex-II configuration data in Table 2.

Corrected Virtex-II Pro configuration data in Table 2.

Added Spartan-3L configuration data to Table 2.

Added Spartan-3E configuration data to Table 2.

Paragraph added to FPGA Master SelectMAP (Parallel) Mode (1), page 11.

Changes to DC Characteristics

-

T_OERchanged, page 26.

I_OLchanged for V_OL, page 26.

V_CCOadded to test conditions for I_IL, I_ILP, I_IHP,and II_H, page 26. Values modified

for I_ILPand I_IHP.

•

Changes to AC Characteristics

-

T_LCand T_HCmodified for 1.8V, page 29.

New rows added for T_CECand T_OEC, page 29.

•

Minor changes to grammar and punctuation.

Add explanation of "Preliminary" to DC and AC Electrical Characteristics.

DS123 (v2.6) March 14, 2005

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42

Preliminary Product Specification


型号：	XCF32PVG
厂家：	XILINX, INC
描述：	Platform Flash In-System Programmable Configuration PROMS Platform Flash在系统可编程配置PROM 可编程只读存储器
文件：	总42页 (文件大小：356K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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