XCR3032XL-10 [XILINX]
XCR3032XL 32 Macrocell CPLD; XCR3032XL 32宏单元CPLD
| 型号： | XCR3032XL-10 |
| 厂家： | 
XILINX, INC |
| 描述： | XCR3032XL 32 Macrocell CPLD |
| 文件： | 总8页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XCR3032XL 32 Macrocell CPLD
0
14
DS023 (v1.6) June 27, 2002
Preliminary Product Specification
Features
Description
•
•
•
•
•
Lowest power 32 macrocell CPLD
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of two function blocks provide
750 usable gates. Pin-to-pin propagation delays are 5.0 ns
with a maximum system frequency of 200 MHz.
5.0 ns pin-to-pin logic delays
System frequencies up to 200 MHz
32 macrocells with 750 usable gates
Available in small footprint packages
-
-
-
48-ball CS BGA (36 user I/O pins)
44-pin VQFP (36 user I/O)
44-pin PLCC (36 user I/O)
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
•
•
Optimized for 3.3V systems
-
-
-
Ultra-low power operation
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five layer metal EEPROM
process
Fast Zero Power™ (FZP) CMOS design
technology
-
Figure 1 and Table 1 showing the I vs. Frequency of our
CC
XCR3032XL TotalCMOS CPLD (data taken with two
resetable up/down, 16-bit counters at 3.3V, 25°C).
Advanced system features
-
-
-
-
-
-
-
-
In-system programming
Input registers
Predictable timing model
Up to 23 available clocks per function block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
20
15
10
Eight product term control terms per function block
•
•
•
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
5
0
2.7V to 3.6V supply voltage at industrial temperature
range
•
•
•
Programmable slew rate control per macrocell
Security bit prevents unauthorized access
0
20
40
60
80 100 120
140 160 180 200
Refer to XPLA3 family data sheet (DS012) for
Frequency (MHz)
architecture description
DS023_01_080101
Figure 1: I vs. Frequency at V = 3.3V, 25°C
CC
CC
Table 1:
Frequency (MHz)
Typical I (mA)
I
vs. Frequency (V
= 3.3V, 25°C)
CC
CC
0
1
5
10
20
50
100
200
20.3
0.02
0.13
0.54
1.06
2.09
5.2
10.26
CC
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS023 (v1.6) June 27, 2002
www.xilinx.com
1
Preliminary Product Specification
1-800-255-7778
R
XCR3032XL 32 Macrocell CPLD
DC Electrical Characteristics Over Recommended Operating Conditions(1)
Symbol
Parameter
Test Conditions
Min.
Max.
-
Unit
V
(2)
V
Output High voltage
V
V
= 3.0V to 3.6V, I
= –8 mA
2.4
OH
CC
CC
OH
OH
(3)
= 2.7V to 3.0V, I
= –500 µA
= –8 mA
2.0
-
V
I
90% V
-
V
OH
CC
V
Output Low voltage
Input leakage current
I/O High-Z leakage current
Standby current
I
= 8 mA
OL
-
0.4
10
10
100
0.25
7.5
8
V
OL
(4)
I
I
I
I
V
V
V
= GND or V
= GND or V
–10
µA
µA
µA
mA
mA
pF
pF
pF
IL
IN
CC
CC
(4)
–10
IH
IN
= 3.6V
-
-
-
-
-
-
CCSB
CC
CC
(5,6)
Dynamic current
f = 1 MHz
f = 50 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
(7)
C
C
C
Input pin capacitance
IN
(7)
Clock input capacitance
12
10
CLK
(7)
I/O pin capacitance
I/O
Notes:
1. See XPLA3 family data sheet (DS012) for recommended operating conditions
2. See Figure 2 for output drive characteristics of the XPLA3 family.
3. This parameter guaranteed by design and characterization, not by testing.
4. Typical leakage current is less than 1 µA.
5. See Table 1, Figure 1 for typical values.
6. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and
unloaded. Inputs are tied to V or ground. This parameter guaranteed by design and characterization, not testing.
CC
7. Typical values, not tested.
100
90
I
(3.3V)
OL
80
70
60
50
40
30
I
(3.3V)
OH
I
(2.7V)
OH
20
10
0
0
0.5
1
1.5
2
2.5
Volts
3
3.5
4
4.5
5
DS012_10_031802
Figure 2: Typical I/V Curve for the XPLA3 Family, 3.3V, 25°C
2
www.xilinx.com
DS023 (v1.6) June 27, 2002
1-800-255-7778
Preliminary Product Specification
R
XCR3032XL 32 Macrocell CPLD
AC Electrical Characteristics Over Recommended Operating Conditions(1,2)
-5
-7
-10
Symbol
Parameter
Min.
Max.
4.5
5.0
3.5
-
Min.
Max.
7.0
7.5
5.0
-
Min.
Max.
9.1
10.0
6.5
-
Unit
ns
T
T
T
T
T
T
T
T
T
T
T
Propagation delay time (single p-term)
-
-
-
PD1
PD2
CO
(3)
Propagation delay time (OR array)
-
ns
Clock to output (global synchronous pin clock)
Setup time (fast input register)
Setup time (single p-term)
Setup time (OR array)
-
ns
2.5
3.0
3.0
ns
SUF
(4)
3.0
-
4.3
-
5.4
-
ns
SU1
3.5
-
4.8
-
6.3
-
ns
SU2
(4)
H
Hold time
0
-
0
-
0
-
ns
(4)
Global Clock pulse width (High or Low)
P-term clock pulse width
Input rise time
2.5
-
3.0
-
4.0
-
ns
WLH
(4)
4.0
-
5.0
-
6.0
-
ns
PLH
(4)
R
-
-
-
-
-
-
-
-
-
20
20
200
30
30
7.2
7.2
6.0
6.5
-
-
-
-
-
-
-
-
-
20
20
119
30
30
9.3
9.3
8.3
9.3
-
-
-
-
-
-
-
-
-
20
20
95
30
30
11.2
11.2
10.7
11.2
ns
(4)
L
Input fall time
ns
(4)
f
Maximum system frequency
MHz
µs
µs
ns
SYSTEM
(4)
(5)
T
T
T
T
T
T
Configuration time
CONFIG
(4)
ISP initialization time
INIT
(4)
P-term OE to output enabled
POE
(4)
(6)
P-term OE to output disabled
ns
POD
(4)
P-term clock to output
ns
PCO
(4)
P-term set/reset to output valid
ns
PAO
Notes:
1. Specifications measured with one output switching.
2. See XPLA3 family data sheet (DS012) for recommended operating conditions.
3. See Figure 4 for derating.
4. These parameters guaranteed by design and/or characterization, not testing.
5. Typical current draw during configuration is 3 mA at 3.6V.
6. Output C = 5 pF.
L
DS023 (v1.6) June 27, 2002
www.xilinx.com
3
Preliminary Product Specification
1-800-255-7778
R
XCR3032XL 32 Macrocell CPLD
Internal Timing Parameters(1,2)
-5
-7
-10
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Buffer Delays
T
T
T
T
T
Input buffer delay
-
-
-
-
-
0.7
2.2
0.7
1.8
4.5
-
-
-
-
-
1.6
3.0
1.0
2.7
5.0
-
-
-
-
-
2.2
3.1
1.3
3.6
5.7
ns
ns
ns
ns
ns
IN
Fast Input buffer delay
FIN
GCK
OUT
EN
Global Clock buffer delay
Output buffer delay
Output buffer enable/disable delay
Internal Register, Product Term, and Combinatorial Delays
T
T
T
T
T
T
Latch transparent delay
-
1.0
0.3
2.0
3.0
-
1.3
-
-
1.6
-
-
1.2
0.7
3.0
5.5
-
2.0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LDI
Register setup time
1.0
SUI
Register hold time
-
0.5
-
-
HI
Register clock enable setup time
Register clock enable hold time
Register clock to output delay
Register async. S/R to output delay
Register async. recovery
-
2.5
-
-
ECSU
ECHO
COI
-
4.5
-
-
1.0
2.0
3.5
2.5
2.0
2.5
-
-
-
-
-
-
1.3
2.3
5.0
2.7
2.7
3.2
1.6
2.1
6.0
3.3
3.3
4.2
T
-
-
AOI
T
-
-
RAI
T
T
T
Product term clock delay
-
-
PTCK
LOGI1
LOGI2
Internal logic delay (single p-term)
Internal logic delay (PLA OR term)
-
-
-
-
Feedback Delays
ZIA delay
Time Adders
T
-
0.5
-
2.9
-
3.5
ns
F
T
T
T
Fold-back NAND delay
Universal delay
-
-
-
2.0
1.2
4.0
-
-
-
2.5
2.0
5.0
-
-
-
3.0
2.5
6.0
ns
ns
ns
LOGI3
UDA
Slew rate limited delay
SLEW
Notes:
1. These parameters guaranteed by design and characterization, not testing.
2. See XPLA3 family data sheet (DS012) for timing model.
4
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1-800-255-7778
DS023 (v1.6) June 27, 2002
Preliminary Product Specification
R
XCR3032XL 32 Macrocell CPLD
Switching Characteristics
V
CC
S1
Component
Values
R1
R2
C1
390Ω
390Ω
35 pF
R1
V
IN
V
OUT
Measurement
S1
S2
Open
Closed
Open
T
(High)
(Low)
POE
R2
C1
T
Closed
Closed
POE
T
Closed
P
Note: For T
, C1 = 5 pF. Delay measured at
POD
output level of V + 300 mV, V
– 300 mV.
OH
OL
S2
DS023_03_102401
Figure 3: AC Load Circuit
4.5
+3.0V
0V
90%
10%
4.0
3.5
T
T
L
R
1.5 ns
1.5 ns
Measurements:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
3.0
1
2
4
8
16
DS023_06_042800
Outputs
Figure 5: Voltage Waveform
DS023_05_061101
Figure 4: Derating Curve for T
PD2
DS023 (v1.6) June 27, 2002
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
5
R
XCR3032XL 32 Macrocell CPLD
Table 3: XCR3032XL I/O Pins
Pin Descriptions
Function
Table 2: XCR3032XL User I/O Pins
Block
Macrocell
PC44
25
VQ44
19
CS48
G5
PC44
VQ44
CS48
2
2
15
16
Total User I/O Pins
36
36
36
24
18
F4
Notes:
1. JTAG pins
Table 3: XCR3032XL I/O Pins
Function
Block
Macrocell
PC44
VQ44
42
CS48
A2
1
1
2
4
5
6
Table 4: XCR3032XL Global, JTAG, Port Enable, Power,
and No Connect Pins
1
43
A1
1
3
44
C4
Pin Type
IN0 / CLK0
IN1 / CLK1
IN2 / CLK2
IN3 / CLK3
TCK
PC44
2
VQ44
40
39
38
37
26
1
CS48
A3
(1)
(1)
(1)
1
4
7
1
B1
1
5
8
9
2
3
5
6
C2
C1
D3
D1
1
B4
1
6
44
43
32
7
A4
1
7
11
12
B5
1
8
E5
(1)
(1)
(1)
1
9
13
7
D2
TDI
B1
1
10
11
12
13
14
15
16
1
14
16
17
18
19
20
21
41
40
39
8
E1
F1
G1
E4
F2
G2
F3
C5
A6
B6
TDO
38
13
32
7
B7
1
10
11
12
13
14
15
35
34
33
TMS
D2
(1)
(1)
(1)
1
PORT_EN
10
4
C3
1
V
3, 15, 23,
35
9, 17, 29,
41
B3, C7,
E2, G4
CC
1
GND
22, 30, 42 16, 24, 36 A5, E3, E6
1
No Connects
-
-
A7, B2,
F6, G3
1
2
Notes:
1. Port Enable is brought High to enable JTAG pins when
JTAG pins are used as I/O. See family data sheet
(DS012) for full explanation.
2
2
2
3
(1)
(1)
(1)
2
4
38
32
B7
2
5
37
36
34
33
31
30
28
27
D4
C6
D6
D7
2
6
2
7
2
8
(1)
(1)
(1)
2
9
32
26
E5
2
10
11
12
13
14
31
29
28
27
26
25
23
22
21
20
E7
F7
G7
G6
F5
2
2
2
2
6
www.xilinx.com
1-800-255-7778
DS023 (v1.6) June 27, 2002
Preliminary Product Specification
R
XCR3032XL 32 Macrocell CPLD
Ordering Information
Example:
XCR3032XL -5 VQ 44 C
Device Type
Temperature Range
Number of Pins
Package Type
Speed Grade
Device Ordering Options
Speed
Package
Temperature
= 0°C to +70°C
-10 10 ns pin-to-pin
delay
PC44
VQ44
CS48
44-pin Plastic Lead Chip Carrier
(PLCC)
C = Commercial
I = Industrial
T
A
V
= 3.0V to 3.6V
CC
-7 7.5 ns pin-to-pin
delay
44-pin Very Thin Quad Flat Pack
(VQFP)
T = –40°C to +85°C
A
V
= 2.7V to 3.6V
CC
-5 5 ns pin-to-pin delay
48-ball Chip Scale Package
Component Availability
Pins
Type
Code
44
44
48
Plastic PLCC
Plastic VQFP
Plastic BGA
PC44
C
VQ44
C
CS48
C
XCR3032XL
-5
-7
C,I
C,I
C,I
-10
C, I
C, I
C, I
DS023 (v1.6) June 27, 2002
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
7
R
XCR3032XL 32 Macrocell CPLD
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
11/18/00
02/05/01
04/11/01
Initial Xilinx release.
1.1
Removed Timing Model.
1.2
Update TSUF spec to meet UMC characterization data. Added Icc vs. Freq. numbers,
Table 1 and updated Figure 1. Added Typical I/V curve, Figure 2; added Table 2: Total User
I/O; changed V
spec.
OH
04/19/01
08/27/01
1.3
1.4
Updated Typical I/V curve, Figure 2: added voltage levels.
Changed from Advance to Preliminary; updated DC Electrical Characteristics; AC Electrical
Characteristics; Internal Timing Parameters; added Derating Curve; added -10 industrial
packages. Added 200 MHz to Figure 1 and Table 1. changed -5 F
to 0.5 ns.
to 200 MHz, -5 T
SYSTEM
F
01/08/02
06/27/02
1.5
1.6
Updated T spec to correct a typo. Added single p-term setup time (T
) to AC Table,
SU1
HI
renamed T to T
for setup time through the OR array. Updated AC Load Circuit diagram
SU
SU2
to more closely resemble true test conditions, added note for T
delay
POD
measurement.Updated note 5 in AC Characteristics table lowering typical current draw
during configuration.
Added voltage and temperature to Figure 2. Increased -5 T
to 6.0 (from 5.5 ns) by
PCO
adding T
parameter to internal timing model.
PTCK
8
www.xilinx.com
1-800-255-7778
DS023 (v1.6) June 27, 2002
Preliminary Product Specification
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