XCR3128-15VQ100I [XILINX]
XCR3128: 128 Macrocell CPLD; XCR3128 ： 128宏单元CPLD
| 型号： | XCR3128-15VQ100I |
| 厂家： | 
XILINX, INC |
| 描述： | XCR3128: 128 Macrocell CPLD |
| 文件： | 总18页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTE
0
R
XCR3128: 128 Macrocell CPLD
0
14*
DS034 (v1.2) August 10, 2000
Product Specification
Introduction
Description
•
•
•
Industry's first TotalCMOS™ PLD - both CMOS design
and process technologies
Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
The XCR3128 CPLD (Complex Programmable Logic
Device) is the third in a family of CoolRunner® CPLDs from
Xilinx. These devices combine high speed and zero power
in a 128 macrocell CPLD. With the FZP design technique,
the XCR3128 offers true pin-to-pin speeds of 10 ns, while
simultaneously delivering power that is less than 100 µA at
standby without the need for ‘turbo-bits’ or other
power-down schemes. By replacing conventional sense
amplifier methods for implementing product terms (a tech-
nique that has been used in PLDs since the bipolar era)
with a cascaded chain of pure CMOS gates, the dynamic
power is also substantially lower than any competing
CPLD. These devices are the first TotalCMOS PLDs, as
they use both a CMOS process technology and the pat-
ented full CMOS FZP design technique. For 5V applica-
tions, Xilinx also offers the high speed XCR5128 CPLD that
offers these features in a full 5V implementation.
IEEE 1149.1-compliant, JTAG Testing Capability
-
-
-
Four pin JTAG interface (TCK, TMS, TDI, TDO)
IEEE 1149.1 TAP Controller
JTAG commands include: Bypass, Sample/Preload,
Extest, Usercode, Idcode, HighZ
•
3.3V, In-System Programmable (ISP) using the JTAG
interface
-
-
On-chip supervoltage generation
ISP commands include: Enable, Erase, Program,
Verify
-
Supported by multiple ISP programming plat-
forms
•
•
•
High speed pin-to-pin delays of 10 ns
Ultra-low static power of less than 100 µA
100% routable with 100% utilization while all pins and
all macrocells are fixed
Deterministic timing model that is extremely simple to
use
The Xilinx FZP CPLDs utilize the patented XPLA
(eXtended Programmable Logic Array) architecture. The
XPLA architecture combines the best features of both PLA
and PAL type structures to deliver high speed and flexible
logic allocation that results in superior ability to make
design changes with fixed pinouts. The XPLA structure in
each logic block provides a fast 10 ns PAL path with five
dedicated product terms per output. This PAL path is joined
by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can
allocate the PLA product terms to any output in the logic
block. This combination allows logic to be allocated effi-
ciently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic
is allocated from the PLA array to an output is only 2.5 ns,
regardless of the number of PLA product terms used, which
results in worst case tPD’s of only 12.5 ns from any pin to
any other pin. In addition, logic that is common to multiple
outputs can be placed on a single PLA product term and
shared across multiple outputs via the OR array, effectively
increasing design density.
•
•
•
•
•
Four clocks available
Programmable clock polarity at every macrocell
Support for asynchronous clocking
Innovative XPLA™ architecture combines high-speed
with extreme flexibility
1000 erase/program cycles guaranteed
20 years data retention guaranteed
Logic expandable to 37 product terms
PCI compliant
Advanced 0.5µ E2CMOS process
Security bit prevents unauthorized access
Design entry and verification using industry standard
and Xilinx CAE tools
•
•
•
•
•
•
•
•
•
Reprogrammable using industry standard device
programmers
Innovative control term structure provides either sum
terms or product terms in each logic block for:
The XCR3128 CPLDs are supported by industry standard
CAE tools (CadencE/OrCAD, Exemplar Logic, Mentor,
Synopsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-
ification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms. Device fitting
uses a Xilinx developed tool, XPLA Professional (available
on the Xilinx web site).
-
-
-
Programmable 3-state buffer
Asynchronous macrocell register preset/reset
Programmable global 3-state pin facilitates "bed of
nails" testing without using logic resources
Available in PLCC, VQFP, and PQFP packages
Available in both commercial and industrial grades
-
-
DS034 (v1.2) August 10, 2000
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XCR3128: 128 Macrocell CPLD
The XCR3128 CPLD is electrically reprogrammable using
industry standard device programmers from vendors such
as Data I/O, BP Microsystems, SMS, and others. The
XCR3128 also includes an industry-standard, IEEE
1149.1, JTAG interface through which in-system program-
ming (ISP) and reprogramming of the device is supported.
by a Zero-power Interconnect Array (ZIA). The ZIA is a vir-
tual crosspoint switch. Each logic block is essentially a
36V16 device with 36 inputs from the ZIA and 16 macro-
cells. Each logic block also provides 32 ZIA feedback paths
from the macrocells and I/O pins.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner
family unique is what is inside each logic block and the
design technique used to implement these logic blocks.
The contents of the logic block will be described next.
XPLA Architecture
Figure 1 shows a high level block diagram of a 128 macro-
cell device implementing the XPLA architecture. The XPLA
architecture consists of logic blocks that are interconnected
MC0
MC0
MC1
MC1
36
36
LOGIC
BLOCK
LOGIC
BLOCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MC15
MC15
16
16
16
16
MC0
MC1
MC0
MC1
36
36
LOGIC
BLOCK
LOGIC
BLOCK
MC15
MC15
16
16
16
16
ZIA
MC0
MC1
MC0
MC1
36
36
LOGIC
BLOCK
LOGIC
BLOCK
MC15
MC15
16
16
16
16
MC0
MC1
MC0
MC1
36
36
LOGIC
BLOCK
LOGIC
BLOCK
I/O
MC15
MC15
16
16
16
16
SP00464
Figure 1: Xilinx XPLA Architecture
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XCR3128: 128 Macrocell CPLD
Logic Block Architecture
Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin tPD of the XCR3128 device
through the PAL array is 10 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macro-
cells. The additional propagation delay incurred by a mac-
rocell using one or all 32 PLA product terms is just 2.5 ns.
So the total pin-to-pin tPD for the XCR3128 using six to 37
product terms is 12.5 ns (10 ns for the PAL + 2.5 ns for the
PLA).
Figure 2 illustrates the logic block architecture. Each logic
block contains control terms, a PAL array, a PLA array, and
16 macrocells. the six control terms can individually be con-
figured as either SUM or PRODUCT terms, and are used to
control the preset/reset and output enables of the 16 mac-
rocells’ flip-flops. The PAL array consists of a programma-
ble AND array with a fixed OR array, while the PLA array
consists of a programmable AND array with a programma-
ble OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased
product term density.
36 ZIA INPUTS
6
CONTROL
5
PAL
ARRAY
PLA
ARRAY
(32)
SP00435A
Figure 2: Xilinx XPLA Logic Block Architecture
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XCR3128: 128 Macrocell CPLD
control terms (CT2-CT5) can be used to control the Output
Enable of the macrocell’s output buffers. The reason there
are as many control terms dedicated for the Output Enable
of the macrocell is to insure that all CoolRunner devices are
PCI compliant. The macrocell’s output buffers can also be
always enabled or disabled. All CoolRunner devices also
provide a Global 3-state (GTS) pin, which, when enabled
and pulled Low, will 3-state all the outputs of the device.
This pin is provided to support "In-circuit Testing" or
"Bed-of-nails" testing.
Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in
the CoolRunner family. The macrocell consists of a flip-flop
that can be configured as either a D- or T-type. A D-type
flip-flop is generally more useful for implementing state
machines and data buffering. A T-type flip-flop is generally
more useful in implementing counters. All CoolRunner fam-
ily members provide both synchronous and asynchronous
clocking and provide the ability to clock off either the falling
or rising edges of these clocks. These devices are
designed such that the skew between the rising and falling
edges of a clock are minimized for clocking integrity. There
are four clocks available on the XCR3128 device. Clock 0
(CLK0) is designated as the "synchronous" clock and must
be driven by an external source. Clock 1 (CLK1), Clock 2
(CLK2), and Clock 3 (CLK3) can either be used as a syn-
chronous clock (driven by an external source) or as an
asynchronous clock (driven by a macrocell equation). The
timing for asynchronous clocks is different in that the tCO
time is extended by the amount of time that it takes for the
signal to propagate through the array and reach the clock
network, and the tSU time is reduced.
There are two feedback paths to the ZIA: one from the mac-
rocell, and one from the I/O pin. The ZIA feedback path
before the output buffer is the macrocell feedback path,
while the ZIA feedback path after the output buffer is the I/O
pin ZIA path. When the macrocell is used as an output, the
output buffer is enabled, and the macrocell feedback path
can be used to feedback the logic implemented in the mac-
rocell. When the I/O pin is used as an input, the output
buffer will be 3-stated and the input signal will be fed into
the ZIA via the I/O feedback path, and the logic imple-
mented in the buried macrocell can be fed back to the ZIA
via the macrocell feedback path. It should be noted that
unused inputs or I/Os should be properly terminated (see
the section on “Terminations” on page 9 in this data sheet
and the application note Terminating Unused I/O Pins in
Xilinx XPLA1 and XPLA2 CoolRunner™ CPLDs).
Two of the control terms (CT0 and CT1) are used to control
the Preset/Reset of the macrocell’s flip-flop. The Pre-
set/Reset feature for each macrocell can also be disabled.
Note that the Power-on Reset leaves all macrocells in the
"zero" state when power is properly applied. The other four
TO ZIA
PAL
LA
D/T
Q
INIT
(P or R)
GTS
CLK0
CLK0
GND
CT0
CT1
CT2
CT3
CT4
CT5
CLK1
CLK1
CLK2
CLK2
GND
CLK3
CLK3
V
CC
GND
SP00457
Figure 3: XCR3128 Macrocell Architecture
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XCR3128: 128 Macrocell CPLD
Simple Timing Model
TotalCMOS Design Technique for Fast Zero
Power
Figure 4 shows the CoolRunner Timing Model. The Cool-
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including tPD, tSU, and tCO. In other competing architec-
tures, the user may be able to fit the design into the CPLD,
but is not sure whether system timing requirements can be
met until after the design has been fit into the device. This is
because the timing models of competing architectures are
very complex and include such things as timing dependen-
cies on the number of parallel expanders borrowed, shar-
able expanders, varying number of X and Y routing
channels used, etc. In the XPLA architecture, the user
knows up front whether the design will meet system timing
requirements. This is due to the simplicity of the timing
model.
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to Figure 5 and Table 1 showing the ICC vs.
Frequency of our XCR3128 TotalCMOS CPLD (data taken
w/eight up/down, loadable 16 bit counters at 3.3V, 25°C).
t
= COMBINATORIAL PAL ONLY
= COMBINATORIAL PAL + PLA
PD_PAL
t
PD_PLA
INPUT PIN
OUTPUT PIN
REGISTERED
= PAL ONLY
t
t
REGISTERED
SU_PAL
= PAL + PLA
t
SU_PLA
CO
INPUT PIN
D
Q
OUTPUT PIN
SP00441
GLOBAL CLOCK PIN
Figure 4: CoolRunner Timing Model
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XCR3128: 128 Macrocell CPLD
140
120
100
80
I
CC
(mA)
60
40
20
0
0
20
40
60
80
100
FREQUENCY (MHz)
SP00471
Figure 5: ICC vs. Frequency @ VCC = 3.3V, 25°C
Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C)
Frequency (MHz)
0
1
20
40
24
60
80
100
Typical ICC (mA)
.03
.06
12
35
46
63
-
Data from pin or core logic signals can be examined
during normal operation
JTAG Testing Capability
JTAG is the commonly-used acronym for the Boundary
Scan Test (BST) feature defined for integrated circuits by
IEEE Standard 1149.1. This standard defines input/output
pins, logic control functions, and commands which facilitate
both board and device level testing without the use of spe-
cialized test equipment. BST provides the ability to test the
external connections of a device, test the internal logic of
the device, and capture data from the device during normal
operation. BST provides a number of benefits in each of the
following areas:
•
Reliability
-
-
-
-
Eliminates physical contacts common to existing test
fixtures (e.g., "bed-of-nails")
Degradation of test equipment is no longer a
concern
Facilitates the handling of smaller, surface-mount
components
Allows for testing when components exist on both
sides of the printed circuit board
•
Cost
•
Testability
-
Reduces/eliminates the need for expensive test
-
Allows testing of an unlimited number of
equipment
interconnects on the printed circuit board
Testability is designed in at the component level
Enables desired signal levels to be set at specific
pins (Preload)
-
-
Reduces test preparation time
Reduces spare board inventories
-
-
The Xilinx XCR3128's JTAG interface includes a TAP Port
and a TAP Controller, both of which are defined by the IEEE
1149.1 JTAG Specification. As implemented in the Xilinx
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XCR3128: 128 Macrocell CPLD
XCR3128, the TAP Port includes four of the five pins (refer
to Table 2) described in the JTAG specification: TCK, TMS,
TDI, and TDO. The fifth signal defined by the JTAG specifi-
cation is TRST* (Test Reset). TRST* is considered an
optional signal, since it is not actually required to perform
BST or ISP. The Xilinx XCR3128 saves an I/O pin for gen-
eral purpose use by not implementing the optional TRST*
signal in the JTAG interface. Instead, the Xilinx XCR3128
supports the test reset functionality through the use of its
power up reset circuit, which is included in all Xilinx CPLDs.
The pins associated with the power up reset circuit should
connect to an external pull-up resistor to keep the JTAG
signals from floating when they are not being used.
ever, unlike competing CPLD’s, the Xilinx XCR3128 does
allow the macrocell logic associated with these dedicated
pins to be used as buried logic even when JTAG/ISP is
selected. Table 3 defines the dedicated pins used by the
four mandatory JTAG signals for each of the XCR3128
package types.
The JTAG specifications defines two sets of commands to
support boundary-scan testing: high-level commands and
low-level commands. High-level commands are executed
via board test software on an a user test station such as
automated test equipment, a PC, or an engineering work-
station (EWS). Each high-level command comprises a
sequence of low level commands. These low-level com-
mands are executed within the component under test, and
therefore must be implemented as part of the TAP Control-
ler design. The set of low-level boundary-scan commands
implemented in the Xilinx XCR3128 is defined in Table 4.
By supporting this set of low-level commands, the
XCR3128 allows execution of all high-level boundary-scan
commands.
In the Xilinx XCR3128, the four mandatory JTAG pins each
require a unique, dedicated pin on the device. However, if
JTAG and ISP are not desired in the end-application, these
pins may instead be used as additional general I/O pins.
The decision as to whether these pins are used for
JTAG/ISP or as general I/O is made when the JEDEC file is
generated. If the use of JTAG/ISP is selected, the dedi-
cated pins are not available for general purpose use. How-
Table 2: JTAG Pin Description
PIN
NAME
Test Clock Output
DESCRIPTION
TCK
Clock pin to shift the serial data and instructions in and out of the
TDI and TDO pins, respectively. TCK is also used to clock the TAP
Controller state machine.
TMS
TDI
Test Mode Select
Test Data Input
Test Data Output
Serial input pin selects the JTAG instruction mode. TMS should be
driven high during user mode operation.
Serial input pin for instructions and test data. Data is shifted in on
the rising edge of TCK.
TDO
Serial output pin for instructions and test data. Data is shifted out on
the falling edge of TCK. The signal is tri-stated if data is not being
shifted out of the device.
Table 3: XCR3128 JTAG Pinout by Package Type
Device
(Pin Number / Macrocell #)
XCR3128
TCK
TMS
TDI
TDO
84-pin PLCC
100-pin PQFP
100-pin VQFP
128-pin TQFP
160-pin PQFP
62 / 96 (F15)
64 / 96 (F15)
62 / 96 (F15)
82 / 96 (F15)
99 / 96 (F15)
23 / 48 (C15)
17 / 48 (C15)
15 / 48 (C15)
21 / 48 (C15)
22 / 48 (C15)
14 / 32 (B15)
6 / 32 (B15)
4 / 32 (B15)
8 / 32 (B15)
9 / 32 (B15)
71 / 112 (G15)
75 / 112 (G15)
73 / 112 (G15)
95 / 112 (G15)
112/ 112 (G15)
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XCR3128: 128 Macrocell CPLD
Table 4: XCR3128 Low-Level JTAG Boundary-Scan Commands
Instruction
(Instruction Code)
Register Used
Description
Sample/Preload
(0010)
Boundary-Scan Register
The mandatory SAMPLE/PRELOAD instruction allows a snapshot of the normal
operation of the component to be taken and examined. It also allows data values to
be loaded onto the latched parallel outputs of the Boundary-Scan Shift-Register
prior to selection of the other boundary-scan test instructions.
Extest
(0000)
Boundary-Scan Register
The mandatory EXTEST instruction allows testing of off-chip circuitry and board
level interconnections. Data would typically be loaded onto the latched parallel
outputs of Boundary-Scan Shift-Register using the Sample/Preload instruction prior
to selection of the EXTEST instruction.
Bypass
(1111)
Bypass Register
Places the 1 bit bypass register between the TDI and TDO pins, which allows the
BST data to pass synchronously through the selected device to adjacent devices
during normal device operation. The Bypass instruction can be entered by holding
TDI at a constant high value and completing an Instruction-Scan cycle.
Idcode
(0001)
Boundary-Scan Register
Selects the IDCODE register and places it between TDI and TDO, allowing the
IDCODE to be serially shifted out of TDO. The IDCODE instruction permits blind
interrogation of the components assembled onto a printed circuit board. Thus, in
circumstances where the component population may vary, it is possible to deter-
mine what components exist in a product.
HighZ
(0101)
Bypass Register
The HIGHZ instruction places the component in a state in which all of its system
logic outputs are placed in an inactive drive state (e.g., high impedance). In this
state, an in-circuit test system may drive signals onto the connections normally
driven by a component output without incurring the risk of damage to the compo-
nent. The HighZ instruction also forces the Bypass Register between TDI and TDO.
•
Field Support
3.3V In-System Programming (ISP)
-
-
Easy remote upgrades and repair
Support for field configuration, re-configuration, and
customization
ISP is the ability to reconfigure the logic and functionality of
a device, printed circuit board, or complete electronic sys-
tem before, during, and after its manufacture and shipment
to the end customer. ISP provides substantial benefits in
each of the following areas:
The Xilinx XCR3128 allows for 3.3V, in-system program-
ming/reprogramming of its EEPROM cells via its JTAG
interface. An on-chip charge pump eliminates the need for
externally-provided supervoltages, so that the XCR3128
may be easily programmed on the circuit board using only
the 3.3-volt supply required by the device for normal opera-
tion. A set of low-level ISP basic commands implemented in
the XCR3128 enable this feature. The ISP commands
implemented in the Xilinx XCR3128 are specified in Table 5
Please note that an ENABLE command must precede all
ISP commands unless an ENABLE command has already
been given for a preceding ISP command and the device
has not gone through a Test-Logic/Rest TAP Controller
State. See also Table 5 Programming Specifications.
•
Design
-
-
-
-
Faster time-to-market
Debug partitioning and simplified prototyping
Printed circuit board reconfiguration during debug
Better device and board level testing
•
Manufacturing
-
-
-
Multi-Functional hardware
Reconfigurability for test
Eliminates handling of "fine lead-pitch" components
for programming
-
-
Reduced Inventory and manufacturing costs
Improved quality and reliability
DS034 (v1.2) August 10, 2000
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XCR3128: 128 Macrocell CPLD
Table 5: Programming Specifications
Symbol
Parameter
Min.
3.0
Max.
Unit
DC Parameters
VCCP
ICCP
VIH
VCC supply program/verify
ICC limit program/verify
Input voltage (High)
3.6
V
mA
V
200
2.0
VIL
Input voltage (Low)
0.8
0.5
V
VSOL
VSOH
Output voltage (Low)
Output voltage (High)
V
2.4
8
V
TDO_IOL Output current (Low)
TDO_IOH Output current (High)
mA
mA
-8
AC Parameters
fMAX
PWE
PWP
PWV
INIT
CLK maximum frequency
Pulse width erase
10
100
10
MHz
ms
ms
µs
Pulse width program
Pulse width verify
10
Initialization time
100
10
µs
TMS_SU TMS setup time before TCK =
ns
TDI_SU
TMS_H
TDI_H
TDI setup time before TCK =
TMS hold time after TCK =
TDI hold time after TCK =
10
ns
25
ns
25
ns
TDO_CO TDO valid after TCK Ο
40
ns
ting these signals float can cause the voltage on TMS to
come close to ground, which could cause the device to
enter JTAG/ISP mode at unspecified times. See the appli-
cation notes JTAG and ISP Overview for Xilinx XPLA1 and
XPLA2 CPLDs and Terminating Unused I/O Pins in Xilinx
XPLA1 and XPLA2 CoolRunner CPLDs for more informa-
tion.
Terminations
The CoolRunner XCR3128 CPLDs are TotalCMOS
devices. As with other CMOS devices, it is important to
consider how to properly terminate unused inputs and I/O
pins when fabricating a PC board. Allowing unused inputs
and I/O pins to float can cause the voltage to be in the linear
region of the CMOS input structures, which can increase
the power consumption of the device. The XCR3128
CPLDs have programmable on-chip pull-down resistors on
each I/O pin. These pull-downs are automatically activated
by the fitter software for all unused I/O pins. Note that an I/O
macrocell used as buried logic that does not have the I/O
pin used for input is considered to be unused, and the
pull-down resistors will be turned on. We recommend that
any unused I/O pins on the XCR3128 device be left uncon-
nected.
JTAG and ISP Interfacing
A number of industry-established methods exist for
JTAG/ISP interfacing with CPLD’s and other integrated cir-
cuits. The Xilinx XCR3128 supports the following methods:
•
•
•
•
•
•
PC parallel port
Workstation or PC serial port
Embedded processor
Automated test equipment
Third party programmers
High-End JTAG and ISP tools
There are no on-chip pull-down structures associated with
the dedicated input pins. Xilinx recommends that any
unused dedicated inputs be terminated with external 10kΩ
pull-up resistors. These pins can be directly connected to
VCC or GND, but using the external pull-up resistors main-
tains maximum design flexibility should one of the unused
dedicated inputs be needed due to future design changes.
A Boundary-Scan Description Language (BSDL) descrip-
tion of the XCR3128 is also available from Xilinx for use in
test program development. For more details on JTAG and
ISP for the XCR3128, refer to the related application note:
JTAG and ISP Overview for Xilinx XPLA1 and XPLA2
CPLDs.
When using the JTAG/ISP functions, it is also recom-
mended that 10kΩ pull-up resistors be used on each of the
pins associated with the four mandatory JTAG signals. Let-
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XCR3128: 128 Macrocell CPLD
Absolute Maximum Ratings1
Symbol
Parameter
Min.
Max.
Unit
VCC
-0.5
7.0
V
Supply voltage2
VI
VOUT
IIN
-1.2
-0.5
-30
VCC + 0.5
V
V
Input voltage
Output voltage
Input current
Output current
VCC + 0.5
30
mA
mA
°C
°C
IOUT
TJ
-100
-40
100
150
Maximum junction temperature
Storage temperature
Tstr
-65
150
Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only.
Functional operation at these or any other condition above those indicated in the operational and programming specification
is not implied.
2. The chip supply voltage must rise monotonically.
Operating Range
Product Grade
Commercial
Industrial
Temperature
0 to +70°C
Voltage
3.3V ± 10%
3.3V ± 10%
-40 to +85°C
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 3.0V ≤ VCC ≤ 3.6V
Symbol
VIL
Parameter
Input voltage low
Test Conditions
Min.
Max.
Unit
V
VCC = 3.0V
VCC = 3.6V
0.8
VIH
VI
Input voltage high
2.0
V
Input clamp voltage
Output voltage low
Output voltage high
Input leakage current
3-stated output leakage current
Standby current
VCC = 3.0V, IIN = -18 mA
VCC = 3.0V, IOL = 8 mA
VCC = 3.0V, IOH = -8 mA
VIN = 0 to VCC
-1.2
0.5
V
VOL
VOH
II
V
2.4
-10
-10
V
10
10
µA
µA
µA
mA
mA
mA
IOZ
ICCQ
ICCD
VIN = 0 to VCC
1
VCC = 3.6V, TAMB = 0°C
VCC = 3.6V, TAMB = 0°C at 1 MHz
60
1, 2
Dynamic current
2
V
CC = 3.6V, TAMB = 0°C at 50 MHz
50
IOS
CIN
Short circuit output current3
One pin at a time for no longer than 1
second
-50
5
-100
Input pin capacitance3
Clock input capacitance3
I/O pin capacitance3
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1MHz
TAMB = 25°C, f = 1MHz
8
pF
pF
pF
CCLK
CI/O
12
10
Notes:
1. See Table 1 on page 6 for typical values.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled
and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
3. Typical values, not tested.
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XCR3128: 128 Macrocell CPLD
AC Electrical Characteristics1 For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 3.0V ≤ VCC ≤ 3.6V
10
12
15
Symbol
Parameter
Unit
Min. Max. Min. Max. Min. Max.
tPD_PAL
Propagation delay time, input (or feedback node) to
output through PAL
2
3
10
12.5
7
2
3
12
14.5
8
2
3
15
17.5
9
ns
tPD_PLA
Propagation delay time, input (or feedback node) to
output through PAL + PLA
ns
tCO
Clock to out (global synchronous clock from pin)
2
6
2
7
2
8
ns
ns
ns
tSU_PAL
tSU_PLA
Setup time (from input or feedback node) through PAL
Setup time (from input or feedback node) through
PAL + PLA
8.5
9.5
10.5
tH
Hold time
0
0
0
ns
ns
tCH
Clock High time
Clock Low time
Input Rise time
Input Fall time
3
3
4
4
4
4
tCL
ns
tR
20
20
20
20
20
20
ns
tF
ns
fMAX1
fMAX2
fMAX3
tBUF
Maximum FF toggle rate 2 1/(tCH + tCL
Maximum internal frequency 2 1/(tSUPAL + tCF
)
167
87
125
74
125
65
MHz
MHz
MHz
ns
)
Maximum external frequency 2 1/(tSUPAL + tCO
)
77
66
59
Output buffer delay time
1.5
0.5
1.5
1.5
tPDF_PAL Input (or feedback node) to internal feedback node delay
time through PAL
2
3
2
3
10.5
2
3
13.5
ns
tPDF_PLA Input (or feedback node) to internal feedback node delay
time through PAL+PLA
11
13
16
ns
tCF
Clock to internal feedback node delay time
Delay from valid VDD to valid reset
Input to output disable 3
5.5
50
6.5
50
14
14
16
16
7.5
50
17
17
19
19
ns
µs
ns
ns
ns
ns
tINIT
tER
12.5
12.5
14
tEA
Input to output valid
tRP
Input to register preset
tRR
Input to register reset
14
Notes:
1. Specifications measured with one output switching. See Figure 6 and Table 6 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5 pF.
11
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XCR3128: 128 Macrocell CPLD
DC Electrical Characteristics For Industrial Grade Devices
Industrial: -40°C ≤ TAMB ≤ +85°C; 3.0V ≤ VCC ≤ 3.6V
Symbol
VIL
Parameter
Input voltage Low
Test Conditions
Min.
Max.
Unit
V
VCC = 3.0V
VCC = 3.6V
0.8
VIH
VI
Input voltage High
2.0
V
Input clamp voltage
Output voltage Low
Output voltage High
Input leakage current
3-stated output leakage current
Standby current
VCC = 3.0V, IIN = -18 mA
VCC = 3.0V, IOL = 8 mA
VCC = 3.0V, IOH = -8 mA
VIN = 0 to VCC
-1.2
0.5
V
VOL
VOH
II
V
2.4
-10
-10
V
10
10
µA
µA
µA
mA
mA
mA
IOZ
VIN = 0 to VCC
1
ICCQ
VCC = 3.6V, TAMB = -40°C
VCC = 3.6V, TAMB = -40°C at 1 MHz
VCC = 3.6V, TAMB = -40°C at 50 MHz
75
1, 2
ICCD
Dynamic current
2
50
IOS
CIN
Short circuit output current3
Input pin capacitance3
One pin at a time for no longer than 1
second
-50
5
-130
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1MHz
TAMB = 25°C, f = 1MHz
8
pF
pF
pF
CCLK Clock input capacitance3
12
10
CI/O
I/O pin capacitance3
Notes:
1. See Table 1 on page 6 for typical values.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs DISabled
and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
3. Typical values, not tested.
DS034 (v1.2) August 10, 2000
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XCR3128: 128 Macrocell CPLD
AC Electrical Characteristics1 For Industrial Grade Devices
Industrial: -40°C ≤ TAMB ≤ +85°C; 3.0V ≤ VCC ≤ 3.6V
12
15
Symbol
Parameter
Unit
Min. Max. Min. Max.
tPD_PAL
tPD_PLA
Propagation delay time, input (or feedback node) to output through PAL
2
3
12
2
3
15
ns
ns
Propagation delay time, input (or feedback node) to output through
PAL + PLA
14.5
17.5
tCO
Clock to out (global synchronous clock from pin)
2
7
7.5
0
2
8
9
0
ns
ns
tSU_PAL
tSU_PLA
tH
Setup time (from input or feedback node) through PAL
Setup time (from input or feedback node) through PAL + PLA
9.5
10.5
ns
Hold time
ns
tCH
Clock High time
Clock Low time
Input Rise time
Input Fall time
3
3
4
4
ns
tCL
ns
tR
20
20
20
20
ns
tF
ns
fMAX1
fMAX2
fMAX3
tBUF
Maximum FF toggle rate2 1/(tCH + tCL
Maximum internal frequency2 1/(tSUPAL + tCF
)
167
77
125
65
MHz
MHz
MHz
ns
)
Maximum external frequency2 1/(tSUPAL + tCO
)
69
59
Output buffer delay time
1.5
1.5
tPDF_PAL Input (or feedback node) to internal feedback node delay time through
PAL
2
3
10.5
2
3
13.5
ns
tPDF_PLA Input (or feedback node) to internal feedback node delay time through
PAL+PLA
13
16
ns
tCF
Clock to internal feedback node delay time
Delay from valid VCC to valid reset
Input to output disable 3
6
7.5
50
ns
µs
ns
ns
ns
ns
tINIT
tER
50
13
13
15
15
15.5
15.5
17
tEA
Input to output valid
tRP
Input to register preset
tRR
Input to register reset
17
Notes:
1. Specifications measured with one output switching. See Figure 6 and Table 8 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5 pF.
13
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XCR3128: 128 Macrocell CPLD
Switching Characteristics
The test load circuit and load values for the AC Electrical Characteristics are illustrated below.
V
CC
COMPONENT
VALUES
390Ω
S1
R1
R2
C1
390Ω
R1
R2
35 pF
V
IN
V
OUT
MEASUREMENT
S1
S2
C1
t
Open
Closed
Closed
Closed
PZH
t
Closed
Closed
PZL
t
P
S2
Note: For tPHZ and tPLZ C = 5 pF, and 3-state levels are
measured 0.5V from steady-state active level.
SP00477
V
= 3.3V, 25°C
DD
9.1
8.7
8.3
7.9
7.5
+3.0V
90%
10%
0V
t
PD_PAL
(ns)
t
R
t
F
1.5ns
1.5ns
SP00368
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
Input Pulses
Figure 7: Voltage Waveform
1
2
4
8
12
16
Table 6: tPD_PAL vs. Number of Outputs Switching
NUMBER OF OUTPUTS SWITCHING
(VCC = 3.3 V, T = 25°C)
SP00466A
Number Of
Outputs
1
2
4
8
12
16
Figure 6: tPD_PAL vs. Output Switching
Typical (ns) 7.9
8
8.1
8.3
8.4
8.6
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R
XCR3128: 128 Macrocell CPLD
Pin Function And Layout
XCR3128: 100-pin and 160-pin PQFP Pin Function Table
Function PQFP
100-pin 160-pin
Function PQFP
100-pin 160-pin
Function PQFP
100-pin 160-pin
Function PQFP
Pin #
Pin #
Pin #
Pin #
100-pin 160-pin
1
I/O-A5
I/O-A4
NC
NC
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VCC
I/O-E0/CLK1
I/O-E2
I/O-C0
GND
81
82
I/O-H7
NC
NC
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O-H0
I/O-H2
I/O-H3
NC
2
I/O-H8
3
I/O-A2
NC
I/O-D15
NC
83
I/O-H10
NC
4
I/O-A0
NC
I/O-E4
84
VCC
NC
5
VCC
NC
GND
NC
85
I/O-H12
NC
NC
6
I/O-B15 (TDI)
I/O-B13
I/O-B12
I/O-B10
I/O-B8
NC
I/O-E5
NC
86
I/O-H13
NC
NC
7
NC
I/O-E7
NC
87
I/O-H15
NC
NC
8
VCC
I/O-E8
I/O-D13
I/O-D12
I/O-D11
I/O-D10
I/O-D8
I/O-D7
I/O-D5
VCC
88
GND
I/O-F2
I/O-F3
I/O-F4
I/O-F5
I/O-F7
I/O-F8
I/O-F10
GND
I/O-H4
I/O-H5
I/O-H7
I/O-H8
I/O-H10
VCC
9
I/O-B15 (TDI)
I/O-B13
I/O-B12
I/O-B11
I/O-B10
I/O-B8
I/O-B7
I/O-B5
GND
I/O-E10
I/O-E12
I/O-E13
I/O-E15
VCC
89
IN0/CK0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
90
IN2/gtsn
I/O-B7
91
IN1
I/O-B5
92
IN3
GND
93
VCC
I/O-B4
I/O-F0
94
I/O-A15/CK3
I/O-H11
I/O-H12
I/O-H13
I/O-H15
GND
I/O-B2
I/O-F2
95
I/O-A13
I/O-B0
I/O-F4
I/O-D4
I/O-D3
I/O-D2
I/0-D0/CLK2
GND
96
I/O-A12
I/O-F11
I/O-F12
I/O-F13
I/O-F15 (TCK)
I/O-G0
I/O-G2
I/O-G3
I/O-G4
VCC
I/O-C15 (TMS)
I/O-C13
I/O-C12
VCC
I/O-F5
97
GND
I/O-B4
I/O-B3
I/O-B2
I/O-B0
I/O-C15 (TMS)
I/O-C13
I/O-C12
I/O-C11
VCC
I/O-F7
98
I/O-A10
I/O-F8
99
I/O-A8
IN0/CK0
IN2/gtsn
IN1
I/O-F10
GND
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
I/O-A7
I/O-C10
I/O-C8
I/O-C7
I/O-C5
I/O-C4
I/O-C2
I/O-C0
GND
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O-F12
I/O-F13
I/O-F15 (TCK)
I/O-G0
I/O-G2
I/O-G4
VCC
I/0-E0/CLK1
I/O-E2
I/O-E3
I/O-E4
GND
IN3
VCC
I/O-A0/CK3
I/O-A13
I/O-A12
I/O-A11
GND
I/O-G5
I/O-G7
I/O-G8
I/O-G10
I/O-G11
I/O-G12
I/O-G13
I/O-G15 (TDO)
GND
I/O-C10
I/O-C8
I/O-C7
I/O-C5
I/O-C4
I/O-C3
I/O-C2
NC
I/0-E5
I/0-E7
I/0-E8
I/0-E10
I/O-E11
I/0-E12
I/0-E13
NC
I/O-D15
I/O-D13
I/O-D12
I/O-D10
I/O-D8
I/O-D7
I/O-D5
VCC
I/O-G5
I/O-G7
I/O-G8
I/O-G10
I/O-G12
I/O-G13
I/O-G15 (TDO)
GND
I/O-A10
I/O-A8
I/O-A7
I/O-A5
I/O-A4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O-D4
I/O-D2
I/O-D0/CK2
GND
NC
I/O-H0
I/O-H2
I/O-H4
I/O-H5
NC
NC
NC
NC
I/O-E15
VCC
NC
I/O-A3
I/O-A2
I/O-A0
NC
NC
NC
I/O-F0
NC
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DS034 (v1.2) August 10, 2000
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R
XCR3128: 128 Macrocell CPLD
XCR3128: 84-pin PLCC, 100-Pin VQFP, and 128-pin TQFP Pin Function Table
Function
Function
Function
Function
Pin
#
Pin
#
Pin
#
Pin
#
PLCC VQFP TQFP
PLCC VQFP TQFP
PLCC VQFP
TQFP
I/O-E15
VCC
PLCC
VQFP
I/O-A8
I/O-A7
I/O-A5
I/O-A4
TQFP
NC
1
2
3
4
IN1
IN3
VCC
I/O-A2
I/O-A0
VCC
I/O-A3
I/O-A2
I/O-A0
NC
33
34
35
36
I/O-D15
I/O-D12
I/O-D10
I/O-D8
I/O-D5
VCC
NC
NC
65
66
67
68
I/O-G4
VCC
I/O-G4
VCC
97
98
-
-
-
-
NC
I/O-D4
I/O-D2
NC
I/O-G7
I/O-G8
I/O-G5
I/O-G7
I/O-F0
NC
99
NC
I/O-A15/ I/O-B15
CLK3 (TDI)
I/O-C0
100
I/O-H0
5
I/O-A13 I/O-B13
NC
37
I/O-D7
I/O-D0/
CLK2
GND
69
I/O-G10
I/O-G8
NC
101
-
-
I/O-H2
6
7
I/O-A12 I/O-B12
NC
38
39
VCC
GND
VCC
I/O-D15
I/O-D13
70
71
I/O-G12 I/O-G10
NC
102
103
-
-
-
-
I/O-H3
I/O-H4
GND
I/O-A10
I/O-A7
I/O-B10
I/O-B8
I/O-B7
VCC
I/O-D4
I/O-G15 I/O-G12
(TDO)
I/O-F2
8
9
I/O-B15
(TDI)
40
41
I/O-D2
I/O-E0/ I/O-D12
CLK1
72
73
GND
I/O-G13
I/O-F3
I/O-F4
104
105
-
-
-
-
I/O-H5
I/O-H7
I/O-B13
I/O-D0/C I/O-E2
LK2
I/O-D11
I/O-H2
I/O-G15
(TDO)
10
11
12
I/O-A5
I/O-A4
I/O-A2
I/O-B5
GND
I/O-B12
I/O-B11
I/O-B10
42
43
44
GND
VCC
I/O-E4
GND
I/O-D10
I/O-D8
I/O-D7
74
75
76
I/O-H4
I/O-H5
I/O-H7
GND
I/O-H0
I/O-H2
I/O-F5
I/O-F7
I/O-F8
106
107
108
-
-
-
-
-
-
I/O-H8
I/O-H10
VCC
I/O-B4
I/O-E0/C I/O-E5
LK1
13
14
VCC
I/O-B2
I/O-B0
I/O-B8
I/O-B7
45
46
I/O-E2
I/O-E4
I/O-E7
I/O-E8
I/O-D5
VCC
77
78
I/O-H10
VCC
I/O-H4
I/O-H5
I/O-F10
GND
109
110
-
-
-
-
I/O-H11
I/O-H12
I/O-B15
(TDI)
15
I/O-B12 I/O-C15
(TMS)
I/O-B5
47
GND
I/O-E10
I/O-D4
79
I/O-H12
I/O-H7
I/O-F11
111
-
-
I/O-H13
16
17
18
I/O-B10 I/O-C13
GND
I/O-B4
I/O-B3
48
49
50
I/O-E7
I/O-E8
I/O-E12
I/O-E13
I/O-D3
I/O-D2
80
81
82
I/O-H13
I/O-H8
I/O-F12
I/O-F13
112
113
114
-
-
-
-
-
-
I/O-H15
GND
I/O-B8
I/O-B7
I/O-C12
VCC
I/O-H15 I/O-H10
I/O-E10 I/O-E15 I/O-D0/C
LK2
GND
VCC
I/O-F15
(TCK)
IN0/CLK0
19
GND
I/O-C10
I/O-B2
I/O-B0
51
I/O-E12
VCC
GND
83
IN0/
CLK0
I/O-H12
I/O-G0
115
-
-
IN2/gtsn
20
21
I/O-B4
I/O-B2
I/O-C8
I/O-C7
52
53
I/O-E15
VCC
I/O-F0
I/O-F2
VCC
84
85
IN2/gtsn I/O-H13
I/O-G2
I/O-G3
116
117
-
-
-
-
IN1
IN3
I/O-C15
(TMS)
I/O-E0/
CLK1
-
I/O-H15
22
23
I/O-B0
I/O-C5
I/O-C4
I/O-C13
I/O-C12
54
55
I/O-F2
I/O-F4
I/O-F4
I/O-F5
I/O-E2
I/O-E3
86
87
-
-
GND
I/O-G4
VCC
118
119
-
-
-
-
VCC
I/O-C15
(TMS)
IN0/CLK0
I/O-A15/
CLK3
24
25
26
27
28
I/O-C13
I/O-C12
VCC
I/O-C2
I/O-C0
GND
I/O-C11
VCC
56
57
58
59
60
I/O-F5
I/O-F7
I/O-F7
I/O-F8
I/O-E4
GND
88
89
90
91
92
-
-
-
-
-
IN2/gtsn
IN1
I/O-G5
I/O-G7
I/O-G8
120
121
122
-
-
-
-
-
-
-
-
-
-
I/O-A13
I/O-A12
I/O-A11
GND
I/O-C10
I/O-C8
I/O-C7
I/O-F10 I/O-F10
GND GND
I/O-F12 I/O-F12
I/O-E5
I/O-E7
I/O-E8
IN3
I/O-C10 I/O-D15
VCC
I/O-G10 123
I/O-C7
I/O-D13
I/O-A15/C I/O-G11 124
LK3
I/O-A10
29
30
I/O-C5
I/O-C4
I/O-D12
I/O-D10
I/O-C5
I/O-C4
61
62
I/O-F13 I/O-F13 I/O-E10
I/O-F15 I/O-F15 I/O-E11
93
94
-
-
I/O-A13 I/O-G12 125
I/O-A12 I/O-G13 126
-
-
-
-
I/O-A8
I/O-A7
(TCK)
(TCK)
31
32
I/O-C2
GND
I/O-D8
I/O-D7
I/O-C3
I/O-C2
63
64
I/O-G0
I/O-G0
I/O-E12
I/O-E13
95
96
-
-
GND
I/O-G15 127
(TDO)
-
-
-
-
I/O-A5
I/O-A4
I/O-G2
I/O-G2
I/O-A10
GND
128
DS034 (v1.2) August 10, 2000
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R
XCR3128: 128 Macrocell CPLD
84-pin PLCC
128-pin TQFP
128
103
11
1
75
1
102
12
32
74
54
TQFP
PLCC
38
65
33
53
SP00467A
39
64
SP00469B
100-pin PQFP
160-pin PQFP
100
81
160
121
80
1
1
120
81
PQFP
PQFP
30
51
40
31
50
41
80
SP00468A
SP00470B
100-pin VQFP
100
76
75
1
VQFP
25
51
26
50
SP00485A
17
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DS034 (v1.2) August 10, 2000
R
XCR3128: 128 Macrocell CPLD
Ordering Information
Example: XCR3128 -10 PC 84 C
Temperature Range
Number of Pins
Package Type
Device Type
Speed Options
Temperature Range
Speed Options
C = Commercial, TA = 0°C to +70°C
I = Industrial, TA = –40°C to +85°C
-15: 15 ns pin-to-pin delay
-12: 12 ns pin-to-pin delay
-10: 10 ns pin-to-pin delay
Packaging Options
PC84: 84-pin PLCC
PQ100: 100-pin PQFP
VQ100: 100-pin VQFP
TQ128: 128-pin TQFP
PQ160: 160-pin PQFP
Component Availability
Pins
84
Plastic PLCC
PC84
C, I
100
128
160
Type
Plastic PQFP
Plastic VQFP
Plastic TQFP
Plastic PQFP
Code
PQ100
C, I
VQ100
C, I
TQ128
C, I
PQ160
C, I
XCR3128
-15
-12
-10
C, I
C, I
C, I
C, I
C, I
C
C
C
C
C
Revision Table
Date
Version #
Revision
8/4/99
2/10/00
8/10/00
1.0
1.1
1.2
Initial Xilinx release
Converted to Xilinx format and updated.
Updated pinout tables.
DS034 (v1.2) August 10, 2000
www.xilinx.com
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