XCV3200E-7CGG1156I [XILINX]
Field Programmable Gate Array, 16224 CLBs, 876096 Gates, 400MHz, CMOS, CBGA1156, 1 MM PITCH, CERAMIC, BGA-1156;
| 型号： | XCV3200E-7CGG1156I |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 16224 CLBs, 876096 Gates, 400MHz, CMOS, CBGA1156, 1 MM PITCH, CERAMIC, BGA-1156 栅 |
| 文件： | 总224页 (文件大小：1494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
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Virtex™-E 1.8 V
Field Programmable Gate Arrays
0
0
DS022-1 (v2.0) April 2, 2001
Preliminary Product Specification
Features
•
Fast, High-Density 1.8 V FPGA Family
•
High-Performance Built-In Clock Management Circuitry
-
-
-
-
Densities from 58 Kb to 4 Mb system gates
-
-
Eight fully digital Delay-Locked Loops (DLLs)
130 MHz internal performance (four LUT levels)
Designed for low-power operation
Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications
-
-
Clock Multiply and Divide
PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard
•
•
Highly Flexible SelectI/O+™ Technology
-
-
Supports 20 high-performance interface standards
•
Flexible Architecture Balances Speed and Density
Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/s
-
-
-
-
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Differential Signalling Support
Cascade chain for wide-input function
-
-
-
-
LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
Differential I/O signals can be input, output, or I/O
Compatible with standard differential devices
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
-
-
-
Internal 3-state bussing
LVPECL and LVDS clock inputs for 300+ MHz
clocks
IEEE 1149.1 boundary-scan logic
Die-temperature sensor diode
•
•
Proprietary High-Performance SelectLink™
Technology
•
Supported by Xilinx Foundation™ and Alliance Series™
Development Systems
-
-
Double Data Rate (DDR) to Virtex-E link
Web-based HDL generation methodology
-
-
Further compile time reduction of 50%
Internet Team Design (ITD) tool ideal for
million-plus gate density designs
Sophisticated SelectRAM+™ Memory Hierarchy
-
-
-
-
1 Mb of internal configurable distributed RAM
Up to 832 Kb of synchronous internal block RAM
True Dual-Port™ BlockRAM capability
-
Wide selection of PC and workstation platforms
•
•
SRAM-Based In-System Configuration
Unlimited re-programmability
Advanced Packaging Options
-
Memory bandwidth up to 1.66 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
-
-
-
-
0.8 mm Chip-scale
1.0 mm BGA
1.27 mm BGA
HQ/PQ
-
Designed for high-performance Interfaces to
External Memories
-
-
-
200 MHz ZBT* SRAMs
200 Mb/s DDR SDRAMs
Supported by free Synthesizable reference design
•
•
0.18 m 6-Layer Metal Process
100% Factory Tested
* ZBT is a trademark of Integrated Device Technology, Inc.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS022-1 (v2.0) April 2, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 1: Virtex-E Field-Programmable Gate Array Family Members
System
Gates
Logic
Gates
CLB
Array
Logic
Cells
Differential
I/O Pairs
User
I/O
BlockRAM Distributed
Device
Bits
RAM Bits
XCV50E
71,693
128,236
20,736
32,400
16 x 24
20 x 30
28 x 42
32 x 48
40 x 60
48 x 72
64 x 96
72 x 108
80 x 120
92 x 138
104 x 156
1,728
2,700
83
176
196
284
316
404
512
660
724
804
804
804
65,536
24,576
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
83
81,920
38,400
306,393
63,504
5,292
119
137
183
247
281
344
344
344
344
114,688
131,072
163,840
294,912
393,216
589,824
655,360
753,664
851,968
75,264
411,955
82,944
6,912
98,304
569,952
129,600
186,624
331,776
419,904
518,400
685,584
876,096
10,800
15,552
27,648
34,992
43,200
57,132
73,008
153,600
221,184
393,216
497,664
614,400
812,544
1,038,336
985,882
1,569,178
2,188,742
2,541,952
3,263,755
4,074,387
The Virtex-E family is not bitstream-compatible with the Vir-
tex family, but Virtex designs can be compiled into equiva-
lent Virtex-E devices.
Virtex-E Compared to Virtex Devices
The Virtex-E family offers up to 43,200 logic cells in devices
up to 30% faster than the Virtex family.
The same device in the same package for the Virtex-E and
Virtex families are pin-compatible with some minor excep-
tions. See the data sheet pinout section for details.
I/O performance is increased to 622 Mb/s using Source
Synchronous data transmission architectures and synchro-
nous system performance up to 240 MHz using sin-
gled-ended SelectI/O technology. Additional I/O standards
are supported, notably LVPECL, LVDS, and BLVDS, which
use two pins per signal. Almost all signal pins can be used
for these new standards.
General Description
The Virtex-E FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 6-layer metal 0.18 m CMOS process. These
advances make Virtex-E FPGAs powerful and flexible alter-
natives to mask-programmed gate arrays. The Virtex-E fam-
ily includes the nine members in Table 1.
Virtex-E devices have up to 640 Kb of faster (250 MHz)
block SelectRAM, but the individual RAMs are the same
size and structure as in the Virtex family. They also have
eight DLLs instead of the four in Virtex devices. Each indi-
vidual DLL is slightly improved with easier clock mirroring
and 4x frequency multiplication.
Building on experience gained from Virtex FPGAs, the
Virtex-E family is an evolutionary step forward in program-
mable logic design. Combining a wide variety of program-
mable system features, a rich hierarchy of fast, flexible
interconnect resources, and advanced process technology,
the Virtex-E family delivers a high-speed and high-capacity
programmable logic solution that enhances design flexibility
while reducing time-to-market.
VCCINT, the supply voltage for the internal logic and mem-
ory, is 1.8 V, instead of 2.5 V for Virtex devices. Advanced
processing and 0.18 m design rules have resulted in
smaller dice, faster speed, and lower power consumption.
I/O pins are 3 V tolerant, and can be 5 V tolerant with an
external 100 resistor. PCI 5 V is not supported. With the
addition of appropriate external resistors, any pin can toler-
ate any voltage desired.
Banking rules are different. With Virtex devices, all input
buffers are powered by VCCINT. With Virtex-E devices, the
LVTTL, LVCMOS2, and PCI input buffers are powered by
Virtex-E Architecture
Virtex-E devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) sur-
rounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing
the I/O supply voltage VCCO
.
Module 1 of 4
2
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DS022-1 (v2.0) April 2, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
resources. The abundance of routing resources permits the
Virtex-E family to accommodate even the largest and most
complex designs.
achieve over 311 MHz. Table 2 shows performance data for
representative circuits, using worst-case timing parameters.
Table 2: Performance for Common Circuit Functions
Virtex-E FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. Con-
figuration data can be read from an external SPROM (mas-
ter serial mode), or can be written into the FPGA
(SelectMAP™, slave serial, and JTAG modes).
Function
Register-to-Register
Adder
Bits
Virtex-E (-7)
16
64
4.3 ns
6.3 ns
The standard Xilinx Foundation Series™ and Alliance
Series™ Development systems deliver complete design
support for Virtex-E, covering every aspect from behavioral
and schematic entry, through simulation, automatic design
translation and implementation, to the creation and down-
loading of a configuration bit stream.
Pipelined Multiplier
Address Decoder
8 x 8
4.4 ns
5.1 ns
16 x 16
16
64
3.8 ns
5.5 ns
16:1 Multiplexer
Parity Tree
4.6 ns
Higher Performance
9
3.5 ns
4.3 ns
5.9 ns
Virtex-E devices provide better performance than previous
generations of FPGAs. Designs can achieve synchronous
system clock rates up to 240 MHz including I/O or 622 Mb/s
using Source Synchronous data transmission architech-
tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica-
tions, and interfaces can be implemented that operate at
33 MHz or 66 MHz.
18
36
Chip-to-Chip
HSTL Class IV
LVTTL,16mA, fast slew
LVDS
While performance is design-dependent, many designs
operate internally at speeds in excess of 133 MHz and can
Virtex-E Device/Package Combinations and Maximum I/O
Table 3: Virtex-E Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)
CS144
PQ240
HQ240
BG352
BG432
BG560
FG256
FG456
FG676
FG680
FG860
FG900
FG1156
CG1156
94
94
94
158
158
158
158
158
158
158
404
196
176
260
260
316
316
404
316
404
404
404
176
176
284
176
312
404
444
512
512
660
660
660
512
660
700
724
512
660
512
804
804
804
DS022-1 (v2.0) April 2, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
3
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Virtex-E Ordering Information
Example: XCV300E-6PQ240C
Device Type
Temperature Range
C = Commercial (Tj = 0 C to +85 C)
I = Industrial (Tj = -40 C to +100 C)
Speed Grade
(-6, -7, -8)
Number of Pins
Package Type
BG = Ball Grid Array
FG = Fine Pitch Ball Grid Array
HQ = High Heat Dissipation
DS022_043_072000
Figure 1: Ordering Information
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
12/7/99
1/10/00
Initial Xilinx release.
1.1
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
1/28/00
1.2
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, TBYP values, buffered Hex Line info, p. 8, I/O Timing
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
2/29/00
5/23/00
7/10/00
1.3
1.4
1.5
Updated pinout tables, VCC page 20, and corrected Figure 20.
Correction to table on p. 22.
•
Numerous minor edits.
•
•
•
•
•
•
Data sheet upgraded to Preliminary.
Preview -8 numbers added to Virtex-E Electrical Characteristics tables.
Reformatted entire document to follow new style guidelines.
Changed speed grade values in tables on pages 35-37.
Min values added to Virtex-E Electrical Characteristics tables.
8/1/00
1.6
1.7
9/20/00
XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).
•
•
Corrected user I/O count for XCV100E device in Table 1 (Module 1).
Changed several pins to “No Connect in the XCV100E“ and removed duplicate VCCINT
pins in Table ~ (Module 4).
•
•
•
Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4).
Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4).
Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“.
Module 1 of 4
4
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1-800-255-7778
DS022-1 (v2.0) April 2, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Date
Version
Revision
•
Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.
11/20/00
1.8
•
•
•
Updated minimums in Table 13 and added notes to Table 14.
Added to note 2 to Absolute Maximum Ratings.
Changed speed grade -8 numbers for TSHCKO32, TREG, TBCCS, and TICKOF
.
•
Changed all minimum hold times to –0.4 under Global Clock Set-Up and Hold for
LVTTL Standard, with DLL.
•
Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters.
Changed GCLK0 to BA22 for FG860 package in Table 46.
Revised footnote for Table 14.
•
•
•
2/12/01
1.9
2.0
Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.
•
•
Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.
Revised Table 62 to include pinout information for the XCV400E and XCV600E devices
in the BG560 package.
•
•
•
Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.
Updated numerous values in Virtex-E Switching Characteristics tables.
4/2/01
Converted data sheet to modularized format. See the Virtex-E Data Sheet section.
Virtex-E Data Sheet
The Virtex-E Data Sheet contains the following modules:
•
DS022-1, Virtex-E 1.8V FPGAs:
Introduction and Ordering Information (Module 1)
•
•
DS022-3, Virtex-E 1.8V FPGAs:
DC and Switching Characteristics (Module 3)
•
DS022-2, Virtex-E 1.8V FPGAs:
DS022-4, Virtex-E 1.8V FPGAs:
Functional Description (Module 2)
Pinout Tables (Module 4)
DS022-1 (v2.0) April 2, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
5
0
R
Virtex™-E 1.8 V
Field Programmable Gate Arrays
0
0
DS022-2 (v2.2) July 23, 2001
Preliminary Product Specification
Architectural Description
Virtex-E Array
The Virtex-E user-programmable gate array, shown in
Figure 1, comprises two major configurable elements: con-
figurable logic blocks (CLBs) and input/output blocks (IOBs).
Values stored in static memory cells control the configurable
logic elements and interconnect resources. These values
load into the memory cells on power-up, and can reload if
necessary to change the function of the device.
•
CLBs provide the functional elements for constructing
logic
Input/Output Block
•
IOBs provide the interface between the package pins
and the CLBs
The Virtex-E IOB, Figure 2, features SelectI/O+ inputs and
outputs that support a wide variety of I/O signalling stan-
dards, see Table 1.
CLBs interconnect through a general routing matrix (GRM).
The GRM comprises an array of routing switches located at
the intersections of horizontal and vertical routing channels.
Each CLB nests into a VersaBlock™ that also provides local
routing resources to connect the CLB to the GRM.
Q
D
CE
T
TCE
Weak
Keeper
SR
PAD
DLLDLL
DLLDLL
O
Q
D
CE
OCE
OBUFT
VersaRing
SR
I
IQ
Programmable
Delay
Q
D
CE
IBUF
Vref
SR
SR
CLK
ICE
ds022_02_091300
Figure 2: Virtex-E Input/Output Block (IOB)
The three IOB storage elements function either as
edge-triggered D-type flip-flops or as level-sensitive latches.
Each IOB has a clock signal (CLK) shared by the three
flip-flops and independent clock enable signals for each
flip-flop.
VersaRing
DLLDLL
DLLDLL
ds022_01_121099
Figure 1: Virtex-E Architecture Overview
The VersaRing™ I/O interface provides additional routing
resources around the periphery of the device. This routing
improves I/O routability and facilitates pin locking.
The Virtex-E architecture also includes the following circuits
that connect to the GRM.
•
•
Dedicated block memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
•
3-State buffers (BUFTs) associated with each CLB that
drive dedicated segmentable horizontal routing
resources
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS022-2 (v2.2) July 23, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
1
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Input Path
Table 1: Supported I/O Standards
The Virtex-E IOB input path routes the input signal directly
to internal logic and/ or through an optional input flip-flop.
Board
Output Input Input Termination
VCCO VREF Voltage (VTT)
I/O
An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Standard
VCCO
3.3
2.5
1.8
3.3
2.5
N/A
N/A
1.5
1.5
3.3
3.3
3.3
3.3
2.5
3.3
LVTTL
LVCMOS2
LVCMOS18
SSTL3 I & II
SSTL2 I & II
GTL
3.3
2.5
N/A
N/A
N/A
1.50
1.25
0.80
1.0
N/A
N/A
N/A
1.50
1.25
1.20
1.50
0.75
1.50
1.50
N/A
N/A
N/A
N/A
N/A
Each input buffer can be configured to conform to any of the
low-voltage signalling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, VREF. The need to supply VREF imposes
constraints on which standards can be used in close prox-
imity to each other. <Link>See “I/O Banking” on page 2.
1.8
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3
GTL+
There are optional pull-up and pull-down resistors at each
input for use after configuration. Their value is in the range
50 – 100 k .
HSTL I
0.75
0.90
1.50
1.32
N/A
N/A
N/A
N/A
HSTL III & IV
CTT
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
AGP-2X
PCI33_3
PCI66_3
BLVDS & LVDS
LVPECL
3.3
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable.
N/A
N/A
Each output driver can be individually programmed for a
wide range of low-voltage signalling standards. Each output
buffer can source up to 24 mA and sink up to 48 mA. Drive
strength and slew rate controls minimize bus transients.
In addition to the CLK and CE control signals, the three
flip-flops share a Set/Reset (SR). For each flip-flop, this sig-
nal can be independently configured as a synchronous Set,
a synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
In most signalling standards, the output High voltage
depends on an externally supplied VCCO voltage. The need
to supply VCCO imposes constraints on which standards
can be used in close proximity to each other. <Link>See
“I/O Banking” on page 2.
The output buffer and all of the IOB control signals have
independent polarity controls.
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. When
PCI 3.3 V compliance is required, a conventional clamp
diode is connected to the output supply voltage, VCCO.
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way eliminates bus chatter.
Optional pull-up, pull-down and weak-keeper circuits are
attached to each pad. Prior to configuration all outputs not
involved in configuration are forced into their high-imped-
ance state. The pull-down resistors and the weak-keeper
circuits are inactive, but I/Os can optionally be pulled up.
Since the weak-keeper circuit uses the IOB input buffer to
monitor the input level, an appropriate VREF voltage must be
provided if the signalling standard requires one. The provi-
sion of this voltage must comply with the I/O banking rules.
The activation of pull-up resistors prior to configuration is
controlled on a global basis by the configuration mode pins.
If the pull-up resistors are not activated, all the pins are in a
high-impedance state. Consequently, external pull-up or
pull-down resistors must be provided on pins required to be
at a well-defined logic level prior to configuration.
I/O Banking
Some of the I/O standards described above require VCCO
and/or VREF voltages. These voltages are externally sup-
plied and connected to device pins that serve groups of
IOBs, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
All Virtex-E IOBs support IEEE 1149.1-compatible bound-
ary scan testing.
Module 2 of 4
2
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DS022-2 (v2.2) July 23, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Eight I/O banks result from separating each edge of the
FPGA into two banks, as shown in Figure 3. Each bank has
multiple VCCO pins, all of which must be connected to the
same voltage. This voltage is determined by the output
standards in use.
In Virtex-E, input buffers with LVTTL, LVCMOS2,
LVCMOS18, PCI33_3, PCI66_3 standards are supplied by
VCCO rather than VCCINT. For these standards, only input
and output buffers that have the same VCCO can be mixed
together.
The VCCO and VREF pins for each bank appear in the device
pin-out tables and diagrams. The diagrams also show the
bank affiliation of each I/O.
Bank 0
Bank 1
GCLK3 GCLK2
Within a given package, the number of VREF and VCCO pins
can vary depending on the size of device. In larger devices,
more I/O pins convert to VREF pins. Since these are always
a super set of the VREF pins used for smaller devices, it is
possible to design a PCB that permits migration to a larger
device if necessary. All the VREF pins for the largest device
anticipated must be connected to the VREF voltage, and not
used for I/O.
VirtexE
Device
GCLK1 GCLK0
Bank 5
Bank 4
In smaller devices, some VCCO pins used in larger devices
do not connect within the package. These unconnected pins
can be left unconnected externally, or can be connected to
the VCCO voltage to permit migration to a larger device if
necessary.
ds022_03_121799
Figure 3: Virtex-E I/O Banks
Within a bank, output standards can be mixed only if they
use the same VCCO. Compatible standards are shown in
Table 2. GTL and GTL+ appear under all voltages because
Configurable Logic Blocks
The basic building block of the Virtex-E CLB is the logic cell
(LC). An LC includes a 4-input function generator, carry
logic, and a storage element. The output from the function
generator in each LC drives both the CLB output and the D
input of the flip-flop. Each Virtex-E CLB contains four LCs,
organized in two similar slices, as shown in Figure 4.
Figure 5 shows a more detailed view of a single slice.
their open-drain outputs do not depend on VCCO
.
Table 2: Compatible Output Standards
VCCO Compatible Standards
3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,
GTL+, LVPECL
In addition to the four basic LCs, the Virtex-E CLB contains
logic that combines function generators to provide functions
of five or six inputs. Consequently, when estimating the
number of system gates provided by a given device, each
CLB counts as 4.5 LCs.
2.5 V
SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+,
BLVDS, LVDS
1.8 V
1.5 V
LVCMOS18, GTL, GTL+
HSTL I, HSTL III, HSTL IV, GTL, GTL+
Look-Up Tables
Some input standards require a user-supplied threshold
voltage, VREF. In this case, certain user-I/O pins are auto-
matically configured as inputs for the VREF voltage. Approx-
imately one in six of the I/O pins in the bank assume this
role.
Virtex-E function generators are implemented as 4-input
look-up tables (LUTs). In addition to operating as a function
generator, each LUT can provide a 16 x 1-bit synchronous
RAM. Furthermore, the two LUTs within a slice can be com-
bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,
or a 16 x 1-bit dual-port synchronous RAM.
The VREF pins within a bank are interconnected internally
and consequently only one VREF voltage can be used within
each bank. All VREF pins in the bank, however, must be con-
nected to the external voltage source for correct operation.
The Virtex-E LUT can also provide a 16-bit shift register that
is ideal for capturing high-speed or burst-mode data. This
mode can also be used to store data in applications such as
Digital Signal Processing.
Within a bank, inputs that require VREF can be mixed with
those that do not. However, only one VREF voltage can be
used within a bank.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
COUT
COUT
YB
Y
YB
Y
G4
G4
G3
G2
SP
SP
Q
G3
G2
G1
Carry &
Control
Carry &
Control
LUT
LUT
D
YQ
D
Q
YQ
CE
CE
G1
BY
F4
RC
RC
BY
XB
X
XB
X
F4
F3
F2
F1
SP
SP
F3
F2
LUT
LUT
Carry &
Control
Carry &
Control
D
Q
D
Q
XQ
XQ
CE
CE
F1
RC
Slice 0
RC
Slice 1
BX
BX
CIN
CIN
ds022_04_121799
Figure 4: 2-Slice Virtex-E CLB
COUT
CY
YB
Y
G4
I3
O
G3
G2
G1
I2
I1
I0
LUT
INIT
D Q
CE
YQ
DI
WE
0
1
REV
BY
XB
F5IN
F6
CY
F5
X
F5
BY DG
CK WSO
WE
BX
WSH
A4
DI
INIT
D Q
CE
XQ
BX
DI
WE
I3
I2
I1
I0
F4
F3
F2
F1
REV
O
LUT
0
1
SR
CLK
CE
ds022_05_092000
CIN
Figure 5: Detailed View of Virtex-E Slice
the function generators within the slice or directly from slice
inputs, bypassing the function generators.
Storage Elements
The storage elements in the Virtex-E slice can be config-
ured either as edge-triggered D-type flip-flops or as
level-sensitive latches. The D inputs can be driven either by
In addition to Clock and Clock Enable signals, each Slice
has synchronous set and reset signals (SR and BY). SR
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Virtex™-E 1.8 V Field Programmable Gate Arrays
forces a storage element into the initialization state speci-
fied for it in the configuration. BY forces it into the opposite
state. Alternatively, these signals can be configured to oper-
ate asynchronously. All of the control signals are indepen-
dently invertible, and are shared by the two flip-flops within
the slice.
Table 3: CLB/Block RAM Column Locations
XCV
Device
/Col.
0 12 24 36 48 60 72 84 96 108 120 138 156
Columns 0, 6, 18, & 24
50E
100E
200E
300E
400E
600E
1000E
1600E
2000E
2600E
3200E
Columns 0, 12, 18, & 30
Additional Logic
Columns 0, 12, 30, & 42
The F5 multiplexer in each slice combines the function gen-
erator outputs. This combination provides either a function
generator that can implement any 5-input function, a 4:1
multiplexer, or selected functions of up to nine inputs.
Similarly, the F6 multiplexer combines the outputs of all four
function generators in the CLB by selecting one of the
F5-multiplexer outputs. This permits the implementation of
any 6-input function, an 8:1 multiplexer, or selected func-
tions of up to 19 inputs.
Each CLB has four direct feedthrough paths, two per slice.
These paths provide extra data input lines or additional local
routing that does not consume logic resources.
Table 4 shows the amount of block SelectRAM memory that
is available in each Virtex-E device.
Arithmetic Logic
Dedicated carry logic provides fast arithmetic carry capabil-
ity for high-speed arithmetic functions. The Virtex-E CLB
supports two separate carry chains, one per Slice. The
height of the carry chains is two bits per CLB.
Table 4: Virtex-E Block SelectRAM Amounts
Virtex-E Device # of Blocks Block SelectRAM Bits
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
16
20
65,536
81,920
The arithmetic logic includes an XOR gate that allows a
2-bit full adder to be implemented within a slice. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementation. The dedicated carry path can also be used
to cascade function generators for implementing wide logic
functions.
28
114,688
131,072
163,840
294,912
393,216
589,824
655,360
753,664
851,968
32
40
BUFTs
72
Each Virtex-E CLB contains two 3-state drivers (BUFTs)
that can drive on-chip busses. <Link>See “Dedicated Rout-
ing” on page 7. Each Virtex-E BUFT has an independent
3-state control pin and an independent input pin.
96
144
160
184
208
Block SelectRAM
Virtex-E FPGAs incorporate large block SelectRAM memo-
ries. These complement the Distributed SelectRAM memo-
ries that provide shallow RAM structures implemented in
CLBs.
As illustrated in Figure 6, each block SelectRAM cell is a
fully synchronous dual-ported (True Dual Port ) 4096-bit
RAM with independent control signals for each port. The
data widths of the two ports can be configured indepen-
dently, providing built-in bus-width conversion.
Block SelectRAM memory blocks are organized in columns,
starting at the left (column 0) and right outside edges and
inserted every 12 CLB columns (see notes for smaller
devices). Each memory block is four CLBs high, and each
memory column extends the full height of the chip, immedi-
ately adjacent (to the right, except for column 0) of the CLB
column locations indicated in Table 3.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
RAMB4_S#_S#
To Adjacent
GRM
WEA
ENA
DOA[#:0]
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]
To
Adjacent
GRM
To Adjacent
GRM
GRM
To Adjacent
GRM
WEB
ENB
Direct
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
DOB[#:0]
Direct Connection
To Adjacent
CLB
Connection
To Adjacent
CLB
CLB
XCVE_ds_007
Figure 7: Virtex-E Local Routing
General Purpose Routing
ds022_06_121699
Figure 6: Dual-Port Block SelectRAM
Table 5 shows the depth and width aspect ratios for the
block SelectRAM. The Virtex-E block SelectRAM also
includes dedicated routing to provide an efficient interface
with both CLBs and other block SelectRAMs.
Most Virtex-E signals are routed on the general purpose
routing, and consequently, the majority of interconnect
resources are associated with this level of the routing hier-
archy. General-purpose routing resources are located in
horizontal and vertical routing channels associated with the
CLB rows and columns and are as follows:
Table 5: Block SelectRAM Port Aspect Ratios
•
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.
Width
Depth
4096
2048
1024
512
ADDR Bus
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
Data Bus
DATA<0>
1
2
DATA<1:0>
DATA<3:0>
DATA<7:0>
DATA<15:0>
4
•
•
24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.
8
72 buffered Hex lines route GRM signals to another
GRMs six-blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
are driven only at their endpoints. Hex-line signals can
be accessed either at the endpoints or at the midpoint
(three blocks from the source). One third of the Hex
lines are bidirectional, while the remaining ones are
uni-directional.
16
256
Programmable Routing Matrix
It is the longest delay path that limits the speed of any
worst-case design. Consequently, the Virtex-E routing
architecture and its place-and-route software were defined
in a joint optimization process. This joint optimization mini-
mizes long-path delays, and consequently, yields the best
system performance.
•
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
I/O Routing
Virtex-E devices have additional routing resources around
their periphery that form an interface between the CLB array
and the IOBs. This additional routing, called the
VersaRing, facilitates pin-swapping and pin-locking, such
that logic redesigns can adapt to existing PCB layouts.
Time-to-market is reduced, since PCBs and other system
components can be manufactured while the logic design is
still in progress.
Local Routing
The VersaBlock provides local routing resources (see
Figure 7), providing three types of connections:
•
•
Interconnections among the LUTs, flip-flops, and GRM
Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay
•
Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Dedicated Routing
Clock Routing
Clock Routing resources distribute clocks and other signals
with very high fanout throughout the device. Virtex-E
devices include two tiers of clock routing resources referred
to as global and local clock routing resources.
Some classes of signal require dedicated routing resources to
maximize performance. In the Virtex-E architecture, dedi-
cated routing resources are provided for two classes of signal.
•
Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row, as shown in Figure 8.
•
The global routing resources are four dedicated global
nets with dedicated input pins that are designed to
distribute high-fanout clock signals with minimal skew.
Each global clock net can drive all CLB, IOB, and block
RAM clock pins. The global nets can be driven only by
global buffers. There are four global buffers, one for
each global net.
•
•
Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB.Global Clock Distribution
Network
DLL Location
•
The local clock routing resources consist of 24
backbone lines, 12 across the top of the chip and 12
across bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These local resources are
more flexible than the global resources since they are
not restricted to routing only to clock pins.
Tri-State
Lines
CLB
CLB
CLB
CLB
buft_c.eps
Figure 8: BUFT Connections to Dedicated Horizontal Bus LInes
Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
global nets that in turn drive any clock pin.
Global Clock Distribution
Virtex-E provides high-speed, low-skew clock distribution
through the global routing resources described above. A
typical clock distribution net is shown in Figure 9.
Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
selected either from these pads or from signals in the gen-
eral purpose routing.
GCLKPAD3
GCLKBUF3
GCLKPAD2
GCLKBUF2
Global Clock Column
Global Clock Rows
Digital Delay-Locked Loops
There are eight DLLs (Delay-Locked Loops) per device,
with four located at the top and four at the bottom,
Figure 10. The DLLs can be used to eliminate skew
between the clock input pad and the internal clock input pins
throughout the device. Each DLL can drive two global clock
networks.The DLL monitors the input clock and the distrib-
uted clock, and automatically adjusts a clock delay element.
Additional delay is introduced such that clock edges arrive
at internal flip-flops synchronized with clock edges arriving
at the input.
In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
DLL provides four quadrature phases of the source clock,
and can double the clock or divide the clock by 1.5, 2, 2.5, 3,
4, 5, 8, or 16.
GCLKBUF1
GCLKPAD1
GCLKBUF0
GCLKPAD0
XCVE_009
Figure 9: Global Clock Distribution Network
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Virtex™-E 1.8 V Field Programmable Gate Arrays
The DLL also operates as a clock mirror. By driving the out-
put from a DLL off-chip and then back on again, the DLL can
be used to de-skew a board level clock among multiple
devices.
also supports two internal scan chains and configura-
tion/readback of the device.
The JTAG input pins (TDI, TMS, TCK) do not have a VCCO
requirement and operate with either 2.5 V or 3.3 V input sig-
nalling levels. The output pin (TDO) is sourced from the
VCCO in bank 2, and for proper operation of LVTTL 3.3 V lev-
els, the bank should be supplied with 3.3 V.
To guarantee that the system clock is operating correctly
prior to the FPGA starting up after configuration, the DLL
can delay the completion of the configuration process until
after it has achieved lock. For more information about DLL
functionality, see the Design Consideration section of the
data sheet.
Boundary-scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including un-bonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
the bidirectional test capability after configuration facilitates
the testing of external interconnections.
DLLDLL
DLLDLL
Table 6 lists the boundary-scan instructions supported in
Virtex-E FPGAs. Internal signals can be captured during
EXTEST by connecting them to un-bonded or unused IOBs.
They can also be connected to the unused outputs of IOBs
defined as unidirectional input pins.
Primary DLLs
Before the device is configured, all instructions except
USER1 and USER2 are available. After configuration, all
instructions are available. During configuration, it is recom-
mended that those operations using the boundary-scan
register (SAMPLE/PRELOAD, INTEST, EXTEST) not be
performed.
DLLDLL
DLLDLL
XCVE_0010
Figure 10: DLL Locations
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
FPGA, and also to read back the configuration data.
Boundary Scan
Virtex-E devices support all the mandatory boundary-scan
instructions specified in the IEEE standard 1149.1. A Test
Access Port (TAP) and registers are provided that imple-
ment the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,
IDCODE, USERCODE, and HIGHZ instructions. The TAP
Figure 11 is a diagram of the Virtex-E Series boundary scan
logic. It includes three bits of Data Register per IOB, the
IEEE 1149.1 Test Access Port controller, and the Instruction
Register with decodes.
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DATA IN
IOB.T
0
1
0
sd
1
D
Q
D
Q
LE
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
sd
1
0
D
Q
D
Q
LE
1
0
IOB.I
1
sd
D
Q
D
Q
0
LE
1
0
IOB.Q
IOB.T
BYPASS
REGISTER
0
1
M
U
X
TDO
1
sd
INSTRUCTION REGISTER
TDI
D
Q
D
Q
0
LE
1
sd
D
Q
D
Q
0
LE
1
0
IOB.I
DATAOUT
UPDATE
EXTEST
SHIFT/
CAPTURE
CLOCK DATA
REGISTER
X9016
Figure 11: Virtex-E Family Boundary Scan Logic
Table 6: Boundary Scan Instructions (Continued)
Instruction Set
The Virtex-E Series boundary scan instruction set also
includes instructions to configure the device and read back
configuration data (CFG_IN, CFG_OUT, and JSTART). The
complete instruction set is coded as shown in Table 6..
Boundary-Scan
Command
Binary
Code(4:0)
Description
Access the
configuration bus for
write operations.
CFG_IN
00101
Table 6: Boundary Scan Instructions
INTEST
00111
01000
01001
01010
Enables boundary-scan
INTEST operation
Boundary-Scan
Command
Binary
Code(4:0)
Description
USERCODE
IDCODE
HIGHZ
Enables shifting out
USER code
EXTEST
00000
00001
Enables boundary-scan
EXTEST operation
Enables shifting out of
ID Code
SAMPLE/
PRELOAD
Enables boundary-scan
SAMPLE/PRELOAD
operation
3-states output pins
while enabling the
Bypass Register
USER1
00010
00011
00100
Access user-defined
register 1
JSTART
01100
11111
Clock the start-up
sequence when
StartupClk is TCK
USER2
Access user-defined
register 2
CFG_OUT
Access the
configuration bus for
read operations.
BYPASS
Enables BYPASS
RESERVED
All other
codes
Xilinx reserved
instructions
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Virtex™-E 1.8 V Field Programmable Gate Arrays
BSDL (Boundary Scan Description Language) files for Vir-
tex-E Series devices are available on the Xilinx web site in
the File Download area.
Data Registers
The primary data register is the boundary scan register. For
each IOB pin in the FPGA, bonded or not, it includes three
bits for In, Out, and 3-State Control. Non-IOB pins have
appropriate partial bit population if input-only or output-only.
Each EXTEST CAPTURED-OR state captures all In, Out,
and 3-state pins.
Identification Registers
The IDCODE register is supported. By using the IDCODE,
the device connected to the JTAG port can be determined.
The IDCODE register has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
where
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
v = the die version number
The FPGA supports up to two additional internal scan
chains that can be specified using the BSCAN macro. The
macro provides two user pins (SEL1 and SEL2) which are
decodes of the USER1 and USER2 instructions respec-
tively. For these instructions, two corresponding pins (T
DO1 and TDO2) allow user scan data to be shifted out of
TDO.
f = the family code (05 for Virtex-E family)
a = the number of CLB rows (ranges from 16 for
XCV50E to 104 for XCV3200E)
c = the company code (49h for Xilinx)
The USERCODE register is supported. By using the USER-
CODE, a user-programmable identification code can be
loaded and shifted out for examination. The identification
code (see Table 7) is embedded in the bitstream during bit-
stream generation and is valid only after configuration.
Likewise, there are individual clock pins (DRCK1 and
DRCK2) for each user register. There is a common input pin
(TDI) and shared output pins that represent the state of the
TAP controller (RESET, SHIFT, and UPDATE).
Bit Sequence
Table 7: IDCODEs Assigned to Virtex-E FPGAs
The order within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes
all three bits.
FPGA
IDCODE
XCV50E
v0A10093h
v0A14093h
v0A1C093h
v0A20093h
v0A28093h
v0A30093h
v0A40093h
v0A48093h
v0A50093h
v0A5C093h
v0A68093h
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
From a cavity-up view of the chip (as shown in EPIC), start-
ing in the upper right chip corner, the boundary scan
data-register bits are ordered as shown in Figure 12.
Right half of top-edge IOBs (Right to Left)
Bit 0 ( TDO end)
Bit 1
Bit 2
GCLK2
GCLK3
Left half of top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
M1
M0
M2
Left half of bottom-edge IOBs (Left to Right)
GCLK1
GCLK0
Right half of bottom-edge IOBs (Left to Right)
Including Boundary Scan in a Design
DONE
PROG
Since the boundary scan pins are dedicated, no special ele-
ment needs to be added to the design unless an internal
data register (USER1 or USER2) is desired.
Right-edge IOBs (Bottom to Top)
(TDI end)
CCLK
990602001
If an internal data register is used, insert the boundary scan
symbol and connect the necessary pins as appropriate.
Figure 12: Boundary Scan Bit Sequence
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implementation of these functions. Users can create their
own library of soft macros or RPMs based on the macros
and primitives in the standard library.
Development System
Virtex-E FPGAs are supported by the Xilinx Foundation and
Alliance Series CAE tools. The basic methodology for Vir-
tex-E design consists of three interrelated steps: design
entry, implementation, and verification. Industry-standard
tools are used for design entry and simulation (for example,
Synopsys FPGA Express), while Xilinx provides proprietary
architecture-specific tools for implementation.
The design environment supports hierarchical design entry,
with high-level schematics that comprise major functional
blocks, while lower-level schematics define the logic in
these blocks. These hierarchical design elements are auto-
matically combined by the implementation tools. Different
design entry tools can be combined within a hierarchical
design, thus allowing the most convenient entry method to
be used for each portion of the design.
The Xilinx development system is integrated under the Xil-
inx Design Manager (XDM™) software, providing designers
with a common user interface regardless of their choice of
entry and verification tools. The XDM software simplifies the
selection of implementation options with pull-down menus
and on-line help.
Design Implementation
The place-and-route tools (PAR) automatically provide the
implementation flow described in this section. The parti-
tioner takes the EDIF net list for the design and maps the
logic into the architectural resources of the FPGA (CLBs
and IOBs, for example). The placer then determines the
best locations for these blocks based on their interconnec-
tions and the desired performance. Finally, the router inter-
connects the blocks.
Application programs ranging from schematic capture to
Placement and Routing (PAR) can be accessed through the
XDM software. The program command sequence is gener-
ated prior to execution, and stored for documentation.
Several advanced software features facilitate Virtex-E design.
RPMs, for example, are schematic-based macros with relative
location constraints to guide their placement. They help
ensure optimal implementation of common functions.
The PAR algorithms support fully automatic implementation
of most designs. For demanding applications, however, the
user can exercise various degrees of control over the pro-
cess. User partitioning, placement, and routing information
is optionally specified during the design-entry process. The
implementation of highly structured designs can benefit
greatly from basic floor planning.
The implementation software incorporates Timing Wizard®
timing-driven placement and routing. Designers specify tim-
ing requirements along entire paths during design entry.
The timing path analysis routines in PAR then recognize
these user-specified requirements and accommodate them.
For HDL design entry, the Xilinx FPGA Foundation develop-
ment system provides interfaces to the following synthesis
design environments.
•
•
•
Synopsys (FPGA Compiler, FPGA Express)
Exemplar (Spectrum)
Synplicity (Synplify)
For schematic design entry, the Xilinx FPGA Foundation
and Alliance development system provides interfaces to the
following schematic-capture design environments.
•
•
Mentor Graphics V8 (Design Architect, QuickSim II)
Viewlogic Systems (Viewdraw)
Timing requirements are entered on a schematic in a form
directly relating to the system requirements, such as the tar-
geted clock frequency, or the maximum allowable delay
between two registers. In this way, the overall performance
of the system along entire signal paths is automatically tai-
lored to user-generated specifications. Specific timing infor-
mation for individual nets is unnecessary.
Third-party vendors support many other environments.
A standard interface-file specification, Electronic Design
Interchange Format (EDIF), simplifies file transfers into and
out of the development system.
Virtex-E FPGAs are supported by a unified library of stan-
dard functions. This library contains over 400 primitives and
macros, ranging from 2-input AND gates to 16-bit accumu-
lators, and includes arithmetic functions, comparators,
counters, data registers, decoders, encoders, I/O functions,
latches, Boolean functions, multiplexers, shift registers, and
barrel shifters.
Design Verification
In addition to conventional software simulation, FPGA users
can use in-circuit debugging techniques. Because Xilinx
devices are infinitely reprogrammable, designs can be veri-
fied in real time without the need for extensive sets of soft-
ware simulation vectors.
The “soft macro” portion of the library contains detailed
descriptions of common logic functions, but does not con-
tain any partitioning or placement information. The perfor-
mance of these macros depends, therefore, on the
partitioning and placement obtained during implementation.
The development system supports both software simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from the
design database, and back-annotates this information into
the net list for use by the simulator. Alternatively, the user
can verify timing-critical portions of the design using the
TRCE® static timing analyzer.
RPMs, on the other hand, do contain predetermined parti-
tioning and placement information that permits optimal
DS022-2 (v2.2) July 23, 2001
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Virtex™-E 1.8 V Field Programmable Gate Arrays
For in-circuit debugging, an optional download and read-
back cable is available. This cable connects the FPGA in the
target system to a PC or workstation. After downloading the
design into the FPGA, the designer can single-step the
logic, readback the contents of the flip-flops, and so observe
the internal logic state. Simple modifications can be down-
loaded into the system in a matter of minutes.
Configuration
Virtex-E devices are configured by loading configuration
data into the internal configuration memory. Some of the
pins used for this are dedicated configuration pins, while
others can be re-used as general purpose inputs and out-
puts once configuration is complete.
Configuration Modes
Virtex-E supports the following four configuration modes.
•
•
•
•
Slave-serial mode
Master-serial mode
SelectMAP mode
The following are dedicated pins:
Boundary-scan mode (JTAG)
•
•
•
•
•
Mode pins (M2, M1, M0)
Configuration clock pin (CCLK)
PROGRAM pin
The Configuration mode pins (M2, M1, M0) select among
these configuration modes with the option in each case of
having the IOB pins either pulled up or left floating prior to
configuration. The selection codes are listed in Table 8.
DONE pin
Boundary-scan pins (TDI, TDO, TMS, TCK)
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes. The
three mode pins have internal pull-up resistors, and default
to a logic High if left unconnected.
Depending on the configuration mode chosen, CCLK can
be an output generated by the FPGA, or can be generated
externally and provided to the FPGA as an input.
For correct operation, these pins require a VCCO of 3.3 V or
2.5 V. At 3.3 V the pins operate as LVTTL, and at 2.5 V they
operate as LVCMOS. All affected pins fall in banks 2 or 3.
Table 8: Configuration Codes
Configuration Mode
M2 M1 M0 CCLK Direction Data Width Serial Dout
Configuration Pull-ups
Master-serial mode
Boundary-scan mode
SelectMAP mode
Slave-serial mode
Master-serial mode
Boundary-scan mode
SelectMAP mode
Slave-serial mode
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Out
N/A
In
1
1
8
1
1
1
8
1
Yes
No
No
No
No
No
In
Yes
Yes
No
No
Out
N/A
In
Yes
Yes
Yes
Yes
No
In
Yes
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 9 lists the total number of bits required to configure
each device.
up at the DIN input pin a short time before each rising edge
of an externally generated CCLK.
Table 9: Virtex-E Bitstream Lengths
For more information on serial PROMs, see the PROM data
sheet at http://www.xilinx.com/partinfo/ds026.pdf.
Device
# of Configuration Bits
630,048
Multiple FPGAs can be daisy-chained for configuration from a
single source. After a particular FPGA has been configured,
the data for the next device is routed to the DOUT pin. The
data on the DOUT pin changes on the rising edge of CCLK.
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
863,840
1,442,016
The change of DOUT on the rising edge of CCLK differs
from previous families, but does not cause a problem for
mixed configuration chains. This change was made to
improve serial configuration rates for Virtex and Virtex-E
only chains.
1, 875,648
2,693,440
3,961,632
6,587,520
Figure 13 shows a full master/slave system. A Virtex-E
device in slave-serial mode should be connected as shown
in the right-most device.
8,308,992
10,159,648
12,922,336
16,283,712
Slave-serial mode is selected by applying <111> or <011> to
the mode pins (M2, M1, M0). A weak pull-up on the mode pins
makes slave serial the default mode if the pins are left uncon-
nected. Figure 14 shows slave-serial configuration timing.
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other source of
serial configuration data. The serial bitstream must be set
Table 10 provides more detail about the characteristics
shown in Figure 14. Configuration must be delayed until the
INIT pins of all daisy-chained FPGAs are High.
Table 10: Master/Slave Serial Mode Programming Switching
Figure
Description
DIN setup/hold, slave mode
DIN setup/hold, master mode
DOUT
References
Symbol
TDCC/TCCD
TDSCK/TCKDS
TCCO
Values
5.0 / 0.0
5.0 / 0.0
12.0
Units
ns, min
ns, min
ns, max
ns, min
ns, min
MHz, max
1/2
1/2
3
High time
CCLK
4
TCCH
5.0
Low time
5
TCCL
5.0
Maximum Frequency
FCC
66
Frequency Tolerance, master mode with respect to nominal
+45% –30%
.
N/C
3.3V
M0 M1
4.7 K
M0 M1
M2
M2
N/C
DOUT
DIN
DOUT
CCLK
VIRTEX-E
MASTER
SERIAL
VIRTEX-E,
XC4000XL,
XC1701L
CCLK
CLK
SLAVE
DATA
DIN
CE
CEO
PROGRAM
DONE
PROGRAM
DONE
RESET/OE
INIT
INIT
(Low Reset Option Used)
PROGRAM
XCVE_ds_013
Figure 13: Master/Slave Serial Mode Circuit Diagram
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Virtex™-E 1.8 V Field Programmable Gate Arrays
DIN
1
2
5
T
T
T
DCC
CCD
CCL
CCLK
4
T
CCH
3
T
CCO
DOUT
(Output)
X5379_a
Figure 14: Slave-Serial Mode Programming Switching Characteristics
devices operate in slave-serial mode. The SPROM RESET
pin is driven by INIT, and the CE input is driven by DONE.
There is the potential for contention on the DONE pin,
depending on the start-up sequence options chosen.
Master-Serial Mode
In master-serial mode, the CCLK output of the FPGA drives
a Xilinx Serial PROM that feeds bit-serial data to the DIN
input. The FPGA accepts this data on each rising CCLK
edge. After the FPGA has been loaded, the data for the next
device in a daisy-chain is presented on the DOUT pin after
the rising CCLK edge.
The sequence of operations necessary to configure a
Virtex-E FPGA serially appears in Figure 15.
Apply Power
The interface is identical to slave-serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK, which always starts at a slow default frequency. Con-
figuration bits then switch CCLK to a higher frequency for
the remainder of the configuration. Switching to a lower fre-
quency is prohibited.
FPGA starts to clear
configuration memory.
Set PROGRAM = High
FPGA makes a final
clearing pass and releases
If used to delay
Release INIT
INIT when finished.
configuration
Low
INIT?
High
The CCLK frequency is set using the ConfigRate option in
the bitstream generation software. The maximum CCLK fre-
quency that can be selected is 60 MHz. When selecting a
CCLK frequency, ensure that the serial PROM and any
daisy-chained FPGAs are fast enough to support the clock
rate.
Load a Configuration Bit
Once per bitstream,
FPGA checks data using CRC
and pulls INIT Low on error.
No
End of
Bitstream?
If no CRC errors found,
FPGA enters start-up phase
causing DONE to go High.
Yes
Configuration Completed
ds009_15_111799
On power-up, the CCLK frequency is approximately
2.5 MHz. This frequency is used until the ConfigRate bits
have been loaded when the frequency changes to the
selected ConfigRate. Unless a different frequency is speci-
fied in the design, the default ConfigRate is 4 MHz.
Figure 15: Serial Configuration Flowchart
Figure 16 shows the timing of master-serial configuration.
Master-serial mode is selected by a <000> or <100> on the
mode pins (M2, M1, M0). Table 10 shows the timing infor-
mation for Figure 16.
In a full master/slave system (Figure 13), the left-most
device operates in master-serial mode. The remaining
CCLK
(Output)
T
2
CKDS
T
1
DSCK
Serial Data In
Serial DOUT
(Output)
DS022_44_071201
Figure 16: Master-Serial Mode Programming Switching Characteristics
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Virtex™-E 1.8 V Field Programmable Gate Arrays
At power-up, VCC must rise from 1.0 V to VCC Min in less
than 50 ms, otherwise delay configuration by pulling PRO-
GRAM Low until VCC is valid.
Write
Write operations send packets of configuration data into the
FPGA. The sequence of operations for a multi-cycle write
operation is shown below. Note that a configuration packet
can be split into many such sequences. The packet does
not have to complete within one assertion of CS, illustrated
in Figure 17.
SelectMAP Mode
The SelectMAP mode is the fastest configuration option.
Byte-wide data is written into the FPGA with a BUSY flag
controlling the flow of data.
1. Assert WRITE and CS Low. Note that when CS is
asserted on successive CCLKs, WRITE must remain
either asserted or de-asserted. Otherwise, an abort is
initiated, as described below.
An external data source provides a byte stream, CCLK, a
Chip Select (CS) signal and a Write signal (WRITE). If
BUSY is asserted (High) by the FPGA, the data must be
held until BUSY goes Low.
2. Drive data onto D[7:0]. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more that one CS should be asserted.
Data can also be read using the SelectMAP mode. If
WRITE is not asserted, configuration data is read out of the
FPGA as part of a readback operation.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained to permit high-speed 8-bit readback.
3. At the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance instead
occurs on the first clock after BUSY goes Low, and the
data must be held until this has happened.
Retention of the SelectMAP port is selectable on a
design-by-design basis when the bitstream is generated. If
retention is selected, PROHIBIT constraints are required to
prevent the SelectMAP-port pins from being used as user
I/O.
4. Repeat steps 2 and 3 until all the data has been sent.
5. De-assert CS and WRITE.
Multiple Virtex-E FPGAs can be configured using the
SelectMAP mode, and be made to start-up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, Data, WRITE, and BUSY pins of all the devices in
parallel. The individual devices are loaded separately by
asserting the CS pin of each device in turn and writing the
appropriate data. See Table 11 for SelectMAP Write Timing
Characteristics.
Table 11: SelectMAP Write Timing Characteristics
Description
Symbol
TSMDCC/TSMCCD
TSMCSCC/TSMCCCS
TSMCCW/TSMWCC
TSMCKBY
Units
ns, min
D
0-7 Setup/Hold
1/2
3/4
5/6
7
5.0 / 1.0
7.0 / 1.0
7.0 / 1.0
12.0
CS Setup/Hold
ns, min
WRITE Setup/Hold
ns, min
CCLK
BUSY Propagation Delay
Maximum Frequency
ns, max
MHz, max
MHz, max
FCC
66
Maximum Frequency with no handshake
FCCNH
50
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Virtex™-E 1.8 V Field Programmable Gate Arrays
CCLK
3
4
CS
5
6
WRITE
1
2
DATA[7:0]
BUSY
7
No Write
Write
No Write
Write
DS022_45_071201
Figure 17: Write Operations
A flowchart for the write operation is shown in Figure 18.
Note that if CCLK is slower than fCCNH, the FPGA never
asserts BUSY, In this case, the above handshake is unnec-
essary, and data can simply be entered into the FPGA every
CCLK cycle.
Apply Power
FPGA starts to clear
configuration memory.
Set PROGRAM = High
FPGA makes a final
clearing pass and releases
INIT when finished.
If used to delay
configuration
Release INIT
Abort
Low
During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the cur-
rent packet command to be aborted. The device remains
BUSY until the aborted operation has completed. Following
an abort, data is assumed to be unaligned to word bound-
aries, and the FPGA requires a new synchronization word
prior to accepting any new packets.
INIT?
High
Set WRITE = Low
Enter Data Source
Sequence A
On first FPGA
Set CS = Low
To initiate an abort during a write operation, de-assert
WRITE. At the rising edge of CCLK, an abort is initiated, as
shown in Figure 19.
Apply Configuration Byte
Once per bitstream,
FPGA checks data using CRC
and pulls INIT Low on error.
High
Busy?
Low
No
End of Data?
Yes
If no errors,
first FPGAs enter start-up phase
releasing DONE.
On first FPGA
Set CS = High
If no errors,
later FPGAs enter start-up phase
releasing DONE.
For any other FPGAs
Repeat Sequence A
Disable Data Source
Set WRITE = High
When all DONE pins
are released, DONE goes High
and start-up sequences complete.
Configuration Completed
ds009_18_111799
Figure 18: SelectMAP Flowchart for Write Operations
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Virtex™-E 1.8 V Field Programmable Gate Arrays
CCLK
CS
WRITE
DATA[7:0]
BUSY
Abort
DS022_46_071201
Figure 19: SelectMAP Write Abort Waveforms
Configuration and readback via the TAP is always available.
The boundary-scan mode is selected by a <101> or <001>
on the mode pins (M2, M1, M0).
Boundary-Scan Mode
In the boundary-scan mode, no non-dedicated pins are
required, configuration being done entirely through the
IEEE 1149.1 Test Access Port.
Configuration Sequence
Configuration through the TAP uses the CFG_IN instruc-
tion. This instruction allows data input on TDI to be con-
verted into data packets for the internal configuration bus.
The configuration of Virtex-E devices is a three-phase pro-
cess. First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
The following steps are required to configure the FPGA
through the boundary-scan port (when using TCK as a
start-up clock).
Configuration is automatically initiated on power-up unless
it is delayed by the user, as described below. The configura-
tion process can also be initiated by asserting PROGRAM.
The end of the memory-clearing phase is signalled by INIT
going High, and the completion of the entire process is sig-
nalled by DONE going High.
1. Load the CFG_IN instruction into the boundary-scan
instruction register (IR).
2. Enter the Shift-DR (SDR) state.
3. Shift a configuration bitstream into TDI.
4. Return to Run-Test-Idle (RTI).
5. Load the JSTART instruction into IR.
6. Enter the SDR state.
The power-up timing of configuration signals is shown in
Figure 20.
7. Clock TCK through the startup sequence.
8. Return to RTI.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Vcc
TPOR
PROGRAM
TPL
INIT
TICCK
VALI
CCLK OUTPUT or INPUT
M0, M1, M2
(Required)
ds022_020_071201
Figure 20: Power-Up Timing Configuration Signals
The corresponding timing characteristics are listed in
Start-Up Sequence
Table 12.
The default Start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary.
Table 12: Power-up Timing Characteristics
Description
Symbol
TPOR
TPL
Value
2.0
Units
ms, max
s, max
s, min
Power-on Reset1
Program Latency
One CCLK cycle later, the Global Set/Reset (GSR) and Glo-
bal Write Enable (GWE) signals are released. This permits
the internal storage elements to begin changing state in
response to the logic and the user clock.
100.0
0.5
CCLK (output) Delay
TICCK
4.0
s, max
ns, min
The relative timing of these events can be changed. In addi-
tion, the GTS, GSR, and GWE events can be made depen-
dent on the DONE pins of multiple devices all going High,
forcing the devices to start synchronously. The sequence
can also be paused at any stage until lock has been
achieved on any or all DLLs.
Program Pulse Width TPROGRAM
300
Notes:
1.
T
POR delay is the initialization time required after VCCINT and
VCCO in Bank 2 reach the recommended operating voltage.
Delaying Configuration
INIT can be held Low using an open-drain driver. An
open-drain is required since INIT is a bidirectional
open-drain pin that is held Low by the FPGA while the con-
figuration memory is being cleared. Extending the time that
the pin is Low causes the configuration sequencer to wait.
Thus, configuration is delayed by preventing entry into the
phase where data is loaded.
Readback
The configuration data stored in the Virtex-E configuration
memory can be readback for verification. Along with the
configuration data it is possible to readback the contents all
flip-flops/latches, LUT RAMs, and block RAMs. This capa-
bility is used for real-time debugging. For more detailed
information, see application note XAPP138 “Virtex FPGA
Series Configuration and Readback”.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Design Considerations
This section contains more detailed design information on
the following features.
In order to guarantee the system clock establishes prior to
the device “waking up,” the DLL can delay the completion of
the device configuration process until after the DLL
achieves lock.
•
•
•
Delay-Locked Loop . . . see page 19
BlockRAM . . . see page 23
SelectI/O . . . see page 30
By taking advantage of the DLL to remove on-chip clock
delay, the designer can greatly simplify and improve system
level design involving high-fanout, high-performance clocks.
Using DLLs
The Virtex-E FPGA series provides up to eight fully digital
dedicated on-chip Delay-Locked Loop (DLL) circuits which
provide zero propagation delay, low clock skew between
output clock signals distributed throughout the device, and
advanced clock domain control. These dedicated DLLs can
be used to implement several circuits which improve and
simplify system level design.
Library DLL Symbols
Figure 21 shows the simplified Xilinx library DLL macro
symbol, BUFGDLL. This macro delivers a quick and effi-
cient way to provide a system clock with zero propagation
delay throughout the device. Figure 22 and Figure 23 show
the two library DLL primitives. These symbols provide
access to the complete set of DLL features when imple-
menting more complex applications.
Introduction
As FPGAs grow in size, quality on-chip clock distribution
becomes increasingly important. Clock skew and clock
delay impact device performance and the task of managing
clock skew and clock delay with conventional clock trees
becomes more difficult in large devices. The Virtex-E series
of devices resolve this potential problem by providing up to
eight fully digital dedicated on-chip DLL circuits, which pro-
vide zero propagation delay and low clock skew between
output clock signals distributed throughout the device.
I
O
0ns
ds022_25_121099
Figure 21: Simplified DLL Macro Symbol BUFGDLL
Each DLL can drive up to two global clock routing networks
within the device. The global clock distribution network min-
imizes clock skews due to loading differences. By monitor-
ing a sample of the DLL output clock, the DLL can
compensate for the delay on the routing network, effectively
eliminating the delay from the external input port to the indi-
vidual clock loads within the device.
CLKDLL
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
In addition to providing zero delay with respect to a user
source clock, the DLL can provide multiple phases of the
source clock. The DLL can also act as a clock doubler or it
can divide the user source clock by up to 16.
RST
ds022_26_121099
Figure 22: Standard DLL Symbol CLKDLL
Clock multiplication gives the designer a number of design
alternatives. For instance, a 50 MHz source clock doubled
by the DLL can drive an FPGA design operating at 100
MHz. This technique can simplify board design because the
clock path on the board no longer distributes such a
high-speed signal. A multiplied clock also provides design-
ers the option of time-domain-multiplexing, using one circuit
twice per clock cycle, consuming less area than two copies
of the same circuit. Two DLLs in can be connected in series
to increase the effective clock multiplication factor to four.
CLKDLLHF
CLKIN
CLKFB
CLK0
CLK180
CLKDV
RST
LOCKED
The DLL can also act as a clock mirror. By driving the DLL
output off-chip and then back in again, the DLL can be used
to de-skew a board level clock between multiple devices.
ds022_027_121099
Figure 23: High Frequency DLL Symbol CLKDLLHF
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Virtex™-E 1.8 V Field Programmable Gate Arrays
DLLs. This makes a total of eight usable input pins for DLLs
in the Virtex-E family.
BUFGDLL Pin Descriptions
Use the BUFGDLL macro as the simplest way to provide
zero propagation delay for a high-fanout on-chip clock from
an external input. This macro uses the IBUFG, CLKDLL and
BUFG primitives to implement the most basic DLL applica-
tion as shown in Figure 24.
Feedback Clock Input — CLKFB
The DLL requires a reference or feedback signal to provide
the delay-compensated output. Connect only the CLK0 or
CLK2X DLL outputs to the feedback clock input (CLKFB)
pin to provide the necessary feedback to the DLL. The feed-
back clock input can also be provided through one of the fol-
lowing pins.
IBUFG
BUFG
CLKDLL
I
O
I
O
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
IBUFG - Global Clock Input Pad
CLK2X
IO_LVDS_DLL - the pin adjacent to IBUF
CLKDV
LOCKED
RST
If an IBUFG sources the CLKFB pin, the following special
rules apply.
ds022_28_121099
1. An external input port must source the signal that drives
the IBUFG I pin.
Figure 24: BUFGDLL Schematic
This symbol does not provide access to the advanced clock
domain controls or to the clock multiplication or clock divi-
sion features of the DLL. This symbol also does not provide
access to the RST, or LOCKED pins of the DLL. For access
to these features, a designer must use the library DLL prim-
itives described in the following sections.
2. The CLK2X output must feedback to the device if both
the CLK0 and CLK2X outputs are driving off chip
devices.
3. That signal must directly drive only OBUFs and nothing
else.
These rules enable the software determine which DLL clock
output sources the CLKFB pin.
Source Clock Input — I
The I pin provides the user source clock, the clock signal on
which the DLL operates, to the BUFGDLL. For the BUF-
GDLL macro the source clock frequency must fall in the low
frequency range as specified in the data sheet. The BUF-
GDLL requires an external signal source clock. Therefore,
only an external input port can source the signal that drives
the BUFGDLL I pin.
Reset Input — RST
When the reset pin RST activates the LOCKED signal deac-
tivates within four source clock cycles. The RST pin, active
High, must either connect to a dynamic signal or tied to
ground. As the DLL delay taps reset to zero, glitches can
occur on the DLL clock output pins. Activation of the RST
pin can also severely affect the duty cycle of the clock out-
put pins. Furthermore, the DLL output clocks no longer
de-skew with respect to one another. For these reasons,
rarely use the reset pin unless re-configuring the device or
changing the input frequency.
Clock Output — O
The clock output pin O represents a delay-compensated
version of the source clock (I) signal. This signal, sourced by
a global clock buffer BUFG symbol, takes advantage of the
dedicated global clock routing resources of the device.
2x Clock Output — CLK2X
The output clock has a 50-50 duty cycle unless you deacti-
vate the duty cycle correction property.
The output pin CLK2X provides a frequency-doubled clock
with an automatic 50/50 duty-cycle correction. Until the
CLKDLL has achieved lock, the CLK2X output appears as a
1x version of the input clock with a 25/75 duty cycle. This
behavior allows the DLL to lock on the correct edge with
respect to source clock. This pin is not available on the
CLKDLLHF primitive.
CLKDLL Primitive Pin Descriptions
The library CLKDLL primitives provide access to the com-
plete set of DLL features needed when implementing more
complex applications with the DLL.
Source Clock Input — CLKIN
Clock Divide Output — CLKDV
The CLKIN pin provides the user source clock (the clock
signal on which the DLL operates) to the DLL. The CLKIN
frequency must fall in the ranges specified in the data sheet.
A global clock buffer (BUFG) driven from another CLKDLL,
one of the global clock input buffers (IBUFG), or an
IO_LVDS_DLL pin on the same edge of the device (top or
bottom) must source this clock signal. There are four
IO_LVDS_DLL input pins that can be used as inputs to the
The clock divide output pin CLKDV provides a lower fre-
quency version of the source clock. The CLKDV_DIVIDE
property controls CLKDV such that the source clock is
divided by N where N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 16.
This feature provides automatic duty cycle correction such
that the CLKDV output pin always has a 50/50 duty cycle,
with the exception of noninteger divides in HF mode, where
the duty cycle is 1/3 for N=1.5 and 2/5 for N=2.5.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
The DLL clock outputs can drive an OBUF, a BUFG, or they
can route directly to destination clock pins. The DLL clock
outputs can only drive the BUFGs that reside on the same
edge (top or bottom).
1x Clock Outputs — CLK[0|90|180|270]
The 1x clock output pin CLK0 represents a delay-compen-
sated version of the source clock (CLKIN) signal. The
CLKDLL primitive provides three phase-shifted versions of
the CLK0 signal while CLKDLLHF provides only the 180
phase-shifted version. The relationship between phase shift
and the corresponding period shift appears in Table 13.
Locked Output — LOCKED
To achieve lock, the DLL might need to sample several thou-
sand clock cycles. After the DLL achieves lock, the
LOCKED signal activates. The DLL timing parameter sec-
tion of the data sheet provides estimates for locking times.
Table 13: Relationship of Phase-Shifted Output Clock
to Period Shift
To guarantee that the system clock is established prior to
the device “waking up,” the DLL can delay the completion of
the device configuration process until after the DLL locks.
The STARTUP_WAIT property activates this feature.
Phase (degrees)
Period Shift (percent)
0
0%
90
25%
50%
75%
Until the LOCKED signal activates, the DLL output clocks
are not valid and can exhibit glitches, spikes, or other spuri-
ous movement. In particular the CLK2X output appears as a
1x clock with a 25/75 duty cycle.
180
270
The timing diagrams in Figure 25 illustrate the DLL clock
output characteristics.
DLL Properties
Properties provide access to some of the Virtex-E series
DLL features, (for example, clock division and duty cycle
correction).
0
90 180 270
0
90 180 270
t
Duty Cycle Correction Property
CLKIN
CLK2X
The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270,
use the duty-cycle corrected default, exhibiting a 50/50 duty
cycle. The DUTY_CYCLE_CORRECTION property (by
default TRUE) controls this feature. To deactivate the DLL
duty-cycle correction for the 1x clock outputs, attach the
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL symbol. When duty-cycle correction deactivates, the
output clock has the same duty cycle as the source clock.
CLKDV_DIVIDE=2
CLKDV
DUTY_CYCLE_CORRECTION=FALSE
CLK0
CLK90
CLK180
CLK270
Clock Divide Property
The CLKDV_DIVIDE property specifies how the signal on
the CLKDV pin is frequency divided with respect to the
CLK0 pin. The values allowed for this property are 1.5, 2,
2.5, 3, 4, 5, 8, or 16; the default value is 2.
DUTY_CYCLE_CORRECTION=TRUE
CLK0
Startup Delay Property
CLK90
CLK180
CLK270
This property, STARTUP_WAIT, takes on a value of TRUE
or FALSE (the default value). When TRUE the device con-
figuration DONE signal waits until the DLL locks before
going to High.
ds022_29_121099
Virtex-E DLL Location Constraints
Figure 25: DLL Output Characteristics
As shown in Figure 26, there are four additional DLLs in the
Virtex-E devices, for a total of eight per Virtex-E device.
These DLLs are located in silicon, at the top and bottom of
the two innermost block SelectRAM columns. The location
constraint LOC, attached to the DLL symbol with the identi-
fier DLL0S, DLL0P, DLL1S, DLL1P, DLL2S, DLL2P, DLL3S,
or DLL3P, controls the DLL location.
The DLL provides duty cycle correction on all 1x clock out-
puts such that all 1x clock outputs by default have a 50/50
duty cycle. The DUTY_CYCLE_CORRECTION property
(TRUE by default), controls this feature. In order to deacti-
vate the DLL duty cycle correction, attach the
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL symbol. When duty cycle correction deactivates, the
output clock has the same duty cycle as the source clock.
The LOC property uses the following form:
LOC = DLL0P
DS022-2 (v2.2) July 23, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
In a similar manner, a phase shift of the input clock is also
possible. The phase shift propagates to the output one to
four clocks after the original shift, with no disruption to the
CLKDLL control.
DLL-3S DLL-3P
DLL-2P DLL-2S
B
R
A
B
R
A
B
R
A
B
R
A
Output Clocks
M
M
M
M
As mentioned earlier in the DLL pin descriptions, some
restrictions apply regarding the connectivity of the output
pins. The DLL clock outputs can drive an OBUF, a global
clock buffer BUFG, or they can route directly to destination
clock pins. The only BUFGs that the DLL clock outputs can
drive are the two on the same edge of the device (top or bot-
tom). In addition, the CLK2X output of the secondary DLL
can connect directly to the CLKIN of the primary DLL in the
same quadrant.
Bottom Right
Half Edge
DLL-1S DLL-1P
DLL-0P DLL-0S
x132_14_100799
Figure 26: Virtex Series DLLs
Design Factors
Use the following design considerations to avoid pitfalls and
improve success designing with Xilinx devices.
Do not use the DLL output clock signals until after activation
of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and
can exhibit glitches, spikes, or other spurious movement.
Input Clock
The output clock signal of a DLL, essentially a delayed ver-
sion of the input clock signal, reflects any instability on the
input clock in the output waveform. For this reason the qual-
ity of the DLL input clock relates directly to the quality of the
output clock waveforms generated by the DLL. The DLL
input clock requirements are specified in the data sheet.
Useful Application Examples
The Virtex-E DLL can be used in a variety of creative and
useful applications. The following examples show some of
the more common applications. The Verilog and VHDL
example files are available at:
In most systems a crystal oscillator generates the system
clock. The DLL can be used with any commercially available
quartz crystal oscillator. For example, most crystal oscilla-
tors produce an output waveform with a frequency tolerance
of 100 PPM, meaning 0.01 percent change in the clock
period. The DLL operates reliably on an input waveform with
a frequency drift of up to 1 ns — orders of magnitude in
excess of that needed to support any crystal oscillator in the
industry. However, the cycle-to-cycle jitter must be kept to
less than 300 ps in the low frequencies and 150 ps for the
high frequencies.
ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip
Standard Usage
The circuit shown in Figure 27 resembles the BUFGDLL
macro implemented to provide access to the RST and
LOCKED pins of the CLKDLL.
CLKDLL
IBUFG
BUFG
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
Input Clock Changes
CLK2X
CLKDV
LOCKED
Changing the period of the input clock beyond the maximum
drift amount requires a manual reset of the CLKDLL. Failure
to reset the DLL produces an unreliable lock signal and out-
put clock.
OBUF
IBUF
RST
ds022_028_121099
Figure 27: Standard DLL Implementation
It is possible to stop the input clock with little impact to the
DLL. Stopping the clock should be limited to less than
100 s to keep device cooling to a minimum. The clock
should be stopped during a Low phase, and when restored
the full High period should be seen. During this time,
LOCKED stays High and remains High when the clock is
restored.
Board Level De-skew of Multiple Non-Virtex-E
Devices
The circuit shown in Figure 28 can be used to de-skew a
system clock between a Virtex-E chip and other non-Vir-
tex-E chips on the same board. This application is com-
monly used when the Virtex-E device is used in conjunction
with other standard products such as SRAM or DRAM
devices. While designing the board level route, ensure that
the return net delay to the source equals the delay to the
other chips involved.
When the clock is stopped, one to four more clocks are still
observed as the delay line is flushed. When the clock is
restarted, the output clocks are not observed for one to four
clocks as the delay line is filled. The most common case is
two or three clocks.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Because any single DLL can access only two BUFGs at
most, any additional output clock signals must be routed
from the DLL in this example on the high speed backbone
routing.
Virtex-E Device
IBUFG
CLKDLL
OBUF
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
The dll_2x files in the xapp132.zip file show the VHDL and
IBUFG
Verilog implementation of this circuit.
CLK2X
Virtex-E 4x Clock
CLKDV
LOCKED
RST
Two DLLs located in the same half-edge (top-left, top-right,
bottom-right, bottom-left) can be connected together, with-
out using a BUFG between the CLKDLLs, to generate a 4x
clock as shown in Figure 30. Virtex-E devices, like the Virtex
devices, have four clock networks that are available for inter-
nal de-skewing of the clock. Each of the eight DLLs have
access to two of the four clock networks. Although all the
DLLs can be used for internal de-skewing, the presence of
two GCLKBUFs on the top and two on the bottom indicate
that only two of the four DLLs on the top (and two of the four
DLLs on the bottom) can be used for this purpose.
CLKDLL
BUFG
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
RST
Non-Virtex-E Chip
Non-Virtex-E Chip
CLKDLL-S
IBUFG
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
Other Non_Virtex-E Chips
ds022_029_121099
CLK2X
CLKDV
Figure 28: DLL De-skew of Board Level Clock
INV
RST
LOCKED
Board-level de-skew is not required for low-fanout clock net-
works. It is recommended for systems that have fanout lim-
itations on the clock network, or if the clock distribution chip
cannot handle the load.
CLKDLL-P
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
Do not use the DLL output clock signals until after activation
of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and
can exhibit glitches, spikes, or other spurious movement.
BUFG
OBUF
CLK2X
CLKDV
RST
LOCKED
The dll_mirror_1 files in the xapp132.zip file show the VHDL
and Verilog implementation of this circuit.
ds022_031_041901
De-Skew of Clock and Its 2x Multiple
Figure 30: DLL Generation of 4x Clock in Virtex-E
The circuit shown in Figure 29 implements a 2x clock multi-
plier and also uses the CLK0 clock output with a zero ns
skew between registers on the same chip. Alternatively, a
clock divider circuit can be implemented using similar con-
nections.
Devices
The dll_4xe files in the xapp132.zip file show the DLL imple-
mentation in Verilog for Virtex-E devices. These files can be
found at:
ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip
CLKDLL
IBUFG
BUFG
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
Using Block SelectRAM+ Features
BUFG
OBUF
CLK2X
The Virtex FPGA Series provides dedicated blocks of
on-chip, true dual-read/write port synchronous RAM, with
4096 memory cells. Each port of the block SelectRAM+
memory can be independently configured as a read/write
port, a read port, a write port, and can be configured to a
specific data width. The block SelectRAM+ memory offers
new capabilities allowing the FPGA designer to simplify
designs.
CLKDV
LOCKED
IBUF
RST
ds022_030_121099
Figure 29: DLL De-skew of Clock and 2x Multiple
DS022-2 (v2.2) July 23, 2001
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Operating Modes
RAMB4_S#_S#
VIrtex-E block SelectRAM+ memory supports two operating
modes:
WEA
ENA
•
•
Read Through
Write Back
DOA[#:0]
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]
Read Through (one clock edge)
The read address is registered on the read port clock edge
and data appears on the output after the RAM access time.
Some memories might place the latch/register at the out-
puts, depending on whether a faster clock-to-out versus
set-up time is desired. This is generally considered to be an
inferior solution, since it changes the read operation to an
asynchronous function with the possibility of missing an
address/control line transition during the generation of the
read pulse clock.
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
DOB[#:0]
ds022_032_121399
Figure 31: Dual-Port Block SelectRAM+ Memory
RAMB4_S#
Write Back (one clock edge)
WE
EN
The write address is registered on the write port clock edge
and the data input is written to the memory and mirrored on
the output.
RST
CLK
DO[#:0]
ADDR[#:0]
DI[#:0]
Block SelectRAM+ Characteristics
ds022_033_121399
•
All inputs are registered with the port clock and have a
set-up to clock timing specification.
Figure 32: Single-Port Block SelectRAM+ Memory
•
All outputs have a read through or write back function
depending on the state of the port WE pin. The outputs
relative to the port clock are available after the
clock-to-out timing specification.
Table 14: Available Library Primitives
Primitive
RAMB4_S1
Port A Width
Port B Width
N/A
1
•
•
The block SelectRAMs are true SRAM memories and
do not have a combinatorial path from the address to
the output. The LUT SelectRAM+ cells in the CLBs are
still available with this function.
RAMB4_S1_S1
RAMB4_S1_S2
RAMB4_S1_S4
RAMB4_S1_S8
RAMB4_S1_S16
RAMB4_S2
2
1
4
The ports are completely independent from each other
(i.e., clocking, control, address, read/write function, and
data width) without arbitration.
8
16
N/A
2
•
•
A write operation requires only one clock edge.
A read operation requires only one clock edge.
RAMB4_S2_S2
RAMB4_S2_S4
RAMB4_S2_S8
RAMB4_S2_S16
RAMB4_S4
The output ports are latched with a self timed circuit to guar-
antee a glitch free read. The state of the output port does
not change until the port executes another read or write
operation.
2
4
4
8
16
N/A
4
Library Primitives
RAMB4_S4_S4
RAMB4_S4_S8
RAMB4_S4_S16
RAMB4_S8
Figure 31 and Figure 32 show the two generic library block
SelectRAM+ primitives. Table 14 describes all of the avail-
able primitives for synthesis and simulation.
8
16
N/A
8
RAMB4_S8_S8
RAMB4_S8_S16
RAMB4_S16
8
16
N/A
16
16
RAMB4_S16_S16
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Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Data Output Bus—DO[A|B]<#:0>
Port Signals
The data out bus reflects the contents of the memory cells
referenced by the address bus at the last active clock edge.
During a write operation, the data out bus reflects the data
in bus. The width of this bus equals the width of the port.
The allowed widths appear in Table 15.
Each block SelectRAM+ port operates independently of the
others while accessing the same set of 4096 memory cells.
Table 15 describes the depth and width aspect ratios for the
block SelectRAM+ memory.
Table 15: Block SelectRAM+ Port Aspect Ratios
Inverting Control Pins
Width
Depth
4096
2048
1024
512
ADDR Bus
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
Data Bus
DATA<0>
The four control pins (CLK, EN, WE and RST) for each port
have independent inversion control as a configuration
option.
1
2
DATA<1:0>
DATA<3:0>
DATA<7:0>
DATA<15:0>
4
Address Mapping
8
Each port accesses the same set of 4096 memory cells
using an addressing scheme dependent on the width of the
port.
16
256
The physical RAM location addressed for a particular width
are described in the following formula (of interest only when
the two ports use different aspect ratios).
Clock—CLK[A|B]
Each port is fully synchronous with independent clock pins.
All port input pins have setup time referenced to the port
CLK pin. The data output bus has a clock-to-out time refer-
enced to the CLK pin.
Start = ((ADDRport +1) * Widthport) –1
End = ADDRport * Widthport
Table 16 shows low order address mapping for each port
width.
Enable—EN[A|B]
The enable pin affects the read, write and reset functionality
of the port. Ports with an inactive enable pin keep the output
pins in the previous state and do not write data to the mem-
ory cells.
Table 16: Port Address Mapping
Port
Port
Width
Addresses
Write Enable—WE[A|B]
1
4095...
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Activating the write enable pin allows the port to write to the
memory cells. When active, the contents of the data input
bus are written to the RAM at the address pointed to by the
address bus, and the new data also reflects on the data out
bus. When inactive, a read operation occurs and the con-
tents of the memory cells referenced by the address bus
reflect on the data out bus.
2
4
2047...
1023...
511...
07
06
05
04
03
02
01
00
03
02
01
00
8
01
00
16
255...
00
Creating Larger RAM Structures
Reset—RST[A|B]
The block SelectRAM+ columns have specialized routing to
allow cascading blocks together with minimal routing delays.
This achieves wider or deeper RAM structures with a smaller
timing penalty than when using normal routing channels.
The reset pin forces the data output bus latches to zero syn-
chronously. This does not affect the memory cells of the
RAM and does not disturb a write operation on the other
port.
Location Constraints
Address Bus—ADDR[A|B]<#:0>
Block SelectRAM+ instances can have LOC properties
attached to them to constrain the placement. The block
SelectRAM+ placement locations are separate from the
CLB location naming convention, allowing the LOC proper-
ties to transfer easily from array to array.
The address bus selects the memory cells for read or write.
The width of the port determines the required width of this
bus as shown in Table 15.
Data In Bus—DI[A|B]<#:0>
The data in bus provides the new data value to be written
into the RAM. This bus and the port have the same width, as
shown in Table 15.
The LOC properties use the following form.
LOC = RAMB4_R#C#
RAMB4_R0C0 is the upper left RAMB4 location on the
device.
DS022-2 (v2.2) July 23, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Conflict Resolution
The block SelectRAM+ memory is a true dual-read/write
port RAM that allows simultaneous access of the same
memory cell from both ports. When one port writes to a
given memory cell, the other port must not address that
memory cell (for a write or a read) within the clock-to-clock
setup window. The following lists specifics of port and mem-
ory cell write conflict resolution.
bus contains the contents of the memory location 0x7E as
indicated by the ADDR bus.
At the fourth rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is Low
indicating that the block SelectRAM+ memory is now dis-
abled. The DO bus retains the last value.
Dual Port Timing
•
If both ports write to the same memory cell
simultaneously, violating the clock-to-clock setup
requirement, consider the data stored as invalid.
Figure 34 shows a timing diagram for a true dual-port
read/write block SelectRAM+ memory. The clock on port A
has a longer period than the clock on Port B. The timing
parameter TBCCS, (clock-to-clock set-up) is shown on this
diagram. The parameter, TBCCS is violated once in the dia-
gram. All other timing parameters are identical to the single
port version shown in Figure 33.
•
If one port attempts a read of the same memory cell
the other simultaneously writes, violating the
clock-to-clock setup requirement, the following occurs.
-
-
The write succeeds
The data out on the writing port accurately reflects
the data written.
TBCCS is only of importance when the address of both ports
are the same and at least one port is performing a write
operation. When the clock-to-clock set-up parameter is vio-
lated for a WRITE-WRITE condition, the contents of the
memory at that location are invalid. When the clock-to-clock
set-up parameter is violated for a WRITE-READ condition,
the contents of the memory are correct, but the read port
has invalid data.
-
The data out on the reading port is invalid.
Conflicts do not cause any physical damage.
Single Port Timing
Figure 33 shows a timing diagram for a single port of a block
SelectRAM+ memory. The block SelectRAM+ AC switching
characteristics are specified in the data sheet. The block
SelectRAM+ memory is initially disabled.
At the first rising edge of the CLKA, memory location 0x00 is
to be written with the value 0xAAAA and is mirrored on the
DOA bus. The last operation of Port B was a read to the
same memory location 0x00. The DOB bus of Port B does
not change with the new value on Port A, and retains the
last read value. A short time later, Port B executes another
read to memory location 0x00, and the DOB bus now
reflects the new memory value written by Port A.
At the first rising edge of the CLK pin, the ADDR, DI, EN,
WE, and RST pins are sampled. The EN pin is High and the
WE pin is Low indicating a read operation. The DO bus con-
tains the contents of the memory location, 0x00, as indi-
cated by the ADDR bus.
At the second rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN and WE pins
are High indicating a write operation. The DO bus mirrors the
DI bus. The DI bus is written to the memory location 0x0F.
At the second rising edge of CLKA, memory location 0x7E
is written with the value 0x9999 and is mirrored on the DOA
bus. Port B then executes a read operation to the same
memory location without violating the TBCCS parameter and
the DOB reflects the new memory values written by Port A.
At the third rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is High
and the WE pin is Low indicating a read operation. The DO
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Virtex™-E 1.8 V Field Programmable Gate Arrays
T
T
BPWL
BPWH
CLK
T
T
BACK
00
ADDR
0F
7E
8F
BDCK
DDDD
CCCC
BBBB
2222
DIN
DOUT
EN
T
BCKO
MEM (00)
CCCC
MEM (7E)
T
BECK
RST
WE
T
BWCK
DISABLED
READ
WRITE
READ
DISABLED
ds022_0343_121399
Figure 33: Timing Diagram for Single Port Block SelectRAM+ Memory
T
BCCS
VIOLATION
CLK_A
ADDR_A
00
7E
0F
0F
7E
EN_A
WE_A
DI_A
T
BCCS
T
BCCS
AAAA
9999
AAAA
0000
1111
AAAA
9999
AAAA
UNKNOWN
2222
DO_A
CLK_B
ADDR_B
00
00
7E
0F
0F
7E
1A
EN_B
WE_B
DI_B
1111
1111
1111
BBBB
1111
2222
FFFF
DO_B
MEM (00)
AAAA
9999
BBBB
UNKNOWN
2222
FFFF
ds022_035_121399
Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory
At the third rising edge of CLKA, the TBCCS parameter is
violated with two writes to memory location 0x0F. The DOA
and DOB busses reflect the contents of the DIA and DIB
busses, but the stored value at 0x0F is invalid.
on the DOA bus. Port B also executes a read operation to
memory location 0x0F and also reads invalid data.
At the fifth rising edge of CLKA a read operation is per-
formed that does not violate the TBCCS parameter to the
previous write of 0x7E by Port B. THe DOA bus reflects the
recently written value by Port B.
At the fourth rising edge of CLKA, a read operation is per-
formed at memory location 0x0F and invalid data is present
DS022-2 (v2.2) July 23, 2001
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Initialization
Design Examples
The block SelectRAM+ memory can initialize during the
device configuration sequence. The 16 initialization properties
of 64 hex values each (a total of 4096 bits) set the initialization
of each RAM. These properties appear in Table 17. Any initial-
ization properties not explicitly set configure as zeros. Partial
initialization strings pad with zeros. Initialization strings
greater than 64 hex values generate an error. The RAMs can
be simulated with the initialization values using generics in
VHDL simulators and parameters in Verilog simulators.
Creating a 32-bit Single-Port RAM
The true dual-read/write port functionality of the block
SelectRAM+ memory allows a single port, 128 deep by
32-bit wide RAM to be created using a single block
SelectRAM+ cell as shown in Figure 35.
RAMB4_S16_S16
WE
WEA
ENA
RSTA
CLKA
EN
RST
CLK
DOA[15:0]
DO[31:16]
ADDR[6:0], V
ADDRA[7:0]
DIA[15:0]
Initialization in VHDL and Synopsys
CC
DI[31:16]
The block SelectRAM+ structures can be initialized in VHDL
for both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the VHDL code uses a generic
to pass the initialization. Synopsys FPGA compiler does not
presently support generics. The initialization values instead
attach as attributes to the RAM by a built-in Synopsys
dc_script. The translate_off statement stops synthesis
translation of the generic statements. The following code
illustrates a module that employs these techniques.
WE
EN
RST
WEB
ENB
RSTB
CLKB
ADDRB[7:0]
DIB[15:0]
DOB[15:0]
DO[15:0]
CLK
ADDR[6:0], GND
DI[15:0]
ds022_036_121399
Figure 35: Single Port 128 x 32 RAM
Interleaving the memory space, setting the LSB of the
address bus of Port A to 1 (VCC), and the LSB of the
address bus of Port B to 0 (GND), allows a 32-bit wide sin-
gle port RAM to be created.
Table 17: RAM Initialization Properties
Property
INIT_00
INIT_01
INIT_02
INIT_03
INIT_04
INIT_05
INIT_06
INIT_07
INIT_08
INIT_09
INIT_0a
INIT_0b
INIT_0c
INIT_0d
INIT_0e
INIT_0f
Memory Cells
255 to 0
Creating Two Single-Port RAMs
511 to 256
The true dual-read/write port functionality of the block
SelectRAM+ memory allows a single RAM to be split into
two single port memories of 2K bits each as shown in
Figure 36.
767 to 512
1023 to 768
1279 to 1024
1535 to 1280
1791 to 2047
2047 to 1792
2303 to 2048
2559 to 2304
2815 to 2560
3071 to 2816
3327 to 3072
3583 to 3328
3839 to 3584
4095 to 3840
RAMB4_S4_S16
WE1
EN1
RST1
WEA
ENA
RSTA
CLKA
ADDRA[9:0]
DIA[3:0]
DOA[3:0]
DO1[3:0]
CLK1
V
, ADDR1[8:0]
DI1[3:0]
CC
WE2
EN2
RST2
CLK2
WEB
ENB
RSTB
CLKB
ADDRB[7:0]
DIB[15:0]
DOB[15:0]
DO2[15:0]
GND, ADDR2[6:0]
DI2[15:0]
ds022_037_121399
Figure 36: 512 x 4 RAM and 128 x 16 RAM
In this example, a 512K x 4 RAM (Port A) and a 128 x 16
RAM (Port B) are created out of a single block SelectRAM+.
The address space for the RAM is split by fixing the MSB of
Port A to 1 (VCC) for the upper 2K bits and the MSB of Port
B to 0 (GND) for the lower 2K bits.
Initialization in Verilog and Synopsys
The block SelectRAM+ structures can be initialized in Verilog
for both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the Verilog code uses a def-
param to pass the initialization. The Synopsys FPGA com-
piler does not presently support defparam. The initialization
values instead attach as attributes to the RAM by a built-in
Synopsys dc_script. The translate_off statement stops syn-
thesis translation of the defparam statements. The following
code illustrates a module that employs these techniques.
Block Memory Generation
The CoreGen program generates memory structures using
the block SelectRAM+ features. This program outputs
VHDL or Verilog simulation code templates and an EDIF file
for inclusion in a design.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
VHDL Initialization Example
library IEEE;
use IEEE.std_logic_1164.all;
entity MYMEM is
port (CLK, WE:in std_logic;
ADDR: in std_logic_vector(8 downto 0);
DIN: in std_logic_vector(7 downto 0);
DOUT: out std_logic_vector(7 downto 0));
end MYMEM;
architecture BEHAVE of MYMEM is
signal logic0, logic1: std_logic;
component RAMB4_S8
--synopsys translate_off
generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0a, INIT_0b, INIT_0c, INIT_0d, INIT_0e, INIT_0f : BIT_VECTOR(255
downto 0)
:= X"0000000000000000000000000000000000000000000000000000000000000000");
--synopsys translate_on
port (WE, EN, RST, CLK: in STD_LOGIC;
ADDR: in STD_LOGIC_VECTOR(8 downto 0);
DI: in STD_LOGIC_VECTOR(7 downto 0);
DO: out STD_LOGIC_VECTOR(7 downto 0));
end component;
--synopsys dc_script_begin
--set_attribute ram0 INIT_00
"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string
--set_attribute ram0 INIT_01
"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string
--synopsys dc_script_end
begin
logic0 <=’0’;
logic1 <=’1’;
ram0: RAMB4_S8
--synopsys translate_off
generic map (
INIT_00 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",
INIT_01 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210")
--synopsys translate_on
port map (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLK,ADDR=>ADDR, DI=>DIN, DO=>DOUT);
end BEHAVE;
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Module 2 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Verilog Initialization Example
module MYMEM (CLK, WE, ADDR, DIN, DOUT);
input CLK, WE;
input [8:0] ADDR;
input [7:0] DIN;
output [7:0] DOUT;
wire logic0, logic1;
//synopsys dc_script_begin
//set_attribute ram0 INIT_00
"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string
//set_attribute ram0 INIT_01
"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string
//synopsys dc_script_end
assign logic0 = 1’b0;
assign logic1 = 1’b1;
RAMB4_S8 ram0 (.WE(WE), .EN(logic1), .RST(logic0), .CLK(CLK), .ADDR(ADDR), .DI(DIN),
.DO(DOUT));
//synopsys translate_off
defparam ram0.INIT_00 =
256h’0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF;
defparam ram0.INIT_01 =
256h’FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210;
//synopsys translate_on
endmodule
Using SelectI/O
The Virtex-E FPGA series includes a highly configurable,
high-performance I/O resource, called SelectI/O™ to pro-
vide support for a wide variety of I/O standards. The
SelectI/O resource is a robust set of features including pro-
grammable control of output drive strength, slew rate, and
input delay and hold time. Taking advantage of the flexibility
and SelectI/O features and the design considerations
described in this document can improve and simplify sys-
tem level design.
Each SelectI/O block can support up to 20 I/O standards.
Supporting such a variety of I/O standards allows the sup-
port of a wide variety of applications, from general purpose
standard applications to high-speed low-voltage memory
busses.
SelectI/O blocks also provide selectable output drive
strengths and programmable slew rates for the LVTTL out-
put buffers, as well as an optional, programmable weak
pull-up, weak pull-down, or weak “keeper” circuit ideal for
use in external bussing applications.
Introduction
Each Input/Output Block (IOB) includes three registers, one
each for the input, output, and 3-state signals within the
IOB. These registers are optionally configurable as either a
D-type flip-flop or as a level sensitive latch.
As FPGAs continue to grow in size and capacity, the larger
and more complex systems designed for them demand an
increased variety of I/O standards. Furthermore, as system
clock speeds continue to increase, the need for high perfor-
mance I/O becomes more important.
The input buffer has an optional delay element used to guar-
antee a zero hold time requirement for input signals regis-
tered within the IOB.
While chip-to-chip delays have an increasingly substantial
impact on overall system speed, the task of achieving the
desired system performance becomes more difficult with
the proliferation of low-voltage I/O standards. SelectI/O, the
revolutionary input/output resources of Virtex-E devices,
resolve this potential problem by providing a highly config-
urable, high-performance alternative to the I/O resources of
more conventional programmable devices. Virtex-E SelectI/O
features combine the flexibility and time-to-market advan-
tages of programmable logic with the high performance pre-
viously available only with ASICs and custom ICs.
The Virtex-E SelectI/O features also provide dedicated
resources for input reference voltage (VREF) and output
source voltage (VCCO), along with a convenient banking
system that simplifies board design.
By taking advantage of the built-in features and wide variety
of I/O standards supported by the SelectI/O features, sys-
tem-level design and board design can be greatly simplified
and improved.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Fundamentals
Overview of Supported I/O Standards
Modern bus applications, pioneered by the largest and most
influential companies in the digital electronics industry, are
commonly introduced with a new I/O standard tailored spe-
cifically to the needs of that application. The bus I/O stan-
dards provide specifications to other vendors who create
products designed to interface with these applications.
Each standard often has its own specifications for current,
voltage, I/O buffering, and termination techniques.
This section provides a brief overview of the I/O standards
supported by all Virtex-E devices.
While most I/O standards specify a range of allowed volt-
ages, this document records typical voltage values only.
Detailed information on each specification can be found on
the Electronic Industry Alliance Jedec website at:
http://www.jedec.org
LVTTL — Low-Voltage TTL
The ability to provide the flexibility and time-to-market
advantages of programmable logic is increasingly depen-
dent on the capability of the programmable logic device to
support an ever increasing variety of I/O standards
The Low-Voltage TTL, or LVTTL standard is a general pur-
pose EIA/JESDSA standard for 3.3V applications that uses
an LVTTL input buffer and a Push-Pull output buffer. This
standard requires a 3.3V output source voltage (VCCO), but
does not require the use of a reference voltage (VREF) or a
termination voltage (VTT).
The SelectI/O resources feature highly configurable input
and output buffers which provide support for a wide variety
of I/O standards. As shown in Table 18, each buffer type can
support a variety of voltage requirements.
LVCMOS2 — Low-Voltage CMOS for 2.5 Volts
Table 18: Virtex-E Supported I/O Standards
The Low-Voltage CMOS for 2.5 Volts or lower, or LVCMOS2
standard is an extension of the LVCMOS standard (JESD
8.-5) used for general purpose 2.5V applications. This stan-
dard requires a 2.5V output source voltage (VCCO), but
does not require the use of a reference voltage (VREF) or a
board termination voltage (VTT).
Board
Termination
Output Input Input
VCCO VREF
Voltage
I/O Standard
LVTTL
VCCO
3.3
2.5
1.8
3.3
2.5
N/A
N/A
1.5
1.5
3.3
3.3
3.3
3.3
2.5
3.3
(VTT
N/A
N/A
N/A
)
3.3
2.5
N/A
N/A
N/A
1.50
1.25
0.80
1.0
LVCMOS18 — 1.8 V Low Voltage CMOS
LVCMOS2
LVCMOS18
SSTL3 I & II
SSTL2 I & II
GTL
This standard is an extension of the LVCMOS standard. It is
used in general purpose 1.8 V applications. The use of a
reference voltage (VREF) or a board termination voltage
(VTT) is not required.
1.8
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3
1.50
1.25
1.20
1.50
0.75
1.50
1.50
N/A
N/A
N/A
N/A
N/A
PCI — Peripheral Component Interface
The Peripheral Component Interface, or PCI standard spec-
ifies support for both 33 MHz and 66 MHz PCI bus applica-
tions. It uses a LVTTL input buffer and a Push-Pull output
buffer. This standard does not require the use of a reference
voltage (VREF) or a board termination voltage (VTT), how-
ever, it does require a 3.3V output source voltage (VCCO).
GTL+
HSTL I
0.75
0.90
1.50
1.32
N/A
N/A
N/A
N/A
GTL — Gunning Transceiver Logic Terminated
HSTL III & IV
CTT
The Gunning Transceiver Logic, or GTL standard is a
high-speed bus standard (JESD8.3) invented by Xerox. Xil-
inx has implemented the terminated variation for this stan-
dard. This standard requires a differential amplifier input
buffer and a Open Drain output buffer.
AGP-2X
PCI33_3
PCI66_3
BLVDS & LVDS
LVPECL
GTL+ — Gunning Transceiver Logic Plus
3.3
The Gunning Transceiver Logic Plus, or GTL+ standard is a
high-speed bus standard (JESD8.3) first used by the Pen-
tium Pro processor.
N/A
N/A
HSTL — High-Speed Transceiver Logic
The High-Speed Transceiver Logic, or HSTL standard is a
general purpose high-speed, 1.5V bus standard sponsored
by IBM (EIA/JESD 8-6). This standard has four variations or
classes. SelectI/O devices support Class I, III, and IV. This
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Virtex™-E 1.8 V Field Programmable Gate Arrays
standard requires a Differential Amplifier input buffer and a
Push-Pull output buffer.
Library Symbols
The Xilinx library includes an extensive list of symbols
designed to provide support for the variety of SelectI/O fea-
tures. Most of these symbols represent variations of the five
generic SelectI/O symbols.
SSTL3 — Stub Series Terminated Logic for 3.3V
The Stub Series Terminated Logic for 3.3V, or SSTL3 stan-
dard is a general purpose 3.3V memory bus standard also
sponsored by Hitachi and IBM (JESD8-8). This standard
has two classes, I and II. SelectI/O devices support both
classes for the SSTL3 standard. This standard requires a
Differential Amplifier input buffer and an Push-Pull output
buffer.
•
•
•
•
•
IBUF (input buffer)
IBUFG (global clock input buffer)
OBUF (output buffer)
OBUFT (3-state output buffer)
IOBUF (input/output buffer)
SSTL2 — Stub Series Terminated Logic for 2.5V
IBUF
The Stub Series Terminated Logic for 2.5V, or SSTL2 stan-
dard is a general purpose 2.5V memory bus standard spon-
sored by Hitachi and IBM (JESD8-9). This standard has two
classes, I and II. SelectI/O devices support both classes for
the SSTL2 standard. This standard requires a Differential
Amplifier input buffer and an Push-Pull output buffer.
Signals used as inputs to the Virtex-E device must source
an input buffer (IBUF) via an external input port. The generic
Virtex-E IBUF symbol appears in Figure 37. The extension
IBUF
I
O
CTT — Center Tap Terminated
The Center Tap Terminated, or CTT standard is a 3.3V
memory bus standard sponsored by Fujitsu (JESD8-4).
This standard requires a Differential Amplifier input buffer
and a Push-Pull output buffer.
x133_01_111699
Figure 37: Input Buffer (IBUF) Symbols
AGP-2X — Advanced Graphics Port
to the base name defines which I/O standard the IBUF
uses. The assumed standard is LVTTL when the generic
IBUF has no specified extension.
The Intel AGP standard is a 3.3V Advanced Graphics
Port-2X bus standard used with the Pentium II processor for
graphics applications. This standard requires a Push-Pull
output buffer and a Differential Amplifier input buffer.
The following list details the variations of the IBUF symbol:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IBUF
LVDS — Low Voltage Differential Signal
IBUF_LVCMOS2
IBUF_PCI33_3
IBUF_PCI66_3
IBUF_GTL
LVDS is a differential I/O standard. It requires that one data
bit is carried through two signal lines. As with all differential
signaling standards, LVDS has an inherent noise immunity
over single-ended I/O standards. The voltage swing
between two signal lines is approximately 350mV. The use
of a reference voltage (VREF) or a board termination voltage
(VTT) is not required. LVDS requires the use of two pins per
input or output. LVDS requires external resistor termination.
IBUF_GTLP
IBUF_HSTL_I
IBUF_HSTL_III
IBUF_HSTL_IV
IBUF_SSTL3_I
IBUF_SSTL3_II
IBUF_SSTL2_I
IBUF_SSTL2_II
IBUF_CTT
BLVDS — Bus LVDS
This standard allows for bidirectional LVDS communication
between two or more devices. The external resistor termi-
nation is different than the one for standard LVDS.
LVPECL — Low Voltage Positive Emitter Coupled
Logic
IBUF_AGP
IBUF_LVCMOS18
IBUF_LVDS
LVPECL is another differential I/O standard. It requires two
signal lines for transmitting one data bit. This standard
specifies two pins per input or output. The voltage swing
between these two signal lines is approximately 850 mV.
The use of a reference voltage (VREF) or a board termina-
tion voltage (VTT) is not required. The LVPECL standard
requires external resistor termination.
IBUF_LVPECL
When the IBUF symbol supports an I/O standard that
requires a VREF, the IBUF automatically configures as a dif-
ferential amplifier input buffer. The VREF voltage must be
supplied on the VREF pins. In the case of LVDS, LVPECL,
and BLVDS, VREF is not required.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
The voltage reference signal is “banked” within the Virtex-E
device on a half-edge basis such that for all packages there
are eight independent VREF banks internally. See Figure 38
for a representation of the Virtex-E I/O banks. Within each
bank approximately one of every six I/O pins is automati-
cally configured as a VREF input. After placing a differential
amplifier input signal within a given VREF bank, the same
external source must drive all I/O pins configured as a VREF
input.
CLKDLLHF, or BUFG symbol. The generic Virtex-E IBUFG
symbol appears in Figure 39.
IBUFG
I
O
x133_03_111699
Figure 39: Virtex-E Global Clock Input Buffer (IBUFG)
Symbol
IBUF placement restrictions require that any differential
amplifier input signals within a bank be of the same stan-
dard. How to specify a specific location for the IBUF via the
LOC property is described below. Table 19 summarizes the
Virtex-E input standards compatibility requirements.
The extension to the base name determines which I/O stan-
dard is used by the IBUFG. With no extension specified for
the generic IBUFG symbol, the assumed standard is
LVTTL.
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element by default activates to ensure a zero hold-time
requirement. The NODELAY=TRUE property overrides this
default.
The following list details variations of the IBUFG symbol.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IBUFG
IBUFG_LVCMOS2
IBUFG_PCI33_3
IBUFG_PCI66_3
IBUFG_GTL
When the IBUF does not drive a flip-flop within the IOB, the
delay element de-activates by default to provide higher per-
formance. To delay the input signal, activate the delay ele-
ment with the DELAY=TRUE property.
IBUFG_GTLP
IBUFG_HSTL_I
IBUFG_HSTL_III
IBUFG_HSTL_IV
IBUFG_SSTL3_I
IBUFG_SSTL3_II
IBUFG_SSTL2_I
IBUFG_SSTL2_II
IBUFG_CTT
Table 19: Xilinx Input Standards Compatibility
Requirements
Rule 1 Standards with the same input VCCO, output VCCO
,
and VREF can be placed within the same bank.
IBUFG_AGP
IBUFG_LVCMOS18
IBUFG_LVDS
Bank 0
Bank 1
GCLK3 GCLK2
IBUFG_LVPECL
When the IBUFG symbol supports an I/O standard that
requires a differential amplifier input, the IBUFG automati-
cally configures as a differential amplifier input buffer. The
low-voltage I/O standards with a differential amplifier input
Virtex-E
Device
require an external reference voltage input VREF
.
GCLK1 GCLK0
The voltage reference signal is “banked” within the Virtex-E
device on a half-edge basis such that for all packages there
are eight independent VREF banks internally. See Figure 38
for a representation of the Virtex-E I/O banks. Within each
bank approximately one of every six I/O pins is automati-
cally configured as a VREF input. After placing a differential
amplifier input signal within a given VREF bank, the same
external source must drive all I/O pins configured as a VREF
input.
Bank 5
Bank 4
ds022_42_012100
Figure 38: Virtex-E I/O Banks
IBUFG
Signals used as high fanout clock inputs to the Virtex-E
device should drive a global clock input buffer (IBUFG) via
an external input port in order to take advantage of one of
the four dedicated global clock distribution networks. The
output of the IBUFG symbol can drive only a CLKDLL,
IBUFG placement restrictions require any differential ampli-
fier input signals within a bank be of the same standard. The
LOC property can specify a location for the IBUFG.
As an added convenience, the BUFGP can be used to
instantiate a high fanout clock input. The BUFGP symbol
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Virtex™-E 1.8 V Field Programmable Gate Arrays
represents a combination of the LVTTL IBUFG and BUFG
symbols, such that the output of the BUFGP can connect
directly to the clock pins throughout the design.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
OBUF_PCI66_3
OBUF_GTL
OBUF_GTLP
Unlike previous architectures, the Virtex-E BUFGP symbol
can only be placed in a global clock pad location. The LOC
property can specify a location for the BUFGP.
OBUF_HSTL_I
OBUF_HSTL_III
OBUF_HSTL_IV
OBUF_SSTL3_I
OBUF_SSTL3_II
OBUF_SSTL2_I
OBUF_SSTL2_II
OBUF_CTT
OBUF
An OBUF must drive outputs through an external output
port. The generic output buffer (OBUF) symbol appears in
Figure 40.
The extension to the base name defines which I/O standard
the OBUF uses. With no extension specified for the generic
OBUF symbol, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
OBUF_AGP
OBUF_LVCMOS18
OBUF_LVDS
OBUF_LVPECL
OBUF
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS packages support four VCCO banks.
I
O
OBUF placement restrictions require that within a given
VCCO bank each OBUF share the same output source drive
voltage. Input buffers of any type and output buffers that do
not require VCCO can be placed within any VCCO bank.
Table 20 summarizes the Virtex-E output compatibility
requirements. The LOC property can specify a location for
the OBUF.
x133_04_111699
Figure 40: Virtex-E Output Buffer (OBUF) Symbol
The LVTTL OBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
LVTTL output buffers have selectable drive strengths.
The format for LVTTL OBUF symbol names is as follows:
Table 20: Output Standards Compatibility
Requirements
OBUF_<slew_rate>_<drive_strength>
Rule 1 Only outputs with standards that share compatible
VCCO can be used within the same bank.
where <slew_rate> is either F (Fast) or S (Slow), and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
Rule 2 There are no placement restrictions for outputs
with standards that do not require a VCCO
.
The following list details variations of the OBUF symbol.
VCCO
3.3
Compatible Standards
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
OBUF
LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL,
GTL+, PCI33_3, PCI66_3
OBUF_S_2
OBUF_S_4
OBUF_S_6
OBUF_S_8
OBUF_S_12
OBUF_S_16
OBUF_S_24
OBUF_F_2
OBUF_F_4
OBUF_F_6
OBUF_F_8
OBUF_F_12
OBUF_F_16
OBUF_F_24
OBUF_LVCMOS2
OBUF_PCI33_3
2.5
1.5
SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+
HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+
OBUFT
The generic 3-state output buffer OBUFT (see Figure 41)
typically implements 3-state outputs or bidirectional I/O.
The extension to the base name defines which I/O standard
OBUFT uses. With no extension specified for the generic
OBUFT symbol, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
The LVTTL OBUFT additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
LVTTL 3-state output buffers have selectable drive
strengths.
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four VCCO banks.
The format for LVTTL OBUFT symbol names is as follows:
OBUFT_<slew_rate>_<drive_strength>
The SelectI/O OBUFT placement restrictions require that
within a given VCCO bank each OBUFT share the same out-
put source drive voltage. Input buffers of any type and out-
put buffers that do not require VCCO can be placed within
the same VCCO bank.
where <slew_rate> is either F (Fast) or S (Slow), and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
The LOC property can specify a location for the OBUFT.
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak “keeper” circuit. Control this feature by adding the
appropriate symbol to the output net of the OBUFT (PUL-
LUP, PULLDOWN, or KEEPER).
OBUFT
T
O
I
The weak “keeper” circuit requires the input buffer within the
IOB to sample the I/O signal. So, OBUFTs programmed for
an I/O standard that requires a VREF have automatic place-
ment of a VREF in the bank with an OBUFT configured with
a weak “keeper” circuit. This restriction does not affect most
circuit design as applications using an OBUFT configured
with a weak “keeper” typically implement a bidirectional I/O.
In this case the IBUF (and the corresponding VREF) are
explicitly placed.
x133_05_111699
Figure 41: 3-State Output Buffer Symbol (OBUFT)
The following list details variations of the OBUFT symbol.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
OBUFT
OBUFT_S_2
OBUFT_S_4
OBUFT_S_6
The LOC property can specify a location for the OBUFT.
OBUFT_S_8
IOBUF
OBUFT_S_12
OBUFT_S_16
OBUFT_S_24
OBUFT_F_2
Use the IOBUF symbol for bidirectional signals that require
both an input buffer and a 3-state output buffer with an
active high 3-state pin. The generic input/output buffer
IOBUF appears in Figure 42.
OBUFT_F_4
The extension to the base name defines which I/O standard
the IOBUF uses. With no extension specified for the generic
IOBUF symbol, the assumed standard is LVTTL input buffer
and slew rate limited LVTTL with 12 mA drive strength for
the output buffer.
OBUFT_F_6
OBUFT_F_8
OBUFT_F_12
OBUFT_F_16
OBUFT_F_24
OBUFT_LVCMOS2
OBUFT_PCI33_3
OBUFT_PCI66_3
OBUFT_GTL
The LVTTL IOBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
LVTTL bidirectional buffers have selectable output drive
strengths.
OBUFT_GTLP
OBUFT_HSTL_I
OBUFT_HSTL_III
OBUFT_HSTL_IV
OBUFT_SSTL3_I
OBUFT_SSTL3_II
OBUFT_SSTL2_I
OBUFT_SSTL2_II
OBUFT_CTT
The format for LVTTL IOBUF symbol names is as follows:
IOBUF_<slew_rate>_<drive_strength>
where <slew_rate> is either F (Fast) or S (Slow), and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
OBUFT_AGP
OBUFT_LVCMOS18
OBUFT_LVDS
OBUFT_LVPECL
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Virtex™-E 1.8 V Field Programmable Gate Arrays
The voltage reference signal is “banked” within the Virtex-E
device on a half-edge basis such that for all packages there
are eight independent VREF banks internally. See Figure 38,
page 33 for a representation of the Virtex-E I/O banks.
Within each bank approximately one of every six I/O pins is
automatically configured as a VREF input. After placing a dif-
ferential amplifier input signal within a given VREF bank, the
same external source must drive all I/O pins configured as a
VREF input.
IOBUF
T
I
IO
O
x133_06_111699
IOBUF placement restrictions require any differential ampli-
fier input signals within a bank be of the same standard.
Figure 42: Input/Output Buffer Symbol (IOBUF)
The following list details variations of the IOBUF symbol.
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four VCCO banks.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IOBUF
Additional restrictions on the Virtex-E SelectI/O IOBUF
placement require that within a given VCCO bank each
IOBUF must share the same output source drive voltage.
Input buffers of any type and output buffers that do not
require VCCO can be placed within the same VCCO bank.
The LOC property can specify a location for the IOBUF.
IOBUF_S_2
IOBUF_S_4
IOBUF_S_6
IOBUF_S_8
IOBUF_S_12
IOBUF_S_16
IOBUF_S_24
IOBUF_F_2
An optional delay element is associated with the input path
in each IOBUF. When the IOBUF drives an input flip-flop
within the IOB, the delay element activates by default to
ensure a zero hold-time requirement. Override this default
with the NODELAY=TRUE property.
IOBUF_F_4
IOBUF_F_6
In the case when the IOBUF does not drive an input flip-flop
within the IOB, the delay element de-activates by default to
provide higher performance. To delay the input signal, acti-
vate the delay element with the DELAY=TRUE property.
IOBUF_F_8
IOBUF_F_12
IOBUF_F_16
IOBUF_F_24
IOBUF_LVCMOS2
IOBUF_PCI33_3
IOBUF_PCI66_3
IOBUF_GTL
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak “keeper” circuit. Control this feature by adding the
appropriate symbol to the output net of the IOBUF (PUL-
LUP, PULLDOWN, or KEEPER).
IOBUF_GTLP
IOBUF_HSTL_I
IOBUF_HSTL_III
IOBUF_HSTL_IV
IOBUF_SSTL3_I
IOBUF_SSTL3_II
IOBUF_SSTL2_I
IOBUF_SSTL2_II
IOBUF_CTT
SelectI/O Properties
Access to some of the SelectI/O features (for example, loca-
tion constraints, input delay, output drive strength, and slew
rate) is available through properties associated with these
features.
Input Delay Properties
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element activates by default to ensure a zero hold-time
requirement. Use the NODELAY=TRUE property to over-
ride this default.
IOBUF_AGP
IOBUF_LVCMOS18
IOBUF_LVDS
IOBUF_LVPECL
In the case when the IBUF does not drive a flip-flop within
the IOB, the delay element by default de-activates to pro-
vide higher performance. To delay the input signal, activate
the delay element with the DELAY=TRUE property.
When the IOBUF symbol used supports an I/O standard
that requires a differential amplifier input, the IOBUF auto-
matically configures with a differential amplifier input buffer.
The low-voltage I/O standards with a differential amplifier
input require an external reference voltage input VREF
.
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
IOB Flip-Flop/Latch Property
Design Considerations
The Virtex-E series I/O Block (IOB) includes an optional
register on the input path, an optional register on the output
path, and an optional register on the 3-state control pin. The
design implementation software automatically takes advan-
tage of these registers when the following option for the Map
program is specified.
Reference Voltage (V
) Pins
REF
Low-voltage I/O standards with a differential amplifier input
buffer require an input reference voltage (VREF). Provide the
VREF as an external signal to the device.
The voltage reference signal is “banked” within the device on
a half-edge basis such that for all packages there are eight
independent VREF banks internally. See Figure 38 for a rep-
resentation of the Virtex-E I/O banks. Within each bank
approximately one of every six I/O pins is automatically con-
figured as a VREF input. After placing a differential amplifier
input signal within a given VREF bank, the same external
source must drive all I/O pins configured as a VREF input.
map –pr b <filename>
Alternatively, the IOB = TRUE property can be placed on a
register to force the mapper to place the register in an IOB.
Location Constraints
Specify the location of each SelectI/O symbol with the loca-
tion constraint LOC attached to the SelectI/O symbol. The
external port identifier indicates the value of the location
constrain. The format of the port identifier depends on the
package chosen for the specific design.
Within each VREF bank, any input buffers that require a
VREF signal must be of the same type. Output buffers of any
type and input buffers can be placed without requiring a ref-
erence voltage within the same VREF bank.
The LOC properties use the following form:
LOC=A42
Output Drive Source Voltage (V
) Pins
CCO
Many of the low voltage I/O standards supported by
SelectI/O devices require a different output drive source
voltage (VCCO). As a result each device can often have to
support multiple output drive source voltages.
LOC=P37
Output Slew Rate Property
As mentioned above, a variety of symbol names provide the
option of choosing the desired slew rate for the output buff-
ers. In the case of the LVTTL output buffers (OBUF, OBUFT,
and IOBUF), slew rate control can be alternatively pro-
gramed with the SLEW= property. By default, the slew rate
for each output buffer is reduced to minimize power bus
transients when switching non-critical signals. The SLEW=
property has one of the two following values.
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four VCCO banks.
Output buffers within a given VCCO bank must share the
same output drive source voltage. Input buffers for LVTTL,
LVCMOS2, LVCMOS18, PCI33_3, and PCI 66_3 use the
VCCO voltage for Input VCCO voltage.
Transmission Line Effects
SLEW=SLOW
The delay of an electrical signal along a wire is dominated
by the rise and fall times when the signal travels a short dis-
tance. Transmission line delays vary with inductance and
capacitance, but a well-designed board can experience
delays of approximately 180 ps per inch.
SLEW=FAST
Output Drive Strength Property
The desired output drive strength can be additionally speci-
fied by choosing the appropriate library symbol. The Xilinx
library also provides an alternative method for specifying
this feature. For the LVTTL output buffers (OBUF, OBUFT,
and IOBUF, the desired drive strength can be specified with
the DRIVE= property. This property could have one of the
following seven values.
Transmission line effects, or reflections, typically start at
1.5" for fast (1.5 ns) rise and fall times. Poor (or non-exis-
tent) termination or changes in the transmission line imped-
ance cause these reflections and can cause additional
delay in longer traces. As system speeds continue to
increase, the effect of I/O delays can become a limiting fac-
tor and therefore transmission line termination becomes
increasingly more important.
DRIVE=2
DRIVE=4
DRIVE=6
Termination Techniques
DRIVE=8
A variety of termination techniques reduce the impact of
transmission line effects.
DRIVE=12 (Default)
DRIVE=16
DRIVE=24
The following are output termination techniques:
•
•
•
•
None
Series
Parallel (Shunt)
Series and Parallel (Series-Shunt)
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Module 2 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Input termination techniques include the following.
Simultaneous Switching Guidelines
•
•
None
Ground bounce can occur with high-speed digital ICs when
multiple outputs change states simultaneously, causing
undesired transient behavior on an output, or in the internal
logic. This problem is also referred to as the Simultaneous
Switching Output (SSO) problem.
Parallel (Shunt)
These termination techniques can be applied in any combi-
nation. A generic example of each combination of termina-
tion methods appears in Figure 43.
Ground bounce is primarily due to current changes in the
combined inductance of ground pins, bond wires, and
ground metallization. The IC internal ground level deviates
from the external system ground level for a short duration (a
few nanoseconds) after multiple outputs change state
simultaneously.
Double Parallel Terminated
Unterminated
Z=50
VTT
VTT
Z=50
VREF
Unterminated Output Driving
a Parallel Terminated Input
Series Terminated Output Driving
a Parallel Terminated Input
VTT
VTT
Ground bounce affects stable Low outputs and all inputs
because they interpret the incoming signal by comparing it
to the internal ground. If the ground bounce amplitude
exceeds the actual instantaneous noise margin, then a
non-changing input can be interpreted as a short pulse with
a polarity opposite to the ground bounce.
Z=50
VREF
Z=50
VREF
Series-Parallel Terminated Output
Driving a Parallel Terminated Input
VTT
VTT
Series Terminated Output
Z=50
VREF
Z=50
VREF
x133_07_111699
Table 21 provides guidelines for the maximum number of
simultaneously switching outputs allowed per output
power/ground pair to avoid the effects of ground bounce. See
Table 22 for the number of effective output power/ground pairs
for each Virtex-E device and package combination.
Figure 43: Overview of Standard Input and Output
Termination Methods
Table 21: Guidelines for Max Number of Simultaneously Switching Outputs per Power/Ground Pair
Package
Standard
LVTTL Slow Slew Rate, 2 mA drive
BGA, CS, FGA
HQ
49
31
22
17
12
10
7
PQ, TQ
68
41
29
22
17
14
9
36
20
15
12
9
LVTTL Slow Slew Rate, 4 mA drive
LVTTL Slow Slew Rate, 6 mA drive
LVTTL Slow Slew Rate, 8 mA drive
LVTTL Slow Slew Rate, 12 mA drive
LVTTL Slow Slew Rate, 16 mA drive
LVTTL Slow Slew Rate, 24 mA drive
LVTTL Fast Slew Rate, 2 mA drive
LVTTL Fast Slew Rate, 4 mA drive
LVTTL Fast Slew Rate, 6 mA drive
LVTTL Fast Slew Rate, 8 mA drive
LVTTL Fast Slew Rate, 12 mA drive
LVTTL Fast Slew Rate, 16 mA drive
LVTTL Fast Slew Rate, 24 mA drive
LVCMOS2
7
5
40
24
17
13
10
8
29
18
13
10
7
21
12
9
7
5
6
4
5
4
3
10
8
7
5
PCI
6
4
GTL
4
4
4
GTL+
4
4
4
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DS022-2 (v2.2) July 23, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 21: Guidelines for Max Number of Simultaneously Switching Outputs per Power/Ground Pair (Continued)
Package
Standard
BGA, CS, FGA
HQ
13
7
PQ, TQ
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
CTT
18
9
9
5
3
8
5
6
4
7
5
5
4
15
10
11
7
11
7
8
5
14
9
10
7
AGP
Note: This analysis assumes a 35 pF load for each output.
Table 22: Virtex-E Equivalent Power/Ground Pairs
Pkg/Part
CS144
PQ240
HQ240
BG352
BG432
BG560
FG256(1)
FG456
FG676
FG680(2)
FG860
FG900
FG1156
XCV100E XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E
12
20
12
20
20
20
20
20
56
20
20
32
32
32
40
40
40
40
58
60
24
40
24
40
54
56
46
56
58
58
96
56
60
56
64
56
60
104
120
Notes:
1. Virtex-E devices in FG256 packages have more VCCO than Virtex series devices.
2. FG680 numbers are preliminary.
DS022-2 (v2.2) July 23, 2001
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Virtex™-E 1.8 V Field Programmable Gate Arrays
GTL+
Application Examples
A sample circuit illustrating a valid termination technique for
GTL+ appears in Figure 45. DC voltage specifications
appear in Table 24.
Creating a design with the SelectI/O features requires the
instantiation of the desired library symbol within the design
code. At the board level, designers need to know the termi-
nation techniques required for each I/O standard.
GTL+
This section describes some common application examples
illustrating the termination techniques recommended by
each of the standards supported by the SelectI/O features.
= 1.5V
= 1.5V
VTT
VTT
50Ω
= N/A
50Ω
V
CCO
Z = 50
Termination Examples
VREF = 1.0V
Figure 45: Terminated GTL+
Table 24: GTL+ Voltage Specifications
Circuit examples involving typical termination techniques for
each of the SelectI/O standards follow. For a full range of
accepted values for the DC voltage specifications for each
standard, refer to the table associated with each figure.
x133_09_012400
The resistors used in each termination technique example
and the transmission lines depicted represent board level
components and are not meant to represent components
on the device.
Parameter
Min
Typ
-
Max
VCCO
REF = N VTT
VTT
-
0.88
1.35
0.98
-
-
1.12
1.65
-
GTL
1
V
1.0
1.5
1.1
0.9
-
A sample circuit illustrating a valid termination technique for
GTL is shown in Figure 44.
V
IH = VREF + 0.1
VIL = VREF – 0.1
1.02
-
GTL
VOH
VOL
-
V
TT = 1.2V VTT = 1.2V
0.3
-
0.45
-
0.6
-
50Ω
50Ω
Z = 50
VCCO = N/A
I
I
I
OH at VOH (mA)
VREF = 0.8V
OLat VOL (mA) at 0.6V
OLat VOL (mA) at 0.3V
36
-
-
-
x133_08_111699
-
48
Figure 44: Terminated GTL
Notes:
1. N must be greater than or equal to 0.653 and less than or
equal to 0.68.
Table 23 lists DC voltage specifications.
Table 23: GTL Voltage Specifications
Parameter
Min
Typ
N/A
0.8
1.2
0.85
0.75
-
Max
VCCO
-
-
0.86
1.26
-
1
V
REF = N VTT
0.74
VTT
1.14
V
IH = VREF + 0.05
0.79
VIL = VREF – 0.05
-
-
0.81
-
VOH
VOL
-
0.2
-
0.4
-
I
I
I
OH at VOH(mA)
-
OLat VOL(mA) at 0.4V
OLat VOL(mA) at 0.2V
32
-
-
-
-
40
Notes:
1. N must be greater than or equal to 0.653 and less than or
equal to 0.68.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
HSTL
HSTL Class III
A sample circuit illustrating a valid termination technique for
HSTL_I appears in Figure 46. A sample circuit illustrating a
valid termination technique for HSTL_III appears in
Figure 47.
VTT= 1.5V
VCCO = 1.5V
50Ω
Z = 50
Table 25: HSTL Class I Voltage Specification
VREF = 0.9V
Parameter
VCCO
Min
Typ
Max
x133_11_111699
1.40
1.50
1.60
Figure 47: Terminated HSTL Class III
VREF
VTT
VIH
0.68
0.75
0.90
A sample circuit illustrating a valid termination technique for
HSTL_IV appears in Figure 48.
-
VCCO 0.5
-
VREF + 0.1
-
-
-
-
-
Table 27: HSTL Class IV Voltage Specification
VIL
VREF – 0.1
Parameter
VCCO
Min
Typ
Max
VOH
VOL
VCCO – 0.4
-
0.4
-
1.40
1.50
1.60
VREF
VTT
VIH
-
0.90
-
I
OH at VOH (mA)
OLat VOL (mA)
8
8
-
-
-
VCCO
-
I
-
VREF + 0.1
-
-
-
-
-
-
-
VIL
-
VREF – 0.1
HSTL Class I
VCCO = 1.5V
VOH
VOL
VCCO – 0.4
-
0.4
-
-
VTT= 0.75V
I
OH at VOH (mA)
OLat VOL (mA)
8
50Ω
Z = 50
I
48
-
VREF = 0.75V
Figure 46: Terminated HSTL Class I
Table 26: HSTL Class III Voltage Specification
Note: Per EIA/JESD8-6, “The value of VREF is to be selected
by the user to provide optimum noise margin in the use
conditions specified by the user.
x133_10_111699
HSTL Class IV
Parameter
VCCO
Min
Typ
Max
V
= 1.5V V = 1.5V
TT
TT
V
= 1.5V
1.40
1.50
1.60
CCO
50Ω
50Ω
(1)
VREF
VTT
VIH
-
0.90
-
Z = 50
-
VCCO
-
V
= 0.9V
REF
x133_12_111699
VREF + 0.1
-
-
-
-
-
-
-
Figure 48: Terminated HSTL Class IV
VIL
-
VREF – 0.1
VOH
VOL
VCCO – 0.4
-
0.4
-
-
I
OH at VOH (mA)
OLat VOL (mA)
8
I
24
-
Note: Per EIA/JESD8-6, “The value of VREF is to be selected
by the user to provide optimum noise margin in the use
conditions specified by the user.”
DS022-2 (v2.2) July 23, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
SSTL3_I
Table 29: SSTL3_II Voltage Specifications
A sample circuit illustrating a valid termination technique for
SSTL3_I appears in Figure 49. DC voltage specifications
appear in Table 28.
Parameter
Min
3.0
1.3
1.3
1.5
0.3(2)
2.1
-
Typ
3.3
1.5
1.5
1.7
1.3
-
Max
3.6
1.7
1.7
3.9(1)
1.5
-
VCCO
V
V
V
REF = 0.45 VCCO
TT = VREF
SSTL3 Class I
V
= 1.5V
TT
V
= 3.3V
CCO
IH = VREF + 0.2
50Ω
25Ω
VIL= VREF – 0.2
Z = 50
V
= 1.5V
REF
VOH = VREF + 0.8
x133_13_111699
V
OL= VREF – 0.8
-
0.9
-
Figure 49: Terminated SSTL3 Class I
I
OH at VOH (mA)
OLat VOL (mA)
16
-
I
16
-
-
Table 28: SSTL3_I Voltage Specifications
Notes:
Parameter
Min
3.0
1.3
1.3
1.5
0.3(2)
1.9
-
Typ
3.3
1.5
1.5
1.7
1.3
-
Max
3.6
1.7
1.7
3.9(1)
1.5
-
1. VIH maximum is VCCO + 0.3
2. VIL minimum does not conform to the formula
VCCO
V
V
V
REF = 0.45 VCCO
SSTL2_I
TT = VREF
A sample circuit illustrating a valid termination technique for
SSTL2_I appears in Figure 51. DC voltage specifications
appear in Table 30.
IH = VREF + 0.2
VIL = VREF – 0.2
OH = VREF + 0.6
OL = VREF – 0.6
SSTL2 Class I
V
V
= 1.25V
TT
V
= 2.5V
V
-
1.1
-
CCO
50Ω
I
OH at VOH (mA)
OLat VOL (mA)
8
-
25Ω
Z = 50
I
8
-
-
V
= 1.25V
REF
Notes:
xap133_15_011000
1. VIH maximum is VCCO + 0.3
2. VIL minimum does not conform to the formula
Figure 51: Terminated SSTL2 Class I
SSTL3_II
Table 30: SSTL2_I Voltage Specifications
A sample circuit illustrating a valid termination technique for
SSTL3_II appears in Figure 50. DC voltage specifications
appear in Table 29.
Parameter
Min
2.3
Typ
2.5
1.25
1.25
1.43
1.07
-
Max
2.7
1.35
1.39
3.0(2)
1.17
-
VCCO
VREF = 0.5 VCCO
1.15
1.11
1.33
0.3(3)
1.76
-
V
TT = VREF + N(1)
IH = VREF + 0.18
SSTL3 Class II
VTT= 1.5V VTT= 1.5V
VCCO = 3.3V
V
VIL = VREF – 0.18
50Ω
50Ω
25Ω
Z = 50
V
OH = VREF + 0.61
OL= VREF – 0.61
VREF = 1.5V
V
-
0.74
-
x133_14_111699
IOH at VOH (mA)
OLat VOL (mA)
Notes:
7.6
-
Figure 50: Terminated SSTL3 Class II
I
7.6
-
-
1. N must be greater than or equal to -0.04 and less than or
equal to 0.04.
2. VIH maximum is VCCO + 0.3.
3. VIL minimum does not conform to the formula.
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
SSTL2_II
Table 32: CTT Voltage Specifications
A sample circuit illustrating a valid termination technique for
SSTL2_II appears in Figure 52. DC voltage specifications
appear in Table 31.
Parameter
Min
2.05(1)
1.35
1.35
1.55
-
Typ
3.3
1.5
1.5
1.7
1.3
1.9
1.1
-
Max
3.6
1.65
1.65
-
VCCO
VREF
VTT
SSTL2 Class II
VTT= 1.25V VTT= 1.25V
VCCO = 2.5V
VIH = VREF + 0.2
VIL = VREF – 0.2
VOH = VREF + 0.4
50Ω
50Ω
25Ω
1.45
-
Z = 50
VREF = 1.25V
1.75
-
x133_16_111699
VOL= VREF – 0.4
1.25
-
Figure 52: Terminated SSTL2 Class II
IOH at VOH (mA)
IOLat VOL (mA)
Notes:
8
Table 31: SSTL2_II Voltage Specifications
8
-
-
Parameter
Min
2.3
Typ
2.5
1.25
1.25
1.43
1.07
-
Max
2.7
1.35
1.39
3.0(2)
1.17
-
1. Timing delays are calculated based on VCCO min of 3.0V.
VCCO
V
V
V
REF = 0.5 VCCO
TT = VREF + N(1)
IH = VREF + 0.18
1.15
1.11
1.33
0.3(3)
1.95
-
PCI33_3 & PCI66_3
PCI33_3 or PCI66_3 require no termination. DC voltage
specifications appear in Table 33.
VIL = VREF – 0.18
OH = VREF + 0.8
OL = VREF – 0.8
Table 33: PCI33_3 and PCI66_3 Voltage Specifications
V
Parameter
Min
3.0
-
Typ
Max
V
-
0.55
-
VCCO
VREF
VTT
3.3
3.6
I
OH at VOH (mA)
OLat VOL (mA)
15.2
15.2
-
-
-
-
-
I
-
-
-
Notes:
1. N must be greater than or equal to -0.04 and less than or
equal to 0.04.
2. VIH maximum is VCCO + 0.3.
V
IH = 0.5 VCCO
1.5
0.5
2.7
-
1.65 VCCO + 0.5
VIL = 0.3 VCCO
0.99
1.08
3. VIL minimum does not conform to the formula.
V
OH = 0.9 VCCO
OL= 0.1 VCCO
-
-
-
-
-
V
0.36
CTT
A sample circuit illustrating a valid termination technique for
CTT appear in Figure 53. DC voltage specifications appear
in Table 32.
IOH at VOH (mA)
OLat VOL (mA)
Notes:
Note 1
Note 1
-
-
I
1. Tested according to the relevant specification.
CTT
VTT = 1.5V
VCCO = 3.3V
50Ω
Z = 50
VREF= 1.5V
x133_17_111699
Figure 53: Terminated CTT
DS022-2 (v2.2) July 23, 2001
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Virtex™-E 1.8 V Field Programmable Gate Arrays
LVTTL
LVCMOS18
LVTTL requires no termination. DC voltage specifications
appears in Table 34.
LVCMOS18 does not require termination. Table 36 lists DC
voltage specifications.
Table 34: LVTTL Voltage Specifications
Table 36: LVCMOS18 Voltage Specifications
Parameter
Min
3.0
-
Typ
Max
Parameter
VCCO
Min
Typ
Max
VCCO
VREF
VTT
3.3
3.6
1.70
1.80
1.90
-
-
-
-
-
-
-
-
-
-
VREF
VTT
VIH
-
-
-
-
-
-
-
-
-
-
-
-
-
VIH
2.0
0.5
2.4
-
3.6
0.8
-
0.7 x VCCO
1.95
VIL
VIL
– 0.5
0.2 x VCCO
VOH
VOL
VOH
VOL
VCCO – 0.4
-
0.4
-
0.4
-
-
–8
8
I
OH at VOH (mA)
OLat VOL (mA)
24
24
I
OH at VOH (mA)
OLat VOL (mA)
I
-
I
-
Notes:
1. Note: VOLand VOH for lower drive currents sample tested.
AGP-2X
The specification for the AGP-2X standard does not docu-
ment a recommended termination technique. DC voltage
specifications appear in Table 37.
LVCMOS2
LVCMOS2 requires no termination. DC voltage specifica-
tions appear in Table 35.
Table 37: AGP-2X Voltage Specifications
Parameter
Min
3.0
Typ
3.3
1.32
-
Max
Table 35: LVCMOS2 Voltage Specifications
VCCO
3.6
Parameter
Min
2.3
-
Typ
Max
(1)
V
REF = N VCCO
1.17
-
1.48
VCCO
VREF
VTT
2.5
2.7
VTT
-
-
-
-
-
-
-
-
-
-
-
V
IH = VREF + 0.2
1.37
-
1.52
1.12
3.0
0.33
-
-
-
VIL = VREF – 0.2
1.28
VIH
1.7
0.5
1.9
-
3.6
0.7
-
V
OH = 0.9 VCCO
OL = 0.1 VCCO
2.7
-
VIL
V
-
0.36
VOH
VOL
I
OH at VOH (mA)
OLat VOL (mA)
Note 2
Note 2
-
-
0.4
-
I
-
I
OH at VOH (mA)
OLat VOL (mA)
12
12
Notes:
I
-
1. N must be greater than or equal to 0.39 and less than or
equal to 0.41.
2. Tested according to the relevant specification.
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
LVDS
LVPECL
Depending on whether the device is transmitting or receiv-
ing an LVPECL signal, two different circuits are used for
LVPECL termination. A sample circuit illustrating a valid ter-
mination technique for transmitting LVPECL signals
appears in Figure 56. A sample circuit illustrating a valid ter-
mination for receiving LVPECL signals appears in
Figure 57. Table 39 lists DC voltage specifications. Further
information on the specific termination resistor packs shown
can be found on Table 40.
Depending on whether the device is transmitting an LVDS
signal or receiving an LVDS signal, there are two different
circuits used for LVDS termination. A sample circuit illustrat-
ing a valid termination technique for transmitting LVDS sig-
nals appears in Figure 54. A sample circuit illustrating a
valid termination for receiving LVDS signals appears in
Figure 55. Table 38 lists DC voltage specifications. Further
information on the specific termination resistor packs shown
can be found on Table 40.
Table 39: LVPECL Voltage Specifications
1/4 of Bourns
Part Number
Parameter
VCCO
Min
3.0
-
Typ
Max
3.6
-
Virtex-E
CAT16-LV4F12
FPGA
RS
Z
Z
= 50Ω
= 50Ω
0
0
Q
3.3
to LVDS Receiver
to LVDS Receiver
2.5V
165
R
VREF
VTT
-
-
-
-
-
-
DIV
140
DATA
Transmit
RS
-
-
Q
165
V
CCO = 2.5V
LVDS
Output
VIH
1.49
0.86
1.8
-
2.72
2.125
-
x133_19_122799
VIL
Figure 54: Transmitting LVDS Signal Circuit
VOH
VOL
1.57
VIRTEX-E
FPGA
Notes:
Z
Z
= 50Ω
= 50Ω
0
0
LVDS_IN
Q
Q
1. For more detailed information, see LVPECL DC
+
–
from
LVDS
Driver
Specifications
R
T
100Ω
DATA
Receive
1/4 of Bourns
Part Number
CAT16-PC4F12
LVDS_IN
Virtex-E
FPGA
RS
Z
Z
= 50Ω
= 50Ω
0
0
LVPECL_OUT
LVPECL_OUT
Q
Q
x133_29_122799
to LVPECL Receiver
3.3V
100
R
DIV
187
DATA
Figure 55: Receiving LVDS Signal Circuit
Table 38: LVDS Voltage Specifications
Transmit
RS
to LVPECL Receiver
100
Parameter
VCCO
Min
2.375
0.2
Typ
2.5
1.25
1.25
0.35
0.35
-
Max
2.625
2.2
x133_20_122799
Figure 56: Transmitting LVPECL Signal Circuit
(2)
VICM
VIRTEX-E
FPGA
(1)
Z
Z
= 50Ω
= 50Ω
0
0
VOCM
1.125
0.1
1.375
-
Q
LVPECL_IN
+
–
(1)
from
LVPECL
Driver
R
T
100Ω
VIDIFF
DATA
Receive
(1)
VODIFF
0.25
1.25
-
0.45
-
Q
LVPECL_IN
(1)
VOH
x133_21_122799
(1)
VOL
-
1.25
Figure 57: Receiving LVPECL Signal Circuit
Notes:
1. Measured with a 100 resistor across Q and Q.
2. Measured with a differential input voltage = / 350 mV.
DS022-2 (v2.2) July 23, 2001
Preliminary Product Specification
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Module 2 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Termination Resistor Packs
Creating LVDS Global Clock Input Buffers
Resistor packs are available with the values and the config-
uration required for LVDS and LVPECL termination from
Bourns, Inc., as listed in Table. For pricing and availability,
please contact Bourns directly at http://www.bourns.com.
Global clock input buffers can be combined with adjacent
IOBs to form LVDS clock input buffers. P-side is the GCLK-
PAD location; N-side is the adjacent IO_LVDS_DLL site.
Table 41: Global Clock Input Buffer Pair Locations
Table 40: Bourns LVDS/LVPECL Resistor Packs
GCLK 3
GCLK 2
GCLK 1
GCLK 0
Term.
for:
Pairs/
Pack Pins
Pkg
P
N
P
N
P
N
P
N
Part Number
CAT16 LV2F6
CAT16 LV4F12
CAT16 PC2F6
CAT16 PC4F12
CAT16 PT2F2
CAT16 PT4F4
I/O Standard
LVDS
CS144
A6
C6
A7
B7
M7
M6
K7
N8
Driver
Driver
Driver
Driver
2
4
2
4
2
4
8
16
8
PQ240 P213 P215 P210 P209 P89
HQ240 P213 P215 P210 P209 P89
P87
P87
P92
P92
P93
P93
LVDS
LVPECL
LVPECL
BG352 D14
BG432 D17
BG560 A17
A15
C17
C18
A7
B14 A13 AF14 AD14 AE13 AC13
A16 B16 AK16 AL17 AL16 AH15
D17 E17 AJ17 AM18 AL17 AM17
16
8
LVDS/LVPECL Receiver
LVDS/LVPECL Receiver
16
FG256
B8
C9
A8
R8
Yll
T8
N8
N9
FG456 C11
FG676 E13
FG680 A20
FG860 C22
FG900 C15
FG1156 E17
B11
B13
C22
A22
A15
C17
A11 D11
AA11
W12
U12
LVDS Design Guide
C13 F14 AB13 AF13 AA14 AC14
D21 A19 AU22 AT22 AW19 AT21
B22 D22 AY22 AW21 BA22 AW20
E15 E16 AK16 AH16 AJ16 AF16
The SelectI/O library elements have been expanded for Vir-
tex-E devices to include new LVDS variants. At this time all
of the cells might not be included in the Synthesis libraries.
The 2.1i-Service Pack 2 update for Alliance and Foundation
software includes these cells in the VHDL and Verilog librar-
ies. It is necessary to combine these cells to create the
P-side (positive) and N-side (negative) as described in the
input, output, 3-state and bidirectional sections.
D17
J18
Al19
AL17 AH18 AM18
HDL Instantiation
IBUF_LVDS
OBUF_LVDS
IOBUF_LVDS
T
Only one global clock input buffer is required to be instanti-
ated in the design and placed on the correct GCLKPAD
location. The N-side of the buffer is reserved and no other
IOB is allowed to be placed on this location.
I
O
I
O
I
IO
IBUFG_LVDS
OBUFT_LVDS
T
O
In the physical device, a configuration option is enabled that
routes the pad wire to the differential input buffer located in
the GCLKIOB. The output of this buffer then drives the out-
put of the GCLKIOB cell. In EPIC it appears that the second
buffer is unused. Any attempt to use this location for another
purpose leads to a DRC error in the software.
I
O
I
O
x133_22_122299
Figure 58: LVDS elements
VHDL Instantiation
gclk0_p : IBUFG_LVDS port map
(I=>clk_external, O=>clk_internal);
Verilog Instantiation
IBUFG_LVDS gclk0_p (.I(clk_external),
.O(clk_internal));
Location constraints
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the .ucf or .ncf file.
NET clk_external LOC = GCLKPAD3;
GCLKPAD3 can also be replaced with the package pin
name such as D17 for the BG432 package.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Verilog Instantiation
Optional N-side
IBUF_LVDS data0_p (.I(data[0]),
.O(data_int[0]));
Some designers might prefer to also instantiate the N-side
buffer for the global clock buffer. This allows the top-level net
list to include net connections for both PCB layout and sys-
tem-level integration. In this case, only the output P-side
IBUFG connection has a net connected to it. Since the
N-side IBUFG does not have a connection in the EDIF net
list, it is trimmed from the design in MAP.
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the input buffers this can be done with the following con-
straint in the .ucf or .ncf file.
NET data<0> LOC = D28; # IO_L0P
VHDL Instantiation
Optional N-side
gclk0_p : IBUFG_LVDS port map
(I=>clk_p_external, O=>clk_internal);
Some designers might prefer to also instantiate the N-side
buffer for the input buffer. This allows the top-level net list to
include net connections for both PCB layout and sys-
tem-level integration. In this case, only the output P-side
IBUF connection has a net connected to it. Since the N-side
IBUF does not have a connection in the EDIF net list, it is
trimmed from the design in MAP.
gclk0_n : IBUFG_LVDS port map
(I=>clk_n_external, O=>clk_internal);
Verilog Instantiation
IBUFG_LVDS gclk0_p (.I(clk_p_external),
.O(clk_internal));
VHDL Instantiation
IBUFG_LVDS gclk0_n (.I(clk_n_external),
.O(clk_internal));
data0_p : IBUF_LVDS port map
(I=>data_p(0), O=>data_int(0));
Location Constraints
data0_n : IBUF_LVDS port map
(I=>data_n(0), O=>open);
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the .ucf or .ncf file.
Verilog Instantiation
IBUF_LVDS data0_p (.I(data_p[0]),
.O(data_int[0]));
NET clk_p_external LOC = GCLKPAD3;
NET clk_n_external LOC = C17;
IBUF_LVDS data0_n (.I(data_n[0]), .O());
GCLKPAD3 can also be replaced with the package pin
name, such as D17 for the BG432 package.
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the .ucf or .ncf file.
Creating LVDS Input Buffers
An LVDS input buffer can be placed in a wide number of IOB
locations. The exact location is dependent on the package
that is used. The Virtex-E package information lists the pos-
sible locations as IO_L#P for the P-side and IO_L#N for the
N-side where # is the pair number.
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Adding an Input Register
HDL Instantiation
All LVDS buffers can have an input register in the IOB. The
input register is in the P-side IOB only. All the normal IOB
register options are available (FD, FDE, FDC, FDCE, FDP,
FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE,
LDP, LDPE). The register elements can be inferred or
explicitly instantiated in the HDL code.
Only one input buffer is required to be instantiated in the
design and placed on the correct IO_L#P location. The
N-side of the buffer is reserved and no other IOB is allowed
to be placed on this location. In the physical device, a con-
figuration option is enabled that routes the pad wire from the
IO_L#N IOB to the differential input buffer located in the
IO_L#P IOB. The output of this buffer then drives the output
of the IO_L#P cell or the input register in the IO_L#P IOB. In
EPIC it appears that the second buffer is unused. Any
attempt to use this location for another purpose leads to a
DRC error in the software.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs.
To improve design coding times VHDL and Verilog synthesis
macro libraries available to explicitly create these structures.
The input library macros are listed in Table 42. The I and IB
inputs to the macros are the external net connections.
VHDL Instantiation
data0_p : IBUF_LVDS port map (I=>data(0),
O=>data_int(0));
DS022-2 (v2.2) July 23, 2001
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Verilog Instantiation
Table 42: Input Library Macros
OBUF_LVDS data0_p
.O(data_p[0]));
(.I(data_int[0]),
Name
Inputs
I, IB, C
Outputs
IBUFDS_FD_LVDS
IBUFDS_FDE_LVDS
IBUFDS_FDC_LVDS
IBUFDS_FDCE_LVDS
IBUFDS_FDP_LVDS
IBUFDS_FDPE_LVDS
IBUFDS_FDR_LVDS
IBUFDS_FDRE_LVDS
IBUFDS_FDS_LVDS
IBUFDS_FDSE_LVDS
IBUFDS_LD_LVDS
IBUFDS_LDE_LVDS
IBUFDS_LDC_LVDS
IBUFDS_LDCE_LVDS
IBUFDS_LDP_LVDS
IBUFDS_LDPE_LVDS
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
INV
data0_inv (.I(data_int[0],
I, IB, CE, C
.O(data_n_int[0]);
I, IB, C, CLR
I, IB, CE, C, CLR
I, IB, C, PRE
I, IB, CE, C, PRE
I, IB, C, R
OBUF_LVDS data0_n
.O(data_n[0]));
(.I(data_n_int[0]),
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following con-
straint in the .ucf or .ncf file.
I, IB, CE, C, R
I, IB, C, S
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Synchronous vs. Asynchronous Outputs
I, IB, CE, C, S
I, IB, G
If the outputs are synchronous (registered in the IOB) then
any IO_L#P|N pair can be used. If the outputs are asynchro-
nous (no output register), then they must use one of the
pairs that are part of the same IOB group at the end of a
ROW or COLUMN in the device.
I, IB, GE, G
I, IB, G, CLR
I, IB, GE, G, CLR
I, IB, G, PRE
I, IB, GE, G, PRE
The LVDS pairs that can be used as asynchronous outputs
are listed in the Virtex-E pinout tables. Some pairs are
marked as asynchronous-capable for all devices in that
package, and others are marked as available only for that
device in the package. If the device size might change at
some point in the product lifetime, then only the common
pairs for all packages should be used.
Creating LVDS Output Buffers
LVDS output buffers can be placed in a wide number of IOB
locations. The exact locations are dependent on the pack-
age used. The Virtex-E package information lists the possi-
ble locations as IO_L#P for the P-side and IO_L#N for the
N-side, where # is the pair number.
Adding an Output Register
All LVDS buffers can have an output register in the IOB. The
output registers must be in both the P-side and N-side IOBs.
All the normal IOB register options are available (FD, FDE,
FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,
LDE, LDC, LDCE, LDP, LDPE). The register elements can
be inferred or explicitly instantiated in the HDL code.
HDL Instantiation
Both output buffers are required to be instantiated in the
design and placed on the correct IO_L#P and IO_L#N loca-
tions. The IOB must have the same net source the following
pins, clock (C), set/reset (SR), output (O), output clock
enable (OCE). In addition, the output (O) pins must be
inverted with respect to each other, and if output registers
are used, the INIT states must be opposite values (one
HIGH and one LOW). Failure to follow these rules leads to
DRC errors in software.
Special care must be taken to insure that the D pins of the
registers are inverted and that the INIT states of the regis-
ters are opposite. The clock pin (C), clock enable (CE) and
set/reset (CLR/PRE or S/R) pins must connect to the same
source. Failure to do this leads to a DRC error in the soft-
ware.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs.
VHDL Instantiation
data0_p : OBUF_LVDS port map
(I=>data_int(0),
O=>data_p(0));
To improve design coding times VHDL and Verilog synthe-
sis macro libraries have been developed to explicitly create
these structures. The output library macros are listed in
Table 43. The O and OB inputs to the macros are the exter-
nal net connections.
data0_inv: INV
(I=>data_int(0),
port map
O=>data_n_int(0));
data0_n : OBUF_LVDS port map
(I=>data_n_int(0), O=>data_n(0));
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Virtex™-E 1.8 V Field Programmable Gate Arrays
VHDL Instantiation
data0_p: OBUFT_LVDS port map
Table 43: Output Library Macros
(I=>data_int(0), T=>data_tri,
O=>data_p(0));
Name
Inputs
Outputs
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
O, OB
OBUFDS_FD_LVDS
OBUFDS_FDE_LVDS
OBUFDS_FDC_LVDS
OBUFDS_FDCE_LVDS
OBUFDS_FDP_LVDS
OBUFDS_FDPE_LVDS
OBUFDS_FDR_LVDS
OBUFDS_FDRE_LVDS
OBUFDS_FDS_LVDS
OBUFDS_FDSE_LVDS
OBUFDS_LD_LVDS
OBUFDS_LDE_LVDS
OBUFDS_LDC_LVDS
OBUFDS_LDCE_LVDS
OBUFDS_LDP_LVDS
OBUFDS_LDPE_LVDS
D, C
data0_inv: INV port map
(I=>data_int(0), O=>data_n_int(0));
DD, CE, C
D, C, CLR
D, CE, C, CLR
D, C, PRE
D, CE, C, PRE
D, C, R
data0_n:
OBUFT_LVDS port map
(I=>data_n_int(0), T=>data_tri,
O=>data_n(0));
Verilog Instantiation
OBUFT_LVDS data0_p
(.I(data_int[0]),
.T(data_tri), .O(data_p[0]));
INV
data0_inv (.I(data_int[0],
D, CE, C, R
D, C, S
.O(data_n_int[0]);
OBUFT_LVDS data0_n
(.I(data_n_int[0]),
.T(data_tri), .O(data_n[0]));
D, CE, C, S
D, G
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following con-
straint in the .ucf or .ncf file.
D, GE, G
D, G, CLR
D, GE, G, CLR
D, G, PRE
D, GE, G, PRE
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Synchronous vs. Asynchronous 3-State Outputs
If the outputs are synchronous (registered in the IOB), then
any IO_L#P|N pair can be used. If the outputs are asynchro-
nous (no output register), then they must use one of the
pairs that are part of the same IOB group at the end of a
ROW or COLUMN in the device. This applies for either the
3-state pin or the data out pin.
Creating LVDS Output 3-State Buffers
LVDS output 3-state buffers can be placed in a wide number
of IOB locations. The exact locations are dependent on the
package used. The Virtex-E package information lists the
possible locations as IO_L#P for the P-side and IO_L#N for
the N-side, where # is the pair number.
LVDS pairs that can be used as asynchronous outputs are
listed in the Virtex-E pinout tables. Some pairs are marked
as “asynchronous capable” for all devices in that package,
and others are marked as available only for that device in
the package. If the device size might be changed at some
point in the product lifetime, then only the common pairs for
all packages should be used.
HDL Instantiation
Both output 3-state buffers are required to be instantiated in
the design and placed on the correct IO_L#P and IO_L#N
locations. The IOB must have the same net source the fol-
lowing pins, clock (C), set/reset (SR), 3-state (T), 3-state
clock enable (TCE), output (O), output clock enable (OCE).
In addition, the output (O) pins must be inverted with
respect to each other, and if output registers are used, the
INIT states must be opposite values (one High and one
Low). If 3-state registers are used, they must be initialized to
the same state. Failure to follow these rules leads to DRC
errors in the software.
Adding Output and 3-State Registers
All LVDS buffers can have an output register in the IOB. The
output registers must be in both the P-side and N-side IOBs.
All the normal IOB register options are available (FD, FDE,
FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,
LDE, LDC, LDCE, LDP, LDPE). The register elements can
be inferred or explicitly instantiated in the HDL code.
Special care must be taken to insure that the D pins of the
registers are inverted and that the INIT states of the regis-
ters are opposite. The 3-state (T), 3-state clock enable
(CE), clock pin (C), output clock enable (CE) and set/reset
(CLR/PRE or S/R) pins must connect to the same source.
Failure to do this leads to a DRC error in the software.
DS022-2 (v2.2) July 23, 2001
Preliminary Product Specification
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The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs.
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following con-
straint in the .ucf or .ncf file.
To improve design coding times VHDL and Verilog synthe-
sis macro libraries have been developed to explicitly create
these structures. The input library macros are listed below.
The 3-state is configured to be 3-stated at GSR and when
the PRE,CLR,S or R is asserted and shares it's clock
enable with the output register. If this is not desirable then
the library can be updated by the user for the desired func-
tionality. The O and OB inputs to the macros are the exter-
nal net connections.
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Synchronous vs. Asynchronous Bidirectional
Buffers
If the output side of the bidirectional buffers are synchro-
nous (registered in the IOB), then any IO_L#P|N pair can be
used. If the output side of the bidirectional buffers are asyn-
chronous (no output register), then they must use one of the
pairs that is a part of the asynchronous LVDS IOB group.
This applies for either the 3-state pin or the data out pin.
Creating a LVDS Bidirectional Buffer
LVDS bidirectional buffers can be placed in a wide number
of IOB locations. The exact locations are dependent on the
package used. The Virtex-E package information lists the
possible locations as IO_L#P for the P-side and IO_L#N for
the N-side, where # is the pair number.
The LVDS pairs that can be used as asynchronous bidirec-
tional buffers are listed in the Virtex-E pinout tables. Some
pairs are marked as asynchronous capable for all devices in
that package, and others are marked as available only for
that device in the package. If the device size might change
at some point in the product’s lifetime, then only the com-
mon pairs for all packages should be used.
HDL Instantiation
Both bidirectional buffers are required to be instantiated in
the design and placed on the correct IO_L#P and IO_L#N
locations. The IOB must have the same net source the fol-
lowing pins, clock (C), set/reset (SR), 3-state (T), 3-state
clock enable (TCE), output (O), output clock enable (OCE).
In addition, the output (O) pins must be inverted with
respect to each other, and if output registers are used, the
INIT states must be opposite values (one HIGH and one
LOW). If 3-state registers are used, they must be initialized
to the same state. Failure to follow these rules leads to DRC
errors in the software.
Adding Output and 3-State Registers
All LVDS buffers can have an output and input registers in
the IOB. The output registers must be in both the P-side and
N-side IOBs, the input register is only in the P-side. All the
normal IOB register options are available (FD, FDE, FDC,
FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE,
LDC, LDCE, LDP, LDPE). The register elements can be
inferred or explicitly instantiated in the HDL code. Special
care must be taken to insure that the D pins of the registers
are inverted and that the INIT states of the registers are
opposite. The 3-state (T), 3-state clock enable (CE), clock
pin (C), output clock enable (CE), and set/reset (CLR/PRE
or S/R) pins must connect to the same source. Failure to do
this leads to a DRC error in the software.
VHDL Instantiation
data0_p:
IOBUF_LVDS port map
(I=>data_out(0), T=>data_tri,
IO=>data_p(0), O=>data_int(0));
data0_inv: INV
port map
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs. To improve design coding times
VHDL and Verilog synthesis macro libraries have been
developed to explicitly create these structures. The bidirec-
tional I/O library macros are listed in Table 44. The 3-state is
configured to be 3-stated at GSR and when the PRE,CLR,S
or R is asserted and shares its clock enable with the output
and input register. If this is not desirable then the library can
be updated be the user for the desired functionality. The I/O
and IOB inputs to the macros are the external net connec-
tions.
(I=>data_out(0),
O=>data_n_out(0));
data0_n : IOBUF_LVDS port map
(I=>data_n_out(0), T=>data_tri,
IO=>data_n(0), O=>open);
Verilog Instantiation
IOBUF_LVDS data0_p(.I(data_out[0]),
.T(data_tri), .IO(data_p[0]),
.O(data_int[0]);
INV
data0_inv (.I(data_out[0],
.O(data_n_out[0]);
IOBUF_LVDS
data0_n(.I(data_n_out[0]),.T(data_tri),.
IO(data_n[0]).O());
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Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 44: Bidirectional I/O Library Macros
Name
Inputs
D, T, C
Bidirectional
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
Outputs
IOBUFDS_FD_LVDS
IOBUFDS_FDE_LVDS
IOBUFDS_FDC_LVDS
IOBUFDS_FDCE_LVDS
IOBUFDS_FDP_LVDS
IOBUFDS_FDPE_LVDS
IOBUFDS_FDR_LVDS
IOBUFDS_FDRE_LVDS
IOBUFDS_FDS_LVDS
IOBUFDS_FDSE_LVDS
IOBUFDS_LD_LVDS
IOBUFDS_LDE_LVDS
IOBUFDS_LDC_LVDS
IOBUFDS_LDCE_LVDS
IOBUFDS_LDP_LVDS
IOBUFDS_LDPE_LVDS
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
D, T, CE, C
D, T, C, CLR
D, T, CE, C, CLR
D, T, C, PRE
D, T, CE, C, PRE
D, T, C, R
D, T, CE, C, R
D, T, C, S
D, T, CE, C, S
D, T, G
D, T, GE, G
D, T, G, CLR
D, T, GE, G, CLR
D, T, G, PRE
D, T, GE, G, PRE
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
12/7/99
1/10/00
Initial Xilinx release.
1.1
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
1/28/00
1.2
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, TBYP values, buffered Hex Line info, p. 8, I/O Timing
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
2/29/00
5/23/00
7/10/00
1.3
1.4
1.5
Updated pinout tables, VCC page 20, and corrected Figure 20.
Correction to table on p. 22.
•
Numerous minor edits.
•
•
•
•
Data sheet upgraded to Preliminary.
Preview -8 numbers added to Virtex-E Electrical Characteristics tables.
Reformatted entire document to follow new style guidelines.
Changed speed grade values in tables on pages 35-37.
8/1/00
1.6
DS022-2 (v2.2) July 23, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Date
Version
Revision
•
•
Min values added to Virtex-E Electrical Characteristics tables.
9/20/00
1.7
XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).
•
•
Corrected user I/O count for XCV100E device in Table 1 (Module 1).
Changed several pins to “No Connect in the XCV100E“ and removed duplicate VCCINT
pins in Table ~ (Module 4).
•
•
•
•
Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4).
Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4).
Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“.
Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.
11/20/00
1.8
•
•
•
Updated minimums in Table 13 and added notes to Table 14.
Added to note 2 to Absolute Maximum Ratings.
Changed speed grade -8 numbers for TSHCKO32, TREG, TBCCS, and TICKOF
.
•
Changed all minimum hold times to –0.4 under Global Clock Set-Up and Hold for
LVTTL Standard, with DLL.
•
Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters.
Changed GCLK0 to BA22 for FG860 package in Table 46.
Revised footnote for Table 14.
•
•
•
2/12/01
4/02/01
1.9
2.0
Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.
•
•
Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.
Revised Table 62 to include pinout information for the XCV400E and XCV600E devices
in the BG560 package.
•
•
•
•
Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.
Updated numerous values in Virtex-E Switching Characteristics tables.
Converted data sheet to modularized format. See the Virtex-E Data Sheet section.
Modified Figure 30 "DLL Generation of 4x Clock in Virtex-E Devices."
4/19/01
2.1
2.2
•
•
Made minor edits to text under Configuration.
07/23/01
Added CLB column locations for XCV2600E anbd XCV3200E devices in Table 3.
Virtex-E Data Sheet
The Virtex-E Data Sheet contains the following modules:
•
DS022-1, Virtex-E 1.8V FPGAs:
Introduction and Ordering Information (Module 1)
•
•
DS022-3, Virtex-E 1.8V FPGAs:
DC and Switching Characteristics (Module 3)
•
DS022-2, Virtex-E 1.8V FPGAs:
DS022-4, Virtex-E 1.8V FPGAs:
Functional Description (Module 2)
Pinout Tables (Module 4)
Module 2 of 4
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Preliminary Product Specification
0
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Virtex™-E 1.8 V
Field Programmable Gate Arrays
0
0
DS022-3 (v2.3) July 26, 2001
Preliminary Product Specification
Virtex-E Electrical Characteristics
Definition of Terms
The status of data sheets is designated as Advance or Preliminary. These specifications are defined as follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families.
Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Data sheets not identified as either Advance or Preliminary are to be considered final.
All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters
included are common to popular designs and typical applications. Contact the factory for design considerations requiring
more detailed information.
All specifications are subject to change without notice.
DC Characteristics
Absolute Maximum Ratings
Symbol
VCCINT
VCCO
VREF
VIN
Description(1)
Internal Supply voltage relative to GND(2)
Units
V
–0.5 to 2.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
50
Supply voltage relative to GND
Input Reference Voltage
V
V
Input voltage relative to GND
Voltage applied to 3-state output
Longest Supply Voltage Rise Time from 0 V - 1.71 V
Storage temperature (ambient)
Junction temperature(3)
V
VTS
V
VCC
ms
C
TSTG
TJ
–65 to +150
+125
Plastic packages
C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability.
2. Power supplies can turn on in any order. All user I/O is 3-stated prior to power-up. If the user I/O must remain in 3-state condition
during power-up, VCCINT must be applied prior to VCCO
.
3. For soldering guidelines and thermal considerations, see the Device Packaging infomation on the Xilinx website.
Recommended Operating Conditions
Symbol
Description
Min
Max
Units
V
Internal Supply voltage relative to GND, TJ = 0 C to +85 C
Internal Supply voltage relative to GND, TJ = –40 C to +100 C
Supply voltage relative to GND, TJ = 0 C to +85 C
Supply voltage relative to GND, TJ = –40 C to +100 C
Input signal transition time
Commercial 1.8 – 5% 1.8 + 5%
VCCINT
Industrial
Commercial
Industrial
1.8 – 5% 1.8 + 5%
V
1.2
1.2
3.6
3.6
250
V
VCCO
TIN
V
ns
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS022-3 (v2.3) July 26, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
DC Characteristics Over Recommended Operating Conditions
Symbol
Description
Data Retention VCCINT Voltage
Device
Min
Max Units
VDRINT
All
1.5
V
(below which configuration data might be lost)
Data Retention VCCO Voltage
VDRIO
All
1.2
V
(below which configuration data might be lost)
ICCINTQ Quiescent VCCINT supply current (Note 1)
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
All
200
200
300
300
300
400
500
500
500
TBD
TBD
2
mA
mA
mA
mA
mA
mA
mA
mA
mA
ICCOQ
Quiescent VCCO supply current (Note 1)
mA
mA
mA
mA
mA
mA
mA
mA
mA
2
2
2
2
2
2
2
2
TBD
TBD
+10
8
IL
Input or output leakage current
–10
A
pF
CIN
Input capacitance (sample tested)
BGA, PQ, HQ, packages
All
IRPU
IRPD
Notes:
Pad pull-up (when selected) @ Vin = 0 V, VCCO = 3.3 V (sample tested)
Pad pull-down (when selected) @ Vin = 3.6 V (sample tested)
All
Note 2 0.25
Note 2 0.25
mA
mA
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
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Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual
current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal
power supply voltage of the device1 from 0 V. The fastest suggested ramp rate is 0 V to nominal voltage in 2 ms and the
slowest allowed ramp rate is 0 V to nominal voltage in 50 ms.
Product (Commercial Grade)
XCV50E - XCV600E
Description2
Current Requirement3
Minimum required current supply
Minimum required current supply
Minimum required current supply
Minimum required current supply
500 mA
1 A
XCV1000E - XCV2000E
XCV2600E - XCV3200E
Virtex-E Family, Industrial Grade
TBD
2 A
Notes:
1. Ramp rate used for this specification is from 0 - 1.8 V dc. Peak current occurs on or near the internal power-on reset threshold and
lasts for less than 3 ms.
2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above.
3. Larger currents might result if ramp rates are forced to be faster.
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at minimum VCCO with the respective VOL and
VOH voltage levels shown. Other standards are sample tested.
VIL
V, Max
VIH
VOL
V, Max
0.4
VOH
V, Min
IOL
mA
24
IOH
mA
– 24
– 12
– 8
Input/Output
Standard
V, Min
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
V, Min
2.0
V, Max
3.6
LVTTL (Note 1)
LVCMOS2
LVCMOS18
PCI, 3.3 V
GTL
0.8
2.4
0.7
1.7
2.7
0.4
1.9
12
35% VCCO
30% VCCO
65% VCCO
1.95
0.4
VCCO – 0.4
90% VCCO
n/a
8
50% VCCO VCCO + 0.5 10% VCCO
Note 2
40
Note 2
n/a
VREF – 0.05 VREF + 0.05
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.6
GTL+
V
REF – 0.1
REF – 0.1
REF – 0.1
REF – 0.1
REF – 0.2
REF – 0.2
REF – 0.2
REF – 0.2
REF – 0.2
REF – 0.2
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.2
n/a
36
n/a
HSTL I
V
V
V
V
V
V
V
V
V
0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VREF + 0.6
VREF + 0.8
8
–8
HSTL III
HSTL IV
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
CTT
0.4
24
–8
0.4
48
–8
VREF – 0.6
VREF – 0.8
8
–8
16
–16
–7.6
–15.2
–8
VREF – 0.61 VREF + 0.61
VREF – 0.80 VREF + 0.80
7.6
15.2
8
VREF – 0.4
10% VCCO
VREF + 0.4
90% VCCO
AGP
Note 2
Note 2
Notes:
1. VOL and VOH for lower drive currents are sample tested.
2. Tested according to the relevant specifications.
DS022-3 (v2.3) July 26, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
LVDS DC Specifications
DC Parameter
Supply Voltage
Symbol
VCCO
VOH
Conditions
Min
Typ
Max Units
2.375
2.5
2.625
1.6
V
V
V
Output High Voltage for Q and Q
Output Low Voltage for Q and Q
RT = 100 across Q and Q signals
RT = 100 across Q and Q signals
1.25 1.425
VOL
0.9
1.075 1.25
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
VODIFF
VOCM
VIDIFF
VICM
RT = 100 across Q and Q signals
250
350 450
mV
V
Output Common-Mode Voltage
RT = 100 across Q and Q signals 1.125 1.25 1.375
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
Common-mode input voltage = 1.25 V 100
350
NA
2.2
mV
V
Input Common-Mode Voltage
Differential input voltage = 350 mV 0.2
1.25
Note: Refer to the Design Consideration section for termination schematics.
LVPECL DC Specifications
These values are valid at the output of the source termination pack shown under LVPECL, with a 100 differential load only.
The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
ranges. The following table summarizes the DC output specifications of LVPECL.
DC Parameter
Min
Max
Min
Max
Min
Max
Units
VCCO
3.0
3.3
3.6
V
V
V
V
V
V
VOH
1.8
0.96
1.49
0.86
0.3
2.11
1.27
2.72
2.125
-
1.92
1.06
1.49
0.86
0.3
2.28
1.43
2.72
2.125
-
2.13
1.30
1.49
0.86
0.3
2.41
1.57
2.72
2.125
-
VOL
VIH
VIL
Differential Input Voltage
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Virtex-E Switching Characteristics
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Virtex-E
devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels in Table 1. For other standards, adjust the delays with the
values shown in IOB Input Switching Characteristics Standard Adjustments, page 7.
Table 1: IOB Input Switching Characteristics
Speed Grade1
Description2
Propagation Delays
Symbol
Device
Min3
-8
-7
-6
Units
Pad to I output, no delay
Pad to I output, with delay
TIOPI
All
0.43
0.51
0.51
0.51
0.51
0.51
0.51
0.55
0.55
0.55
0.55
0.55
0.8
1.0
1.0
1.0
1.0
1.0
1.0
1.1
1.1
1.1
1.1
1.1
0.8
1.0
1.0
1.0
1.0
1.0
1.0
1.1
1.1
1.1
1.1
1.1
0.8
1.0
1.0
1.0
1.0
1.0
1.0
1.1
1.1
1.1
1.1
1.1
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
TIOPID
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E4
XCV3200E4
Pad to output IQ via transparent
latch, no delay
TIOPLI
All
0.8
1.4
1.5
1.6
ns, max
Pad to output IQ via transparent
latch, with delay
TIOPLID
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E4
XCV3200E4
1.31
1.31
1.39
1.39
1.43
1.55
1.55
1.59
1.59
1.59
1.59
2.9
2.9
3.1
3.1
3.2
3.5
3.5
3.6
3.6
3.6
3.6
3.0
3.0
3.2
3.2
3.3
3.6
3.6
3.7
3.7
3.7
3.7
3.1
3.1
3.3
3.3
3.4
3.7
3.7
3.8
3.8
3.8
3.8
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
DS022-3 (v2.3) July 26, 2001
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 1: IOB Input Switching Characteristics (Continued)
Speed Grade1
Description2
Sequential Delays
Clock CLK to output IQ
Symbol
Device
Min3
-8
-7
-6
Units
TIOCKIQ
All
0.18
0.4
0.7
0.7
ns, max
Setup and Hold Times with respect to Clock at IOB Input
Register
Pad, no delay
TIOPICK/
TIOICKP
All
0.69 / 0
1.3 / 0
1.4 / 0
1.5 / 0
ns, min
Pad, with delay
TIOPICKD
TIOICKPD
/
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E4
XCV3200E4
All
1.25 / 0
1.25 / 0
1.33 / 0
1.33 / 0
1.37 / 0
1.49 / 0
1.49 / 0
1.53 / 0
1.53 / 0
1.53 / 0
1.53 / 0
2.8 / 0
2.8 / 0
3.0 / 0
3.0 / 0
3.1 / 0
3.4 / 0
3.4 / 0
3.5 / 0
3.5 / 0
3.5 / 0
3.5 / 0
2.9 / 0
2.9 / 0
3.1 / 0
3.1 / 0
3.2 / 0
3.5 / 0
3.5 / 0
3.6 / 0
3.6 / 0
3.6 / 0
3.6 / 0
2.9 / 0
2.9 / 0
3.1 / 0
3.1 / 0
3.2 / 0
3.5 / 0
3.5 / 0
3.6 / 0
3.6 / 0
3.6 / 0
3.6 / 0
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ICE input
TIOICECK
TIOCKICE
/
0.28 /
0.0
0.55 /
0.01
0.7 /
0.01
0.7 /
0.01
SR input (IFF, synchronous)
Set/Reset Delays
TIOSRCKI
All
0.38
0.8
0.9
1.0
ns, min
SR input to IQ (asynchronous)
GSR to output IQ
TIOSRIQ
TGSRQ
All
All
0.54
3.88
1.1
7.6
1.2
8.5
1.4
9.7
ns, max
ns, max
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
2. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
3. The numbers for Min are Advance specification numbers. See Definition of Terms, page 1 for a description.
4. The numbers for XCV2600E and XCV3200E devices are Preview specification numbers for all speed grades.
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
IOB Input Switching Characteristics Standard Adjustments
Speed Grade1
Description
Symbol
Standard
Min2
-8
-7
-6
Units
Data Input Delay Adjustments
Standard-specific data input delay
adjustments
TILVTTL
TILVCMOS2
TILVCMOS18
TILVDS
LVTTL
LVCMOS2
LVCMOS18
LVDS
0.0
–0.02
0.12
0.00
0.00
0.0
0.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.0
0.0
0.0
+0.20
+0.15
+0.15
+0.08
–0.11
+0.14
+0.14
+0.04
+0.04
+0.04
+0.10
+0.04
+0.20
+0.15
+0.15
+0.08
–0.11
+0.14
+0.14
+0.04
+0.04
+0.04
+0.10
+0.04
+0.20
+0.15
+0.15
+0.08
–0.11
+0.14
+0.14
+0.04
+0.04
+0.04
+0.10
+0.04
TILVPECL
TIPCI33_3
TIPCI66_3
TIGTL
LVPECL
PCI, 33 MHz, 3.3 V –0.05
PCI, 66 MHz, 3.3 V –0.05
GTL
GTL+
HSTL
SSTL2
SSTL3
CTT
+0.10
+0.06
+0.02
–0.04
–0.02
+0.01
–0.03
TIGTLPLUS
TIHSTL
TISSTL2
TISSTL3
TICTT
TIAGP
AGP
Notes:
1. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
2. The numbers for Min are Advance product specification numbers. See Definition of Terms, page 1 for a description.
Q
D
CE
T
TCE
Weak
Keeper
SR
PAD
O
Q
D
CE
OCE
OBUFT
SR
I
IQ
Programmable
Delay
Q
D
CE
IBUF
Vref
SR
SR
CLK
ICE
ds022_02_091300
Figure 1: Virtex-E Input/Output Block (IOB)
DS022-3 (v2.3) July 26, 2001
Preliminary Product Specification
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Module 3 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
IOB Output Switching Characteristics, Figure 1
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 9.
Speed Grade(1)
Description(2)
Propagation Delays
Symbol
Min(3)
-8
-7
-6
Units
O input to Pad
TIOOP
1.04
1.24
2.5
2.9
2.7
3.1
2.9
3.4
ns, max
ns, max
O input to Pad via transparent latch
3-State Delays
TIOOLP
T input to Pad high-impedance (Note 2)
T input to valid data on Pad
TIOTHZ
TIOTON
0.73
1.13
1.5
2.7
1.7
2.9
1.9
3.1
ns, max
ns, max
T input to Pad high-impedance via transparent latch
(Note 2)
TIOTLPHZ
0.86
1.8
2.0
2.2
ns, max
T input to valid data on Pad via transparent latch
GTS to Pad high impedance (Note 2)
Sequential Delays
TIOTLPON
TGTS
1.26
1.94
3.0
4.1
3.2
4.6
3.4
4.9
ns, max
ns, max
Clock CLK to Pad
TIOCKP
TIOCKHZ
TIOCKON
0.97
0.77
1.17
2.4
1.6
2.8
2.8
2.0
3.2
2.9
2.2
3.4
ns, max
ns, max
ns, max
Clock CLK to Pad high-impedance (synchronous)
(Note 2)
Clock CLK to valid data on Pad (synchronous)
Setup and Hold Times before/after Clock CLK
O input
TIOOCK
/
0.43 / 0
0.28 / 0
0.40 / 0
0.26 / 0
0.30 / 0
0.38 / 0
0.9 / 0
0.55 / 0.01
0.8 / 0
1.0 / 0
0.7 / 0
0.9 / 0
0.6 / 0
0.7 / 0
0.9 / 0
1.1 / 0
0.7 / 0
1.0 / 0
0.7 / 0
0.8 / 0
1.0 / 0
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
TIOCKO
OCE input
TIOOCECK
TIOCKOCE
/
SR input (OFF)
TIOSRCKO
TIOCKOSR
/
3-State Setup Times, T input
3-State Setup Times, TCE input
3-State Setup Times, SR input (TFF)
TIOTCK /
TIOCKT
0.51 / 0
0.6 / 0
TIOTCECK
TIOCKTCE
/
TIOSRCKT
TIOCKTSR
/
0.8 / 0
Set/Reset Delays
SR input to Pad (asynchronous)
TIOSRP
1.30
1.08
3.1
2.2
3.3
2.4
3.5
2.7
ns, max
ns, max
SR input to Pad high-impedance (asynchronous)
(Note 2)
TIOSRHZ
SR input to valid data on Pad (asynchronous)
TIOSRON
TIOGSRQ
1.48
3.88
3.4
7.6
3.7
8.5
3.9
9.7
ns, max
ns, max
GSR to Pad
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
2. 3-state turn-off delays should not be adjusted.
3. The numbers for Min are Advance product specification numbers. See Definition of Terms, page 1 for a description.
Module 3 of 4
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DS022-3 (v2.3) July 26, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Speed Grade
Description
Symbol
Standard
Min1
-8
-7
-6
Units
Output Delay Adjustments
Standard-specific adjustments for output
delays terminating at pads (based on
standard capacitive load, Csl)
TOLVTTL_S2
TOLVTTL_S4
TOLVTTL_S6
TOLVTTL_S8
TOLVTTL_S12
TOLVTTL_S16
TOLVTTL_S24
TOLVTTL_F2
TOLVTTL_F4
TOLVTTL_F6
TOLVTTL_F8
TOLVTTL_F12
TOLVTTL_F16
TOLVTTL_F24
TOLVCMOS_2
TOLVCMOS_18
TOLVDS
LVTTL, Slow, 2 mA
4 mA
4.2
2.5
+14.7
+7.5
+14.7
+7.5
+14.7
+7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6 mA
1.8
+4.8
+4.8
+4.8
8 mA
1.2
+3.0
+3.0
+3.0
12 mA
1.0
+1.9
+1.9
+1.9
16 mA
0.9
+1.7
+1.7
+1.7
24 mA
0.8
+1.3
+1.3
+1.3
LVTTL, Fast, 2 mA
4 mA
1.9
+13.1
+5.3
+13.1
+5.3
+13.1
+5.3
0.7
6 mA
0.20
0.10
0.0
+3.1
+3.1
+3.1
8 mA
+1.0
+1.0
+1.0
12 mA
0.0
0.0
0.0
16 mA
–0.10
–0.10
0.10
0.10
–0.39
–0.20
0.50
0.10
0.6
–0.05
–0.20
+0.09
+0.7
–0.05
–0.20
+0.09
+0.7
–0.05
–0.20
+0.09
+0.7
24 mA
LVCMOS2
LVCMOS18
LVDS
–1.2
–1.2
–1.2
TOLVPECL
TOPCI33_3
TOPCI66_3
TOGTL
LVPECL
PCI, 33 MHz, 3.3 V
PCI, 66 MHz, 3.3 V
GTL
–0.41
+2.3
–0.41
+2.3
–0.41
+2.3
–0.41
+0.49
+0.8
–0.41
+0.49
+0.8
–0.41
+0.49
+0.8
TOGTLP
GTL+
0.7
TOHSTL_I
HSTL I
0.10
–0.10
–0.20
–0.10
–0.20
–0.20
–0.30
0.0
–0.51
–0.91
–1.01
–0.51
–0.91
–0.51
–1.01
–0.61
–0.91
–0.51
–0.91
–1.01
–0.51
–0.91
–0.51
–1.01
–0.61
–0.91
–0.51
–0.91
–1.01
–0.51
–0.91
–0.51
–1.01
–0.61
–0.91
TOHSTL_III
TOHSTL_IV
TOSSTL2_I
TOSSTL2_II
TOSSTL3_I
TOSSTL3_II
TOCTT
HSTL III
HSTL IV
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
CTT
TOAGP
AGP
–0.1
Notes:
1. The numbers for Min are Advance product specification numbers. See Definition of Terms, page 1 for a description.
DS022-3 (v2.3) July 26, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Calculation of Tioop as a Function of Capacitance
Tioop is the propagation delay from the O Input of the IOB to
the pad. The values for Tioop are based on the standard
capacitive load (Csl) for each I/O standard as listed in
Table 2.
For other capacitive loads, use the formulas below to calcu-
late the corresponding Tioop
ioop = Tioop + Topadjust + (Cload – Csl) * fl
where:
opadjust is reported above in the Output Delay
:
T
Table 2: Constants for Use in Calculation of Tioop
T
Standard
LVTTL Fast Slew Rate, 2mA drive
LVTTL Fast Slew Rate, 4mA drive
LVTTL Fast Slew Rate, 6mA drive
LVTTL Fast Slew Rate, 8mA drive
LVTTL Fast Slew Rate, 12mA drive
LVTTL Fast Slew Rate, 16mA drive
LVTTL Fast Slew Rate, 24mA drive
LVTTL Slow Slew Rate, 2mA drive
LVTTL Slow Slew Rate, 4mA drive
LVTTL Slow Slew Rate, 6mA drive
LVTTL Slow Slew Rate, 8mA drive
LVTTL Slow Slew Rate, 12mA drive
LVTTL Slow Slew Rate, 16mA drive
LVTTL Slow Slew Rate, 24mA drive
LVCMOS2
Csl (pF) fl (ns/pF)
Adjustment section.
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
10
10
0
0.41
0.20
Cload is the capacitive load for the design.
Table 3: Delay Measurement Methodology
0.13
Meas.
Point
VREF
Standard
LVTTL
VL
VH
(Typ)2
1
1
0.079
0.044
0.043
0.033
0.41
0
3
1.4
-
LVCMOS2
PCI33_3
PCI66_3
GTL
0
2.5
Per PCI Spec
Per PCI Spec
VREF +0.2
VREF +0.2
VREF +0.5
VREF +0.5
VREF +0.5
VREF +1.0
1.125
-
-
-
0.20
VREF –0.2
VREF –0.2
VREF –0.5
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
0.80
1.0
0.75
0.90
0.90
1.5
1.25
1.5
0.10
GTL+
0.086
0.058
0.050
0.048
0.041
0.050
0.050
0.033
0.014
0.017
0.022
0.016
0.014
0.028
0.016
0.029
0.016
0.035
0.037
HSTL Class I
HSTL Class III VREF –0.5
HSTL Class IV VREF –0.5
SSTL3 I & II
SSTL2 I & II
CTT
VREF –1.0
VREF –0.75 VREF +0.75
VREF –0.2 VREF +0.2
VREF VREF
(0.2xVCCO (0.2xVCCO
LVCMOS18
PCI 33 MHZ 3.3 V
AGP
–
+
Per
AGP
Spec
PCI 66 MHz 3.3 V
)
)
GTL
GTL+
0
LVDS
1.2 –0.125 1.2 + 0.125
1.6 –0.3 1.6 + 0.3
1.2
1.6
HSTL Class I
20
20
20
30
30
30
30
20
10
LVPECL
Notes:
HSTL Class III
HSTL Class IV
1. Input waveform switches between VLand VH.
2. Measurements are made at VREF (Typ), Maximum, and
Minimum. Worst-case values are reported.
SSTL2 Class I
I/O parameter measurements are made with the
capacitance values shown in Table 14. See the Application
Examples (Module 2) for appropriate terminations.
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
CTT
AGP
Notes:
1. I/O parameter measurements are made with the capacitance
values shown above. See the Application Examples
(Module 2) for appropriate terminations.
2. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
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Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Clock Distribution Switching Characteristics
Speed Grade
Description
GCLK IOB and Buffer
Symbol
Min1
-8
-7
-6
Units
Global Clock PAD to output.
Global Clock Buffer I input to O output
Notes:
TGPIO
TGIO
0.38
0.11
0.7
0.7
0.7
ns, max
ns, max
0.20
0.45
0.50
1. The numbers for Min are Advance product specification numbers. See Definition of Terms, page 1 for a description.
I/O Standard Global Clock Input Adjustments
Speed Grade
Description
Symbol1
Standard
Min2
-8
-7
-6
Units
Data Input Delay Adjustments
Standard-specific global clock
input delay adjustments
TGPLVTTL
TGPLVCMOS2
TGPLVCMOS18
TGLVDS
LVTTL
LVCMOS2
LVCMOS18
LVDS
0.0
–0.02
0.12
0.23
0.23
–0.05
–0.05
0.20
0.20
0.18
0.21
0.18
0.22
0.21
0.0
0.0
0.0
0.0
0.0
0.0
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
0.20
0.38
0.38
0.08
–0.11
0.37
0.37
0.27
0.27
0.27
0.33
0.27
0.20
0.38
0.38
0.08
–0.11
0.37
0.37
0.27
0.27
0.27
0.33
0.27
0.20
0.38
0.38
0.08
–0.11
0.37
0.37
0.27
0.27
0.27
0.33
0.27
TGLVPECL
TGPPCI33_3
TGPPCI66_3
TGPGTL
LVPECL
PCI, 33 MHz, 3.3 V
PCI, 66 MHz, 3.3 V
GTL
TGPGTLP
GTL+
TGPHSTL
HSTL
TGPSSTL2
TGPSSTL3
TGPCTT
SSTL2
SSTL3
CTT
TGPAGP
AGP
Notes:
1. Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
2. The numbers for Min are Advance product specification numbers. See Definition of Terms, page 1 for a description.
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Virtex™-E 1.8 V Field Programmable Gate Arrays
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used, see Figure 2. The values listed below are
worst-case. Precise values are provided by the timing analyzer.
Speed Grade(1)
Description
Combinatorial Delays
Symbol
Min(2)
-8
-7
-6
Units
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
6-input function: F/G inputs to Y output via F6 MUX
6-input function: F5IN input to Y output
TILO
TIF5
0.19
0.36
0.35
0.35
0.04
0.40
0.76
0.74
0.74
0.11
0.42
0.8
0.47
0.9
ns, max
ns, max
ns, max
ns, max
ns, max
TIF5X
TIF6Y
TF5INY
0.8
0.9
0.9
1.0
0.20
0.22
Incremental delay routing through transparent latch to
XQ/YQ outputs
TIFNCTL
TBYYB
0.27
0.19
0.63
0.38
0.7
0.8
ns, max
ns, max
BY input to YB output
0.46
0.51
Sequential Delays
FF Clock CLK to XQ/YQ outputs
Latch Clock CLK to XQ/YQ outputs
Setup and Hold Times before/after Clock CLK
4-input function: F/G Inputs
TCKO
0.34
0.40
0.87
0.87
0.9
0.9
1.0
1.0
ns, max
ns, max
TCKLO
TICK
TCKI
/
0.39 / 0
0.55 / 0
0.27 / 0
0.58 / 0
0.25 / 0
0.28 / 0
0.24 / 0
0.9 / 0
1.3 / 0
0.6 / 0
1.3 / 0
0.6 / 0
0.55 / 0
0.46 / 0
1.0 / 0
1.4 / 0
0.8 / 0
1.5 / 0
0.7 / 0
0.7 / 0
0.52 / 0
1.1 / 0
1.5 / 0
0.8 / 0
1.6 / 0
0.8 / 0
0.7 / 0
0.6 / 0
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
5-input function: F/G inputs
6-input function: F5IN input
6-input function: F/G inputs via F6 MUX
BX/BY inputs
TIF5CK /
TCKIF5
TF5INCK
TCKF5IN
/
TIF6CK
TCKIF6
/
TDICK
TCKDI
/
CE input
TCECK /
TCKCE
SR/BY inputs (synchronous)
TRCK /
TCKR
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Set/Reset
TCH
TCL
0.56
0.56
1.2
1.2
1.3
1.3
1.4
1.4
ns, min
ns, min
Minimum Pulse Width, SR/BY inputs
TRPW
TRQ
0.94
0.39
-
1.9
0.8
2.1
0.9
400
2.4
1.0
ns, min
ns, max
MHz
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
Toggle Frequency (MHz) (for export control)
FTOG
416
357.2
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
2. The numbers for Min are Advance product specification numbers. See Definition of Terms, page 1 for a description.
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
COUT
CY
YB
G4
G3
G2
G1
I3
I2
I1
I0
Y
O
LUT
WE
INIT
D Q
CE
YQ
XB
DI
0
1
REV
BY
F5IN
F6
CY
F5
X
F5
BY DG
CK WSO
WE
BX
WSH
A4
DI
INIT
D Q
CE
XQ
BX
DI
WE
I3
I2
I1
I0
F4
F3
F2
F1
REV
O
LUT
0
1
SR
CLK
CE
ds022_05_092000
CIN
Figure 2: Detailed View of Virtex-E Slice
DS022-3 (v2.3) July 26, 2001
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Module 3 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Speed Grade1
Description
Combinatorial Delays
Symbol
Min2
-8
-7
-6
Units
F operand inputs to X via XOR
F operand input to XB output
F operand input to Y via XOR
F operand input to YB output
F operand input to COUT output
G operand inputs to Y via XOR
G operand input to YB output
G operand input to COUT output
BX initialization input to COUT
CIN input to X output via XOR
CIN input to XB
TOPX
TOPXB
TOPY
0.32
0.35
0.59
0.48
0.37
0.34
0.47
0.36
0.19
0.27
0.02
0.26
0.16
0.05
0.68
0.65
1.06
0.89
0.71
0.72
0.78
0.60
0.36
0.50
0.03
0.45
0.28
0.10
0.8
0.8
0.8
0.9
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
1.4
1.5
TOPYB
TOPCYF
TOPGY
TOPGYB
TOPCYG
TBXCY
TCINX
1.1
1.3
0.9
1.0
0.8
0.9
1.2
1.3
0.9
1.0
0.51
0.6
0.57
0.7
TCINXB
TCINY
TCINYB
TBYP
0.07
0.7
0.08
0.7
CIN input to Y via XOR
CIN input to YB
0.38
0.14
0.43
0.15
CIN input to COUT output
Multiplier Operation
F1/2 operand inputs to XB output via AND
F1/2 operand inputs to YB output via AND
F1/2 operand inputs to COUT output via AND
G1/2 operand inputs to YB output via AND
G1/2 operand inputs to COUT output via AND
Setup and Hold Times before/after Clock CLK
CIN input to FFX
TFANDXB
TFANDYB
TFANDCY
TGANDYB
TGANDCY
0.10
0.28
0.17
0.20
0.09
0.30
0.56
0.38
0.46
0.28
0.35
0.7
0.39
0.8
ns, max
ns, max
ns, max
ns, max
ns, max
0.46
0.55
0.30
0.51
0.7
0.34
TCCKX/TCKCX
0.47 / 0
0.49 / 0
1.0 / 0
1.2 / 0
1.2 / 0
1.3 / 0
1.3 / 0
ns, min
ns, min
CIN input to FFY
T
CCKY/TCKCY
0.92 / 0
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
2. The numbers for Min are Advance product specification numbers. See Definition of Terms, page 1 for a description.
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
CLB Distributed RAM Switching Characteristics
Speed Grade1
Description
Symbol
Min2
-8
-7
-6
Units
Sequential Delays
Clock CLK to X/Y outputs (WE active) 16 x 1 mode
Clock CLK to X/Y outputs (WE active) 32 x 1 mode
Shift-Register Mode
TSHCKO16
TSHCKO32
0.67
0.84
1.48
1.76
1.5
1.9
1.7
2.1
ns, max
ns, max
Clock CLK to X/Y outputs
Setup and Hold Times before/after Clock CLK
F/G address inputs
TREG
1.25
2.49
2.9
3.2
ns, max
TAS/TAH
0.19 / 0
0.24 / 0
0.29 / 0
0.38 / 0 0.42 / 0 0.47 / 0 ns, min
BX/BY data inputs (DIN)
T
DS/TDH
0.47 / 0 0.53 / 0 0.6 / 0
0.57 / 0 0.7 / 0 0.8 / 0
ns, min
ns, min
CE input (WE)
TWS/TWH
Shift-Register Mode
BX/BY data inputs (DIN)
TSHDICK
TSHCECK
0.24 / 0
0.29 / 0
0.47 / 0 0.53 / 0 0.6 / 0
ns, min
ns, min
CE input (WS)
0.57 / 0 0.7 / 0
0.8 / 0
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum clock period to meet address write cycle time
Shift-Register Mode
TWPH
TWPL
TWC
0.96
0.96
1.92
1.9
1.9
3.8
2.1
2.1
4.2
2.4
2.4
4.8
ns, min
ns, min
ns, min
Minimum Pulse Width, High
Minimum Pulse Width, Low
Notes:
TSRPH
TSRPL
1.0
1.0
1.9
1.9
2.1
2.1
2.4
2.4
ns, min
ns, min
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
2. The numbers for Min are Advance product specification numbers. See Definition of Terms, page 1 for a description.
RAMB4_S#_S#
WEA
ENA
DOA[#:0]
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]
WEB
ENB
RSTB
DOB[#:0]
CLKB
ADDRB[#:0]
DIB[#:0]
ds022_06_121699
Figure 3: Dual-Port Block SelectRAM
DS022-3 (v2.3) July 26, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Block RAM Switching Characteristics
Speed Grade1
Description
Sequential Delays
Symbol
Min2
-8
-7
-6
Units
Clock CLK to DOUT output
Setup and Hold Times before Clock CLK
TBCKO
0.63
2.46
3.1
3.5
ns, max
ADDR inputs
TBACK/TBCKA
BDCK/TBCKD
BECK/TBCKE
BRCK/TBCKR
0.42 / 0
0.42 / 0
0.97 / 0
0.9 / 0
0.9 / 0
0.9 / 0
2.0 / 0
1.8 / 0
1.7 / 0
1.0 / 0
1.0 / 0
2.2 / 0
2.1 / 0
2.0 / 0
1.1 / 0
1.1 / 0
2.5 / 0
2.3 / 0
2.2 / 0
ns, min
ns, min
ns, min
ns, min
ns, min
DIN inputs
T
EN input
T
RST input
T
WEN input
T
BWCK/TBCKW
0.86 / 0
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
CLKA -> CLKB setup time for different ports
Notes:
TBPWH
TBPWL
TBCCS
0.6
0.6
1.2
1.2
1.2
2.4
1.35
1.35
2.7
1.5
1.5
3.0
ns, min
ns, min
ns, min
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
2. The numbers for Min are Advance product specification numbers. See Definition of Terms, page 1 for a description.
TBUF Switching Characteristics
Speed Grade
Description
Combinatorial Delays
Symbol
Min1
-8
-7
-6
Units
IN input to OUT output
TIO
TOFF
TON
0.0
0.0
0.0
0 .0
0.11
0.11
ns, max
ns, max
ns, max
TRI input to OUT output high-impedance
TRI input to valid data on OUT output
Notes:
0.05
0.05
0.092
0.092
0.10
0.10
1. The numbers for Min are Advance product specification numbers. See Definition of Terms, page 1 for a description.
JTAG Test Access Port Switching Characteristics
Description
TMS and TDI Setup times before TCK
Symbol
TTAPTK
TTCKTAP
TTCKTDO
FTCK
Value
4.0
Units
ns, min
TMS and TDI Hold times after TCK
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
2.0
ns, min
11.0
33
ns, max
MHz, max
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Virtex-E Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are
expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
Speed Grade2, 3
Description1
Symbol
Device
XCV50E
Min4
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
-8
-7
-6
Units
ns
LVTTL Global Clock Input to Output Delay using TICKOFDLL
Output Flip-flop, 12 mA, Fast Slew Rate, with
DLL. For data output with different standards,
adjust the delays with the values shown in IOB
Output Switching Characteristics Standard
Adjustments, page 9.
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E5
XCV3200E5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
Table 2 and Table 3.
3. DLL output jitter is already included in the timing calculation.
4. The numbers for Min are Advance product specification numbers. See Definition of Terms, page 1 for a description.
5. The numbers for XCV2600E and XCV3200E devices are Preview specification numbers for all speed grades.
DS022-3 (v2.3) July 26, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL
Speed Grade2
Description1
Symbol
Device
XCV50E
Min4
1.5
1.5
1.5
1.5
1.5
1.6
1.7
1.8
1.8
2.0
2.2
-8
-7
-6
Units
ns
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, without
DLL. For data output with different standards,
adjust the delays with the values shown in IOB
Output Switching Characteristics Standard
Adjustments, page 9.
TICKOF
4.2
4.2
4.3
4.3
4.4
4.5
4.6
4.7
4.8
5.0
5.2
4.4
4.4
4.5
4.5
4.6
4.7
4.8
4.9
5.0
5.2
5.4
4.6
4.6
4.7
4.7
4.8
4.9
5.0
5.1
5.2
5.4
5.6
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E4
XCV3200E4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
Table 2 and Table 3.
3. The numbers for Min are Advance product specification numbers. See Definition of Terms, page 1 for a description.
4. The numbers for XCV2600E and XCV3200E devices are Preview specification numbers for all speed grades.
Module 3 of 4
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DS022-3 (v2.3) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Virtex-E Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are
expressed in nanoseconds unless otherwise noted
Global Clock Set-Up and Hold for LVTTL Standard, with DLL
Speed Grade2, 3
Description1
Symbol
Device
Min4
-8
-7
-6
Units
Input Setup and Hold Time Relative to Global Clock Input Signal
for LVTTL Standard. For data input with different standards,
adjust the setup time delay by the values shown in IOB Input
Switching Characteristics Standard Adjustments, page 7.
No Delay
TPSDLL/TPHDLL
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Global Clock and IFF, with DLL
XCV2600E5 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
XCV3200E5 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. DLL output jitter is already included in the timing calculation.
4. The numbers for Min are Advance product specification numbers. See Definition of Terms, page 1 for a description.
5. The numbers for XCV2600E and XCV3200E devices are Preview specification numbers for all speed grades.
DS022-3 (v2.3) July 26, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Global Clock Set-Up and Hold for LVTTL Standard, without DLL
Speed Grade2, 3
Description1
Symbol
Device
Min4
-8
-7
-6
Units
Input Setup and Hold Time Relative to Global Clock Input Signal
for LVTTL Standard. For data input with different standards, adjust
the setup time delay by the values shown in IOB Input Switching
Characteristics Standard Adjustments, page 7.
Full Delay
TPSFD/TPHFD
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E5
XCV3200E5
1.8 / 0
1.8 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
2.3 / 0
2.5 / 0
2.5 / 0
2.7 / 0
2.8 / 0
1.8 / 0
1.8 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
2.3 / 0
2.5 / 0
2.5 / 0
2.7 / 0
2.8 / 0
1.8 / 0
1.8 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
2.3 / 0
2.5 / 0
2.5 / 0
2.7 / 0
2.8 / 0
1.8 / 0
1.8 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
2.3 / 0
2.5 / 0
2.5 / 0
2.7 / 0
2.8 / 0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Global Clock and IFF, without DLL
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
4. The numbers for Min are Advance product specification numbers. See Definition of Terms, page 1 for a description.
5. The numbers for XCV2600E and XCV3200E devices are Preview specification numbers for all speed grades.
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
DLL Timing Parameters
Switching parameters testing is modeled after testing methods specified by MIL-M-38510/605; all devices are 100 percent
functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are
derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended
operating conditions.
Speed Grade1
-8
-7
-6
Description
Symbol
FCLKINHF
FCLKINLF
TDLLPW
FCLKIN
Min
60
Max
350
160
Min
60
Max
320
160
Min Max Units
Input Clock Frequency (CLKDLLHF)
Input Clock Frequency (CLKDLL)
Input Clock Low/High Pulse Width
60
25
275
135
MHz
MHz
ns
25
25
5 MHz
50 MHz
100 MHz
5.0
3.0
2.4
5.0
3.0
2.4
2.0
1.8
1.5
1.3
5.0
3.0
2.4
2.0
1.8
1.5
NA
ns
ns
150 MHz 2.0
200 MHz 1.8
250 MHz 1.5
300 MHz 1.3
ns
ns
ns
ns
Notes:
1. All specifications correspond to Commercial Operating Temperatures (0°C to +85°C).
Period Tolerance: the allowed input clock period change in nanoseconds.
+ T
_
IPTOL
T
T
CLKIN
CLKIN
Output Jitter: the difference between an ideal
Phase Offset and Maximum Phase Difference
reference clock edge and the actual design.
Ideal Period
Actual Period
+/- Jitter
+ Maximum
Phase Difference
+ Phase Offset
ds022_24_091200
Figure 4: DLL Timing Waveforms
DS022-3 (v2.3) July 26, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock
mirror configuration and matched drivers.
CLKDLLHF
CLKDLL
Min Max Units
Description
Input Clock Period Tolerance
Symbol
TIPTOL
TIJITCC
TLOCK
FCLKIN
Min
Max
1.0
150
20
-
-
-
-
-
-
-
-
-
1.0
300
20
ns
ps
s
Input Clock Jitter Tolerance (Cycle to Cycle)
Time Required for DLL to Acquire Lock
-
-
-
-
-
-
> 60 MHz
50 - 60 MHz
40 - 50 MHz
30 - 40 MHz
25 - 30 MHz
25
s
-
50
s
-
90
s
-
120
60
s
Output Jitter (cycle-to-cycle) for any DLL Clock Output1
Phase Offset between CLKIN and CLKO2
TOJITCC
TPHIO
60
100
140
160
200
ps
ps
ps
ps
ps
100
140
160
200
Phase Offset between Clock Outputs on the DLL3
Maximum Phase Difference between CLKIN and CLKO4
Maximum Phase Difference between Clock Outputs on the DLL5
Notes:
TPHOO
TPHIOM
TPHOOM
1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding Output Jitter and input clock jitter.
3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
5. Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).
6. All specifications correspond to Commercial Operating Temperatures (0°C to +85°C).
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
12/7/99
1/10/00
Initial Xilinx release.
1.1
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
1/28/00
1.2
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, TBYP values, buffered Hex Line info, p. 8, I/O Timing
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
2/29/00
5/23/00
1.3
1.4
Updated pinout tables, VCC page 20, and corrected Figure 20.
Correction to table on p. 22.
Module 3 of 4
22
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DS022-3 (v2.3) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Revision
Date
Version
•
•
•
•
•
•
•
Numerous minor edits.
7/10/00
1.5
Data sheet upgraded to Preliminary.
Preview -8 numbers added to Virtex-E Electrical Characteristics tables.
Reformatted entire document to follow new style guidelines.
Changed speed grade values in tables on pages 35-37.
8/1/00
1.6
1.7
Min values added to Virtex-E Electrical Characteristics tables.
9/20/00
XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).
•
•
Corrected user I/O count for XCV100E device in Table 1 (Module 1).
Changed several pins to “No Connect in the XCV100E“ and removed duplicate VCCINT
pins in Table ~ (Module 4).
•
•
•
•
Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4).
Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4).
Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“.
Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.
11/20/00
1.8
•
•
•
Updated minimums in Table 13 and added notes to Table 14.
Added to note 2 to Absolute Maximum Ratings.
Changed speed grade -8 numbers for TSHCKO32, TREG, TBCCS, and TICKOF
.
•
Changed all minimum hold times to –0.4 under Global Clock Set-Up and Hold for
LVTTL Standard, with DLL.
•
Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters.
Changed GCLK0 to BA22 for FG860 package in Table 46.
Revised footnote for Table 14.
•
•
•
2/12/01
4/02/01
1.9
2.0
Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.
•
•
Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.
Revised Table 62 to include pinout information for the XCV400E and XCV600E devices
in the BG560 package.
•
•
•
•
Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.
Updated numerous values in Virtex-E Switching Characteristics tables.
Converted data sheet to modularized format. See the Virtex-E Data Sheet section.
Updated values in Virtex-E Switching Characteristics tables.
4/19/01
2.1
2.2
•
•
Under Absolute Maximum Ratings, changed (TSOL) to 220 C.
07/23/01
Changes made to SSTL symbol names in IOB Input Switching Characteristics
Standard Adjustments table.
•
Removed TSOL parameter and added footnote to Absolute Maximum Ratings table.
07/26/01
2.3
Virtex-E Data Sheet
The Virtex-E Data Sheet contains the following modules:
•
DS022-1, Virtex-E 1.8V FPGAs:
Introduction and Ordering Information (Module 1)
•
•
DS022-3, Virtex-E 1.8V FPGAs:
DC and Switching Characteristics (Module 3)
•
DS022-2, Virtex-E 1.8V FPGAs:
DS022-4, Virtex-E 1.8V FPGAs:
Functional Description (Module 2)
Pinout Tables (Module 4)
DS022-3 (v2.3) July 26, 2001
Preliminary Product Specification
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23
0
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Virtex™-E 1.8 V
Field Programmable Gate Arrays
0
0
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
Virtex-E Pin Definitions
Pin Name
Dedicated Pin
Direction
Description
GCK0, GCK1,
GCK2, GCK3
Yes
Input
Clock input pins that connect to Global Clock Buffers.
Mode pins are used to specify the configuration mode.
M0, M1, M2
CCLK
Yes
Yes
Input
Input or
Output
The configuration Clock I/O pin: it is an input for SelectMAP and
slave-serial modes, and output in master-serial mode. After
configuration, it is input only, logic level = Don’t Care.
PROGRAM
DONE
Yes
Yes
Input
Initiates a configuration sequence when asserted Low.
Bidirectional Indicates that configuration loading is complete, and that the start-up
sequence is in progress. The output can be open drain.
INIT
No
No
Bidirectional When Low, indicates that the configuration memory is being cleared.
The pin becomes a user I/O after configuration.
(Open-drain)
BUSY/DOUT
Output
In SelectMAP mode, BUSY controls the rate at which configuration
data is loaded. The pin becomes a user I/O after configuration unless
the SelectMAP port is retained.
In bit-serial modes, DOUT provides preamble and configuration data
to downstream devices in a daisy-chain. The pin becomes a user I/O
after configuration.
D0/DIN,
D1, D2,
D3, D4,
D5, D6,
D7
No
Input or
Output
In SelectMAP mode, D0-7 are configuration data pins. These pins
become user I/Os after configuration unless the SelectMAP port is
retained.
In bit-serial modes, DIN is the single data input. This pin becomes a
user I/O after configuration.
WRITE
No
No
Input
Input
Mixed
In SelectMAP mode, the active-low Write Enable signal. The pin
becomes a user I/O after configuration unless the SelectMAP port is
retained.
CS
In SelectMAP mode, the active-low Chip Select signal. The pin
becomes a user I/O after configuration unless the SelectMAP port is
retained.
TDI, TDO,
TMS, TCK
DXN, DXP
VCCINT
Yes
Boundary-scan Test-Access-Port pins, as defined in IEEE1149.1.
Yes
Yes
Yes
No
N/A
Temperature-sensing diode pins. (Anode: DXP, cathode: DXN)
Power-supply pins for the internal core logic.
Input
Input
Input
VCCO
Power-supply pins for the output drivers (subject to banking rules)
VREF
Input threshold voltage pins. Become user I/Os when an external
threshold voltage is not needed (subject to banking rules).
GND
Yes
Input
Ground
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Preliminary Product Specification
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Module 4 of 4
1
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Pinout Differences Between Virtex and Virtex-E Families
The same device in the same package for the Virtex-E and
Virtex families are pin-compatible with some minor excep-
tions, listed in Table 1.
XCV400E Device, FG676 Package
The Virtex-E XCV400E has two I/O pins swapped with the
Virtex XCV400 to accommodate differential clock pairing.
XCV200E Device, FG456 Package
All Devices, PQ240 and HQ240 Packages
The Virtex-E XCV200E has two I/O pins swapped with the
Virtex XCV200 to accommodate differential clock pairing.
The Virtex devices in PQ240 and HQ240 packages do not
have VCCO banking, but Virtex-E devices do. To achieve
this, eight Virtex I/O pins (P232, P207, P176, P146, P116,
P85, P55, and P25) are now VCCO pins in the Virtex-E fam-
ily. This change also requires one Virtex I/O or VREF pin to
be swapped with a standard I/O pin.
XCV300E Device, BG432 Package
The Virtex-E XCV300E has eight pins (B26, C7, F1, F30, S
AE29, AF1, AH8, and AH24) connected to VCCINT that are
not connected in the Virtex XCV300.
Additionally, accommodating differential clock input pairs in
Virtex-E caused some IO_VREF differences in the XCV400E
and XCV600E devices only. Virtex IO_VREF pins P215 and
P87 are Virtex-E IO_VREF pins P216 and P86, respectively.
Virtex-E pins P215 and P87 are IO_DLL.
Table 1: Pinout Differences Summary
Part
Package
FG456
Pins
Virtex
Virtex-E
No Connect
IO_LVDS_DLL
VCCINT
XCV200
E11, U11
I/O
B11, AA11
No Connect
No Connect
I/O
XCV300
XCV400
BG432
FG676
B26, C7, F1, F30, AE29, AF1, AH8, and AH24
D13, Y13
No Connect
IO_LVDS_DLL
IO_LVDS_DLL
IO_VREF
B13, AF13
No Connect
IO_VREF
I/O
XCV400/600 PQ240/HQ240 P215, P87
P216, P86
All
PQ240/HQ240 P232, P207, P176, P146, P116, P85, P55, and P25 I/O
VCCO
P231
I/O
IO_VREF
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Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 2: LVDS Pin Pairs
Pin Name
Low Voltage Differential Signals
The Virtex-E family incorporates low-voltage signalling
(LVDS and LVPECL). Two pins are utilized for these signals
to be connected to a Virtex-E device. These are known as
differential pin pairs. Each differential pin pair has a Positive
(P) and a Negative (N) pin. These pairs are labeled in the
following manner.
Description
IO_L#[P/N]
Represents a general IO or a
synchronous input/output
differential signal. When used
as a differential signal, N
means Negative I/O and P
means Positive I/O.
Example: IO_L22N
IO_L#[P/N]
where
IO_L#[P/N]_Y
Represents a general IO or a
synchronous input/output
differential signal, or a
part-dependent asynchronous
output differential signal.
L = LVDS or LVPECL pin
# = Pin Pair Number
P = Positive
Example: IO_L22N_Y
N = Negative
IO_L#[P/N]_YY
Represents a general IO or a
synchronous input/output
differential signal, or an
asynchronous output
I/O pins for differential signals can either be synchronous or
asynchronous, input or output. The pin pairs can be used for
synchronous input and output signals as well as asynchro-
nous input signals. However, only some of the low-voltage
pairs can be used for asynchronous output signals.
Example: O_L22N_YY
differential signal.
IO_LVDS_DLL_L#[P/N] Represents a general IO or a
synchronous input/output
DIfferential signals require the pins of a pair to switch almost
simultaneously. If the signals driving the pins are from IOB
flip-flops, they are synchronous. If the signals driving the
pins are from internal logic, they are asynchronous. Table 2
defines the names and function of the different types of
low-voltage pin pairs in the Virtex-E family.
differential signal, a differential
clock input signal, or a DLL
Example:
IO_LVDS_DLL_L16N
input. When used as a
differential clock input, this pin
is paired with the adjacent
GCK pin. The GCK pin is
always the positive input in the
differential clock input
configuration.
Virtex-E Package Pinouts
The Virtex-E family of FPGAs is available in 12 popular
packages, including chip-scale, plastic and high heat-dissi-
pation quad flat packs, and ball grid and fine-pitch ball grid
arrays. Family members have footprint compatibility across
devices provided in the same package. The pinout tables in
this section indicate function, pin, and bank information for
each package/device combination. Following each pinout
table is an additional table summarizing information specific
to differential pin pairs for all devices provided in that pack-
age.
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
3
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
CS144 Chip-Scale Package
XCV50E, XCV100E, XCV200E, XCV300E and XCV400E
devices in CS144 Chip-scale packages have footprint com-
patibility. In the CS144 package, bank pairs that share a
side are internally interconnected, permitting four choices
for VCCO. See Table 3.
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Bank
Pin Description
IO_VREF
Pin #
A10
B8
1
1
1
IO_VREF
IO_VREF
B101
Table 3: I/O Bank Pairs and Shared Vcco Pins
Paired Banks
Banks 0 & 1
Banks 2 & 3
Banks 4 & 5
Banks 6 & 7
Shared VCCO Pins
A2, A13, D7
2
2
2
2
2
2
2
2
2
2
2
2
2
IO
IO
D12
F12
C11
C12
E10
D132
E13
E12
F11
F10
F13
C131
D11
B12, G11, M13
N1, N7, N13
IO_DOUT_BUSY_L6P_YY
IO_DIN_D0_L6N_YY
IO_D1_L7N
B2, G2, M2
Pins labeled I0_VREF can be used as either in all parts
unless device-dependent, as indicated in the footnotes. If
the pin is not used as VREF, it can be used as general I/O.
Immediately following Table 4, see Table 5 is Differential
Pair information.
IO_VREF_L7P
IO_L8N_YY
IO_D2_L8P_YY
IO_D3_L9N
IO_VREF_L9P
IO_L10P
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Bank
Pin Description
GCK3
Pin #
A6
0
0
0
0
0
0
0
0
0
0
IO_VREF
IO
B3
IO_VREF
IO_VREF_L0N_YY
IO_L0P_YY
IO_L1N_YY
IO_L1P_YY
IO_LVDS_DLL_L2N
IO_VREF
B42
A4
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
H13
K13
G13
H11
H12
J13
B5
IO
A5
IO_L10N
C6
IO_VREF_L11N
IO_D4_L11P
IO_D5_L12N_YY
IO_L12P_YY
IO_VREF_L13N
IO_D6_L13P
IO_INIT_L14N_YY
IO_D7_L14P_YY
IO_VREF
A31
C4
IO_VREF
IO_VREF
D6
H10
J102
J11
1
1
1
1
1
1
1
1
1
GCK2
IO
A7
A8
L13
IO_LVDS_DLL_L2P
IO_L3N_YY
B7
K10
K111
K12
C8
IO_L3P_YY
D8
IO_VREF
IO_L4N_YY
C9
IO_VREF_L4P_YY
IO_WRITE_L5N_YY
IO_CS_L5P_YY
D92
C10
D10
4
4
4
GCK0
IO
K7
M8
IO
M10
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Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Bank
Pin Description
IO_L15N_YY
IO_L15P_YY
IO_L16N_YY
IO_VREF_L16P_YY
IO_L17N_YY
IO_L17P_YY
IO_LVDS_DLL_L18P
IO_VREF
Pin #
M11
L11
K9
Bank
Pin Description
Pin #
4
4
4
4
4
4
4
4
4
4
6
IO_L26N
G1
7
7
7
7
7
7
7
7
7
7
7
7
IO
IO
C2
D3
F3
N102
K8
IO
N9
IO_L26P
F2
N8
IO_L27N
IO_VREF_L27P
IO_L28N_YY
IO_L28P_YY
IO_L29N
IO_VREF_L29P
IO_VREF
IO_VREF
F4
L8
E1
E2
E3
D1
D22
C11
D4
IO_VREF
L10
N111
IO_VREF
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
IO
M7
M4
M6
N5
K6
IO_LVDS_DLL_L18N
IO_L19N_YY
IO_L19P_YY
IO_VREF_L20N_YY
IO_L20P_YY
IO_L21N_YY
IO_L21P_YY
IO_VREF
2
CCLK
DONE
M0
B13
M12
M1
L2
N42
K5
3
NA
NA
NA
NA
NA
NA
2
M3
N3
K41
L4
M1
M2
N2
PROGRAM
TDI
L12
A11
C3
IO_VREF
IO_VREF
L6
TCK
TDO
A12
B1
6
6
6
6
6
6
6
6
6
6
6
6
IO
G4
J4
NA
TMS
IO
IO_L25P
H1
H2
H3
H4
J2
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
A9
B6
IO_VREF_L25N
IO_L24P_YY
IO_L24N_YY
IO_L23P
C5
G3
G12
M5
M9
N6
IO_VREF_L23N
IO_VREF
J32
K1
K21
L1
IO_VREF
IO_L22N_YY
IO_L22P_YY
K3
0
VCCO
A2
DS022-4 (v2.1) July 26, 2001
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Module 4 of 4
5
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 4: CS144 — XCV50E, XCV100E, XCV200E
CS144 Differential Pin Pairs
Bank
Pin Description
VCCO
Pin #
A13
D7
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
1
1
2
3
3
4
5
5
6
7
7
VCCO
VCCO
B12
G11
M13
N13
N1
VCCO
VCCO
VCCO
VCCO
VCCO
N7
Table 5: CS144 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E
VCCO
M2
VCCO
B2
P
N
Other
VCCO
G2
Pair Bank
Pin
Pin
AO
Functions
Global Differential Clock
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
B9
0
1
2
3
4
5
1
0
K7
M7
A7
A6
N8
M6
NA
NA
NA
NA
IO_DLL_L18P
IO_DLL_L18N
IO_DLL_L2P
IO_DLL_L2N
NA
B11
C7
D5
E4
B7
NA
C6
NA
IO LVDS
NA
Total Pairs: 30, Asynchronous Output Pairs: 18
NA
E11
F1
0
1
0
0
1
1
1
1
2
2
2
2
3
3
3
3
3
4
4
4
A4
A5
B4
B5
VREF
NA
-
NA
G10
J1
2
B7
C6
NA
IO_LVDS_DLL
NA
3
D8
C8
-
VREF
CS, WRITE
DIN, D0
D1, VREF
D2
NA
J12
L3
4
D9
C9
NA
5
D10
C11
D13
E12
F10
F13
H12
H10
J11
K10
L11
N10
N9
C10
C12
E10
E13
F11
G13
H11
J13
J10
L13
M11
K9
NA
L5
6
NA
L7
7
1
NA
L9
8
NA
N12
9
1
NA
1
D3, VREF
-
Notes:
10
11
12
13
14
15
16
17
1.
V
REF or I/O option only in the XCV200E; otherwise, I/O
option only.
D4, VREF
D5
2. VREF or I/O option only in the XCV100E, 200E; otherwise,
I/O option only.
1
D6, VREF
INIT
-
VREF
-
K8
Module 4 of 4
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 5: CS144 Differential Pin Pair Summary
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV50E, XCV100E, XCV200E
XCV300, XCV400E
P
N
Other
Pin #
P222
P221
P220
P218
P217
P2163
P215
P213
Pin Description
IO
Bank
Pair Bank
Pin
Pin
AO
Functions
0
0
0
0
0
0
0
0
18
19
20
21
22
23
24
25
26
27
28
29
5
5
5
5
6
6
6
6
7
7
7
7
N8
K6
K5
N3
K3
J2
M6
N5
N4
M3
L1
NA
IO_LVDS_DLL
IO_L4N_Y
-
IO_L4P_Y
VREF
IO_VREF_L5N_Y
IO_L5P_Y
-
-
IO_VREF
J3
1
VREF
IO_LVDS_DLL_L6N
GCK3
H3
H1
F2
E1
E3
D2
H4
H2
G1
F4
E2
D1
-
1
NA
1
VREF
-
P210
P209
P2083
P206
P205
P203
P202
P201
P200
P199
P195
P1941
P193
P192
P191
P189
P188
P1872
P186
P185
P184
GCK2
IO_LVDS_DLL_L6P
IO_VREF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VREF
-
1
VREF
IO_L7N_Y
Note 1: AO in the XCV50E
IO_VREF_L7P_Y
IO_L8N_Y
PQ240 Plastic Quad Flat-Pack Packages
IO_L8P_Y
XCV50E, XCV100E, XCV200E, XCV300E and XCV400E
devices in PQ240 Plastic Flat-pack packages have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as VREF, it can be used as gen-
eral I/O. Immediately following Table 6, see Table 7 for
Differential Pair information.
IO
IO_L9N_YY
IO_L9P_YY
IO_L10N_YY
IO_VREF_L10P_YY
IO
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
IO_L11N_YY
IO_VREF_L11P_YY
IO_L12N_YY
IO_L12P_YY
IO_VREF_L13N_Y
IO_L13P_Y
XCV300, XCV400E
Pin #
P238
P237
P2362
P235
P234
P231
P230
P2291
P228
P224
P223
Pin Description
IO
Bank
0
0
0
0
0
0
0
0
0
0
0
IO_L0N_Y
IO_VREF_L0P_Y
IO_L1N_YY
IO_L1P_YY
IO_VREF
IO_WRITE_L14N_YY
IO_CS_L14P_YY
IO
P178
P177
P1752
P174
IO_DOUT_BUSY_L15P_YY
IO_DIN_D0_L15N_YY
IO_VREF
2
2
2
2
IO_VREF_L2N_YY
IO_L2P_YY
IO_L3N_YY
IO_L3P_YY
IO_L16P_Y
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
7
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV300, XCV400E
XCV300, XCV400E
Pin #
P173
P171
P170
P169
P1681
P167
P163
P162
P161
P160
P159
P157
P156
P155
P1543
P153
P152
Pin Description
IO_L16N_Y
Bank
Pin #
P125
P124
P123
Pin Description
IO_L30N_Y
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
IO_VREF_L17P_Y
IO_L17N_Y
IO_D7_L31P_YY
IO_INIT_L31N_YY
IO
IO_VREF_L18P_Y
IO_D1_L18N_Y
IO_D2_L19P_YY
IO_L19N_YY
IO
P118
P117
P1152
P114
P113
P111
P110
P109
P1081
P107
P103
P102
P101
P100
P99
IO_L32P_YY
IO_L32N_YY
IO_VREF
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
IO_L33P_YY
IO_L33N_YY
IO_VREF_L34P_YY
IO_L34N_YY
IO
IO_L20P_Y
IO_L20N_Y
IO_VREF_L21P_Y
IO_D3_L21N_Y
IO_L22P_Y
IO_VREF_L35P_YY
IO_L35N_YY
IO_L36P_YY
IO_L36N_YY
IO
IO_VREF_L22N_Y
IO_L23P_YY
IO_L23N_YY
IO_L37P_Y
P149
P1473
P145
P144
P142
P141
P140
P139
P138
P134
P1331
P132
P131
P130
P128
P127
P1262
IO
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L37N_Y
IO_VREF
P97
IO_VREF_L38P_Y
IO_L38N_Y
IO_D4_L24P_Y
IO_VREF_L24N_Y
IO_L25P_Y
P96
P95
IO_L39P_Y
P943
P93
IO_VREF_L39N_Y
IO_LVDS_DLL_L40P
GCK0
IO_L25N_Y
IO
P92
IO_L26P_YY
IO_D5_L26N_YY
IO_D6_L27P_Y
IO_VREF_L27N_Y
IO
P89
P87
P863
P84
P82
P81
P80
P79
P78
GCK1
IO_LVDS_DLL_L40N
IO_VREF
5
5
5
5
5
5
5
5
5
IO_VREF_L41P_Y
IO_L41N_Y
IO
IO_L28P_Y
IO_VREF_L28N_Y
IO_L29P_Y
IO
IO_L29N_Y
IO_L42P_YY
IO_L42N_YY
IO_VREF_L30P_Y
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV300, XCV400E
XCV300, XCV400E
Pin #
P74
P731
P72
P71
P70
P68
P67
P662
P65
P64
P63
Pin Description
IO_L43P_YY
IO_VREF_L43N_YY
IO
Bank
Pin #
P263
P24
P23
P21
P20
P19
P18
P17
P13
P121
P11
P10
P9
Pin Description
IO_VREF
Bank
7
5
5
5
5
5
5
5
5
5
5
5
IO_L57N_Y
IO_VREF_L57P_Y
IO_L58N_Y
IO_L58P_Y
IO
7
7
IO_L44P_YY
IO_VREF_L44N_YY
IO_L45P_YY
IO_L45N_YY
IO_VREF_L46P_Y
IO_L46N_Y
7
7
7
IO_L59N_YY
IO_L59P_YY
IO_L60N_Y
IO_VREF_L60P_Y
IO
7
7
7
IO_L47P_YY
IO_L47N_YY
7
7
IO_L61N_Y
IO_VREF_L61P_Y
IO_L62N_Y
IO_L62P_Y
IO_VREF_L63N_Y
IO_L63P_Y
IO
7
P57
P56
P542
P53
P52
P50
P49
P48
P471
P46
P42
P41
P40
P39
P38
P36
P35
P34
P333
P31
IO_L48N_YY
IO_L48P_YY
IO_VREF
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
P7
7
P6
7
IO_L49N_Y
IO_L49P_Y
IO_VREF_L50N_Y
IO_L50P_Y
IO
P52
P4
7
7
P3
7
P179
P120
P60
CCLK
DONE
M0
2
IO_VREF_L51N_Y
IO_L51P_Y
IO_L52N_YY
IO_L52P_YY
IO
3
NA
NA
NA
NA
NA
NA
2
P58
M1
P62
M2
P122
P183
P239
P181
P2
PROGRAM
TDI
IO_L53N_Y
IO_L53P_Y
IO_VREF_L54N_Y
IO_L54P_Y
IO_L55N_Y
IO_VREF_L55P_Y
IO
TCK
TDO
TMS
NA
P225
P214
P198
P164
P148
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
NA
NA
NA
NA
NA
P28
P27
IO_L56N_YY
IO_L56P_YY
7
7
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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1-800-255-7778
Module 4 of 4
9
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV300, XCV400E
XCV300, XCV400E
Pin #
P137
P104
P88
Pin Description
VCCINT
Bank
NA
NA
NA
NA
NA
NA
NA
Pin #
P219
P211
P204
P196
P190
P182
P172
P166
P158
P151
P143
P135
P129
P119
P112
P106
P98
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
P77
VCCINT
P43
VCCINT
P32
VCCINT
P16
VCCINT
P240
P232
P226
P212
P207
P197
P180
P176
P165
P150
P146
P136
P121
P116
P105
P90
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
7
0
0
0
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
P91
P83
P75
P69
P59
P51
P45
P85
P37
P76
P29
P61
P22
P55
P14
P44
P8
P30
P1
P25
Notes:
1. REF or I/O option only in the XCV100E, 200E, 300E, 400E;
otherwise, I/O option only.
V
P15
2. VREF or I/O option only in the XCV200E, 300E, 400E;
otherwise, I/O option only.
3. VREF or I/O option only in the XCV400E; otherwise, I/O
option only.
P233
P227
GND
GND
NA
NA
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 7: PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E
PQ240 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
Other
Pair Bank P Pin
N Pin AO
Functions
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
P174
P171
P168
P163
P160
P157
P155
P153
P145
P142
P139
P134
P131
P128
P126
P124
P118
P114
P111
P108
P103
P100
P97
P173
P170
P167
P162
P159
P156
P154
P152
P144
P141
P138
P133
P130
P127
P125
P123
P117
P113
P110
P107
P102
P99
2
3
4
-
VREF
D1, VREF
D2
2
4
5
-
a differential pair or differential clock.
D3, VREF
.
Table 7: PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E
VREF
-
Other
4
2
D4, VREF
Pair Bank P Pin
N Pin AO
Functions
-
Global Differential Clock
D5
0
1
2
3
4
5
1
0
P92
P89
P93
P87
NA
NA
NA
NA
IO_DLL_L40P
IO_DLL_L40N
IO_DLL_L6P
IO_DLL_L6N
4
3
2
6
VREF
VREF
P210
P213
P209
-
P215
VREF
IO LVDS
Total Pairs: 64, Asynchronous Outputs Pairs: 27
INIT
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
2
P236
P234
P228
P223
P220
P217
P209
P205
P202
P199
P194
P191
P188
P186
P184
P178
P237
P235
P229
P224
P221
P218
P215
P206
P203
P200
P195
P192
P189
P187
P185
P177
1
VREF
-
-
-
2
VREF
VREF
3
-
VREF
4
3
3
-
-
5
VREF
3
3
-
6
NA
3
IO_LVDS_DLL
P96
VREF
7
VREF
-
P95
P94
7
VREF
8
3
P93
P87
NA
8
IO_LVDS_DLL
9
-
P84
P82
VREF
10
11
12
13
14
15
VREF
VREF
-
P79
P78
-
P74
P73
VREF
VREF
-
P71
P70
1
VREF
CS
P68
P67
P66
P65
1
VREF
-
DIN, D0
P64
P63
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
11
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 7: PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E
HQ240 High-Heat Quad Flat-Pack Packages
XCV600E and XCV1000E devices in High-heat dissipation
Quad Flat-pack packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as VREF, it can be used as general I/O. Immedi-
ately following Table 8, see Table 9 for Differential Pair infor-
mation.
Other
Pair Bank P Pin
N Pin AO
Functions
48
49
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
P56
P52
P49
P46
P41
P38
P35
P33
P27
P23
P20
P17
P12
P9
P57
-
P53
P50
P47
P42
P39
P36
P34
P28
P24
P21
P18
P13
P10
P7
2
3
4
-
50
VREF
Table 8: HQ240 — XCV600E, XCV1000E
51
VREF
Pin #
P240
P239
P238
P237
P236
P235
P234
P233
P232
P231
P230
P229
P228
P227
P226
P225
P224
P223
P222
P221
P220
P219
P218
P217
P216
P215
P214
P213
P212
P211
Pin Description
VCCO
Bank
7
52
-
53
2
4
5
-
TCK
NA
0
54
VREF
VREF
-
IO
55
IO_L0N
0
56
IO_VREF_L0P
IO_L1N_YY
IO_L1P_YY
GND
0
57
4
2
VREF
-
0
58
0
59
-
NA
0
VCCO
60
4
3
2
6
VREF
VREF
-
IO_VREF
IO_VREF
IO_VREF_L2N_YY
IO_L2P_YY
GND
0
61
0
62
P6
0
63
P4
P5
VREF
0
Notes:
1. AO in the XCV50E.
NA
0
2. AO in the XCV50E, 100E, 200E, 300E.
3. AO in the XCV50E, 200E, 300E, 400E.
4. AO in the XCV50E, 300E, 400E.
5. AO in the XCV100E, 200E, 400E.
6. AO in the XCV100E, 400E.
VCCO
VCCINT
NA
0
IO_L3N_YY
IO_L3P_YY
IO_VREF
IO_L4N_Y
IO_L4P_Y
GND
7. AO in the XCV50E, 200E, 400E.
8. AO in the XCV100E.
0
01
0
0
NA
0
IO_VREF_L5N_Y
IO_L5P_Y
IO_VREF
IO_LVDS_DLL_L6N
VCCINT
0
0
0
NA
0
GCK3
VCCO
0
GND
NA
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 8: HQ240 — XCV600E, XCV1000E
Table 8: HQ240 — XCV600E, XCV1000E
Pin #
P210
P209
P208
P207
P206
P205
P204
P203
P202
P2011
P200
P199
P198
P197
P196
P195
P194
P193
P192
P191
P190
P189
P188
P187
P186
P185
P184
P183
P182
P181
P180
P179
P178
P177
P176
P175
Pin Description
GCK2
Bank
1
Pin #
P174
P173
P172
P171
P170
P169
P168
P167
P166
P165
P164
P163
P162
P1611
P160
P159
P158
P157
P156
P155
P154
P153
P152
P151
P150
P149
P148
P147
P146
P145
P144
P143
P142
P141
P1401
P139
Pin Description
IO_L16P_Y
IO_L16N_Y
GND
Bank
2
IO_LVDS_DLL_L6P
IO_VREF
1
2
1
NA
2
VCCO
1
IO_VREF_L17P_Y
IO_L17N_Y
IO_VREF
IO_L7N_Y
1
2
IO_VREF_L7P_Y
GND
1
2
NA
1
IO_VREF_L18P_Y
IO_D1_L18N_Y
GND
2
IO_L8N_Y
2
IO_L8P_Y
1
NA
2
IO_VREF
1
VCCO
IO_L9N_YY
IO_L9P_YY
VCCINT
1
VCCINT
NA
2
1
IO_D2_L19P_YY
IO_L19N_YY
IO_VREF
NA
1
2
VCCO
2
GND
NA
1
IO_L20P_Y
IO_L20N_Y
GND
2
IO_L10N_YY
IO_VREF_L10P_YY
IO_VREF
2
1
NA
2
1
IO_VREF_L21P_Y
IO_D3_L21N_Y
IO_L22P_Y
IO_VREF_L22N_Y
IO_L23P_YY
IO_L23N_YY
GND
IO_L11N_YY
IO_VREF_L11P_YY
GND
1
2
1
2
NA
1
2
IO_L12N_YY
IO_L12P_YY
IO_VREF_L13N
IO_L13P
2
1
2
1
NA
2
1
VCCO
IO_WRITE_L14N_YY
IO_CS_L14P_YY
TDI
1
IO
3
1
VCCINT
NA
3
NA
NA
2
IO_VREF
GND
VCCO
3
TDO
IO_D4_L24P_Y
IO_VREF_L24N_Y
GND
3
VCCO
1
3
CCLK
2
NA
3
IO_DOUT_BUSY_L15P_YY
IO_DIN_D0_L15N_YY
VCCO
2
IO_L25P_Y
IO_L25N_Y
IO_VREF
2
3
2
3
IO_VREF
2
IO_L26P_YY
3
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
13
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 8: HQ240 — XCV600E, XCV1000E
Table 8: HQ240 — XCV600E, XCV1000E
Pin #
P138
P137
P136
P135
P134
P133
P132
P131
P130
P129
P128
P127
P126
P125
P124
P123
P122
P121
P120
P119
P118
P117
P116
P115
P114
P113
P112
P111
P110
P109
P108
P107
P106
P105
P104
P103
Pin Description
IO_D5_L26N_YY
VCCINT
Bank
3
Pin #
P102
P1011
P100
P99
P98
P97
P96
P95
P94
P93
P92
P91
P90
P89
P88
P87
P86
P85
P84
P83
P82
P81
P801
P79
P78
P77
P76
P75
P74
P73
P72
P71
P70
P69
P68
P67
Pin Description
IO_L36N_YY
IO_VREF
Bank
4
NA
3
4
VCCO
IO_L37P_Y
IO_L37N_Y
GND
4
GND
NA
3
4
IO_D6_L27P_Y
IO_VREF_L27N_Y
IO_VREF
NA
4
3
IO_VREF_L38P_Y
IO_L38N_Y
IO_L39P
3
4
IO_L28P_Y
IO_VREF_L28N_Y
GND
3
4
3
IO_VREF_L39N
IO_LVDS_DLL_L40P
GCK0
4
NA
3
4
IO_L29P_Y
IO_L29N_Y
IO_VREF_L30P_Y
IO_L30N_Y
IO_D7_L31P_YY
IO_INIT_L31N_YY
PROGRAM
VCCO
4
3
GND
NA
4
3
VCCO
3
GCK1
5
3
VCCINT
NA
5
3
IO_LVDS_DLL_L40N
IO_VREF
NA
3
5
VCCO
5
DONE
3
IO_VREF_L41P
GND
5
GND
NA
4
NA
5
IO_L32P_YY
IO_L32N_YY
VCCO
IO_L41N
4
IO
5
4
IO_VREF
5
IO_VREF
4
IO_L42P_YY
IO_L42N_YY
VCCINT
5
IO_L33P_YY
IO_L33N_YY
GND
4
5
4
NA
5
NA
4
VCCO
IO_VREF_L34P_YY
IO_L34N_YY
IO_VREF
GND
NA
5
4
IO_L43P_YY
IO_VREF_L43N_YY
IO_VREF
4
5
IO_VREF_L35P_YY
IO_L35N_YY
GND
4
5
4
IO_L44P_YY
IO_VREF_L44N_YY
GND
5
NA
4
5
VCCO
NA
5
VCCINT
NA
4
IO_L45P_YY
IO_L45N_YY
IO_L36P_YY
5
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 8: HQ240 — XCV600E, XCV1000E
Table 8: HQ240 — XCV600E, XCV1000E
Pin #
P66
P65
P64
P63
P62
P61
P60
P59
P58
P57
P56
P55
P54
P53
P52
P51
P50
P49
P48
P47
P46
P45
P44
P43
P42
P41
P401
P39
P38
P37
P36
P35
P34
P33
P32
P31
Pin Description
IO_VREF_L46P
IO_L46N
Bank
5
Pin #
P30
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P191
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
Pin Description
VCCO
Bank
6
5
GND
NA
7
IO_L47P_YY
IO_L47N_YY
M2
5
IO_L56N_YY
IO_L56P_YY
IO_VREF
5
7
NA
5
7
VCCO
VCCO
7
M0
NA
NA
NA
6
IO_L57N_Y
IO_VREF_L57P_Y
GND
7
GND
7
M1
NA
7
IO_L48N_YY
IO_L48P_YY
VCCO
IO_L58N_Y
IO_L58P_Y
IO_VREF
6
7
6
7
IO_VREF
IO_L49N_Y
IO_L49P_Y
GND
6
IO_L59N_YY
IO_L59P_YY
VCCINT
7
6
7
6
NA
7
NA
6
VCCO
IO_VREF_L50N_Y
IO_L50P_Y
IO_VREF
IO_VREF_L51N_Y
IO_L51P_Y
GND
GND
NA
7
6
IO_L60N_Y
IO_VREF_L60P_Y
IO_VREF
6
7
6
7
6
IO_L61N_Y
IO_VREF_L61P_Y
GND
7
NA
6
7
VCCO
P8
NA
7
VCCINT
NA
6
P7
IO_L62N_Y
IO_L62P_Y
IO_VREF_L63N_Y
IO_L63P_Y
IO
IO_L52N_YY
IO_L52P_YY
IO_VREF
IO_L53N_Y
IO_L53P_Y
GND
P6
7
6
P5
7
6
P4
7
6
P3
7
6
P2
TMS
NA
NA
NA
6
P1
GND
IO_VREF_L54N_Y
IO_L54P_Y
IO_L55N_Y
IO_VREF_L55P_Y
VCCINT
Notes:
1. REF or I/O option only in the XCV1000E; otherwise, I/O
option only.
V
6
6
6
NA
6
IO
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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1-800-255-7778
Module 4 of 4
15
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 9: HQ240 Differential Pin Pair Summary
XCV600E, XCV1000E
HQ240 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
P174
P171
P168
P163
P160
P157
P155
P153
P145
P142
P139
P134
P131
P128
P126
P124
P118
P114
P111
P108
P103
P100
P97
P173
P170
P167
P162
P159
P156
P154
P152
P144
P141
P138
P133
P130
P127
P125
P123
P117
P113
P110
P107
P102
P99
-
VREF
D1
D2
-
D3
Table 9: HQ240 Differential Pin Pair Summary
XCV600E, XCV1000E
1
VREF
-
P
N
Other
D4, VREF
Pair Bank
Pin
Pin
AO
Functions
-
Global Differential Clock
D5
0
1
2
3
4
5
1
0
P92
P89
P93
P87
NA
NA
NA
NA
IO _DLL_L40P
IO _DLL_L40N
IO _DLL_L6P
IO _DLL_L6N
VREF
VREF
P210
P213
P209
-
P215
1
VREF
IO LVDS
Total Pairs: 64, Asynchronous Output Pairs: 53
INIT
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
2
P236
P234
P228
P223
P220
P217
P209
P205
P202
P199
P194
P191
P188
P186
P184
P178
P237
P235
P229
P224
P221
P218
P215
P206
P203
P200
P195
P192
P189
P187
P185
P177
NA
VREF
-
-
-
2
VREF
VREF
3
-
VREF
4
-
-
5
VREF
-
6
NA
IO_LVDS_DLL
P96
VREF
7
VREF
-
P95
P94
NA
NA
NA
VREF
8
P93
P87
IO_LVDS_DLL
9
-
P84
P82
VREF
10
11
12
13
14
15
VREF
VREF
-
P79
P78
-
P74
P73
VREF
VREF
-
P71
P70
NA
VREF
CS
P68
P67
P66
P65
NA
VREF
-
DIN, D0
P64
P63
Module 4 of 4
16
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 9: HQ240 Differential Pin Pair Summary
XCV600E, XCV1000E
BG352 Ball Grid Array Packages
XCV100E, XCV200E, and XCV300E devices in BG352 Ball
Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as VREF, it can be used as general I/O. Immedi-
ately following Table 10, see Table 11 for Differential Pair
information.
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
P56
P52
P49
P46
P41
P38
P35
P33
P27
P23
P20
P17
P12
P9
P57
P53
P50
P47
P42
P39
P36
P34
P28
P24
P21
P18
P13
P10
P7
-
-
VREF
Table 10: BG352 — XCV100E, XCV200E, XCV300E
VREF
Bank
0
Pin Description
Pin #
D22
C231
B241
C22
D212
B23
A241
A23
D20
C21
B22
B211
C201
B20
A21
D18
C19
B19
D17
C18
B181
C17
A18
D161
B17
C16
A16
D15
-
IO
-
0
IO
IO
VREF
VREF
-
0
1
0
IO
0
IO_VREF_0_L0N_YY
IO_L0P_YY
IO
VREF
-
0
0
-
0
IO_L1N_YY
IO_L1P_YY
IO_VREF_0_L2N_YY
IO_L2P_YY
IO
VREF
VREF
-
0
0
P6
0
P4
P5
1
VREF
0
Note 1: AO in the XCV600E.
0
IO
0
IO_L3N
0
IO_L3P
0
IO
0
IO_VREF_0_L4N_YY
IO_L4P_YY
IO_L5N_YY
IO_L5P_YY
IO
0
0
0
0
0
IO_L6N
0
IO_L6P
0
IO
0
IO_L7N_Y
IO_L7P_Y
IO_VREF_0_L8N_Y
IO_L8P_Y
0
0
0
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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1-800-255-7778
Module 4 of 4
17
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank
Pin Description
Pin #
C15
B151
A15
Bank
Pin Description
Pin #
B4
0
0
0
0
IO
1
1
1
1
1
IO
IO
IO
C51
A31
D5
IO_LVDS_DLL_L9N
GCK3
IO
D14
IO_WRITE_L20N_YY
IO_CS_L20P_YY
C4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GCK2
IO_LVDS_DLL_L9P
IO
B14
A13
B131
C13
A12
B12
C12
A11
B11
B101
C11
D11
A91
B9
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_DOUT_BUSY_L21P_YY
E4
D3
C21
E31
F4
IO_DIN_D0_L21N_YY
IO_L10N
IO
IO
IO_L10P
IO_L11N_Y
IO_VREF_1_L11P_Y
IO_L12N_Y
IO_L12P_Y
IO
IO
IO_VREF_2_L22P_YY
IO_L22N_YY
IO
D22
C1
D11
G4
F3
IO_L23P_YY
IO_L23N_YY
IO_VREF_2_L24P_Y
IO_L24N_Y
IO
IO_L13N
IO_L13P
E2
IO
F2
IO_L14N_YY
IO_L14P_YY
IO_L15N_YY
IO_VREF_1_L15P_YY
IO_L16N _Y
IO_L16P _Y
IO
G31
G21
F1
C10
B8
IO
IO_L25P
C9
IO_L25N
J4
D9
IO
H3
H2
G1
J3
A7
IO_VREF_2_L26P _Y
IO_D1_L26N _Y
IO_D2_L27P_YY
IO_L27N_YY
IO
B7
IO
C81
D81
A6
IO
J2
IO_L17N_YY
IO_VREF_1_L17P_YY
IO_L18N_YY
IO_L18P_YY
IO
K31
J1
B6
IO_L28P
C7
IO_L28N
L4
A4
IO
K21
L3
B51
C6
IO_L29P_YY
IO_L29N_YY
IO_VREF_2_L30P _Y
IO_L19N_YY
IO_VREF_1_L19P_YY
L2
D62
M4
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank
Pin Description
IO_D3_L30N _Y
IO_L31P
Pin #
M3
Bank
Pin Description
Pin #
AC22
AB3
2
2
2
2
2
2
3
3
3
3
3
3
IO_VREF_3_L42N_YY
M2
IO
IO_L31N
M1
IO
AD11
AB41
AC3
IO
N31
N4
IO
IO_L32P_YY
IO_L32N_YY
IO_D7_L43P_YY
IO_INIT_L43N_YY
N2
AD2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
IO
P1
P31
R1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
IO_L44P_YY
AC5
AD4
IO_L44N_YY
IO_L33P
IO
IO
AE31
AD51
AC6
IO_L33N
R2
IO_D4_L34P _Y
IO_VREF_3_L34N _Y
IO_L35P_YY
IO_L35N_YY
IO
R3
IO
R4
IO_VREF_4_L45P_YY
IO_L45N_YY
IO
AE42
AF3
T2
U2
AF41
AC7
T31
T4
IO_L46P_YY
IO_L46N_YY
IO_VREF_4_L47P_YY
IO_L47N_YY
IO
IO_L36P
AD6
IO_L36N
V1
AE5
IO
V21
U3
AE6
IO_L37P_YY
IO_D5_L37N_YY
IO_D6_L38P _Y
IO_VREF_3_L38N _Y
IO_L39P _Y
IO_L39N _Y
IO
AD71
AE71
AF6
U4
IO
V3
IO_L48P
V4
IO_L48N
AC9
Y1
IO
AD8
Y2
IO_VREF_4_L49P_YY
IO_L49N_YY
IO_L50P_YY
IO_L50N_YY
IO
AE8
W3
W41
AA11
AA2
Y3
AF7
IO
AD9
IO
AE9
IO_L40P_Y
IO_VREF_3_L40N_Y
IO_L41P_YY
IO_L41N_YY
IO
AD101
AF9
IO_L51P
AC1
AB2
AA31
AA4
IO_L51N
AC11
AE101
AD11
AE11
IO
IO_L52P_Y
IO_L52N_Y
IO_L42P_YY
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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1-800-255-7778
Module 4 of 4
19
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank
Pin Description
IO_VREF_4_L53P_Y
IO_L53N_Y
IO_L54P
Pin #
AC12
AD12
AE12
AF12
AD131
AC13
AE13
Bank
Pin Description
Pin #
AC21
AE232
AD22
AF241
AC221
4
4
4
4
4
4
4
5
5
5
5
5
IO_L64P_YY
IO_VREF_5_L64N_YY
IO
IO
IO
IO_L54N
IO
IO_LVDS_DLL_L55P
GCK0
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L65N_YY
IO_L65P_YY
IO
AC24
AD25
AB241
AA231
AC25
AD262
AC26
Y231
AA24
AB25
AA25
Y24
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
IO_LVDS_DLL_L55N
IO
AF14
AD14
AF151
AE15
AD15
AC15
AE16
AE17
AD161
AC16
AF18
AE181
AD17
AC17
AD18
AC18
AF20
AE20
AD19
AC191
AF211
AE21
AD20
AF23
AE22
AD211
IO
IO
IO
IO_VREF_6_L66N_YY
IO_L66P_YY
IO
IO_L56P_Y
IO_VREF_5_L56N_Y
IO_L57P_Y
IO_L57N_Y
IO
IO_L67N_YY
IO_L67P_YY
IO_VREF_6_L68N_Y
IO_L68P_Y
IO
IO_L58P
IO_L58N
Y251
AA261
V23
IO
IO
IO_L59P_YY
IO_L59N_YY
IO_L60P_YY
IO_VREF_5_L60N_YY
IO_L61P _Y
IO_L61N _Y
IO
IO_L69N
IO_L69P
W24
W25
Y26
IO
IO_VREF_6_L70N _Y
IO_L70P _Y
IO_L71N_YY
IO_L71P_YY
IO
U23
V25
U24
IO
V261
T23
IO
IO_L72N
IO_L62P_YY
IO_VREF_5_L62N_YY
IO_L63P_YY
IO_L63N_YY
IO
IO_L72P
U25
IO
T241
T25
IO_L73N_YY
IO_L73P_YY
IO_VREF_6_L74N _Y
T26
R24
Module 4 of 4
20
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank
Pin Description
IO_L74P _Y
IO_L75N
IO_L75P
IO
Pin #
R25
R26
P24
Bank
Pin Description
Pin #
E242
C26
6
6
6
6
6
7
7
7
7
7
IO_VREF_7_L86P_YY
IO
IO
IO
IO
E231
D241
C25
P231
N26
IO
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L76N_YY
IO_L76P_YY
IO
N25
N24
M261
M25
M24
M23
L26
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
TDI
TDO
B3
D4
CCLK
TCK
C3
IO_L77N
C24
IO_L77P
TMS
D23
IO_L78N _Y
IO_VREF_7_L78P _Y
IO_L79N_YY
IO_L79P_YY
IO
PROGRAM
DONE
DXN
AC4
AD3
AD23
AE24
AC23
AD24
AB23
K25
L24
DXP
L231
J26
M2
IO_L80N
M0
IO_L80P
J25
M1
IO
K241
K23
H25
J23
IO_L81N_YY
IO_L81P_YY
IO_L82N _Y
IO_VREF_7_L82P _Y
IO_L83N _Y
IO_L83P _Y
IO
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
A20
B16
C14
D12
D10
K4
G26
G25
H24
H23
F261
F251
G24
D26
E25
F24
F231
D25
L1
IO
P2
IO
T1
IO_L84N_Y
IO_VREF_7_L84P_Y
IO_L85N_YY
IO_L85P_YY
IO
W2
AC10
AF11
AE14
AF16
AE19
IO_L86N_YY
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
21
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank
NA
Pin Description
VCCINT
Pin #
V24
R23
P25
L25
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
A19
A14
A8
NA
VCCINT
NA
VCCINT
NA
VCCINT
A5
NA
VCCINT
J24
A2
A1
0
0
0
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
D19
B25
A17
D13
D7
B26
B1
E26
E1
H26
H1
A10
K1
N1
H4
P26
W26
W1
B2
Y4
U1
AB26
AB1
AE26
AE1
AF26
AF25
AF22
AF19
AF13
AF8
AF5
AF2
AF1
P4
AF10
AE2
AC8
AF17
AC20
AC14
AE25
W23
U26
N23
K26
G23
Notes:
1. No Connect in the XCV100E.
2. VREF or I/O option only in the XCV200E and XCV300E;
otherwise, I/O option only.
NA
NA
NA
GND
GND
GND
A26
A25
A22
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 11: BG352 Differential Pin Pair Summary
XCV100E, XCV200E, XCV300E
BG352 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
check ( in the AO column indicates that the pin pair can be
used as an asynchronous output for all devices provided in
this package. Pairs with a note number in the AO column
are device dependent. They can have asynchronous out-
puts if the pin pair are in the same CLB row and column in
the device. Numbers in this column refer to footnotes that
indicate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates alter-
native function(s) not available when the pair is used as a
differential pair or differential clock
P
N
Pin
C6
Other
Pair
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Bank
1
1
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
Pin
D6
AO
Functions
VREF_1
C4
D5
CS
E4
D3
DIN_D0
D2
C1
VREF_2
G4
F3
-
E2
F2
VREF_2
F1
J4
2
1
-
Table 11: BG352 Differential Pin Pair Summary
XCV100E, XCV200E, XCV300E
H2
G1
D1
P
N
Other
J3
J2
D2
Pair
Bank
Pin
Pin
AO
Functions
J1
L4
-
Global Differential Clock
AE13 AC13 NA
AF14 AD14 NA
L3
L2
-
0
1
2
3
4
5
1
0
IO LVDS 55
IO LVDS 55
IO LVDS 9
IO LVDS 9
M4
M2
N4
M3
M1
N2
D3
2
2
-
B14
D14
A13
A15
NA
NA
-
R1
R2
-
IO LVDS
R3
R4
VREF_3
Total Outputs: 87, Asynchronous Output Pairs: 43
T2
U2
-
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
B23
D20
B22
A21
B19
C18
A18
C16
D15
A13
A12
C12
B11
D11
C10
C9
D21
A23
C21
B20
C19
D17
C17
B17
A16
A15
C13
B12
A11
C11
B9
VREF_0
T4
V1
1
1
-
-
U3
U4
D5
2
VREF_0
V3
V4
VREF_3
3
2
2
-
Y1
Y2
-
4
VREF_0
AA2
AC1
AA4
AC3
AC5
AE4
AC7
AE5
AF6
AE8
AD9
AF9
Y3
VREF_3
5
-
AB2
AC2
AD2
AD4
AF3
AD6
AE6
AC9
AF7
AE9
AC11
-
6
-
VREF_3
7
-
INIT
8
VREF_0
-
9
GCLK LVDS 3/2
VREF_4
10
11
12
13
14
15
16
17
18
2
2
1
-
-
VREF_1
VREF_4
-
2
2
2
-
-
VREF_4
-
-
B8
VREF_1
-
A7
D9
-
AD11 AE11
AC12 AD12
AE12 AF12
-
B6
A6
VREF_1
-
VREF_4
-
A4
C7
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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1-800-255-7778
Module 4 of 4
23
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 11: BG352 Differential Pin Pair Summary
XCV100E, XCV200E, XCV300E
BG432 Ball Grid Array Packages
XCV300E, XCV400E, and XCV600E devices in BG432 Ball
Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as VREF, it can be used as general I/O. Immedi-
ately following Table 12, see Table 13 for Differential Pair
information.
P
N
Other
Pair
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
Notes:
Bank
5
Pin
Pin
AO
Functions
AC13 AD14
AD15 AC15
AE16 AE17
AC16 AF18
AD17 AC17
AD18 AC18
AF20 AE20
AE21 AD20
AF23 AE22
AC21 AE23
AD25 AC24
AC26 AD26
AB25 AA24
GCLK LVDS 1/0
5
VREF_5
5
-
Table 12: BG432 — XCV300E, XCV400E, XCV600E
5
2
1
-
Bank
0
Pin Description
GCK3
Pin #
D17
A22
A26
B20
C23
C28
B29
D27
B28
C27
D26
A28
B27
C26
D25
A27
D24
C25
B25
D23
C241
B24
D22
A24
C22
B22
C21
D20
B21
C20
5
-
5
VREF_5
0
IO
5
-
0
IO
5
VREF_5
5
-
0
IO
5
VREF_5
0
IO
6
-
0
IO
6
VREF_6
0
IO_L0N_Y
IO_L0P_Y
IO_L1N_YY
IO_L1P_YY
IO_VREF_L2N_YY
IO_L2P_YY
IO_L3N_Y
IO_L3P_Y
IO_L4N_YY
IO_L4P_YY
IO_VREF_L5N_YY
IO_L5P_YY
IO_L6N_Y
IO_L6P_Y
IO_VREF_L7N_Y
IO_L7P_Y
IO_VREF_L8N_YY
IO_L8P_YY
IO_L9N_YY
IO_L9P_YY
IO_L10N_YY
IO_L10P_YY
IO_L11N_YY
IO_L11P_YY
6
-
0
6
Y24
W24
U23
U24
U25
T26
R25
P24
N24
M24
L26
L24
J25
AA25
V23
Y26
V25
T23
T25
R24
R26
N25
M25
M23
K25
J26
VREF_6
0
6
2
1
-
0
6
VREF_6
0
6
-
0
6
-
0
6
-
0
6
VREF_6
0
6
2
2
-
0
7
-
0
7
-
0
7
VREF_7
0
7
-
0
7
1
1
-
0
7
H25
G26
H24
D26
F24
E24
K23
J23
-
0
7
VREF_7
0
7
G25
G24
E25
D25
-
0
7
VREF_7
-
0
7
0
7
VREF_7
0
1. AO in the XCV100E.
2. AO in the XCV200E.
0
0
0
Module 4 of 4
24
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1-800-255-7778
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank
Pin Description
IO_L12N_YY
Pin #
A20
D19
B19
A19
B18
D18
C182
B17
C17
Bank
Pin Description
IO_L26P_Y
Pin #
B8
C8
B7
D8
A6
B6
D7
A5
C6
B5
D6
A4
C5
B4
D5
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L12P_YY
IO_L27N_YY
IO_VREF_L13N_YY
IO_L13P_YY
IO_VREF_L27P_YY
IO_L28N_YY
IO_L14N_Y
IO_L28P_YY
IO_L14P_Y
IO_L29N_Y
IO_VREF_L15N_Y
IO_L15P_Y
IO_L29P_Y
IO_L30N_YY
IO_LVDS_DLL_L16N
IO_VREF_L30P_YY
IO_L31N_YY
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GCK2
IO
A16
A12
B9
IO_L31P_YY
IO_L32N_Y
IO
IO_L32P_Y
IO
B11
C16
D9
IO_WRITE_L33N_YY
IO_CS_L33P_YY
IO
IO
IO_LVDS_DLL_L16P
IO_L17N_Y
IO_L17P_Y
IO_L18N_Y
IO_L18P_Y
IO_L19N_YY
IO_VREF_L19P_YY
IO_L20N_YY
IO_L20P_YY
IO_L21N_YY
IO_L21P_YY
IO_L22N_YY
IO_L22P_YY
IO_L23N_YY
IO_L23P_YY
IO_L24N_YY
IO_VREF_L24P_YY
IO_L25N_Y
IO_VREF_L25P_Y
IO_L26N_Y
B16
A15
B152
C15
D15
B14
A13
B13
D14
C13
B12
D13
C12
D12
C11
B10
C10
C9
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO
IO
H4
J3
IO
L3
IO
M1
R2
D3
C2
D2
E4
D1
E3
E2
F4
E1
F3
F2
G4
G3
G2
H3
IO
IO_DOUT_BUSY_L34P_YY
IO_DIN_D0_L34N_YY
IO_L35P
IO_L35N
IO_L36P_Y
IO_L36N_Y
IO_VREF_L37P_Y
IO_L37N_Y
IO_L38P
IO_L38N
IO_L39P_Y
IO_L39N_Y
IO_VREF_L40P_YY
IO_L40N_YY
IO_L41P_Y
D101
A8
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
25
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank
2
Pin Description
IO_L41N_Y
Pin #
H2
H11
J4
Bank
3
Pin Description
IO_L56N_Y
Pin #
Y3
2
IO_VREF_L42P_Y
IO_L42N_Y
3
IO_L57P_Y
Y4
2
3
IO_L57N_Y
Y2
2
IO_VREF_L43P_YY
IO_D1_L43N_YY
IO_D2_L44P_YY
IO_L44N_YY
IO_L45P_Y
J2
3
IO_L58P_YY
IO_D5_L58N_YY
IO_D6_L59P_YY
IO_VREF_L59N_YY
IO_L60P_Y
AA3
AB1
AB3
AB4
AD1
AC31
AC4
AD2
AD3
AD4
AF2
AE3
AE4
AG1
AG2
AF3
AF4
AH1
AH2
AG3
AG4
AJ2
T2
2
K4
K2
K1
L2
3
2
3
2
3
2
3
2
IO_L45N_Y
M4
M3
M2
N4
N3
N1
P4
P3
P2
R32
R4
R1
T3
3
IO_VREF_L60N_Y
IO_L61P_Y
2
IO_L46P_Y
3
2
IO_L46N_Y
3
IO_L61N_Y
2
IO_L47P_Y
3
IO_L62P_YY
IO_VREF_L62N_YY
IO_L63P_Y
2
IO_L47N_Y
3
2
IO_VREF_L48P_YY
IO_D3_L48N_YY
IO_L49P_Y
3
2
3
IO_L63N_Y
2
3
IO_L64P
2
IO_L49N_Y
3
IO_L64N
2
IO_VREF_L50P_Y
IO_L50N_Y
3
IO_L65P_Y
2
3
IO_VREF_L65N_Y
IO_L66P_Y
2
IO_L51P_YY
IO_L51N_YY
3
2
3
IO_L66N_Y
3
IO_L67P
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
IO
AA2
AC2
AE2
U3
3
IO_L67N
3
IO_D7_L68P_YY
IO_INIT_L68N_YY
IO
IO
3
IO
3
IO
W1
U4
IO_L52P_Y
IO_VREF_L52N_Y
IO_L53P_Y
IO_L53N_Y
IO_D4_L54P_YY
IO_VREF_L54N_YY
IO_L55P_Y
IO_L55N_Y
IO_L56P_Y
4
4
4
4
4
4
4
4
4
GCK0
AL16
AH10
AJ11
AK7
U22
U1
IO
IO
IO
V3
V4
IO
AL12
AL15
AJ4
V2
IO
W3
W4
Y1
IO_L69P_YY
IO_L69N_YY
IO_L70P_Y
AK3
AH5
Module 4 of 4
26
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank
4
Pin Description
IO_L70N_Y
Pin #
AK4
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO
Pin #
AJ23
AJ24
AL17
AK17
AJ172
AH17
AK18
AL19
AJ18
AH18
AL20
AK20
AH19
AJ20
AK21
AJ21
AL22
AJ22
AK23
AH22
AL241
AK24
AH23
AK25
AJ25
AL26
AK26
AH25
AL27
AJ26
AK27
AH26
AL28
AJ27
AK28
4
IO_L71P_YY
IO_L71N_YY
IO_VREF_L72P_YY
IO_L72N_YY
IO_L73P_Y
AJ5
IO
4
AH6
IO_LVDS_DLL_L86N
IO_L87P_Y
4
AL4
4
AK5
IO_VREF_L87N_Y
IO_L88P_Y
4
AJ6
4
IO_L73N_Y
AH7
AL5
IO_L88N_Y
4
IO_L74P_YY
IO_L74N_YY
IO_VREF_L75P_YY
IO_L75N_YY
IO_L76P_Y
IO_L89P_YY
IO_VREF_L89N_YY
IO_L90P_YY
IO_L90N_YY
IO_L91P_YY
IO_L91N_YY
IO_L92P_YY
IO_L92N_YY
IO_L93P_YY
IO_L93N_YY
IO_L94P_YY
IO_VREF_L94N_YY
IO_L95P_Y
4
AK6
4
AJ7
4
AL6
4
AH9
AJ8
4
IO_L76N_Y
4
IO_VREF_L77P_Y
IO_L77N_Y
AK81
AJ9
4
4
IO_VREF_L78P_YY
IO_L78N_YY
IO_L79P_YY
IO_L79N_YY
IO_L80P_YY
IO_L80N_YY
IO_L81P_YY
IO_L81N_YY
IO_L82P_YY
IO_L82N_YY
IO_VREF_L83P_YY
IO_L83N_YY
IO_L84P_Y
AL8
4
AK9
4
AK10
AL10
AH12
AK11
AJ12
AK12
AH13
AJ13
AL13
AK14
AH14
AJ14
AK152
AJ15
AH15
4
4
4
IO_VREF_L95N_Y
IO_L96P_Y
4
4
IO_L96N_Y
4
IO_L97P_YY
IO_VREF_L97N_YY
IO_L98P_YY
IO_L98N_YY
IO_L99P_Y
4
4
4
4
4
IO_L84N_Y
IO_L99N_Y
4
IO_VREF_L85P_Y
IO_L85N_Y
IO_L100P_YY
IO_VREF_L100N_YY
IO_L101P_YY
IO_L101N_YY
IO_L102P_Y
IO_L102N_Y
4
4
IO_LVDS_DLL_L86P
5
5
5
GCK1
IO
AK16
AH20
AJ19
IO
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Preliminary Product Specification
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Module 4 of 4
27
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO
Pin #
AA30
AC30
AD29
U31
Bank
Pin Description
IO_L118P_Y
IO_VREF_L119N_Y
IO_L119P_Y
IO
Pin #
U29
U282
U30
T30
6
6
6
6
IO
IO
IO
IO
W28
IO_L103N_YY
IO_L103P_YY
IO_L104N
AJ30
AH30
AG28
AH31
AG29
AG30
AF28
AG31
AF29
AF30
AE28
AF31
AE30
AD28
AD30
AD31
AC281
AC29
AB28
AB29
AB31
AA29
Y28
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO
IO
C30
H29
H31
L29
IO
IO_L104P
IO
IO_L105N_Y
IO_L105P_Y
IO_VREF_L106N_Y
IO_L106P_Y
IO_L107N
IO
M31
R28
T31
R29
R30
R312
P29
P28
P30
N30
N28
N31
M29
M28
M30
L30
IO
IO_L120N_YY
IO_L120P_YY
IO_L121N_Y
IO_VREF_L121P_Y
IO_L122N_Y
IO_L122P_Y
IO_L123N_YY
IO_VREF_L123P_YY
IO_L124N_Y
IO_L124P_Y
IO_L125N_Y
IO_L125P_Y
IO_L126N_Y
IO_L126P_Y
IO_L127N_YY
IO_L127P_YY
IO_L128N_YY
IO_VREF_L128P_YY
IO_L129N_Y
IO_VREF_L129P_Y
IO_L130N_Y
IO_L130P_Y
IO_L131N_YY
IO_VREF_L131P_YY
IO_L132N_Y
IO_L107P
IO_L108N_Y
IO_L108P_Y
IO_VREF_L109N_YY
IO_L109P_YY
IO_L110N_Y
IO_L110P_Y
IO_VREF_L111N_Y
IO_L111P_Y
IO_VREF_L112N_YY
IO_L112P_YY
IO_L113N_YY
IO_L113P_YY
IO_L114N_Y
IO_L114P_Y
IO_L115N_Y
IO_L115P_Y
IO_L116N_Y
IO_L116P_Y
IO_VREF_L117N_YY
IO_L117P_YY
IO_L118N_Y
K31
K30
K28
J30
Y29
Y30
J29
Y31
J281
H30
G30
H28
F31
G29
W29
W30
V28
V29
V30
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank
Pin Description
IO_L132P_Y
IO_L133N
Pin #
G28
E31
E30
F29
F28
D31
D30
E29
E28
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin #
T1
7
7
7
7
7
7
7
7
7
T29
IO_L133P
W2
IO_L134N_Y
IO_VREF_L134P_Y
IO_L135N_Y
IO_L135P_Y
IO_L136N
W31
AB2
AB30
AE29
AF1
IO_L136P
AH8
AH24
AJ10
AJ16
AK22
AK13
AK19
2
CCLK
DONE
DXN
D4
AH4
AH27
AK29
AH28
AH29
AJ28
AH3
D28
3
NA
NA
NA
NA
NA
NA
NA
NA
2
DXP
M0
M1
M2
0
0
0
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
A21
C29
D21
A1
PROGRAM
TCK
TDI
B3
TDO
C4
A11
D11
C3
NA
TMS
D29
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
A10
A17
B23
B26
C7
L4
L1
AA1
AA4
AJ3
C14
C19
F1
AH11
AL1
AL11
AH21
AL21
AJ29
AA28
AA31
F30
K3
K29
N2
N29
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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1-800-255-7778
Module 4 of 4
29
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Table 12: BG432 — XCV300E, XCV400E, XCV600E
Bank
Pin Description
VCCO
Pin #
AL31
A31
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
Pin #
AH16
AJ1
6
7
7
7
VCCO
GND
VCCO
L28
GND
AJ31
AK1
VCCO
L31
GND
GND
AK2
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A2
A3
GND
AK30
AK31
AL2
GND
A7
GND
A9
GND
AL3
A14
A18
A23
A25
A29
A30
B1
GND
AL7
GND
AL9
GND
AL14
AL18
AL23
AL25
AL29
AL30
GND
GND
GND
GND
B2
GND
Notes:
B30
B31
C1
1. VREF or I/O option only in the XCV600E; otherwise, I/O
option only.
2. VREF or I/O option only in the XCV400E, XCV600E;
otherwise, I/O option only.
C31
D16
G1
G31
J1
J31
P1
P31
T4
T28
V1
V31
AC1
AC31
AE1
AE31
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E
BG432 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also Vir-
tex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Pair Bank
P
N
AO
Other
Pin
Pin
Functions
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
B16
B15
D15
A13
D14
B12
C12
C11
C10
D10
B8
C17
A15
C15
B14
B13
C13
D13
D12
B10
C9
NA
1
IO_LVDS_DLL
VREF
1
-
VREF
-
-
-
Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E
-
Pair Bank
P
N
AO
Other
VREF
Pin
Pin
Functions
1
1
VREF
Global Differential Clock
A8
-
0
1
2
3
4
5
1
0
AL16
AK16
A16
AH15
AL17
B16
NA
NA
NA
NA
IO_DLL_L86P
IO_DLL_L86N
IO_DLL_L16P
IO_DLL_L16N
B7
C8
VREF
A6
D8
-
D7
B6
2
1
-
D17
C17
C6
A5
VREF
IO LVDS
D6
B5
-
Total Outputs: 137, Asynchronous Output Pairs: 63
C5
A4
-
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D27
C27
A28
C26
A27
C25
D23
B24
A24
B22
D20
C20
D19
A19
D18
B17
B29
B28
D26
B27
D25
D24
B25
C24
D22
C22
C21
B21
A20
B19
B18
C18
1
2
-
D5
B4
CS, WRITE
-
D3
C2
DIN, D0, BUSY
2
VREF
D2
E4
3
4
1
5
1
-
3
-
D1
E3
-
4
-
E2
F4
VREF
5
VREF
E1
F3
-
6
1
1
-
F2
G4
G2
H2
-
7
VREF
G3
H3
VREF
8
VREF
4
1
-
9
-
H1
J4
VREF
10
11
12
13
14
15
-
J2
K4
D1
-
K2
K1
D2
-
L2
M4
M2
N3
4
1
1
-
-
-
VREF
-
M3
N4
1
1
VREF
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 13: BG432 Differential Pin Pair Summary
Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E
XCV300E, XCV400E, XC600E
Pair Bank
P
N
AO
Other
Pair Bank
P
N
AO
Other
Pin
Pin
Functions
Pin
Pin
Functions
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
N1
P3
P4
P2
D3
80
81
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
AH12
AJ12
AH13
AL13
AH14
AK15
AH15
AK17
AH17
AL19
AH18
AK20
AJ20
AJ21
AJ22
AH22
AK24
AK25
AL26
AH25
AJ26
AH26
AJ27
AH30
AH31
AG30
AG31
AF30
AF31
AD28
AD31
AC29
AK11
AK12
AJ13
AK14
AJ14
AJ15
AL17
AJ17
AK18
AJ18
AL20
AH19
AK21
AL22
AK23
AL24
AH23
AJ25
AK26
AL27
AK27
AL28
AK28
AJ30
AG28
AG29
AF28
AF29
AE28
AE30
AD30
AC28
-
4
1
-
-
R3
R4
VREF
82
-
R1
T3
-
83
VREF
U4
U2
1
4
VREF
84
1
1
-
U1
V3
-
85
VREF
V4
V2
VREF
86
NA
1
IO_LVDS_DLL
W3
W4
1
1
4
-
87
VREF
Y1
Y3
-
88
1
-
Y4
Y2
-
89
VREF
AA3
AB3
AD1
AC4
AD3
AF2
AE4
AG2
AF4
AH2
AG4
AJ4
AH5
AJ5
AL4
AJ6
AL5
AJ7
AH9
AK8
AL8
AK10
AB1
AB4
AC3
AD2
AD4
AE3
AG1
AF3
AH1
AG3
AJ2
AK3
AK4
AH6
AK5
AH7
AK6
AL6
AJ8
AJ9
AK9
AL10
D5
90
-
VREF
91
-
1
4
VREF
92
-
-
93
-
VREF
94
VREF
1
5
1
4
3
-
95
1
1
VREF
-
96
-
VREF
97
VREF
-
98
-
-
99
2
1
-
INIT
100
101
102
103
104
105
106
107
108
109
110
111
VREF
-
-
1
2
-
-
-
-
VREF
3
4
1
5
1
-
-
-
-
VREF
VREF
-
-
1
1
-
VREF
VREF
-
VREF
-
4
1
VREF
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E
BG560 Ball Grid Array Packages
XCV1000E, XCV1600E, and XCV2000E devices in BG560
Ball Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as VREF, it can be used as general I/O. Immedi-
ately following Table 14, see Table 15 for Differential Pair
information.
Pair Bank
P
N
AO
Other
Pin
Pin
Functions
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
Notes:
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
AB29
AA29
Y29
Y31
W30
V29
U29
U30
R29
R31
P28
N30
N31
M28
L30
AB28
AB31
Y28
Y30
W29
V28
V30
U28
T31
R30
P29
P30
N28
M29
M30
K31
K28
J29
VREF
-
4
1
1
-
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
-
-
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
GCK3
Pin#
A17
A27
B25
C28
C30
D30
E28
D29
D28
A31
E27
C29
B30
D27
E26
B29
D26
C27
E25
A28
D25
C26
E24
B26
C25
D24
E23
A25
D23
See Note
VREF
IO
4
1
-
IO
VREF
IO
-
IO
1
4
VREF
IO
-
IO_L0N
VREF
IO_VREF_L0P
IO_L1N_YY
IO_L1P_YY
IO_VREF_L2N_YY
IO_L2P_YY
IO_L3N_Y
IO_L3P_Y
IO_L4N_YY
IO_L4P_YY
IO_VREF_L5N_YY
IO_L5P_YY
IO_L6N_Y
IO_VREF_L6P_Y
IO_L7N_Y
IO_L7P_Y
IO_VREF_L8N_Y
IO_L8P_Y
IO_L9N_Y
IO_L9P_Y
IO_VREF_L10N_YY
IO_L10P_YY
IO_L11N_YY
3
1
1
4
-
-
-
K30
J30
-
VREF
J28
1
4
VREF
G30
F31
G28
E30
F28
D30
E28
H30
H28
G29
E31
F29
D31
E29
-
VREF
1
5
1
4
3
-
-
VREF
-
-
1
4
1. AO in the XCV300E, 600E.
2. AO in the XCV300E.
3. AO in the XCV400E, 600E.
4. AO in the XCV300E, 400E.
5. AO in the XCV600E.
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
33
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
0
Pin Description
IO_L11P_YY
IO_L12N_Y
Pin#
B24
E22
C23
A23
D22
E21
B22
D21
C21
B21
E20
D20
C20
B20
E19
D19
C19
A19
D18
C18
E18
See Note
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L25P_Y
Pin#
C15
D15
E15
C14
D14
A13
E14
C13
D13
C12
E13
A11
D12
B11
C11
B10
D11
C10
A9
See Note
0
IO_L26N_YY
IO_VREF_L26P_YY
IO_L27N_YY
IO_L27P_YY
IO_L28N_Y
0
IO_L12P_Y
0
IO_L13N_YY
IO_L13P_YY
IO_VREF_L14N_YY
IO_L14P_YY
IO_L15N_Y
0
0
3
0
IO_L28P_Y
0
IO_L29N_YY
IO_VREF_L29P_YY
IO_L30N_YY
IO_L30P_YY
IO_L31N_Y
0
IO_L15P_Y
3
0
IO_L16N_YY
IO_L16P_YY
IO_VREF_L17N_YY
IO_L17P_YY
IO_L18N_Y
0
0
0
IO_L31P_Y
0
IO_L32N_YY
IO_L32P_YY
IO_L33N_YY
IO_VREF_L33P_YY
IO_L34N_Y
0
IO_L18P_Y
0
IO_L19N_Y
0
IO_L19P_Y
0
IO_VREF_L20N_Y
IO_L20P_Y
0
IO_L34P_Y
0
IO_LVDS_DLL_L21N
IO_VREF
IO_L35N_Y
C9
0
2
IO_VREF_L35P_Y
IO_L36N_Y
D10
A8
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GCK2
IO
D17
A3
IO_L36P_Y
B8
IO_L37N_Y
E10
C8
IO
D9
IO_VREF_L37P_Y
IO_L38N_YY
IO_VREF_L38P_YY
IO_L39N_YY
IO_L39P_YY
IO_L40N_Y
IO
E8
B7
IO
E11
E17
C17
B17
B16
D16
E16
C16
A15
A6
IO_LVDS_DLL_L21P
IO_VREF_L22N_Y
IO_L22P_Y
IO_L23N_Y
IO_VREF_L23P_Y
IO_L24N_Y
IO_L24P_Y
IO_L25N_Y
C7
2
D8
A5
IO_L40P_Y
B5
IO_L41N_YY
IO_VREF_L41P_YY
IO_L42N_YY
IO_L42P_YY
C6
D7
A4
B4
Module 4 of 4
34
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
Pin Description
IO_L43N_Y
Pin#
C5
E7
See Note
Bank
2
Pin Description
IO_L58P_Y
Pin#
M5
L3
See Note
1
1
1
1
IO_VREF_L43P_Y
IO_WRITE_L44N_YY
IO_CS_L44P_YY
3
2
IO_L58N_Y
D6
A2
2
IO_L59P_Y
L1
2
IO_L59N_Y
M4
N5
M2
N4
N3
N2
P5
P4
P3
P2
R5
R4
R3
R1
T4
T5
T3
T2
U3
2
IO_VREF_L60P_Y
IO_L60N_Y
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO
IO
D3
F3
G1
J2
2
2
IO_L61P_Y
IO
2
IO_L61N_Y
IO
2
IO_L62P_Y
IO_DOUT_BUSY_L45P_YY
IO_DIN_D0_L45N_YY
IO_L46P_Y
D4
E4
F5
B3
F4
C1
G5
E3
D2
G4
H5
E2
H4
G3
J5
2
IO_L62N_Y
2
IO_VREF_L63P_YY
IO_D3_L63N_YY
IO_L64P_Y
2
IO_VREF_L46N_Y
IO_L47P_Y
3
2
2
IO_L64N_Y
IO_L47N_Y
2
IO_L65P_Y
IO_VREF_L48P_Y
IO_L48N_Y
2
IO_L65N_Y
2
IO_VREF_L66P_Y
IO_L66N_Y
IO_L49P_Y
2
IO_L49N_Y
2
IO_L67P_Y
IO_L50P_Y
2
IO_VREF_L67N_Y
IO_L68P_YY
IO_L68N_YY
2
IO_L50N_Y
2
IO_VREF_L51P_YY
IO_L51N_YY
IO_L52P_Y
2
3
3
3
3
3
3
3
3
3
3
3
3
IO
IO
AE3
AF3
AH3
AK3
U1
IO_VREF_L52N_Y
IO_L53P_Y
F1
J4
1
4
IO
IO_L53N_Y
H3
K5
H2
J3
IO
IO_VREF_L54P_Y
IO_L54N_Y
IO_VREF_L69P_Y
IO_L69N_Y
IO_L70P_Y
IO_VREF_L70N_Y
IO_L71P_Y
IO_L71N_Y
IO_L72P_Y
IO_L72N_Y
2
U2
IO_L55P_Y
V2
IO_L55N_Y
K4
L5
K3
L4
K2
V4
IO_VREF_L56P_YY
IO_D1_L56N_YY
IO_D2_L57P_YY
IO_L57N_YY
V5
V3
W1
W3
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
35
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_D4_L73P_YY
IO_VREF_L73N_YY
IO_L74P_Y
Pin#
W4
See Note
Bank
Pin Description
IO_VREF_L90N_Y
IO_D7_L91P_YY
IO_INIT_L91N_YY
IO
Pin#
AH4
AJ4
AH5
U4
See Note
3
3
3
3
3
W5
Y3
IO_L74N_Y
Y4
IO_L75P_Y
AA1
Y5
IO_L75N_Y
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
GCK0
IO
AL17
AJ8
IO_L76P_Y
AA3
AA4
AB3
AA5
AC1
AB4
AC3
AB5
AC4
AD3
AE1
AC5
AD4
AF1
AF2
AD5
AG2
AE4
AH1
AE5
AF4
AJ1
AJ2
AF5
AG4
AK2
AJ3
AG5
AL1
IO_VREF_L76N_Y
IO_L77P_Y
3
IO
AJ11
AK6
AK9
AL4
IO
IO_L77N_Y
IO
IO_L78P_Y
IO_L92P_YY
IO_L92N_YY
IO_L93P_Y
IO_L78N_Y
AJ6
IO_L79P_YY
IO_D5_L79N_YY
IO_D6_L80P_YY
IO_VREF_L80N_YY
IO_L81P_Y
AK5
AN3
AL5
IO_VREF_L93N_Y
IO_L94P_YY
IO_L94N_YY
IO_VREF_L95P_YY
IO_L95N_YY
IO_L96P_Y
3
AJ7
AM4
AM5
AK7
AL6
IO_L81N_Y
IO_L82P_Y
IO_VREF_L82N_Y
IO_L83P_Y
4
1
IO_L96N_Y
IO_L97P_YY
IO_L97N_YY
IO_VREF_L98P_YY
IO_L98N_YY
IO_L99P_Y
AM6
AN6
AL7
IO_L83N_Y
IO_L84P_Y
IO_VREF_L84N_Y
IO_L85P_YY
IO_VREF_L85N_YY
IO_L86P_Y
AJ9
AN7
AL8
IO_VREF_L99N_Y
IO_L100P_Y
IO_L100N_Y
IO_VREF_L101P_Y
IO_L101N_Y
IO_L102P_Y
IO_L102N_Y
IO_VREF_L103P_YY
IO_L103N_YY
IO_L104P_YY
1
4
AM8
AJ10
AL9
IO_L86N_Y
IO_L87P_Y
IO_L87N_Y
AM9
AK10
AN9
AL10
AM10
AL11
IO_L88P_Y
IO_VREF_L88N_Y
IO_L89P_Y
IO_L89N_Y
IO_L90P_Y
Module 4 of 4
36
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
4
Pin Description
IO_L104N_YY
IO_L105P_Y
Pin#
AJ12
AN11
AK12
AL12
AM12
AK13
AL13
AM13
AN13
AJ14
AK14
AM14
AN15
AJ15
AK15
AL15
AM16
AL16
AJ16
AK16
AN17
AM17
See Note
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L118N_Y
Pin#
AM20
AJ19
AL20
AN21
AL21
AJ20
AM22
AK21
AN23
AJ21
AM23
AK22
AM24
AL23
AJ22
AK23
AL24
AN26
AJ23
AK24
AM26
AM27
AJ24
AL26
AK25
AN29
AJ25
AK26
AM29
AM30
AJ26
AK27
AL29
AN31
AJ27
See Note
4
IO_L119P_YY
IO_VREF_L119N_YY
IO_L120P_YY
IO_L120N_YY
IO_L121P_Y
4
IO_L105N_Y
4
IO_L106P_YY
IO_L106N_YY
IO_VREF_L107P_YY
IO_L107N_YY
IO_L108P_Y
4
4
3
4
IO_L121N_Y
4
IO_L122P_YY
IO_VREF_L122N_YY
IO_L123P_YY
IO_L123N_YY
IO_L124P_Y
4
IO_L108N_Y
3
4
IO_L109P_YY
IO_L109N_YY
IO_VREF_L110P_YY
IO_L110N_YY
IO_L111P_Y
4
4
4
IO_L124N_Y
4
IO_L125P_YY
IO_L125N_YY
IO_L126P_YY
IO_VREF_L126N_YY
IO_L127P_Y
4
IO_L111N_Y
4
IO_L112P_Y
4
IO_L112N_Y
4
IO_VREF_L113P_Y
IO_L113N_Y
4
IO_L127N_Y
4
IO_L114P_Y
IO_L128P_Y
4
IO_VREF_L114N_Y
IO_LVDS_DLL_L115P
2
IO_VREF_L128N_Y
IO_L129P_Y
4
1
4
IO_L129N_Y
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
IO
AJ17
AL25
AL28
AL30
AN28
AM18
AL18
AK18
AJ18
AN19
AL19
AK19
IO_L130P_Y
IO_VREF_L130N_Y
IO_L131P_YY
IO_VREF_L131N_YY
IO_L132P_YY
IO_L132N_YY
IO_L133P_Y
IO
IO
IO
IO_LVDS_DLL_L115N
IO_VREF
2
IO_L116P_Y
IO_VREF_L116N_Y
IO_L117P_Y
IO_L117N_Y
IO_L118P_Y
IO_L133N_Y
IO_L134P_YY
IO_VREF_L134N_YY
IO_L135P_YY
IO_L135N_YY
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
37
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
Pin Description
IO_L136P_Y
Pin#
AM31
AK28
See Note
Bank
6
Pin Description
IO_L151N_Y
IO_L151P_Y
Pin#
AB31
AA29
AA30
AA31
AA32
Y29
See Note
5
5
IO_VREF_L136N_Y
3
6
6
IO_VREF_L152N_Y
IO_L152P_Y
3
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO
AE33
AF31
AJ32
AL33
AH29
AJ30
AK31
AH30
AG29
AJ31
AK32
AG30
AH31
AF29
AH32
AF30
AE29
AH33
AG33
AE30
AD29
AF32
AE31
AD30
AE32
AC29
AD31
AC30
AB29
AC31
AC33
AB30
6
IO
6
IO_L153N_Y
IO_L153P_Y
IO
6
IO
6
IO_L154N_Y
IO_L154P_Y
AA33
Y30
IO_L137N_YY
IO_L137P_YY
IO_L138N_Y
IO_VREF_L138P_Y
IO_L139N_Y
IO_L139P_Y
IO_VREF_L140N_Y
IO_L140P_Y
IO_L141N_Y
IO_L141P_Y
IO_L142N_Y
IO_L142P_Y
IO_VREF_L143N_YY
IO_L143P_YY
IO_L144N_Y
IO_VREF_L144P_Y
IO_L145N_Y
IO_L145P_Y
IO_VREF_L146N_Y
IO_L146P_Y
IO_L147N_Y
IO_L147P_Y
IO_VREF_L148N_YY
IO_L148P_YY
IO_L149N_YY
IO_L149P_YY
IO_L150N_Y
IO_L150P_Y
6
6
IO_VREF_L155N_YY
IO_L155P_YY
IO_L156N_Y
IO_L156P_Y
Y32
6
W29
W30
W31
W33
V30
3
6
6
6
IO_L157N_Y
IO_L157P_Y
6
6
IO_VREF_L158N_Y
IO_L158P_Y
V29
6
V31
6
IO_L159N_Y
IO_VREF_L159P_Y
IO
V32
6
U33
2
6
U29
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO
IO
E30
F29
F33
G30
K30
U31
U32
T32
T30
T29
T31
R33
R31
R30
R29
1
4
IO
IO
IO
IO_L160N_YY
IO_L160P_YY
IO_VREF_L161N_Y
IO_L161P_Y
IO_L162N_Y
IO_VREF_L162P_Y
IO_L163N_Y
IO_L163P_Y
IO_L164N_Y
IO_L164P_Y
2
Module 4 of 4
38
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L165N_YY
IO_VREF_L165P_YY
IO_L166N_Y
Pin#
P32
P31
P30
P29
M32
N31
N30
L33
M31
L32
M30
L31
M29
J33
See Note
Bank
Pin Description
Pin#
See Note
7
IO_VREF_L182P_Y
D31
3
2
CCLK
DONE
DXN
C4
AJ5
IO_L166P_Y
3
IO_L167N_Y
NA
NA
NA
NA
NA
NA
NA
NA
2
AK29
AJ28
AJ29
AK30
AN32
AM1
E29
IO_L167P_Y
DXP
IO_L168N_Y
M0
IO_VREF_L168P_Y
IO_L169N_Y
3
M1
M2
IO_L169P_Y
PROGRAM
TCK
IO_L170N_Y
IO_L170P_Y
TDI
D5
IO_L171N_YY
IO_L171P_YY
IO_L172N_YY
IO_VREF_L172P_YY
IO_L173N_Y
TDO
E6
NA
TMS
B33
L30
K31
L29
H33
J31
NA
NA
NA
NA
NC
NC
NC
NC
C31
AC2
AK4
AL3
IO_L173P_Y
IO_L174N_Y
IO_VREF_L174P_Y
IO_L175N_Y
H32
K29
H31
J30
4
1
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
A21
B12
B14
B18
B28
C22
C24
E9
IO_L175P_Y
IO_L176N_Y
IO_VREF_L176P_Y
IO_L177N_YY
IO_VREF_L177P_YY
IO_L178N_Y
G32
J29
G31
E33
E32
H29
F31
D32
E31
G29
C33
F30
IO_L178P_Y
IO_L179N_Y
E12
F2
IO_L179P_Y
IO_L180N_Y
H30
J1
IO_VREF_L180P_Y
IO_L181N_Y
K32
M3
IO_L181P_Y
IO_L182N_Y
N1
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
39
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin#
N29
See Note
Bank
2
Pin Description
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
Pin#
M1
See Note
N33
2
R2
U5
3
V1
U30
3
AA2
AD1
AK1
AL2
Y2
3
Y31
3
AB2
3
AB32
AD2
AD32
AG3
AG31
AJ13
AK8
4
AN4
AN8
AN12
AM2
AM15
AL31
AM21
AN18
AN24
AN30
W32
AB33
AF33
AK33
AM32
C32
4
4
4
4
5
5
AK11
AK17
AK20
AL14
AL22
AL27
AN25
5
5
5
6
6
6
6
6
0
0
0
0
0
1
1
1
1
1
2
2
2
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
A22
A26
A30
B19
B32
A10
A16
B13
C3
7
7
D33
7
K33
7
N32
7
T33
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
A1
A7
A12
A14
A18
A20
A24
E5
B2
D1
H1
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
XCV1600E, XCV2000E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin#
A29
A32
A33
B1
See Note
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Notes:
Pin Description
GND
Pin#
AL32
AM3
See Note
GND
GND
AM7
GND
AM11
AM19
AM25
AM28
AM33
AN1
B6
GND
B9
GND
B15
B23
B27
B31
C2
GND
GND
GND
GND
AN2
GND
AN5
E1
GND
AN10
AN14
AN16
AN20
AN22
AN27
AN33
F32
G2
GND
GND
G33
J32
K1
GND
GND
GND
L2
GND
M33
P1
1.
2.
3.
V
REF or I/O option only in the XCV2000E; otherwise, I/O
option only.
V
REF or I/O option only in the XCV1600E & 2000E;
P33
R32
T1
otherwise, I/O option only.
V
REF or I/O option only in the XCV1000E, 1600E, & 2000E;
otherwise, I/O option only.
4. VREF or I/O option only in the XCV600E, 1000E, 1600E, &
2000E; otherwise, I/O option only.
V33
W2
Y1
Y33
AB1
AC32
AD33
AE2
AG1
AG32
AH2
AJ33
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
41
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
BG560 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
E20
C20
E19
C19
D18
E17
B17
D16
C16
C15
E15
D14
E14
D13
E13
D12
C11
D11
A9
B21
D20
B20
D19
A19
C18
C17
B16
E16
A15
D15
C14
A13
C13
C12
A11
B11
B10
C10
C9
-
VREF
9
7
7
-
-
VREF
NA IO_LVDS_DLL
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
2
7
7
9
VREF
P
N
Other
VREF
Pair Bank
Pin
Pin
AO
Functions
-
Global Differential Clock
-
0
1
2
3
4
5
1
0
AL17
AJ17
D17
AM17
AM18
E17
NA
NA
NA
NA
IO_DLL_L15P
IO_DLL_L15N
IO_DLL_L21P
IO_DLL_L21N
VREF
-
3
8
-
A17
C18
VREF
IO LVDS
-
Total Outputs: 183, Asynchronous Outputs: 87
-
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D29
A31
C29
D27
B29
C27
A28
C26
B26
D24
A25
B24
C23
D22
B22
C21
E28
D28
E27
B30
E26
D26
E25
D25
E24
C25
E23
D23
E22
A23
E21
D21
8
3
VREF
-
VREF
-
-
2
VREF
10
7
3
-
D10
B8
VREF
-
4
-
A8
7
5
VREF
C8
E10
B7
5
VREF
VREF
-
6
9
7
7
2
VREF
A6
7
-
D8
C7
8
VREF
B5
A5
11
12
17
-
9
-
D7
C6
VREF
-
10
11
12
13
14
15
VREF
B4
A4
-
E7
C5
VREF
CS
8
3
-
A2
D6
-
VREF
-
D4
E4
DIN, D0
VREF
F5
B3
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 15: BG560 Differential Pin Pair Summary
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
14
15
16
15
Functions
Pair Bank
Pin
Pin
AO
Functions
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
F4
G5
D2
H5
H4
J5
C1
E3
G4
E2
G3
F1
-
78
79
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
AC1
AC3
AC4
AE1
AD4
AF2
AG2
AH1
AF4
AJ2
AB4
AB5
AD3
AC5
AF1
AD5
AE4
AE5
AJ1
17
-
VREF
D5
-
80
VREF
-
81
4
-
VREF
82
18
14
20
VREF
17
14
18
19
VREF
83
-
J4
H3
H2
K4
K3
K2
L3
-
84
VREF
K5
J3
VREF
85
VREF
-
86
15
14
15
14
14
-
L5
D1
87
AF5
AK2
AG5
AH4
AH5
AJ6
-
L4
D2
88
AG4
AJ3
VREF
M5
L1
17
14
15
16
15
-
89
-
M4
M2
N3
P5
P3
R5
R3
T4
-
90
AL1
VREF
N5
N4
N2
P4
P2
R4
R1
T5
VREF
91
AJ4
INIT
-
92
AL4
-
-
93
AK5
AL5
AN3
AJ7
8
3
VREF
D3
94
-
17
14
18
19
-
95
AM4
AK7
AM6
AL7
AM5
AL6
VREF
-
96
-
VREF
97
AN6
AJ9
-
T3
VREF
98
VREF
T2
U3
U2
V4
V3
W3
W5
Y4
Y5
AA4
AA5
-
99
AN7
AM8
AL9
AL8
9
7
7
2
VREF
U1
V2
V5
W1
W4
Y3
AA1
AA3
AB3
19
18
14
17
VREF
100
101
102
103
104
105
106
107
108
AJ10
AM9
AN9
AM10
AJ12
AK12
AM12
AL13
-
VREF
VREF
-
AK10
AL10
AL11
AN11
AL12
AK13
-
-
VREF
VREF
-
15
16
15
14
-
8
3
-
-
VREF
-
-
VREF
-
AM13 AN13
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
43
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
15
16
15
Functions
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
AJ14
AK14
-
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
AG30
AF29
AF30
AH33
AE30
AF32
AD30
AC29
AC30
AC31
AB30
AA29
AA31
Y29
AK32
AH31
AH32
AE29
AG33
AD29
AE31
AE32
AD31
AB29
AC33
AB31
AA30
AA32
AA33
Y32
VREF
AM14 AN15
VREF
-
-
AJ15
AL15
AL16
AK16
AK15
AM16
AJ16
AN17
1
7
7
2
-
-
VREF
VREF
VREF
17
14
18
19
VREF
-
AM17 AM18
NA IO_LVDS_DLL
VREF
AK18
AN19
AK19
AJ19
AN21
AJ20
AK21
AJ21
AK22
AL23
AK23
AN26
AK24
AM27
AL26
AN29
AK26
AM30
AK27
AN31
AM31
AJ30
AH30
AJ31
AJ18
AL19
AM20
AL20
AL21
AM22
AN23
AM23
AM24
AJ22
AL24
AJ23
AM26
AJ24
AK25
AJ25
AM29
AJ26
AL29
AJ27
AK28
AH29
AK31
AG29
7
7
9
VREF
-
-
VREF
-
-
VREF
17
14
15
16
15
-
-
-
3
8
-
VREF
VREF
-
-
Y30
-
-
W29
W31
V30
VREF
-
W30
W33
V29
17
14
18
19
-
VREF
-
13
7
-
V31
VREF
VREF
U33
V32
VREF
-
U32
U31
-
5
VREF
T30
T32
19
18
14
17
VREF
VREF
T31
T29
VREF
-
R31
R33
-
11
12
-
R29
R30
-
VREF
P31
P32
VREF
-
P29
P30
15
16
15
14
17
-
VREF
N31
M32
-
-
VREF
-
L33
N30
VREF
17
14
L32
M31
-
-
L31
M30
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
FG256 Fine-Pitch Ball Grid Array Packages
XCV50E, XCV100E, XCV200E, and XCV300E devices in
FG256 fine-pitch Ball Grid Array packages have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as VREF, it can be used as gen-
eral I/O. Immediately following Table 16, see Table 17 for
Differential Pair information.
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
171
172
173
174
175
176
177
178
179
180
181
182
Notes:
7
7
7
7
7
7
7
7
7
7
7
7
J33
K31
H33
H32
H31
G32
G31
E32
F31
E31
C33
D31
M29
L30
L29
J31
K29
J30
J29
E33
H29
D32
G29
F30
-
VREF
4
-
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
18
14
20
VREF
Bank
0
Pin Description
GCK3
Pin #
B8
B3
E7
D8
C5
A32
D5
E6
B4
A4
D6
B5
C61
A5
B6
C7
D7
C8
B7
A6
A7
-
VREF
0
IO
VREF
0
IO
15
14
15
14
14
-
0
IO
-
0
IO_L0N_Y
VREF
-
0
IO_VREF_L0P_Y
IO_L1N_YY
IO_L1P_YY
IO_VREF_L2N_YY
IO_L2P_YY
IO_L3N_Y
0
VREF
0
0
1. AO in the XCV1600E.
2. AO in the XCV2000E.
0
3. AO in the XCV1600E, 2000E.
4. AO in the XCV1000E, 1600E.
5. AO in the XCV1000E, 2000E.
6. AO in the XCV1000E.
0
0
IO_L3P_Y
0
IO_VREF_L4N_YY
IO_L4P_YY
IO_L5N_YY
IO_L5P_YY
IO_L6N_Y
7. AO in the XCV1000E, 1600E, 2000E.
8. AO in the XCV600E, 1600E.
0
0
9. AO in the XCV400E, 600E, 1600E.
10. AO in the XCV400E, 600E, 1000E, 2000E.
11. AO in the XCV400E, 600E, 1000E.
12. AO in the XCV400E, 1000E, 2000E.
13. AO in the XCV400E, 600E, 1000E, 1600E.
14. AO in the XCV400E, 1000E, 1600E.
15. AO in the XCV600E, 1000E, 2000E.
16. AO in the XCV600E, 2000E.
0
0
0
IO_L6P_Y
0
IO_VREF_L7N_Y
IO_L7P_Y
0
0
IO_LVDS_DLL_L8N
17. AO in the XCV400E, 600E, 1600E, 2000E.
18. AO in the XCV600E, 1000E, 1600E, 2000E.
19. AO in the XCV400E, 600E, 2000E.
20. AO in the XCV400E, 1000E.
1
1
1
1
1
1
1
GCK2
IO
C9
B10
A8
IO_LVDS_DLL_L8P
IO_L9N_Y
D9
IO_L9P_Y
A9
IO_L10N_Y
IO_VREF_L10P_Y
E10
B9
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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1-800-255-7778
Module 4 of 4
45
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 16: FG256 Package — XCV50E, XCV100E,
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
XCV200E, XCV300E
Bank
Pin Description
IO_L11N_Y
Pin #
A10
D10
C10
A11
B11
E111
A12
D11
A13
C11
B12
D12
A142
C12
C13
B13
Bank
Pin Description
IO_VREF_L28P_Y
IO_D3_L28N_Y
IO_L29P
Pin #
H13
G16
J13
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
IO_L11P_Y
IO_L12N_YY
IO_L12P_YY
IO_L29N
H15
H14
H16
IO_L13N_YY
IO_L30P_YY
IO_L30N_YY
IO_VREF_L13P_YY
IO_L14N_Y
IO_L14P_Y
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
J15
K15
J14
IO_L15N_YY
IO_L31P
IO_VREF_L15P_YY
IO_L16N_YY
IO_L31N
IO_D4_L32P_Y
IO_VREF_L32N_Y
IO_L33P_YY
IO_L33N_YY
IO_L34P
J16
IO_L16P_YY
K16
K12
L15
K13
L16
K14
M16
N16
L131
P16
L12
M15
L14
M14
R16
M132
T15
N14
N15
IO_VREF_L17N_Y
IO_L17P_Y
IO_WRITE_L18N_YY
IO_CS_L18P_YY
IO_L34N
IO_L35P_YY
IO_D5_L35N_YY
IO_D6_L36P_Y
IO_VREF_L36N_Y
IO_L37P
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_DOUT_BUSY_L19P_YY
IO_DIN_D0_L19N_YY
IO_L20P
C15
D14
B16
E132
C16
E14
F13
E15
F12
D16
F141
E16
F15
G13
F16
G12
G15
G14
IO_VREF_L20N
IO_L21P_YY
IO_L21N_YY
IO_VREF_L22P_Y
IO_L22N_Y
IO_L37N
IO_L38P_Y
IO_VREF_L38N_Y
IO_L39P_YY
IO_L39N_YY
IO_VREF_L40P
IO_L40N
IO_L23P
IO_L23N
IO_VREF_L24P_Y
IO_D1_L24N_Y
IO_D2_L25P_YY
IO_L25N_YY
IO_L26P
IO_D7_L41P_YY
IO_INIT_L41N_YY
4
4
4
4
GCK0
IO
N8
IO_L26N
P10
T14
P13
IO_L27P_YY
IO_L27N_YY
IO_L42P_YY
IO_L42N_YY
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 16: FG256 Package — XCV50E, XCV100E,
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
XCV200E, XCV300E
Bank
4
Pin Description
IO_L43P_Y
Pin #
P12
R132
N12
T13
T12
P11
R12
N11
T111
M11
R11
T10
R10
M10
P9
Bank
Pin Description
IO_VREF_L58N_YY
IO_L59P_YY
Pin #
T4
5
5
5
5
5
4
IO_VREF_L43N_Y
IO_L44P_YY
T3
4
IO_L59N_YY
P5
4
IO_L44N_YY
IO_VREF_L45P_YY
IO_L45N_YY
IO_L46P_Y
IO_VREF_L60P_Y
IO_L60N_Y
T22
N5
4
4
4
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L61N_YY
IO_L61P_YY
IO_L62N
M3
R1
M4
N22
L5
4
IO_L46N_Y
4
IO_VREF_L47P_YY
IO_L47N_YY
IO_L48P_YY
4
IO_VREF_L62P
IO_L63N_YY
IO_L63P_YY
IO_VREF_L64N_Y
IO_L64P_Y
IO_L65N
4
4
IO_L48N_YY
IO_L49P_Y
P1
N1
L3
4
4
IO_L49N_Y
4
IO_VREF_L50P_Y
IO_L50N_Y
M2
L4
4
T9
IO_L65P
4
IO_L51P_Y
N10
R9
IO_VREF_L66N_Y
IO_L66P_Y
IO_L67N_YY
IO_L67P_YY
IO_L68N
M11
K4
L2
4
IO_L51N_Y
4
IO_LVDS_DLL_L52P
N9
L1
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
IO
R8
N7
T7
K3
K1
K2
K5
J3
IO_L68P
IO
IO_L69N_YY
IO_L69P_YY
IO_VREF_L70N_Y
IO_L70P_Y
IO_L71N
IO_LVDS_DLL_L52N
IO_L53P_Y
IO_VREF_L53N_Y
IO_L54P_Y
IO_L54N_Y
IO_L55P_YY
IO_L55N_YY
IO_L56P_YY
IO_VREF_L56N_YY
IO_L57P_Y
IO_L57N_Y
IO_L58P_YY
T8
R7
P8
P7
T6
J1
J4
IO_L71P
H1
J2
M7
R6
P6
R51
N6
T5
IO
7
7
7
7
7
IO
C2
G1
H4
G5
H2
IO_L72N_YY
IO_L72P_YY
IO_L73N
M6
IO_L73P
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
47
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 16: FG256 Package — XCV50E, XCV100E,
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
XCV200E, XCV300E
Bank
7
Pin Description
IO_L74N_Y
Pin #
G4
H3
G2
F5
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin #
D13
E5
7
IO_VREF_L74P_Y
IO_L75N_YY
IO_L75P_YY
IO_L76N
7
E12
M5
7
7
F4
M12
N4
7
IO_L76P
F1
7
IO_L77N_YY
IO_L77P_YY
IO_L78N_Y
G3
F2
N13
P3
7
7
E1
D11
E4
E2
F3
P14
7
IO_VREF_L78P_Y
IO_L79N
7
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
F8
E8
7
IO_L79P
7
IO_L80N_Y
F9
7
IO_VREF_L80P_Y
IO_L81N_YY
IO_L81P_YY
IO_VREF_L82N
IO_L82P
C1
D2
E3
B12
A2
E9
7
H12
H11
J12
J11
M9
L9
7
7
7
2
CCLK
DONE
DXN
D15
R14
R4
3
M8
L8
NA
NA
NA
NA
NA
NA
NA
NA
2
DXP
P4
J6
M0
N3
J5
M1
P2
H6
H5
M2
R3
PROGRAM
TCK
P15
C4
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
T16
T1
TDI
A15
B14
D3
TDO
R15
R2
NA
TMS
L11
L10
L7
NA
NA
NA
VCCINT
VCCINT
VCCINT
C3
C14
D4
L6
Module 4 of 4
48
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
FG256 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
K11
K10
K9
K8
K7
K6
J10
J9
Table 17: FG256 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E
J8
P
N
Other
J7
Pair
Bank
Pin
Pin
AO
Functions
H10
H9
Global Differential Clock
0
1
2
3
4
5
1
0
N8
R8
C9
B8
N9
T8
NA
NA
NA
NA
IO_DLL_L52P
IO_DLL_L52N
IO_DLL_L8P
IO_DLL_L8N
H8
H7
A8
G11
G10
G9
G8
G7
G6
F11
F10
F7
A7
IO LVDS
Total Pairs: 83, Asynchronous Outputs: 35
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A3
E6
C5
D5
7
2
VREF
-
2
A4
B4
VREF
3
B5
D6
-
4
A5
C6
VREF
5
C7
B6
-
-
6
C8
D7
1
1
F6
7
A6
B7
VREF
B15
B2
8
A8
A7
NA IO_LVDS_DLL
9
A9
D9
2
1
1
-
A16
A1
10
11
12
13
14
15
16
17
18
B9
E10
A10
C10
B11
A12
A13
B12
A14
C13
VREF
D10
A11
E11
D11
C11
D12
C12
B13
-
Notes:
1. REF or I/O option only in the XCV100E, 200E, 300E;
otherwise, I/O option only.
V
-
VREF
-
2. VREF or I/O option only in the XCV200E, 300E; otherwise,
I/O option only.
2
7
VREF
-
VREF
CS
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
49
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 17: FG256 Differential Pin Pair Summary
Table 17: FG256 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E
XCV50E, XCV100E, XCV200E, XCV300E
P
N
Other
P
N
Pin
R6
R5
T5
T4
P5
N5
M3
M4
L5
Other
Pair
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Bank
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
5
5
5
Pin
Pin
D14
E13
E14
E15
D16
E16
G13
G12
G14
G16
H15
H16
J14
K16
L15
L16
M16
L13
L12
L14
R16
T15
N15
P13
R13
T13
P11
N11
M11
T10
M10
T9
AO
Functions
Pair
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
Notes:
Bank
5
Pin
M7
P6
N6
M6
T3
T2
R1
N2
P1
L3
L4
K4
L1
K1
K5
J1
AO
Functions
C15
B16
C16
F13
F12
F14
F15
F16
G15
H13
J13
H14
K15
J16
K12
K13
K14
N16
P16
M15
M14
M13
N14
T14
P12
N12
T12
R12
T11
R11
R10
P9
DIN, D0
-
6
VREF
5
VREF
-
5
2
-
1
5
3
VREF
5
VREF
-
5
-
D1
5
7
6
VREF
D2
6
-
6
-
6
VREF
-
6
-
3
4
D3
6
N1
M2
M1
L2
1
5
3
VREF
-
6
-
-
6
VREF
4
3
-
6
-
VREF
6
K3
K2
J3
6
-
-
6
-
6
-
6
3
4
VREF
D5
6
H1
H4
H2
H3
F5
F1
F2
D1
E2
C1
E3
A2
J4
-
3
5
1
VREF
7
G1
G5
G4
G2
F4
G3
E1
E4
F3
D2
B1
-
-
7
4
3
-
VREF
7
VREF
-
7
-
6
7
2
VREF
7
6
-
INIT
7
-
-
7
3
5
1
VREF
-
VREF
7
-
7
VREF
-
VREF
7
-
7
6
VREF
VREF
1. AO in the XCV50E, 200E, 300E.
2. AO in the XCV50E, 200E.
3. AO in the XCV50E, 300E.
4. AO in the XCV100E, 200E.
5. AO in the XCV200E.
-
1
1
1
-
VREF
-
6. AO in the XCV100E.
7. AO in the XCV50E.
N10
N9
R9
T8
NA IO_LVDS_DLL
R7
P8
1
1
VREF
-
P7
T6
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 18: FG456 — XCV200E and XCV300E
FG456 Fine-Pitch Ball Grid Array Packages
Bank
Pin Description
IO_L10N
Pin #
C9
XCV200E and XCV300E devices in FG456 fine-pitch Ball
Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in both devices pro-
vided in this package. If the pin is not used as VREF, it can be
used as general I/O. Immediately following Table 18, see
Table 19 for Differential Pair information.
0
0
0
0
0
0
0
IO_L10P
E10
A9
IO_VREF_L11N_YY
IO_L11P_YY
IO_L12N_Y
C10
F11
B10
B11
Table 18: FG456 — XCV200E and XCV300E
Bank
0
Pin Description
GCK3
Pin #
C11
A21
A3
IO_L12P_Y
IO_LVDS_DLL_L13N
0
IO
0
IO
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GCK2
IO
A11
A121
A14
B161
B19
E13
E15
E16
E171
D11
C12
D12
B12
A13
E12
B13
C13
D13
B14
C14
F12
A15
B15
C15
A16
E14
D14
C16
D15
0
IO
A61
A10
B5
0
IO
IO
0
IO
IO
0
IO
B9
IO
0
IO
C5
D8
D10
E111
D5
B3
IO
0
IO
IO
0
IO
IO
0
IO
IO
0
IO_L0N
IO_LVDS_DLL_L13P
IO_L14N_Y
IO_L14P_Y
IO_L15N_Y
IO_L15P_Y
IO_L16N_YY
IO_VREF_L16P_YY
IO_L17N_YY
IO_L17P_YY
IO_L18N_Y
IO_L18P_Y
IO_L19N_Y
IO_L19P_Y
IO_L20N_YY
IO_L20P_YY
IO_L21N_YY
IO_VREF_L21P_YY
IO_L22N_Y
IO_L22P_Y
IO_L23N_Y
0
IO_L0P
0
IO_VREF_L1N_YY
IO_L1P_YY
IO_L2N
B4
0
E6
0
A4
0
IO_L2P
E7
0
IO_VREF_L3N_YY
IO_L3P_YY
IO_L4N_Y
IO_L4P_Y
IO_L5N_Y
IO_L5P_Y
IO_VREF_L6N_YY
IO_L6P_YY
IO_L7N_YY
IO_L7P_YY
IO_L8N_Y
IO_L8P_Y
IO_L9N_Y
IO_L9P_Y
C6
D6
A5
0
0
0
B6
0
D7
C7
E8
0
0
0
B7
0
A7
0
E9
0
C8
B8
0
0
D9
A8
0
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
51
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 18: FG456 — XCV200E and XCV300E
Table 18: FG456 — XCV200E and XCV300E
Bank
Pin Description
IO_L23P_Y
Pin #
A17
B17
A18
D16
C17
B18
A19
D17
C18
A20
C19
Bank
Pin Description
IO_D2_L37P_YY
IO_L37N_YY
IO_L38P_YY
IO_L38N_YY
IO_L39P_YY
IO_L39N_YY
IO_L40P_Y
Pin #
H20
H19
H21
J19
J18
J20
K18
J21
K22
K21
K19
L22
L21
L18
L17
L20
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L24N_YY
IO_VREF_L24P_YY
IO_L25N_YY
IO_L25P_YY
IO_L26N_YY
IO_VREF_L26P_YY
IO_L27N_YY
IO_L40N_Y
IO_L27P_YY
IO_L41P
IO_WRITE_L28N_YY
IO_CS_L28P_YY
IO_VREF_L41N
IO_L42P_Y
IO_L42N_Y
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO
IO
D181
E191
E20
F20
G21
G221
J22
IO_L43P_YY
IO_L43N_YY
IO_L44P_YY
IO_L44N_YY
IO
IO
IO
IO
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
IO
M211
P22
R201
R22
T19
IO
IO
L191
K20
C21
D20
C22
D21
D22
E21
E22
F18
F21
F19
F22
G19
G20
G18
H18
H22
IO
IO_D3
IO
IO_DOUT_BUSY_L29P_YY
IO_DIN_D0_L29N_YY
IO_L30P_YY
IO_L30N_YY
IO_VREF_L31P_YY
IO_L31N_YY
IO_L32P_YY
IO_L32N_YY
IO_VREF_L33P_YY
IO_L33N_YY
IO_L34P_Y
IO_L34N_Y
IO_L35P_Y
IO_L35N_Y
IO_VREF_L36P_Y
IO_D1_L36N_Y
IO
IO
U181
V20
V21
Y221
M18
M20
M19
M17
N22
N21
N20
N18
N19
P21
P20
IO
IO
IO
IO_L45P_YY
IO_L45N_YY
IO_L46P_Y
IO_L46N_Y
IO_D4_L47P_Y
IO_VREF_L47N_Y
IO_L48P_YY
IO_L48N_YY
IO_L49P_YY
IO_L49N_YY
IO_L50P_YY
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 18: FG456 — XCV200E and XCV300E
Table 18: FG456 — XCV200E and XCV300E
Bank
3
Pin Description
IO_L50N_YY
IO_L51P_YY
Pin #
P19
P18
R21
T22
R19
U22
R18
T21
V22
T20
U21
W22
T18
U19
U20
W21
AA22
Y21
V19
M22
Bank
4
Pin Description
IO_L63N
Pin #
V16
3
4
IO_VREF_L64P_YY
IO_L64N_YY
IO_L65P_Y
AB19
AB18
W16
AA17
Y16
3
IO_D5_L51N_YY
IO_D6_L52P_Y
IO_VREF_L52N_Y
IO_L53P_Y
4
3
4
3
4
IO_L65N_Y
3
4
IO_L66P_Y
3
IO_L53N_Y
4
IO_L66N_Y
V15
3
IO_L54P_YY
4
IO_VREF_L67P_YY
IO_L67N_YY
IO_L68P_YY
IO_L68N_YY
IO_L69P_Y
AB16
Y15
3
IO_L54N_YY
IO_L55P_YY
4
3
4
AA15
AB15
W15
Y14
3
IO_VREF_L55N_YY
IO_L56P_YY
4
3
4
3
IO_L56N_YY
IO_L57P_YY
4
IO_L69N_Y
3
4
IO_L70P_Y
V14
3
IO_VREF_L57N_YY
IO_L58P_YY
4
IO_L70N_Y
AA14
AB14
V13
3
4
IO_L71P
3
IO_L58N_YY
IO_D7_L59P_YY
IO_INIT_L59N_YY
IO
4
IO_L71N
3
4
IO_VREF_L72P_YY
IO_L72N_YY
IO_L73P_Y
AA13
AB13
W13
AA12
Y12
3
4
3
4
4
IO_L73N_Y
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
GCK0
W12
W14
4
IO_L74P_Y
IO
4
IO_L74N_Y
V12
IO
Y13
4
IO_LVDS_DLL_L75P
U12
IO
Y17
IO
IO
AA161
AA19
AB121
AB17
AB211
W18
5
5
5
5
5
5
5
5
5
5
5
5
IO
U111
V8
IO
IO
IO
W5
IO
IO
AA31
AA9
AA10
AB4
AB71
AB8
Y11
IO
IO
IO_L60P_YY
IO_L60N_YY
IO_L61P
IO_L61N
IO_VREF_L62P_YY
IO_L62N_YY
IO_L63P
IO
AA20
Y18
IO
IO
IO
V17
AB20
W17
GCK1
IO_LVDS_DLL_L75N
IO_L76P_Y
AA11
AB11
AA18
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 18: FG456 — XCV200E and XCV300E
Table 18: FG456 — XCV200E and XCV300E
Bank
5
Pin Description
IO_L76N_Y
Pin #
W11
V11
Y10
AB10
W10
V10
Y9
Bank
6
Pin Description
IO_L90N_YY
IO_L90P_YY
IO_VREF_L91N_YY
IO_L91P_YY
IO_L92N_YY
IO_L92P_YY
IO_VREF_L93N_YY
IO_L93P_YY
IO_L94N_Y
Pin #
V4
V3
Y1
U4
V2
W1
T3
5
IO_L77P_YY
IO_VREF_L77N_YY
IO_L78P_YY
IO_L78N_YY
IO_L79P_Y
6
5
6
5
6
5
6
5
6
5
IO_L79N_Y
6
5
IO_L80P_Y
AB9
W9
6
U2
T5
5
IO_L80N_Y
6
5
IO_L81P_YY
IO_L81N_YY
IO_L82P_YY
IO_VREF_L82N_YY
IO_L83P_Y
V9
6
IO_L94P_Y
V1
R5
U1
R4
T1
5
AA8
Y8
6
IO_L95N_Y
5
6
IO_L95P_Y
5
W8
6
IO_VREF_L96N_Y
IO_L96P_Y
5
W7
6
5
IO_L83N_Y
AA7
AB6
AA6
AB5
AA5
Y7
6
IO_L97N_YY
IO_L97P_YY
IO_L98N_YY
IO_L98P_YY
IO_L99N_YY
IO_L99P_YY
IO_L100N_Y
IO_L100P_Y
IO_L101N
R2
P3
P5
R1
P2
N5
P1
N4
N3
N2
N1
M4
M3
M6
M1
5
IO_L84P_Y
6
5
IO_L84N_Y
6
5
IO_L85P_YY
IO_VREF_L85N_YY
IO_L86P_YY
IO_L86N_YY
IO_L87P_YY
IO_VREF_L87N_YY
IO_L88P_YY
IO_L88N_YY
6
5
6
5
6
5
W6
6
5
AA4
Y6
6
5
6
5
V7
6
IO_VREF_L101P
IO_L102N_Y
IO_L102P_Y
IO_L103N_YY
IO_L103P_YY
IO
5
AB3
6
6
6
6
6
6
6
6
6
6
6
6
6
IO
M21
M5
6
IO
6
IO
P4
6
IO
R31
T2
IO
7
7
7
7
7
7
7
IO
IO
IO
IO
IO
IO
IO
B1
C21
D11
E4
IO
T4
IO
IO
U31
W2
AA11
W3
Y2
IO
F4
IO_L89N_YY
IO_L89P_YY
G21
G4
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 18: FG456 — XCV200E and XCV300E
Table 18: FG456 — XCV200E and XCV300E
Bank
7
Pin Description
IO
Pin #
J1
Bank
NA
NA
NA
NA
NA
NA
NA
2
Pin Description
Pin #
V6
DXP
M0
7
IO
J4
AB2
U5
7
IO
L21
L3
M1
7
IO_L104N_YY
IO_L104P_YY
IO_L105N_YY
IO_L105P_YY
IO_L106N_Y
IO_L106P_Y
IO_L107N_Y
IO_VREF_L107P_Y
IO_L108N_YY
IO_L108P_YY
IO_L109N_YY
IO_L109P_YY
IO_L110N_YY
IO_L110P_YY
IO_L111N_YY
IO_L111P_YY
IO_L112N_Y
IO_VREF_L112P_Y
IO_L113N_Y
IO_L113P_Y
IO_L114N_YY
IO_L114P_YY
IO_L115N_YY
IO_VREF_L115P_YY
IO_L116N_YY
IO_L116P_YY
IO_L117N_YY
IO_VREF_L117P_YY
IO_L118N_YY
IO_L118P_YY
M2
Y4
7
L4
PROGRAM
TCK
W20
C4
7
L5
7
L1
TDI
B20
A21
D3
7
L6
TDO
TMS
7
K2
K4
K3
K1
K5
J3
NA
7
7
NA
NA
NA
NA
NC
NC
NC
NC
W19
W4
7
7
D19
D4
7
7
J2
7
J5
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
E5
E18
F6
7
H1
H2
H3
G1
H4
F1
F2
H5
G3
E1
E2
F3
G5
E3
D2
F5
C1
7
7
F17
G7
7
7
G8
7
G9
7
G14
G15
H7
7
7
7
G16
H16
J7
7
7
7
J16
P7
7
7
P16
R7
7
7
R16
T7
2
3
CCLK
DONE
DXN
B22
Y19
Y5
T8
T9
NA
T14
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
55
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 18: FG456 — XCV200E and XCV300E
Table 18: FG456 — XCV200E and XCV300E
Bank
NA
Pin Description
VCCINT
Pin #
T15
T16
U6
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
Pin #
K17
J17
H17
G17
L16
K16
G13
G12
F16
F15
F14
F13
G11
G10
F10
F9
NA
VCCINT
NA
VCCINT
NA
VCCINT
U17
V5
NA
VCCINT
NA
VCCINT
V18
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
L7
K7
K6
J6
H6
G6
N7
M7
T6
R6
F8
P6
F7
N6
U10
U9
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AB22
AB1
AA21
AA2
Y20
Y3
U8
U7
T11
T10
U16
U15
U14
U13
T13
T12
T17
R17
P17
N17
N16
M16
P14
P13
P12
P11
P10
P9
N14
N13
N12
N11
N10
N9
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 18: FG456 — XCV200E and XCV300E
FG456 Differential Pin Pairs
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
M14
M13
M12
M11
M10
M9
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
L14
L13
L12
L11
L10
L9
Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E
P
N
Other
Pair
Bank
Pin
Pin
AO
Functions
Global Differential Clock
K14
K13
K12
K11
K10
K9
0
1
2
3
4
5
1
0
W12
Y11
A11
C11
U12
AA11
D11
NA
NA
NA
NA
IO_DLL_L75P
IO_DLL_L75N
IO_DLL_L13P
IO_DLL_L13N
B11
IO LVDS
Total Pairs: 119, Asynchronous Output Pairs: 69
J14
J13
J12
J11
J10
J9
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
B3
E6
D5
B4
NA
-
VREF
2
E7
A4
NA
-
3
D6
C6
VREF
4
B6
A5
1
1
-
5
C7
D7
-
C20
C3
6
B7
E8
VREF
7
E9
A7
-
B21
B2
8
B8
C8
1
1
-
9
A8
D9
-
A22
A1
10
11
12
13
14
15
16
17
E10
C10
B10
D11
D12
A13
B13
D13
C9
NA
-
A9
VREF
Note 1: NC in the XCV200E device.
F11
B11
C12
B12
E12
C13
2
NA
2
-
IO_LVDS_DLL
-
2
-
VREF
-
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
57
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 19: FG456 Differential Pin Pair Summary
Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E
XCV200E, XCV300E
P
N
P
N
Other
Other
Pair
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Bank
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
Pin
Pin
AO
2
Functions
Pair
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Bank
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin
Pin
AO
Functions
C14
A15
C15
E14
C16
A17
A18
C17
A19
C18
C19
C21
C22
D22
E22
F21
F22
G20
H18
H20
H21
J18
B14
F12
B15
A16
D14
D15
B17
D16
B18
D17
A20
D20
D21
E21
F18
F19
G19
G18
H22
H19
J19
-
U22
T21
R18
V22
2
-
2
-
-
-
T20
U21
T18
VREF
VREF
W22
U19
W21
Y21
-
2
2
-
U20
AA22
V19
VREF
-
-
VREF
INIT
-
W18
Y18
AA20
V17
-
VREF
NA
NA
-
-
AB20
AA18
W17
V16
VREF
CS
-
DIN, D0
AB19 AB18
VREF
-
W16
Y16
AA17
V15
1
1
-
VREF
-
-
AB16
Y15
VREF
VREF
AA15 AB15
-
2
1
2
-
W15
V14
Y14
AA14
V13
1
1
-
-
-
D1, VREF
AB14
NA
-
D2
AA13 AB13
VREF
-
W13
Y12
U12
AB11
V11
AB10
V10
AB9
V9
AA12
V12
AA11
W11
Y10
W10
Y9
2
2
-
J20
-
-
K18
K22
K19
L21
L17
M18
M19
N22
N20
N19
P20
P18
T22
J21
2
1
2
-
NA
1
IO_LVDS_DLL
K21
L22
L18
L20
M20
M17
N21
N18
P21
P19
R21
R19
VREF
-
-
VREF
-
-
-
2
2
-
-
W9
-
2
2
-
AA8
W8
-
VREF
Y8
VREF
-
W7
AA7
AA6
AA5
W6
2
2
-
-
-
AB6
AB5
Y7
-
VREF
-
D5
2
VREF
AA4
Y6
VREF
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E
FG676 Fine-Pitch Ball Grid Array Package
XCV400E and XCV600E devices in the FG676 fine-pitch
Ball Grid Array package have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as VREF, it can be used as general I/O. Immedi-
ately following Table 20, see Table 21 for Differential Pair
information.
P
N
Other
Pair
88
Bank
5
Pin
Pin
AO
Functions
V7
Y2
V3
U4
W1
U2
V1
U1
T1
P3
R1
N5
N4
N2
M4
M6
L4
AB3
W3
V4
Y1
V2
T3
T5
R5
R4
R2
P5
P2
P1
N3
N1
M3
L3
-
89
6
-
90
6
-
Table 20: FG676 — XCV400E, XCV600E
91
6
VREF
Bank
0
Pin Description
GCK3
Pin #
E13
A6
92
6
-
93
6
VREF
0
IO
94
6
2
1
2
-
0
IO
A91
A101
B3
95
6
-
0
IO
96
6
VREF
0
IO
97
6
-
0
IO
B41
B121
C6
98
6
-
0
IO
99
6
-
0
IO
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
Notes:
6
2
1
2
-
0
IO
C8
6
VREF
0
IO
D5
6
-
0
IO
D131
G13
C4
6
-
0
IO
7
-
0
IO_L0N_Y
IO_L0P_Y
IO_L1N_YY
IO_L1P_YY
IO_VREF_L2N_YY
IO_L2P_YY
IO_L3N
IO_L3P
7
L1
L5
-
0
F7
7
K2
K3
K5
J2
L6
2
2
-
0
G8
7
K4
K1
J3
VREF
0
C5
7
-
0
D6
7
-
0
E7
7
H1
H3
H4
F2
G3
E2
G5
D2
C1
J5
-
0
A4
7
H2
G1
F1
H5
E1
F3
E3
F5
-
0
F8
7
2
2
VREF
0
IO_L4N
IO_L4P
B5
7
-
0
D7
7
-
0
IO_VREF_L5N_YY
IO_L5P_YY
IO_L6N_YY
IO_L6P_YY
IO_L7N_Y
IO_L7P_Y
IO_VREF_L8N_Y
IO_L8P_Y
E8
7
VREF
0
G9
7
-
VREF
-
0
A5
7
0
F9
7
0
D8
1. AO in the XCV200E.
2. AO in the XCV300E.
0
C7
0
B72
E9
0
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
0
Pin Description
IO_L9N
Pin #
A7
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L22N
Pin #
E14
F13
D14
A14
C14
H14
G14
C15
E15
D15
C16
F15
G15
D16
E16
A17
C17
E17
F16
D17
F17
C18
A18
G16
C19
G17
D18
B192
D19
E18
F18
B20
G19
C20
G18
E19
A21
0
IO_L9P
D9
IO_L22P
0
IO_L10N
B8
IO_L23N_Y
0
IO_VREF_L10P
IO_L11N_YY
IO_L11P_YY
IO_L12N_Y
G10
C9
IO_VREF_L23P_Y
IO_L24N_Y
0
0
F10
A8
IO_L24P_Y
0
IO_L25N_YY
IO_L25P_YY
IO_L26N_YY
IO_VREF_L26P_YY
IO_L27N_YY
IO_L27P_YY
IO_L28N
0
IO_L12P_Y
E10
G11
D10
B10
F11
C10
E11
G12
D11
C11
F12
A11
E12
D12
C12
A12
H13
B13
0
IO_L13N_YY
IO_L13P_YY
IO_L14N_YY
IO_L14P_YY
IO_L15N
0
0
0
0
0
IO_L15P
IO_L28P
0
IO_L16N_YY
IO_L16P_YY
IO_VREF_L17N_YY
IO_L17P_YY
IO_L18N_YY
IO_L18P_YY
IO_L19N_Y
IO_L29N_YY
IO_L29P_YY
IO_L30N_YY
IO_L30P_YY
IO_L31N_Y
0
0
0
0
0
IO_L31P_Y
0
IO_L32N_YY
IO_L32P_YY
IO_L33N_YY
IO_VREF_L33P_YY
IO_L34N_YY
IO_L34P_YY
IO_L35N_Y
0
IO_L19P_Y
0
IO_VREF_L20N_Y
IO_L20P_Y
0
0
IO_LVDS_DLL_L21N
1
1
1
1
1
1
1
1
1
1
1
GCK2
C13
A131
A161
A19
IO
IO_VREF_L35P_Y
IO_L36N_Y
IO
IO
IO_L36P_Y
IO
A20
IO_L37N_YY
IO_L37P_YY
IO_L38N_YY
IO_VREF_L38P_YY
IO_L39N_YY
IO_L39P_YY
IO_L40N_YY
IO
A22
IO
A241
B151
B171
B23
IO
IO
IO
IO_LVDS_DLL_L21P
F14
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
Pin Description
IO_L40P_YY
Pin #
D20
F19
C21
B22
E20
A23
D21
C22
E21
Bank
2
Pin Description
IO_VREF_L54P_Y
IO_L54N_Y
Pin #
G262
J22
1
1
1
1
1
1
1
1
1
IO_L41N_YY
2
IO_VREF_L41P_YY
IO_L42N_YY
2
IO_L55P_YY
IO_L55N_YY
IO_L56P_YY
IO_VREF_L56N_YY
IO_D2_L57P_YY
IO_L57N_YY
IO_L58P_YY
IO_L58N_YY
IO_L59P_Y
H24
J23
2
IO_L42P_YY
2
J24
IO_L43N_Y
2
K20
K22
K21
H25
K23
L20
J26
IO_L43P_Y
2
IO_WRITE_L44N_YY
IO_CS_L44P_YY
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO
IO
D251
D26
E26
F26
H261
K261
M251
N261
K24
E23
F22
E24
F20
G21
G22
F24
H20
E25
H21
F23
G23
H23
J20
2
2
IO_L59N_Y
IO
2
IO_L60P_Y
K25
L22
L21
L23
M20
L24
M23
M22
L26
M21
N19
M24
M26
N20
N24
N21
N23
N22
IO
2
IO_L60N_Y
IO
2
IO_L61P_Y
IO
2
IO_L61N_Y
IO
2
IO_L62P_Y
IO
2
IO_L62N_Y
IO_D1
2
IO_VREF_L63P_YY
IO_D3_L63N_YY
IO_L64P_YY
IO_L64N_YY
IO_L65P_Y
IO_DOUT_BUSY_L45P_YY
IO_DIN_D0_L45N_YY
IO_L46P_YY
IO_L46N_YY
IO_L47P_Y
IO_L47N_Y
IO_VREF_L48P_Y
IO_L48N_Y
IO_L49P_Y
IO_L49N_Y
IO_L50P_YY
IO_L50N_YY
IO_VREF_L51P_YY
IO_L51N_YY
IO_L52P_YY
IO_L52N_YY
IO_L53P_Y
IO_L53N_Y
2
2
2
2
2
IO_L65N_Y
2
IO_VREF_L66P_Y
IO_L66N_Y
2
2
IO_L67P_YY
IO_L67N_YY
IO_L68P_YY
IO_L68N_YY
2
2
2
3
3
3
3
3
3
IO
IO
IO
IO
IO
IO
P24
P261
R261
T261
U261
W25
G24
H22
J21
G25
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
61
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO
Pin #
Y26
AB25
AC251
AC26
P21
P23
P22
R25
P19
P20
R21
R22
R24
R23
T24
Bank
Pin Description
IO_VREF_L85N_YY
IO_L86P_Y
Pin #
W23
AA24
Y23
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
IO
IO_L86N_Y
IO
IO_L87P_Y
AB26
W21
Y22
IO_L69P_YY
IO_L69N_YY
IO_L70P_Y
IO_VREF_L70N_Y
IO_L71P_Y
IO_L71N_Y
IO_L72P_YY
IO_L72N_YY
IO_D4_L73P_YY
IO_VREF_L73N_YY
IO_L74P_Y
IO_L74N_Y
IO_L75P_Y
IO_L75N_Y
IO_L76P_Y
IO_L76N_Y
IO_L77P_Y
IO_L77N_Y
IO_L78P_YY
IO_L78N_YY
IO_L79P_YY
IO_D5_L79N_YY
IO_D6_L80P_YY
IO_VREF_L80N_YY
IO_L81P_YY
IO_L81N_YY
IO_L82P_Y
IO_VREF_L82N_Y
IO_L83P_Y
IO_L83N_Y
IO_L84P_YY
IO_L84N_YY
IO_L85P_YY
IO_L87N_Y
IO_L88P_Y
IO_VREF_L88N_Y
IO_L89P_Y
W22
AA23
AB24
W20
AC24
AB23
Y21
IO_L89N_Y
IO_L90P_YY
IO_L90N_YY
IO_D7_L91P_YY
IO_INIT_L91N_YY
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
GCK0
AA14
AC18
AE151
AE20
AE23
AF141
AF161
AF181
AF21
AF231
AC22
AD26
AD23
AA20
Y19
R20
T22
IO
IO
U24
T23
IO
IO
U25
T21
IO
IO
U20
U22
V26
T20
IO
IO
IO
IO_L92P_YY
IO_L92N_YY
IO_L93P_Y
IO_L93N_Y
IO_L94P_YY
IO_L94N_YY
IO_VREF_L95P_YY
IO_L95N_YY
IO_L96P
IO_L96N
IO_L97P
IO_L97N
IO_VREF_L98P_YY
U23
V24
U21
V23
W24
V22
W262
Y25
V21
V20
AA26
Y24
AC21
AD22
AB20
AE22
Y18
AF22
AA19
AD21
Module 4 of 4
62
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L98N_YY
IO_L99P_YY
IO_L99N_YY
IO_L100P_Y
IO_L100N_Y
IO_VREF_L101P_Y
IO_L101N_Y
IO_L102P
Pin #
AB19
AC20
AA18
AC19
AD20
AF202
AB18
AD19
Y17
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO
Pin #
AD7
IO
AD13
AE4
IO
IO
AE7
IO
AE121
AF31
AF5
IO
IO
IO
AF101
AF111
AF13
AA13
AF12
AC13
W13
IO_L102N
IO
IO_L103P
AE19
AD18
AF19
AA17
AC17
AB17
Y16
IO_LVDS_DLL_L115N
IO_L116P_Y
IO_VREF_L116N_Y
IO_L117P_Y
IO_L117N_Y
IO_L118P_YY
IO_L118N_YY
IO_L119P_YY
IO_VREF_L119N_YY
IO_L120P_YY
IO_L120N_YY
IO_L121P
IO_VREF_L103N
IO_L104P_YY
IO_L104N_YY
IO_L105P_Y
IO_L105N_Y
IO_L106P_YY
IO_L106N_YY
IO_L107P_YY
IO_L107N_YY
IO_L108P
AA12
AD12
AC12
AB12
AD11
Y12
AE17
AF17
AA16
AD17
AB16
AC16
AD16
AC15
Y15
IO_L108N
AB11
AD10
AC11
AE10
AC10
AA11
Y11
IO_L109P_YY
IO_L109N_YY
IO_VREF_L110P_YY
IO_L110N_YY
IO_L111P_YY
IO_L111N_YY
IO_L112P_Y
IO_L112N_Y
IO_VREF_L113P_Y
IO_L113N_Y
IO_L114P
IO_L121N
IO_L122P_YY
IO_L122N_YY
IO_L123P_YY
IO_L123N_YY
IO_L124P_Y
IO_L124N_Y
IO_L125P_YY
IO_L125N_YY
IO_L126P_YY
IO_VREF_L126N_YY
IO_L127P_YY
IO_L127N_YY
IO_L128P_Y
IO_VREF_L128N_Y
IO_L129P_Y
AD15
AA15
W14
AD9
AB15
AF15
Y14
AB10
AF9
AD8
AD14
AB14
AC14
AA10
AE8
IO_L114N
IO_LVDS_DLL_L115P
Y10
AC9
5
5
GCK1
IO
AB13
Y131
AF82
AF7
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
63
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
Pin Description
IO_L129N_Y
Pin #
AB9
AA9
AF6
AC8
AC7
AD6
Y9
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L142P_YY
IO_VREF_L143N_YY
IO_L143P_YY
IO_L144N_YY
IO_L144P_YY
IO_L145N_Y
Pin #
Y4
V5
W5
AA1
V6
W4
Y3
Y12
U7
W1
V4
W2
U6
V3
T5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L130P_YY
IO_L130N_YY
IO_L131P_YY
IO_VREF_L131N_YY
IO_L132P_YY
IO_L132N_YY
IO_L133P_YY
IO_L133N_YY
IO_L134P_YY
IO_VREF_L134N_YY
IO_L135P_YY
IO_L135N_YY
IO_L136P_Y
IO_L145P_Y
AE5
AA8
AC6
AB8
AD5
AA7
AF4
AC5
IO_VREF_L146N_Y
IO_L146P_Y
IO_L147N_YY
IO_L147P_YY
IO_L148N_YY
IO_VREF_L148P_YY
IO_L149N_YY
IO_L149P_YY
IO_L150N_YY
IO_L150P_YY
IO_L151N_Y
IO_L136N_Y
U5
U4
T7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO
P3
AA3
AC11
P11
R21
T11
V11
W3
IO
IO
IO_L151P_Y
U3
U2
T6
IO
IO_L152N_Y
IO
IO_L152P_Y
IO
IO_L153N_Y
U1
T4
IO
IO_L153P_Y
IO
IO_L154N_Y
R7
T3
IO
Y2
IO_L154P_Y
IO
Y6
IO_VREF_L155N_YY
IO_L155P_YY
IO_L156N_YY
IO_L156P_YY
IO_L157N_Y
R4
R6
R3
R5
P8
P7
R1
P6
P5
P4
IO_L137N_YY
IO_L137P_YY
IO_L138N_YY
IO_L138P_YY
IO_L139N_Y
IO_L139P_Y
IO_VREF_L140N_Y
IO_L140P_Y
IO_L141N_Y
IO_L141P_Y
IO_L142N_YY
AA5
AC3
AC2
AB4
W6
IO_L157P_Y
AA4
AB3
Y5
IO_VREF_L158N_Y
IO_L158P_Y
IO_L159N_YY
IO_L159P_YY
AB2
V7
AB1
7
IO
D11
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO
Pin #
D2
D3
E1
G1
H2
J11
L11
M11
N11
N5
N8
N6
N3
N4
M2
N7
M7
M6
M3
M4
M5
L3
Bank
7
Pin Description
IO_L174N_Y
Pin #
J5
IO
7
IO_VREF_L174P_Y
IO_L175N_Y
H12
G2
J6
IO
7
IO
7
IO_L175P_Y
IO
7
IO_L176N_YY
IO_L176P_YY
IO_L177N_YY
IO_VREF_L177P_YY
IO_L178N_Y
J7
IO
7
F1
IO
7
H4
G4
F3
IO
7
IO
7
IO_L160N_YY
IO_L160P_YY
IO_L161N_YY
IO_L161P_YY
IO_L162N_Y
IO_VREF_L162P_Y
IO_L163N_Y
IO_L163P_Y
IO_L164N_YY
IO_L164P_YY
IO_L165N_YY
IO_VREF_L165P_YY
IO_L166N_Y
IO_L166P_Y
IO_L167N_Y
IO_L167P_Y
IO_L168N_Y
IO_L168P_Y
IO_L169N_Y
IO_L169P_Y
IO_L170N_YY
IO_L170P_YY
IO_L171N_YY
IO_L171P_YY
IO_L172N_YY
IO_VREF_L172P_YY
IO_L173N_YY
IO_L173P_YY
7
IO_L178P_Y
H5
E2
H6
G5
F4
7
IO_L179N_Y
7
IO_L179P_Y
7
IO_L180N_Y
7
IO_VREF_L180P_Y
IO_L181N_Y
7
H7
G6
E3
E4
7
IO_L181P_Y
7
IO_L182N_YY
IO_L182P_YY
7
2
CCLK
DONE
DXN
D24
AB21
AB7
Y8
3
NA
NA
NA
NA
NA
NA
NA
NA
2
L7
DXP
L6
M0
AD4
W7
K2
L4
M1
M2
AB6
AA22
E6
K1
K3
L5
PROGRAM
TCK
TDI
D22
C23
F5
K5
J3
TDO
NA
TMS
K4
J4
NA
NA
NA
NA
NA
NC
NC
NC
NC
NC
T25
T2
H3
K6
K7
G3
P2
N25
L25
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
65
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
NC
Pin #
L2
Bank
NA
Pin Description
Pin #
A2
NC
NC
NC
F6
NA
A15
NC
F25
F21
F2
NC
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
G7
G20
H8
NC
NC
C26
C25
C2
NC
H19
J9
NC
NC
C1
J10
J11
J16
J17
J18
K9
NC
B6
NC
B26
B24
B21
B16
B11
B1
NC
NC
NC
NC
K18
L9
NC
NC
AF25
AF24
AF2
AE6
AE3
AE26
AE24
AE21
AE16
AE14
AE11
AE1
AD25
AD2
AD1
AA6
AA25
AA21
AA2
A3
L18
T9
NC
NC
T18
U9
NC
NC
U18
V9
NC
NC
V10
V11
V16
V17
V18
Y7
NC
NC
NC
NC
NC
NC
Y20
W8
W19
NC
NC
NC
NC
0
0
0
0
0
VCCO
VCCO
VCCO
VCCO
VCCO
J13
J12
H9
NC
NC
NC
H12
H11
NC
A25
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
0
1
1
1
1
1
1
2
2
2
2
2
2
3
3
3
3
3
3
4
4
4
4
4
4
5
5
5
5
5
5
6
6
6
6
6
6
Pin Description
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
Pin #
H10
J15
J14
H18
H17
H16
H15
N18
M19
M18
L19
K19
J19
V19
U19
T19
R19
R18
P18
W18
W17
W16
W15
V15
V14
W9
Bank
Pin Description
VCCO
Pin #
N9
7
7
7
7
7
7
VCCO
M9
M8
L8
VCCO
VCCO
VCCO
K8
VCCO
J8
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V25
V2
U17
U16
U15
U14
U13
U12
U11
U10
T17
T16
T15
T14
T13
T12
T11
T10
R17
R16
R15
R14
R13
R12
R11
R10
P25
P17
P16
P15
W12
W11
W10
V13
V12
V8
U8
T8
R9
R8
P9
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
67
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 20: FG676 — XCV400E, XCV600E
Table 20: FG676 — XCV400E, XCV600E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
P14
P13
P12
P11
P10
N2
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Notes:
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
K10
J25
J2
E5
E22
D4
N17
N16
N15
N14
N13
N12
N11
N10
M17
M16
M15
M14
M13
M12
M11
M10
L17
L16
L15
L14
L13
L12
L11
L10
K17
K16
K15
K14
K13
K12
K11
D23
C3
C24
B9
B25
B2
B18
B14
AF26
AF1
AE9
AE25
AE2
AE18
AE13
AD3
AD24
AC4
AC23
AB5
AB22
A26
A1
1. NC in the XCV400E.
2. VREF or I/O option only in the XCV600E; otherwise, I/O
option only.
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E
FG676 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
P
N
Other
Ban
k
Pair
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Pin
Pin
AO
Functions
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
E12
C12
H13
F14
F13
A14
H14
C15
D15
F15
D16
A17
E17
D17
C18
G16
G17
B19
E18
B20
C20
E19
D20
C21
E20
D21
E21
E23
E24
G21
F24
E25
F23
H23
A11
D12
A12
B13
E14
D14
C14
G14
E15
C16
G15
E16
C17
F16
F17
A18
C19
D18
D19
F18
G19
G18
A21
F19
B22
A23
C22
F22
F20
G22
H20
H21
G23
J20
-
1
1
-
VREF
NA
NA
1
IO_LVDS_DLL
-
VREF
1
-
Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E
-
P
N
Other
Ban
k
VREF
Pair
Pin
Pin
AO
Functions
-
Global Differential Clock
-
-
3
2
1
0
0
1
5
4
E13
C13
B13
F14
NA
NA
IO_DLL_L21N
IO_DLL_L21P
-
-
AB13
AA14
AF13
AC14
IOLVDS
NA IO_DLL_L115N
NA IO_DLL_L115P
1
-
-
VREF
Total Pairs: 183, Asynchronous Output Pairs: 97
-
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F7
C5
C4
G8
D6
1
-
1
1
VREF
-
-
2
E7
VREF
-
3
F8
A4
NA
NA
-
VREF
4
D7
B5
-
-
5
G9
E8
VREF
-
6
F9
A5
-
VREF
7
C7
D8
1
-
-
8
E9
B7
1
VREF
2
-
9
D9
A7
NA
NA
-
CS
10
11
12
13
14
15
16
17
G10
F10
E10
D10
F11
E11
D11
F12
B8
VREF
DIN, D0
C9
-
-
A8
1
-
2
1
1
-
G11
B10
C10
G12
C11
-
VREF
-
-
-
NA
-
-
VREF
VREF
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
69
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 21: FG676 Differential Pin Pair Summary
Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E
XCV400E, XCV600E
P
N
Other
P
N
Other
Ban
k
Ban
k
Pair
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Pin
Pin
AO
Functions
Pair
86
Pin
Pin
AO
1
Functions
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
G24
J21
H22
G25
J22
-
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
AA24
AB26
Y22
Y23
W21
-
2
1
-
87
2
-
G26
H24
J24
VREF
88
W22
1
VREF
J23
-
89
AA23
W20
AB24
AC24
Y21
2
-
K20
K21
K23
J26
VREF
90
-
K22
H25
L20
K25
L21
M20
M23
L26
N19
M26
N24
N23
P21
P22
P19
R21
R24
T24
T22
T23
T21
U22
T20
V24
V23
V22
Y25
V20
Y24
D2
91
AB23
AC22
AD23
Y19
INIT
-
92
AD26
AA20
AC21
AB20
Y18
-
2
1
1
1
-
93
1
-
L22
-
94
-
L23
-
95
AD22
AE22
AF22
AD21
AC20
AC19
AF20
AD19
AE19
AF19
AC17
Y16
VREF
L24
-
96
NA
NA
-
M22
M21
M24
N20
N21
N22
P23
R25
P20
R22
R23
R20
U24
U25
U20
V26
U23
U21
W24
W26
V21
AA26
W23
D3
97
AA19
AB19
AA18
AD20
AB18
Y17
-
-
98
VREF
2
1
-
99
-
VREF
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
1
-
-
1
VREF
-
NA
NA
-
-
AD18
AA17
AB17
AE17
AA16
AB16
AD16
Y15
VREF
1
2
VREF
-
-
1
-
-
-
VREF
AF17
AD17
AC16
AC15
AD15
W14
-
1
1
1
2
-
NA
-
-
-
-
VREF
-
AA15
AB15
Y14
-
-
1
1
-
D5
AF15
AD14
AC14
AA13
AC13
AA12
AC12
VREF
VREF
AB14
AF13
AF12
W13
NA
NA
1
-
-
IO_LVDS_DLL
1
2
VREF
VREF
-
-
1
-
-
AD12
AB12
VREF
VREF
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 21: FG676 Differential Pin Pair Summary
Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E
XCV400E, XCV600E
P
N
Other
P
N
Other
Ban
k
Ban
k
Pair
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Pin
Pin
AO
Functions
Pair
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
Notes:
Pin
Pin
AO
Functions
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
AD11
AB11
AC11
AC10
Y11
AB10
AD8
AE8
AC9
AF7
AA9
AC8
AD6
AE5
AC6
AD5
AF4
AC3
AB4
AA4
Y5
Y12
AD10
AE10
AA11
AD9
AF9
AA10
Y10
AF8
AB9
AF6
AC7
Y9
-
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
T3
R6
R5
P7
P6
P4
N8
N3
M2
M7
M3
M5
L7
R7
R4
R3
P8
R1
P5
N5
N6
N4
N7
M6
M4
L3
1
-
NA
-
VREF
-
-
-
2
1
-
1
-
VREF
-
-
VREF
-
-
-
1
1
VREF
1
2
VREF
-
-
-
-
VREF
VREF
-
1
1
1
2
-
AA8
AB8
AA7
AC5
AA5
AC2
W6
-
K2
K1
L5
L6
-
VREF
L4
-
-
K3
K5
K4
H3
K7
J5
-
2
-
J3
-
-
J4
-
-
K6
G3
H1
J6
VREF
2
1
1
-
-
AB3
AB2
AB1
V5
VREF
1
2
VREF
V7
-
G2
J7
-
Y4
-
F1
G4
H5
H6
F4
G6
E4
-
W5
VREF
H4
F3
E2
G5
H7
E3
VREF
V6
AA1
W4
-
1
2
1
2
-
Y3
2
1
-
-
U7
Y1
VREF
VREF
V4
W1
-
-
-
U6
W2
VREF
T5
V3
-
-
-
-
-
1. AO in the XCV600E.
2. AO in the XCV400E.
U4
U5
U3
T7
2
1
1
T6
U2
T4
U1
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
FG680 Fine-Pitch Ball Grid Array Package
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L13N_Y
Pin #
A29
B29
B28
A28
C28
B27
D27
A27
C27
B26
D26
C26
A261
D25
B25
C25
A25
D24
A24
B23
C24
A23
B24
B22
E23
A22
D23
B21
C23
A21
E22
B20
C22
D222
XCV600E, XCV1000E, XCV1600E, and XCV2000E
devices in the FG680 fine-pitch Ball Grid Array package
have footprint compatibility. Pins labeled I0_VREF can be
used as either in all parts unless device-dependent as indi-
cated in the footnotes. If the pin is not used as VREF, it can
be used as general I/O. Immediately following Table 22, see
Table 23 for Differential Pair information.
IO_L13P_Y
IO_VREF_L14N_YY
IO_L14P_YY
IO_L15N_YY
IO_L15P_YY
IO_L16N_Y
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
0
Pin Description
GCK3
Pin #
A20
D35
B36
C35
A36
D341
B35
C34
A35
D33
B34
C33
A34
D32
B33
C32
D31
A33
C31
B32
B31
A323
D30
A31
C30
B30
D29
A30
C29
IO_L16P_Y
0
IO
IO_L17N_Y
0
IO
IO_L17P_Y
0
IO_L0N_Y
IO_L18N_YY
IO_L18P_YY
IO_VREF_L19N_YY
IO_L19P_YY
IO_L20N_Y
0
IO_L0P_Y
0
IO_VREF_L1N_Y
IO_L1P_Y
0
0
IO_L2N_YY
IO_L2P_YY
IO_VREF_L3N_YY
IO_L3P_YY
IO_L4N
0
IO_L20P_Y
0
IO_L21N_Y
0
IO_L21P_Y
0
IO_L22N_YY
IO_L22P_YY
IO_VREF_L23N_YY
IO_L23P_YY
IO_L24N_Y
0
IO_L4P
0
IO_L5N_Y
0
IO_L5P_Y
0
IO_L6N_YY
IO_L6P_YY
IO_VREF_L7N_YY
IO_L7P_YY
IO_L8N_Y
0
IO_L24P_Y
0
IO_L25N_Y
0
IO_L25P_Y
0
IO_L26N_YY
IO_L26P_YY
IO_VREF_L27N_YY
IO_L27P_YY
IO_L28N_Y
0
IO_L8P_Y
0
IO_VREF_L9N_Y
IO_L9P_Y
0
0
IO_L10N_YY
IO_L10P_YY
IO_VREF_L11N_YY
IO_L11P_YY
IO_L12N_Y
IO_L12P_Y
0
IO_L28P_Y
0
IO_LVDS_DLL_L29N
IO_VREF
0
0
0
1
GCK2
D21
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO
Pin #
C5
Bank
1
Pin Description
IO_L47N_Y
Pin #
B11
C11
A10
D11
B10
C10
A9
IO_LVDS_DLL_L29P
IO_L30N_Y
A19
C21
B192
C19
A18
D19
B18
C18
A17
D18
B17
E18
A16
C17
D17
B16
E17
A15
C16
B15
D16
A14
B141
C15
A13
D15
B13
C14
A12
D14
C13
B12
D13
A11
C12
1
IO_L47P_Y
1
IO_L48N_YY
IO_VREF_L48P_YY
IO_L49N_YY
IO_L49P_YY
IO_L50N_Y
IO_VREF_L30P_Y
IO_L31N_Y
1
1
IO_L31P_Y
1
IO_L32N_YY
IO_VREF_L32P_YY
IO_L33N_YY
IO_L33P_YY
IO_L34N_Y
1
1
IO_VREF_L50P_Y
IO_L51N_Y
D103
B9
1
1
IO_L51P_Y
C9
1
IO_L52N_YY
IO_VREF_L52P_YY
IO_L53N_YY
IO_L53P_YY
IO_L54N_Y
A8
IO_L34P_Y
1
B8
IO_L35N_Y
1
D9
IO_L35P_Y
1
A7
IO_L36N_YY
IO_VREF_L36P_YY
IO_L37N_YY
IO_L37P_YY
IO_L38N_Y
1
C8
1
IO_L54P_Y
B7
1
IO_L55N_Y
D8
1
IO_L55P_Y
A6
1
IO_L56N_YY
IO_VREF_L56P_YY
IO_L57N_YY
IO_L57P_YY
IO_L58N_Y
C7
IO_L38P_Y
1
B6
IO_L39N_Y
1
D7
IO_L39P_Y
1
A5
IO_L40N_YY
IO_VREF_L40P_YY
IO_L41N_YY
IO_L41P_YY
IO_L42N_Y
1
C6
1
IO_VREF_L58P_Y
IO_L59N_Y
B51
D6
1
1
IO_L59P_Y
A4
1
IO_WRITE_L60N_YY
IO_CS_L60P_YY
B4
IO_L42P_Y
1
D5
IO_L43N_Y
IO_L43P_Y
2
2
2
2
2
2
2
IO
IO
D1
F4
IO_L44N_YY
IO_L44P_YY
IO_L45N_YY
IO_VREF_L45P_YY
IO_L46N_Y
IO_DOUT_BUSY_L61P_YY
IO_DIN_D0_L61N_YY
IO_L62P_Y
E3
C2
D3
F3
IO_L62N_Y
IO_L46P_Y
IO_VREF_L63P
D21
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
73
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L63N
Pin #
G4
G3
E2
H4
E1
H3
F2
Bank
2
Pin Description
IO_L81N_Y
IO_L82P_YY
IO_L82N_YY
IO_L83P
Pin #
T3
IO_L64P
2
P2
IO_L64N
2
U5
IO_VREF_L65P_Y
IO_L65N_Y
IO_L66P_YY
IO_L66N_YY
IO_L67P
2
P1
2
IO_L83N
U4
2
IO_L84P_Y
R2
2
IO_L84N_Y
IO_VREF_L85P_YY
IO_D3_L85N_YY
IO_L86P_YY
IO_L86N_YY
IO_L87P
U3
J4
2
V5
IO_L67N
F1
2
R1
IO_L68P_Y
IO_L68N_Y
IO_VREF_L69P_YY
IO_L69N_YY
IO_L70P_YY
IO_L70N_YY
IO_VREF_L71P
IO_L71N
J3
2
V4
G2
G1
K4
H2
K3
H13
L4
2
T2
2
V3
2
IO_L87N
T1
2
IO_L88P
W4
U2
2
IO_L88N
2
IO_VREF_L89P_YY
IO_L89N_YY
IO_L90P_YY
IO_L90N_YY
IO_VREF_L91P
IO_L91N
W3
U1
2
IO_L72P
J2
2
AA3
V2
IO_L72N
L3
2
IO_VREF_L73P_YY
IO_L73N_YY
IO_L74P_YY
IO_L74N_YY
IO_L75P
J1
2
AA42
V1
M3
K2
N4
K1
N3
L2
2
2
IO_L92P_YY
IO_L92N_YY
AB2
W2
2
IO_L75N
3
3
3
3
3
3
3
3
3
3
3
3
IO
IO
AP3
AT3
AB3
AB4
W12
AB5
Y2
IO_VREF_L76P_YY
IO_D1_L76N_YY
IO_D2_L77P_YY
IO_L77N_YY
IO_L78P_Y
IO_L78N_Y
IO_L79P
P4
P3
L1
IO
IO_L93P
IO_VREF_L93N
IO_L94P_YY
IO_L94N_YY
IO_L95P_YY
IO_VREF_L95N_YY
IO_L96P
R4
M2
R3
M1
T4
AC2
Y1
IO_L79N
IO_L80P
AC3
AA1
AC4
IO_L80N
N2
N11
IO_L96N
IO_VREF_L81P_Y
IO_L97P
Module 4 of 4
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Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L97N
Pin #
AA2
AC5
AB1
AD3
AC1
AD1
AD4
AD2
AE3
AE1
AE4
AE2
AF31
AF4
AF1
AG3
AF2
AG4
AG1
AH3
AG2
AH1
AJ2
Bank
Pin Description
IO_VREF_L115N_YY
IO_L116P_Y
Pin #
AL4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L98P_YY
IO_L98N_YY
IO_D4_L99P_YY
IO_VREF_L99N_YY
IO_L100P_Y
IO_L100N_Y
IO_L101P
AM3
AN1
AM4
AP1
AN2
AP2
AN3
AR1
AN4
AT1
IO_L116N_Y
IO_L117P
IO_L117N
IO_L118P_YY
IO_L118N_YY
IO_L119P_Y
IO_L101N
IO_VREF_L119N_Y
IO_L120P
IO_L102P_YY
IO_L102N_YY
IO_L103P_Y
IO_VREF_L103N_Y
IO_L104P
IO_L120N
IO_L121P
AR2
AP41
AT2
IO_VREF_L121N
IO_L122P_Y
IO_L104N
IO_L122N_Y
AR3
AR4
AU2
IO_L105P
IO_D7_L123P_YY
IO_INIT_L123N_YY
IO_L105N
IO_L106P_Y
IO_L106N_Y
IO_L107P_YY
IO_D5_L107N_YY
IO_D6_L108P_YY
IO_VREF_L108N_YY
IO_L109P
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
GCK0
IO
AW19
AV3
AU4
AV5
AT6
IO_L124P_YY
IO_L124N_YY
IO_L125P_Y
IO_L125N_Y
IO_VREF_L126P_Y
IO_L126N_Y
IO_L127P_YY
IO_L127N_YY
IO_VREF_L128P_YY
IO_L128N_YY
IO_L129P_Y
IO_L129N_Y
IO_L130P_Y
IO_L130N_Y
IO_L131P_YY
IO_L131N_YY
AH2
AJ3
AV4
AU61
AW4
AT7
IO_L109N
IO_L110P_YY
IO_L110N_YY
IO_L111P_YY
IO_VREF_L111N_YY
IO_L112P
AJ1
AJ4
AK1
AK3
AK2
AK4
AL1
AL23
AM1
AL3
AM2
AW5
AU7
AV6
AT8
IO_L112N
IO_L113P
AW6
AU8
AV7
AT9
IO_VREF_L113N
IO_L114P_YY
IO_L114N_YY
IO_L115P_YY
AW7
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_VREF_L132P_YY
IO_L132N_YY
IO_L133P_Y
Pin #
AV8
Bank
Pin Description
IO_L150P_Y
Pin #
AT18
AV17
AU18
AW17
AT19
AV18
AU19
AW18
AU212
AV19
AT21
4
4
4
4
4
4
4
4
4
4
4
AU9
IO_L150N_Y
AW8
IO_L151P_YY
IO_L151N_YY
IO_VREF_L152P_YY
IO_L152N_YY
IO_L153P_Y
IO_L133N_Y
AT10
AV93
AU10
AW9
IO_VREF_L134P_Y
IO_L134N_Y
IO_L135P_YY
IO_L135N_YY
IO_VREF_L136P_YY
IO_L136N_YY
IO_L137P_Y
AT11
AV10
AU11
AW10
AU12
AV11
AT13
AW11
AU13
AT14
AV12
AU14
AW12
AT15
AV13
AU15
AW13
AV141
AT16
AW14
AU16
AV15
AR17
AW15
AT17
AU17
AV16
AR18
AW16
IO_L153N_Y
IO_VREF_L154P
IO_L154N
IO_LVDS_DLL_L155P
IO_L137N_Y
IO_L138P_Y
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
IO
AU22
AT34
IO_L138N_Y
IO_VREF_L139P_YY
IO_L139N_YY
IO_L140P_YY
IO_L140N_YY
IO_L141P_Y
IO
AW20
AT22
IO_LVDS_DLL_L155N
IO_VREF_L156P_Y
IO_L156N_Y
AV202
AR22
AV23
AW21
AU23
AV21
AT23
IO_L157P_YY
IO_VREF_L157N_YY
IO_L158P_YY
IO_L158N_YY
IO_L159P_Y
IO_L141N_Y
IO_L142P_Y
IO_L142N_Y
IO_L143P_YY
IO_L143N_YY
IO_VREF_L144P_YY
IO_L144N_YY
IO_L145P_Y
IO_L159N_Y
AW22
AR23
AV22
AV24
AW23
AW24
AU24
AW25
AT24
IO_L160P_Y
IO_L160N_Y
IO_L161P_YY
IO_VREF_L161N_YY
IO_L162P_YY
IO_L162N_YY
IO_L163P_Y
IO_L145N_Y
IO_L146P_Y
IO_L146N_Y
IO_L147P_YY
IO_L147N_YY
IO_VREF_L148P_YY
IO_L148N_YY
IO_L149P_Y
IO_L163N_Y
IO_L164P_Y
AV25
AU25
AW26
AT251
IO_L164N_Y
IO_L165P_YY
IO_VREF_L165N_YY
IO_L149N_Y
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L166P_YY
IO_L166N_YY
IO_L167P_Y
Pin #
AV26
AW27
AU26
AV27
AT26
AW28
AU27
AV28
AW29
AT27
AW30
AU28
AV30
AV29
AW31
AU29
AV31
AT29
AW32
AU303
AW33
AT30
AV33
AU31
AT31
AW34
AV32
AV34
AU32
AW35
AT32
AV35
AU33
AW36
AT33
AV361
Bank
Pin Description
IO_L184P_Y
IO_L184N_Y
Pin #
AU34
AU36
5
5
IO_L167N_Y
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO
IO
W39
AR37
AR39
AR36
AT38
AR38
AP36
AT391
AP37
AP38
AP39
AN36
AN38
AN37
AN39
AM36
AM38
AM37
AL36
AM39
AL37
AL38
AK36
AL393
AK37
AK38
AJ36
AK39
AJ37
AJ38
AH37
AJ39
AH38
IO_L168P_Y
IO_L168N_Y
IO
IO_L169P_YY
IO_L169N_YY
IO_L170P_YY
IO_VREF_L170N_YY
IO_L171P_Y
IO_L185N_YY
IO_L185P_YY
IO_L186N_Y
IO_L186P_Y
IO_VREF_L187N
IO_L187P
IO_L171N_Y
IO_L172P_Y
IO_L188N
IO_L172N_Y
IO_L188P
IO_L173P_YY
IO_VREF_L173N_YY
IO_L174P_YY
IO_L174N_YY
IO_L175P_Y
IO_VREF_L189N_Y
IO_L189P_Y
IO_L190N_YY
IO_L190P_YY
IO_L191N
IO_VREF_L175N_Y
IO_L176P_Y
IO_L191P
IO_L192N_Y
IO_L192P_Y
IO_VREF_L193N_YY
IO_L193P_YY
IO_L194N_YY
IO_L194P_YY
IO_VREF_L195N
IO_L195P
IO_L176N_Y
IO_L177P_YY
IO_VREF_L177N_YY
IO_L178P_YY
IO_L178N_YY
IO_L179P_Y
IO_L179N_Y
IO_L180P_Y
IO_L196N
IO_L180N_Y
IO_L196P
IO_L181P_YY
IO_VREF_L181N_YY
IO_L182P_YY
IO_L182N_YY
IO_L183P_Y
IO_VREF_L197N_YY
IO_L197P_YY
IO_L198N_YY
IO_L198P_YY
IO_L199N
IO_VREF_L183N_Y
IO_L199P
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
6
Pin Description
IO_VREF_L200N_YY
IO_L200P_YY
IO_L201N_YY
IO_L201P_YY
IO_L202N_Y
IO_L202P_Y
IO_L203N
Pin #
AH39
AG38
AG36
AG39
AG37
AF39
AF36
AE38
AF37
AF38
AE391
AE36
AD38
AE37
AD39
AD36
AC38
AC39
AD37
AB38
AC35
AB39
AC36
AA38
AC37
AA39
AB35
Y38
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L216N_YY
IO_L216P_YY
IO_L217N
Pin #
AA37
W38
W37
V392
W36
U39
V38
U38
V37
T39
V36
T38
V35
R39
U37
U36
R38
U35
P39
T37
P38
T36
N39
N381
R37
M39
R36
M38
P37
L39
6
6
6
IO_VREF_L217P
IO_L218N_YY
IO_L218P_YY
IO_L219N_YY
IO_VREF_L219P_YY
IO_L220N
6
6
6
6
IO_L203P
6
IO_L204N
6
IO_L204P
IO_L220P
6
IO_VREF_L205N_Y
IO_L205P_Y
IO_L206N_YY
IO_L206P_YY
IO_L207N
IO_L221N
6
IO_L221P
6
IO_L222N_YY
IO_L222P_YY
IO_L223N_YY
IO_VREF_L223P_YY
IO_L224N_Y
IO_L224P_Y
IO_L225N
6
6
6
IO_L207P
6
IO_L208N_Y
IO_L208P_Y
IO_VREF_L209N_YY
IO_L209P_YY
IO_L210N_YY
IO_L210P_YY
IO_L211N
6
6
6
IO_L225P
6
IO_L226N_YY
IO_L226P_YY
IO_L227N_Y
IO_VREF_L227P_Y
IO_L228N
6
6
6
IO_L211P
6
IO_L212N
6
IO_L212P
IO_L228P
6
IO_VREF_L213N_YY
IO_L213P_YY
IO_L214N_YY
IO_L214P_YY
IO_VREF_L215N
IO_L215P
IO_L229N
6
IO_L229P
6
AB36
Y39
IO_L230N_Y
IO_L230P_Y
IO_L231N_YY
IO_L231P_YY
IO_L232N_YY
IO_VREF_L232P_YY
IO_L233N
6
6
AB372
AA36
P36
N37
L38
6
7
7
7
IO
IO
IO
C38
B37
F37
N36
K39
M37
IO_L233P
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
7
Pin Description
IO_L234N_YY
IO_L234P_YY
IO_L235N_YY
IO_VREF_L235P_YY
IO_L236N
Pin #
K38
L37
Bank
NA
2
Pin Description
Pin #
B3
TDI
TDO
TMS
7
C4
7
J39
NA
E36
7
L36
7
J38
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
E8
E9
7
IO_L236P
K37
H39
K363
H38
J37
7
IO_L237N
E15
E16
E24
E25
E31
E32
H5
7
IO_VREF_L237P
IO_L238N_YY
IO_L238P_YY
IO_L239N_YY
IO_VREF_L239P_YY
IO_L240N_Y
IO_L240P_Y
IO_L241N
7
7
7
G39
G38
J36
7
7
7
F39
H37
F38
H36
E39
G37
E38
G36
D39
D38
F361
D37
E37
H35
J5
7
7
IO_L241P
J35
7
IO_L242N_YY
IO_L242P_YY
IO_L243N_Y
IO_VREF_L243P_Y
IO_L244N
R5
7
R35
T5
7
7
T35
7
AD5
AD35
AE5
AE35
AL5
AL35
AM5
AM35
AR8
AR9
AR15
AR16
AR24
AR25
AR31
AR32
7
IO_L244P
7
IO_L245N
7
IO_VREF_L245P
IO_L246N_Y
IO_L246P_Y
7
7
2
CCLK
DONE
DXN
E4
3
AU5
NA
NA
NA
NA
NA
NA
NA
AV37
AU35
AT37
AU38
AT35
AT5
DXP
M0
M1
M2
PROGRAM
TCK
C36
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
79
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
Pin Description
Pin #
Bank
Pin Description
VCCO
Pin #
AR26
AP35
AN35
AK35
AJ35
AG35
AF35
P35
5
6
6
6
6
6
6
7
7
7
7
7
7
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
2
2
2
3
3
3
3
3
3
4
4
4
4
4
4
5
5
5
5
5
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
E34
E33
E30
E29
E27
E26
E10
E11
E13
E14
E6
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
N35
VCCO
L35
VCCO
K35
VCCO
G35
E7
VCCO
F35
P5
N5
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Y5
Y4
L5
K5
Y37
Y36
Y35
Y3
G5
F5
AP5
AN5
AK5
AJ5
AG5
AF5
AR10
AR11
AR13
AR14
AR6
AR7
AR34
AR33
AR30
AR29
AR27
W5
W35
M5
M4
M36
M35
E5
E35
E28
E21
E20
E19
E12
D4
D36
D28
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
D20
Bank
NA
Pin Description
GND
Pin #
AR19
AR12
AH5
AH4
AH36
AH35
AA5
AA35
A39
D12
NA
GND
C39
NA
GND
C37
NA
GND
C3
NA
GND
C20
NA
GND
C1
NA
GND
B39
NA
GND
B38
NA
GND
B2
NA
GND
A38
B1
NA
GND
A37
AW39
AW38
AW37
AW3
AW2
AW1
AV39
AV38
AV2
NA
GND
A3
NA
GND
A2
NA
GND
A1
Notes:
1. VREF or I/O option only in the XCV1000E, 1600E, 2000E;
otherwise, I/O option only.
2.
V
REF or I/O option only in the XCV1600E, 2000E; otherwise,
I/O option only.
3. VREF or I/O option only in the XCV2000E; otherwise, I/O
option only.
AV1
AU39
AU37
AU3
AU20
AU1
AT4
AT36
AT28
AT20
AT12
AR5
AR35
AR28
AR21
AR20
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
81
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
FG680 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C26
D25
C25
D24
B23
A23
B22
A22
B21
A21
B20
A19
B19
A18
B18
A17
B17
A16
D17
E17
C16
D16
B14
A13
B13
A12
C13
D13
C12
C11
D11
C10
D10
C9
D26
A26
B25
A25
A24
C24
B24
E23
D23
C23
E22
C22
C21
C19
D19
C18
D18
E18
C17
B16
A15
B15
A14
C15
D15
C14
D14
B12
A11
B11
A10
B10
A9
-
VREF
3
3
-
-
-
VREF
5
5
-
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
-
P
N
Other
-
Pair Bank
Pin
Pin
AO
Functions
VREF
GCLK LVDS
2
NA
2
-
3
2
1
0
0
1
5
4
A20
D21
C22
A19
NA
NA
IO_DLL_L29N
IO_DLL_L29P
IO_DLL_L155N
IO_DLL_L155P
IO_LVDS_DLL
VREF
AU22 AT22 NA
AW19 AT21 NA
IO LVDS
2
-
VREF
-
Total Pairs: 247, Asynchronous Output Pairs: 111
5
5
-
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A36
B35
A35
B34
A34
B33
D31
C31
B31
D30
C30
D29
C29
B29
A28
B27
A27
B26
C35
D34
C34
D33
C33
D32
C32
A33
B32
A32
A31
B30
A30
A29
B28
C28
D27
C27
5
5
-
-
VREF
VREF
2
-
-
3
VREF
3
3
-
4
3
3
-
-
5
-
VREF
6
-
-
7
VREF
5
5
-
8
5
5
-
-
9
VREF
-
10
11
12
13
14
15
16
17
-
VREF
VREF
2
2
-
2
2
-
-
-
VREF
VREF
-
VREF
-
-
-
-
5
5
5
5
B9
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 23: FG680 Differential Pin Pair Summary
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
XCV600E, XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
Functions
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
B8
A7
B7
A6
B6
A5
B5
A4
D5
E3
D3
D2
G3
H4
H3
J4
A8
D9
C8
D8
C7
D7
C6
D6
B4
C2
F3
G4
E2
E1
F2
F1
G2
K4
K3
L4
VREF
86
87
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
V4
T2
T1
-
-
V3
7
4
-
3
3
-
88
W4
U2
-
-
89
W3
U1
VREF
VREF
90
AA3
AA4
AB2
AB4
AB5
AC2
AC3
AC4
AC5
AD3
AD1
AD2
AE1
AE2
AF4
AG3
AG4
AH3
AH1
AH2
AJ1
AK1
AK2
AL1
AM1
AM2
AM3
AM4
AN2
AN3
V2
-
-
91
V1
4
4
VREF
5
5
VREF
92
W2
-
-
93
W1
VREF
CS
94
Y2
-
DIN, D0
95
Y1
VREF
6
4
4
6
-
96
AA1
AA2
AB1
AC1
AD4
AE3
AE4
AF3
AF1
AF2
AG1
AG2
AJ2
AJ3
AJ4
AK3
AK4
AL2
AL3
AL4
AN1
AP1
AP2
AR1
4
7
-
VREF
97
-
-
98
-
VREF
99
VREF
-
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
6
4
-
4
6
-
-
J3
-
-
G1
H2
H1
J2
VREF
6
4
4
6
VREF
-
-
7
4
VREF
-
L3
-
-
J1
M3
N4
N3
P4
L1
VREF
D5
K2
K1
L2
-
VREF
4
-
4
-
D1
-
P3
R4
R3
T4
N1
P2
P1
R2
V5
D2
VREF
M2
M1
N2
T3
U5
U4
U3
R1
6
4
4
6
-
4
7
-
-
VREF
-
-
VREF
VREF
-
-
6
4
-
4
6
-
-
-
D3
6
VREF
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 23: FG680 Differential Pin Pair Summary
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
XCV600E, XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
4
Functions
Pair Bank
Pin
Pin
AO
Functions
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
AN4
AR2
AT2
AR4
AU4
AT6
AU6
AT7
AU7
AT8
AU8
AT9
AV8
AW8
AV9
AW9
AT1
AP4
AR3
AU2
AV5
-
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
AU21 AV19
AT21
2
VREF
4
VREF
AT22 NA
IO_LVDS_DLL
6
-
AV20 AR22
AV23 AW21
AU23 AV21
AT23 AW22
AR23 AV22
AV24 AW23
AW24 AU24
AW25 AT24
AV25 AU25
AW26 AT25
AV26 AW27
AU26 AV27
AT26 AW28
AU27 AV28
AW29 AT27
AW30 AU28
AV30 AV29
AW31 AU29
8
VREF
INIT
VREF
-
-
AV4
5
5
-
5
5
-
AW4
AW5
AV6
VREF
-
-
VREF
VREF
-
AW6
AV7
3
3
-
3
3
-
-
-
AW7
AU9
AT10
AU10
AT11
-
VREF
VREF
-
5
5
-
5
5
-
VREF
-
-
-
AV10 AU11
AW10 AU12
VREF
VREF
2
2
-
2
2
-
AV11
AW11 AU13
AT14 AV12
AU14 AW12
AT15 AV13
AU15 AW13
AV14 AT16
AT13
-
-
VREF
VREF
-
AV31
AT29
-
5
5
-
AW32 AU30
AW33 AT30
AV33 AU31
AT31 AW34
AV32 AV34
AU32 AW35
5
5
VREF
-
-
-
VREF
VREF
-
AW14 AU16
AV15 AR17
AW15 AT17
AU17 AV16
AR18 AW16
3
3
-
3
3
-
-
-
-
AT32
AU33 AW36
AT33 AV36
AV35
VREF
VREF
-
5
5
-
5
5
VREF
AT18
AU18 AW17
AT19 AV18
AU19 AW18
AV17
-
AU34 AU36
AT38 AR36
AP36 AR38
AP37 AT39
-
-
VREF
-
-
-
6
4
2
VREF
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Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 23: FG680 Differential Pin Pair Summary
Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E
XCV600E, XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
4
Functions
Pair Bank
Pin
Pin
AO
Functions
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
AP39 AP38
AN38 AN36
AN39 AN37
AM38 AM36
AL36 AM37
AL37 AM39
AK36 AL38
AK37 AL39
AJ36 AK38
AJ37 AK39
AH37 AJ38
AH38 AJ39
AG38 AH39
AG39 AG36
AF39 AG37
AE38 AF36
AF38 AF37
AE36 AE39
AE37 AD38
AD36 AD39
AC39 AC38
AB38 AD37
AB39 AC35
AA38 AC36
AA39 AC37
-
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
Notes:
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
R39
U36
U35
T37
T36
N38
M39
M38
L39
N37
N36
M37
L37
L36
K37
K36
J37
V35
U37
R38
P39
P38
N39
R37
R36
P37
P36
L38
K39
K38
J39
-
6
VREF
VREF
-
6
4
-
4
6
-
-
-
-
VREF
6
4
4
6
VREF
-
-
7
4
VREF
-
-
-
VREF
-
-
VREF
4
-
4
4
-
VREF
-
-
VREF
6
4
4
6
-
J38
-
-
H39
H38
G39
J36
VREF
-
-
VREF
G38
F39
F38
E39
E38
D39
F36
E37
VREF
-
6
4
-
4
6
-
H37
H36
G37
G36
D38
D37
-
-
-
VREF
6
4
4
6
VREF
-
-
VREF
-
7
4
-
-
Y38
Y39
AB35
AB36
VREF
1. AO in the XCV1000E, 1600E, 2000E.
2. AO in the XCV600E, 1000E, 1600E.
3. AO in the XCV600E, 1000E.
4. AO in the XCV1000E, 1600E.
5. AO in the XCV1000E, 2000E.
6. AO in the XCV600E, 1000E, 2000E.
7. AO in the XCV1000E.
-
AA36 AB37
4
4
VREF
W38
V39
U39
U38
T39
T38
AA37
W37
W36
V38
-
VREF
8. AO in the XCV2000E.
-
VREF
V37
4
7
-
-
V36
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
FG860 Fine-Pitch Ball Grid Array Package
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L8P_YY
Pin #
C32
C36
B32
A32
D35
C312
C35
E34
A31
D34
C30
B30
E33
A30
D33
C33
B29
E32
A29
D32
C28
E31
B28
D31
A28
D30
C27
E29
B27
D29
A27
C26
D28
B26
F27
E27
C25
XCV1000E, XCV1600E, and XCV2000E devices in the
FG680 fine-pitch Ball Grid Array package have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as VREF, it can be used as gen-
eral I/O. Immediately following Table 24, see Table 25 for
Differential Pair information.
IO_VREF_L9N_YY
IO_L9P_YY
IO_L10N_Y
IO_L10P_Y
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
IO_VREF_L11N_Y
IO_L11P_Y
Bank
0
Pin Description
GCK3
Pin #
C22
A26
B31
B34
C24
C29
C34
D24
D36
D40
E26
E28
E35
A38
D38
B37
E37
A37
C39
B36
C38
A36
B35
A35
D37
C37
A34
E36
B33
A33
IO_L12N_YY
IO_L12P_YY
IO_VREF_L13N_YY
IO_L13P_YY
IO_L14N_Y
0
IO
0
IO
0
IO
0
IO
0
IO
IO_L14P_Y
0
IO
IO_L15N_Y
0
IO
IO_L15P_Y
0
IO
IO_VREF_L16N_YY
IO_L16P_YY
IO_L17N_YY
IO_L17P_YY
IO_L18N_Y
0
IO
0
IO
0
IO
0
IO
0
IO_L0N_Y
IO_L0P_Y
IO_L1N_Y
IO_L1P_Y
IO_VREF_L2N_Y
IO_L2P_Y
IO_L3N_Y
IO_L3P_Y
IO_L4N_YY
IO_L4P_YY
IO_VREF_L5N_YY
IO_L5P_YY
IO_L6N_Y
IO_L6P_Y
IO_L7N_Y
IO_L7P_Y
IO_L8N_YY
IO_L18P_Y
0
IO_L19N_Y
0
IO_L19P_Y
0
IO_L20N_Y
0
IO_L20P_Y
0
IO_L21N_Y
0
IO_L21P_Y
0
IO_L22N_YY
IO_L22P_YY
IO_VREF_L23N_YY
IO_L23P_YY
IO_L24N_Y
0
0
0
0
0
IO_L24P_Y
0
IO_L25N_Y
0
IO_L25P_Y
0
IO_L26N_YY
IO_L26P_YY
0
Module 4 of 4
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
Pin Description
IO_VREF_L27N_YY
IO_L27P_YY
Pin #
D27
B25
A25
D26
A24
E25
D25
B24
E24
A23
C23
E23
B231
D23
A22
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L38P_YY
IO_L39N_Y
Pin #
E19
D18
A19
E18
C19
B19
E17
A18
D16
E16
B18
F16
A17
C17
E15
B17
D14
A16
E14
C16
D13
B16
D12
A15
E12
C15
C11
B15
D11
E11
C14
C10
B14
A13
E10
C13
C9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L28N_Y
IO_L39P_Y
IO_L28P_Y
IO_L40N_Y
IO_L29N_Y
IO_L40P_Y
IO_L29P_Y
IO_L41N_YY
IO_VREF_L41P_YY
IO_L42N_YY
IO_L42P_YY
IO_L43N_Y
IO_L30N_YY
IO_L30P_YY
IO_VREF_L31N_YY
IO_L31P_YY
IO_L32N_Y
IO_L43P_Y
IO_L32P_Y
IO_L44N_Y
IO_VREF_L33N_Y
IO_L33P_Y
IO_L44P_Y
IO_L45N_YY
IO_VREF_L45P_YY
IO_L46N_YY
IO_L46P_YY
IO_L47N_Y
IO_LVDS_DLL_L34N
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GCK2
B22
A14
A20
B11
B13
C8
IO
IO
IO_L47P_Y
IO
IO_L48N_Y
IO
IO_L48P_Y
IO
IO_L49N_Y
IO
C18
C21
D7
IO_L49P_Y
IO
IO
IO_L50N_Y
IO_L50P_Y
IO
D10
D15
D17
E20
D22
D21
B211
D20
A21
C20
D19
B20
IO_L51N_YY
IO_L51P_YY
IO_L52N_YY
IO_VREF_L52P_YY
IO_L53N_Y
IO
IO
IO
IO_LVDS_DLL_L34P
IO_L35N_Y
IO_VREF_L35P_Y
IO_L36N_Y
IO_L36P_Y
IO_L37N_YY
IO_VREF_L37P_YY
IO_L38N_YY
IO_L53P_Y
IO_L54N_Y
IO_L54P_Y
IO_L55N_YY
IO_VREF_L55P_YY
IO_L56N_YY
IO_L56P_YY
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
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Module 4 of 4
87
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
1
Pin Description
IO_L57N_Y
Pin #
D9
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO
Pin #
Y3
AA3
F5
D2
E4
E2
D3
F2
E1
F4
G2
E3
F1
G5
G1
F3
G4
H1
J2
1
IO_VREF_L57P_Y
IO_L58N_Y
A122
E9
IO
1
IO_DOUT_BUSY_L70P_YY
IO_DIN_D0_L70N_YY
IO_L71P_Y
1
IO_L58P_Y
C12
B12
D8
1
IO_L59N_YY
IO_VREF_L59P_YY
IO_L60N_YY
IO_L60P_YY
IO_L61N_Y
1
IO_L71N_Y
1
A11
E8
IO_L72P_Y
1
IO_L72N_Y
1
C7
IO_VREF_L73P_Y
IO_L73N_Y
1
IO_L61P_Y
A10
C6
1
IO_L62N_Y
IO_L74P
1
IO_L62P_Y
B10
A9
IO_L74N
1
IO_L63N_YY
IO_VREF_L63P_YY
IO_L64N_YY
IO_L64P_YY
IO_L65N_Y
IO_L75P_Y
1
B9
IO_L75N_Y
1
A8
IO_VREF_L76P_Y
IO_L76N_Y
1
E7
1
B8
IO_L77P_YY
IO_L77N_YY
IO_L78P_Y
1
IO_L65P_Y
C5
1
IO_L66N_Y
A7
1
IO_VREF_L66P_Y
IO_L67N_Y
A6
IO_L78N_Y
G3
H5
K2
H4
K1
L2
1
B7
IO_L79P_Y
1
IO_L67P_Y
D6
IO_L79N_Y
1
IO_L68N_Y
A5
IO_VREF_L80P_YY
IO_L80N_YY
IO_L81P_YY
IO_L81N_YY
IO_VREF_L82P_Y
IO_L82N_Y
1
IO_L68P_Y
C4
1
IO_WRITE_L69N_YY
IO_CS_L69P_YY
B6
1
E6
L3
L12
J5
2
2
2
2
2
2
2
2
2
2
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
H2
H3
J1
IO_L83P_Y
J4
IO_L83N_Y
M3
J3
K5
M2
N1
R5
U1
U4
W3
IO_VREF_L84P_YY
IO_L84N_YY
IO_L85P_YY
IO_L85N_YY
IO_L86P_Y
M1
N2
K4
N3
K3
L5
IO_L86N_Y
IO_VREF_L87P_YY
Module 4 of 4
88
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_D1_L87N_YY
IO_D2_L88P_YY
IO_L88N_YY
IO_L89P_Y
Pin #
P2
Bank
Pin Description
Pin #
P3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
IO
AB4
AC2
AD1
AE3
AF4
AH5
AJ2
L4
P1
IO
IO_L89N_Y
R2
M5
R3
M4
R1
N4
T2
IO
IO_L90P_Y
IO
IO_L90N_Y
IO
IO_L91P_Y
IO
IO_L91N_Y
IO
AL1
AM3
AP3
AR5
AU4
AB2
AB3
AC41
AB1
AC5
AD4
AC3
AC1
AD5
AE4
AD3
AE5
AD2
AE1
AF5
AE2
AG4
AG5
AF1
AH4
AF2
AF3
AJ4
IO_L92P
IO
IO_L92N
IO
IO_L93P_Y
P5
IO
IO_L93N_Y
T3
IO
IO_VREF_L94P_Y
IO_L94N_Y
P4
IO
T1
IO_L106P_Y
IO_VREF_L106N_Y
IO_L107P_YY
IO_L107N_YY
IO_L108P_YY
IO_VREF_L108N_YY
IO_L109P_Y
IO_L109N_Y
IO_L110P_Y
IO_L110N_Y
IO_L111P_YY
IO_L111N_YY
IO_D4_L112P_YY
IO_VREF_L112N_YY
IO_L113P_Y
IO_L113N_Y
IO_L114P_Y
IO_L114N_Y
IO_L115P_YY
IO_L115N_YY
IO_L116P_Y
IO_VREF_L116N_Y
IO_L117P_Y
IO_L95P_YY
IO_L95N_YY
IO_L96P_Y
U2
R4
U3
T5
IO_L96N_Y
IO_L97P_Y
T4
IO_L97N_Y
V2
IO_VREF_L98P_YY
IO_D3_L98N_YY
IO_L99P_YY
IO_L99N_YY
IO_L100P_Y
IO_L100N_Y
IO_L101P_Y
IO_L101N_Y
IO_VREF_L102P_YY
IO_L102N_YY
IO_L103P_YY
IO_L103N_YY
IO_VREF_L104P_Y
IO_L104N_Y
IO_L105P_YY
IO_L105N_YY
U5
V3
V1
V5
W2
V4
W5
W1
Y2
W4
Y1
Y5
AA11
Y4
AA4
AA2
AG1
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
89
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L117N_Y
Pin #
AJ5
Bank
Pin Description
IO_L136P
Pin #
AR2
AT1
3
3
3
3
3
3
3
3
3
3
IO_L118P
AG2
AK4
AG3
AL4
AH1
AL5
AH2
AM4
AH3
AM5
AJ1
IO_L136N
IO_L118N
IO_L137P_Y
AV4
AT2
IO_L119P_Y
IO_VREF_L137N_Y
IO_L138P_Y
IO_L119N_Y
AU1
AU5
AU2
AW3
AV1
AW5
IO_L120P_Y
IO_L138N_Y
IO_L120N_Y
IO_L139P_Y
IO_L121P_Y
IO_L139N_Y
IO_L121N_Y
IO_D7_L140P_YY
IO_INIT_L140N_YY
IO_L122P_YY
IO_D5_L122N_YY
IO_D6_L123P_YY
IO_VREF_L123N_YY
IO_L124P_Y
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
GCK0
BA22
AV17
AY11
AY12
AY13
AY14
BA8
AN3
AN4
AJ3
IO
IO
IO_L124N_Y
IO
IO
IO_L125P_YY
IO_L125N_YY
IO_L126P_YY
IO_VREF_L126N_YY
IO_L127P_Y
AN5
AK1
AK2
AP4
AK3
AP5
AR3
AL22
AR4
AL3
AM1
AT3
IO
IO
IO
BA17
BA19
BA20
BA21
BB9
IO
IO_L127N_Y
IO
IO_L128P_Y
IO
IO_VREF_L128N_Y
IO_L129P_YY
IO_L129N_YY
IO_L130P_YY
IO_VREF_L130N_YY
IO_L131P_Y
IO
IO
BB18
AV6
IO_L141P_YY
IO_L141N_YY
IO_L142P_Y
IO_L142N_Y
IO_L143P_Y
IO_L143N_Y
IO_VREF_L144P_Y
IO_L144N_Y
IO_L145P_Y
IO_L145N_Y
IO_L146P_YY
IO_L146N_YY
IO_VREF_L147P_YY
BA4
AY4
AM2
AT4
BA5
IO_L131N_Y
AW6
BB5
IO_L132P_Y
AT5
IO_L132N_Y
AN1
AU3
AN2
AP1
AP2
AR1
AV3
BA6
IO_L133P_YY
IO_L133N_YY
IO_L134P_Y
AY5
BB6
AY6
IO_VREF_L134N_Y
IO_L135P_Y
BA7
AV7
IO_L135N_Y
BB7
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L147N_YY
IO_L148P_Y
Pin #
AW7
Bank
4
Pin Description
IO_L166P_Y
Pin #
AY17
AW15
BB17
AU16
AV16
AY18
AW16
BA18
BB19
AW17
AY19
AV18
AW18
BB20
AY20
AV19
BB21
AW19
AY211
AV20
AW20
AY7
4
IO_L166N_Y
IO_L148N_Y
BB8
4
IO_L167P_Y
IO_L149P_Y
BA9
4
IO_L167N_Y
IO_L149N_Y
AV8
4
IO_L168P_YY
IO_L168N_YY
IO_VREF_L169P_YY
IO_L169N_YY
IO_L170P_Y
IO_L150P_YY
IO_L150N_YY
IO_VREF_L151P_YY
IO_L151N_YY
IO_L152P_Y
AW8
4
BA10
BB10
AY8
4
4
4
AV9
4
IO_L170N_Y
IO_L152N_Y
BA11
BB112
AW9
4
IO_L171P_Y
IO_VREF_L153P_Y
IO_L153N_Y
4
IO_L171N_Y
4
IO_L172P_YY
IO_L172N_YY
IO_VREF_L173P_YY
IO_L173N_YY
IO_L174P_Y
IO_L154P_YY
IO_L154N_YY
IO_VREF_L155P_YY
IO_L155N_YY
IO_L156P_Y
AY9
4
BA12
BB12
AV10
BA13
AW10
BB13
AY10
AV11
BA14
AW11
BB14
AV12
BA15
AW12
AY15
AW13
BB15
AV14
BA16
AW14
AY16
BB16
AV15
4
4
4
4
IO_L174N_Y
IO_L156N_Y
4
IO_VREF_L175P_Y
IO_L175N_Y
IO_L157P_Y
4
IO_L157N_Y
4
IO_LVDS_DLL_L176P
IO_VREF_L158P_YY
IO_L158N_YY
IO_L159P_YY
IO_L159N_YY
IO_L160P_Y
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
AY22
AV24
AV34
AW27
AW36
AY23
AY31
AY33
BA26
BA29
BA33
BB25
AW21
BB22
AW221
IO
IO
IO
IO_L160N_Y
IO
IO_L161P_Y
IO
IO_L161N_Y
IO
IO_L162P_Y
IO
IO_L162N_Y
IO
IO_L163P_Y
IO
IO
IO_L163N_Y
IO_L164P_YY
IO_L164N_YY
IO_VREF_L165P_YY
IO_L165N_YY
IO
IO_LVDS_DLL_L176N
IO_L177P_Y
IO_VREF_L177N_Y
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
91
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L178P_Y
Pin #
BB23
AW23
AV23
BA23
AW24
BB24
AY24
AW25
BA24
AV25
AW26
AY25
AV26
BA25
BB26
AV27
AY26
AU27
AW28
BB27
AY27
AV28
BA27
AW29
BB28
AV29
AY28
AW30
BA28
AW31
BB29
AV31
AY29
AY32
AW32
BB30
AV32
Bank
5
Pin Description
IO_L196N_Y
Pin #
AY30
BA30
AW33
BB31
AV33
AY34
BA312
AW34
BB32
BA32
AY35
BB33
AW35
AV35
BB34
AY36
BA34
BB35
AV36
BA35
AY37
BB36
BA36
AW37
BB37
BA37
AY38
BB38
AY39
IO_L178N_Y
5
IO_L197P_YY
IO_VREF_L197N_YY
IO_L198P_YY
IO_L198N_YY
IO_L199P_Y
IO_L179P_YY
IO_VREF_L179N_YY
IO_L180P_YY
IO_L180N_YY
IO_L181P_Y
5
5
5
5
5
IO_VREF_L199N_Y
IO_L200P_Y
IO_L181N_Y
5
IO_L182P_Y
5
IO_L200N_Y
IO_L182N_Y
5
IO_L201P_YY
IO_VREF_L201N_YY
IO_L202P_YY
IO_L202N_YY
IO_L203P_Y
IO_L183P_YY
IO_VREF_L183N_YY
IO_L184P_YY
IO_L184N_YY
IO_L185P_Y
5
5
5
5
5
IO_L203N_Y
IO_L185N_Y
5
IO_L204P_Y
IO_L186P_Y
5
IO_L204N_Y
IO_L186N_Y
5
IO_L205P_YY
IO_VREF_L205N_YY
IO_L206P_YY
IO_L206N_YY
IO_L207P_Y
IO_L187P_YY
IO_VREF_L187N_YY
IO_L188P_YY
IO_L188N_YY
IO_L189P_Y
5
5
5
5
5
IO_L207N_Y
IO_L189N_Y
5
IO_L208P_Y
IO_L190P_Y
5
IO_VREF_L208N_Y
IO_L209P_Y
IO_L190N_Y
5
IO_L191P_Y
5
IO_L209N_Y
IO_L191N_Y
5
IO_L210P_Y
IO_L192P_Y
5
IO_L210N_Y
IO_L192N_Y
IO_L193P_YY
IO_L193N_YY
IO_L194P_YY
IO_VREF_L194N_YY
IO_L195P_Y
6
6
6
6
6
6
6
IO
IO
IO
IO
IO
IO
IO
AA40
AB41
AC42
AD39
AE40
AF38
AF40
IO_L195N_Y
IO_L196P_Y
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO
Pin #
AJ40
AL41
AN38
AN42
AP41
AR39
AV41
AV42
AW40
AU41
AV39
AU42
AT41
AU38
AT42
AV40
AR41
AU39
AR42
AU40
AT38
AP42
AN41
AT39
AT40
AM40
AR38
AM41
AM42
AR40
AL402
AP38
AP39
AL42
AP40
AK40
AK41
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L226P_YY
IO_L227N_Y
Pin #
AN39
AK42
AN40
AM38
AJ41
AJ42
AM39
AH40
AH41
AL38
AH42
AL39
AG41
AK39
AG40
AJ38
AG42
AF42
AJ39
AF41
AH38
AE42
AH39
AG38
AE41
AG39
AD42
AD40
AF39
AD41
AE38
AE39
AC40
AD38
AC41
AB42
AC38
IO
IO
IO_L227P_Y
IO
IO_VREF_L228N_YY
IO_L228P_YY
IO_L229N_YY
IO_L229P_YY
IO_L230N_Y
IO
IO
IO_L211N_YY
IO_L211P_YY
IO_L212N_Y
IO_L212P_Y
IO_L213N_Y
IO_L213P_Y
IO_VREF_L214N_Y
IO_L214P_Y
IO_L215N
IO_L230P_Y
IO_L231N_Y
IO_L231P_Y
IO_L232N_Y
IO_L232P_Y
IO_L233N
IO_L233P
IO_L215P
IO_L234N_Y
IO_L216N_Y
IO_L216P_Y
IO_VREF_L217N_Y
IO_L217P_Y
IO_L218N_YY
IO_L218P_YY
IO_L219N_Y
IO_L219P_Y
IO_L220N_Y
IO_L220P_Y
IO_VREF_L221N_YY
IO_L221P_YY
IO_L222N_YY
IO_L222P_YY
IO_VREF_L223N_Y
IO_L223P_Y
IO_L224N_Y
IO_L224P_Y
IO_VREF_L225N_YY
IO_L225P_YY
IO_L226N_YY
IO_L234P_Y
IO_VREF_L235N_Y
IO_L235P_Y
IO_L236N_YY
IO_L236P_YY
IO_L237N_Y
IO_L237P_Y
IO_L238N_Y
IO_L238P_Y
IO_VREF_L239N_YY
IO_L239P_YY
IO_L240N_YY
IO_L240P_YY
IO_L241N_Y
IO_L241P_Y
IO_L242N_Y
IO_L242P_Y
IO_VREF_L243N_YY
IO_L243P_YY
IO_L244N_YY
IO_L244P_YY
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
Pin Description
IO_VREF_L245N_Y
IO_L245P_Y
Pin #
AB401
AC39
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L256P_YY
IO_L257N_Y
Pin #
T38
R39
T42
R42
R38
R40
P39
R41
P38
P42
N39
P40
M39
P41
M38
N42
L39
L38
N41
K40
M42
M40
K38
M41
J40
6
6
IO_VREF_L257P_Y
IO_L258N_Y
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO
IO
F38
H40
H41
J42
IO_L258P_Y
IO
IO_L259N
IO
IO_L259P
IO
K39
L42
IO_L260N_Y
IO
IO_L260P_Y
IO
N40
T40
IO_L261N_Y
IO
IO_L261P_Y
IO
U40
V38
W42
Y42
AA42
AA41
AB39
Y41
AA391
Y40
Y39
Y38
W41
W40
W39
W38
V41
V39
V40
V42
U39
U41
U38
U42
T39
IO_L262N_Y
IO
IO_L262P_Y
IO
IO_L263N_YY
IO_L263P_YY
IO_L264N_YY
IO_VREF_L264P_YY
IO_L265N_Y
IO
IO
IO_L246N_YY
IO_L246P_YY
IO_L247N_Y
IO_VREF_L247P_Y
IO_L248N_YY
IO_L248P_YY
IO_L249N_YY
IO_VREF_L249P_YY
IO_L250N_Y
IO_L250P_Y
IO_L251N_Y
IO_L251P_Y
IO_L252N_YY
IO_L252P_YY
IO_L253N_YY
IO_VREF_L253P_YY
IO_L254N_Y
IO_L254P_Y
IO_L255N_Y
IO_L255P_Y
IO_L256N_YY
IO_L265P_Y
IO_L266N_YY
IO_L266P_YY
IO_L267N_YY
IO_VREF_L267P_YY
IO_L268N_Y
IO_L268P_Y
IO_L269N_Y
J39
IO_VREF_L269P_Y
IO_L270N_YY
IO_L270P_YY
IO_L271N_YY
IO_VREF_L271P_YY
IO_L272N_Y
L40
J38
L41
K42
H39
K41
H38
J41
IO_L272P_Y
IO_L273N_Y
IO_L273P_Y
G40
H42
G39
IO_L274N_YY
IO_L274P_YY
T41
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
Pin Description
IO_L275N_Y
IO_VREF_L275P_Y
IO_L276N_Y
IO_L276P_Y
IO_L277N
Pin #
G38
G42
G41
F40
F42
F41
F39
E42
E40
E41
E39
D41
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin #
K37
7
7
7
7
7
7
7
7
7
7
7
7
T6
T37
U6
U37
IO_L277P
V6
IO_L278N_Y
IO_VREF_L278P_Y
IO_L279N_Y
IO_L279P_Y
IO_L280N_Y
IO_L280P_Y
V37
AE6
AE37
AF6
AF37
AG6
AG37
AN6
AN37
AP6
2
CCLK
DONE
DXN
B4
AW2
BA38
AW38
AW41
AV37
BA39
AV2
3
NA
NA
NA
NA
NA
NA
NA
NA
2
DXP
AP37
AU9
M0
M1
AU10
AU17
AU18
AU25
AU26
AU33
AU34
M2
PROGRAM
TCK
B38
TDI
B5
TDO
D5
NA
TMS
B39
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
F9
F10
F17
F18
F25
F26
F33
F34
J6
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
F23
F24
F28
F29
F31
F32
F35
F36
F11
F12
F14
J37
K6
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
Pin #
F15
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
Pin #
AC37
AD37
AH37
AJ37
AL37
AM37
AR37
AT37
G37
F19
F20
F7
F8
G6
H6
L6
M6
P6
H37
R6
L37
W6
M37
Y6
P37
AC6
AD6
AH6
AJ6
R37
W37
Y37
AL6
AM6
AR6
AT6
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N6
N5
N38
N37
F6
AU11
AU12
AU14
AU15
AU19
AU20
AU7
AU8
AU23
AU24
AU28
AU29
AU31
AU32
AU35
AU36
F37
F30
F22
F21
F13
E5
E38
E30
E22
E21
E13
D42
D4
D39
D1
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
C42
C41
C40
C3
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
AV22
AV21
AV13
AU6
C2
AU37
AU30
AU22
AU21
AU13
AK6
C1
BB41
BB40
BB4
BB39
BB3
BB2
BA42
BA41
BA40
BA3
BA2
BA1
B42
AK5
AK38
AK37
AB6
AB5
AB38
AB37
AA6
AA5
B41
AA38
AA37
A41
B40
B3
B2
A40
B1
A4
AY42
AY41
AY40
AY3
A39
A3
A2
Notes:
1. VREF or I/O option only in the XCV1600E, 2000E; otherwise,
I/O option only.
AY2
2.
V
REF or I/O option only in the XCV2000E; otherwise, I/O
AY1
option only.
AW42
AW4
AW39
AW1
AV5
AV38
AV30
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
FG860 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
P
N
Other
Pair Bank
Pin
Pin
AO
2
Functions
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C28
B28
A28
C27
B27
A27
D28
F27
C25
B25
D26
E25
B24
A23
E23
D23
D22
B21
A21
D19
E19
A19
C19
E17
D16
B18
A17
E15
D14
E14
D13
D12
E12
C11
D32
E31
D31
D30
E29
D29
C26
B26
E27
D27
A25
A24
D25
E24
C23
B23
A22
D21
D20
C20
B20
D18
E18
B19
A18
E16
F16
C17
B17
A16
C16
B16
A15
C15
-
1
-
1
-
5
-
-
VREF
5
5
-
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
-
P
N
Other
-
Pair Bank
Pin
Pin
AO
Functions
VREF
Global Differential Clock
1
1
-
3
2
1
0
0
1
5
4
C22
B22
A22
D22
NA
NA
IO_DLL_L34N
IO_DLL_L34P
IO_DLL_L176N
IO_DLL_L176P
-
-
AY22 AW21 NA
BA22 AW20 NA
IO LVDS
VREF
2
2
-
VREF
Total Pairs: 281, Asynchronous Output Pairs: 111
NA
2
IO_LVDS_DLL
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D38
E37
C39
C38
B35
D37
A34
B33
C32
B32
D35
C35
A31
C30
E33
D33
B29
A29
A38
B37
A37
B36
A36
A35
C37
E36
A33
C36
A32
C31
E34
D34
B30
A30
C33
E32
2
1
1
1
-
VREF
-
2
-
2
VREF
VREF
3
-
-
4
-
1
1
-
5
VREF
-
6
5
5
-
VREF
7
-
-
8
-
5
5
-
9
VREF
-
10
11
12
13
14
15
16
17
1
1
-
VREF
VREF
-
-
-
-
-
-
-
5
1
1
2
VREF
2
2
-
-
VREF
-
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 25: FG860 Differential Pin Pair Summary
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
Functions
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
D11
C14
B14
E10
C9
A12
C12
D8
E8
B15
E11
C10
A13
C13
D9
E9
VREF
86
87
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
N3
L5
K3
P2
2
-
2
2
-
D1
-
88
P3
L4
D2
VREF
89
P1
R2
3
1
2
4
2
1
-
-
90
M5
R3
-
1
1
VREF
91
M4
R1
-
-
92
N4
T2
-
B12
A11
C7
C6
A9
VREF
93
P5
T3
-
-
94
P4
T1
VREF
A10
B10
B9
5
5
-
95
U2
R4
-
-
96
U3
T5
2
1
-
VREF
97
T4
V2
-
E7
A8
-
98
U5
V3
D3
C5
A6
B8
5
1
1
2
-
99
V1
V5
-
A7
VREF
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
W2
W5
Y2
V4
5
2
-
D6
C4
E6
B7
-
W1
W4
Y5
-
A5
-
VREF
B6
CS
Y1
-
F5
D2
E2
DIN, D0
AA1
AA4
AB3
AB1
AD4
AC1
AE4
AE5
AE1
AE2
AG5
AH4
AF3
AG1
AG2
AG3
Y4
2
2
VREF
E4
3
1
2
4
2
1
-
AA2
AC4
AC5
AC3
AD5
AD3
AD2
AF5
AG4
AF1
AF2
AJ4
AJ5
AK4
AL4
-
D3
E1
F2
-
VREF
F4
VREF
-
G2
F1
E3
-
VREF
G5
F3
-
2
5
-
G1
G4
J2
VREF
-
H1
G3
K2
-
-
2
1
-
VREF
H5
H4
L2
-
1
2
-
K1
VREF
-
L3
-
-
L1
J5
5
2
VREF
1
2
4
2
VREF
J4
M3
M1
K4
-
VREF
-
-
-
-
J3
N2
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 25: FG860 Differential Pin Pair Summary
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
1
Functions
Pair Bank
Pin
Pin
AO
Functions
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
AH1
AH2
AH3
AJ1
AL5
AM4
AM5
AN3
AJ3
-
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
AY9
BA12
AV10
-
3
-
BB12
VREF
D5
BA13 AW10
2
2
-
VREF
BB13
AV11
AY10
BA14
-
AN4
AN5
AK2
AK3
AR3
AR4
AM1
AM2
AT5
2
-
VREF
AK1
AP4
AP5
AL2
AL3
AT3
-
AW11 BB14
AV12 BA15
-
VREF
2
1
1
5
-
2
5
-
AW12 AY15
AW13 BB15
-
VREF
-
-
AV14
AW14 AY16
BB16 AV15
BA16
-
VREF
-
AT4
1
2
-
VREF
AN1
AN2
AP2
AV3
AT1
-
AY17 AW15
BB17 AU16
5
5
-
AU3
AP1
AR1
AR2
AV4
AU1
AU2
AV1
AV6
AY4
AW6
BA6
BB6
BA7
BB7
AY7
BA9
AW8
BB10
AV9
BB11
-
-
1
2
4
2
1
3
VREF
AV16
AY18
-
-
AW16 BA18
BB19 AW17
VREF
-
1
1
-
AT2
VREF
AY19
AW18 BB20
AY20 AV19
BB21 AW19
AY21 AV20
AV18
-
AU5
AW3
AW5
BA4
BA5
BB5
AY5
AY6
AV7
AW7
BB8
AV8
BA10
AY8
BA11
AW9
-
-
-
VREF
INIT
2
2
-
-
VREF
2
1
1
5
-
AW20 AW21 NA
IO_LVDS_DLL
-
BB22 AW22
BB23 AW23
2
2
VREF
VREF
-
-
AV23
BA23
VREF
-
AW24 BB24
AY24 AW25
-
VREF
1
1
-
5
5
-
BA24
AV25
-
-
AW26 AY25
VREF
-
AV26
BB26
AY26
BA25
AV27
AU27
-
VREF
-
5
5
-
-
1
1
VREF
AW28 BB27
VREF
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Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 25: FG860 Differential Pin Pair Summary
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
XCV1000E, XCV1600E, XCV2000E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
Functions
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
AY27
AV28
-
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
AR40 AM42
-
BA27 AW29
BB28 AV29
5
1
1
2
-
AP38
AL42
AL40
AP39
5
2
VREF
-
-
AY28 AW30
BA28 AW31
-
AK40 AP40
AN39 AK41
AN40 AK42
AJ41 AM38
AM39 AJ42
AH41 AH40
VREF
-
-
BB29
AY29
AV31
AY32
-
2
-
VREF
VREF
AW32 BB30
AV32 AY30
BA30 AW33
2
2
-
-
-
3
1
2
4
2
1
-
VREF
AH42
AL38
-
BB31
AY34
AV33
BA31
-
AG41 AL39
AG40 AK39
-
1
1
VREF
-
AW34 BB32
BA32 AY35
BB33 AW35
-
AG42
AJ39
AJ38
AF42
-
VREF
VREF
-
AH38 AF41
AH39 AE42
AE41 AG38
AD42 AG39
AF39 AD40
AE38 AD41
AC40 AE39
AC41 AD38
AC38 AB42
AC39 AB40
AB39 AA41
-
AV35
AY36
BB35
BA35
BB34
BA34
AV36
AY37
5
5
-
2
1
-
-
-
VREF
VREF
-
-
BB36 BA36
AW37 BB37
5
1
1
2
-
5
2
-
VREF
-
BA37
BB38
AV42
AY38
AY39
AV41
-
VREF
-
-
-
2
2
VREF
AU41 AW40
3
1
2
4
2
1
-
-
AU42
AU38
AV40
AV39
AT41
AT42
-
AA39
Y39
W41
W39
V41
V40
U39
U38
T39
Y41
Y40
Y38
W40
W38
V39
V42
U41
U42
VREF
VREF
-
-
VREF
AU39 AR41
AU40 AR42
-
2
5
-
VREF
-
AP42
AT39
AT38
-
-
AN41
2
1
-
-
VREF
AM40 AT40
AM41 AR38
1
2
-
-
VREF
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E
FG900 Fine-Pitch Ball Grid Array Package
XCV600E, XCV1000E, and XCV1600E devices in the
FG900 fine-pitch Ball Grid Array package have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as VREF, it can be used as gen-
eral I/O. Immediately following Table 26, see Table 27 for
Differential Pair information.
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
Notes:
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
T38
T42
R38
P39
P38
N39
M39
M38
L39
N41
M42
K38
J40
T41
R39
R42
R40
R41
P42
P40
P41
N42
L38
K40
M40
M41
J39
-
1
2
4
2
1
3
VREF
-
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
-
Bank
0
Pin Description
Pin #
C15
A74
A134
C54
C64
C144
D85
D10
D134
E6
-
GCK3
-
0
IO
-
0
IO
-
0
IO
VREF
0
IO
2
-
0
IO
-
0
IO
VREF
0
IO
2
5
-
0
IO
IO
L40
L41
H39
H38
G40
G39
G42
F40
F41
E42
E41
D41
VREF
0
J38
-
0
IO
E95
E145
F94
F145
G15
K115
K12
L134
C44
F73
D5
K42
K41
J41
VREF
0
IO
1
2
-
0
IO
-
0
IO
H42
G38
G41
F42
F39
E40
E39
-
0
IO
1
2
4
2
1
3
VREF
0
IO
-
0
IO
-
0
IO
VREF
0
IO_L0N_YY
IO_L0P_YY
IO_L1N_Y
IO_L1P_Y
IO_VREF_L2N_Y
IO_L2P_Y
IO_L3N_Y
IO_L3P_Y
IO_L4N_YY
IO_L4P_YY
IO_VREF_L5N_YY
IO_L5P_YY
-
-
0
0
0
G8
1. AO in the XCV1000E, 2000E.
2. AO in the XCV1000E, 1600E.
3. AO in the XCV2000E.
4. AO in the XCV1600E.
5. AO in the XCV1000E.
0
A31
H9
0
0
B44
J104
A4
0
0
0
D6
0
E7
0
B5
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L6N_Y
Pin #
A5
Bank
0
Pin Description
IO_L24P_Y
Pin #
A11
G13
B12
A12
K13
F13
IO_L6P_Y
F8
0
IO_L25N_Y
IO_L7N_Y
D7
0
IO_L25P_Y
IO_L7P_Y
N11
G9
0
IO_L26N_YY
IO_L26P_YY
IO_VREF_L27N_YY
IO_L27P_YY
IO_L28N_Y
IO_L8N_YY
IO_L8P_YY
IO_VREF_L9N_YY
IO_L9P_YY
IO_L10N_Y
IO_L10P_Y
IO_L11N_Y
IO_L11P_Y
IO_L12N_YY
IO_L12P_YY
IO_VREF_L13N_YY
IO_L13P_YY
IO_L14N
0
E8
0
A6
0
B13
G14
E13
D14
B14
A14
J14
J11
C7
0
0
IO_L28P_Y
B7
0
IO_L29N_Y
C8
0
IO_L29P_Y
H10
G10
F10
A8
0
IO_L30N_YY
IO_L30P_YY
IO_VREF_L31N_YY
IO_L31P_YY
IO_L32N
0
0
K14
J15
0
H11
D94
C93
B9
0
B154
H153
F152,3
D154
A15
0
IO_L32P
IO_L14P
0
IO_VREF_L33N_YY
IO_L33P_YY
IO_LVDS_DLL_L34N
IO_L15N_YY
IO_L15P_YY
IO_L16N
0
J12
E104
A9
0
IO_VREF_L16P
IO_L17N
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GCK2
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
E15
A254
B174
B184
C234
D164
D175
D234
E194
E245
F224
G175
G204
J164
J174
J195
G11
B10
H124
C104
H13
F11
E11
D11
B114
G124
F12
C11
A101
D12
E12
IO_L17P
IO_L18N_YY
IO_L18P_YY
IO_L19N_Y
IO_L19P_Y
IO_L20N_Y
IO_L20P_Y
IO_L21N_Y
IO_L21P_Y
IO_L22N_YY
IO_L22P_YY
IO_VREF_L23N_YY
IO_L23P_YY
IO_L24N_Y
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO
Pin #
J205
L184
E16
B16
F162
A16
H16
C16
K15
K16
G16
A17
E17
F17
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L52N_YY
IO_VREF_L52P_YY
IO_L53N_YY
IO_L53P_YY
IO_L54N_YY
IO_L54P_YY
IO_L55N_YY
IO_VREF_L55P_YY
IO_L56N_YY
IO_L56P_YY
IO_L57N_Y
Pin #
C21
A22
H19
B22
E21
D22
F21
C22
H20
E22
G21
A23
A24
K19
C24
B24
H21
G22
E23
C25
D24
A26
B26
K20
D25
J21
IO
IO_LVDS_DLL_L34P
IO_L35N_YY
IO_VREF_L35P_YY
IO_L36N_YY
IO_L36P_YY
IO_L37N_YY
IO_VREF_L37P_YY
IO_L38N_YY
IO_L38P_YY
IO_L39N_Y
IO_L57P_Y
IO_L39P_Y
IO_L58N_Y
IO_L40N_Y
IO_L58P_Y
IO_L40P_Y
C17
E18
A18
D18
A19
B19
G18
D19
H18
F18
IO_L59N_YY
IO_VREF_L59P_YY
IO_L60N_YY
IO_L60P_YY
IO_L61N_Y
IO_L41N_YY
IO_VREF_L41P_YY
IO_L42N_YY
IO_L42P_YY
IO_L43N_Y
IO_L61P_Y
IO_L43P_Y
IO_L62N_Y
IO_L44N_Y
IO_L62P_Y
IO_L44P_Y
IO_L63N_YY
IO_VREF_L63P_YY
IO_L64N_YY
IO_L64P_YY
IO_L65N_Y
IO_L45N_YY
IO_VREF_L45P_YY
IO_L46N_YY
IO_L46P_YY
IO_L47N_Y
F191
B20
K17
D204
A204
G19
C20
K18
E20
B214
D214
F20
C264
F234
B27
G231
A27
F24
B283
A284
K21
C27
IO_L65P_Y
IO_L47P_Y
IO_L66N_Y
IO_L48N_Y
IO_VREF_L66P_Y
IO_L67N_Y
IO_L48P_Y
IO_L49N_Y
IO_L67P_Y
IO_L49P_Y
IO_L68N_YY
IO_L68P_YY
IO_WRITE_L69N_YY
IO_CS_L69P_YY
IO_L50N_YY
IO_L50P_YY
IO_L51N_YY
IO_L51P_YY
A21
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
Pin #
D295
G264
H244
H254
H285
J254
J275
K304
M244
M254
N20
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L80N_YY
IO_L81P_YY
IO_L81N_YY
IO_L82P
Pin #
L22
IO
IO
H27
G29
G30
M21
J24
IO
IO
IO
IO_L82N
IO
IO
IO_L83P_YY
IO_L83N_YY
IO_VREF_L84P_YY
IO_L84N_YY
IO_L85P_YY
IO_L85N_YY
IO_L86P_YY
IO_L86N_YY
IO_L87P_YY
IO_VREF_L87N_YY
IO_D1_L88P
IO_D2_L88N
IO_L89P_YY
IO_L89N_YY
IO_L90P
J26
IO
H30
L23
IO
IO
K264
J283
J29
IO
IO
N234
P265
P275
P304
R30
IO
K24
K274
J30
IO
IO
IO
M22
K29
K283
L254
N21
K25
L24
IO_DOUT_BUSY_L70P_YY
IO_DIN_D0_L70N_YY
IO_L71P
J22
E27
C294
D283
G25
E25
IO_L71N
IO_L72P_Y
IO_L72N_Y
IO_VREF_L73P_YY
IO_L73N_YY
IO_L74P_Y
IO_L74N_Y
IO_L75P_YY
IO_L75N_YY
IO_VREF_L76P_Y
IO_L76N_Y
IO_L77P_YY
IO_L77N_YY
IO_L78P_YY
IO_L78N_YY
IO_L79P
IO_L90N
IO_L91P_YY
IO_L91N_YY
IO_L92P_Y
E281
C30
L27
L294
M234
L26
K224
F273
D30
IO_L92N_Y
IO_L93P_YY
IO_L93N_YY
IO_VREF_L94P
IO_L94N
L28
J23
L301
M27
M26
M29
N29
M30
N25
N27
N30
P21
L21
F28
IO_L95P_YY
IO_L95N_YY
IO_L96P_YY
IO_L96N_YY
IO_L97P
G28
E30
G27
E29
K23
IO_L97N
IO_L79N
H26
IO_VREF_L98P_YY
IO_D3_L98N_YY
IO_VREF_L80P_YY
F30
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
Pin Description
IO_L99P_YY
Pin #
N26
P28
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L108N_YY
IO_L109P_YY
IO_VREF_L109N_YY
IO_L110P_YY
IO_L110N_YY
IO_L111P
Pin #
T28
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L99N_YY
T21
IO_L100P
P29
T25
IO_L100N
N24
P22
U28
U30
T23
IO_L101P_YY
IO_L101N_YY
IO_VREF_L102P_YY
IO_L102N_YY
IO_L103P_YY
IO_L103N_YY
IO_VREF_L104P_YY
IO_L104N_YY
IO_L105P_YY
IO_L105N_YY
IO_L106P
R26
P25
IO_L111N
U27
U25
V27
R29
R214
R283
R252
T30
IO_L112P_YY
IO_L112N_YY
IO_D4_L113P_YY
IO_VREF_L113N_YY
IO_L114P
U24
V29
W30
U22
U21
W29
V26
P244
R273
R24
IO_L114N
IO_L115P_YY
IO_L115N_YY
IO_L116P_YY
IO_L116N_YY
IO_L117P
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
T224
T244
W27
W26
Y291
W25
Y30
IO
IO
T264
IO_VREF_L117N
IO_L118P_YY
IO_L118N_YY
IO_L119P_Y
IO
T294
IO
U265
V234
V254
V305
Y214
AA264
AA234
AB274
AB294
AC285
AD264
AD295
AE275
U29
IO
V244
Y284
AA30
W24
AA29
V20
IO
IO_L119N_Y
IO
IO_L120P_YY
IO_L120N_YY
IO_L121P
IO
IO
IO
IO_L121N
IO
IO_L122P
Y274
W234
Y26
IO
IO_L122N
IO
IO_L123P_YY
IO_D5_L123N_YY
IO_D6_L124P_YY
IO_VREF_L124N_YY
IO_L125P_YY
IO_L125N_YY
IO_L126P_YY
IO_L126N_YY
IO
IO
AB30
V21
IO
AA28
Y25
IO_L106N
IO_L107P_YY
IO_VREF_L107N_YY
IO_L108P_YY
R22
AA27
W22
Y23
T272
R23
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Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
3
Pin Description
IO_L127P_YY
IO_VREF_L127N_YY
IO_L128P_YY
IO_L128N_YY
IO_L129P
Pin #
Y24
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO
Pin #
AE154
AE184
AE21
AE245
AF175
AF185
AJ184
AK18
AK255
AK274
AH234
AH245
AF27
AK28
AG264
AH273
AD23
AJ27
3
AB28
AC30
AA25
W21
IO
3
IO
3
IO
3
IO
3
IO_L129N
AA24
AB26
AD30
Y22
IO
3
IO_L130P_YY
IO_L130N_YY
IO_L131P_YY
IO_VREF_L131N_YY
IO_L132P
IO
3
IO
3
IO
3
AC27
AD28
AB25
AC26
AE30
AD27
AF30
AF29
AB24
AB23
AE28
AG303
AC254
AE26
AG291
AH30
AC24
AF283
AD254
AH29
AA22
IO
3
IO
3
IO_L132N
IO
3
IO_L133P_YY
IO_L133N_YY
IO_L134P_YY
IO_L134N_YY
IO_L135P
IO_L142P_YY
IO_L142N_YY
IO_L143P_YY
IO_L143N_YY
IO_L144P
IO_L144N
IO_VREF_L145P
IO_L145N
IO_L146P
IO_L146N
IO_L147P_YY
IO_L147N_YY
IO_VREF_L148P_YY
IO_L148N_YY
IO_L149P
IO_L149N
IO_L150P
IO_L150N
IO_L151P_YY
IO_L151N_YY
IO_VREF_L152P_YY
IO_L152N_YY
IO_L153P
IO_L153N
IO_L154P
3
3
3
3
3
IO_VREF_L135N
IO_L136P_YY
IO_L136N_YY
IO_L137P_Y
3
AB211
AF25
AC224
AH264
AA21
AG25
AJ26
3
3
3
IO_L137N_Y
3
IO_L138P_YY
IO_VREF_L138N_YY
IO_L139P
3
3
3
IO_L139N
AD22
AA20
AH25
AC21
AF24
AG24
AK26
AJ24
3
IO_L140P
3
IO_L140N
3
IO_D7_L141P_YY
IO_INIT_L141N_YY
3
4
4
4
4
4
4
GCK0
IO
AJ16
AB194
AC164
AC19
IO
AF23
AE23
AB20
AC20
IO
IO
AD184
AD214
IO
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L154N
Pin #
AG23
AF22
AE22
AJ22
Bank
Pin Description
IO_L173P_YY
Pin #
AE16
AE17
AG17
AJ17
4
4
4
4
4
4
4
4
4
IO_L155P_YY
IO_L155N_YY
IO_VREF_L156P_YY
IO_L156N_YY
IO_L157P
IO_L173N_YY
IO_VREF_L174P_YY
IO_L174N_YY
AG22
AK244
AD203
AA19
AF21
AH224
AA18
AG21
AK23
AH214
AD194
AE20
AJ21
IO_L175P
AD154
AH173
AG162
AK17
AF16
IO_L175N
IO_L157N
IO_VREF_L176P_YY
IO_L176N_YY
IO_L158P_YY
IO_L158N_YY
IO_L159P
IO_LVDS_DLL_L177P
IO_VREF_L159N
IO_L160P
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
AK16
AA114
AA144
AD144
AE75
IO
IO_L160N
IO
IO_L161P_YY
IO_L161N_YY
IO_L162P
IO
IO
IO
AE85
IO_L162N
IO
AE104
AF64
IO_L163P
AG20
AF20
AC184
AF194
AJ20
IO
IO_L163N
IO
AF104
AG94
IO_L164P
IO
IO_L164N
IO
IO
AG124
AG145
AH84
IO_L165P_YY
IO_L165N_YY
IO_VREF_L166P_YY
IO_L166N_YY
IO_L167P
AE19
AK221
AH20
AG19
AB17
AJ19
IO
IO
AK65
IO
AK145
AJ134
AJ154
AH16
AC154
AG152,3
AB15
AF15
IO
IO_L167N
IO
IO_L168P
IO_LVDS_DLL_L177N
IO_L178P_YY
IO_VREF_L178N_YY
IO_L179P_YY
IO_L179N_YY
IO_L180P_YY
IO_VREF_L180N_YY
IO_L181P_YY
IO_L181N_YY
IO_L182P
IO_L168N
AD17
AA16
AA17
AK21
AB16
AG18
AK20
AK19
AD16
IO_L169P_YY
IO_L169N_YY
IO_VREF_L170P_YY
IO_L170N_YY
IO_L171P
AA15
AF14
IO_L171N
AH15
AK15
AB14
IO_L172P
IO_L172N
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L182N
Pin #
AF13
AH14
AJ14
AE14
AG13
AK13
AD13
AE13
AF12
AC13
AA13
AA12
AJ121
AB12
AE11
AK124
Y134
AG11
AF11
AH11
AJ11
AE124
AG104
AD12
AK11
AJ10
AC12
AK10
AD11
AJ9
Bank
5
Pin Description
IO_L201P
Pin #
AC11
AG8
AK8
IO_L183P
5
IO_L201N
IO_L183N
5
IO_L202P_YY
IO_VREF_L202N_YY
IO_L203P_YY
IO_L203N_YY
IO_L204P
IO_L184P_YY
IO_VREF_L184N_YY
IO_L185P_YY
IO_L185N_YY
IO_L186P
5
AF7
5
AG7
AK7
5
5
AJ7
5
IO_L204N
AD10
AH6
AC10
AD9
AG6
AB10
AJ5
IO_L186N
5
IO_L205P
IO_L187P
5
IO_L205N
IO_L187N
5
IO_L206P_YY
IO_VREF_L206N_YY
IO_L207P_YY
IO_L207N_YY
IO_L208P
IO_L188P_YY
IO_VREF_L188N_YY
IO_L189P_YY
IO_L189N_YY
IO_L190P
5
5
5
5
AD84
AK54
AC9
5
IO_L208N
IO_L190N
5
IO_L209P
IO_L191P
5
IO_VREF_L209N
IO_L210P
AJ41
AG5
AK4
IO_L191N
5
IO_L192P
5
IO_L210N
IO_L192N
5
IO_L211P_YY
IO_L211N_YY
AH53
AG34
IO_L193P_YY
IO_L193N_YY
IO_L194P_YY
IO_L194N_YY
IO_L195P_YY
IO_VREF_L195N_YY
IO_L196P_YY
IO_L196N_YY
IO_L197P_YY
IO_L197N_YY
IO_L198P_YY
IO_VREF_L198N_YY
IO_L199P_YY
IO_L199N_YY
IO_L200P
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
T24
T104
U1
U45
U64
U74
V14
AE9
V55
AH10
AF9
V8
Y104
AA44
AB55
AB74
AC35
AH9
AK9
AF8
IO_L200N
AB11
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO
Pin #
AC54
AD14
AE55
AF3
AC6
AH24
AG23
AB9
AE4
AE31
AH1
AB84
AD63
AG1
AA10
AA9
AD4
AD5
AD2
AD3
AF2
AA8
AA7
AF1
Y9
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L229N_YY
IO_VREF_L229P_YY
IO_L230N
Pin #
Y74
AC1
V11
AA3
AA23
U104
W7
AA6
Y6
IO
IO
IO_L212N_YY
IO_L212P_YY
IO_L213N
IO_L230P
IO_L231N_YY
IO_L231P_YY
IO_L232N
IO_L213P
IO_L214N
IO_L232P
IO_L214P
IO_L233N_YY
IO_L233P_YY
IO_L234N_Y
IO_L234P_Y
IO_VREF_L215N_YY
IO_L215P_YY
IO_L216N_Y
IO_L216P_Y
IO_L217N_YY
IO_L217P_YY
IO_VREF_L218N
IO_L218P
Y4
AA14
V74
Y3
IO_L235N_YY
IO_L235P_YY
IO_VREF_L236N
IO_L236P
Y2
Y51
W5
W4
W6
V6
IO_L237N_YY
IO_L237P_YY
IO_L238N_YY
IO_L238P_YY
IO_L239N
IO_L219N_YY
IO_L219P_YY
IO_L220N_YY
IO_L220P_YY
IO_L221N
W2
U9
IO_L239P
V4
IO_L221P
IO_VREF_L240N_YY
IO_L240P_YY
IO_L241N_YY
IO_L241P_YY
IO_L242N
AB2
T8
IO_VREF_L222N_YY
IO_L222P_YY
IO_L223N_YY
IO_L223P_YY
IO_L224N
U5
AB6
AC4
AE1
W8
W1
Y1
IO_L242P
T9
IO_L224P
IO_L243N_YY
IO_L243P_YY
IO_VREF_L244N_YY
IO_L244P_YY
IO_L245N_YY
IO_L245P_YY
IO_VREF_L246N_YY
IO_L246P_YY
IO_L247N
T7
IO_L225N_YY
IO_L225P_YY
IO_VREF_L226N_YY
IO_L226P_YY
IO_L227N_YY
IO_L227P_YY
IO_L228N_YY
IO_L228P_YY
Y8
U3
AB4
AB3
W9
T5
V2
R94
T63
T42
U2
AA54
W103
AB1
V10
T1
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
Pin Description
Pin #
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L256P
Pin #
N6
N5
N1
M4
M5
M2
M11
L4
7
7
7
7
7
7
7
7
7
7
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
E3
F14
G15
G45
H35
J14
IO_L257N_YY
IO_L257P_YY
IO_L258N_YY
IO_L258P_YY
IO_L259N
IO_VREF_L259P
IO_L260N_YY
IO_L260P_YY
IO_L261N_Y
IO_L261P_Y
IO_L262N_YY
IO_L262P_YY
IO_L263N
J34
J44
L2
J64
M74
L54
L1
L104
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO
IO
N24
N84
N104
P35
P94
R15
T34
R10
R53
R64
R8
M8
K2
M9
L34
M104
K5
K1
L6
IO
IO_L263P
IO
IO_L264N
IO
IO_L264P
IO
IO_L265N_YY
IO_L265P_YY
IO_L266N_YY
IO_VREF_L266P_YY
IO_L267N_YY
IO_L267P_YY
IO_L268N_YY
IO_L268P_YY
IO_L269N_YY
IO_VREF_L269P_YY
IO_L270N_YY
IO_L270P_YY
IO_L271N
IO
IO_L247P
IO_L248N_YY
IO_L248P_YY
IO_L249N_YY
IO_VREF_L249P_YY
IO_L250N_YY
IO_L250P_YY
IO_L251N_YY
IO_VREF_L251P_YY
IO_L252N_YY
IO_L252P_YY
IO_L253N
K3
L7
K4
L8
R42
R7
J5
R3
K6
H4
H1
K7
J7
P10
P6
P5
P2
P7
IO_L271P
J2
IO_L253P
P4
IO_L272N_YY
IO_L272P_YY
IO_L273N_YY
IO_VREF_L273P_YY
IO_L274N
H5
G2
L9
IO_L254N_YY
IO_L254P_YY
IO_L255N_YY
IO_VREF_L255P_YY
IO_L256N
N4
R2
N7
G5
F3
P1
M6
IO_L274P
K8
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
Pin Description
IO_L275N_YY
IO_L275P_YY
IO_L276N_YY
IO_L276P_YY
IO_L277N
Pin #
G3
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin #
M20
N13
N14
N15
N16
N17
N18
P13
P18
R13
R18
T13
T18
U13
U18
V13
V14
V15
V16
V17
V18
W11
W12
W19
W20
Y11
Y12
Y19
Y20
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
E1
H6
E2
E4
IO_VREF_L277P
IO_L278N_YY
IO_L278P_YY
IO_L279N_Y
K9
J8
F4
D13
H74
G6
IO_L279P_Y
IO_L280N_YY
IO_VREF_L280P_YY
IO_L281N
C21
D2
IO_L281P
F5
IO_L282N_YY
IO_L282P_YY
D34
K103
2
CCLK
DONE
DXN
F26
AJ28
AJ3
AH4
AF4
AC7
AK3
AG28
B3
3
NA
NA
NA
NA
NA
NA
NA
NA
2
DXP
M0
M1
M2
PROGRAM
TCK
TDI
H22
D26
C1
TDO
NA
TMS
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
L11
L12
L19
L20
M11
M12
M19
NA
NA
NA
NA
NA
NA
NA
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
B6
M15
M14
L15
L14
H14
M13
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_5
Pin #
C12
B25
C19
M18
M17
L17
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
Pin #
Y14
W14
W13
AH12
AE2
V12
U12
T12
U11
T11
U8
H17
L16
M16
F29
M28
P23
R20
P20
R19
N19
P19
AE29
W28
U23
U20
T20
W3
F2
R12
P12
N12
R11
P11
P8
M3
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Y18
AH7
AK30
AJ30
B30
V19
T19
U19
AJ25
AH19
W18
AC17
Y17
W17
W16
Y16
AJ6
A30
AK29
AJ29
AC29
H29
B29
A29
AH28
V28
Y15
W15
AC14
N28
C28
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Table 26: FG900 — XCV600E, XCV1000E, XCV1600E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
AG27
D27
AF26
E26
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Notes:
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
J13
C13
V9
N9
F25
J9
AE25
G24
AJ23
AD24
H23
B23
AJ8
AC8
H8
AD7
B8
AE6
G7
AC23
AB22
V22
F6
AF5
E5
N22
AH18
AB18
J18
AG4
D4
V3
C18
U17
T17
N3
C3
AK2
AH3
AC2
H2
R17
P17
U16
T16
B2
R16
P16
A2
AK1
AJ2
AJ1
A1
U15
T15
R15
P15
B1
U14
T14
1. VREF or I/O option only in the XCV1000E and XCV1600E;
otherwise, I/O option only.
2.
V
REF or I/O option only in the XCV1600E; otherwise, I/O
R14
P14
option only.
3. I/O option only in the XCV600E.
4. No Connect in the XCV600E.
5. No Connect in the XCV600E, 1000E.
AH13
AB13
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Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
FG900 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
P
N
Other
Pair Bank
Pin
Pin
AO
4
Functions
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C10
F11
D11
G12
C11
D12
A11
B12
K13
B13
E13
B14
J14
H12
H13
E11
B11
F12
A10
E12
G13
A12
F13
G14
D14
A14
K14
B15
F15
A15
B16
A16
C16
K16
A17
F17
E18
D18
B19
D19
F18
B20
D20
G19
K18
B21
F20
-
2
-
2
-
2
-
-
VREF
1
1
-
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
-
P
N
Other
-
Pair Bank
Pin
Pin
AO
Functions
VREF
GCLK LVDS
A15
2
2
-
3
2
1
0
0
1
5
4
C15
E15
NA
NA
NA
NA
IO_DLL_ 34N
IO_DLL_ 34P
IO_DLL_ 177N
IO_DLL_ 177P
-
E16
-
AK16 AH16
J15
VREF
AJ16
AF16
H15
D15
E16
F16
H16
K15
G16
E17
C17
A18
A19
G18
H18
F19
K17
A20
C20
E20
D21
A21
NA
-
IO LVDS
VREF
Total Pairs: 283, Asynchronous Output Pairs: 168
NA
4
IO_ LVDS_DLL
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F7
G8
C4
D5
A3
4
2
2
2
-
VREF
-
4
-
2
H9
VREF
VREF
3
J10
D6
B4
-
-
4
A4
-
2
2
-
5
B5
E7
VREF
-
6
F8
A5
1
1
-
VREF
7
N11
E8
D7
G9
A6
-
-
8
-
1
1
-
9
J11
B7
VREF
-
10
11
12
13
14
15
16
17
C7
C8
G10
A8
2
2
-
VREF
H10
F10
H11
C9
-
-
-
-
-
-
-
-
2
2
2
4
VREF
D9
B9
NA
4
-
J12
A9
-
VREF
-
E10
G11
NA
NA
B10
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Module 4 of 4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 27: FG900 Differential Pin Pair Summary
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
XCV600E, XCV1000E, XCV1600E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
4
Functions
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
A22
B22
D22
C22
E22
A23
K19
B24
G22
C25
A26
K20
J21
C21
H19
E21
F21
H20
G21
A24
C24
H21
E23
D24
B26
D25
C26
B27
A27
B28
K21
E27
D28
E25
C30
F27
J23
VREF
86
87
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
J29
K27
M22
K28
N21
L24
L29
L26
L30
M26
N29
N25
N30
N26
P29
P22
P25
R21
R25
P24
R24
R22
R23
T21
U28
T23
U25
U24
W30
U21
V26
W26
W25
V24
K24
J30
-
4
4
-
4
VREF
-
88
K29
L25
K25
L27
M23
L28
M27
M29
M30
N27
P21
P28
N24
R26
R29
R28
T30
R27
U29
T27
T28
T25
U30
U27
V27
V29
U22
W29
W27
Y29
Y30
Y28
NA
4
D2
VREF
89
-
-
90
1
-
2
2
-
91
4
-
-
92
3
-
VREF
93
4
-
-
94
1
VREF
1
1
-
95
-
-
96
4
1
-
VREF
97
-
-
98
D3
F23
G23
F24
A28
C27
J22
2
2
2
4
-
99
-
VREF
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
2
-
-
-
-
4
4
VREF
CS
-
VREF
-
DIN, D0
4
C29
G25
E28
K22
D30
L21
G28
G27
K23
F30
H27
G30
J24
NA
1
-
4
-
NA
4
4
VREF
VREF
3
-
4
-
4
-
4
VREF
F28
E30
E29
H26
L22
G29
M21
J26
1
VREF
4
-
-
2
-
4
1
-
-
-
VREF
VREF
1
4
-
-
-
2
4
4
4
-
-
-
VREF
-
1
4
3
VREF
H30
K26
L23
J28
-
-
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 27: FG900 Differential Pin Pair Summary
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
XCV600E, XCV1000E, XCV1600E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
4
Functions
Pair Bank
Pin
Pin
AO
Functions
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
AA30
AA29
Y27
W24
V20
-
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
AC20 AG23
2
-
1
-
AF22
AJ22
AE22
AG22
-
W23
AB30
AA28
AA27
Y23
NA
-
VREF
Y26
D5
AK24 AD20
AA19 AF21
NA
4
-
V21
VREF
-
Y25
4
4
4
-
AH22 AA18
AG21 AK23
AH21 AD19
NA
NA
4
VREF
W22
Y24
-
-
AB28
VREF
-
AC30 AA25
W21 AA24
AB26 AD30
Y22 AC27
-
AE20
AJ21
2
-
2
-
AG20 AF20
2
-
-
AC18
AJ20
AF19
AE19
2
-
VREF
-
AD28 AB25
AC26 AE30
AD27 AF30
2
4
-
AK22 AH20
AG19 AB17
VREF
-
1
1
-
-
AJ19
AD17
-
AF29
AB24
1
4
VREF
AA16 AA17
AK21 AB16
AG18 AK20
AK19 AD16
AE16 AE17
-
AB23 AE28
AG30 AC25
AE26 AG29
AH30 AC24
-
VREF
3
-
2
2
-
4
VREF
-
1
-
-
AF28
AH29 AA22
AF27 AK28
AG26 AH27
AD25
NA
-
AG17
AJ17
VREF
INIT
AD15 AH17
AG16 AK17
NA
4
-
-
VREF
4
2
2
2
-
AF16
AH16
NA
4
IO_ LVDS_DLL
AD23
AB21
AJ27
AF25
-
AC15 AG15
VREF
VREF
AB15
AA15
AF15
AF14
-
AC22 AH26
AA21 AG25
-
VREF
-
AH15 AK15
-
AJ26
AA20 AH25
AC21 AF24
AG24 AK26
AJ24 AF23
AE23 AB20
AD22
VREF
AB14
AH14
AF13
AJ14
2
2
-
1
1
-
-
-
AE14 AG13
AK13 AD13
VREF
-
VREF
-
-
-
-
AE13
AF12
1
1
2
AC13 AA13
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 27: FG900 Differential Pin Pair Summary
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
XCV600E, XCV1000E, XCV1600E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
Functions
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
AA12
AJ12
VREF
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
Y9
AC4
W8
AB4
W9
W10
V10
AC1
AA3
U10
AA6
Y4
AF1
AB6
AE1
Y8
VREF
AB12 AE11
AK12 Y13
AG11 AF11
AH11 AJ11
-
-
2
2
2
4
-
2
4
-
-
-
-
AB3
AA5
AB1
Y7
4
VREF
AE12 AG10
AD12 AK11
-
4
-
-
4
-
AJ10
AC12
VREF
4
VREF
AK10 AD11
4
4
-
V11
AA2
W7
Y6
NA
4
-
AJ9
AH10
AH9
AF8
AE9
AF9
AK9
AB11
AG8
AF7
AK7
AD10
AC10
AG6
AJ5
-
-
VREF
1
-
-
4
-
2
2
-
V7
AA1
Y3
3
-
AC11
AK8
AG7
AJ7
-
Y2
4
-
VREF
W5
W6
W2
V4
Y5
1
VREF
-
W4
V6
-
1
1
-
4
1
-
AH6
AD9
AB10
AD8
AC9
AG5
AH5
AC6
AG2
AE4
AH1
AD6
AA10
AD4
AD2
AF2
-
U9
-
VREF
T8
AB2
U5
VREF
-
W1
T9
-
AK5
AJ4
2
2
2
4
-
Y1
2
4
-
VREF
U3
T7
-
AK4
AG3
AF3
AH2
AB9
AE3
AB8
AG1
AA9
AD5
AD3
AA8
-
V2
T5
4
VREF
-
-
T6
R9
4
-
U2
T4
4
VREF
NA
1
-
R10
R6
T1
NA
4
-
R5
-
4
VREF
R4
R8
4
VREF
3
-
R3
R7
4
-
4
-
P6
P10
P5
4
VREF
1
VREF
P2
4
-
-
-
-
P4
P7
2
-
-
4
1
R2
N4
AA7
P1
N7
VREF
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Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
FG1156 Fine-Pitch Ball Grid Array Package
CG1156 Ceramic Ball Grid Array Package
P
N
Other
XCV1000E, XCV1600E, XCV2000E, and XCV2600E
devices in the FG1156 fine-pitch Ball Grid Array package
and XCV3200E device in the CG1156 package have foot-
print compatibility. Pins labeled IO_VREF can be used as
either VREF or general io unless indicated in the footnotes. If
the pin is not used as VREF, it can be used as general I/O.
Immediately following Table 28, see Table 29 for Differential
Pair information.
Pair Bank
Pin
Pin
AO
1
Functions
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
Notes:
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
N6
N1
M5
M1
L2
M6
N5
M4
M2
L4
M7
L1
K2
L3
K5
L6
L7
L8
K6
H1
J7
-
4
-
-
1
4
VREF
-
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
L5
3
-
Bank
0
Pin Description
Pin #
E17
B4
M8
M9
M10
K1
K3
K4
J5
4
-
GCK3
1
-
0
IO
NA
-
0
IO
B9
-
0
IO
B10
D93
D16
E73
E113
E133
E163
F173
J123
J133
J143
K113
F7
VREF
0
IO
4
4
4
4
2
-
0
IO
IO
-
0
H4
K7
J2
VREF
0
IO
-
-
0
IO
G2
G5
K8
E1
E2
K9
F4
H5
L9
F3
G3
H6
E4
J8
-
0
IO
VREF
0
IO
1
4
-
0
IO
-
0
IO
-
0
IO
1
4
3
4
1
4
VREF
0
IO
-
0
IO_L0N_Y
IO_L0P_Y
IO_L1N_Y
IO_L1P_Y
IO_VREF_L2N_Y
IO_L2P_Y
IO_L3N_Y
IO_L3P_Y
IO_L4N_YY
IO_L4P_YY
IO_VREF_L5N_YY
IO_L5P_YY
H7
C2
F5
D1
G6
D2
D3
-
0
H9
VREF
0
C5
-
-
0
J10
E6
K10
0
0
D6
1. AO in the XCV600E, 1000E.
2. AO in the XCV1000E.
3. AO in the XCV1600E.
0
A4
0
G8
4. AO in the XCV1000E, XCV1600E.
0
C6
0
J11
G9
0
0
F8
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L6N_YY
IO_L6P_YY
IO_L7N_Y
Pin #
A54
H105
D7
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L23N_Y
IO_L23P_Y
IO_L24N_Y
IO_L24P_Y
IO_L25N_Y
IO_L25P_Y
IO_L26N_YY
IO_L26P_YY
IO_VREF_L27N_YY
IO_L27P_YY
IO_L28N_YY
IO_L28P_YY
IO_L29N_Y
IO_L29P_Y
IO_L30N_Y
IO_L30P_Y
IO_L31N
Pin #
G13
C12
K15
A12
B12
H14
D12
F13
IO_L7P_Y
B5
IO_L8N_Y
K12
E8
IO_L8P_Y
IO_L9N
B64
F95
G10
C7
IO_L9P
IO_L10N_YY
IO_L10P_YY
IO_VREF_L11N_YY
IO_L11P_YY
IO_L12N
A13
B13
J154
G145
C13
F14
D8
B7
H114
C85
E9
IO_L12P
IO_L13N_Y
IO_L13P_Y
IO_VREF_L14N_Y
IO_L14P_Y
IO_L15N
H15
D13
A144
K165
E14
B14
G15
D14
J164
D155
F15
B8
K132
G11
A84
F105
C9
IO_L31P
IO_L32N_YY
IO_L32P_YY
IO_VREF_L33N_YY
IO_L33P_YY
IO_L34N
IO_L15P
IO_L16N_YY
IO_L16P_YY
IO_VREF_L17N_YY
IO_L17P_YY
IO_L18N_Y
IO_L18P_Y
IO_L19N_Y
IO_L19P_Y
IO_VREF_L20N_YY
IO_L20P_YY
IO_L21N_YY
IO_L21P_YY
IO_L22N_Y
IO_L22P_Y
H12
D10
A9
IO_L34P
F11
A10
K14
C10
H13
G12
A11
B11
E12
D11
IO_L35N_Y
IO_L35P_Y
IO_L36N_Y
IO_L36P_Y
IO_L37N
B15
A15
E15
G164
A165
F16
IO_L37P
IO_L38N_YY
IO_L38P_YY
IO_VREF_L39N_YY
IO_L39P_YY
J17
C16
B16
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
XCV2600E and CG1156 — XCV3200E
Bank
Pin Description
IO_L40N_Y
Pin #
H17
A17
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L49N_Y
IO_L49P_Y
IO_L50N
Pin #
A20
G20
B205
F204
D20
E20
H20
A21
E215
J204
D21
K20
B21
H21
G215
F214
A22
B22
J21
0
0
0
0
0
IO_L40P_Y
IO_VREF_L41N_Y
IO_L41P_Y
G171
B17
IO_L50P
IO_LVDS_DLL_L42N
C17
IO_L51N_YY
IO_VREF_L51P_YY
IO_L52N_YY
IO_L52P_YY
IO_L53N
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GCK2
D17
A18
IO
IO
B183
B24
IO
IO_L53P
IO
B25
IO_L54N_Y
IO_L54P_Y
IO
E223
E233
D183
D19
D253
D263
D283
D293
G233
J233
J18
IO
IO
IO_L55N_Y
IO_L55P_Y
IO_L56N_YY
IO_L56P_YY
IO_L57N_YY
IO_VREF_L57P_YY
IO_L58N_YY
IO_L58P_YY
IO_L59N_Y
IO_L59P_Y
IO_L60N_Y
IO_L60P_Y
IO
IO
IO
IO
IO
IO
C22
D22
G22
K21
A23
F22
B23
C23
H22
D23
K22
A24
J22
IO
IO_LVDS_DLL_L42P
IO_L43N_Y
IO_VREF_L43P_Y
IO_L44N_Y
IO_L44P_Y
IO_L45N_YY
IO_VREF_L45P_YY
IO_L46N_YY
IO_L46P_YY
IO_L47N
IO_L47P
IO_L48N_Y
IO_L48P_Y
G18
C181
H18
F18
IO_L61N_Y
IO_L61P_Y
B19
IO_L62N_Y
IO_L62P_Y
IO_L63N_YY
IO_L63P_YY
IO_L64N_YY
IO_VREF_L64P_YY
IO_L65N_Y
IO_L65P_Y
A19
K19
C19
F195
E194
G19
J19
H23
D24
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Description
IO_L66N_Y
Pin #
A25
E24
A26
C25
F24
Bank
Pin Description
IO_L83N_Y
Pin #
L25
1
1
1
1
1
1
IO_L66P_Y
IO_L83P_Y
B30
B31
E29
A31
D30
IO_L67N_YY
IO_VREF_L67P_YY
IO_L68N_YY
IO_L68P_YY
IO_L69N
IO_L84N
IO_L84P
IO_WRITE_L85N_YY
IO_CS_L85P_YY
B26
K235
F254
C26
H242
G24
A27
B275
G254
E26
C27
J24
IO_L69P
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO
F313
J32
IO_L70N_Y
IO
IO_VREF_L70P_Y
IO_L71N_Y
IO
K273
K313
L283
L303
M323
N26
N283
P253
U263
U30
U323
U34
M30
D32
J27
IO
IO_L71P_Y
IO
IO_L72N
IO
IO_L72P
IO
IO_L73N_YY
IO_VREF_L73P_YY
IO_L74N_YY
IO_L74P_YY
IO_L75N
IO
IO
IO
B28
K245
H254
D27
F26
IO
IO
IO_L75P
IO
IO_L76N_Y
IO
IO_L76P_Y
IO_D2
IO_L77N_Y
G26
C28
E275
J254
A30
H26
G27
B29
F27
IO_DOUT_BUSY_L86P_YY
IO_DIN_D0_L86N_YY
IO_L87P_Y
IO_L87N_Y
IO_L88P_Y
IO_L88N_Y
IO_VREF_L89P_Y
IO_L89N_Y
IO_L90P
IO_L77P_Y
IO_L78N_YY
IO_L78P_YY
IO_L79N_YY
IO_VREF_L79P_YY
IO_L80N_YY
IO_L80P_YY
IO_L81N_Y
E31
F30
G29
F32
E32
G30
M25
G31
L26
IO_L81P_Y
C29
E28
F28
IO_L90N
IO_L82N_Y
IO_L91P_Y
IO_L91N_Y
IO_VREF_L82P_Y
D33
Module 4 of 4
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
XCV2600E and CG1156 — XCV3200E
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_VREF_L92P_Y
IO_L92N_Y
Pin #
D34
H29
J284
E335
H28
H30
H32
K28
L274
F335
M26
E34
H31
G32
N254
J315
J30
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Description
IO_L109P_Y
IO_L109N_Y
IO_L110P_Y
IO_L110N_Y
IO_L111P
Pin #
L31
L33
IO_L93P_YY
IO_L93N_YY
IO_L94P_YY
IO_L94N_YY
IO_L95P_Y
P27
M33
M31
R26
N30
P28
N29
N33
T254
N345
P34
R27
P29
P31
P334
T265
R34
R28
N31
N32
P304
R335
R29
T34
IO_L111N
IO_L112P_Y
IO_L112N_Y
IO_VREF_L113P_Y
IO_L113N_Y
IO_L114P_YY
IO_L114N_YY
IO_L115P_YY
IO_L115N_YY
IO_L116P_Y
IO_L116N_Y
IO_L117P_Y
IO_L117N_Y
IO_L118P_Y
IO_L118N_Y
IO_VREF_L119P_YY
IO_D3_L119N_YY
IO_L120P_YY
IO_L120N_YY
IO_L121P_YY
IO_L121N_YY
IO_L122P_Y
IO_L122N_Y
IO_L123P
IO_L95N_Y
IO_L96P_Y
IO_L96N_Y
IO_L97P_Y
IO_L97N_Y
IO_VREF_L98P_YY
IO_L98N_YY
IO_L99P_YY
IO_L99N_YY
IO_L100P_YY
IO_L100N_YY
IO_VREF_L101P_Y
IO_L101N_Y
IO_L102P
G33
H342
J29
M274
H335
K29
J34
IO_L102N
IO_L103P_Y
IO_L103N_Y
IO_VREF_L104P_YY
IO_L104N_YY
IO_L105P_YY
IO_L105N_YY
IO_L106P_Y
L29
J33
M28
K34
N27
L34
R30
T30
T284
R315
T29
IO_L106N_Y
IO_VREF_L107P_YY
IO_D1_L107N_YY
IO_L108P_Y
IO_L123N
K33
P26
R25
M34
IO_L124P_Y
IO_L124N_Y
IO_VREF_L125P_YY
IO_L125N_YY
U27
T31
IO_L108N_Y
T33
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Bank
Pin Description
IO_L126P_YY
IO_L126N_YY
IO_VREF_L127P_Y
IO_L127N_Y
Pin #
U28
T32
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L135N_YY
IO_L136P_YY
IO_L136N_YY
IO_D4_L137P_YY
IO_VREF_L137N_YY
IO_L138P_Y
Pin #
Y30
2
2
2
2
2
2
AA345
W314
AA33
Y29
U291
U33
V33
U31
IO_L128P_YY
IO_L128N_YY
W25
IO_L138N_Y
AB34
Y285
AB334
AA30
Y26
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO
V273
V31
IO_L139P_Y
IO
IO_L139N_Y
IO
V323
W33
IO_L140P_Y
IO
IO_L140N_Y
IO
AB253
AB263
AB313
AC313
AF34
AG313
AG333
AG34
AH293
AJ303
V26
IO_L141P_YY
IO_L141N_YY
IO_L142P_YY
IO_L142N_YY
IO_L143P_Y
Y27
IO
IO
AA31
AA275
AA294
AB32
AB29
AA28
AC34
Y25
IO
IO
IO
IO_VREF_L143N_Y
IO_L144P_Y
IO
IO
IO_L144N_Y
IO
IO_L145P
IO
IO_L145N
AD34
AB30
AC33
AA26
AC32
AD33
AB28
AE34
AB27
AE33
AC30
AA25
AE32
AE31
IO_L129P_Y
IO_VREF_L129N_Y
IO_L130P_YY
IO_L130N_YY
IO_L131P_YY
IO_VREF_L131N_YY
IO_L132P_Y
IO_L132N_Y
IO_L133P
IO_L133N
IO_L134P_Y
IO_L134N_Y
IO_L135P_YY
IO_L146P_Y
V301
W34
IO_L146N_Y
IO_L147P_Y
V28
IO_L147N_Y
W32
IO_L148P_Y
W30
IO_L148N_Y
V29
IO_L149P_YY
IO_D5_L149N_YY
IO_D6_L150P_YY
IO_VREF_L150N_YY
IO_L151P_Y
Y34
W295
Y334
W26
W28
IO_L151N_Y
Y31
IO_L152P_YY
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
XCV2600E and CG1156 — XCV3200E
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Description
IO_L152N_YY
IO_L153P_YY
IO_VREF_L153N_YY
IO_L154P_Y
Pin #
AD29
AD31
AF33
AC28
AF31
AC275
AF324
AE29
AD282
AD30
AG32
AC265
AH334
AD26
AF30
AC25
AH32
AE285
AL344
AG30
AD27
AF29
AK34
AD255
AE274
AJ33
Bank
Pin Description
IO_L169N_Y
IO_L170P_Y
IO_L170N_Y
IO_D7_L171P_YY
IO_INIT_L171N_YY
IO
Pin #
AJ32
AK33
AH30
AK32
AK31
V34
3
3
3
3
3
3
IO_L154N_Y
IO_L155P_Y
IO_L155N_Y
IO_L156P_Y
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
GCK0
AH18
AE213
AG18
AG23
AH243
AH253
AJ283
AK183
AK193
AL25
IO_VREF_L156N_Y
IO_L157P_YY
IO_L157N_YY
IO_L158P_YY
IO_L158N_YY
IO_L159P_YY
IO_VREF_L159N_YY
IO_L160P_Y
IO
IO
IO
IO
IO
IO
IO
IO
IO_L160N_Y
IO
IO_L161P_Y
IO
AL273
AL303
AN18
AN223
AN243
AP31
AK29
AP30
AN31
AH27
AN30
AM30
AK28
AG26
AN29
AF25
IO_L161N_Y
IO
IO_L162P_Y
IO
IO_L162N_Y
IO
IO_L163P_YY
IO_L163N_YY
IO_L164P_YY
IO_L164N_YY
IO_L165P_Y
IO
IO_L172P_YY
IO_L172N_YY
IO_L173P_Y
IO_L173N_Y
IO_L174P_Y
IO_L174N_Y
IO_VREF_L175P_Y
IO_L175N_Y
IO_L176P_Y
IO_L176N_Y
IO_L177P_YY
IO_L177N_YY
IO_VREF_L165N_Y
IO_L166P_Y
AH31
AE26
AL33
AF28
AL32
AJ31
IO_L166N_Y
IO_L167P
IO_L167N
IO_L168P_Y
IO_VREF_L168N_Y
IO_L169P_Y
AF27
AG29
AM29
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_VREF_L178P_YY
IO_L178N_YY
IO_L179P_YY
IO_L179N_YY
IO_L180P_Y
Pin #
AL29
AL28
AE244
AN285
AJ27
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Pin Description
IO_L195P_Y
IO_L195N_Y
IO_L196P_Y
IO_L196N_Y
IO_L197P_Y
IO_L197N_Y
IO_L198P_Y
IO_L198N_Y
IO_L199P_YY
IO_L199N_YY
IO_VREF_L200P_YY
IO_L200N_YY
IO_L201P_YY
IO_L201N_YY
IO_L202P_Y
IO_L202N_Y
IO_L203P_Y
IO_L203N_Y
IO_L204P
Pin #
AG22
AN23
AP23
AM23
AH22
AP22
AL23
AF21
AL22
AJ22
IO_L180N_Y
AH26
AG25
AK27
AM284
AF245
AJ26
IO_L181P_Y
IO_L181N_Y
IO_L182P
IO_L182N
IO_L183P_YY
IO_L183N_YY
IO_VREF_L184P_YY
IO_L184N_YY
IO_L185P
AK22
AM22
AG214
AJ215
AP21
AE20
AH21
AL21
AN214
AF205
AK21
AP20
AE19
AN20
AG204
AL205
AH20
AK20
AN19
AJ20
AP27
AK26
AN27
AE234
AM275
AL26
AP26
AN262
AJ25
IO_L185N
IO_L186P_Y
IO_L186N_Y
IO_VREF_L187P_Y
IO_L187N_Y
IO_L204N
IO_L188P
AG244
AP255
AF23
AM26
AJ24
IO_L205P_YY
IO_L205N_YY
IO_VREF_L206P_YY
IO_L206N_YY
IO_L207P_Y
IO_L207N_Y
IO_L208P_Y
IO_L208N_Y
IO_L209P_Y
IO_L209N_Y
IO_L210P
IO_L188N
IO_L189P_YY
IO_L189N_YY
IO_VREF_L190P_YY
IO_L190N_YY
IO_L191P_Y
AN25
AE22
AM25
AK24
AH23
AF22
AP24
AL24
AK23
IO_L191N_Y
IO_L192P_Y
IO_L192N_Y
IO_VREF_L193P_YY
IO_L193N_YY
IO_L194P_YY
IO_L194N_YY
AF194
AP195
AM19
AH19
IO_L210N
IO_L211P_YY
IO_L211N_YY
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Preliminary Product Specification
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
XCV2600E and CG1156 — XCV3200E
Bank
Pin Description
IO_VREF_L212P_YY
IO_L212N_YY
Pin #
AJ19
AP18
AF18
AP17
AJ181
AL18
AM18
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L221N_Y
IO_L222P_Y
Pin #
AH16
AN15
AF16
AP145
AE164
AK15
AJ15
4
4
4
4
4
4
4
IO_L213P_Y
IO_L222N_Y
IO_L223P_Y
IO_L213N_Y
IO_VREF_L214P_Y
IO_L214N_Y
IO_L223N_Y
IO_L224P_YY
IO_VREF_L224N_YY
IO_L225P_YY
IO_L225N_YY
IO_L226P
IO_LVDS_DLL_L215P
AH15
AN14
AK145
AG154
AM13
AF15
AG14
AP13
AE145
AE154
AN13
AG13
AH14
AP12
AJ14
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GCK1
AL19
AF173
AG123
AH12
AJ103
AJ113
AK73
IO
IO
IO_L226N
IO
IO_L227P_Y
IO
IO_L227N_Y
IO_L228P_Y
IO
IO
IO
IO_L228N_Y
IO_L229P_YY
IO_L229N_YY
IO_L230P_YY
IO_VREF_L230N_YY
IO_L231P_YY
IO_L231N_YY
IO_L232P_Y
AK133
AL133
AM43
AN9
IO
IO
IO
IO
AN103
AN16
AN173
AL17
IO
IO
IO_LVDS_DLL_L215N
IO_L216P_Y
IO_VREF_L216N_Y
IO_L217P_Y
IO_L217N_Y
IO_L218P_YY
IO_VREF_L218N_YY
IO_L219P_YY
IO_L219N_YY
IO_L220P
IO_L220N
IO_L221P_Y
IO_L232N_Y
IO_L233P_Y
AL14
AF13
AN12
AF14
AP11
AN11
AH13
AM12
AL12
AJ13
AH17
AM171
AJ17
IO_L233N_Y
IO_L234P_Y
AG17
AP16
AL16
IO_L234N_Y
IO_L235P_Y
IO_L235N_Y
IO_L236P_YY
IO_L236N_YY
IO_L237P_YY
IO_VREF_L237N_YY
IO_L238P_Y
AJ16
AM16
AK165
AP154
AL15
AP10
AK12
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Bank
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Pin Description
IO_L238N_Y
IO_L239P_Y
Pin #
AM10
AP9
Bank
Pin Description
IO_VREF_L255N_Y
IO_L256P_Y
Pin #
AG9
AH8
AP4
AN4
AJ7
5
5
5
5
5
5
5
IO_L239N_Y
IO_L240P_YY
IO_VREF_L240N_YY
IO_L241P_YY
IO_L241N_YY
IO_L242P
AK11
AL11
AL10
AE13
AM9
AF125
AP84
AL9
IO_L256N_Y
IO_L257P_Y
IO_L257N_Y
IO_L258P_YY
IO_L258N_YY
AM5
AK6
IO_L242N
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO
T1
V2
IO_L243P_Y
IO
IO_VREF_L243N_Y
IO_L244P_Y
AH112
AF11
AN8
IO
V3
IO
V53
IO_L244N_Y
IO_L245P_Y
IO
V83
AM85
AG114
AL8
IO
AA103
AB53
AB73
AB93
AD73
AD83
AE2
AE4
AJ43
AH53
AH6
AF8
AE9
AK3
AD10
AL2
IO_L245N_Y
IO_L246P_YY
IO_VREF_L246N_YY
IO_L247P_YY
IO_L247N_YY
IO_L248P
IO
IO
AK9
IO
AH10
AN7
IO
IO
AE125
AJ94
AM7
AL7
IO
IO_L248N
IO
IO_L249P_Y
IO
IO_L249N_Y
IO_L250P_Y
IO
AG10
AN6
IO_L259N_YY
IO_L259P_YY
IO_L260N_Y
IO_L260P_Y
IO_L261N_Y
IO_L261P_Y
IO_VREF_L262N_Y
IO_L262P_Y
IO_L263N
IO_L263P
IO_L264N_Y
IO_L250N_Y
IO_L251P_YY
IO_L251N_YY
IO_L252P_YY
IO_VREF_L252N_YY
IO_L253P_YY
IO_L253N_YY
IO_L254P_Y
AK85
AH94
AP5
AJ8
AE11
AN5
AL1
AH4
AG6
AK1
AF7
AF10
AM6
AL6
IO_L254N_Y
IO_L255P_Y
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
XCV2600E and CG1156 — XCV3200E
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L264P_Y
Pin #
AK2
AJ3
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Pin Description
IO_L281P_YY
IO_L282N_Y
IO_L282P_Y
IO_L283N_Y
IO_L283P_Y
IO_L284N_Y
IO_L284P_Y
IO_L285N
Pin #
AC2
AA9
AC3
AC4
AD4
AA8
AB6
AB1
Y10
AB2
AA7
AA4
AA1
Y94
AB45
AA2
Y8
IO_VREF_L265N_Y
IO_L265P_Y
AG5
AD94
AJ25
AC10
AH2
AH3
AF5
IO_L266N_YY
IO_L266P_YY
IO_L267N_YY
IO_L267P_YY
IO_L268N_Y
IO_L268P_Y
IO_L285P
IO_L269N_Y
AE84
AG35
AE7
AG2
AF6
IO_L286N_Y
IO_L286P_Y
IO_VREF_L287N_Y
IO_L287P_Y
IO_L288N_YY
IO_L288P_YY
IO_L289N_YY
IO_L289P_YY
IO_L290N_Y
IO_L290P_Y
IO_L291N_Y
IO_L291P_Y
IO_L292N_Y
IO_L292P_Y
IO_VREF_L293N_YY
IO_L293P_YY
IO_L294N_YY
IO_L294P_YY
IO_L295N_YY
IO_L295P_YY
IO_L296N_Y
IO_L296P_Y
IO_L297N_Y
IO_L297P_Y
IO_L298N_Y
IO_L269P_Y
IO_L270N_Y
IO_L270P_Y
IO_VREF_L271N_YY
IO_L271P_YY
IO_L272N_YY
IO_L272P_YY
IO_L273N_YY
IO_L273P_YY
IO_VREF_L274N_Y
IO_L274P_Y
AG1
AC94
AG45
AE6
AF3
AA6
AA5
AB34
Y75
Y1
AF12
AF4
IO_L275N
AB104
AF25
AC8
AE1
AD5
AE3
AC7
AD1
AD6
AD2
AB8
AC1
AC5
IO_L275P
W10
Y5
IO_L276N_Y
IO_L276P_Y
Y2
IO_VREF_L277N_YY
IO_L277P_YY
IO_L278N_YY
IO_L278P_YY
IO_L279N_Y
W94
W25
W7
Y4
W1
IO_L279P_Y
Y6
IO_VREF_L280N_YY
IO_L280P_YY
IO_L281N_YY
W64
W35
V9
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Bank
Pin Description
IO_L298P_Y
Pin #
W4
W5
V1
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L307N_Y
IO_L307P_Y
IO_L308N_Y
IO_L308P_Y
IO_L309N_YY
IO_L309P_YY
IO_L310N_YY
IO_VREF_L310P_YY
IO_L311N_Y
IO_L311P_Y
IO_L312N_Y
IO_L312P_Y
IO_L313N_Y
IO_L313P_Y
IO_L314N_YY
IO_L314P_YY
IO_L315N_YY
IO_L315P_YY
IO_L316N_Y
IO_VREF_L316P_Y
IO_L317N_Y
IO_L317P_Y
IO_L318N
Pin #
T55
R14
R6
6
6
6
6
6
6
6
IO_VREF_L299N_YY
IO_L299P_YY
IO_L300N_YY
V7
T10
R2
IO_L300P_YY
U2
IO_VREF_L301N_Y
IO_L301P_Y
V61
U1
R5
P1
P5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO
F5
G63
H1
R8
IO
P2
IO
R95
N14
P4
IO
H73
K23
K43
L63
M53
M103
N53
N10
R74
T2
IO
IO
R10
P8
IO
IO
N2
IO
P65
P74
M1
N4
IO
IO
IO
IO
N6
IO
T73
U8
N3
IO
P9
IO
V43
U9
IO_L318P
M2
N7
IO_L302N_YY
IO_L302P_YY
IO_L303N_Y
IO_VREF_L303P_Y
IO_L304N_YY
IO_L304P_YY
IO_L305N_YY
IO_VREF_L305P_YY
IO_L306N_Y
IO_L306P_Y
IO_L319N_Y
IO_L319P_Y
IO_L320N_Y
IO_L320P_Y
IO_L321N_Y
IO_L321P_Y
IO_L322N_YY
IO_L322P_YY
IO_L323N_YY
IO_VREF_L323P_YY
U4
M3
P10
M4
L1
U7
U51
U3
U6
N8
T3
L2
T6
N9
T9
M7
K1
T4
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
XCV2600E and CG1156 — XCV3200E
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L324N_Y
Pin #
M8
L4
Bank
Pin Description
IO_L341N_Y
Pin #
E3
7
7
7
7
7
7
IO_L324P_Y
IO_VREF_L341P_Y
IO_L342N_Y
J8
IO_L325N_YY
IO_L325P_YY
IO_L326N_YY
IO_VREF_L326P_YY
IO_L327N_Y
J1
E4
L5
IO_L342P_Y
D2
F4
J2
IO_L343N_Y
K3
IO_L343P_Y
D3
L7
IO_L327P_Y
J3
2
CCLK
DONE
DXN
C31
AM31
AJ5
AL5
AK4
AG7
AL3
AG28
D5
IO_L328N_Y
M95
H24
J4
3
IO_L328P_Y
NA
NA
NA
NA
NA
NA
NA
NA
2
IO_L329N_Y
DXP
IO_VREF_L329P_Y
IO_L330N_YY
IO_L330P_YY
IO_L331N_YY
IO_L331P_YY
IO_L332N_YY
IO_VREF_L332P_YY
IO_L333N_Y
K62
L8
M0
M1
G2
H35
K74
G3
J5
M2
PROGRAM
TCK
TDI
C30
K26
C4
TDO
L9
NA
TMS
IO_L333P_Y
H5
J65
H44
G4
K8
IO_L334N_Y
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
K10
K17
K18
K25
L11
L24
M12
M23
N13
N14
N15
N16
N19
N20
IO_L334P_Y
IO_L335N_Y
IO_L335P_Y
IO_L336N_YY
IO_L336P_YY
IO_L337N_YY
IO_L337P_YY
IO_L338N_Y
J7
F2
F35
L104
E1
IO_VREF_L338P_Y_Y
IO_L339N_Y
H6
G5
E2
IO_L339P_Y
IO_L340N
K9
IO_L340P
D1
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
131
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Pin #
N21
Bank
Pin Description
Pin #
N22
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
M17
L17
L16
E10
C14
A6
P13
P22
R13
R22
T13
T22
M13
M14
M15
M16
L12
L13
L14
L15
M18
L18
L23
E25
C21
A29
M19
M20
M21
M22
L19
L20
L21
L22
U24
U23
N24
M24
K30
U10
U25
V10
V25
W13
W22
Y13
Y22
AA13
AA22
AB13
AB14
AB15
AB16
AB19
AB20
AB21
AB22
AC12
AC23
AD24
AD11
AE10
AE17
AE18
AE25
Module 4 of 4
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Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
XCV2600E and CG1156 — XCV3200E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
Pin #
F34
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_4
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_7
VCCO_7
VCCO_7
Pin #
AD21
AD22
AD23
AC17
AD17
AC13
AC14
AC15
AC16
AP6
T23
T24
R23
R24
P23
P24
P32
N23
V23
V24
AM14
AK10
AD12
AD13
AD14
AD15
AD16
V11
Y23
Y24
W23
W24
AJ34
AE30
AC24
AB23
AB24
AA23
AA24
AA32
AD18
AC18
AC19
AC20
AC21
AC22
AP29
AM21
AK25
AD19
AD20
V12
Y11
Y12
W11
W12
AJ1
AE5
AC11
AB11
AB12
AA3
AA11
AA12
U11
U12
N12
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
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Module 4 of 4
133
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
Pin #
M11
K5
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
AM15
AK17
AH34
AC6
AA21
Y21
W20
V20
U21
T21
F1
T11
T12
R11
R12
P3
P11
P12
N11
R20
P20
H16
F23
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K32
R4
AN1
AM11
AK5
AH28
AD32
AA20
Y20
W19
V19
U20
T20
R19
P19
H8
C3
B2
A28
AP34
AM3
AL31
AH7
AD3
AA19
Y19
W18
V18
U19
T19
F12
C2
R18
P18
J26
B1
A7
F6
AP1
AN2
C1
C34
Module 4 of 4
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
XCV2600E and CG1156 — XCV3200E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
A3
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
H27
E5
AP2
AN3
AM20
AK30
AG8
AC29
Y3
C15
B32
A33
AP7
AN33
AM32
AJ12
AG19
AA15
Y15
Y32
W21
V21
T8
T27
R21
P21
H19
F29
C11
B3
W14
V14
U15
T15
R14
P14
M29
G1
A32
AP3
AN32
AM24
AJ6
AG16
AA14
Y14
W8
E18
C20
B33
A34
AP28
AN34
AM33
AJ23
AG27
AA16
Y16
W27
U14
T14
R3
W15
V15
R32
M6
U16
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
135
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E and CG1156 — XCV3200E
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
T16
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
GND
Pin #
V17
U18
T18
R17
P17
J9
R15
P15
L3
GND
GND
GND
G7
GND
E30
C24
B34
AP32
AM1
AM34
AJ29
AF9
AA17
Y17
W16
V16
U17
T17
GND
GND
G34
D31
C33
A2
GND
GND
GND
GND
AB17
AB18
N17
N18
U13
V13
U22
V22
GND
GND
GND
GND
GND
GND
GND
Notes:
1. VREF or I/O option only in the XCV1600E, XCV2000E,
XCV2600E, and XCV3200E; otherwise, I/O option only.
R16
P16
L32
2. VREF or I/O option only in the XCV2000E, XCV2600E, and
XCV3200E; otherwise, I/O option only.
3. No Connect in the XCV1000E, XCV1600E.
4. No Connect in the XCV1000E.
5. I/O in the XCV1000E.
G28
D4
C32
A1
AP33
AM2
AL4
AH1
AF26
AA18
Y18
W17
Module 4 of 4
136
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E
CG1156 Differential Pin Pair Summary: XCV3200E
FG1156 / CG1156 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
H12
A9
C9
-
D10
F11
K14
H13
A11
E12
G13
K15
B12
D12
A13
J15
VREF
A10
C10
G12
B11
D11
C12
A12
H14
F13
B13
G14
F14
D13
K16
B14
D14
D15
B15
E15
A16
J17
B16
A17
B17
J18
C18
F18
A19
C19
E19
2
2
-
-
VREF
-
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E
CG1156 Differential Pin Pair Summary: XCV3200E
2
1
1
5
-
-
P
N
Other
-
Pair Bank
Pin
Pin
AO
Functions
-
GCLK LVDS
-
3
2
1
0
0
1
5
4
E17
D17
C17
J18
NA
IO_DLL_L 42N
IO_DLL_L 42P
IO_DLL_L 215N
IO_DLL_L 215P
VREF
NA
NA
NA
6
5
-
AL19
AL17
C13
H15
A14
E14
G15
J16
-
AH18 AM18
IO LVDS
Total Pairs: 344, Asynchronous Output Pairs: 134
5
-
NA
-
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
H9
J10
D6
F7
C5
2
1
1
5
-
-
-
VREF
2
E6
VREF
4
1
-
3
G8
J11
F8
A4
-
F15
A15
G16
F16
C16
H17
G17
C17
G18
H18
B19
K19
F19
-
4
C6
-
1
-
5
G9
A5
VREF
NA
-
6
H10
B5
6
5
-
-
7
D7
-
VREF
8
E8
K12
B6
5
-
2
2
-
9
F9
NA
-
VREF
10
11
12
13
14
15
C7
G10
D8
-
NA
2
IO_LVDS_DLL
B7
VREF
VREF
C8
H11
E9
4
1
-
2
-
B8
-
VREF
-
VREF
G11
F10
K13
A8
1
-
-
NA
NA
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
137
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E
CG1156 Differential Pin Pair Summary: XCV3200E
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E
CG1156 Differential Pin Pair Summary: XCV3200E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
1
Functions
Pair Bank
Pin
Pin
AO
Functions
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
J19
G20
F20
E20
A21
J20
G19
A20
B20
D20
H20
E21
D21
B21
G21
A22
J21
-
80
81
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
B29
C29
F28
B30
E29
D30
D32
E31
G29
E32
M25
L26
D34
J28
G27
F27
E28
L25
B31
A31
J27
F30
F32
G30
G31
D33
H29
E33
H30
K28
F33
E34
G32
J31
G33
J29
H33
J34
J33
K34
L34
P26
M34
L33
M33
R26
-
1
-
5
1
1
2
-
4
-
82
VREF
VREF
83
-
-
84
-
NA
5
-
85
CS
K20
H21
F21
B22
C22
G22
A23
B23
H22
K22
J22
-
86
DIN, D0
5
-
87
3
1
2
4
2
1
6
-
6
-
88
-
VREF
89
VREF
-
90
-
D22
K21
F22
C23
D23
A24
H23
A25
A26
F24
K23
C26
G24
B27
E26
J24
5
1
1
2
-
91
-
-
92
VREF
-
93
-
-
94
H28
H32
L27
M26
H31
N25
J30
-
-
95
2
3
1
-
VREF
96
-
D24
E24
C25
B26
F25
H24
A27
G25
C27
B28
H25
F26
C28
J25
2
2
-
97
-
-
98
VREF
VREF
99
6
-
-
100
101
102
103
104
105
106
107
108
109
110
111
-
NA
1
-
H34
M27
K29
L29
M28
N27
K33
R25
L31
P27
M31
5
4
2
VREF
VREF
-
1
-
-
4
-
VREF
VREF
-
-
-
2
K24
D27
G26
E27
A30
NA
5
-
D1
-
-
3
1
2
2
5
-
-
-
6
-
H26
VREF
-
Module 4 of 4
138
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DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E
CG1156 Differential Pin Pair Summary: XCV3200E
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E
CG1156 Differential Pin Pair Summary: XCV3200E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
2
Functions
Pair Bank
Pin
Pin
AO
2
Functions
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
N30
N29
T25
P28
N33
N34
R27
P31
T26
R28
N32
R33
T34
T30
R31
U27
T33
T32
U33
U31
V30
V28
W30
Y34
Y33
W28
Y30
W31
Y29
AB34
AB33
Y26
AA31
-
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
AA28 AC34
Y25 AD34
-
1
VREF
2
-
6
-
AB30 AC33
AA26 AC32
AD33 AB28
2
-
P34
P29
P33
R34
N31
P30
R29
R30
T28
-
10
3
-
2
3
1
-
-
-
AE34
AE33 AC30
AA25 AE32
AE31 AD29
AB27
D5
-
9
2
VREF
D3
-
6
-
-
-
AD31
AC28
AC27
AF33
AF31
AF32
VREF
5
4
2
-
2
4
5
-
-
-
T29
-
AE29 AD28
AD30 AG32
AC26 AH33
VREF
T31
VREF
-
U28
U29
V33
V26
W34
W32
V29
W29
W26
Y31
AA34
AA33
W25
Y28
AA30
Y27
-
8
-
2
2
VREF
AD26
AC25 AH32
AE28 AL34
AG30 AD27
AF29 AK34
AD25 AE27
AF30
VREF
-
1
3
2
-
VREF
-
-
-
VREF
-
2
4
5
-
6
1
2
2
2
1
3
-
-
AJ33
AE26
AF28
AJ31
AG29
AH31
AL33
AL32
AF27
AJ32
VREF
-
-
-
-
8
9
1
3
2
-
VREF
VREF
-
-
AK33 AH30
-
-
AK32
AP31
AK31
AK29
INIT
-
-
-
-
AP30 AN31
AH27 AN30
AM30 AK28
2
1
1
-
-
AA27 AA29
AB32 AB29
6
1
VREF
VREF
DS022-4 (v2.1) July 26, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
139
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E
CG1156 Differential Pin Pair Summary: XCV3200E
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E
CG1156 Differential Pin Pair Summary: XCV3200E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
1
Functions
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
AG26 AN29
AF25 AM29
5
-
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
AH20 AK20
-
-
AN19
AF19
AJ20
AP19
1
-
AL29
AE24 AN28
AJ27 AH26
AL28
VREF
NA
-
6
5
-
AM19 AH19
-
-
AJ19
AF18
AJ18
AP18
AP17
AL18
VREF
AG25 AK27
AM28 AF24
5
-
2
2
-
NA
-
VREF
AJ26
AP27
-
AM18 AL17
AH17 AM17
NA
2
IO_LVDS_DLL
AK26 AN27
AE23 AM27
VREF
VREF
4
1
-
AJ17
AP16
AG17
AL16
2
-
AL26
AN26
AP26
AJ25
-
VREF
1
VREF
AJ16 AM16
-
AG24 AP25
AF23 AM26
NA
-
AK16
AL15
AN15
AP14
AK15
AP15
AH16
AF16
AE16
AJ15
NA
1
-
-
-
AJ24
AN25
VREF
1
-
AE22 AM25
AK24 AH23
2
2
-
4
-
-
VREF
AF22
AL24
AP24
AK23
VREF
AH15 AN14
AK14 AG15
AM13 AF15
AG14 AP13
-
-
NA
5
-
AG22 AN23
AP23 AM23
AH22 AP22
2
1
1
5
-
-
-
5
-
-
AE14
AE15
6
-
AL23
AL22
AF21
AJ22
-
AN13 AG13
AH14 AP12
VREF
-
-
AK22 AM22
AG21 AJ21
AP21 AE20
VREF
AJ14
AF13 AN12
AF14 AP11
AL14
5
1
1
2
-
6
5
-
-
-
-
AH21
AN21
AL21
AF20
5
-
AN11 AH13
AM12 AL12
-
NA
-
-
AK21 AP20
AE19 AN20
-
VREF
-
AJ13
AK12 AM10
AP9 AK11
AP10
VREF
2
2
-
-
AG20
AL20
4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E
CG1156 Differential Pin Pair Summary: XCV3200E
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E
CG1156 Differential Pin Pair Summary: XCV3200E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
Functions
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
AL11
AE13
AF12
AL9
AL10
AM9
AP8
AH11
AN8
AG11
AK9
AN7
AJ9
VREF
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
AG4
AF3
AF4
AF2
AE1
AE3
AD1
AD2
AC1
AC2
AC3
AD4
AB6
Y10
AA7
AA1
AB4
Y8
AC9
AE6
AF1
AB10
AC8
AD5
AC7
AD6
AB8
AC5
AA9
AC4
AA8
AB1
AB2
AA4
Y9
6
-
-
-
NA
1
-
7
4
2
VREF
VREF
-
AF11
AM8
AL8
1
-
-
4
-
VREF
VREF
-
AH10
AE12
AM7
AG10
AK8
AP5
AE11
AF10
AL6
-
2
-
NA
5
-
VREF
AL7
-
-
AN6
AH9
AJ8
5
-
3
1
2
4
2
1
6
-
6
-
-
VREF
-
AN5
AM6
AG9
AP4
AJ7
-
-
5
1
1
2
-
-
VREF
VREF
AH8
AN4
AM5
AF8
-
-
-
AA2
AA6
AB3
Y1
-
AK6
AH6
AE9
AD10
AL1
-
AA5
Y7
2
3
1
-
-
-
AK3
AL2
3
1
2
4
2
1
6
-
W10
Y2
-
-
Y5
VREF
AH4
AK1
AK2
AG5
AJ2
VREF
W2
W9
6
-
AG6
AF7
AJ3
-
Y4
W7
-
-
Y6
W1
5
4
2
-
VREF
W3
W6
-
AD9
AC10
AH3
AE8
AE7
AF6
-
W4
V9
-
AH2
AF5
-
V1
W5
VREF
-
2
3
1
-
U2
V7
9
2
AG3
AG2
AG1
-
-
U1
V6
VREF
-
U4
U9
VREF
U5
U7
2
VREF
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E
CG1156 Differential Pin Pair Summary: XCV3200E
Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E
CG1156 Differential Pin Pair Summary: XCV3200E
P
N
Other
P
N
Other
Pair Bank
Pin
Pin
AO
Functions
Pair Bank
Pin
Pin
AO
Functions
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
U6
T6
U3
T3
T9
T5
R6
R2
P1
R8
R9
P4
P8
P6
M1
N6
P9
N7
P10
L1
-
336
337
7
7
7
7
7
7
7
7
F2
L10
H6
E2
D1
J8
J7
F3
E1
G5
K9
E3
E4
F4
-
VREF
6
1
2
4
2
1
3
-
T4
2
4
5
-
338
VREF
R1
T10
R5
P5
P2
N1
R10
N2
P7
N4
N3
M2
M3
M4
N8
N9
K1
L4
-
339
-
-
340
-
-
341
VREF
VREF
342
D2
D3
-
-
1
3
2
-
343
-
Notes:
1. AO in the XCV1000E, XCV2000E, XCV2600E, XCV3200E.
2. AO in the XCV1600E, XCV1000E.
-
-
3. AO in the XCV2000E, XCV2600E, XCV3200E.
4. AO in the XCV1600E
6
1
2
4
2
1
3
-
5. AO in the XCV1000E.
VREF
6. AO in the XCV1600E, XCV2000E, XCV2600E, XCV3200E.
7. AO in the XCV1000E, XCV2600E.
-
8. AO in the XCV1600E, XCV2000E.
-
9. AO in the XCV1000E, XCV1600E, XCV2000E.
10. AO in the XCV1000E, XCV2000E.
-
-
-
L2
-
M7
M8
J1
VREF
2
-
L5
-
K3
J3
J2
VREF
L7
2
4
5
-
H2
K6
G2
K7
J5
M9
J4
-
VREF
L8
-
H3
G3
L9
6
-
VREF
H5
H4
K8
1
3
2
-
-
-
J6
G4
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
12/7/99
1/10/00
Initial Xilinx release.
1.1
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
1/28/00
1.2
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, TBYP values, buffered Hex Line info, p. 8, I/O Timing
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
2/29/00
5/23/00
7/10/00
1.3
1.4
1.5
Updated pinout tables, VCC page 20, and corrected Figure 20.
Correction to table on p. 22.
•
Numerous minor edits.
•
•
Data sheet upgraded to Preliminary.
Preview -8 numbers added to Virtex-E Electrical Characteristics tables.
•
•
Reformatted entire document to follow new style guidelines.
Changed speed grade values in tables on pages 35-37.
8/1/00
1.6
1.7
•
•
Min values added to Virtex-E Electrical Characteristics tables.
9/20/00
XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).
•
•
Corrected user I/O count for XCV100E device in Table 1 (Module 1).
Changed several pins to “No Connect in the XCV100E“ and removed duplicate VCCINT
pins in Table ~ (Module 4).
•
•
•
Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4).
Changed pin J30 to “VREF or I/O option only in the XCV600E” in Table 74 (Module 4).
Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“.
•
Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.
11/20/00
1.8
•
•
•
Updated minimums in Table 13 and added notes to Table 14.
Added to note 2 to Absolute Maximum Ratings.
Changed speed grade -8 numbers for TSHCKO32, TREG, TBCCS, and TICKOF
.
•
Changed all minimum hold times to –0.4 under Global Clock Set-Up and Hold for
LVTTL Standard, with DLL.
•
•
Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters.
Changed GCLK0 to BA22 for FG860 package in Table 46.
Revised footnote for Table 14.
•
•
2/12/01
1.9
Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.
•
•
Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.
Revised Table 62 to include pinout information for the XCV400E and XCV600E devices
in the BG560 package.
•
Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.
DS022-4 (v2.1) July 26, 2001
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Date
Version
Revision
•
•
Updated numerous values in Virtex-E Switching Characteristics tables.
Changed pinout table footnotes from "VREF option only" to "VREF or I/O option only" to
improve clarity.
4/2/01
2.0
•
•
Converted file to modularized format. See the Virtex-E Data Sheet section.
Changed pinout table footnotes from "VREF or I/O option only" to "VREF or I/O option only;
otherwise I/O only" to improve clarity.
7/26/01
2.1
•
Changed designation for pin pair 300 in Table 29 from AO to footnote 9.
Virtex-E Data Sheet
The Virtex-E Data Sheet contains the following modules:
•
DS022-1, Virtex-E 1.8V FPGAs:
Introduction and Ordering Information (Module 1)
•
•
DS022-3, Virtex-E 1.8V FPGAs:
DC and Switching Characteristics (Module 3)
•
DS022-2, Virtex-E 1.8V FPGAs:
DS022-4, Virtex-E 1.8V FPGAs:
Functional Description (Module 2)
Pinout Tables (Module 4)
Module 4 of 4
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Preliminary Product Specification
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