CA0508JPY5V0BN121 [YAGEO]
SURFACE-MOUNT CERAMIC MULTILAYER CAPACITORS;
| 型号： | CA0508JPY5V0BN121 |
| 厂家： | 
YAGEO CORPORATION |
| 描述： | SURFACE-MOUNT CERAMIC MULTILAYER CAPACITORS |
| 文件： | 总17页 (文件大小：985K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SURFACE-MOUNT CERAMIC
MULTILAYER CAPACITORS
C-Array
NP0/X7R/Y5V
16 V TO 50 V
sizes 0508 (4 x 0402) / 0612 (4 x 0603)
RoHS compliant & Halogen Free
Product specification
2
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
ORDERING INFORMATION -GLOBAL PART NUMBER, PHYCOMP
CTC & 12NC
All part numbers are identified by the series, size, tolerance, TC material,
packing style, voltage, process code, termination and capacitance value.
SCOPE
This specification describes
NP0/X7R/Y5V 4-capacitor Array
with lead-free terminations.
Please note that 12 digits ordering code will expire at the end of 2010.
APPLICATIONS
Professional electronics
YAGEO BRAND ordering code
(
)
GLOBAL PART NUMBER PREFERRED
High density consumer
electronics
CA XXXX
X X XXX X B X XXX
(1) (2) (3) (4) (5)
(6) (7)
FEATURES
( )
1 SIZE – INCH BASED (METRIC)
Supplied in tape on reel
Nickel-barrier end termination
0508 (1220)
0612 (1632)
0508 (4x0402) / 0612 (4x0603)
capacitors (of the same
( )
2 TOLERANCE
capacitance value) per array
J = ±5%
Less than 50% board space of
an equivalent discrete
component
K = ±10%
M = ±20%
Z = -20% to +80%
High volumetric efficiency
( )
Increased throughout, by time
3 PACKING STYLE
saved in mounting
RoHS compliant
Halogen Free compliant
R = Paper/PE taping reel; Reel 7 inch
P = Paper/PE taping reel; Reel 13 inch
( )
4 TC MATERIAL
NPO
X5R
X7R
Y5V
( )
5 RATED VOLTAGE
7 = 16 V
8 = 25 V
9 = 50 V
0 =100V
( )
6 PROCESS
N = NP0
B = class 2 material
( )
7 CAPACITANCE VALUE
2 significant digits+number of zeros
The 3rd digit signifies the multiplying factor, and letter R is decimal point
Example: 121 = 12 x 101 = 120 pF
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Nov. 10, 2015 V.4
Product specification
3
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
CONSTRUCTION
The capacitor consists of a rectangular
block of ceramic dielectric in which
a number of interleaved metal
electrodes are contained. This
structure gives rise to a high
capacitance per unit volume.
The inner electrodes are connected
to the two end terminations and
finally covered with a layer of
plated tin (NiSn).
Fig. 1 Simplified outline
The terminations are lead-free.
An outline of the structure is
shown in Fig.1.
DIMENSIONS
OUTLINES
Table 1
TYPE
0508
0612
For dimensions see Table 1
(4 X 0402) (4 X 0603)
L (mm)
2.0 ±0.15
1.25 ±0.15
0.50
3.2 ±0.15
1.60 ±0.15
0.70
W (mm)
Tmin. (mm)
Tmax. (mm)
A (mm)
0.70
0.90
0.28 ±0.10
0.2 ±0.10
0.5 ±0.10
0.4 ±0.10
0.3 ±0.20
0.8 ±0.10
B (mm)
P (mm)
Fig. 2 Surface mounted multilayer ceramic capacitor dimension
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Nov. 10, 2015 V.4
Product specification
4
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
CAPACITANCE RANGE & THICKNESS FOR 4C-ARRAY
Table 2 Temperature characteristic material from NP0
0508 (4 x 0402)
50 V
0612 (4 x 0603)
50 V
CAPACITANCE
100V
100V
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
10 pF
15 pF
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
18 pF
22 pF
33 pF
39 pF
47 pF
56 pF
68 pF
82 pF
100 pF
120 pF
150 pF
180 pF
220 pF
270 pF
330 pF
390 pF
470 pF
560 pF
680 pF
820 pF
1.0 nF
NOTE
Values in shaded cells indicate thickness class in mm
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Nov. 10, 2015 V.4
Product specification
5
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
CAPACITANCE RANGE & THICKNESS FOR 4C-ARRAY
Table 3 Temperature characteristic material from X7R
0508 (4 x 0402)
16 V
0612 (4 x 0603)
CAPACITANCE
25 V
50 V
16 V
25 V
50 V
100V
0.6±0.1
1.0 nF
1.2 nF
1.5 nF
1.8 nF
2.2 nF
2.7 nF
3.3 nF
3.9 nF
4.7 nF
5.6 nF
6.8 nF
8.2 nF
10 nF
12 nF
15 nF
18 nF
22 nF
27 nF
33 nF
47 nF
56 nF
68 nF
82 nF
100 nF
220 nF
470 nF
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.6±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.85±0.1
0.85±0.1
0.85±0.1
0.85±0.1
0.85±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
0.8±0.1
NOTE
Values in shaded cells indicate thickness class in mm
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Nov. 10, 2015 V.4
Product specification
6
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
CAPACITANCE RANGE & THICKNESS FOR 4C-ARRAY
Table 4 Temperature characteristic material from Y5V
0612 (4 x 0603)
25 V
CAPACITANCE
10 nF
22 nF
0.6±0.1
47 nF
100 nF
NOTE
Values in shaded cells indicate thickness class in mm
THICKNESS CLASSES AND PACKING QUANTITY
Table 5
Ø 180 MM / 13 INCH
Paper
Ø 180 MM / 7 INCH
Paper
SIZE
THICKNESS
TAPE WIDTH QUANTITY
PER REEL
CODE
CLASSIFICATION
20,000
15,000
0508
0612
0.6 ±0.1 mm
0.8 ±0.1 mm
8 mm
8 mm
4,000
4,000
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Nov. 10, 2015 V.4
Product specification
7
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
ELECTRICAL CHARACTERISTICS
4C-ARRAY DIELECTRIC CAPACITORS; NISN TERMINATIONS
Unless otherwise stated all electrical values apply at an ambient temperature of 20±1 °C, an atmospheric
pressure of 86 to 106 kPa, and a relative humidity of 63 to 67%.
Table 6
VALUE
DESCRIPTION
Capacitance range
Rated voltage
10 pF to 100 nF
NP0
X7R
Y5V
50 V
16 V to 50 V
0612: 25 V
Capacitance tolerance
Dissipation factor (D.F.)
NP0
X7R
Y5V
±5%, ±10%
±10%, ±20%
–20% to +80%
NP0
X7R
Y5V
≤ 0.1%
16 V ≤ 3.5%, 25V ≤ 2.5%, 50V ≤ 2.5%
0508/12nF~100nF/16V, Df ≤5%
0508 ≤ 9%, 0612 ≤ 7%
Insulation resistance after 1 minute at Ur (DC)
Rins ≥ 10 GΩ or Rins × Cr ≥ 500 seconds whichever is less
Maximum capacitance change as a function of temperature
(temperature characteristic/coefficient):
NP0
X7R
Y5V
±30 ppm/°C
±15%
+22% to –82%
Operating temperature range:
NP0
X7R
Y5V
–55 °C to +125 °C
–55 °C to +125 °C
–30 °C to +85 °C
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Nov. 10, 2015 V.4
Product specification
8
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
NP0 0508/0612 50 V
Sample limits (broken lines)
Requirement levels (dotted lines)
Fig. 3 Typical temperature coefficient as a function of
Fig. 4 Typical tan δ as a function of temperature
temperature
Fig. 5 Typical capacitance change with respect to the
capacitance at 1 V as a function of DC voltage
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Nov. 10, 2015 V.4
Product specification
9
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
X7R 0508 16 V
Fig. 6 Typical capacitance change with respect to the
capacitance at 1 V as a function of DC voltage
at 20 °C
Fig. 7 Typical tan δ as a function of temperature
Fig. 8 Typical capacitance change as a function of
temperature
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Nov. 10, 2015 V.4
Product specification
10
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
X7R 0612 16 V to 50 V
Curve 1 = 16 V product
Curve 2 = 25 V product
Curve 3 = 50 V product
Curve 1 = 16 V product
Curve 2 = 25 V product
Curve 3 = 50 V product
Fig. 9 Typical capacitance change with respect to the
capacitance at 1 V as a function of DC voltage
at 25 °C
Fig. 10 Typical tan δ as a function of temperature
Fig. 11 Typical capacitance change as a function of
temperature
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Nov. 10, 2015 V.4
Product specification
11
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
Y5V 0612 25 V
Fig. 12 Typical capacitance change with respect to the
capacitance at 1 V as a function of DC voltage
at 25 °C
Fig. 13 Typical tan δ as a function of temperature
Fig. 14 Typical capacitance change as a function of
temperature
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Nov. 10, 2015 V.4
Product specification
12
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
TESTS AND REQUIREMENTS
Table 7 Test procedures and requirements
TEST TEST METHOD PROCEDURE
REQUIREMENTS
No visible damage
IEC 60384- 4.3
21/22
The capacitors may be mounted on printed-circuit boards or
ceramic substrates
Mounting
4.4
Any applicable method using × 10 magnification
In accordance with specification
Within specified tolerance
Visual
Inspection and
Dimension
Check
4.5.1 Class 1:
Capacitance
f = 1 MHz for C ≤ 1 nF, measuring at voltage 1 Vrms at 20 °C
f = 1 KHz for C > 1 nF, measuring at voltage 1 Vrms at 20 °C
Class 2:
f = 1 KHz for C ≤ 10 µF, measuring at voltage 1 Vrms at 20 °C
f = 120 Hz for C >10 µF, measuring at voltage 0.5 Vrms at 20 °C
4.5.2 Class 1:
In accordance with specification
Dissipation
f = 1 MHz for C ≤ 1 nF , measuring at voltage 1 Vrms at 20 °C
Factor (D.F.)
f = 1 KHz for C > 1 nF, measuring at voltage 1 Vrms at 20 °C
Class 2:
f = 1 KHz for C ≤ 10 µF, measuring at voltage 1 Vrms at 20 °C
f = 120 Hz for C > 10 µF, measuring at voltage 0.5 Vrms at 20 °C
4.5.3
At Ur (DC) for 1 minute
In accordance with specification
Insulation
Resistance
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Nov. 10, 2015 V.4
Product specification
13
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
TEST
TEST METHOD PROCEDURE
REQUIREMENTS
4.6
Capacitance shall be measured by the steps shown in the following Class1: Δ C/C: ±30ppm
Temperature
Coefficient
table.
Class2: X7R: Δ C/C: ±15%
The capacitance change should be measured after 5 min at each
specified temperature stage.
Y5V: Δ C/C: 22~-82%
Step
Temperature(℃)
25±2
a
b
c
Lower temperature±3℃
25±2
d
Upper Temperature± 2℃
25±2
e
(1) Class I
Temperature Coefficient shall be calculated from the formula as
below
C2 - C1
Temp, Coefficient =
106 [ppm/℃]
C1xΔT
C1: Capacitance at step c
C2: Capacitance at 125℃
∆T: 100℃(=125℃-25℃)
(2) Class II
Capacitance Change shall be calculated from the formula as below
C2 - C1
∆C =
x 100%
C1
C1: Capacitance at step c
C2: Capacitance at step b or d
4.7
A force applied for 10 seconds to the line joining the terminations Force
and in a plane parallel to the substrate
size ≥ 0603: 5N
Adhesion
size = 0402: 2.5N
size = 0201: 1N
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Nov. 10, 2015 V.4
Product specification
14
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
TEST
TEST METHOD PROCEDURE
REQUIREMENTS
IEC 60384- 4.8
21/22
Mounting in accordance with IEC 60384-22
paragraph 4.3
No visible damage
Bond
Strength of
Plating on
End Face
Conditions: bending 1 mm at a rate of 1 mm/s,
radius jig 5 mm
Δ C/C Class 1:
NP0: within ±1% or 0.5 pF, whichever is greater
Class2:
X5R/X7R/Y5V: ±10%
4.9
Precondition: 150 +0/–10 °C for 1 hour, then
keep for 24 ±1 hours at room temperature
Dissolution of the end face plating shall not
exceed 25% of the length of the edge
concerned
Resistance to
Soldering
Heat
Preheating: for size ≤ 1206: 120 °C to 150 °C for
1 minute
Δ C/C Class 1:
NP0: within ±0.5% or 0.5 pF, whichever is
greater
Preheating: for size >1206: 100 °C to 120 °C for
1 minute and 170 °C to 200 °C for 1 minute
Solder bath temperature: 260 ±5 °C
Dipping time: 10 ±0.5 seconds
Recovery time: 24 ±2 hours
Class2:
X5R/X7R: ±10% Y5V: ±20%
D.F. within initial specified value
Rins within initial specified value
4.10
Preheated the temperature of 80 °C to 140 °C
and maintained for 30 seconds to 60 seconds.
The solder should cover over 95% of the critical
area of each termination
Solderability
Test conditions for lead containing solder alloy
Temperature: 235 ±5 °C
Dipping time: 2 ±0.2 seconds
Depth of immersion: 10 mm
Alloy Composition: 60/40 Sn/Pb
Number of immersions: 1
Test conditions for leadfree containing solder alloy
Temperature: 245 ±5 °C
Dipping time: 3 ±0.3 seconds
Depth of immersion: 10 mm
Alloy Composition: SAC305
Number of immersions: 1
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Nov. 10, 2015 V.4
Product specification
15
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
TEST
TEST METHOD PROCEDURE
REQUIREMENTS
IEC 60384- 4.11
21/22
Preconditioning;
150 +0/–10 °C for 1 hour, then keep for
24 ±1 hours at room temperature
No visual damage
Rapid Change
of
Temperature
Δ C/C Class 1:
NP0: within ±1% or 1 pF, whichever is greater
5 cycles with following detail:
30 minutes at lower category temperature
30 minutes at upper category temperature
Class2:
X5R/X7R: ±15% Y5V: ±20%
D.F. meet initial specified value
Rins meet initial specified value
Recovery time 24 ±2 hours
4.13
No visual damage after recovery
Damp Heat
with Ur Load
1. Preconditioning, class 2 only:
150 +0/-10 °C /1 hour, then keep for
24 ±1 hour at room temp
∆C/C
2. Initial measure:
Class 1:
Spec: refer initial spec C, D, IR
NP0: within ±2% or 1 pF, whichever is greater
Class2:
3. Damp heat test:
500 ±12 hours at 40 ±2 °C;
90 to 95% R.H. 1.0 Ur applied
X5R/X7R: ±15%; Y5V: ±30%
D.F.
4. Recovery:
Class 1: 6 to 24 hours
Class 2: 24 ±2 hours
Class 1: NP0: ≤ 2 x specified value
Class2:
X5R/X7R: ≤ 16V: ≤ 7%
≥ 25V: ≤ 5%
Y5V: ≤ 15%
5. Final measure: C, D, IR
P.S. If the capacitance value is less than the
minimum value permitted, then after the
other measurements have been made the
capacitor shall be precondition according to
“IEC 60384 4.1” and then the requirement
shall be met.
Rins
Class 1:
NP0: ≥ 2,500 MΩ or Rins x Cr ≥ 25s whichever is less
Class2:
X5R/X7R/Y5V: ≥ 500 MΩ or Rins x Cr ≥ 25s
whichever is less
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Nov. 10, 2015 V.4
Product specification
16
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
TEST
TEST METHOD
PROCEDURE
REQUIREMENTS
IEC 60384- 4.14
21/22
No visual damage
Endurance
1. Preconditioning, class 2 only:
150 +0/-10 °C /1 hour, then keep for
24 ±1 hour at room temp
<General purpose series>
∆C/C
2. Initial measure:
Class1:
Spec: refer initial spec C, D, IR
NP0: within ±2% or 1 pF, whichever is greater
Class2:
3. Endurance test:
Temperature: NP0/X7R: 125 °C
X5R/Y5V: 85 °C
X5R/X7R: ±15%; Y5V: ±30%
Specified stress voltage applied for 1,000 hours:
Applied 2.0 x Ur for general product.
D.F.
Class1:
4. Recovery time: 24 ±2 hours
5. Final measure: C, D, IR
NP0: ≤ 2 x specified value
Class2:
X5R/X7R: ≤ 16V: ≤ 7%
≥ 25V: ≤ 5%
P.S. If the capacitance value is less than the
minimum value permitted, then after the other
measurements have been made the capacitor shall
be precondition according to “IEC 60384 4.1” and
then the requirement shall be met.
Y5V: ≤ 15%
Rins
Class1:
NP0: ≥ 4,000 MΩ or
Rins x Cr ≥ 40s whichever is less
Class2:
X5R/X7R/Y5V: ≥ 1,000 MΩ or
Rins x Cr ≥ 50s whichever is less
IEC 60384-1 4.6
Specified stress voltage applied for 1 minute
No breakdown or flashover
Voltage Proof
Ur ≤ 100 V: series applied 2.5 Ur
100 V < Ur ≤ 200 V series applied (1.5 Ur + 100)
200 V < Ur ≤ 500 V series applied (1.3 Ur + 100)
Ur > 500 V: 1.3 Ur
I: 7.5 mA
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Nov. 10, 2015 V.4
Product specification
17
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
REVISION HISTORY
REVISION DATE
CHANGE NOTIFICATION DESCRIPTION
Version 4
Version 3
Version 2
Version 1
Version 0
Nov. 10, 2015
-
-
-
-
-
- Product range updated
May 21, 2014
Jun. 17, 2013
Feb 05, 2010
Jun 22, 2009
- Product range updated
- Product range updated
- The statement of "Halogen Free" on the cover added
- New datasheet for 4C-Array series with RoHS compliant
- Replace from pdf files: 0508_16V to 50V_1, 0612_16V to 50V_0,
C-Array_NP0_50V_0508_7, C-Array_NP0_50V_0612_7,
C-Array_X7R_16V_25V_50V_0612_6, C-Array_X7R_16V_0508_5,
C-Array_Y5V_25V_0508_0, C-Array_Y5V_25V_0612_5
- Define global part number
- Description of "Halogen Free compliant" added
- Test method and procedure updated
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Nov. 10, 2015 V.4
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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