YSS920B-SZ [YAMAHA]
Consumer Circuit, CMOS, CQFP100, CERAMIC, LEAD-FREE , SQFP-100;
| 型号： | YSS920B-SZ |
| 厂家： | 
YAMAHA CORPORATION |
| 描述： | Consumer Circuit, CMOS, CQFP100, CERAMIC, LEAD-FREE , SQFP-100 |
| 文件： | 总28页 (文件大小：993K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
YSS920B
EVE
32-bit DSP Engine for Various sound Effects
Outline
YSS920B is a 32-bit digital signal processor exclusively designed for sound field processing. As a
post-processing DSP after surround sound decoding, YSS920B can process various sound fields such as
various simulation surround and virtual surround through user programs, which can provide wide
variation of sound field effects on audio equipments.
Features
YSS920B has following features:
• Basic compatibility with the SubDSP section of YSS922/932 for DSP program
• High precision processing by 32-bit floating-point operation
• Capability to process various sound effects by downloading external programs to the built-in RAM
• 16 channels processing capability (input: 16ch, output: 16ch)
• Zero data detecting function on each channel
• 32-bit data transmission ability between multiple YSS920Bs
• Connectability to most types of ADC, DAC and DIR through control register setting
• Built-in delay memory with 32 bits × 1024 words (Max. 21.3 ms at fs = 48 kHz)
• Ability to execute up to 2.73 seconds delay (at fs = 48 kHz) when connected with an external DRAM or
SRAM
• Support for sampling frequencies from 32 kHz to 192 kHz
• DSP section specifications
Internal operating frequency: 30.72 to 50.00 MHz
Data bus width: 32 bits
MAC: 32 bits (floating-point) × 16 bits (fixed-point) + 49 bits → 49 bits
Program RAM: 50 bits × 1024 words
Coefficient RAM: 16 bits × 1024 words
• Ability to use up to 20 general-purpose input/output terminals
• Power supply voltage: 2.5 V (for internal and PLL circuits), 3.3 V (for I/O)
• Si-gate CMOS process
• Lead-free 100-pin SQFP package:YSS920B-SZ
YSS920B CATALOG
CATALOG No.: LSI-4SS920B20
2006.2
YSS920B
Application
Sound field processing for AV amplifiers and audio mixers such as:
1) Simulation surrounds for Hall, Theater, Church, Stadium, Disco, Jazz, and Live
2) Virtual surround
3) Bass Management
4) Filtering process for LPF, HPF, equalizer, etc.
5) Fader and Level meters
6) Generating white noise, pink noise, sine waves, etc.
Difference between YSS920B and YSS920
The principal differences are as follows. Please sufficiently check that no problem occurs in your
product when you replace YSS920 by YSS920B.
Item
YSS920B
YSS920
1
2
3
4
Internal operating frequency
Power consumption (VDD1)
30.72 to 50.00MHz
30.72 to 40.96MHz
30mW (typ) / 45mW(max)
80mW (typ) / 115mW (max)
Undefined
45mW (typ) / 65mW (max)
Power consumption (VDD2/AVDD) 120mW (typ) / 145mW (max)
Power supply start-up order) Defined (see p18 Power-on)
2
YSS920B
Block Diagram
3
YSS920B
Pin Configuration
VSS
XO
XI
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD2
RAMA10
RAMA9
RAMA3
RAMA4
RAMA2
RAMA5
VDD1
RAMA1
RAMA6
RAMA0
RAMA7
RAMA8
RASN
RAMOEN
RAMWEN
CASN
RAMD15
RAMD14
RAMD13
VDD1
IOPORT0
IOPORT1
IOPORT2
IOPORT3
IOPORT4
IOPORT5
IOPORT6
IOPORT7
AVSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CPO
AVDD
VDD1
(NC)
IOPORT8
IOPORT9
IOPORT10
IOPORT11
IOPORT12
IOPORT13
IOPORT14
IOPORT15
VDD2
RAMD12
RAMD11
RAMD10
VSS
< 100-pin SQFP top view >
4
YSS920B
Pin Function
No.
Name
I/O
Functions
1
2
3
4
VSS
XO
XI
-
O
I
Digital ground pin
Crystal oscillator connecting pin
Crystal oscillator connecting pin (12.288 to 15.000 MHz)
IOPORT0 I+/O General-purpose input/output pin / SDO 0 Lch zero-flag output pin / Program branch condition
input/output pin
5
6
7
8
9
IOPORT1 I+/O General-purpose input/output pin / SDO 0 Rch zero-flag output pin / Program branch condition
input/output pin
IOPORT2 I+/O General-purpose input/output pin / SDO 1 Lch zero-flag output pin / Program branch condition
input/output pin
IOPORT3 I+/O General-purpose input/output pin / SDO 1 Rch zero-flag output pin / Program branch condition
input/output pin
IOPORT4 I+/O General-purpose input/output pin / SDO 2 Lch zero-flag output pin / Program branch condition
input/output pin
IOPORT5 I+/O General-purpose input/output pin / SDO 2 Rch zero-flag output pin / Program branch condition
input/output pin
10 IOPORT6 I+/O General-purpose input/output pin / SDO 3 Lch zero-flag output pin / Program branch condition
input/output pin
11 IOPORT7 I+/O General-purpose input/output pin / SDO 3 Rch zero-flag output pin / Program branch condition
input/output pin
12
13
14
15
16
AVSS
CPO
AVDD
VDD1
(NC)
-
A
-
-
-
Analog ground pin (for PLL)
PLL filter connection pin
+2.5 V analog power supply pin (for PLL)
+3.3 V digital power supply pin (for input/output pin)
(No connection)
17 IOPORT8 I+/O General-purpose input/output pin / SDO 4 Lch zero-flag output pin
18 IOPORT9 I+/O General-purpose input/output pin / SDO 4 Rch zero-flag output pin
19 IOPORT10 I+/O General-purpose input/output pin / SDO 5 Lch zero-flag output pin
20 IOPORT11 I+/O General-purpose input/output pin / SDO 5 Rch zero-flag output pin
21 IOPORT12 I+/O General-purpose input/output pin / SDO 6 Lch zero-flag output pin / Chip address setting input pin 0
22 IOPORT13 I+/O General-purpose input/output pin / SDO 6 Rch zero-flag output pin / Chip address setting input pin 1
23 IOPORT14 I+/O General-purpose input/output pin / SDO 7 Lch zero-flag output pin / Chip address setting input pin 2
24 IOPORT15 I+/O General-purpose input/output pin / SDO 7 Rch zero-flag output pin / Chip address setting input pin 3
25
26
27
28
29
30
31
32
33
34
VDD2
VSS
-
-
+2.5 V digital power supply pin (for internal circuits)
Digital ground pin
PCM output pin
PCM output pin
PCM output pin
PCM output pin
PCM output pin
PCM output pin
PCM output pin
SDO0
SDO1
SDO2
SDO3
SDO4
SDO5
SDO6
SDO7
O
O
O
O
O
O
O
O
PCM output pin
35 IOPORT16 I+/O General-purpose input/output pin / Overflow detection output pin
36 IOPORT17 I+/O General-purpose input/output pin / Program end detection output pin
37 IOPORT18 I+/O General-purpose input/output pin / 64fs clock output pin
38 IOPORT19 I+/O General-purpose input/output pin / fs clock output pin
39
40
41
42
43
44
45
46
47
48
49
VDD1
-
+3.3 V digital power supply pin (for input/output pin)
RAMD0 I+/O Data input/output pin for external memory 0
RAMD1 I+/O Data input/output pin for external memory 1
RAMD2 I+/O Data input/output pin for external memory 2
RAMD3 I+/O Data input/output pin for external memory 3
RAMD4 I+/O Data input/output pin for external memory 4
RAMD5 I+/O Data input/output pin for external memory 5
RAMD6 I+/O Data input/output pin for external memory 6
RAMD7 I+/O Data input/output pin for external memory 7
RAMD8 I+/O Data input/output pin for external memory 8
RAMD9 I+/O Data input/output pin for external memory 9
5
YSS920B
50
51
VDD2
VSS
-
-
+2.5 V digital power supply pin (for internal circuit)
Digital ground pin
52 RAMD10 I+/O Data input/output pin for external memory 10
53 RAMD11 I+/O Data input/output pin for external memory 11
54 RAMD12 I+/O Data input/output pin for external memory 12
55
VDD1
-
+3.3 V digital power supply pin (for input/output pin)
56 RAMD13 I+/O Data input/output pin for external memory 13
57 RAMD14 I+/O Data input/output pin for external memory 14
58 RAMD15 I+/O Data input/output pin for external memory 15
59
CASN
O
O
O
O
O
O
O
O
O
-
O
O
O
O
O
O
-
Column-address strobe output pin for external DRAM
Write enable output pin for external memory
Output-enable output pin for external memory
Row address strobe output pin for external DRAM
Address output pin for external memory 8
Address output pin for external memory 7
Address output pin for external memory 0
Address output pin for external memory 6
Address output pin for external memory 1
+3.3 V digital power supply pin (for input/output pin)
Address output pin for external memory 5
Address output pin for external memory 2
Address output pin for external memory 4
Address output pin for external memory 3
Address output pin for external memory 9
Address output pin for external memory 10
+2.5 V digital power supply pin (for internal circuit)
Digital ground pin
60 RAMWEN
61 RAMOEN
62
63
64
65
66
67
68
69
70
71
72
73
RASN
RAMA8
RAMA7
RAMA0
RAMA6
RAMA1
VDD1
RAMA5
RAMA2
RAMA4
RAMA3
RAMA9
74 RAMA10
75
76
VDD2
VSS
-
77 RAMA11
78 RAMA12
79 RAMA13
80 RAMA14
81 RAMA15
82 RAMA16
83 RAMA17
O
O
O
O
O
O
O
-
Address output pin for external memory 11
Address output pin for external memory 12
Address output pin for external memory 13
Address output pin for external memory 14
Address output pin for external memory 15
Address output pin for external memory 16
Address output pin for external memory 17
+3.3 V digital power supply pin (for input/output pin)
Microcomputer interface Chip select input pin
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VDD1
/CS
SO
SI
SCK
Is
Ot Microcomputer interface Data output pin
Is
Is
Is
I
Is
I
I
I
I
I
Microcomputer interface Data input pin
Microcomputer interface Clock input pin
Initial clear input pin
Word clock (fs) input pin for SDI/SDO interface
Bit clock (64fs) input pin for SDI/SDO interface
PCM input pin
PCM input pin
PCM input pin
PCM input pin
PCM input pin
/IC
SDWCK
SDBCK
SDI7
SDI6
SDI5
SDI4
SDI3
SDI2
SDI1
SDI0
VDD2
I
I
I
-
PCM input pin
PCM input pin
PCM input pin
+2.5 V digital power supply pin (for internal circuit)
I: Input terminal
Is: Schmitt trigger input terminal
I+: Input terminal with pull-up resistor
0: Digital output terminal
0t: 3-state digital output terminal
A: Analog terminal
6
YSS920B
Pin Description
1) Serial data interface
z
SDI7-0
PCM data input pin for this LSI. Up to 16 channels of PCM data can be input.
Connect unused pins to VSS.
Select the input format by setting the SDI register.
z
SDO7-0
Output pin for the PCM signal processed by the DSP. Up to 16 channels of PCM data can be output.
Select the output format by setting the SDO register.
z
SDBCK and SDWCK
Clock input pins for SDI input and SDO output.
Input clock signals at 64fs to SDBCK and fs to SDWCK.
See “■ Format for serial data interface” for the format.
2) External memory interface
z
RAMA17-0, RAMD15-0, RAMWEN, RAMOEN, CASN, and RASN
Pins for connecting the external memory for data delay.
See “RAM interface” in “ 4) AC characteristics” for the access timing.
3) Microprocessor interface
z
/CS, SCK, SI, and SO
4-line serial interfaces for reading/writing of the control register and for program downloading.
See “■ Microprocessor interface format” for the format.
4) General-purpose input/output pins
z
IOPORT19-0
IOPORT0 to IOPORT19 can be used as general-purpose input/output ports.
Select whether to use the pins as input pins (IPORT) or output pins (OPORT) by setting IOSEL 19-0 bits
of the IOSEL registers (IOSEL_H, IOSEL_M, and IOSEL_L).
If setup as an output pin (OPORT), you can select whether to output the value set to registers (OPORT_H,
OPORT_M, and OPORT_L) or output various status signals by setting OPSEL 19-0 bits of registers
(OPSEL_H, OPSEL_M, and OPSEL_L).
Functions of the IOPORT pins can be set as follows:
7
YSS920B
IOSEL
setting
OPSEL
setting
Bit position
11-0
IOPORT function
Remarks
General input
(IPORT)
IOPORT7-0 can be used for the conditional
branching of DSP programs. See Note 4).
0
--
General input
(IPORT)
Combined use with chip address setting
terminal. See Note 1).
0
0
1
15-12
19-16
--
--
0
General input
(IPORT)
General output
(OPORT)
IOPORT7-0 can be used for the conditional
branching of DSP programs. See Note 4).
11-0
1
1
1
1
1
1
0
1
0
1
Zero detection output See Note 2)
General output
(OPORT)
15-12
19-16
Zero detection output See Note 2)
General output
(OPORT)
Status output
See Note 3)
Note 1) Pins for chip address setting (IOPORT 15-12)
These pins are also used as chip address setting pins:
IOPORT 12-----chip address 0 (CA0)
IOPORT 13-----chip address 1 (CA1)
IOPORT 14-----chip address 2 (CA2)
IOPORT 15-----chip address 3 (CA3)
Note 2) ZEROF output pins (IOPORT 15-0)
By setting the IOSEL and the OPSEL, IOPORT 15-0 operate as digital zero detection pins for SDO
output signal.
If the SD0 output signal remains at digital zero consecutively for the number of samples specified by the
ZEROB register, the flag output pin of the corresponding channel is set to H. This flag output pin can be
used for analog mute after DAC.
The channels correspond to the pins as follows:
IOPORT0 -----
IOPORT1 -----
IOPORT2 -----
IOPORT3 -----
IOPORT4 -----
IOPORT5 -----
IOPORT6 -----
IOPORT7 -----
IOPORT8 -----
IOPORT9 -----
IOPORT10-----
IOPORT11-----
IOPORT12-----
IOPORT13-----
IOPORT14-----
IOPORT15-----
ZEROF0L (SDO0 Lch)
ZEROF0R (SDO0 Rch)
ZEROF1L (SDO1 Lch)
ZEROF1R (SDO1 Rch)
ZEROF2L (SDO2 Lch)
ZEROF2R (SDO2 Rch)
ZEROF3L (SDO3 Lch)
ZEROF3R (SDO3 Rch)
ZEROF4L (SDO4 Lch)
ZEROF4R (SDO4 Rch)
ZEROF5L (SDO5 Lch)
ZEROF5R (SDO5 Rch)
ZEROF6L (SDO6 Lch)
ZEROF6R (SDO6 Rch)
ZEROF7L (SDO7 Lch)
ZEROF7R (SDO7 Rch)
8
YSS920B
Note 3) Various status signal output pins
By setting the IOSEL and the OPSEL, the following status signals will be output from each pin:
IOPORT16-----
IOPORT17-----
IOPORT18-----
IOPORT19-----
OVF
END
SDBCKO (64fs clock)
SDWCKO (fs clock)
OVF
END
If overflow occurs in the operation result of the DSP, OVF is set to H.
The H interval is from the occurrence of the overflow to the output start of the next PCM
sample from the SDO interface. When the next PCM sample output starts, OVF is reset to L.
This pin is used for DSP programming and debugging.
END is set to H when the DSP program counter is active. It is set to L when all processes
have been finished and the program counter stops. When the program is operating correctly,
the pin is always set to L once per sample. If it is not, this indicates that the program has not
finished correctly to the end. This pin is used for DSP programming and debugging.
SDBCKO This pin outputs 64fs clock synchronized to the SDO output signal. This clock can be used as
a 64fs clock for the devices in subsequent stages. The polarity of the SDBCKO clock can be
selected by setting BCKOP of the SDO register.
SDWCKO This pin outputs fs clock synchronized to the SDO output signal. This clock can be used as an
fs clock for the devices in subsequent stages. The polarity of the SDWCKO clock can be
selected by setting WCKOP of the SDO register.
Each pin of IOPORT 19-0 is pulled up with 80-kΩ (Typ) resistors. The structure of the LSI is shown below:
Structure of the LSI
IPORT
IOPORT
OPORT
Zero detection
or status signal
IOSEL
Note 4) When the pins are set to input mode, set a branch condition directly to each pin.
When the pins are set to output mode, IOPORT output can be used as the branch condition.
9
YSS920B
5) Clock
z
XI and XO
Pins for connecting a crystal oscillator (12.288 to 15.000 MHz). Use a crystal oscillator with a fundamental
wave.
If an external clock is used, connect it to XI.
Internal operation clock (ck) is set with the oscillating frequency of this crystal oscillator and the setting of
the CKUP bit of the ERAM register.
CKUP=0
CKUP=1
I=12.288 MHz CK=30.72 MHz CK=40.96 MHz
:
:
:
XI=14.000 MHz CK=35.00 MHz CK=46.66MHz
:
:
－
XI=15.000 MHz CK=37.50 MHz CK=50.00MHz
z
CPO, AVDD, and AVSS
Pins for connecting external elements for the PLL used to generate a clock pulse in the DSP section.
Connect resistor and capacitors near the CPO as shown below.
Connect decoupling capacitors near the pin between AVDD and AVSS.
+2.5 V
1 kΩ
+
470 pF
4700 pF
0.1 µF
10 µF
10
YSS920B
Register map
This LSI is controlled by reading/writing the registers below through the microcomputer interface (/CS, SCK,
SI, and SO).
See “■ Microprocessor interface format” for the microcomputer interface format.
All the registers except addresses 0x13 and 0x14 are reset to 0 when initial clear (/IC=L) is executed. The
initial values of addresses 0x13 and 0x14 are undefined.
Name
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
CHIP ADR
SDI
CAE
CA3-0
NOEXP
SDIFMT1-0
SDOFMT1-0
SDIBIT1-0
SDOBIT1-0
RASREF
SDWP
SDBP
SDO
WCKOP
BCKOP
ERAM
CKUP
ERAMSEL1-0
ERAMMOD
IOSEL_H
IOSEL_M
IOSEL_L
OPSEL_H
OPSEL_M
OPSEL_L
OPORT_H
OPORT_M
OPORT_L
IPORT_H
IPORT_M
IPORT_L
IOSEL19-16
IOSEL15-8
IOSEL7-0
OPSEL19-16
OPORT19-16
IPORT19-16
MPCNT11-8
OPSEL15-8
OPSEL7-0
OPORT15-8
OPORT7-0
IPORT15-8
IPORT7-0
MPCNT_H MPLOAD
MPCNT_L
MPCLEARN DSPMUTEN
MPCNT7-0
ZEROB7-0
ZEROB
ZEROF_H
ZEROF_L
MI STATE
ZEROF7R ZEROF7L ZEROF6R ZEROF6L ZEROF5R ZEROF5L ZEROF4R ZEROF4L
ZEROF3R ZEROF3L ZEROF2R ZEROF2L ZEROF1R ZEROF1L ZEROF0R ZEROF0L
MI7S
MI6S
MI5S
MI4S
MI3S
MI2S
MI1S
MI0S
0x16
0x17
TEST
TEST
0x18
:
Invalid
Output of SO pin becomes High-Z.
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
MI00
MI01
MI02
MI03
MI10
MI11
MI12
MI13
MI20
MI21
MI22
MI23
MI30
MI31
MI32
MI33
MI40
MI41
MI0REG31-24
MI0REG23-16
MI0REG15-8
MI0REG7-0
MI1REG31-24
MI1REG23-16
MI1REG15-8
MI1REG7-0
MI2REG31-24
MI2REG23-16
MI2REG15-8
MI2REG7-0
MI3REG31-24
MI3REG23-16
MI3REG15-8
MI3REG7-0
MI4REG31-24
MI4REG23-16
11
YSS920B
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
MI42
MI43
MI50
MI51
MI52
MI53
MI60
MI61
MI62
MI63
MI70
MI71
MI72
MI73
MI4REG15-8
MI4REG7-0
MI5REG31-24
MI5REG23-16
MI5REG15-8
MI5REG7-0
MI6REG31-24
MI6REG23-16
MI6REG15-8
MI6REG7-0
MI7REG31-24
MI7REG23-16
MI7REG15-8
MI7REG7-0
0x40
:
Invalid
Output of SO pin becomes High-Z.
0x7E
0x7F
DEVICE ID
0
0
0
0
0
0
1
0
Note
i)
Do not write ‘1’ in the shaded area in the above table, because test bits are allocated.
ii) Do not access addresses 0x16 and 0x17 because they are test registers.
12
YSS920B
Format for serial data interface
Input/output of PCM signals are performed through:
・ SDI interface, and
・ SDO interface.
1) SDI interface: (Serial data input)
The input format of serial data is as follows in accordance with the setting of the SDI register.
Regardless of the setting, the input signal to the SDI7-0 pins is processed as 32-bit data consisting of 28-bit
mantissa and 4-bit exponent.
1 Frame
Lch
Rch
SDWP=0
SDWP=1
SDWCK
SDBCK
SDBP=0
SDBP=1
No Delay
Lch
Rch
SDIFMT1-0=00
SDIBIT1-0=XX
M
LM
LM
LM
L
Mantissa
Exponent
Mantissa
Exponent
1bit Delay
Lch
Rch
SDIFMT1-0=10
SDIBIT1-0=XX
LM
LM
LM
LM
L
EIAJ
Lch
Rch
Rch
SDI7
│
SDIFMT1-0=01
SDIBIT1-0=00
LM
LM
LM
LM
16 bits
16 bits
SDI0
Rch
Lch
Rch
SDIFMT1-0=01
SDIBIT1-0=01
LM
LM
LM
LM
18 bits
18 bits
Rch
Lch
Rch
SDIFMT1-0=01
SDIBIT1-0=10
LM
LM
LM
LM
LM
LM
20 bits
20 bits
Rch
Lch
Rch
SDIFMT1-0=01
SDIBIT1-0=11
LM
LM
24 bits
24 bits
M : MSB L : LSB
13
YSS920B
2) SDO interface: (Serial data output)
The output format of serial data is as follows in accordance with the setting of the SDO register.
Regardless of the setting, 32-bit data consisting of 28-bit mantissa and 4-bit exponent is always output from
the SDO7-0 pins.
When passing the SDO7-0 output to other devices such as the D/A, specify fixed-point number (linear)
output in the DSP program. When multiple YSS920Bs are used, 32-bit data consisting of 28-bit mantissa and
4-bit exponent can be passed by specifying floating-point (float) output.
1 Frame
Lch
Rch
SDWP=0
SDWP=1
SDWCK
SDBCK
SDBP=0
SDBP=1
No Delay
Lch
Rch
SDOFMT1-0=00
SDOBIT1-0=XX
M
LM
LM
LM
L
Mantissa
Exponent
Mantissa
Exponent
1bit Delay
Lch
Rch
SDOFMT1-0=10
SDOBIT1-0=XX
LM
LM
LM
LM
L
EIAJ
Lch
Rch
Rch
SDO7
│
SDOFMT1-0=01
SDOBIT1-0=00
LM
LM
LM
LM
16 bits
16 bits
SDO0
Rch
Lch
Rch
SDOFMT1-0=01
SDOBIT1-0=01
LM
LM
LM
LM
18 bits
18 bits
Rch
Lch
Rch
SDOFMT1-0=01
SDOBIT1-0=10
LM
LM
LM
LM
LM
LM
20 bits
20 bits
Rch
Lch
Rch
SDOFMT1-0=01
SDOBIT1-0=11
LM
LM
24 bits
24 bits
M : MSB L : LSB
14
YSS920B
Microprocessor interface format
Reading/writing of the internal control register is performed through the 4-line serial interface as shown
below:
1) When /CS is used only by one device
/CS
SCK
Don't Care A0 A1 A2 A3 A4 A5 A6 R/W D0 D1 D2 D3 D4 D5 D6 D7 Don't Care
SI
write
R/W = L
High impedance
SO
Don't Care A0 A1 A2 A3 A4 A5 A6 R/W
Don't Care
Don't Care
SI
read
R/W = H
High impedance
High
impedance
D0 D1 D2 D3 D4 D5 D6 D7
SO
SO is set to output mode only when all of the following conditions are met:
・ When /CS=L
・ When reading a valid address setting
・ During the output timing of data (8-bit).
In all other cases, it is set to High-Z, so that SO, SI, and SCK can be shared with devices having similar
interfaces. When multiple YSS920Bs are used, /CS can also be shared by specifying CHIP ADR register
CA3-0. See the next Section “ 2) “.
If the general-purpose input/output pin (IOPORT19-0) is used as an input pin (IPORT), then the IOPORT
(IPORT) value during the period of “R/W” shown above will be read through SO.
If it is used as an output pin (OPORT), then the IOPORT (OPORT) output will be switched over at the time
of SCK rising edge on “D7” shown above.
[Note] Set /CS to H during initial clear (/IC=L).
15
YSS920B
2) When /CS is shared with multiple devices
When multiple YSS920Bs are used or /CS is shared with other LSI, be sure to set CAE=1 and CA 3-0
immediately after the falling edge of /CS as shown in the following figure.
For details, refer to “0x00 CHIP ADR Register” description in the section 3.2 Register Details.
/CS
SCK
Address=0x00
R/WCAE
R/W
A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 Don’t Care
Don’t Care
CA3-0
SI
write
R/W = L
High-Z
SO
A setup of CAE=1 and CA 3-0 is
performed by accessafter the falling
edge of /CS.
Don’t Care
Address=0x00
R/WCAE
CA3-0
A0 A1 A2 A3 A4 A5 A6 R/W
Don’t Care
Don’t Care
SI
read
R/W = H
High-Z
High-Z
D0 D1 D2 D3 D4 D5 D6 D7
SO
[Note] Set /CS = high during initial clear (/IC = low).
16
YSS920B
Electrical characteristics
1) Absolute maximum ratings
Items
Symbol
VDD1
AVDD
VDD2
VI
Condition
Min
Typ
Max
Unit
V
V
V
V
VSS -0.5
VSS -0.5
VSS -0.5
-0.5
VSS +4.6
VSS +3.6
VSS +3.6
VSS +5.75
Power-supply voltage
Pins other than XI pin
Input voltage
*1
XI pin
-0.5
-50
VDD1+0.5
125
V
°C
Tstg
Storage temperature
*1: Using a 5 V tolerant input pin.
2) Recommended operating conditions
Item
Symbol
Condition
Min.
Typ.
3.3
2.5
2.5
25
Max.
3.6
2.7
2.7
85
Unit
Power supply voltage
V
3.0
2.3
2.3
-40
V
V
V
DD1
Internal Operation Frequency
30.72MHz to 50.00MHz
AV
DD
V
DD2
Operating temperature
Top
°C
3) DC characteristics
Condition: Under recommended condition
Items
Symbol
Condition
Min
0.7 V
Typ
Max
Unit
Input voltage H level (1)
Input voltage L level (1)
Input voltage H level (2)
Input voltage L level (2)
Input voltage H level (3)
Input voltage L level (3)
Output voltage H level
Output voltage L level
V
IH1
*1
*1
*2
*2
*3
*3
V
V
V
V
V
V
V
V
DD1
V
IL1
0.3 V
DD1
V
IH2
2.4
2.2
V
IL2
0.8
0.8
V
IH3
V
IL3
V
OH
V
OL
V
-0.4
DD1
I
I
= -80 μA
= 1.0 mA
OH
OL
0.4
10
Pin w/o
pull-up resistor
Input leakage current
I
LI
-10
40
μA
Pull-up resistor
R
160
65
U
kΩ
mW
Power consumption (V
Power consumption (V
)
P
*4
*4
45
DD1
D1
DD2
P
120
145
mW
D2
/AV
)
DD
*1
*2
*3
Applied to the XI input pin.
Applied to the /IC input pin.
Applied to the input pins other than above.
*4 Power consumption largely depends on the DSP program, DSP internal operation clock, and other items
to be operated.
Values listed above are measured under the following conditions:
・50.00 MHz DSP internal operation clock
・fs=96 kHz data input to SDI7-0 pin
・Using SRAM (ERAMSEL1-0=10) as external RAM
・Using a YAMAHA evaluation board
・Using programs that are assumed to produce a high level of processing (maximum number of
steps, frequent access to external RAM)
“The standard values” are obtained at VDD1=3.3 V and VDD2=AVDD=2.5 V
“The Maximum values” are obtained at VDD1=3.6 V and VDD2=AVDD=2.7 V
17
YSS920B
4) AC characteristics
Condition: Under recommended condition
z
No.
Clock
Item
Symbol
Condition
Min.
Typ.
Max. Unit
15.000 MHz
1
2
3
4
XI clock frequency
XI clock duty
PLL lock frequency
PLL lock-up time
f
X
f
12.288
40
xin
60
%
MHz
s
duty
xpll
f
xin
×10
t
lpll
900
CKUP = 0
12.288 MHz ≤ fxin ≤ 15.000 MHz
CKUP = 1
26.66 1/( f /4) 32.55
ns
ns
xpll
CK
5
t
ckc
(Internal operation clock)
20.00 1/(f /3) 24.41
xpll
fxin = 12.288 MHz
z
No.
Power-on / Hardware Reset
Items
Symbol
Condition
Min.
1
Typ.
Max. Unit
ms
6
/IC low time
t
*1
icl
*2
*3
0
-1
1
1
s
s
7
Power-on time *4
tV1V2
*1: Be sure to set /IC to L at power-up. Set /IC to H 1 ms after VDD1, VDD2, and AVDD of the power
supply and XI input have stabilized.
Also, the initial setting of the control register and the downloading of programs shall be started 1 ms after
setting /IC to H.
*2: When a Schottky barrier diode is not connected
The 3.3 V power supply (VDD1) should be started before the2.5 V power supply (VDD2 and AVDD).
At the time of power off, be sure to start the 2.5V power off and then apply 3.3V in reverse order of
power on.
18
YSS920B
*3: When a Schottky barrier diode is connected
Insert a Schottky barrier diode with a forward voltage of 0.4 V or less between the 3.3 V power supply
(VDD1) and 2.5 V power supply (VDD2 and AVDD) (cathode is VDD1 and anode is VDD2).
The 3.3 V power supply and 2.5 V power supply can be started in either order.
*4: The time lag of power ON or OFF between 3.3V power supply and 2.5V power supply must be within
one second. Only one power keeps on supplying, LSI would be damaged.
z
No.
Microprocessor interface
Items
Symbol
Condition
Min.
160
Typ.
Max.
Unit
1
2
3
4
5
6
7
8
9
SCK cycle
SCK rise time
SCK fall time
SCK high level time
SCK low level time
/CS, SI setup time
/CS, SI hold time
SO delay time
t
cc
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
20
20
cr
cf
t
ch
80
80
10
50
t
cl
t
set
t
hold
t
C =50 pF
L
50
delay
/CS high level time
t
160
csnh
1
3
2
5
4
4
SCK
/CS
SI
6
6
7
9
7
8
High impedance
High impedance
SO
(when reading)
19
YSS920B
z
Serial data interface
No.
Items
SDBCK input frequency
SDBCK rise time
SDBCK fall time
Input setup time
Input hold time
Symbol
Condition
Min.
2
Typ.
Max.
12.3
20
Unit
MHz
ns
ns
ns
1
2
3
4
5
6
f
bck
t
ibr
t
20
ibf
t
is
5
10
t
ih
ns
ns
Output delay from
input clock
t
C =50 pF
50
iodly
L
7
8
Clock delay time
Output delay time from
output clock
t
C =50 pF
C =50 pF
L
50
10
ns
bdly
L
t
-10
oodly
9
10
SDBCKO rise time
SDBCKO fall time
t
t
C =50 pF
C =50 pF
L
20
20
ns
ns
obr
L
obf
1
2
3
SDBCK
5
4
4
SDWCK
SDI7-0
5
7
9
SDBCKO
10
8
SDWCKO
SDO7-0
6
・SDBCKO will be output from the IOPORT18 pin by setting IOSEL18=1 and OPSEL18=1.
・SDWCKO will be output from the IOPORT19 pin by setting IOSEL19=1 and OPSEL19=1.
・When SDBP=1, the polarity of SDBCK is inverted.
・When BCKOP=1, the polarity of SDBCK becomes opposite to SDBCKO.
・When WCKOP=1, the polarity of SDWCK becomes opposite to SDWCKO.
20
YSS920B
z
RAM interface
In ERAMSEL 1-0=1* (SRAM/high speed SRAM mode) (CL=20 pF)
No.
1
Items
Symbol
Condition
Min.
Typ.
Max.
Unit
(When reading)
Read cycle
t
rc
ERAMSEL1-0=11
ERAMSEL1-0=10
ns
ns
ns
ns
ns
ckc
×2
t
t
ckc
×3
2
3
4
Data input setup time
Data input hold time
Address delay time
(When writing)
t
20
0
dis
t
dih
t
ad
10
5
Write cycle time
t
ERAMSEL1-0=11
ERAMSEL1-0=10
ns
ns
ns
ns
ns
ns
ns
ns
wc
t
t
×2
×3
ckc
ckc
6
7
Address setup time
Write pulse width
t
0
as
t
wp
ERAMSEL1-0=11
ERAMSEL1-0=10
ckc
×1
t
t
ckc
×2
8
9
10
Write recovery time
Data output delay time
Data output hold time
t
0
wr
t
t
8
dod
0
doh
Note) See “● Clock in the 4) AC characteristics” for tckc (=internal operation clock cycle time).
(when reading)
(when writing)
1
5
RAMA17-0
RAMWEN
RAMOEN
RAMD15-0
6
7
8
4
2
3
9
10
21
YSS920B
When ERAMSEL 1-0=00 (DRAM mode)
(CL=20 pF)
Symbol
No.
Items
Condition
Min.
5
10
115
55
5
40
40
10
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
Setup time for Row address
Hold time for Row address
RASN pulse width
t
ras
t
rah
t
rpw
4
5
6
7
RASN pre-charge time
t
t
t
rpt
cas
cah
Setup time for Column address
Hold time for Column address
CASN pulse width
t
cpw
8
CASN pre-charge time
t
cpt
9
CASN access time
t
cat
30
45
60
10
11
12
13
14
15
16
17
18
Access time from Column address
Access time from RASN
Hold time for read data
Setup time for write data
Hold time for write data
Setup time for write command
Hold time for write command
CASN high-RASN low delay time
Refresh cycle time
t
t
aat
rat
t
0
5
40
5
40
40
rdh
t
wds
t
wdh
t
wcs
t
wch
t
crd
t
RASREF=1
200
rc
Note) Set the internal operation clock cycle time tckc to 32.55 ns (30.72 MHz) in DRAM mode.
(when reading)
3
4
RASN
CASN
7
8
7
17
1
2
5
6
5
6
ROW
COLUMN
COLUMN
RAMA8-0
RAMWEN
RAMOEN
RAMD15-0
9
9
12
12
10
11
10
22
YSS920B
(when writing)
3
4
RASN
7
8
5
7
17
CASN
1
2
5
6
6
ROW
COLUMN
COLUMN
16
RAMA8-0
RAMWEN
RAMOEN
RAMD15-0
15
13
14
13
14
(during /RAS only refresh (RASREF = 1))
18
3
4
RASN
CASN
17
23
YSS920B
Example of Connection Diagrams
1) When using one YSS920B
An example of the basic connection when one YSS920B is used is indicated below:
HOST
PROCESSOR
fs
64fs
SDI0
SDI1
SDI2
SDI3
SDI4
SDI5
SDI6
SDI7
SDO0
SDO1
SDO2
SDO3
SDO4
SDO5
SDO6
SDO7
YSS920B
(EVE)
12.288-15.0MHz
1kO
4700pF
SRAM or DRAM
(option)
z
z
z
It is not necessary to set chip address (CA3-0) when using one YSS920B.
The SO pin may become High-Z. Therefore, pull-up resistors may be necessary on some systems.
On peripheral devices such as the ADC and DAC that require a bit clock with inversed polarity, use the
SDBCKO output from the IOPORT18 pin by setting IOSEL18=1, OPSEL18=1, and BCKOP=1.
24
YSS920B
2) When using multiple YSS920Bs
An example of the basic connection when multiple YSS920Bs are used is indicated below:
HOST
PROCESSOR
fs
64fs
/IC
SDI0
SDI1
SDI2
SDI3
SDI4
SDI5
SDI6
SDI7
SDO0
SDO1
SDO2
SDO3
SDO4
SDO5
SDO6
SDO7
SDI0
SDI1
SDI2
SDI3
SDI4
SDI5
SDI6
SDI7
SDO0
SDO1
SDO2
SDO3
SDO4
SDO5
SDO6
SDO7
YSS920B
(EVE)
YSS920B
(EVE)
12.288-15.0MHz
12.288-15.0MHz
1kO
1kO
4700pF
4700pF
SRAM or DRAM
(option)
SRAM or DRAM
(option)
z
/CS can be shared by setting chip addresses (CA3-0) to the IOPORT15-12 pins.
When switching the device to control, rewrite the control register address 0x00 (CA3-0).
For example, in the case above:
To control the left device, set the register as CAE=1 and CA3-0=0000,
To control the right device, set the register as CAE=1 and CA3-0=0001.
z
z
On peripheral devices such as the ADC and DAC that require a bit clock with inversed polarity, use the
SDBCKO output from the IOPORT18 pin by setting IOSEL18=1, OPSEL18=1, and BCKOP=1.
The SO pin may become High-Z. Therefore, pull-up resistors may be necessary on some systems.
25
YSS920B
Package Dimensions
26
YSS920B
Notice The specifications of this product are subject to improvement changes without prior notice.
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