MAS17501CLXXX [ZARLINK]
Micro Peripheral IC;
| 型号： | MAS17501CLXXX |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Micro Peripheral IC |
| 文件： | 总36页 (文件大小：937K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
APRIL 1995
DS3564-3.4
MA17501
RADIATION HARD MIL-STD-1750A EXECUTION UNIT
The MA17501 Execution Unit is a component of the GEC
BLOCK DIAGRAM
Plessey Semiconductors MAS281 chip set. Other chips in the
set include the MA17502 Control Unit and the MA17503
lnterrupt Unit. Also available is the peripheral MA31751
Memory Management Unit/Block Protection Unit. These chips
in conjunction implement the full MlL-STD-1750A lnstruction
Set.
The MA17501 - consisting of a full function 16-bit ALU, 24 x
16-bit dual-port RAM register file, 32-bit barrel shifter, 4 x 24-
bit parallel multiplier, synchronisation clock generation logic,
and microcode decode logic - provides all computational,
logical, and synchronisation functions for the chip set. Table 1
provides brief signal definitions.
The MA17501 is offered in several package styles
including; dual-in-line, flatpack and leadless chip carrier. Full
packaging information is given at the end of the document.
FEATURES
■ MIL-STD-1750A Instruction Set Architecture
■ Full Performance over Military Temperature Range
(-55°C to +125°C)
■ Radiation Hard CMOS/SOS Technology
■ 16-Bit Bidirectional Address/Data Bus
■ 16-Bit Full Function Registered ALU
■ 32-Bit Barrel Shifter
■ 24 x 16-Bit Dual-Port RAM File
1.0 SYSTEM CONSIDERATIONS
• 16 User Accessible General Purpose Registers
• 8 Microcode Accessible Registers
The MA17501 Execution Unit (EU) is a component of the
GEC Plessey Semiconductors MAS281 chip set. This chip set
implements the full MlL-STD-1750A instruction set
architecture. The other chips in the set are the MA17502
Control Unit (CU) and the MA17503 Interrupt Unit (IU). Also
available is the peripheral MA31751 Memory Management
Unit/Block Protection Unit (MMU(BPU)).
Figure 1 depicts the relationship between the chip set
components. The EU provides the arithmetic and logical
computation resources for the chip set. The EU also provides
program sequencing logic in support of branching and
subroutine functions. The lU provides interrupt and fault
handling resources, DMA interface control signals, and the
three MIL-STD-1750A timers. The EU and lU are each
controlled by microcode from the CU. The MMU(BPU) may be
configured to provide 1M-word memory management (MMU)
and/or 1K-word memory block write protection (BPU)
functions.
■ 4 x 24-Bit Parallel Multiplier
• 48-Bit Accumulator
• 16-Bit x 16-Bit Multiply in 4 Machine Cycles
■ Instruction Pre-Fetch
■ MAS281 Integrated Built-in Self Test
■ TTL Compatible System Interface
MA17501
Figure 1: MAS281 Chip Set with Optional MA17504 and Support RAMs
As shown in Figure 1, the MAS281 is the minimum
2.0 ARCHITECTURE
processor configuration consisting of an Execution Unit, a
Control Unit, and an Interrupt Unit. This configuration is
capable of accessing a 64K-word address space. Addition of a
MA31751 allows access to a 1M-word address space and/or
provides hardware support for 1K-word memory block write
protection.
The EU, as with all components of the MAS281 chip set, is
fabricated with GEC Plessey Semiconductors CMOS/SOS
process technology. lnput and output buffers associated with
signals external to the MAS281 are TTL compatible.
Detailed descriptions of the EU's companion chips are
provided in separate data sheets. Additional discussions on
chip set system considerations, interconnection details, and
DAlS mix benchmarking analysis are provided in separate
applications notes.
The Execution Unit consists of a full function 16-bit ALU,
32-bit barrel shifter, 4 x 24-bit parallel multiplier, 24 x 16bit
dual-port RAM register file, processor status word register,
three operand transfer registers, three instruction fetch
registers, various interconnect buses, synchronization clock
generation logic, and microcode decode logic. Details of these
components are depicted in Figure 2 and are discussed below:
2.1 ALU
The ALU is a full function 16-bit arithmetic/logic unit
capable of performing arithmetic and logic operations on either
one or two 16-bit operands in a single machine cycle. ln
addition to operand manipulation, the ALU is used to compute
memory addresses.
The ALU supports 16-bit fixed-point single-precision, 32-bit
fixed-point double-precision, 32-bit floating-point, and 48-bit
floating-point extended-precision data in two’s complement
representation. Double-precision and extended-precision
operands are passed through the ALU 16 bits at a time on
consecutive machine cycles. Machine flags provide an
indication of ALU results and are used to set condition status
(CS) bits C, P, Z, and N in the Status Word Register. Condition
status bits and the Status Word register are discussed below.
2
MA17501
Signal
I/O
Definition
AD00 - AD15
AS
CLKPC
CLK02
PAUSE
DS
HLDAK
HOLD
lN/OP
INTRE
lRDY
I/O
O/Z
O
O
External 16-Bit Address/Data Bus
Address Strobe Indicates Address lnformation on A/D Bus
Precharge Clock
Phase 2 Clock
l
DMA Acknowledge (A/D Bus to be used for DMA)
Data Strobe lndicates Data lnformation on A/D Bus
Hold Acknowledge
Hold Request Suspends lnternal Processor Functions
lnstruction/Operand lndicates Type of Memory Access
lnterrupt Enable
O/Z
O
l
O/Z
O
l
lnterrupt Unit Ready Signal
M/lO
M00 - M19
OSC
O/Z
l
l
Memory or lnput/Output lndicates Transaction on A/D Bus
20-Bit Microcode Bus
External Oscillator Clock
OVl
PlF
O
l
Overflow lndicator
Privileged Instruction Fault
RD/W
O/Z
Read/Write IndicatesData Direction on A/D Bus
RDY
l
l
O
O
O
I
Ready lnforms CPU of the Conclusion of External Bus Cycle
Reset Indicates Device Initialization
Interrupt Unit's Sync Clock
System Clock - CPU Sync Clock (External)
System Clock (Internal)
RESET
SYNCLK
SYNC
SYSCLK1
TEST
T1
Test Enable
Branch or Jump Control
O
VDD
Power (External), 5 Volts
GND
Ground
Table 1: Signal Definitions
2.4 DUAL-PORT REGISTER FILE
2.2 BARREL SHIFTER
The Register File is a dual port RAM structure containing
24, 16-bit registers. Sixteen of these registers are general
purpose and user accessible. These user accessible registers
- referred to as R0 through R15 - may be used as
accumulators, index registers, base registers temporary
operand registers, or stack pointers. The remaining eight
registers are only accessible by microcode.
The Barrel Shifter is a 32-bit input, 16-bit output right shift
network. A 32-bit operand may be shifted right arithmetically,
logically, or cyclically up to 31 bit positions in a single machine
cycle. While not directly accessible or visible to user programs,
the Barrel Shifter is utilized by microcode to effect all shift,
rotate, and normalize instructions with minimum execution
time.
Adjacent registers are concatenated to effectively form 32-
bit and 48-bit registers for storage of double precision and
extended-precision operands, respectively. Instructions
access these operands by specifying the register containing
the most significant part of the operand, and the register set
wraps around automatically under microcode control, e.g.,
R15 concatenates with R0 for 32-bit operands and R15
concatenates with R0 and R1 for 48-bit operands.
2.3 PARALLEL MULTIPLIER
The Parallel Multiplier performs a 4-bit multiplier by 24-bit
multiplicand multiplication plus accumulation in a single
machine cycle. Only four machine cycles are required to
complete a 16-bit by 16-bit multiplication. Contained within the
multiplier is a 48-bit product accumulation register with the
lower 24 bits serving as a source operand register.
On each multiply machine cycle, the lower four bits of the
accumulator are multiplied by 24 bits from the two ALU
operand source buses (R and S). The lower 24 bits of this 28-
bit product are then added to the upper 24 bits of the
accumulator and the whole accumulator is shifted right four
bits. This right shift makes room for the upper four bits of the
product. The four bits shifted out are used in the next multiply
iteration.
3
MA17501
Figure 2: MA17501 Execution Unit Architecture
2.5 STATUS WORD REGISTER
2.6 OPERAND TRANSFER REGISTERS
The Status Word Register (SW) holds the condition status
(CS) bits C, P, Z, and N generated by ALU operations. The SW
also stores the address state (AS) and processor state (PS)
fields. Figure 3 defines the Status Word Register storage
format. The CS bits are stored with each logical, shift, and
arithmetic operation performed by the ALU as required by MlL-
STD-1750A and remain valid until changed by subsequent
operations. The CS bits are interrogated during "jump on
condition" and "instruction counter relative" MlL-STD-1750A
branch instructions.
The Address (A), Data Output (DO), and Data lnput (Dl)
registers are referred to as Operand Transfer Registers. These
registers serve as storage buffers between internal EU buses
and the EU's externally accessible address/data (AD) Bus.
The DO register buffers data transferred from the EU to the AD
Bus. The A register buffers operand addresses and XlO
commands onto the AD Bus. The Dl register buffers data
transferred from the AD Bus to the EU .
4
MA17501
A 20-bit multiplexed microcode (M) bus provides a
pathway between the Control Unit (CU) and the Execution
Register (E) buffered microcode decode logic on the EU chip.
Microcode placed on this bus by the CU controls all actions of
the EU.
2.9 SYNCHRONISATION CLOCK GENERATION LOGIC
The Execution Unit generates all of the synchronisation
clocks required by the chip set and CPU system. The EU
converts an externally supplied oscillator signal into five
synchronisation signals: SYNCN, SYSCLK1N,SYNCLKN,
CLKPCN, CLK02N. The EU generates SYNCN for elements
external to the chip set whereas SYNCLKN and SYSCLK1N
are generated for the Interrupt Unit and internal EU
synchronisation, respectively. SYSCLK1N is also brought out
on a pin for use by external monitoring systems. The EU
generates CLKPCN and CLK02N for use in the Control Unit.
The CU uses CLKPCN to precharge the M Bus and transmit
the first microword while CLK02N is used to transmit
microword two.
The EU also contains the wait state generation interface.
Failure of memory or l/O subsystems to drive RDYN low at the
proper time during the DSN pulse causes the EU to hold
SYNCLKN, SYNCN, SYSCLK1N, and CLKPCN in the high
state; CLK02N, AS and DSN, in the low state; and RD/WN, IN/
OPN and M/ION in their current states for one or more
oscillator cycles beyond the end of the normal five OSC cycle
machine cycle. When RDYN is asserted low, the EU allows the
machine cycle to conclude at the high-to-low transition of the
current oscillator cycle. This will allow all the synchronisation
and control signals to resume normal operation.
Additionally, IRDYN is used to signal completion of internal
l/O command control of the lnterrupt Unit (IU). The IU thus can
extend the duration of the above mentioned bus signals.
Failure of the lU to drive lRDYN low at the proper time during
the DSN low pulse causes the EU to hold SYNCLKN, SYNCN,
SYSCLK1N, and CLKPCN in the high state; CLK02N, AS, and
DSN in the low state; and lN/OPN, M/lON, and RD/WN in the
state for the normal five OSC cycle machine cycle. When the
lU asserts IRDYN low, the EU allows the machine cycle to
conclude at the high-to-low transition of the current oscillator
cycle. This will allow all the synchronisation and control signals
to resume normal operation.
Figure 3: Status Word Format
2.7 INSTRUCTION FETCH REGISTERS
The Instruction Counter (IC), Instruction A (IA), and
Instruction B (IB) registers allow sequential instruction fetches
to be performed without assistance from the ALU. The lC
register, which holds the 16-bit address of the next instruction
to be fetched from memory, is loaded automatically by reset,
jump, or branch operations. Once loaded, it functions as a
dedicated counter to sequence from one instruction to the
next. The current IC contents may be stored in registers R0
through R15 or in memory (pushed onto a stack) to provide
return linkages for subroutine calls. As part of the microcoded
interrupt handling routine the lC is saved in memory via the
interrupt linkage pointer.
Registers lA and IB provide an instruction look-ahead
capability. ln the case of 16-bit instructions, lB holds the
instruction currently executing while lA holds the next
instruction to be executed. ln the case of 32-bit instructions, IB
and lA each hold half of the instruction. IA and Dl (Dl stores the
immediate operands) are loaded as the instruction in lA is
transferred to lB for execution; if the instruction in lB uses an
immediate operand, lA is reloaded with the next instruction
while Dl maintains the immediate data. This overlapping of
operations allows higher performance levels to be achieved.
[NOTE: Whenever the EU is executing a machine cycle
which requires IRDYN to drop low for completion, the machine
cycle will be a minimum of six OSC cycles long. The maximum
duration of this machine cycle depends on the length of time
that the lU holds IRDYN high.]
2.8 BUSES
Three 16-bit wide buses (R, S, and Y) interconnect the EU
data storage and computational elements. The R and S buses
accept operands from selected EU data storage elements and
route them to inputs of selected EU computational elements.
The Y, or destination, bus serves to route computational
results either back to EU data storage and computational
elements or to the various operand transfer registers.
A 16-bit multiplexed Address/Data (AD) Bus provides a
communications path between the EU, other components of
the MAS281 chip set, and any other devices mapped into the
chip set's address space. Data transfers between the AD Bus
and the R, S, and Y buses are buffered by the operand transfer
registers.
5
MA17501
[NOTE: For MAS281s operating at high OSC frequencies,
the lnterrupt Unit logic that creates lRDYN may cause a wait
state to be inserted during execution of internal XlO
commands. This would result in a SYNCN cycle of seven OSC
cycles duration. Though unlikely, this condition must be taken
into account in implementing a RDYN generation circuit. Refer
to the description of the RDYN signal for further details].
3.0 INTERFACE SIGNALS
All signals comply with the voltage levels of Table 1. ln
addition, each of these functions is provided with Electrostatic
Discharge (ESD) protection diodes. All unused inputs must be
held to their inactive state via a connection to VDD or GND. A
500-ohm pull-up at the OSC input pin is recommended to
damp line reflections.
Throughout this data sheet, active low signals are denoted
by either a bar over the signal name or by following the name
with an "N" suffix, e.g., HOLDN. Referenced signals that are
not found on the MA17501 are preceded by the originating
chip's functional acronym in parentheses, e.g., (lU)DMARN.
A description of each pin function, grouped according to
functional interface, follows. The function acronym is
presented first, followed by its definition, its type, and its
detailed description. Function type is either input, output, high
impedance (Hi-z), or a combination thereof. Timing
characteristics of each of the functions described is provided in
Section 5.0.
3.2.3 IU Synchronisation Clock (SYNCLKN)
Output. The SYNCLKN signal is a logical equivalent of the
SYNCN signal provided for Interrupt Unit synchronisation.
3.2.4 System Clock (SYSCLK1N)
Output. SYSCLK1N is the MA17501's synchronization
clock. It is the logical equivalent of SYNCN and SYNCLKN with
the exception that during PAUSEN low or during HLDAKN low,
SYSCLK1N is held in its low state. SYSCLK1N, like
SYNCLKN, has a VSS to VDD logic level swing.
3.2.5 Precharge Clock (CLKPCN)
Output. CLKPCN is used by the MA17502 Control Unit
(CU) to synchronize the precharging of the internal M Bus and
most other CU operations to the MAS281 machine cycle.
CLKPCN cycles associated with MAS281 external memory
or l/O bus transactions are a minimum of five OSC cycles in
duration and are extended when wait states are inserted via
the RDYN input. CLKPCN low indicates that the internal CU M
Bus is being precharged to the high state; the low-to-high
transition places the lower 20 bits of a microinstruction on the
external M Bus. Wait states extend the high state of CLKPCN.
When PAUSEN or HLDAKN is low, CLKPCN is held low.
CLKPCN cycles associated with internal MAS281
operations are either five or six OSC cycles in duration. Six
OSC cycles are required for machine cycles associated with
microcode branches or with the execution of internally
(lnterrupt Unit) decoded XlO commands. Five OSC cycles are
used for all other internal operations, e.g., register to register
transfers, ALU functions, etc.
3.1 POWER INTERFACE
The power interface consists of one 5V VDD connection
and three common GND pins.
3.2 CLOCKS
The Execution Unit provides the synchronisation clocks for
the MAS281 chip set. Together these clocks form the basic
operation cycle.
3.2.1 Oscillator (OSC)
lnput. The MA17501 requires a single external oscillator
input for operation. The EU converts the oscillator into the five
other clocks listed in this section. To minimise skew between
OSC edges and signals derived from OSC, the OSC rise and
fall times should be minimised. lt is recommended that a clock
driver with high drive capability, such as a 54AS244,
54ALS244 or 54HST240, be used to drive the OSC input.
ln order to avoid double clocking due to line reflections, a
500-ohm pull-up resistor, placed close to the EU, is
recommended.
[NOTE: For MAS281s operating at high OSC frequencies,
the lnterrupt Unit logic that creates lRDYN may cause a wait
state to be inserted during execution of internal XlO
commands. This would result in a CLKPCN cycle of seven
OSC cycles duration.]
3.2.2 Synchronisation Clock (SYNCN)
Output. The MA17501 provides the MAS281
Synchronisation Clock output to synchronise external circuitry
to the MAS281 machine cycle. The high-to-low transition of
this signal indicates the start of a new machine cycle.
SYNCN cycles associated with external memory or l/O bus
transactions are a minimum of five OSC cycles in duration and
may be extended by inserting wait states via the RDYN input.
SYNCN low indicates that either an address or XlO command
is on the AD Bus; a high indicates data is on the bus. Wait
states extend the high state of SYNCN.
SYNCN cycles associated with internal CPU operations
are either five or six OSC cycles in duration. Six OSC cycles
are required for machine cycles associated with microcode
branches or with the execution of internally (Interrupt Unit)
decoded XlO commands. Five OSC cycles are used for all
other internal operations, e.g., register to register transfers,
ALU functions, etc.
6
MA17501
3.2.6 Phase 2 Clock (CLK02N)
Output. CLK02N is used by the MA17502 Control Unit
(CU) in conjunction with CLKPCN to synchronize
microinstruction transmission on the M Bus to the
MAS281 machine cycle.
CLK02N cycles associated with MAS281 external
memory or l/O bus transactions are a minimum of five
OSC cycles in duration and are extended when wait
states are inserted via the RDYN input.
The high-to-low transition of CLK02N places the
upper 20 bits of a microinstruction on the external M Bus.
Wait states extend the trailing (based on SYNCN high-to-
low beginning the machine cycle) low state of CLK02N.
When PAUSEN or HLDAKN is low, CLK02N is held high.
CLK02N cycles associated with internal MAS281
operations are either five or six OSC cycles in duration.
Six OSC cycles are required for machine cycles
associated with microcode branches or with the
execution of internally (Interrupt Unit) decoded XlO
commands. Five OSC cycles are used for all other
internal operations, e.g., register to register transfers,
ALU functions, etc.
[NOTE: For MAS281s operating at high OSC
frequencies, the Interrupt Unit logic that creates IRDYN
may cause a wait state to be inserted during execution of
internal XlO commands. This would result in a CLK02N
cycle of seven OSC cycles duration.]
3.3 BUS CONTROL
This group of signals is provided to control Address/
Data (AD) bus transmissions (See Figure 4). The signals
indicate when address or data information is on the AD
Bus and what type of transaction is taking place during a
particular machine cycle.
3.3.1 Address Strobe (AS)
Output/Hi-z. AS high indicates that the Address/Data
(AD) Bus contains address information. The address
information is assured stable at the high-to-low transition
of this signal. ln this way, AS provides the necessary
control for a system Address Bus transparent latch
system interface.
Figure 4: Typical MAS281/MA17504 System Interface
The Interrupt Unit uses AS to extract the XlO
command information off the AD Bus for internally
decoded XlO commands, and the Memory Management
Unit/Block Protection Unit (MMU(BPU)) uses AS to
extract address information for memory management
and block protection functions, and to extract XlO
command information for MMU(BPU) decoded XlO
commands.
AS is placed in the high-impedance state during DMA
cycles by PAUSEN low and during the Hold state by
HLDAKN low. During internal non-AD Bus related CPU
operations, AS is held low for the entire machine cycle via
microcode control.
7
MA17501
3.3.2 Data Strobe (DSN)
3.3.5 Instruction/Operand (IN/OPN)
Output/Hi-z. DSN low indicates that data is on the AD Bus
(write/output cycles) or that the MAS281 AD Bus drivers are in
the high-impedance state (read/input cycles). For write/output
cycles, the data is guaranteed stable at the low-to-high
transition of DSN. For read/input cycles, the DSN low-to-high
transition indicates the acceptance of data by the MAS281
(SYSCLK1N high-to-low transition latches AD Bus data into
the lA and Dl registers).
DSN is placed in the high-impedance state during DMA
cycles by PAUSEN low and during the Hold state by HLDAKN
low. DSN is held high, for the entire machine cycle, during
internal non-AD Bus operations via microcode.
Output/Hi-z. lN/OPN high indicates an instruction is to be
read from memory during the current AD Bus cycle. IN/OPN is
low for all other MAS281 directed AD Bus transfers. The
Memory Management Unit/Block Protection Unit
(MMU(BPU)), when configured as a MMU, uses lN/OPN to
select the proper page register set within the specified page
register group.
IN/OPN is asserted at the SYNCN high-to-low transition
and remains valid for the duration of the current SYNCN
period. lN/OPN is placed in the high-impedance state during
DMA cycles by PAUSEN low and during the Hold state by
HLDAKN low.
3.3.3 Read/Write (RD/WN)
3.3.6 Ready (RDYN)
Output/Hi-z. RD/WN defines the direction of data flow on
the bidirectional AD Bus and provides read/write cycle
information to the MMU(BPU) for write protection control.
RD/WN high indicates a read/input bus cycle and data transfer
to the MAS281. RD/WN low indicates a write/output bus cycle
and data transfer from the MAS281.
This signal is asserted at the SYNCN high-to-low transition
and remains valid for the duration of the current SYNCN
period. RD/WN is placed in the high impedance state during
DMA cycles by PAUSEN low and during the Hold state by
HLDAKN low.
Input. During external AD Bus transfers (those dealing with
devices external to the MAS281 chip set), a low is required on
this input to allow the MAS281 machine cycle to complete
(high-to-low transition of SYNCN). RDYN high is used to
prolong the data portion of the machine cycle (SYNCN high) to
accommodate slow memory and l/O devices. The MAS281
assumes memory or l/O devices are NOT ready to provide
(accept) data to (from) the AD Bus, and requires these devices
to signal their readiness via the RDYN input.
A low on RDYN, enveloping the current machine cycle's
fifth (or later) OSC cycle high-to-low transition, allows the
current machine cycle to complete (SYNCN high-to-low
transition) at the following low-to-high transition of the OSC
input.
3.3.4 Memory/lnput-Output (M/ION)
Output/Hi-z. M/lON defines the type of device involved in
the data transfer occurring on the AD Bus and provides
functional control for the lnterrupt Unit (lU) and the Memory
Management Unit/Block Protection Unit (MMU(BPU)). The lU
ignores memory transfer AD Bus activity and the MMU(BPU)
uses M/lON to decide whether to decode the address
information on the AD Bus as an MMU(BPU) XlO command or
a memory address. M/lON high indicates a memory access,
and M/lON low indicates an input-output operation.
3.4 BUSES
The following is a discussion of the communication buses
connecting the MA17501 to the other chips of the MAS281 set.
The AD Bus transfers all data and instructions and the M Bus
provides the microcode instructions from the MA17502.
3.4.1 Address/Data Bus (AD Bus)
This signal is asserted at the SYNCN high-to-low
transition and remains valid for the duration of the current
SYNCN period. M/lON is placed in the high impedance state
during DMA cycles by PAUSEN low and during the Hold state
by HLDAKN low. M/lON is raised high, for the entire machine
cycle, during internal non AD Bus operations via microcode.
Input/Output/Hi-z. These signals comprise a 16-bit
bidirectional multiplexed address and data bus. During
external bus transfers, the AD Bus accommodates the transfer
of address and data information between the MA17501 and
memory, or l/O ports. During internal bus operations, the AD
Bus provides additional communication among the Execution,
Control, Interrupt and Memory Management/Block Protection
Units. AD00 is the most significant bit position and AD15 is the
least significant bit position of both the 16-bit data and 16-bit
address. A high on this bus corresponds to a logic one and a
low corresponds to a logic zero.
Address information is valid on the bus at the AS high to-
low transition. The RD/WN signal indicates the MA17501 AD
Bus drivers state during the data portion of the bus cycle (DSN
low) and the M/lON function defines the type of device the
transfer is with. The AD Bus drivers are placed in the high
impedance state during Read operations (DSN low), during
DMA cycles by PAUSEN low, and during the Hold state by
HLDAKN low.
8
MA17501
3.4.2 Microcontrol Bus (M Bus)
3.5.3 Processor Hold Acknowledge (HLDAKN)
Input. The M Bus is a 20-bit multiplexed microcontrol bus
which provides microcoded control to the EU. The Control Unit
multiplexes the 40-bit microcode instructions into two 20-bit
words. The upper 20 bits are placed on the M Bus by the
CLKPCN low-to-high transition and the lower 20 bits are
placed on the M Bus by the trailing high-to-low transition of
CLK02N. The microinstruction is reassembled in the EU’s
Execution (E) register and used to control EU functions during
the next machine cycle. M19 is the most significant bit position
and M00 is the least significant bit position for both
microwords. The high order 20 bits are transmitted first,
followed by the low order 20 bits of the microinstruction. A high
on this bus corresponds to a logic one and low corresponds to
a logic zero.
Output. HLDAKN drops low after reaching the end of the
MIL-STD-1750A instruction during which HOLDN was pulled
low, or after encountering a BPT software instruction. The Hold
state is terminated by raising HOLDN high (if HOLDN low
initiated the Hold state), or by pulsing HOLDN low (if the Hold
state was initiated by a BPT instruction). During the Hold state,
software execution is suspended and the MAS281 interface
functions are placed in the high impedance state to allow a
monitor system to take control of the memory/input-output
system.
3.6 INTER-CHIP CONTROL
The following signals perform control functions internal to
the MAS281 chip set. These functions include microcode
execution branching control and arithmetic error indication.
3.5 SYSTEM SUPPORT INTERFACE
The system support interface signals have control over
functions that affect the chip set as a whole.
3.6.1 Internal Ready (IRDYN)
Input. The IRDYN signal is the means by which Interrupt
Unit (IU) command cycles, involving the AD Bus, are
completed. The lU drops lRDYN low when the XlO command
has been decoded and allows the six OSC period machine
cycle to complete. The IRDYN and RDYN signals are
effectively ORed together to control the EU clock generation
circuitry; therefore, RDYN should be high during lU decoded
XlO commands.
3.5.1 Processor Pause (PAUSEN)
lnput. PAUSEN is driven low by the lnterrupt Unit upon
acknowledgement of a DMA transfer request. A low on
PAUSEN causes the EU to place all the bus control signals
(AS, DSN, M/lON, RD/WN, IN/OPN) and the AD Bus in the
high impedance state, and to disable all clock outputs, except
for SYNCLKN and SYNCN. The requesting device maintains
control of the AD Bus and bus control lines until (lU)DMARN is
raised high, thus causing PAUSEN to raise high.
lt is recommended that the MAS281 chip set be buffered to
the memory/input-output system. lf an MMU(BPU) peripheral
chip is used for memory expansion/protection it must reside on
the MAS281 side of these buffer transceivers (see Figure 4).
Thus, for a DMA device to access the MMU(BPU), the
MAS281 AD Bus and bus control signal drivers must be in the
high impedance state to allow the DMA device to drive these
signals. The interrupt Unit also provides the CDN signal for the
directional control of the bus control transceivers.
3.6.2 Interrupt Unit Microinstruction Enable (INTREN)
Output. The Execution Unit controls the lnterrupt Unit (lU)
3-bit microcode interface through the use of the INTREN
signal. lNTREN low enables the lU microcode decoding logic.
lU functions handled through microcode are; enable/disable
DMA interface XlO command control, set Normal Power-Up
discrete, load fault register, and read encoded 4-bit vector
identifying the highest priority pending interrupt.
Machine cycles during lNTREN low are a special case of
internal non-AD Bus operations. These cycles are denoted by
a six OSC period machine cycle.
3.6.3 Overflow Indicator (OVIN)
3.5.2 Processor Hold Request (HOLDN)
Output. OVlN is an indication that a fixed-point overflow
condition, as specified in MIL-STD-1750A, has occurred
during an operation. The Interrupt Unit accepts this as an input
to the pending interrupt register level four interrupt bit.
lnput. A low on this input suspends all chip set functions
(except SYNCN and SYNCLKN) at the end of the current MlL-
STD-1750A instruction. The AD Bus and bus control functions
(AS, DSN, M/ION, lN/OPN, RD/WN) are placed in the high
impedance state permitting a monitor system to take control of
the memory/input-output system. The internal synchronisation
clocks are placed in an inactive state, which halts further
instruction sequencing until HOLDN is released. As with DMA
cycles, the reason for this is to allow access to the MMU(BPU)
if an expanded memory system is used. The (lU)CDN output is
provided for control bus transceiver directional control during
the Hold state. This input should be synchronised to AS falling.
9
MA17501
3.6.4 Privileged Instruction Fault (PIFN)
4.0 OPERATING MODES
lnput. PlFN low is an indication to the Execution Unit that a
fault, requiring the current MlL-STD-1750A instruction to be
aborted, has occurred. The faults that cause the instruction
abort are 0, 5, and 8 which are, respectively, memory protect
error ((IU)MPROEN low), an out-of-bounds memory/input-
output address ((lU)EXADE low), or a bus fault timeout. ln
response to PIFN low, the EU maintains AS low, DSN high,
and forces the M/lON signal high for two machine cycles. ln
addition, the EU will internally complete the current SYNCN
cycle and resume operation. This allows the Control Unit to
sequence to the interrupt handling routine without affecting the
bus status.
The following discussions detail the MAS281 chip set
operating modes from the perspective of the Execution Unit.
MAS281 operating modes involving the MA17501 include: (1)
Initialisation, (2) lnstruction Execution, (3) Interrupt Servicing,
(4) Fault Servicing, (5) DMA Support, and (6) Software
Development Support.
4.1 INITIALISATION
RESET starts the chip set microcoded initialisation
sequence, but also affects the Execution Unit Circuitry directly.
When RESET is raised high, the Hold state acknowledge
signal (HLDAKN) is forced high thus releasing the MAS281
from the Hold state (if changing HOLDN is unable to release
the Hold state). RESET also forces the clock generation
circuitry to create a five OSC period machine cycle by
disabling state machine inputs that vary the machine cycle
length.
Upon releasing RESET, the EU Hold State circuitry is
enabled and the clock generation circuitry is allowed to
function normally. HOLDN will not have an effect on chip set
operation until the initialisation routine has completed because
the microcode branch to the Hold routine is disabled.
The microcoded initialisation routine clears the lnstruction
Counter (lC), Status Word Register (SW), and Register File
(R00-R15) and performs the BlT. The successful completion of
the BlT is necessary to guarantee the register file is cleared at
the end of the initialisation routine.
3.6.5 Branch or Jump Control (T1)
Output. The Execution Unit raises the T1 signal high to
indicate a microcode conditional branch condition is true. The
Control Unit accepts T1 and feeds it into the microcode
address multiplexer where microinstruction branches are
effected.
3.6.6 Test Microword (TESTN)
lnput. The TESTN signal is used during chip test to load 40-
bit microinstructions into the EU execution register. TESTN
low loads E39 (MSB) to E20, and TESTN high loads E19 to
E00 (LSB). TESTN should be pulled-up to VDD in customer
applications.
The microcoded BIT exercises all legal microinstruction bit
combinations and tests all internally accessible structures of
the MAS281. For the Execution Unit this includes the full
Register Set, ALU, Multiplier, Barrel Shifter, and Macroflag
logic. Table 2 details the tests performed by each of the five
BlT subroutines.
lf any part of BlT fails, an error code identifying the failed
subroutine is loaded into the lnterrupt Unit Fault Register (via
the AD Bus), BlT is aborted, and NPU is left in the low state.
Table 2 defines the coding of the BlT results. (lNTREN enables
microcode control of the lnterrupt Unit (lU) to raise NPU high (if
BlT passes) and load BIT error codes (if BIT fails) into the lU
Fault Register).
The last action performed by the initialisation routine is to
load the instruction pipeline. Instruction fetches start at
memory location zero (page zero) from the Start-Up ROM (if
implemented). Whether or not BIT passes, the processor will
begin instruction execution at this point.
[NOTE: To complete initialisation and pass BIT, interrupt
and fault inputs must be high for the duration of the
initialisation routine. Also, the Timers A and B must be clocked
for BlT success.]
10
MA17501
BIT
Test Coverage
BIT Fail Codes (FT13,14,15
)
Cycles
1
Mlcrocode Sequencer
IB Register Control
Barrel Shifter
100
221
Byte Operations and Flags
2
Temporary Registers (T0 - T7)
Microcode Flags
Multiply
101
166
Divide
3
4
Interrupt Unit - MK, Pl, FT
Enable/Disable Interrupts
111
110
214
154
Status Word Control
User Flags
General Registers (R0 - R15
5
-
Timer A
Timer B
111
-
763
26
BIT Pass/Fail Overhead
Note: BIT pass is indicated by all zeros in FT bits 13, 14, and 15.
Table 2: MAS281 BIT Summary
4.2 INSTRUCTION EXECUTION
lnstruction fetches are five (minimum) OSC period
machine cycles characterised by IN/OPN, M/lON, and RD/WN
high. lnstruction fetches use pipeline registers lA and IB, the
instruction counter (lC), and the data input register (Dl).
Assuming an empty instruction pipeline (as a result of a reset,
jump or branch), the contents of lC are placed on the AD Bus
as an address. The returned value (the instruction) is stored in
the IA register. The lC register is incremented (dedicated
counter mode) and the next fetch is performed.
This second returned value, which may be an instruction or
an immediate operand, is stored in both the lA and Dl registers
as the previous contents of IA advance to the IB register to be
decoded into their microcoded routine. If the second returned
value is an immediate operand, a third instruction fetch will
occur with the instruction being loaded into lA only; Dl retains
the immediate operand.
The data portion (SYNCN high) of instruction fetch cycles
can be extended beyond their minimum five OSC periods by
use of the RDYN signal. RDYN held high during the high-to-
low transition of the machine cycles fifth OSC cycle will extend
the data portion of the machine cycle. The machine cycle can
be completed at any succeeding OSC cycle high-to-low
transition by enveloping this OSC edge with RDYN low.
Instruction execution is characterised by a variety of
operations composed of various types of machine cycles. The
Execution Unit contains the clock generation circuitry that
creates the different machine cycles depending on the
particular operation being performed at the time. These
operations include: (1) internal CPU cycles, (2) instruction
fetches, (3) operand transfers, and (4) input/output transfers.
Instruction execution may be interrupted at the end of any
individual machine cycle by the PAUSEN (denoting DMA
operations) clock generation circuitry input, and at the
beginning of any given MIL-STD-1750A instruction by an
(IU)IRN or HOLDN low input to the Control Unit.
4.2.1 Internal CPU Cycles
All CPU data manipulation and housekeeping operations
are performed using internal CPU cycles. Internal CPU cycles
are either five or six OSC periods long and are characterised
by AS low and DSN, (IU)DDN, and M/ION high. Section 5.0
provides timing characteristics for internal CPU cycles.
The majority of lnternal CPU Cycles are five OSC period
machine cycles. Six OSC period machine cycles occur when
executing conditional jump or branch microinstructions; the EU
is calculating the branch condition to determine the state of the
T1 output signal.
4.2.3 Operand Transfers
Operand transfers are used to obtain operands to be used
by an instruction and to save any results of an instructions
execution. Machine cycles associated with operand transfers
are a minimum of five OSC periods in duration. The RDYN
signal can be used to insert wait states into the data portion of
the machine cycle (SYNCN high) to accommodate slow
memory.
4.2.2 Instruction Fetches
lnstruction fetches are used to keep the instruction pipeline
full. This ensures that the next instruction is ready for
execution when the preceding instruction is completed.
During jump and branch instruction execution the pipeline
is flushed, then refilled via two consecutive instruction fetches
starting at the new instruction location. The pipeline is also
refilled as part of the interrupt and Hold processing.
11
MA17501
Operand transfers use the address register (A), data input
4.3 INTERRUPT SERVICING
register (Dl), and data output register (DO). Before the
operand transfer begins, the Execution Unit calculates the
effective operand address and stores this value in A.
For write transfers the EU loads the operand into DO. For
operand ready cycles the EU latches the operand from the AD
Bus into Dl at the SYSCLK1N high-to-low transition.
All operand transfers between the MAS281 and memory
are referenced to the AS and DSN bus control signals and are
characterised by lN/OPN low, M/lON and CDN high, and RD/
WN (high, read; low, write).
The EU first places the contents of A on the AD Bus at the
SYSCLK1N high-to-low transition. Shortly following, AS is
raised high to enable the system address bus transparent
latch. This address is assured valid at the high-to-low transition
of AS. At the SYSCLK1N low-to high transition, DSN drops low
to indicate the contents of DO have been placed on the AD
Bus (write) or the EU AD Bus drivers have been placed in the
high impedance state (read).
Interrupts are latched into the lnterrupt Unit (lU) pending
interrupt register by the SYNCLKN high-to-low transition. The
lU signals the Control Unit (CU) that an interrupt is pending
and the CU branches to the microcoded interrupt handling
routine at the completion of the currently executing MlL-STD-
1750A instruction.
The EU supports the interrupt handling routine by enabling
microcode control of the lU at the proper time via the lNTREN
signal and by calculating the memory addresses of the service
and linkage pointers based on the 4-bit interrupt priority code
transmitted by the IU. Machine cycles during which lNTREN is
low are six OSC periods in length. During these lNTREN
cycles, DSN and M/lON are high, and AS is low.
The EU also provides a hardwired interrupt to the lU. the
OVIN interrupt signals a fixed-point arithmetic overflow.
4.4 FAULT SERVICING
The Interrupt Unit (IU) latches fault inputs into the fault
register on the high-to-low transition of SYNCLKN. Faults other
than 0, 5, and 8 latch a level one pending interrupt in the lU and
the interrupt sequencing proceeds as previously explained.
Faults 0, 5, and 8 caused during non-DMA AD Bus transactions
demand more immediate attention; the MlL-STD-1750A
instruction during which the fault occurred must be aborted.
PIFN indicates to the Control Unit that one of these faults
has occurred and forces a branch to the “next instruction fetch’’
microinstruction so that the interrupt caused by the PlFN fault
can be serviced immediately. Under normal instruction
execution circumstances, the bus control signals would operate
during the machine cycle between the fault and the instruction
fetch machine cycle. PlFN causes the bus control signals AS
and DSN to stay in their inactive state during this transitional
machine cycle to allow the branch to the microcoded interrupt
routine without performing any AD Bus transactions.
DSN subsequently raises high when the output data is
stable, prior to SYSCLK1N dropping low, or raises high in
response to SYSCLK1N dropping low to indicate the EU's
acceptance of the input data.
All operand transfer cycles are allowed to complete via the
RDYN input. During the data portion of the cycle the EU
assumes memory is NOT READY, and requires RDYN low to
signal the memory’s readiness to complete the cycle. If RDYN
is high at the high-to-low transition of the fifth OSC cycle within
the operand transfer cycle, a wait state will be injected (one
OSC period at a time) for each OSC high-to-low transition that
RDYN remains high. Memory readiness, thus cycle
completion, is signalled by RDYN low enveloping a
subsequent OSC high-to-low transition.
4.2.4 Input/Output Transfers
Input/Output transfers are characterised by M/lON and IN/
OPN low, and RD/WN (high, input; low, output). AS and DSN
operate as during operand transfers. Two different types of
input/output transfers are controlled by the Execution Unit:
internal and external.
Internal l/O transfers involve all XlO commands that are
decoded by the lnterrupt Unit (lU) and use the local AD Bus to
transfer response data. These commands are listed in Table 3
(the only exception is RCW; it is an lU decoded, lRDYN
completed, External l/O command). Internal XlO commands
implemented in the lU (per Table 3) use a six OSC period
machine cycle and the IRDYN cycle completion input. lnternal
XlO commands implemented in the MA31751 MMU/BPU use
a minimum five OSC period machine cycle. The system RDYN
generator provides the RDYN cycle completion input to the
EU.
The term "local AD Bus" in this context refers to the AD Bus
on the processor side of the system data bus demultiplexing
transceivers. The three chips of the MAS281 and the
MA17504 (in either configuration) reside on the local AD Bus
and communicate to the user system through the required
address and data bus buffers, as depicted in Figure 4.
External I/O transfers involve all XlO and VlO instructions
not included under lnternal l/O transfers. They execute during
a minimum five OSC period machine cycle that is extendible
via RDYN, as previously described.
4.5 DIRECT MEMORY ACCESS
The Interrupt Unit DMA interface logic signals the
Execution Unit (EU) that it has acknowledged a DMA request
(PAUSEN low). PAUSEN low causes the EU to halt the
synchronisation clocks CLK02N (high), CLKPCN (low), and
SYSCLK1N (low); disables clock generation circuitry input that
could vary the machine cycle length; and places all bus control
signals and the AD Bus in the high impedance state. The
SYNCN and SYNCLKN clocks continue to operate with a five
OSC cycle period. Upon removal of PAUSEN by the Interrupt
Unit, the MAS281 resumes microinstruction execution where it
was interrupted.
4.6 SOFTWARE DEVELOPMENT SUPPORT
The Execution Unit responds to a HOLDN signal by
suspending all internal operations upon completion of the
currently executing instruction. Microcode, from the Control
Unit, directs HLDAKN low during the third SYNCN cycle after
HOLDN has been pulled low and the previous instruction has
been completed. M/lON, RD/WN, IN/OPN, AS, DSN, and the
AD Bus are placed in the high impedance state permitting a
monitor system to take control of the memory/input-output
system. Raising HOLDN releases the MAS281 from the Hold
state and instruction execution begins by refilling the pipeline.
The execution of a BPT instruction also causes HLDAKN
to drop low and the bus control signals and AD Bus to be
placed in the high impedance state. A low pulse on HOLDN
releases the MAS281 from the BPT initiated Hold state.
12
MA17501
Cycles*
P
Command
Code(Hex)
Operation
Mnemonic
M
B
Implemented in MAS281
Set Fault Register
Set lnterrupt Mask
Clear lnterrupt Request
Enable lnterrupts
Disable Interrupts
Reset Pending Interrupt
Set Pending lnterrupt Register
Reset Normal Power Up Discrete
Write Status Word
Enable Start-Up ROM
Disable Start-up ROM
Direct Memory Access Enable
Direct Memory Access Disable
Timer A Start
Timer A Halt
Output Timer A
Reset Trigger-Go
Timer B Start
Timer B Halt
Output Timer B
0401
2000
2001
2002
2003
2004
2005
200A
200E
4004
4005
4006
4007
4008
4009
400A
400B
400C
400D
400E
8400
8401
A000
A004
A00E
A00F
C00A
C00E
SFR
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3a
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
1
2
2
2
9
9
9
9
9
9
9
9
8.5a
9
9
9
9
9
9
9
9
9
9
9
4
4
4
4
4
4
SMK
CLlR
ENBL
DSBL
RPI
SPI
RNS
WSW
ESUR
DSUR
DMAE
DMAD
TAS
TAH
OTA
GO
TBS
TBH
OTB
RCW
RFR
RMK
RPlR
RSW
RCFR
lTA
Read Configuration Word
Read Fault Register without Clear
Read Interrupt Mask
Read Pending Interrupt Register
Read Status Word
Read and Clear Fault Register
lnput Timer A
Input Timer B
4
4
lTB
Implemented in BPU
Memory Protect Enable
Load Memory Protect RAM
Read Memory Protect RAM
4003
S0XX
D0XX
MPEN
LMP
RMP
2
2
2
4
4
3
8
8
3
Implemented in MMU
Write Instruction Page Register
Write Operand Page Register
Read Memory Fault Status
Read lnstruction Page Register
Read Operand Page Register
S1XY
52XY
A00D
D1XY
D2XY
WIPR
WOPR
RMFS
RlPR
2
2
2
2
2
4
4
3
3
3
8
8
3
3
3
ROPR
M = memory, P = processor (5 OSC cycles), B = processor (6 OSC cycles), a = average if more than one
alternative exlsts.
Table 3: Internal I/O Command Summary
13
MA17501
5.0 TIMING CHARACTERISTICS
This section provides the detailed timing specifications for
the MA17501. Figure 5 depicts the test loads used to obtain
timing data. Figures 6 through 20 depict the timing waveforms
associated with various MA17501 signals. Table 5 provides
values for parameters specified in the timing waveforms. All
timing values provided in Table 5 are valid over the full military
temperature range (-55°C to +125°C), and are measured from
50% point to 50% point (50% VDD supply voltage, unless
otherwise specified). Crosshatching in Figures 6 through 20
indicates either a "don’t care" or indeterminate state.
Load 1
Load 3
Load 2
Figure 5: Test Loads
14
MA17501
Figure 6: Reset Timing
Figure 7: Basic Clock Timing
15
MA17501
Figure 8: Potential Branch Clock Timing
Figure 9: Microcode Bus Timing
16
MA17501
Figure 10: Internal Processor Cycle
17
MA17501
Figure 11: Write Transfer Timing
18
MA17501
Figure 12: Read Transfer Timing
19
MA17501
Figure 13: Internal I/O Timing - Write/Command
20
MA17501
Figure 14: Internal I/O Timing - Read
21
MA17501
Figure 15: DMA Access/Release Timing
22
MA17501
Figure 16: Hold State Generation Timing
23
MA17501
Figure 17: Hold State Termination Timing
Figure 18: Fixed Point Overflow Timing
24
MA17501
Figure 19: Instruction Abort Fault Timing
Figure 20: Interrupt Unit Microcode Enable Timing
Subgroup Definition
1
2
Static characteristics specified in Table 6 at +25°C
Static characteristics specified in Table 6 at +125°C
3
Static characteristics specified in Table 6 at -55°C
Functional tests at +25°C
7
8a
8b
9
Functional tests at +125°C
Functional tests at -55°C
Switching characteristics specified in Table 4b at +25°C
Switching characteristics specified in Table 4b at +125°C
Switching characteristics specified in Table 4b at -55°C
10
11
Table 4a: Definition of Subgroups
25
MA17501
No.
Parameter
Test Conditions (1) (2)
Min (2) Typ (2) Max (2) Units
1
2
3
4
5
6
7
8
OSC ↑ to SYNCN
OSC ↑ to SYSCLK1N
OSC ↑ to SYNCLKN
OSC ↑ to CLKPCN
OSC ↑ to CLK02N
SYNCN ↓ to AS ↑
SYNCN ↓ to AS ↓ (4)
SYNCN ↓ to DSN (Read)
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 2
Load 2
Load 2
Load 2
Load 2, 3
Load 2, 3
Load 2
Load 2
Load 2, 3
Load 2, 3
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
10
40
40
40
40
40
1τ+5
2.5τ+15
3τ+20
30
3τ+22
4.5τ+10
68
3τ+45
70
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1τ-10
2.5τ-10
3τ-5
10
3τ-5
9
SYNCN ↓ to DSN ↓ (Read) (3)
SYNCN ↓ to DSN ↓ (Write)
SYNCN ↓ to DSN ↑ (Write) (3)
SYNCN ↓ to Address Valid
SYNCN ↓ to Data Valid
SYNCN ↓ to M/ION, RD/WN, IN/OPN, INTREN Valid
SYNCN ↓ to HLDAKN Valid
SYSCLKN1 ↓ to T1 Valid
SYSCLKN1 ↓ to OVIN Valid
SYNCN ↓ to AD Bus Hi-Z (Read) (6)
SYNCN ↓ to AD Bus Active (Read)
PAUSEN ↓ to AD Bus Hi-Z (Read) (6)
PAUSEN ↑ to AD Bus Valid
PAUSEN ↓ to AS, DSN, M/ION, RD/WN, IN/IOPN Hi-Z (6)
PAUSEN ↑ to AS, DSN, M/ION, RD/WN, IN/IOPN Valid
HLDAKN ↓ to AD Bus Hi-Z (Read) (6)
HLDAKN ↑ to AD Bus Valid
HLDAKN ↓ to AS, DSN, M/ION, RD/WN, IN/IOPN Hi-Z (6)
HLDAKN↑ to AS, DSN, M/ION, RD/WN, IN/IOPN Valid
Address after SYNCN ↓
Data after SYNCN ↓
M/ION, RD/WN, IN/OPN, INTREN after SYNCN
HLDAKN after SYNCN ↓
T1N after SYSCLK1N ↓
OVIN after SYSCLK1N ↓
Data to SYNCN ↓
Microcode to CLK02N ↓
Microcode to SYSCLK1N ↓
RDYN to OSC ↓
IRDYN to OSC ↓
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
4.5τ-5
75
100
3τ+50
15
70
60
50
59
60
50
30
30
3τ+15
12
5
-7
15
20
20
10
10
15
15
0
5
15
5
10
5τ-2
2
Data after SYNCN ↓
Microcode after CLK02N ↓
Microcode after SYSCLK1N ↓
RDYN after OSC ↓
IRDYN after OSC ↓
SYNCN to SYNCN ↓ (7)
RESET ↑ to RESET ↓ (7)
5τ+2
RESET ↑ to Related Outputs Valid (7)
PIFN to Related Outputs Valid
HOLDN to Related Outputs Valid (7)
DSN to Data Valid (Write) (7)
SYNCN to SYNCLKN (No.1 - No.3)
CLKPCN to SYNCLKN (No.4 - No.3)
SYSCLK1 to CLKPC (No.2 - No.4)
50
50
50
Load 3 (DSN) Load 2 (Data)
15
-5
-5
-5
8
5
10
MIL-STD-883, Method 5005, Subgroup 9, 10, 11
Notes:
1. TA = +25°C, -55°C and +125°C tested at VDD = 4.5V and 5.5V
2. r = 1OSC period 0.5r implies 50% OSC duty cycle
3. Add 1r for internal XlO; nr for memory wait
4. Excluding DMA and Hold conditions
5. Unless otherwise noted: Vll = ≥ 0.0V, VIHTTL ≤ 4.0V, VIHOSC = 4.0V timing measured from 50% to 50% points
6. High impedance measured by 20% (of VDD) voltage change using 1K-ohm pullup resistor
7. Data obtained by characterisation or analysis, not routinely measured
8. Load 2 applies to bus interface signals AS, RD/W and IN/OP; Load 3 applies to bus interface signals M/ION and DSN
Table 4b: Timing Parameter Values
26
MA17501
6.0 ABSOLUTE MAXIMUM RATINGS
Note: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these conditions, or at
any other condition above those indicated in the operations
section of this specification, is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
Parameter
Min
-0.5
-0.3
-20
-55
-65
Max
7
Units
V
Supply Voltage
Input Voltage
V
DD+0.3
+20
125
150
V
Current Through Any Pin
Operating Temperature
Storage Temperature
mA
°C
°C
Table 5: Absolute Maximum Ratings
7.0 DC ELECTRICAL CHARACTERISTICS
Total Dose Radiation Not
Exceeding 3x105 Rad(Si)
Symbol Parameter
Conditions
Min
Typ
Max
Units
VDD
VIHC
VILC
VIHT
VILT
Supply Voltage
VSS = 0
4.5
5.0
5.5
-
V
V
CMOS Input High Voltage (Note 1)
CMOS Input Low Voltage (Note 1)
TTL Input High Voltage (Note 2)
TTL Input Low Voltage (Note 2)
OSC Input High Voltage (Note 6)
OSC Input Low Voltage (Note 6)
-
-
-
-
-
-
VDD-1
-
-
-
VSS+1
-
V
2.0
-
V
-
-
0.8
-
V
VCH
4.0
-
V
VCL
-
-
1.0
-
V
VOHC
VOLC
VOHT
VOLT
VOHCLK
VOLCLK
II
CMOS Output High Voltage (Note 1) IOH = -1.4mA, VDD = 4.5V
4.0
-
V
CMOS Output Low Voltage (Note 1)
TTL Output High Voltage (Note 2)
TTL Output Low Voltage (Note 2)
Clock Output High Voltage (Note 3)
Clock Output Low Voltage (Note 3)
Input Leakage Current (Note 4)
Output Leakage Current (Note 4)
IOL = 2mA, VDD = 5.5V
-
-
0.5
-
V
IOH = -1.4mA, VDD = 4.5V
IOH = -1.4mA, VDD = 4.5V
IOH = -12mA, VDD = 4.5V
IOL = 12mA, VDD = 5.5V
VDD = 5.5V, VIN = 0V or 5.5V
VDD = 5.5V, VO = 0V or 5.5V
3.5
-
V
-
-
0.4
-
V
4.0
-
V
-
-
-
-
-
-
-
-
0.5
±10
±50
-300
35
10
V
µA
µA
µA
mA
mA
IOZ
-
IIPU
TESTN Input Pullup Current (Note 5) VDD = 5.5V, TESTN = 0V
-150
25
5
IDDOP
IDDST
Operating Supply Current
Static Supply Current
VDD = 5.5V, OSC = 20MHz
VDD = 5.5V, OSC = 0MHz
Mil-Std-883, Method 5005, Subgroup 1, 2, 3.
Notes: 1. The following signals are CMOS compatible:
a) CMOS inputs: Microcode Bus, (M00-M19), TESTN, IRDYN and PIFN.
b) CMOS outputs: T1, OVIN, INTREN, SYSCLK1N, CLKPCN and CLK02N.
2. The following signals are TTL compatible:
a) TTL inputs: HOLDN, RESET, PAUSEN, RDYN and OSC.
b) TTL outputs: HOLDAKN and SYNCN.
c) TTL 3 state outputs: AS, DSN, M/ION, RD/WN and IN/OPN.
d) TTL 3 state I/O signals: Address/Data Bus (AD00-AD15).
3. The clock output pins, SYSCLK1N, SYNCLK, CLKPCN and CLK02N have a higher drive capability than the
standard outputs.
4. Worst case at TA = +125°C, guaranteed but not tested at TA = -55°C.
5. The TESTN input signal is used during chip test and has an integral pullup reistor. In normal operation TESTN is at
VDD
6. Guaranteed but not tested.
.
Table 6: Operating DC Electrical Characteristics
27
MA17501
8.0 PACKAGING INFORMATION
Millimetres
Ref
Inches
Min.
Nom.
Max.
5.715
1.53
0.508
0.36
82.04
-
Min.
Nom.
Max.
0.225
0.060
0.020
0.014
3.230
-
A
A1
b
-
-
-
-
0.38
-
0.015
-
0.35
-
0.014
-
c
0.229
-
0.009
-
D
-
-
-
-
e
-
2.54 Typ.
-
0.100 Typ.
e1
H
-
22.86 Typ.
-
-
0.900 Typ.
-
4.71
-
-
-
-
5.38
23.4
1.27
1.53
0.185
-
-
-
-
0.212
0.920
0.050
0.060
Me
Z
-
-
-
-
-
-
W
XG413
D
W
ME
Seating Plane
A1
A
C
H
e1
e
b
Z
15°
Figure 21a: 64-Lead Ceramic DIL - Package Style C
28
MA17501
1
2
OSC
NC
64 SYNCN
63 RDYN
62 IRDYN
61 OVIN
60 T1
3
SYNCLK1N
SYNCLKN
CLKPCN
CLK02N
AS
4
5
6
59 PAUSEN
58 HLDAKN
57 RESET
56 HOLDN
55 AD00
54 AD01
53 AD02
52 GND
51 AD03
50 AD04
49 AD05
48 AD06
47 AD07
46 AD08
45 AD09
44 AD10
43 AD11
42 VDD
7
8
DSN
9
GND
10
M/ION
RD/WN 11
GND 12
IN/OPN 13
INTREN 14
PIFN 15
M19 16
Top
View
M18 17
M17 18
M16 19
M15 20
21
22
23
24
M14
M13
M12
M11
41 NC
M10 25
M09 26
M08 27
M07 28
M06 29
M05 30
M04 31
M03 32
40 AD12
39 AD13
38 AD14
37 AD15
36 TESTN
35 M00
34 M01
33 M02
Figure 21b: Pin Assignments
29
MA17501
Millimetres
Inches
Ref
Min.
1.905
-
Nom.
Max.
2.21
-
Min.
0.075
-
Nom.
Max.
0.087
-
A
b1
D
E
-
-
0.51
0.020
18.08
18.08
-
-
18.62
18.62
-
0.712
0.712
-
-
0.733
0.733
-
-
1.02
-
-
0.040
-
e
Z
1.40
1.78
0.055
0.070
XG493
D
A
e
b
Z
1
Pad 1
Bottom
View
E
Radius r
3 corners
Figure 22a: 64-Lead Leadless Chip Carrier - Package Style L
30
MA17501
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
DSN
AS
8
7
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
M10
M09
M08
M07
M06
M05
M04
M03
M02
M01
M00
CLK02N
CLKPCN
SYNCLKN
SYSCLK1N
NC
6
5
4
3
2
Bottom
View
OSC
1
SYNCN
RDYN
64
63
62
61
60
59
58
57
IRDYN
OVIN
TESTN
AD15
AD14
AD13
AD12
T1
PAUSEN
HLDAKN
RESET
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Figure 22b: Pin Assignments
31
MA17501
Millimetres
Inches
Ref
Min.
-
Nom.
Max.
2.72
2.24
0.51
0.30
24.51
-
Min.
-
Nom.
Max.
0.107
0.088
0.020
0.012
0.960
-
A
-
-
A1
1.83
0.41
0.20
23.88
-
-
0.072
0.016
0.008
0.940
-
-
b
-
-
c
-
-
D1, D2
-
-
e
j1
j2
L
2.54
1.02
0.51
-
0.050
0.040
0.020
-
-
-
-
-
-
-
-
-
10.16
1.65
10.54
2.16
0.400
0.065
0.415
0.085
Z
-
-
XG540
A
A1
c
L
D1
j1
Z
Pin 1
b
e
D2
Top View
j2
Figure 23a: 68-Lead Topbraze Flatpack - Package Style F
32
MA17501
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
M11
M10
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9
8
DSN
AS
M09
7
CLK02N
CLKPCN
SYNCLKN
SYSCLK1N
NC
M08
6
M07
5
M06
4
M05
3
M04
2
NC
M03
Top View
1
OSC
M02
68
67
66
65
64
63
62
61
SYNCN
RDYN
IRDYN
OVIN
M01
M00
TESTN
AD15
AD14
AD13
AD12
T1
PAUSEN
HLDAKN
RESET
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Figure 23b: Pin Assignments
33
MA17501
9.0 RADIATION TOLERANCE
Total Dose (Function to specification)*
Transient Upset (Stored data loss)
Transient Upset (Survivability)
Neutron Hardness (Function to specification)
Single Event Upset**
3x105 Rad(Si)
1x1011 Rad(Si)/sec
>1x1012 Rad(Si)/sec
>1x1015 n/cm2
Total Dose Radiation Testing
For product procured to guaranteed total dose radiation
levels, each wafer lot will be approved when all sample
devices from each lot pass the total dose radiation test.
The sample devices will be subjected to the total dose
radiation level (Cobalt-60 Source), defined by the ordering
code, and must continue to meet the electrical parameters
specified in the data sheet. Electrical tests, pre and post
irradiation, will be read and recorded.
<1x10-10 Errors/bit day
Not possible
Latch Up
* Other total dose radiation levels available on request
** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit
GEC Plessey Semiconductors can provide radiation
testing compliant with Mil-Std-883 method 1019 Ionizing
Radiation (total dose) test.
Table 10: Radiation Hardness Parameters
10.0 ORDERING INFORMATION
Unique Circuit Designator
MAx17501xxxxx
Radiation Tolerance
S
R
Q
Radiation Hard Processing
100 kRads (Si) Guaranteed
300 kRads (Si) Guaranteed
QA/QCI Process
(See Section 9 Part 4)
Test Process
(See Section 9 Part 3)
Package Type
C
F
L
Ceramic DIL (Solder Seal)
Flatpack (Solder Seal)
Leadless Chip Carrier
Assembly Process
(See Section 9 Part 2)
Reliability Level
L
Rel 0
C
D
E
B
S
Rel 1
Rel 2
Rel 3/4/5/STACK
Class B
Class S
For details of reliability, QA/QC, test and assembly
options, see ‘Manufacturing Capability and Quality
Assurance Standards’ Section 9.
34
MA17501
HEADQUARTERS OPERATIONS
CUSTOMER SERVICE CENTRES
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07
• GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55
• ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire, SN2 2QW, United Kingdom.
Tel: (01793) 518000
• JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510
• NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023
• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
• SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
• TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260
• UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK Tel: (01793) 518527/518566
Fax: (01793) 518582
Fax: (01793) 518411
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017,
1500 Green Hills Road, Scotts Valley,
California 95067-0017,
United States of America.
Tel: (408) 438 2900
Fax: (408) 438 5576
These are supported by Agents and Distributors in major countries world-wide.
© GEC Plessey Semiconductors 1995 Publication No. DS3564-3.4 April 1995
TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to
be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only
and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any
equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose
failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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