MFR62340A-JOS [ZARLINK]
Receiver,;
| 型号： | MFR62340A-JOS |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Receiver, 光纤 |
| 文件： | 总11页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MFR62340A-J
Parallel Fiber Receiver
Preliminary Information
DS5397
ISSUE 2.1
October 2001
Ordering Information
MFR62340A-JO
MPO/MTP Connector
MFR62340A-JOS
MFR62340A-JX
With EMI shield
MPX Connector
Applications
•
High-speed interconnects within and between
Switches, Routers and Transport equipment
•
•
Proprietary backplanes
Low cost OC-192 VSR (Very Short Reach)
connections
•
•
InfiniBand™ connections
Interconnects rack-to-rack, shelf-to-shelf, board-
to-board, board-to-optical backplane
Features
•
•
•
•
•
Data rate 155Mbps to 2.5Gbps per channel
Description
12 parallel channels, total 30Gbps capacity
The MFT62340A-J and MFR62340A-J make a very
high speed transmitter and receiver pair for parallel
fiber applications. This pair, coupled through a
multimode parallel fiber ribbon cable, constitutes a
complete parallel fiber link. These links provide high-
speed interconnects for use within and between large
capacity switches, routers and data transport
equipment. The transmitter and receiver have a
differential CML interface and support MPO/MTP
and MPX fiber connectors.
Differential CML (Current-Mode Logic) interface
.
Link length up to 300m (with 500MHz km fiber)
-12
Channel BER 10
MFT62340A-J
when used with
•
•
•
•
•
Designed for multimode fiber ribbon
MPO/MTP or MPX connector options
Surface-mount package
Pick-and-placeable; reflow solderable
Matches the MFT62340A-J Transmitter
16.0
46.9
16.7
Dimensions in mm
Figure 1 - MFR62340A-JO: MPO/MTP Connector Option
1
MFR62340A-J Preliminary Information
Absolute Maximum Ratings (note 1)
Parameter
Symbol
Min
Max
Unit
1
2
3
4
5
Supply voltage
VCC
-0.5
-0.5
20
4.0
VCC+0.3
85
V
V
Voltage on any pin
V
PIN
Operating and storage moisture
Storage temperature
M
%
°C
V
OS
TSTG
-40
+100
400
ESD resistance all I/O (note 2)
V
-400
E
Recommended Operating Conditions (note 3)
Parameter
Symbol
Min
Max
Unit
1
2
3
4
5
6
Case temperature (note 4, fig. 6)
Supply voltage (note 5)
T
0
80
°C
V
CASE
V
3.3-5% 3.3+5%
CC
Data rate per channel
f
0.155
830
80
2.5
860
120
100
Gbps
nm
Ω
D
Optical wavelength
λ
CML differential load impedance (Fig. 4)
Power supply noise (1MHz to 2GHz)
Z
O
V
mV
p-p
NPS
Note 1:
Note 2:
Note 3:
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Human body model.
Data patterns are to have maximum run lengths and DC balance shifts no worse than those of a Pseudo Random Bit
23
Sequence of length 2 -1 (PRBS-23).
Note 4:
Note 5:
An air flow parallel to the PCB, and parallel with the module’s heatsink flanges, is recommended. See figure 6 for
information about ambient temperature vs. air flow.
The heat sink of the module is at Vcc potential. To prevent accidental short circuit to any other component in the
system, each module is supplied with an adhesive thermally conductive strip attached to the top of the heat sink.
2
Preliminary Information MFR62340A-J
Characteristics (note 1)
Parameter
Symbol
Min
Typ
Max
Unit
1
2
3
4
5
6
7
8
9
Power consumption (0.155 to 2.5 Gbps)
Power supply current
P
2.4
W
D
I
760
mA
CC
Saturation (average power)
P
P
-3
dBm
dBm
dBm
ps
SAT
Sensitivity (note 2)
-15
S12
Stressed receiver sensitivity (note 3)
Stressed receiver eye opening (note 4)
P
-10.1
SS
P
108
SE
Jitter
Total (note 5)
TJ
DJ
, t
153
46
ps
ps
p-p
p-p
Contribution
Deterministic (note 6)
CML differential output rise/fall time (20-80%, Fig. 5)
t
160
450
-5
ps
RC FC
10 CML differential output voltage (Fig. 3,4,5)
11 CML differential output reflection coefficient
12 Channel skew (note 7)
V
250
350
mV
dB
OCML
S
22
t
175
ps
SK
13 Return Loss (note 9)
RL
12
dB
14
15
16
17
Low (I
High
= 3mA)
V
0.4
V
sink
LNMOS
HNMOS
NMOS output
voltage
V
2.4
V
Assert level
P
-15.5
dBm
dBm
dBm
µs
AS
De-assert level
P
-31
0.5
DS
Receiver Signal
18 Detect (RX_SD) Hysteresis
(note 8)
P -P
AS DS
19
20
Assert time (fig. 7)
T
10
10
AS
De-assert time (fig. 7)
T
µs
DS
Note 1:
Note 2:
Operating conditions are as per Recommended Operating Conditions. Test pattern PRBS-23 at 2.5Gbps with
50/125µm fiber, unless otherwise specified.
-12
Sensitivity for a channel (as defined in IEEE 802.3z Gigabit Ethernet) is specified at a BER of 10
using a fast rise/
fall time source with low RIN and Extinction Ratio not less than 6 dB. All channels not under test are receiving signals
with an average input power of 6 dB, or higher, above worst case sensitivity.
Note 3:
Note 4:
The stressed receiver sensitivity is measured using 2.4 dB Inter-Symbol Interference, ISI, (min), 33 ps Duty Cycle
Dependent Deterministic Jitter, DCD DJ (min) and 6 dB ER (ER Penalty = 2.2 dB). All channels not under test are
receiving signals with an average input power of 6 dB, or higher, above worst case sensitivity.
The stressed receiver eye opening represents the eye at TP4 as defined in IEEE 802.3z Gigabit Ethernet
Specification 38.5. The stressed receiver eye opening is measured using 2.4 dB ISI (min), 33 ps DCD DJ (min), 6 dB
ER (ER Penalty = 2.2 dB) and an average input optical power of –9.6 dBm (0.5 dB above Minimum Stressed
Receiver Sensitivity as defined in IEEE 802.3z Gigabit Ethernet Specification Section 38.5). All channels not under
test are receiving signals with an average input power of 6 dB, or higher, above worst case sensitivity.
Note 5:
Total Jitter, TJ, equals TP3 to TP4 as defined in IEEE 802.3z Gigabit Ethernet Specification 38.5. Total jitter is
-12
-12
specified at a BER of 10
(TJ=DJ+RJ
x 2Q, where Q=7 for BER 10
and RJ=Random Jitter).
rms
Note 6:
Note 7:
Deterministic jitter includes duty cycle distortion.
Electrical channel skew is measured with the input signals having equal amplitude and no input optical
channel skew.
Note 8:
Note 9:
All channels not under test are receiving signals with an average input power of 6 dB, or higher, above the channel
under test.
Return loss is the ratio between received optical power and optical power reflected back into the fiber.
3
MFR62340A-J Preliminary Information
Use of solder with no-clean flux, i.e. solder that does
not require washing after assembly, is
recommended. Washing the module with any kind of
liquid is not advised due to potential damage.
Cleaning the Optical Interface
A protective connector plug is supplied with each
module. This plug should remain in place prior to
use, and be re-attached whenever a fiber cable is not
inserted. This will keep the optical interface free
from dust or other contaminants, which may
potentially degrade the optical signal. Before re-
attaching the connector plug to the module, visually
inspect the plug and remove any contamination. If
the optical interface becomes contaminated, it can
be cleaned with high-pressure nitrogen. Liquids or
physical contact with the optical interface are not
advised due to potential damage.
Electrostatic Discharge (ESD)
The module is classified as Class 1 according to
MIL-STD-883, test method 3015. When handling the
modules, precautions for ESD sensitive devices
should be taken. These precautions include use of
ESD protected work areas with wrist straps,
controlled work benches, floors etc. The
recommendations advised by Zarlink in the technical
note "MFTN6005A Manufacturing Guidelines" should
be followed.
Assembly on Printed Circuit Board
The module can be soldered by hand or by a reflow
process.
Electromagnetic Interference (EMI)
•
For hand soldering, a soldering iron with its tip
connected to ground should be used. Solder
extractors, including replacement parts, should
be of the non-static generating type.
•
Emission: The electromagnetic emission is
tested in front of the module (module fitted with
EMI shield “-JOS option”), with the module
mounted in a front-panel cutout as shown in fig.
10. The specification is to FCC Class B with
6dB margin.
•
For reflow soldering, the recommendations
advised by Zarlink in the technical note
“MFTN6005A Manufacturing Guidelines” should
be followed. This document provides guidelines
about choice of solder, reflow temperature and
time profile etc.
•
Immunity: The electromagnetic immunity is
tested without a front panel or enclosure. The
module specification is maintained with an
applied field of 10V/m for frequencies between
80MHz and 1GHz.
4
Preliminary Information MFR62340A-J
RX_SD9,12
RX_SD5,8
RX_SD1,4
Do1
1
Do1c
:
:
:
:
TIA/Limiting
Amplifier
PIN
Array
2
3
4
Do4
Do5
Do4c
Do5c
5
6
7
8
:
:
:
:
Optical
Inputs
TIA/Limiting
Amplifier
PIN
Array
Do8
Do9
Do8c
Do9c
9
:
:
:
:
TIA/Limiting
Amplifier
PIN
Array
10
11
12
Do12
Do12c
VCC Gnd
Figure 2 - Block Diagram
Vcc
100Ω
100Ω
100 nF
DoN
DoNc
Z
=100Ω Differential
Z =100Ω Differential
O
O
100 nF
Figure 3 - Data Output Equivalent Circuit
MFR62340A-J CML Output
Recommended CML Input
+3.3V
100nF
Z
=100Ω
IN
Z =100Ω Differential
O
Differential
100nF
AC coupling capacitors are included
in the module
Figure 4 - Differential CML Interface
5
MFR62340A-J Preliminary Information
Data
80%
20%
VOCML
Data Inv
tRC
tFC
Figure 5 - CML Differential Signals
80
70
60
50
40
30
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Air Flow [m/s]
Figure 6 - Max Air Temperature vs. Air Flow for Case Temperature Max 80˚C
Optical
Input
Normal Signal
Loss of Signal
Normal Signal
TDS
TAS
2.4V
0.4V
RX_SD
Figure 7 - Receiver Signal Detect Timing Diagram
25
1
MFR62340A-J
50
1
FIBER RIBBON
12
26
Figure 8 - Pin Assignment (Top View)
6
Preliminary Information MFR62340A-J
Pin Description
No
1
Name
Logic
Description
No
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Name
Logic
Description
Gnd
Ground
Gnd
Ground
2
V
V
Positive power supply
Positive power supply
V
V
Positive power supply
Positive power supply
Not Connected
Not Connected
Not Connected
Ground
CC
CC
CC
CC
3
4
RX_SD
NMOS
Receiver Signal Detect
channels 1 and 4
(channels 2 and 3 are not
monitored).
High = Signal detected.
Low = No signal detected.
Open drain with internal
pull-up resistor 40kΩ
(note 1).
1,4
Gnd
Do12c
Do12
Gnd
CML
CML
Data output No 12, inv.
Data output No 12.
Ground
5
6
RX_SD
NMOS
NMOS
Receiver Signal Detect
channels 5 and 8
(Channels 6 and 7 are not
monitored).
High = Signal detected.
Low = No signal detected.
Open drain with internal
pull-up resistor 40kΩ
(note 1).
5,8
Do11c
Do11
Gnd
CML
CML
Data output No 11, inv.
Data output No 11.
Ground
RX_SD
Receiver Signal Detect
channels 9 and 12
(channels 10 and 11 are
not monitored).
High = Signal detected.
Low = No signal detected.
Open drain with internal
pull-up resistor 40kΩ
(note 1).
Do10c
Do10
Gnd
CML
CML
Data output No 10, inv.
Data output No 10.
Ground
9,12
Do9c
Do9
CML
CML
Data output No 9, inv.
Data output No 9.
Ground
7
Gnd
Do1
Ground
Gnd
8
CML
CML
Data output No 1.
Data output No 1, inv
Ground
Do8c
Do8
CML
CML
Data output No 8, inv.
Data output No 8.
Ground
9
Do1c
Gnd
Do2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Gnd
CML
CML
Data output No 2.
Data output No 2, inv.
Ground
Do7c
Do7
CML
CML
Data output No 7, inv.
Data output No 7.
Ground
Do2c
Gnd
Do3
Gnd
CML
CML
Data output No 3.
Data output No 3, inv.
Ground
Do3c
Gnd
Do4
CML
CML
Data output No 4.
Data output No 4, inv.
Ground
Do4c
Gnd
Do5
CML
CML
Data output No 5.
Data output No 5, inv.
Ground
Do5c
Gnd
Do6
CML
CML
Data output No 6.
Data output No 6, inv.
Ground
Do6c
Gnd
Note 1:
All RX_SD pins may be tied together (wired OR) to create one Receiver Signal Detect (RX_SD) output.
7
MFR62340A-J Preliminary Information
Mechanical Drawings
16
14.4
46.9
Ø3
8.5
0.76
1.27
0.5
3.5
7.19
16.7
Dimensions in mm
Figure 9 - MFR62340A-JO: MPO/MTP Connector Option
46.5
1.27
0.5
18.1
1.9
0.76
6
22.75
Dimensions in mm
Figure 10 - MFR62340A-JX: MPX Connector Option
8
Preliminary Information MFR62340A-J
PCB Footprints
3.5
Guide pin key
Ø3.2
1
50
25
26
12.7
17.78
Rear of Module
Dashed lines indicate module outline
Solid lines indicate board layout
Dimensions in mm
Figure 11 - MFR62340A-JO: MPO/MTP Connector Option (Top View)
9.05
9.05
Guide pin keys
1
50
25
26
12.7
17.78
Rear of Module
Dashed lines indicate module outline
Solid lines indicate board layout
Dimensions in mm
Figure 12 - MFR62340A-JX: MPX Connector Option (Top View)
9
MFR62340A-J Preliminary Information
Electrical Connections
Vcc(3.3V)
Do12c
Do12
Zo=100 Ohm Differential
ZL=100 Ohm
C1
R1
100pF
5.1Ohm
.
.
.
.
.
.
.
.
.
.
C2
100nF
C4
100pF
Do01c
C3
100nF
R2
5.1Ohm
Zo=100 Ohm Differential
ZL=100 Ohm
Do01
Notes:
RX_SD9,12
RX_SD5,8
*
C1-C4 and R1-R2 should be placed as close
to the Vcc pins as possible.
RX_SD1,4
*
*
Use a ground plane under the module.
Use vias to connect Gnd pins to ground plane
Figure 15 - Recommended Electrical Connections
10
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2
2
2
Purchase of Zarlink’s I C components conveys a licence under the Philips I C Patent rights to use these components in an I C System, provided that the system conforms
2
to the I C Standard Specification as defined by Philips
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Copyright 2001, Zarlink Semiconductor Inc. All rights reserved.
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