NJ88C22MAMP [ZARLINK]
Frequency Synthesiser with resettable counters; 频率合成器与计数器复位
| 型号： | NJ88C22MAMP |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Frequency Synthesiser with resettable counters |
| 文件： | 总7页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJ88C22
Frequency Synthesiser with resettable counters
DS2439 - 2.2
T
he NJ88C22 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-holdcomparators,10-bitprogrammable‘M’counter,
7-bit programmable ‘A’ counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented serially under external control from a
suitable microprocessor. Although 28 bits of data are initially
required to program all counters, subsequent updating can be
abbreviatedto17bits,whenonlythe‘A’and‘M’countersrequire
changing.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
PDA
PDB
LD
CH
RB
MC
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
CH
PDA
PDB
NC
F
CAP
ENABLE
CLOCK
DATA
NC
IN
RB
NJ88C22
MC
V
SS
CAP
LD
ENABLE
CLOCK
DATA
NC
V
F
NJ88C22
DD
IN
V
SS
OSC IN
The NJ88C22 is intended to be used in conjunction with a
two-modulus prescaler such as the SP8715 series to produce a
universalbinarycodedsynthesiserforupto1100MHz operation.
V
DD
NC
OSC OUT
OSC OUT
OSC IN
DG16, DP16
MP18
FEATURES
Fig.1 Pin connections - top view (not to scale)
■
■
■
■
■
Low Power Consumption
High Performance Sample and Hold Phase Detector
Serial Input with Fast Update Feature
>20MHz Input Frequency
ABSOLUTE MAXIMUM RATINGS
20·75V to 7V
Supply voltage, VDD2VSS
:
Input voltage
Fast Lock-up Time
7V
SS20·3V to VDD10·3V
255°C to 1125°C
Open drain output, LD pin:
All other pins:
Storage temperature:
V
ORDERING INFORMATION
NJ88C22 MA DG Ceramic DIL Package
NJ88C22 MA DP Plastic DIL Package
NJ88C22 MA MP Miniature Plastic DIL Package
(DP and MP packages)
265°C to 1150°C
(DG package)
RB
15
CAP
17
CH
16
(18)
(17)
(15)
f
7 (9)
REFERENCE COUNTER
r
SAMPLE/HOLD
PHASE
DETECTOR
2
÷
1 (1)
OSC IN
(11BITS)
PDA
8 (10)
OSC OUT
LATCH 6 LATCH 7 LATCH 8
‘R’ REGISTER
10 (12)
12 (14)
FREQUENCY/
PHASE
DETECTOR
2 (2)
DATA
ENABLE
f
PDB
V
11 (13)
3 (4)
SS
‘M’ REGISTER
‘A’ REGISTER
CLOCK
LOCK DETECT (LD)
V
LATCH 1 LATCH 2 LATCH 3
LATCH 4 LATCH 5
4 (5)
‘M’ COUNTER
(10 BITS)
‘A’ COUNTER
(7 BITS)
F
IN
6 (7)
5 (6)
V
DD
MODULUS
CONTROL
OUTPUT (MC)
14 (16)
CONTROL LOGIC
V
SS
Fig.2 Block diagram (MP pinout shown in parentheses)
NJ88C22
ELECTRICAL CHARACTERISTICS AT VDD = 5V
Test conditions unless otherwise stated:
V
DD–VSS=5V ±0·5V. Temperature range = –40°C to +85°C
DC Characteristics
Value
Characteristic
Units
Conditions
Min. Typ. Max.
0 to 5V
square
wave
Supply current
5·5
1.5
mA
mA
f
, fFIN = 10MHz
, fFIN = 1MHz
osc
f
osc
Modulus Control Output (MC)
High level
4·6
V
V
I
I
SOURCE = 1mA
SINK = 1mA
Low level
0·4
Lock Detect Output (LD)
Low level
Open drain pull-up voltage
PDB Output
0·4
7·0
V
V
ISINK = 4mA
High level
Low level
4·6
V
V
I
SOURCE = 5mA
0·4
ISINK = 5mA
3-state leakage current
±0·1
µA
AC Characteristics
Characteristic
Value
Units
Conditions
Min. Typ.
Max.
FIN and OSC IN input level
Max. operating frequency, fFIN and f
200
20
mV RMS 10MHz AC-coupled sinewave
MHz
Input squarewave VDD to VSS,
osc
25°C.
Propagation delay, clock to modulus control MC
Programming Inputs
Clock high time, tCH
30
50
ns
See note 2
0·5
0·5
0·2
0·2
0·2
0·2
µs
µs
µs
µs
µs
µs
µs
V
Clock low time, tCL
Enable set-up time, tES
Enable hold time, tEH
Data set-up time, tDS
Data hold time, tDH
Clock rise and fall times
High level threshold
Low level threshold
All timing periods
are referenced to
the negative
transition of the
clock waveform
tCH
0·2
DD20·8
V
See note 1
See note 1
See note 1
0·8
1·0
V
V
Hysteresis
Phase Detector
Digital phase detector propagation delay
Gain programming resistor, RB
Hold capacitor, CH
Programming capacitor, CAP
Output resistance, PDA
500
5
ns
kΩ
nF
nF
kΩ
1
1
5
See note 3
NOTES
1. Data, Clock and Enable inputs are high impedance Schmitt buffers without pull-up resistors; they are therefore not TTL compatible.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant
to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs.
4. The inputs to the device should be at logic ‘0’ when power is applied if latch-up conditions are to be avoided. This includes the signal/osc.
frequency inputs.
2
NJ88C22
PIN DESCRIPTIONS
Pin no.
Name
Description
DG,DP MP
PDA
PDB
1
1
Analog output from the sample and hold phase comparator for use as a ‘fine’ error signal. Voltage
increases as f (the output from the ‘M’ counter) phase lead increases; voltage decreases as f (the
output from the reference counter) phase lead increases. Output is linear over only a narrow phase
window, determined by gain (programmed by RB). In a type 2 loop, this pin is at (VDD2VSS)/2 when the
system is in lock.
v
r
2
2
Three-state output from the phase/frequency detector for use as a ‘coarse’ error signal.
f . f or f leading: positive pulses with respect to the bias point VBIAS
v
r
v
f , f or f leading: negative pulses with respect to the bias point VBIAS
v
r
r
f = f and phase error within PDA window: high impedance.
v
r
NC
LD
–
3
3
4
Not connected.
An open-drain lock detect output at low level when phase error is within PDA window (in lock); high
impedance at all other times.
FIN
4
5
The input to the main counters. It is normally driven from a prescaler, which may be AC-coupled or,
when a full logic swing is available, may be DC-coupled.
VSS
VDD
NC
5
6
–
6
7
8
Negative supply (ground).
Positive supply (normally 5V)
Not connected.
OSC IN/
OSC OUT
7, 8 9,10
These pins form an on-chip reference oscillator when a series resonant crystal is connected across
them. Capacitors of appropriate value are also required between each end of the crystal and ground
to provide the necessary additional phase shift. The addition of a 220Ωresistor between OSC OUT and
the crystal will improve stability. An external reference signal may, alternatively, be applied to OSC IN.
This may be a low-level signal, AC-coupled, or if a full logic swing is available it may be DC-coupled.
The program range of the reference counter is 3 to 2047 , with the total division ratio being twice the
programmed number.
NC
9
–
Not connected.
DATA
10
12
Information on this input is transferred to the internal data latches during the appropriate data read time
slot. DATA is high for a ‘1’ and low for a ‘0’. There are three data words which control the NJ88C22;
MSB is first in the order: ‘A’ (7 bits), ‘M’ (10 bits), ‘R’ (11 bits).
CLOCK
11
12
13
14
Data is clocked on the negative transition of the CLOCK waveform. If less than 28 negative clock
transitions have been received when the ENABLE line goes low (i.e., only ‘M’ and ‘A’ will have been
clockedin), thenthe‘R’counterlatchwillremainunchangedandonly‘M’and‘A’willbetransferredfrom
the input shift register to the counter latches. This will protect the ‘R’ counter from being corrupted by
any glitches on the clock line after only ‘M’ and ‘A’ have been loaded If 28 negative transitions have
been counted, then the ‘R’ counter will be loaded with the new data.
ENABLE
When ENABLE is low, the DATA and CLOCK inputs are disabled internally. As soon as ENABLE is
high, the DATA and CLOCK inputs are enabled and data may be clocked into the device. The data is
transferred from the input shift register to the counter latches on the negative transition of the ENABLE
input and both inputs to the phase detector are synchronised to each other.
CAP
MC
13
14
15
16
This pin allows an external capacitor to be connected in parallel with the internal ramp capacitor and
allows further programming of the device. (This capacitor is connected from CAP to VSS).
Moduluscontroloutputforcontrollinganexternaldual-modulusprescaler.MCwillbelowatthebeginning
of a count cycle and will remain low until the ‘A’ counter completes its cycle. MC then goes high and
remains high until the ‘M’ counter completes its cycle, at which point both ‘A’ and ‘M’ counters are reset.
This gives a total division ratio of MP1A, where P and P11 represent the dual-modulus prescaler
values. The program range of the ‘A’ counter is 0-127 and therefore can control prescalers with a
division ratio up to and including 4128/129. The programming range of the ‘M’ counter is 8-1023
and, for correct operation, M>A. Where every possible channel is required, the minimum total division
ratio N should be: N>P 22P, where N = MP1A.
An external sample and hold phase comparator gain programming resistor should be connected
RB
CH
15
16
17
18
between this pin and VSS
.
An external hold capacitor should be connected between this pin and VSS
.
3
NJ88C22
2·0
8
7
6
5
4
3
2
1
V
= 5V
DD
V
= 5V
DD
F
= LOW FREQUENCY
IN
OSC IN, F = 0V TO 5V SQUARE WAVE
IN
0V TO 5V SQUARE WAVE
1·5
1·0
0·5
OSC IN
10MHz
1MHz
F
IN
TOTAL SUPPLY CURRENT IS
THE SUM OF THAT DUE TO F
AND OSC IN
IN
1
2
3
4
5
6
7
8
9
10
0·2 0·4
0·6
0·8
1·0
1·2
1·4
1·6
INPUT FREQUENCY (MHz)
INPUT LEVEL (V RMS)
Fig. 3 Typical supply current v. input frequency
Fig. 4 Typical supply current v. input level, OSC IN
PROGRAMMING
Reference Divider Chain
Note that M>A and
The comparison frequency depends upon the crystal
oscillator frequency and the division ratio of th ‘R’ counter,
which can be programmed in the range 3 to 2047, and a fixed
divide by two stage.
fVCO
fcomp
N =
For example, if the desired VCO frequency = 275MHz, the
comparison frequency is 12·5kHz and a two-modulus prescaler
of 464/65 is being used, then
fosc
23fcomp
R =
where fosc = oscillator frequency,
2753106
12·53103
N =
= 223103
fcomp = comparison frequency,
R = ‘R’ counter ratio
For example, where the crystal frequency = 10MHz and a
channelspacingcomparisonfrequencyof12·5kHzisrequired,
Now, N = MP1A, which can be rearranged as N/P = M1A/P.
In our example we have P = 64, therefore
107
2312·53103
223103
A
64
R =
= 400
= M1
64
such that M = 343 and A /64 = 0·75.
Thus,the‘R’registerwouldbeprogrammedto400expressed
in binary. The total division ratio would then be 23400 = 800
since the total division ratio of the ‘R’ counter plus the42 stage
is from 6 to 4094 in steps of 2.
Now, M is programmed to the integer part = 343 and A is
programmed to the fractional part364 i.e., A = 0·75364 = 48.
NB The minimum ratio N that can be used is P 22P (= 4032 in
our example) for all contiguous channels to be available.
To check: N = 343364148 = 22000, which is the required
division ratio and is greater than 4032 ( = P 22P ).
Whenre-programming,aresettozeroisfollowedbyreloading
with the new counter values, which means that the loop lock-up
time will be well defined and less than 10ms. If shorter lock-up
timesarerequired,whenmakingonlysmallchangesinfrequency,
the non-resettable NJ88C28 should be considered.
VCO Divider Chain
Thesynthesisedfrequencyofthevoltagecontrolledoscillator
(VCO) will depend on the division ratios of the ‘M’ and ‘A’
counters, the ratio of the external two-modulus prescaler
(P/P11)and the comparison frequency .
The division ratio N = MP1A,
where M is the ratio of the ‘M’ counter in the range 8 to 1023
and A is the ratio of the ‘A’ counter in the range 0 to 127.
t
t
CL
CH
CLOCK
ENABLE
DATA
t
t
ES
t
t
t
ES
EH
EH
t
DS
DH
Fig. 5 Timing diagram showing timing periods required for correct operation
4
NJ88C22
1
2
(15)26
(16)27
(17)28
3
4
5
CLOCK
ENABLE
DATA
A
A
A
A
A
(M )R
(M )R
(M )R
0 0
6
5
4
3
2
2
2
1
1
Fig.6 Timing diagram showing programming details
PHASE COMPARATORS
Noise output from a synthesiser loop is related to loop gain:
KPD KVCO
is sampled at the reference frequency to give the ‘fine’ error
signal, PDA. When in phase lock, this output would be typically
at (VDD2VSS)/2 and any offset from this would be proportional
to phase error.
The relationship between this offset and the phase error is
the phase comparator gain, KPDA, which is programmable with
an external resistor, RB, and a capacitor, CAP. An internal
50pF capacitor is used in the sample and hold comparator.
N
where KPD is the phase detector constant (volts/rad), KVCO is
theVCOconstant(rad/sec/volt)andNistheoverallloopdivision
ratio. When N is large and the loop gain is low, noise may be
reduced by employing a phase comparator with a high gain.
The sample and hold phase comparator in the NJ88C22 has
a high gain and uses a double sampling technique to reduce
spurious outputs to a low level.
CRYSTAL OSCILLATOR
When using the internal oscillator, the stability may be
enhanced at high frequencies by the inclusion of a resistor
between the OSC OUT pin and the other components. A value
of between 150Ω and 270Ω is advised, depending on the
crystal series resistance.
Astandarddigitalphase/frequencydetectordrivingathree-
state output,PDB, provides a ‘coarse’ error signal to enable
fast switching between channels.
The PDB output is active until the phase error is within the
sample and hold phase detector window, when PDB becomes
high impedance. Phase-lock is indicated at this point by a low
level on LD. The sample and hold phase detector provides a
‘fine’ error signal to give further phase adjustment and to hold
theloopinlock. Aninternallygeneratedramp, controlledbythe
digital output from both the reference and main divider chains,
PROGRAMMING/POWER UP
Data and signal input pins should not have input applied to
them prior to the application of VDD, as otherwise latch-up may
occur.
5
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