NJ88C25KAMP [ZARLINK]
FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE); 频率合成器（微处理器串行接口）
| 型号： | NJ88C25KAMP |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE) |
| 文件： | 总8页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
NJ88C25 IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
DS3280-1.3
NJ88C25
FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE)
The NJ88C25 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-holdcomparators, 10-bitprogrammable‘M’counter,
7-bit programmable ‘A’ counter, latched and buffered Band 0 and
Band 1 outputs and the necessary control and latch circuitry for
accepting and latching the input data.
Dataispresentedseriallyunderexternalcontrolfromasuitable
microprocessor. Although 30 bits of data are initially required to
programallcounters, subsequentupdatingcanbeabbreviatedto
19 bits, when only the ‘A’, ‘M’ and ‘B’ counters require changing.
The NJ88C25 is intended to be used in conjunction with a two-
modulus prescaler such as the SP8710 series to produce a
universal binary coded synthesiser.
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
PDA
PDB
CH
RB
F
V
MC
LD
CAP
F
NJ88C25
ENABLE
CLOCK
DATA
BAND 1
OSC OUT
IN
V
SS
V
DD
BAND 0
OSC IN
DG18, DP18, MP18
FEATURES
Fig.1 Pin connections - top view
■
■
■
Low Power Consumption
ABSOLUTE MAXIMUM RATINGS
High Performance Sample and Hold Phase Detector
Serial Input with Fast Update Feature
Supply voltage, VDD2VSS
:
20·5V to 7V
Input voltage
Open drain output, pins 3 and 4:
All other pins:
7V
ORDERING INFORMATION
V
SS20·3V to VDD10·3V
NJ88C25 KA DG Ceramic DIL Package
NJ88C25 KA DP Plastic DIL Package
NJ88C25 KA MP Miniature Plastic DIL Package
Storage temperature:
265°C to 1150°C (DG package)
255°C to 1125°C
(DP and MP packages)
RB
17
CAP
15
CH
18
f
r
9
REFERENCE COUNTER
SAMPLE/HOLD
PHASE
DETECTOR
42
OSC IN
1
(11BITS)
PDA
10
OSC OUT
LATCH 6 LATCH 7 LATCH 8
‘R’ REGISTER
12
14
FREQUENCY/
PHASE
DETECTOR
2
4
DATA
ENABLE
f
PDB
V
13
‘M’ REGISTER
‘A’ REGISTER
‘B’ REGISTER
LATCH 6
CLOCK
LOCK DETECT (LD)
V
SS
LATCH 1 LATCH 2 LATCH 3
LATCH 4 LATCH 5
3
8
F
V
BAND 0
BAND 1
11
‘M’ COUNTER
(10 BITS)
‘A’ COUNTER
(7 BITS)
V
SS
5
F
IN
MODULUS
CONTROL
OUTPUT (MC)
16
CONTROL LOGIC
7
6
V
DD
V
SS
Fig.2 Block diagram
NJ88C25
ELECTRICAL CHARACTERISTICS AT VDD = 5V
Test conditions unless otherwise stated:
V
DD–VSS=2·7V to 5·5V. Temperature range = –30°C to +70°C
DC Characteristics
Value
Characteristic
Units
Conditions
Min.
Typ. Max.
Supply current
5·5
0·7
3·7
mA
mA
mA
f
f
f
, fFIN = 20MHz
, fFIN = 1MHz
, fFIN = 10MHz
osc
osc
osc
0 to 5V
square
wave
OUTPUTS
Modulus Control (MC), BAND 1 and BAND 2
High level
Low level
VDD20·4
V
V
ISOURCE = 1mA
SINK = 1mA
0·4
I
Lock Detect (LD) and FV
Low level
Open drain pull-up voltage
PDB
0·4
7·0
V
V
ISINK = 4mA
High level
4·6
V
ISOURCE = 4mA
Low level
0·4
V
ISINK = 4mA
3-state leakage current
±0·1
µA
AC Characteristics
Characteristic
Value
Units
Conditions
Min. Typ.
Max.
F
IN and OSC IN input level
200
20
mV RMS 10MHz AC-coupled sinewave
Max. operating frequency, fFIN and f
Propagation delay, clock to modulus control MC
MHz
ns
Input squarewave VDD to VSS
See note 2
,
osc
30
50
Programming Inputs
Clock high time, tCH
Clock low time, tCL
Enable set-up time, tES (see note 5)
Enable hold time, tEH
Data set-up time, tDS
Data hold time, tDH
Clock rise and fall times
Positive threshold
0·5
0·5
0·2
0·2
0·2
0·2
0·2
3
µs
µs
µs
µs
µs
µs
µs
V
All timing periods
are referenced to
the negative
transition of the
clock waveform.
See note 5
tCH
TTL compatible, see note 1
Negative threshold
2
V
Phase Detector
Digital phase detector propagation delay
Gain programming resistor, RB
Hold capacitor, CH
Programming capacitor, CAP
Output resistance, PDA
500
ns
5
kΩ
nF
nF
kΩ
1
1
5
See note 3
NOTES
1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant
to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs.
4. The inputs to the device should be at logic ‘0’ when power is applied if latch-up conditions are to be avoided. This includes the OSC IN and
FIN inputs.
5. Clock to enable set-up time (tES) is variable, dependent on fOSC. It needs to be specified in terms of fOSC, clock high time (tCH) and clock low time
(tCL) and must meet the following conditions: 431/fOSC<tES,(tCH1tCL).
2
NJ88C25
PIN DESCRIPTIONS
Pin no.
Name
Description
1
PDA
Analog output from the sample and hold phase comparator for use as a ‘fine’ error signal. Voltage
increases as f (the output from the ‘M’ counter) phase lead increases; voltage decreases as f (the
v
r
output from the reference counter) phase lead increases. Output is linear over only a narrow phase
window, determined by gain (programmed by RB). In a type 2 loop, this pin is at (VDD2VSS)/2 when the
system is in lock.
2
PDB
Three-state output from the phase/frequency detector for use as a ‘coarse’ error signal.
f . f or f leading: positive pulses with respect to the bias point VBIAS
v
r
v
f , f or f leading: negative pulses with respect to the bias point VBIAS
v
r
r
f = f and phase error within PDA window: high impedance.
v
r
3
4
FV
This pin is an open drain output from the ‘M’ counter.
LD
An open-drain lock detect output at low level when phase error is within PDA window (in lock); high
impedance at all other times.
5
FIN
The input to the main counters. It is normally driven from a prescaler, which may be AC-coupled or,
when a full logic swing is available, may be DC-coupled.
6
7
VSS
VDD
Negative supply (ground).
Positive supply (normally 5V)
9,10
OSC IN/ These pins form an on-chip reference oscillator when a series resonant crystal is connected across
OSC OUT them. Capacitors of appropriate value are also required between each end of the crystal and ground
to provide the necessary additional phase shift. The addition of a 220Ωresistor between OSC OUT and
the crystal will improve stability. An external reference signal may, alternatively, be applied to OSC IN.
This may be a low-level signal, AC-coupled, or if a full logic swing is available it may be DC-coupled.
The program range of the reference counter is 3 to 2047 , with the total division ratio being twice the
programmed number.
8, 11
12
BAND 0/1 Two latch outputs, providing an output of the data from the ‘B’ register.
DATA
Information on this input is transferred to the internal data latches during the appropriate data read time
slot. DATA is high for a ‘1’ and low for a ‘0’. There are four data words which control the NJ88C25; MSB
is first in the order: ‘A’ (7 bits), ‘M’ (10 bits), ]B’ (2 bits) and ‘R’ (11 bits).
13
CLOCK
Data is clocked on the negative transition of the CLOCK waveform. If less than 30 negative clock
transitions have been received when the ENABLE line goes low (i.e., only ‘B’,‘M’ and ‘A’ will have been
clockedin), thenthe‘R’counterlatchwillremainunchangedandonly‘M’and‘A’willbetransferredfrom
the input shift register to the counter latches. This will protect the ‘R’ counter from being corrupted by
any glitches on the clock line after only ‘B’, ‘M’ and ‘A’ have been loaded. If 30 negative transitions have
been counted, then the ‘R’ counter will be loaded with the new data.
14
ENABLE When ENABLE is low, the DATA and CLOCK inputs are disabled internally. As soon as ENABLE is
high, the DATA and CLOCK inputs are enabled and data may be clocked into the device. The data is
transferred from the input shift register to the counter latches on the negative transition of the ENABLE
input and both inputs to the phase detector are synchronised to each other.
15
16
CAP
This pin allows an external capacitor to be connected in parallel with the internal ramp capacitor and
allows further programming of the device. (This capacitor is connected from CAP to VSS).
Moduluscontroloutputforcontrollinganexternaldual-modulusprescaler.MCwillbelowatthebeginning
of a count cycle and will remain low until the ‘A’ counter completes its cycle. MC then goes high and
remains high until the ‘M’ counter completes its cycle, at which point both ‘A’ and ‘M’ counters are reset.
This gives a total division ratio of MP1A, where P and P11 represent the dual-modulus prescaler
values. The program range of the ‘A’ counter is 0-127 and therefore can control prescalers with a
division ratio up to and including 4128/129. The programming range of the ‘M’ counter is 8-1023
and, for correct operation, M>A. Where every possible channel is required, the minimum total division
ratio N should be: N>P 22P.
MC
An external sample and hold phase comparator gain programming resistor should be connected
17
18
RB
CH
between this pin and VSS
.
An external hold capacitor should be connected between this pin and VSS
.
3
NJ88C25
8
7
6
5
4
3
2
1
2·0
V
= 5V
DD
V
= 5V
DD
F
= LOW FREQUENCY
IN
OSC IN, F = 0V TO 5V SQUARE WAVE
IN
0V TO 5V SQUARE WAVE
1·5
1·0
0·5
10MHz
OSC IN
F
IN
1MHz
TOTAL SUPPLY CURRENT IS
THE SUM OF THAT DUE TO F
AND OSC IN
IN
0·2 0·4
0·6
0·8
1·0
1·2
1·4
1·6
1
2
3
4
5
6
7
8
9
10
INPUT LEVEL (V RMS)
INPUT FREQUENCY (MHz)
Fig. 3 Typical supply current v. input frequency
Fig. 4 Typical supply current v. input level, OSC IN
PROGRAMMING
Reference Divider Chain
The comparison frequency depends upon the crystal
oscillator frequency and the division ratio of th ‘R’ counter,
which can be programmed in the range 3 to 2047, and a fixed
divide by two stage.
The division ratio N = MP1A,
where M is the ratio of the ‘M’ counter in the range 8 to 1023
and A is the ratio of the ‘A’ counter in the range 0 to 127.
Note that M>A and
fosc
23fcomp
fVCO
fcomp
R =
N =
where fosc = oscillator frequency,
For example, if the desired VCO frequency = 275MHz, the
comparisonfrequencyis12·5kHzandatwo-modulusprescaler
of 464/65 is being used, then
fcomp = comparison frequency,
R = ‘R’ counter ratio
For example, where the crystal frequency = 10MHz and a
channelspacingcomparisonfrequencyof12·5kHzisrequired,
2753106
12·53103
N =
= 223103
107
2312·53103
R =
= 400
Now, N = MP1A, which can be rearranged as N/P = M1A/P.
In our example we have P = 64, therefore
Thus,the‘R’registerwouldbeprogrammedto400expressed
in binary. The total division ratio would then be 23400 = 800
since the total division ratio of the ‘R’ counter plus the42 stage
is from 6 to 4094 in steps of 2.
223103
A
64
= M1
64
such that M = 343 and A /64 = 0·75.
VCO Divider Chain
Now, M is programmed to the integer part = 343 and A is
programmed to the fractional part364 i.e., A = 0·75364 = 48.
NB The minimum ratio N that can be used is P 22P (=4032 in
our example) for all contiguous channels to be available.
To check: N = 343364148 = 22000, which is the required
division ratio and is greater than 4032 ( = P 22P ).
Thesynthesisedfrequencyofthevoltagecontrolledoscillator
(VCO) will depend on the division ratios of the ‘M’ and ‘A’
counters, the ratio of the external two-modulus prescaler
(P/P11)and the comparison frequency .
t
t
CL
CH
CLOCK
ENABLE
DATA
t
t
ES
t
t
t
ES
EH
EH
t
DS
DH
Fig. 5 Timing diagram showing timing periods required for correct operation
4
NJ88C25
1
2
(17)28
(18)29
(19)30
3
4
5
CLOCK
ENABLE
DATA
A
A
A
A
A
(M )R
(B )R
(B )R
0 0
6
5
4
3
2
2
2
1
1
Fig.6 Timing diagram showing programming details
PHASE COMPARATORS
Noise output from a synthesiser loop is related to loop gain:
KPD KVCO
sample and hold phase detector window, when PDB becomes
high impedance. Phase-lock is indicated at this point by a low
level on LD. The sample and hold phase detector provides a
‘fine’ error signal to give further phase adjustment and to hold
theloopinlock. Aninternallygeneratedramp, controlledbythe
digital output from both the reference and main divider chains,
is sampled at the reference frequency to give the ‘fine’ error
signal, PDA. When in phase lock, this output would be typically
at (VDD2VSS)/2 and any offset from this would be proportional
to phase error.
The relationship between this offset and the phase error is
the phase comparator gain, KPDA, which is programmable with
an external resistor, RB, and a capacitor, CAP. An internal
50pF capacitor is used in the sample and hold comparator.
N
where KPD is the phase detector constant (volts/rad), KVCO is
theVCOconstant(rad/sec/volt)andNistheoverallloopdivision
ratio. When N is large and the loop gain is low, noise may be
reduced by employing a phase comparator with a high gain.
The sample and hold phase comparator in the NJ88C25 has
a high gain and uses a double sampling technique to reduce
spurious outputs to a low level.
Astandarddigitalphase/frequencydetectordrivingathree-
state output,PDB, provides a ‘coarse’ error signal to enable
fast switching between channels.
The PDB output is active until the phase error is within the
5
NJ88C25
CUSTOMER SERVICE CENTRES
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Tx: 602858F
Fax : (1) 64 46 06 07
HEADQUARTERS OPERATIONS
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
• GERMANY Munich Tel: (089) 3609 06-0 Tx: 523980 Fax : (089) 3609 06-55
• ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
• JAPAN Tokyo Tel: (03) 3296-0281 Fax: (03) 3296-0228
• NORTH AMERICA Integrated Circuits and Microwave Products Scotts Valley, USA
Tel (408) 438 2900 Fax: (408) 438 7023.
Hybrid Products, Farmingdale, USA Tel (516) 293 8686
Fax: (516) 293 0061.
• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
• SWEDEN Stockholm, Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
• UNITED KINGDOM & SCANDINAVIA
Wiltshire SN2 2QW, United Kingdom.
Tel: (0793) 518000
Fax: (0793) 518411
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017
1500 Green Hills Road,
Scotts Valley, California 95067-0017,
United States of America.
Tel: (408) 438 2900
Swindon Tel: (0793) 518510 Tx: 444410 Fax : (0793) 518582
These are supported by Agents and Distributors in major countries world-wide.
Fax: (408) 438 5576
GEC Plessey Semiconductors 1992 Publication No. DS3280 Issue No. 1.3 May 1992
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded
as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company
reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information
and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
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