P11C68-45DPBS [ZARLINK]
CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM; CMOS / SNOS NVSRAM高性能为8K ×8非易失性静态RAM
| 型号： | P11C68-45DPBS |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
| 文件： | 总17页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY INFORMATION
DS3600-1.2 September 1992
P10C68/P11C68
(Previously PNC10C68 and PNC11C68
)
CMOS/SNOS NVSRAM
HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM
(Supersedes DS3159-1.3, DS3160-1.3, DS3234-1.1, DS3235-1.1)
The P10C68 and P11C68 are fast static RAMs (35 and 45
ns) with a non-volatile electically-erasable PROM (EEPROM)
cell incorporating in each static memory cell. The SRAM can
be read and written an unlimited number of times while
independent non-volatile data resides in PROM.
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
NE
A12
On the P10C68 data may easily be transferred from the
SRAM to the EEPROM (STORE) and from the EEPROM back
to the SRAM ( RECALL) using the NE (bar) pin. The Store and
Recall cycles are initiated through software sequences on the
P11C68. These devices combine the high performance and
ease of use of a fast SRAM with the data integrity of non-
volatility.
The P10C68 and P11C68 feature the industry standard
pinout for non-volatile RAMs in a 28-pin 0.3-inch plastic and
ceramic dual-in-line packages.
3
NC
A8
A7
A6
4
5
A9
A5
6
A11
G
A4
7
A3
8
A10
E
A2
9
A1
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
A0
DQ0
DQ1
DQ2
Vss
FEATURES
I Non-Volatile Data Integrity
Pin Name
Function
I 10 year Data Retention in EEPROM
I 35ns and 45ns Address and Chip Enable Access Times
I 20ns and 25ns Output Enable Access
I Unlimited Read and Write to SRAM
I Unlimited Recall Cycles from EEPROM
I 104 Store Cycles to EEPROM
I Automatic Recall on Power up
I Automatic Store Timing
A - A
W
Address inputs
Write enable
Data in/out
Chip enable
Output enable
Power (+5V)
Ground
Non volatile enable P10C68
No connection
0
12
DQ - DQ
0
7
E
G
V
CC
V
SS
Pin 1 NE
Pin 1 N/C
P11C68
I Hardware Store Protection
Figure 1. Pin connections - top view.
I Single 5V ꢀ 10% Operation
I Available in Standard Package 28-pin 0.3-inch DIL
plastic and ceramic
I Commercial and Industrial temperature ranges
ORDERING INFORMATION
(See back page)
1
P10C68/P11C68
EEPROM ARRAY
256 x 256
A3
A4
A5
A6
A7
A8
A9
A12
R
O
W
STORE
D
E
C
O
D
E
R
STATIC RAM
ARRAY
256 x 256
RECALL
STORE/
RECALL
CONTROL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN I/O
COLUMN DECODER
I
N
P
U
T
B
U
F
F
E
R
S
A0 A1 A2 A10 A11
G
NE (P10C68 only)
E
W
F
igure 2. Logic block diagram.
2
P10C68/P11C68
ABSOLUTE MAXIMUM RATINGS
Voltage on typical input
relative to VSS
NOTE
Stresses greater than those listed in the Absolute
Maximum Ratings may cause permanent damage to the
device. These are stress ratings only; functional operation of
the device at any other conditions than those indicated in the
operational sections of the specification is not implied.
Exposure to absolute maximum ratings conditions for
extended periods may affect reliability.
-0.6V to 7.0V
-0.5V to (Vcc + 0.5V)
-55°C to + 125°C
-65°C to + 150°C
1W
Voltage on DQ0-7 and G(bar)
Temperature under Bias
Storage temperature
Power dissipation
DC output current
15mA
(one output at a time, one second duration)
DC OPERATING CONDITIONS
Value
Parameter
Symbol
Units
Conditions
Typ.
Max.
Min.
Supply voltage
V
V
V
V
V
V
5.0
CC
IH
IL
Input logic '1' voltage
Input logic '0' voltage
Ambient operating temperature
commercial
All inputs
All inputs
V
CC
+0.5
0.8
2.2
V
-0.5
SS
oC
oC
T
T
+70
+85
0
-40
amb
amb
industrial
DC ELECTRICAL CHARACTERISTICS
Commercial temperature range
Test conditions (unless otherwise stated):
Tamb = 0°C to 70°C, Vcc = +5V (See notes 1, 2 and 3)
Value
Characteristic
Units
Conditions
Symbol
Min.
Max.
Average power supply
current
mA
mA
t
t
= 35ns
= 45ns
I
I
75
65
CC1
CC2
AVAV
AVAV
Average power supply current
during STORE cycle
mA
All inputs at V ≤ 0.2V
IN
50
Average power supply current
(standby, cycling TTL input levels)
mA
mA
t
t
= 35ns
= 45ns
I
I
23
20
SB1
AVAV
AVAV
E(bar) ≥V , all other inputs
cycling
IH
Average power supply current
(standby, stable CMOS input levels)
mA
E (bar)≥(V -0.2V), all other
1
SB2
CC
IN
inputs at V ≤0.2V or ≥(V
-
CC
0.2V)
Input leakage current (any input)
Off state output leakage current
Output logic '1' voltage
µA
µA
V
V
V
I
= max, V = V to V
IN SS
I
ꢀ1
ꢀ5
ILK
CC
CC
OUT
OUT
CC
CC
= max, V = V to V
I
OLK
IN
SS
= 4mA
= 8mA
V
V
2.4
OH
OL
Output voltage '0' voltage
V
I
0.4
NOTES
1.
I
is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC1
2.
Bringing E (bar) ≥ V will not produce standby currents levels until any non-volatile cycle in progress has timed out. See
IH
Mode Selection table.
3.
I
is the average current required for the duration of the STORE cycle (t
) after the sequence that initiates the
STORE
CC2
cycle.
3
P10C68/P11C68
Industrial temperature range
Test conditions (unless otherwise stated):
Tamb = -40˚C to 70˚C, Vcc = +5V ꢀ 10% (See notes 4, 5 and 6)
Value
Characteristic
Symbol
Units
Conditions
Min.
Max.
Average power supply
current
mA
mA
t
t
= 35ns
= 45ns
I
80
75
AVAV
AVAV
CC1
Average power supply current
during STORE cycle
mA
All inputs at V ≤ 0.2V
IN
I
50
CC2
Average power supply current
(standby, cycling TTL input levels)
mA
mA
t
t
= 35ns
= 45ns
I
27
23
AVAV
AVAV
SB1
E(bar) ≥V , all other inputs
IH
cycling
Average power supply current
(standby, stable CMOS input levels)
mA
E (bar)≥(V
-0.2V), all other
CC
I
1
SB2
inputs at V ≤0.2V or ≥(V
-
IN
CC
0.2V)
Input leakage current (any input)
Off state output leakage current
Output logic '1' voltage
Output voltage '0' voltage
µA
µA
V
V
V
I
= max, V = V to V
IN SS
I
ꢀ1
ꢀ5
CC
CC
OUT
OUT
CC
CC
ILK
= max, V = V to V
I
IN
SS
OLK
= 4mA
= 8mA
V
V
2.4
OH
OL
V
I
0.4
NOTES
4.
I
is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC1
5.
Bringing E (bar) ≥ V will not produce standby currents levels until any non-volatile cycle in progress has timed out. See
IH
Mode Selection table.
6.
I
is the average current required for the duration of the STORE cycle (t
) after the sequence that initiates the
CC2
STORE
cycle.
AC TEST CONDITIONS
Input pulse levels
V
SS
to 3V
Input rise and fall times
Input and output timing reference levels
Output load
≤5ns
5.0V
1.5V
See Figure 3
480 Ohms
OUTPUT
CAPACITANCE T
= 25°C, f = 1.0MHz (see note 7)
amb
255
Ohms
30p
Conditions
Parameter
Symbol Max. Units
INCLUDING
SCOPE AND
FIXTURE
Input capacitance
Output capacitance
C
5
7
pF
pF
∆V=0 to 3V
∆V=0 to 3V
IN
C
OUT
NOTE
Figure 3. AC output loading.
7. These parameters are characterised but not 100% tested.
4
P10C68/P11C68
SRAM MEMORY OPERATION
Test conditions (unless otherwise stated):
Commercial and Industrial Temperature Range
Tamb = -40°C to + 85°C, Vcc = + 5V ꢀ 10%
READ CYCLES 1 AND 2 (See note 8)
P10C68-45
P11C68-45
P10C68-35
P11C68-35
Symbol
Units
Parameter
Notes
Min.
Max.
Max.
Min.
Standard
Alternative
Chip enable access time
Read cycle time
Address access time
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
ACS
ELQV
35
9
10
45
t
t
RC
AVAV
35
20
45
25
t
t
AA
OE
OH
AVQV
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Outout disable to output inactive
Chip enable to power active
Chip disable to power standby
Write recovery time
t
t
t
GLQV
5
5
5
5
t
AXQX
t
t
LZ
ELQX
20
15
25
20
11
t
t
OHZ
EHQZ
0
0
0
0
t
t
OLZ
GLQX
11
12
12
t
t
t
t
HZ
PA
PS
GHQZ
t
t
ELICCH
EHICCL
25
45
25
55
t
t
WR
WHQV
NOTES
8.
E (bar), G (bar) and W (bar) must make the transition between VIH(min) to VIL(max), or VIL(max) to VIH(min) in a
monotonic fashion. NE (bar) must be ≥ VIH during entire cycle.
For READ CYCLE 1 and 2, W (bar) and NE (bar) must be high for entire cycle.
Device is continuously selected with E (bar) low, and G (bar) low.
Measured ꢀ200mV from steady state output voltage. Load capacitance is 5pF.
Parameter guaranteed but not tested.
9.
10.
11.
12.
tAVAV
ADDRESS
tAVQV
tAXQX
DQ (DATA OUT)
W
DATA VALID
tWHQV
Figure 4. READ CYCLE 1 timing diagram (see notes 9 and 10).
5
P10C68/P11C68
tAVAV
ADDRESS
E
tEHICCL
tELQV
tELQX
tEHQZ
tGLQV
G
tGHQZ
tGLQX
DQ (DATA OUT)
ACTIVE
DATA VALID
tELICCH
ICC
STANDBY
W
tWHQV
F
igure 5. READ CYCLE 2 timing diagram (see note 9).
WRITE CYCLE 1 : W (BAR) CONTROLLED (See notes 8 and 13)
Commercial and Industrial Temperature Range
P10C68-45
P11C68-45
P10C68-35
P11C68-35
Max.
Symbol
Alternative
Units
Notes
Parameter
Min.
Max.
Min.
Standard
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
Write pulse width
45
35
35
30
0
35
0
0
t
t
t
t
45
35
35
30
0
35
0
0
t
AVAV
WC
WP
CW
DW
DH
AW
t
WLWH
Chip enable to end of write
Data set-up to end of write
Data hold after end of write
Address set-up to end of write
Address set-up to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
t
ELWH
DVWH
WHDX
AVWH
t
t
t
t
t
t
t
t
AVWL
AS
t
WHAX
WR
35
11, 14
35
t
t
t
WLQZ
WHQZ
WZ
5
t
5
OW
NOTES
13.
14.
E (bar) or W (bar) must be ≥ VIH during address transitions.
If W (bar) is low when E (bar) goes low, the outputs remain in the high impedance state.
6
P10C68/P11C68
tAVAV
ADDRESS
E
tWHAX
tELWH
tAVWH
tWLWH
tAVWL
W
tDVWH
tWHDX
DATA IN
DATA VALID
tWHQX
tWLQZ
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
F
igure 6. WRITE CYCLE 1: W (bar) controlled timing diagram (see notes 8 and 13).
WRITE CYCLE 2 : E (BAR) CONTROLLED (See notes 8 and 13)
P10C68-45
P11C68-45
P10C68-35
P11C68-35
Max.
Symbol
Standard Alternative
Units
Notes
Parameter
Min.
Max.
Min.
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
Write pulse width
45
35
35
30
0
35
0
0
45
35
35
30
0
35
0
0
t
t
t
t
t
WC
WP
CW
DW
AVAV
t
WLEH
Chip enable to end of write
Data set-up to end of write
Data hold after end of write
Address set-up to end of write
Address hold after end of write
Address set-up to start of write
t
t
t
ELEH
DVEH
EHDX
t
DH
AW
WR
t
t
t
t
t
AVEH
EHAX
AVWL
t
AS
tAVAV
ADDRESS
tAVEL
tELEH
tEHAX
E
tAVEH
tWLEH
W
tDVEH
DATA VALID
tEHDX
DATA IN
HIGH IMPEDANCE
DATA OUT
F
igure 7. WRITE CYCLE 2: E (bar) controlled timing diagram (see notes 8 and 13).
7
P10C68/P11C68
VCC
5.0V
3.3V
t
AUTO RECALL
STORE INHIBIT
Figure 8. Automatic RECALL and STORE inhibit.
NON-VOLATILE MEMORY OPERATION OF P10C68
MODE SELECTION
E
H
L
L
L
L
L
L
G
X
L
NE
X
H
H
L
Mode
Power
Standby
W
X
H
L
Not selected
Read RAM
Write RAM
Active
Active
Active
X
L
Non-volatile recall (Note 15)
Non-volatile store
H
L
H
L
L
I
CC2
L
No operation
Active
L
H
X
H
NOTE
15.
An automatic RECALL also takes place on chip power-up, starting when Vcc exceeds 3.3V, and taking t
from the
RECALL
time at which Vcc exceeds 3.3V. Vcc must not drop below 3.3V once it has exceeded it for the RECALL to function
properly.
STORE CYCLE 1 : W (BAR) CONTROLLED (See note 16)
P10C68-35
Max.
10
0
0
45
0
P10C68-45
Symbol
Units
Notes
17
Parameter
Min.
Max.
10
Alternative
Min.
Standard
ms
ns
ns
ns
ns
Store cycle time
t
t
t
t
t
WLQX
STORE
Output disable set-up to NE (bar) fall
Non-volatile set-up to write low
Write low to NE (bar) rise
Chip enable SET-UP
0
0
45
0
GHNL
NLWL
WLNH
18
t
WC
t
ELWL
8
P10C68/P11C68
STORE CYCLE 2 : E (BAR) CONTROLLED (See note 13)
P10C68-45
Symbol
P10C68-35
Min. Max.
10
0
0
Parameter
Units
Notes
17
Max.
Min.
Alternative
Standard
ms
ns
ns
ns
ns
Store cycle time
10
t
t
ELQX1
STORE
NE (bar) set-up to chip enable
Write enable wet-up to chip enable
Chip enable to NE (bar) rise
Output disable set-up to E (bar) fall
0
0
45
0
t
NLEL
t
t
t
WLEL
ELNH
GHEL
18
45
0
t
WC
NOTES
16. E (bar), G (bar), NE (bar) and W (bar) must make the transition between VIH(max) to VIL(max), or VIL(max) to VIH(min) in a
monotonic fashion.
17. Measured with W (bar) and NE (bar) both returned high, and G (bar) returned low. Note that store cycles are inhibited/aborted
by Vcc <3.3V (STORE inhibit).
18. Once twc has been satisfied by NE (bar), G (bar), W (bar) and E (bar) the store cycle is completed automatically, ignoring all
inputs. Any of NE (bar), G (bar), W (bar) or E (bar) may be used to terminate the store initiation cycle.
NE
G
tGHNL
tNLWL
tWLNH
W
E
tELWL
tWLQX
HIGH IMPEDANCE
DQ
(DATA
OUT)
Figure 9. STORE CYCLE 1: W (bar) controlled timing diagram (see note 16).
tNLEL
NE
tGHEL
G
tWLEL
W
tELNH
E
tELQX1
DQ
(DATA
OUT)
HIGH IMPEDANCE
Figure 10. STORE CYCLE 2: E (bar) controlled timing diagram (see note 16).
9
P10C68/P11C68
P10C68 RECALL CYCLE 1 : NE (BAR) CONTROLLED (See note 16)
P10C68-35
Max.
P10C68-45
Symbol
Alternative
Parameter
Units
Notes
Min.
Max.
Min.
Standard
19
20
Recall cycle time
20
µs
µs
ns
ns
ns
ns
20
t
t
t
t
RECALL
NLQX
NLNH
GLNL
Recall initiation cycle time
Output enable set-up
Write enable set-up
Chip enable set-up
NE (bar) fall to output inactive
25
0
0
25
0
0
t
RC
t
WHNL
0
0
t
t
ELNL
NLQZ
25
25
P10C68 RECALL CYCLE 2 : E (BAR) CONTROLLED (See note 16)
P10C68-35
Max.
20
25
0
0
P10C68-45
Symbol
Parameter
Units
Notes
Standard
Min.
Max.
Min.
Alternative
19
20
t
t
Recall cycle time
Recall initiation cycle time
NE (bar) set-up
Output enable set-up
Write enable set-up
µs
ns
ns
ns
ns
20
t
ELQX2
RECALL
25
0
0
t
ELNH
NLEL
GLEL
RC
t
t
t
0
0
WHEL
P10C68 RECALL CYCLE 3 : G (BAR) CONTROLLED (See note 16)
P10C68-35
Max.
20
25
0
0
P10C68-45
Symbol
Parameter
Units
Notes
Standard
Min.
Max.
Alternative
Min.
19
20
t
t
µs
ns
ns
ns
ns
Recall cycle time
Recall initiation cycle time
NE (bar) set-up
Write enable set-up
Chip enable set-up
20
t
GLQX2
RECALL
t
25
0
0
GLNH
NLGL
WHGL
ELGL
RC
t
t
t
0
0
NOTES
19.
Measured with W (bar) and NE (bar) both returned high, and G (bar) returned low. Address transitions may not occur on
any address pin during this time.
20.
Once t has been satisfied by NE (bar), G (bar), W (bar) and E (bar) the RECALL cycle is completed automatically. Any
RC
of NE (bar), G (bar) or E (bar) may be used to terminate the RECALL initiation cycle.
10
P10C68/P11C68
tNLHN
NE
G
tGLNL
W
E
tWHNL
tELNL
tNLQX
tNLQZ
DQ
(DATA
OUT)
HIGH IMPEDANCE
F
igure 11. P10C68 RECALL CYCLE 1: NE (bar) controlled timing diagram (see note 16).
tNLEL
NE
G
tGLEL
W
E
tWHEL
tELNH
tELQX2
DQ
(DATA
OUT)
HIGH IMPEDANCE
Figure 12. P10C68 RECALL CYCLE 2: E (bar) controlled timing diagram (see note 16).
tNLGL
NE
tGLNH
G
tWHGL
W
E
tELGL
tGLQX2
DQ
(DATA
OUT)
HIGH IMPEDANCE
Figure 13. P10C68 RECALL CYCLE 3: E (bar) controlled timing diagram (see note 16).
11
P10C68/P11C68
NON-VOLATILE MEMORY OPERATION OF P11C68
MODE SELECTION
E
H
L
W
X
H
L
A
12
-A (hex)
0
Mode
Not selected
I/O
Power
Standby
Active
Notes
X
Output High Z
Output data
Input Data
X
Read RAM
22
L
X
Write RAM
Active
L
H
0000
1555
0AAA
1FFF
10F0
0F0F
0000
1555
0AAA
1FFF
10F0
0F0E
Read RAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
21, 22
21, 22
21, 22
21, 22
21, 22
20
Read RAM
Read RAM
Read RAM
Read RAM
Non-volatile STORE
Read RAM
I
CC2
L
H
Active
21, 22
21, 22
21, 22
21, 22
21, 22
21
Read RAM
Read RAM
Read RAM
Read RAM
Non-volatile RECALL
NOTES
21.
The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or
(0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W (bar) must be high during all six consecutive cycles. See
STORE CYCLE and RECALL CYCLE tables and diagrams for further details.
22.
I/O state assumes that G (bar) ≥V . Activation of non-volatile cycles does not depend on the state of G (bar).
IL
STORE / RECALL CYCLES 1 AND 2 (See notes 24 and 29)
P11C68-45
P11C68-35
Max.
Symbol
Parameter
Units
Notes
Min.
Max.
Min.
Alternative
Standard
ns
ns
Read cycle time
Skew between sequentially
adjacent addresses
35
45
t
t
t
AVAV
AXAV
ACS
5
23
5
t
SKEW
75
10
20
ns
ms
µs
ns
ns
ns
25
26
26, 30
27
27
27
Address valid to output inactive
Store cycle time
Recall cycle time
Address set-up to chip enable
Chip enable pulse width
Chip disable to address change
75
10
20
t
t
AVQZ
ELQZ
t
t
STORE
RECALL
0
35
0
0
45
0
t
t
AVEL
ELEH
AE
t
t
t
EP
t
EHAX
EA
NOTES
23.
Skew spec may be avoided by using E (bar) (STORE/RECALL CYCLE 2).
24.
W (bar) ≥V during entire address sequence to initiate a non-volatile cycle.
IH
Required address sequences are shown in the Mode Selection table.
25.
26.
Once the software STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
Measured with W (bar) high, G (bar) low and E (bar) low. Note that STORE cycles (but not RECALLS) are aborted by Vcc
< 3.3V (STORE Inhibit).
27.
28.
29.
E (bar) must make the transition between V (max) to V (max), or V (max) to V (min) in a monotonic fashion.
Chip is continuously selected with E (bar) low.
IH
IL
IL
IH
Addresses 1 through 6 are found in the Mode Selection table. Address 6 determines whether the P11C68 performs a
STORE or RECALL. A RECALL cycle is performed automatically at power up when V exceeds 3.3V. V must not drop
CC
CC
below 3.3V once it has exceeded it for the RECALL to function properly, t
exceeds 3.3V.
is measured from the point at which V
RECALL
CC
30.
Address transitions may not occur on any address pin during this time.
12
P10C68/P11C68
tSKEW
tAVAV
tAVAV
tAVAV
INVALID
ADDRESS 1
ADDRESS 2
ADDRESS 6
ADDRESS
tSTORE / t RECALL
tAVQZ
DATA VALID
DQ
(DATA
OUT)
HIGH
IMPEDANCE
DATA VALID
DATA VALID
DATA VALID
Figure 14. STORE/RECALL cycle 1. Address controlled timing diagram (see notes 22, 26 and 27).
tAVAV
tAVAV
ADDRESS
ADDRESS 1
ADDRESS 6
tEHAX
tAVEL
tELEH
E
tSTORE / t RECALL
tELQZ
DATA VALID
DQ
(DATA
OUT)
HIGH
IMPEDANCE
DATA VALID
DATA VALID
Figure 15. STORE/RECALL cycle 2. E (bar) controlled timing diagram (see notes 22, 25 and 27).
OPERATING NOTES
If the READ is initiated by E (bar) or G (bar), the outputs will
be valid at tELQV or tGLQV, whichever is later. (READ CYCLE 2).
The data outputs will repeatedly respond to address changes
within the tAVQV access time without the need for transitions on
any control input pins and will remain valid until another
address change or until E (bar) or G (bar) is brought HIGH or
W (bar) or NE (bar) is brought LOW.
Note: References to NE (bar) should be taken as applying
to P10C68 only and can be ignored for P11C68.
The devices have two separate modes of operation: SRAM
mode and non-volatile mode. In SRAM mode, the memory
operates as an ordinary static RAM. While in non-volatile
mode, data is transferred in parallel from SRAM to EEPROM
or from EEPROM to SRAM.
SRAM WRITE
SRAM READ
A write cycle is performed whenever E (bar) and W (bar)
are LOW and NE (bar) is HIGH. The address inputs must be
stable prior to entering the WRITE cycle and must remain
stable until either E (bar) or W (bar) go HIGH at the end of the
cycle. The data on the eight pins DQ0-7, will be written into the
memory location specified by the address inputs if valid tDVWH
before the end of a W (bar) controlled WRITE or tDVEH before
the end of an E (bar) controlled WRITE.
The devices perform a read cycle when ever E (bar) and G
(bar) are LOW and NE (bar) and W (bar) are HIGH. The
address specified by the thirteen address pins A0-12 determine
which of the 8192 data bytes will be accessed. When the
READ is initiated by an address transistion, the outputs will be
valid after a delay of tAVQV (READ CYCLE 1).
13
P10C68/P11C68
The P11C68 STORE cycle is initiated by executing
sequential READ cycles from six specific address locations.
By relying on READ cycles only, the P11C68 implements non-
volatile operation while remaining pin-for-pin compatible with
standard 8Kx8 SRAMs. During the STORE cycle, an erase of
the previous non-volatile data is first performed, followed by a
program of the non-volatile elements. The program operation
copies the SRAM data into non-volatile storage. Once a
STORE cycle is initiated, further input and output are disabled
until the cycle is completed. Because a sequence of addresses
is used for STORE initiation, it is critical that no invalid address
states intervene in the sequence or the sequence will be
aborted. The maximum skew between address inputs A0-12
for each address state is tSKEW (STORE CYCLE 1).
It is recommended that G (bar) be kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G (bar) is left LOW, internal circuitry will
turn off the output buffers tWHQZ after W (bar) goes LOW.
Non-Volatile STORE - P10C68
A STORE cycle is performed when NE, (bar) E (bar) and W
(bar) are LOW and G (bar) is HIGH. While any sequence to
achieve this state will initiate a STORE, only W(bar) initiation
(STORE CYCLE 1) and E (bar) initiation (STORE CYCLE 2)
are practical without risking an unintentional SRAM WRITE
that would disturb SRAM data. During the STORE cycle,
previous non-volatile data is erased and the SRAM contents
are then programmed into non-volatile elements. Once a
STORE cycle is initiated, further input and output is disabled
If tSKEW is exceeded it is possible that the transitional data
state will be interpreted as a valid address and the sequence
will be aborted. If E (bar) controlled READ cycles are used for
the sequence (STORE CYCLE 2), address skew is no longer a
concern.
and the DQ
pins are tri-stated until the cycle is completed.
0-7
If E (bar) and G (bar) are LOW and W (bar) and NE (bar)
are HIGH at the end of the cycle, a READ will be performed
and the outputs will go active, signalling the end of the STORE.
To enable the STORE cycle the following READ sequence
must be performed.
The P10C68 will not be activated into either a STORE or
RECALL cycle by the software sequence required for the
P11C68.
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0F (hex) Initiate STORE Cycle
Hardware Protect - P10C68
The P10C68 offers two levels of protection to suppress
inadvertent STORE cycles. If the clock signals remain in the
STORE condition at the end of a STORE cycle, a second
STORE cycle will not be started. The STORE will be initiated
only after a HIGH to LOW transition on NE (bar)Because the
STORE cycle is initiated by an NE (bar) transition, powering-
up the chip with NE (bar) Low will not initiate a STORE cycle
either.
Once the sixth address in the sequence has been entered,
the STORE cycle will commence and the chip will be disabled.
It is important that READ cycles and not WRITE cycles be
used in the sequence, although it is not necessary that G (bar)
be LOW for the sequence to be valid. After the tSTORE cycle
time has been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
Once the first of the six reads has taken place, the read
sequence must either complete or terminate with an incorrect
address (other than 0000 hex) before it may be started anew.
In addition to multi-trigger protection, the P10C68 offers
hardware protection through Vcc Sense. A STORE cycle will
not be initiated, and one in progress will discontinue, if Vcc
goes below 3.3V.
Non-Volatile RECALL - P10C68
The P11C68 offers hardware protection against
inadvertent STORE cycles through Vcc Sense. A STORE
cycle will not be initiated, and one in progress will discontinue,
if Vcc goes below 3.3V.
A RECALL cycle is performed when E (bar), G (bar) and
NE (bar) are LOW and W (bar) is HIGH. Like the STORE cycle,
RECALL is initiated when the last of the four clock signals goes
to the RECALL state. Once initiated, the RECALL cycle will
take tNLQX to complete, during which all inputs are ignored.
When the RECALL completes, any READ or WRITE state on
the input pins will take effect.
Internally, RECALL is a two step procedure. First the
SRAM data is cleared and second, the non-volatile information
is transferred into the SRAM cells. The RECALL operation in
no way alters the data in the non-volatile cells. The non-volatile
data can be recalled an unlimited number of times. Address
transitions may not occur during the RECALL cycle. Like the
STORE cycle, a transition must occur on the NE (bar) pin to
cause a RECALL, preventing inadvertent multi-triggering. On
power-up, once Vcc exceeds Vcc sense voltage of 3.3V, a
RECALL cycle is automatically initiated. The voltage on the
Vcc pin must not drop below 3.3V once it has risen above it in
order for the RECALL to operate properly. Due to the
automatic RECALL, SRAM operation cannot commence until
tNLQX after Vcc exceeds 3.3V.
A RECALL of the EEPROM data into the SRAM is initiated
with a sequence of READ operations in a manner similar to the
STORE initiation. To initiate the RECALL cycle the following
sequence of READ operations must be performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0E (hex) Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second the non-volatile information
is transferred into the SRAM cells. The RECALL operation in
no way alters the data in the EEPROM cells. The non-volatile
data can be recalled an unlimited number of times. Address
transitions may not occur during the RECALL cycle.
14
P10C68/P11C68
On power-up, once Vcc exceeds the Vcc sense voltage of
3.3V, a RECALL cycle is automatically initiated. The voltage
on the Vcc pin must not drop below 3.3V once it has risen
above it in order for the RECALL to operate properly. Due to
this automatic RECALL, SRAM operation cannot commence
until tRECALL after Vcc exceeds 3.3V.
PACKAGE DETAILS
Dimensions are shown thus: mm (in). For further package
information please contact your local Customer Service
Centre.
The automatic RECALL feature can be adversely affected
by factors such as supply rise time, temperature and elapsed
time since the last STORE cycle. For this reason it is
recommended that the user initiate a RECALL cycle after
power-up for critical applications.
PIN 1
7.620/8.128
(0.300/0.320)
1.27 (0.050) TYP
35.20/35.92
(1.386/1.414)
1.016/1.524
(0.040/0.060)
0.229/0.308
(0.009/0.012)
1.930/2.39
(0.05576/0.094)
0.36/0.51
(0.014/0.020)
2.54
(0.100)
7.37/7.87
(0.290/0.310)
3.30/4.06
(0.130/0.160)
Figure 16, 28-lead sidebrazed ceramic DIL (0.3in) DCB
1.37 (34.8)
PIN 1
Pin 1 Ref. notch
0.288
(7.32)
Leads
0.3/0.55 (0.76/1.4)
0.2 (5.08) max
SEATING
PLANE
0.02 (0.51)
0.2/0.3
0.12 (3.05) min
Nominal Centres
0.3 (7.62)
0.1 (2.54)
0.015/0.02
(0.38/0.53)
Figure 17. 28 plastic DIL Package (0.3in) DPB
15
P10C68/P11C68
ORDERING INFORMATION
PxxC68 - xx / xG / DxBS
Device number
eg. 10 = hardware store/recall
11 = software store/recall
Package type
C = Ceramic
P = Plastic
Temperature range
C = Commercial
I = Industrial
Speed Grade
-35 = 35ns
-45 = 45ns
CUSTOMER SERVICE CENTRES
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Tx: 602858F
Fax : (1) 64 46 06 07
HEADQUARTERS OPERATIONS
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
• GERMANY Munich Tel: (089) 3609 06-0 Tx: 523980 Fax : (089) 3609 06-55
• ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
• JAPAN Tokyo Tel: (03) 3296-0281 Fax: (03) 3296-0228
• NORTH AMERICA Integrated Circuits and Microwave Products, Scotts Valley, USA
Tel (408) 438 2900 ITT Tx: 4940840 Fax: (408) 438 7023.
Hybrid Products, Farmingdale, USA Tel (516) 293 8686
Fax: (516) 293 0061.
• SOUTH EAST ASIA Singapore Tel: 2919291 Fax: 2916455
• SWEDEN Johanneshov Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
• UNITED KINGDOM & SCANDINAVIA
Wiltshire SN2 2QW, United Kingdom.
Tel: (0793) 518000 Tx: 449637
Fax: (0793) 518411
GEC PLESSEY SEMICONDUCTORS
Sequoia Research Park, 1500 Green Hills Road,
Scotts Valley, California 95066,
United States of America. Tel (408) 438 2900
ITT Telex: 4940840 Fax: (408) 438 5576
Swindon Tel: (0793) 518510 Tx: 444410 Fax : (0793) 518582
These are supported by Agents and Distributors in major countries world-wide.
© GEC Plessey Semiconductors Year Publication No. XX XXXX Issue No. X.X Month Year
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be
regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service.
The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and
does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any
equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to
perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
16
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”)
is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or
use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from
such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or
other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use
of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned
by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability,
performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee
that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any
equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily
include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
2
2
2
Purchase of Zarlink s I C components conveys a licence under the Philips I C Patent rights to use these components in and I C System, provided
2
that the system conforms to the I C Standard Specification as defined by Philips.
Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2001, Zarlink Semiconductor Inc. All Rights Reserved.
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