PDSP16116 [ZARLINK]

ALU and Barrel Shifter; ALU和桶式移位器


型号：	PDSP16116
厂家：	ZARLINK SEMICONDUCTOR INC
描述：	ALU and Barrel Shifter ALU和桶式移位器
文件：	总16页 (文件大小：121K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PDSP1601/PDSP1601A

ALU and Barrel Shifter

DS3705

ISSUE 3.0

November 1998

The PDSP1601 is a high performance 16-bit arithmetic

logic unit with an independent on-chip 16-bit barrel shifter.

The PDSP1601A has two operating modes giving 20MHz or

10MHz register-to-register transfer rates.

The PDSP1601 supports Multicycle multiprecision

operation. This allows a single device to operate at 20MHz for

16-bitfields, 10MHzfor32-bitfieldsand5MHzfor64-bitfields.

ThePDSP1601canalsobecascadedtoproducewiderwords

at the 20MHz rate using the Carry Out and Carry In pins. The

Barrel Shifter is also capable of extension, for example the

PDSP1601 can used to select a 16-bit field from a 32-bit input

in 100ns.

PIN 1A INDEX MARK

ON TOP SURFACE

11 10

AC84

FEATURES

■

16-bit, 32 instruction 20MHz ALU

16-bit, 20MHz Logical, Arithmetic or Barrel Shifter

Independent ALU and Shifter Operation

4 x 16-bit On Chip Scratchpad Registers

Multiprecision Operation; e.g. 200ns 64-bit

Accumulate

GC100

■

Three Port Structure with Three Internal Feedback

Paths Eliminates I/O Bottlenecks

■

Block Floating Point Support

300mW Maximum Power Dissipation

84-pin Pin Grid Array or 84 Contact LCC Packages

or 100 pin Ceramic Quad Flat Pack

Fig.1 Pin connections - bottom view

APPLICATIONS

ORDERING INFORMATION

■

Digital Signal Processing

Array Processing

Graphics

Database Addressing

High Speed Arithmetic Processors

PDSP1601 MC GGCR

10MHz MIL883 Screened -

QFP package

PDSP1601A BO AC

20MHz Industrial - PGA

package

N.B

Further details of the Military grade part are

available in a separate datasheet (DS3763)

ASSOCIATED PRODUCTS

PDSP16112 Complex Multiplier

PDSP16116 16 x 16 Complex Multiplier

PDSP16318 Complex Accumulator

PDSP16330 Pythagoras Processor

PDSP1601/PDSP1601A

PIN DESCRIPTION

AC pin

Function

Function AC pin

AC pin

F11

E11

E10

D11

D10

C11

B11

C10

A11

B10

A10

IS0

IS1

IS2

GND

C10

C11

C12

C13

C14

C15

IA4

MSB

MSS

B15

B14

B13

B12

B11

B10

GND

MSA0

MSA1

A15

A14

A13

A12

A11

A10

L10

L11

K10

J10

K11

J11

H10

H11

F10

G10

G11

IS3

SV0

SV1

SV2

SV3

SVOE

RS0

RS1

VCC

RS2

BFP

VCC

RA0

RA1

RA2

IA0

IA1

IA2

IA3

CEB

CLK

CEA

MSC

SIG

100

N/C

VCC

RS2

GND

N/C

VCC

RA0

RA1

RA2

N/C

CEA

MSC

IS0

IS1

IS2

IA0

IA1

IA2

IA3

CEB

CLK

GND

MSA0

MSA1

A15

A14

A13

A12

A11

A10

IA4

MSB

MSS

B15

B14

B13

B12

B11

B10

C10

C11

C12

C13

C14

C15

IS3

SV0

SV1

SV2

SV3

SVOE

RS0

RS1

BFP

N/C = not connected - leave open circuit

All GND and VDD pin must be used

PDSP1601/PDSP1601A

PIN DESCRIPTIONS

Symbol

Description

ALU B-input multiplexer select control.¹This input is latched internally on the rising edge

of CLK.

MSB

Shifter Input multiplexer select control.¹This input is latched internally on the rising edge

of CLK.

MSS

B15 - B0

B Port data input. Data presented to this port is latched into the input register on the rising

edge of CLK. B15 is the MSB.

Clock enable, B Port input register. When low the clock to this register is enabled.

CEB

CLK

Common clock to all internal registered elements. All registers are loaded, and outputs

change on the rising edge of CLK.

ALU A-input multiplexer select control.¹These inputs are latched internally on the rising

MSA0 - MSA1

A15 - A0

edge of CLK.

A Port data input. Data presented to this port is latched into the input register on the rising

edge of CLK. A15 is the MSB.

Clock enable, A Port input register. When low the clock to this register is enabled.

CEA

C-Port multiplexer select control.¹This input is latched internally on the rising edge

of CLK.

MSC

Instruction inputs to Barrel Shifter, IS3 = MSB.¹These inputs are latched internally on the

rising edge of CLK.

IS0 - IS3

SV0 - SV3

Shift Value I/O Port. This port is used as an input when shift values are supplied from

external sources, and as an output when Normalise operations are invoked. The I/O functions

are determined by the IS0 - IS3 instruction inputs, and by the SVOE control.

The shift value is latched internally on the rising edge of CLK.

SV Output enable. When high the SV port can only operate as an input. When low the SV

port can act as an input or as an output, according to the IS0 - IS3 instruction. This pin should

be tied hihg or low, depending upon the application.

SVOE

Instruction inputs to Barrel Shifter registers.¹These inputs are latched internally on the

rising edge of CLK.

RS0, RS1

RS2

C0 - C15

C Port data output. Data output on this port is selected by the C output multiplexer.

C15 is the MSB.

Output enable. The C Port outputs are in high impedance condition when this control is high.

Block Floating Point Flag from ALU, active high.

BFP

Carry out from MSB of ALU.

Instruction inputs to ALU registers.¹These inputs are latched internally on the rising

edge of CLK.

RA0 - RA2

Carry in to LSB of ALU.

Instruction inputs to ALU.¹IA4 = MSB. These inputs are latched internally on the rising

edge of CLK.

IA0 - IA3

IA4

Vcc

+5V supply: Both Vcc pins must be connected.

0V supply: Both GND pins must be connected.

GND

NOTES

1. All instructions are executed in the cycle commencing with the rising edge of the CLK which latches the inputs.

PDSP1601/PDSP1601A

A INPUT

B INPUT

CEA

CEB

MSS

B REG

A REG

MSA0-1

MSB

A MUX

B MUX

S MUX

BFP

IA0-4

IS0-3

SHIFT

CONTROL

BARREL SHIFTER

ALU

SV0-3

SVOE

RAD-2

RS0-2

ALU REG FILE

LEFT REG. RIGHT REG.

SHIFTER REG FILE

LEFT REG.

RIGHT REG.

MSC

C MUX

COUT

Fig.2 PDSP1601 block diagram

FUNCTIONAL DESCRIPTION

The PDSP1601 contains four main blocks: the ALU, the

Barrel Shifter and the two Register Files.

activetheALUresultmusthaveoverflowedintothe16th(sign)

bit, (this flag is only valid whilst the most significant 16 bit byte

is being processed). The zero condition is active if the result

from the ALU is equal to zero. For multiprecision operations

the zero flag must be active for all of the 16 bit bytes of an

extended word.

The BFP flag is programmed by executing on of the four

SBFXXinstructions(seeTable1). Duringtheexecutionofany

of these four instructions, the output of the ALU is forced to

zero.

The ALU

The ALU supports 32 instructions as detailed in Table 1.

The inputs to the ALU are selected by the A and B MUXs.

Data will fall through from the selected register through the A

or B input MUXs and the ALU to the ALU output register file in

50ns for the PDSP1601A (100ns for the PDSP1601).

The ALU instructions are latched, such that the instruction

will not start executing until the rising edge of CLK latches the

instruction into the device.

Multicycle/Cascade Operation

The ALU arithmetic instructions contain two or three

options for each arithemtic operation.

The ALU accepts a carry in from the CI input and supplies

a carry out to the CO output. Additionally, at the end of each

cycle, the carry out from the ALU is loaded into an internal 1

bit register, so that it is available as an input to the ALU on the

next cycle. In the manner, multicycle, multiprecision

operations are supported. (See MULTICYCLE CASCADE

OPERATIONS).

The ALU is designed to operate with two's complement

arithmetic, requiring a one to be added to the LSB for all

subtractoperations. Theinstructionssetincludesinstructions

thatwillforceaoneintotheLSB, e.g. MIAX1, AMBX1, BMAX1

(see Table 1).

These instructions are used for the least significant 16 bit

byte of any subtract operation.

BFP Flag

The user has an option of cascading multiple devices, or

multicycling a single device to extend the arithmetic precision.

Should the user cascade multiple devices, then the cascade

arithmetic instructions using the external CI input should be

employedforallbuttheleastsignificant16bitbyte,e.g.MIACI,

APBCI, BMACI (see Table 1).

Should the user multicycle a single device, then the

Multicycle Arithmetic instructions, using the internally

registered CO bit should be employed for all but the least

significant 16 bit byte, e.g. MIACO, APBCO, AMBCO,

BMACO (see Table 1).

The ALU has a user programmable BFP flag. This flag

may be programmed to become active at any one of four

conditions. Two of these conditions are intended to support

Block Floating Point operations, in that they provide flags

indicating that the ALU result is within a factor of two or four of

overflowing the 16 bit number range. For multiprecision

operations the flag is only valid whilst the most significant 16

bit byte is being processed. In this manner the BFP flag may

be used over any extended word width.

The remaining two conditions detect either an overflow

condition or a zero result. For the overflow condition to be

PDSP1601/PDSP1601A

Table 1 ALU instructions

1a. ARITHMETIC INSTRUCTIONS

Mnemonic

Inst

Function

IA4-AI0

Operation

Mode

CLRXX

MIAX1

MIACI

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

RESET

CLEAR ALL REGISTERS

NA Plus 1

NA Plus CI

---------

LSBYTE

MINUS A

A/2

CASCADE

MULTICYCLE

MSBYTE

MULTICYCLE

CASCADE

MULTICYCLE

LSBYTE

CASCADE

MULTICYCLE

LSBYTE

CASCADE

MULTICYCLE

MIACO

A2SGN

A2RAL

A2RAR

A2RSX

APBCI

APBCO

AMBX1

AMBCI

AMBCO

BMAX1

BMACI

BMACO

NA Plus CO

A/2 Sign Extend

A/2 with RAL LSB

A/2 with RAR LSB

A/2 with RSX LSB

A Plus B Plus CI

A Plus B Plus CO

A Plus NB Plus 1

A Plus NB Plus CI

A Plus NB Plus CO

NA Plus B Plus 1

NA Plus B Plus CI

NA Plus B Plus CO

A/2

A PLUS B

A MINUS B

B MINUS A

1b. LOGICAL INSTRUCTIONS

Mnemonic

Inst IA4-AI0

Operation

Function

ANXAB

ANANB

ANNAB

ORXAB

ORNAB

XORAB

PASXA

PASNA

10000

10001

10010

10011

10100

10101

10110

10111

A AND B

A AND NB

NA AND B

A OR B

NA OR B

A XOR B

PASS A

A. B

A. NB

NA. B

A + B

NA + B

A XOR B

INVERT A

1c. CONTROL INSTRUCTIONS

Mnemonic

Inst IA4-AI0

Operation

SBFOV

SBFU1

SBFU2

SBFZE

OPONE

OPBYT

OPNIB

OPALT

11000

11001

11010

11011

11100

11101

11110

11111

Set BFP Flag to OVR, Force ALU output to zero

Set BFP Flag to UND 1 Force ALU output to zero

Set BFP Flag to UND 2 Force ALU output to zero

Set BFP Flag to ZERO Force ALU output to zero

Output 0001 Hex

Output 00FF Hex

Output 000F Hex

Output 5555 Hex

KEY

MNEMONICS

= A input to ALU

= B input to ALU

= External Carry in to ALU

CLRXX

MIAXX

A2XXX

APBXX

AMBXX

BMAXX

ANX-Y

ORX-Y

XORXY

PASXX

SBFXX

OPXXX

Clear All Registers to zero

Minus A,

A Divided by 2, XXX = Source of MSB

A Plus B,

A Minus B,

B Minus A,

AND

XX = Carry in to LSB

= Internally Registered Carry out from ALU

RAL = ALU Register (Left)

RAR = ALU Register (Right)

RSX = Shifter Register (Left or Right)

= Operand 1, Y = Operand 2

Exclusive OR

Pass

Set BFP Flag

XX = Operand

XX = Function

Output Constant XXX

PDSP1601/PDSP1601A

Divide by Two

The Barrel Shifter

The ALU has four (A2SGN, A2RAL, A2RAR, A2RSX)

instructions used for right shifting (dividing by two) extended

precision words. These words, (up to 64 bits) may be stored

in the two on-chip register files. When the least significant 16

bit word is shifted, the vacant MSB must be filled with the LSB

from the next most significant 16 bit byte. This is achieved via

the A2RAL, A2RAR or A2RSX instructions which indicate the

source of the new MSB (see ALU INSTRUCTION SET).

When the most significant 16 bit byte is right shifted, the

MSB must be filled with a duplicate of the original MSB so as

to maintain the correct sign (Sign Extension). This operation

is achieved via the A2SGN instruction (see Table 1).

The Barrel Shifter supports 16 instructions as detailed in

Table 2. The input to the Barrel Shifter is selected by the S

MUX. Data will fall through from the selected register, through

the S MUX and the Barrel Shifter to the shifter output register

file in 50ns for the PDSP1601A (100ns for the PDSP1601).

The Barrel Shifter instructions are latched, such that the

instructions will not start executing until the rising edge of CLK

latches the instruction into the device.

TheBarrelShifteriscapableofLogicalArithmeticorBarrel

Shifts in either direction.

A. Logical shifts discard bits that exit the 16 bit field and fill

spaces with zeros.

Constants

B. Arithmetic shifts discard bits that exit the 16 bit field and

fill spaces with duplicates of the original MSB.

C. Barrel Shifts rotate the 16 bit fields such that bits tha exit

the 16 bit field to the left or right reappear in the vacant

spaces on the right or left.

The ALU has four instructions (OPONE, OPBYT, OPNIB,

OPALT) that force a constant value onto the ALU output.

These values are primarily intended to be used as masks, or

the seeds for mask generation, for example, the OPONE

instruction will set a single bit in the least significant position.

This bit may be rotated any where in the 16 bit field by the

BarrelShifter, allowingtheANDfunctionoftheALUtoperform

bit-pick operations on input data.

Theamountofshiftappliedisencodedontothe4bitBarrel

Shifter input as illustrated in Table 3. The type of shift and the

amount are determined by the shift control block. The shift

controlblock(seeFig.3)acceptsanddecodesthefourbitISO-

3 instruction. The shift control block contains a priority

encoder and two user programmable 4 bit registers R1 and

R2.

CLR

The ALU instruction CLRXX is used as a Master Reset for

the entire device. This instruction has the effect of:

There are four possible sources of shift value that can be

passed onto the Barrel Shifter, there are:

1. Clearing ALU and Barrel Shifter register files to zero.

2. Clearing A and B port input registers to zero.

1. The Priority Encoder

2. The SV input

3. Clearing the R1 and R2 shift control registers to zero.

4. Clearing the internally registered CO bit to zero.

5. Programming the BFP flag to detect overflow conditions.

3. The R1 register

4. The R2 register

Mnemonic

Inst IS3-IS0

Operation

I/O

LSRSV

LSLSV

BSRSV

BSLSV

LSRR1

LSLR1

LSRR2

LSLR2

LR1SV

LR2SV

ASRSV

ASRR1

ASRR2

NRMXX

NRMR1

NRMR2

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Logical Shift Right by SV

Logical Shift Left by SV

Barrel Shift Right by SV

Barrel Shift Left by SV

Logical Shift Right by R1

Logical Shift Left by R1

Logical Shift Right by R2

Logical Shift Left by R2

Load Register 1 From SV

Load Register 2 From SV

Arithmetic Shift Right by SV

Arithmetic Shift Right by R1

Arithmetic Shift Right by R2

Normalise Output PE

Normalise Output PE, Load R1

Normalise Output PE, Load R2

Table 2 Barrel shifter instructions

MNEMONICS

LSXYY Logical Shift,

BSXYY Barrel Shift,

ASXYY Arithmetic Shift, X

LXXYY Load

NRMYY Normalise by PE, Output PE value on SV Port, Load YY Reg

KEY

= Direction YY = Source of Shift Value

= Shift Value

= Register 1

= Register 2

XX = Target YY = Source

= Priority Encoder Output

=> SV Port operates as an Input

=> SV Port operates as an Output

=> SV Port in a High Impedance State

PDSP1601/PDSP1601A

(1)

Priority encode the 16 bit input to the Barrel Shifter and

SV3

SV2 SV1 SV0

Shift

place the 4 bit value in either of the R1 or R2 registers and

output the value on the SV port (if enabled by SVOE).

No shift

1 place

(2)

Shift the 16 bit input by the amount indicated by the

2 places

3 places

4 places

5 places

6 places

7 places

8 places

9 places

10 places

11 places

12 places

13 places

14 places

15 places

Priority Encoder such that the output from the Barrel Shifter is

a normalised value.

SV Input

If the SV port is selected as the source of the shift value,

thentheinputtotheBarrelShifterisshiftedbythevaluestored

in the internal SV register.

SVOE

The SV port acts as an input or an output depending upon

the IS0-3 instruction. If the user does not wish to use the

normalise instructions, then the SV port mat be forced to be

Table 3 Barrel shifter codes

input only by typing SVOE control high. In this mode the SV

port may be considered an extension of the instruction inputs.

R1 and R2 Registers

Priority Encoder

The R1 and R2 registers may be loaded from the Priority

Encoder (NRMR1 and NRMR2) or from the SV input (LR1SV,

LR2SV).

Whilst the latter two instructions are executing, the Barrel

Shifter will pass its input to the output unshifted.

If the priority encoder is selected as the source of the shift

value (instructions:- NRMXX, NRMR1, MRMRZ), then within

one 100ns cycle or two 50ns cycles for the PDSP1601A (one

200ns or two 100ns cycles for the PDSP1601), the shift

circuitry will:

INSTRUCTION

IS0-3

DECODE

PRIORITY ENCODER

MUX

SVOE

Fig.3 Shift control block

PDSP1601/PDSP1601A

The Register Files

Therearetwoon-chipregisterfiles(ALUandShifter),each

containing two 16 bit registers and each supporting 8

instructions (see Table 4). The instructions for the ALU

The Inputs to the register files come from either the ALU or

the Barrel Shifter, and are loaded into the Register files on the

rising edge of CLK.

CLK latches the instruction into the device.

The register file instructions (see Table 4) allow input data

to be loaded into either, neither or both of the registers. Data

is loaded at the end of the cycle in which the instruction is

executing.

The register file instructions allow the output to be sourced

fromeitherofthetworegisters,theselectedoutputwillbevalid

during the cycle in which the instruction is executing.

The register file instructions are latched such that the

instruction will not start executing until the rising edge of the

ALU REGISTER INSTRUCTIONS

Mnemonic

Inst RA2-RA0

Operation

LLRRR

LRRLR

LLRLR

LRRRR

LBRLR

NOPRR

NOPLR

NOPPS

000

001

010

011

100

101

110

111

Load Left Reg Output Right Reg

Load Right Reg Output Left Reg

Load Left Register, Output Left Reg

Load Right Register, Output Right Reg

Load Both Registers, Output Left Reg

No Load Operation, Output Right Reg

No Load Operation, Output Left Reg

No Load Operation, Pass ALU Result

SHIFTER REGISTER INSTRUCTIONS

Mnemonic

Inst RA2-RA0

Operation

LLRRR

LRRLR

LLRLR

LRRRR

LBRLR

NOPRR

NOPLR

NOPPS

000

001

010

011

100

101

110

111

Load Left Reg Output Right Reg

Load Right Reg Output Left Reg

Load Left Register, Output Left Reg

Load Right Register, Output Right Reg

Load Both Registers, Output Left Reg

No Load Operation, Output Right Reg

No Load Operation, Output Left Reg

No Load Operation, Pass Barrel Shifter Result

Table 4 ALU and shift register instructions mnemonics

MNEMONICS

LXXYY Load XX = Target,

YY = Source of Output

LBOXX Load Both Registers, XX = Source of Output

NOPXX No Load Operation, XX = Source of Output

PDSP1601/PDSP1601A

Multiplexers

There are four user selectable on-chip multiplexers (A-

MUX, B-MUX, S-MUX and C-MUX).

These four multiplexers support instructions as tabulated

in Table 5.

The MUX instructions are latched such that the instruction

will not start executing until the rising edge of CLK latches the

instruction onto the device.

Output

MSA1

MSA0

ALU REGISTER FILE OUPUT

A-PORT INPUT

B-PORT INPUT

MARAX

MAAPR

MABPR

MARSX

A-MUX

SHIFTER REGISTER FILE OUTPUT

Output

MSB

B-PORT INPUT

SHIFTER REGISTER FILE OUTPUT

B-MUX

S-MUX

C-MUX

Output

MSS

B-PORT INPUT

SHIFTER REGISTER FILE OUTPUT

Output

MSC

ALU REGISTER FILE OUTPUT

SHIFTER REGISTER FILE OUTPUT

Table 5

PDSP1601/PDSP1601A

INSTRUCTION SET

ALU Arithmetic Instructions

Op Code

Function

Mnemonic

<00>

On the rising edge of CLK at the end of the cycle in which this instruction is executing, the

A Port, B Port, ALU, Barrel Shifter, and Shift Control Registers will be loaded with zeros.

The internal registered CO will also be set to zero, and the BFP flag will be set to activate

on overflow conditions.

CLRXX

<01>

<02>

<03>

The A input to the ALU is inverted and a one is added to the LSB.

The A input to the ALU is inverted and the CI input is added to the LSB.

MIAX1

MIAC1

MIACO

The A input to the ALU is inverted and the CO output from the ALU on the previous cycle

is added to the LSB.

<04>

<05>

<06>

<07>

TheAinputtotheALUisrightshiftedonebitposition. TheLSBisdiscarded,andthevacant

MSB is filled by duplicating the original MSB (Sign Extension).

A2SGN

A2RAL

A2RAR

A2RSX

TheAinputtotheALUisrightshiftedonebitposition. TheLSBisdiscarded,andthevacant

MSB is filled with the LSB from the ALU register.

TheAinputtotheALUisrightshiftedonebitposition. TheLSBisdiscarded,andthevacant

MSB is filled with the LSB from the ALU register.

TheAinputtotheALUisrightshiftedonebitposition. TheLSBisdiscarded,andthevacant

MSB is filled with the LSB from the B input to the ALU.

<08>

<09>

The A input to the ALU is added to the B input, and the CI input is added to the LSB.

APBCI

TheAinputtotheALUisaddedtotheBinput, andtheCOoutfromtheALUontheprevious

cycle is added to the LSB.

APBCO

<0A>

<0B>

The A input to the ALU is added to the inverted B input, and a one is added to the LSB.

AMBX1

AMBCI

The A input to the ALU is added to the inverted B input, and the CI input is added to the

LSB.

<0C>

The A input to the ALU is added to the inverted B input, and the CO out from the ALU on

the previous cycle is added to the LSB.

AMBCO

<0D>

<0E>

The inverted A input to the ALU is added to the B input, and a one is added to the LSB.

BMAX1

BMAC1

The inverted A input to the ALU is added to the B input, and the CI input is added to the

LSB.

<0F>

The inverted A input to the ALU is added to the B input, and the CO out from the ALU on

the previous cycle is added to the LSB.

BMACO

ALU Logical Instructions

Op Code

Function

Mnemonic

<10>

The A input to the ALU is logically 'ANDed' with the B input.

The A input to the ALU is logically 'ANDed' with the inverse of the B input.

The inverse of the A input to the ALU is logically 'ANDed' with the B input.

The A input to the ALU is logically 'ORed' with the B input.

The inverse A input to the ALU is logically 'ORed' with the B input.

The A input to the ALU is logically Exclusive-ORed with the B input.

The A input to the ALU is passed to the output.

ANXAB

<11>

ANANB

<12>

ANNAB

<13>

ORXAB

<14>

ORNAB

<15>

XORAB

<16>

PASXA

<17>

The inverse of the A input to the ALU is passed to the output.

PASNA

PDSP1601/PDSP1601A

ALU Control Instructions

Op Code

Function

Mnemonic

<18>

The BFP flag is programmed to activate when an ALU operation causes an overflow of the

16 bit number range. This flag is logically the exclusive-or of the carry into and out of the

MSB of the ALU. For the most significant Byte this flag indicates that the result of an

arithmetic two's complement operation has overflowed into the sign bit. The output of the

ALU is forced to zero for the duration of this instruction.

SBFOV

<19>

The BFP flag is programmed to activate when an ALU operation comes within a factor of

two of causing an overflow of the 16 bit number range. For the most significant Byte this

flag indicates that the result of an arithmetic two's complement operation is within a factor

oftwoof overflowingintothesignbit. TheoutputoftheALUisforcedtozerofortheduration

of this instruction.

SBFU1

<1A>

The BFP flag is programmed to activate when an ALU operation comes within a factor of

four of causing an overflow of the 16 bit number range. For the most significant Byte this

flag indicates that the result of an arithmetic two's complement operation is within a factor

offourofoverflowingintothesignbit. TheoutputoftheALUisforcedtozerofortheduration

of this instruction.

SBFU2

<1B>

The BFP flag is programmed to activate when an ALU operation causes a result of zero.

The output of the ALU is forced to zero for the duration of this instruction. During the

execution of this instruction the BFP flag will become active.

SBFZE

<1C>

The ALU will output the binary value 0000000000000001, the MSB on the left.

The ALU will output the binary value 0000000011111111, the MSB on the left.

The ALU will output the binary value 0000000000001111, the MSB on the left.

The ALU will output the binary value 0101010101010101, the MSB on the left.

OPONE

<1D>

OPBYT

<1E>

OPNIB

<1F>

OPALT

Barrel Shifter Instructions

Op Code

Function

Mnemonic

<0>

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by

the magnitude of the four bit number present in the SV register. The LSBs are dicarded,

and the vacant MSBs are filled with zeros.

LSRSV

<1>

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the

magnitude of the four bit number present in the SV register. The LSBs are dicarded, and

the vacant MSBs are filled with zeros.

LSLSV

<2>

The 16 bit input to the Barrel Shifter is rotated to the right by the number of places indicated

by the magnitude of the four bit number present in the SV register. The LSBs that exit the

16 bit field to the right, reappear in the vacant MSBs on the left.

BSRSV

<3>

The 16 bit input to the Barrel Shifter is rotated to the left by the number of places indicated

by the magnitude of the four bit number present in the SV register. The LSBs that exit the

16 bit field to the right, reappear in the vacant MSBs on the right.

BSLSV

<4>

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by

the magnitude of the four bit number resident within the R1 register. The LSBs are

discarded, and the vacant MSBs are filled with zeros.

LSRR1

<5>

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the

magnitude of the four bit number resident within the R1 register. The LSBs are discarded,

and the vacant LSBs are filled with zeros.

LSLR1

<6>

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by

the magnitude of the four bit number resident within the R2 register. The LSBs are

discarded, and the vacant MSBs are filled with zeros.

LSRR2

<7>

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the

magnitude of the four bit number resident within the R2 register. The LSBs are discarded,

and the vacant LSBs are filled with zeros.

LSLR2

PDSP1601/PDSP1601A

Op Code

Function

Mnemonic

<8>

<9>

<A>

<B>

On the rising edge of CLK at the end of the cycle in which this instruction is executing, the

R1 register will be loaded with the data present on the SV port. The input to the Barrel

Shifter will be passed onto the output unshifted.

LR1SV

LR2SV

ASRSV

ASRR1

On the rising edge of CLK at the end of the cycle in which this instruction is executing, the

R2 register will be loaded with the data present on the SV port. The input to the Barrel

Shifter will be passed onto the output unshifted.

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by

the magnitude of the four bit number present in the SV register. The LSBs are discarded,

and the vacant MSBs are filled with duplicates of the original MSB. (Sign Extension).

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by

the magnitude of the four bit number resident within the R1 register. The LSBs are

discarded, and the vacant MSBs are filled with duplicates of the original MSB.

(Sign Extension).

<C>

<D>

The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by

the magnitude of the four bit number resident within the R2 register. The LSBs are

discarded, and the vacant MSBs are filled with duplicates of the original MSB.

(Sign Extension).

ASRR2

NRMXX

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the

magnitudeofthefourbitnumberoutputfromthePriorityEncoder. Thisvalueisalsooutput

on the SV port (provided SVOE is low).

The effect of this operation is to left shift the input by the necessary amount

(max 15 places) to result in the MSB and the next most significant bit being different. This

has the effect of eliminating unnecessary Sign Bits, and hence Normalising the input data.

The MSBs shifted out to the left are discarded, and the vacant LSBs on the right are filled

with zeros.

<E>

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the

magnitudeofthefourbitnumberoutputfromthePriorityEncoder. Thisvalueisalsoloaded

NRMR1

NRMR2

into the R1 register at the end of the cycle, and is output on the SV port (provided SVOE

is low).

The effect of this operation is to left shift the input by the necessary amount

(max 15 places) to result in the MSB and the next most significant bit being different. This

has the effect of eliminating unnecessary Sign Bits, and hence Normalising the input data.

The MSBs shifted out to the left are discarded, and the vacant LSBs on the right are filled

with zeros.

<F>

The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the

magnitudeofthefourbitnumberoutputfromthePriorityEncoder. Thisvalueisalsoloaded

into the R2 register at the end of the cycle, and is output on the SV port (provided SVOE

is low).

The effect of this operation is to left shift the input by the necessary amount

(max 15 places) to result in the MSB and the next most significant bit being different. This

has the effect of eliminating unnecessary Sign Bits, and hence Normalising the input data.

The MSBs shifted out to the left are discarded, and the vacant LSBs on the right are filled

with zeros.

PDSP1601/PDSP1601A

Barrel Shifter or ALU Register Instructions

Op Code

Function

Mnemonic

<0>

<1>

<2>

<3>

<4>

<5>

<6>

<7>

After the rising edge of CLK at the beginning of the cycle in which this instruction is

executed, the contents of the Right register will appear on the output. On the rising edge

of CLK at the end of the cycle, and the data on the register inputs will be loaded into the

Left Register.

LLRRR

LRRLR

LLRLR

LRRRR

LBRLR

NOPRR

NOPLR

NOPPS

After the rising edge of CLK at the beginning of the cycle in which this instruction is

executed, the contents of the Left register will appear on the output. On the rising edge

of CLK at the end of the cycle, the data on the register inputs will be loaded into the Right

After the rising edge of CLK at the beginning of the cycle in which this instruction is

executed, the contents of the Left register will appear on the output. On the rising edge

of CLK at the end of the cycle, the data on the register inputs will be loaded into the Left

After the rising edge of CLK at the beginning of the cycle in which this instruction is

executed, the contents of the Right register will appear on the output. On the rising edge

of CLK at the end of the cycle, the data on the register inputs will be loaded into the Right

After the rising edge of CLK at the beginning of the cycle in which this instruction is

executed, the contents of the Left register will appear on the output. On the rising edge

of CLK at the end of the cycle, and the data on the register inputs will be loaded into both

Left and Right Register.

After the rising edge of CLK at the beginning of the cycle in which this instruction is

executed, the contents of the Right register will appear on the output. On the rising edge

of CLK at the end of the cycle no load operation will occur, the register contents will remain

unchanged.

After the rising edge of CLK at the beginning of the cycle in which this instruction is

executed, the contents of the Left register will appear on the output. On the rising edge

of CLK at the end of the cycle no load operation will occur, the register contents will remain

unchanged.

After the rising edge of CLK at the beginning of the cycle in which this instruction is

executed, the input to the registers will appear on the output. On the rising edge

of CLK at the end of the cycle no load operation will occur, the register contents will remain

unchanged.

PDSP1601/PDSP1601A

TYPICAL APPLICATION

(2)

The LS byte is logically right shifted, n-places, the

Select a 16 bit field from each word in a block of 32 bit

words with a 10MHz throughput.

The 16 bit field indicated is to be selected from each 32 bit

word.

LSBs being discarded and the MSBs being filled with zeros.

This shifted data is loaded into the shifter register file left

During this cycle the previous contents of this register are

passed through the ALU to the ALU register file left register.

MS Byte

LS Byte

MS Bit

(3)

While the MS byte of the next 32 bit word is shifted in

the Barrel Shifter, the two previous results, resident within the

left registers of the ALU and Shifter Register files are 'ORed'

by the ALU, the result being the desired 16 bit field is loaded

intotheALUregisterfilerightregisterreadytobeoutputonthe

next cycle.

16 bits

nbits

The 32 bit words are fed into the B port of the PDSP1601

in two cycles, MS byte first.

The PDSP1601 shift control is initiated by programming

the R1 and R2 registers with n and 16-n respectively.

The shift operation is implemented in three steps:-

The instructions from initialisation are given in Table 6.

(1)

The MS byte is logically left shifted (16-n) places, the

MSBs being discarded and the LSB spaces being filled with

zeros. This shifted data is loaded into the shifter register file

left register.

CLK CEB

MSA

MSB MSS MSC

Comment

CLRXX

MARSX

MARAX

NOPLR

LLRRR

LRRLR

Clear

NOPLR

LLRLR

PASXA LR1SV

PASXA LR2SV

PASXA LSLR2

PASXA LSRR1

ORXAB LSLR2

(16-n)

Load R1 with n

Load R2 with (16-n)

Shift 1st MS byte

Shift 1st LS byte

OR 1st bytes and

shift 2nd MS byte

Shift 2nd LS byte

and output first result

Shift 3rd LS byte

PASXA LSRR1

ORXAB LSLR2

MARSX

MARAX

LLRRR

LRRLR

LLRLR

Repeat instruction pair 5/ and 6/ until all 16 bit fields have been selected.

Table 6

ABSOLUTE MAXIMUM RATINGS (Note 1)

NOTES

Supply voltage Vcc

Input voltage V_IN

Output voltage V_OUT

-0.5V to 7.0V

-0.9 to Vcc + 0.9V

1. Exceeding these ratings may cause permanent damage.

Functional operation under these conditions is not implied.

2. Maximum dissipation or 1 second should not be exceeded, only

one output to be tested at any one time.

Clamp diode current per pin Ik(see note 2)

±18mA

Static discharge voltage (HMB)

Storage temperature T_S

Ambient temperature with

power applied T_amb

Military

500V

-65°C to +150°C

-40°C to +125°C

-40°C to +85°C

THERMAL CHARACTERISTICS

Industrial

Package power dissipation P^TOT

Package type

ΘJC °C/W

ΘJA °C/W

1000mw

PDSP1601/PDSP1601A

ELECTRICAL CHARACTERISTICS

Operating Conditions (unless otherwise stated)

T_AMB(Commercial) = 0°C to +70°C, V_CC= 5.0V±5%, Ground = 0V

T_AMB(Industrial) = -40°C to +85°C, V_CC= 5.0V±10%, Ground = 0V

T_AMB(Military) = -55°C to +125°C, V_CC= 5.0V±10%, Ground = 0V

Static Characteristics

Symbol

Value

Typ.

Characteristic

Units

Conditions

Min.

2.4

Max.

V_OH

V_OL

V_IH

V_IL

I_IL

I_CC

I_OZ

I_SC

C_IN

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input leakage current

Vcc current

Output leakage current

Output S/C current

Input capacitance

I_OH= 8mA

I_OL= -8mA

0.4

3.5

0.5

+10

+50

-10

µA

GND < V_IN< V_CC

T_amb= -40°C to +85°C

GND < V_OUT< V_CC

V_CC= Max

-50

Switching Characteristics

Value

PDSP1601A

PDSP1601

Min. Max.

Characteristic

Conditions

Units

Min.

Max.

2 x LSTTL + 20pF

1 x LSTTL + 5pF

100

CLK rising edge to C-PORT

CLK rising edge to CO

CLK rising edge to BFP

Setup CEA or CEB to CLK rising edge

Hold CEA or CEB after CLK rising edge

Setup A or B port inputs to CLK rising edge

Hold A or B port inputs after CLK rising edge

Setup MSA0-1, MSB, MSS, MSC, RA2-0, RS0-2, IA0-4,

IS0-3, to CLK rising edge

Hold RS0-2, IA0-4 after CLK rising edge

Hold IS0-3 after CLK rising edge

Hold MSA0-1, MSB, MSS, MSC, RA0-2 after CLK rising edge

Setup SV to CLK rising edge

Hold SV after CLK rising edge

Input mode

100

20pF load, SV O P mode

2 x LSTTL + 20pF

CLK rising edge to SV

C-PORT

C-PORT Z

100

200

100

Clock period (ALU & Barrel Shifter, serial mode)

Clock period (ALU & Barrel Shifter, parallel mode)

Clock high time

Clock low time

NOTES

1. LSTTL is equivalent to IOH at 20µA IOL of -0.4mA

2. Current is defined as negative into the device.

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