SP5024 [ZARLINK]
3-Wire Bus Controlled Synthesiser; 3 - Wire总线控制合成器
| 型号： | SP5024 |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | 3-Wire Bus Controlled Synthesiser |
| 文件： | 总8页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SP5024
3-Wire Bus Controlled Synthesiser
DS2452 - 2.1 December 1992
The SP5024 is a programming variant of the SP5510
allowing the design of one tuner with either I2C bus or 3-wire
bus format depending on which device is inserted. The
SP5024, when used with a TV varicap tuner, forms a complete
phase locked loop tuning system. The circuit consists of a
divide-by-8 prescaler with its own preamplifier and a 15 bit
programmable divider controlled by a serially - loaded data
register. Four open-collector outputs, each independently
programmable, are included. The device has two modes of
operation selected by the 'mode selected input'. In mode 1 the
comparison frequency is 7.8125kHz and the programmable
divider MSB is bypassed; mode 2 comparison frequency is
6.25kHz. The comparison frequencies are both obtained from
a 4MHz crystal controlled on-chip oscillator. The comparator
has a charge pump output with an output amplifier stage
around which feedback may be applied. Only one external
transistor is required for varicap line driving.
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
CHARGE PUMP
CRYSTAL
MODE SELECT
DATA
DRIVE OUTPUT
V
EE
RF INPUT
RF INPUT
CLOCK
V
CC
PORT P4
NC
PORT P3
NC
PORT P2
LOCK
ENABLE
PORT P1
DP18
FEATURES
■ Complete 1.3GHz Single Chip System
■ Dual Standard 50kHz or 62.5kHz Step Size
■ Low Power Consumption (5V 40mA)
1
16
CHARGE PUMP
CRYSTAL
MODE SELECT
DATA
DRIVE OUTPUT
V
EE
■
Programming Compatible with Toshiba TD6380 and
RF INPUT
RF INPUT
TD6381
*
■ Pin Compatible with SP5510 *
■ Low Radiation
■ Varactor Drive Amplifier Disable
■ Charge Pump Disable
CLOCK
V
CC
PORT P4
LOCK
PORT P3
ENABLE
PORT P1
8
9
PORT P2
MP16
■ Single Port 18/19 Bit Serial Data Entry
■ Four Controllable Outputs
■ ESD Protection †
* See notes on pin compatibility
Fig. 1 Pin connections – top view
† Normal ESD handling procedures should be observed
APPLICATIONS
ORDERING INFORMATION
SP5024 DP
-
(18-lead plastic package)
■ Satellite TV When Combined With SP4902 2.5GHz
SP5024S MP
-
(16-lead miniature plastic package)
Prescaler
■ Cable Tuning Systems
■ VCRs
SP5024
ELECTRICAL CHARACTERISTICS
Tamb = -20°C to +80°C, VCC = +4·5V to +5·5V. Reference frequency = 4MHz. Pin numbers refer to SP5024 (DP package).
These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
and supply voltage unless otherwise stated.
Value
Symbol
Characteristic
Pin
Units
Conditions
Typ.
Min.
Max.
ICC
Supply current
14
40
55
mA
VCC = 5V
Prescaler input voltage
Prescaler input voltage
15,16
15, 16
15,16
12.5
30
300
300
mVRMS 50MHz to 1GHz sinewave
mVRMS 1.3GHz, see Fig. 5
Prescaler input impedance
Input capacitance
50
2
Ω
pF
High level input voltage
High level input voltage
Low level input voltage
High level input current
Low level input current
Low level input current
High level input current
Low level input current
Clock input hysteresis
Clock rate
4,5,10
3
4
0
VCC
VCC
0.6
1
V
V
V
3
3,4,5,10
4,5,10
µA
µA
µA
µA
µA
V
VIN = 5·5V, VCC = 5·5V
VIN = 0V, VCC = 5·5V
VIN = 0V, VCC = 5·5V
VIN = 5·5V, VCC = 5·5V
VIN = 0V, VCC = 5·5V
5
4,10
3
5
-250
150
-1
3
5
0.4
5
0.5
MHz
ns
t2
t3
t1
t5
t4
Data set up time
4
300
600
300
600
300
See Fig. 3
Data hold time
4
ns
See Fig. 3
Enable set up time
10
10
10
1
ns
See Fig. 3
Enable hold time
ns
See Fig. 3
Clock-to-enable time
Charge pump output current
ns
See Fig. 4
±150
µA
nA
V pin 1 = 2·0V
V pin 1 = 2·0V
Charge pump output leakage
current
1
±5
Drift due to leakage
5
mV/s
mA
At collector of external
varicap drive transistor
Charge pump drive output
current
18
1
V pin 18 = 0·7V
Charge pump amplifier gain
Oscillator temperature stability
6400
Pin 18 Current 100µA
2
2
ppm/°C
ppm/V
Oscillator stability with supply
voltage
200
Ω
Recommended crystal series
resistance
10
"Parallel resonant" crystal
40
mV p-p
Crystal oscillator drive level
2
2
-400
Ω
Crystal oscillator source
impedance
Nominal spread = 615%
2
SP5024
ELECTRICAL CHARACTERISTICS (continued)
Value
Typ.
Symbol
Characteristic
Pin
Units
Conditions
Min.
Max.
6 - 9,11
6-9
11
10
mA
µA
µA
µA
µA
VOUT = 0.7V
Port and Lock sink current
Port leakage current
10
10
VOUT = 13.2V
VOUT = VCC
VIN = <0V
Lock leakage current
10
-350
-350
Varactor Drive Amp Disable
Charge Pump Disable
4
VIN = <0V
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE = 0V
Value
Pin
SP5024
S
Pin
SP5024
Parameter
Units
Conditions
Min.
Max.
12
13, 14
6-9
-0.3
Supply voltage
Prescaler inputs
Output ports
-6
V
14
15, 16
6-9
2.5
Vp-p
-0.3
-0.3
Port in off state
Port in on state
14
6
V
V
6-9
13, 14
1, 16
2
Total port output current
Prescaler DC offset
50
mA
V
6-9
15, 16
1, 18
2
-0.3
-0.3
-0.3
-0.7
-55
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
+125
Loop amplifier DC offset
Crystal oscillator DC offset
Data bus inputs
V
V
4, 5 ,10
With VCC applied
V
4, 5 ,10
Storage temperature
Junction temperature
°C
°C
+150
DP 18 thermal resistance, chip-to-ambient
DP 18 thermal resistance, chip-to-case
78
24
°C/W
°C/W
MP 16 thermal resistance, chip-to-ambient
MP 16 thermal resistance, chip-to-case
111
41
°C/W
°C/W
All ports off
Power consumption at 5V
275
mW
V
CC
RF IN
14/15 BIT
PROGRAMMABLE
DIVIDER
F
PD
F
COMP
PHASE
PRE
AMP
48
4640/
512
OSC
4MHz
CRYSTAL
COMP
PRESCALER
F
RF IN
CHARGE
PUMP
CLOCK
DATA
DATA
14/15 BIT LATCH
DIVIDER RATIO
CHARGE
PUMP
DRIVE/VARICAP
OUTPUT
AMP
DATA
INPUT
INTERFACE
CLOCK
ENABLE
MODE SELECT
MODE
SELECT
CONTROL
OUTPUT
BUFFER
LOCK
DETECT
CPDIS
VADIS
V
EE
P4 P3 P2 P1
LOCK
Fig.2 Block diagram
3
SP5024
FUNCTIONAL DESCRIPTION
The programmable divider is preceded by an input RF
preamplifier and high speed, low radiation prescaler. The
preamplifierisarrangedtobeselfoscillating,sogivingexcellent
input sensitivity. The input sensitivity and impedance are
shown in Figs. 5 and 7, respectively.
The SP5024 contains all the elements necessary, with the
exception of reference crystal, loop filter and external high
voltagetransistor,tocontrolavoltagecontrolledlocaloscillator,
so forming a PLL frequency synthesised source.
Thesystemiscontrolledbyamicroprocessorviaastandard
data, clock, enable, three-wire data bus. The data load
normally consists of a single word, which contains the
frequency and port information, and is only transferred to the
internal data shift register during an enable high period. The
clock input is disabled during enable low periods. New data
words are only accepted by the internal data buffers from the
shift register on a negative transition of the enable, so giving
improved fine tune facility for digital AFC etc.
The data sequence and timing follows the format shown in
Fig. 3.
The frequency is set by loading the programmable divider
with the required 14/15 bit divisor word. The output of this
divider, FPD, is fed to the phase comparator where it is
compared in phase and frequency domain to the internally
The SP5024 contains an improved lock detect circuit
which generates a flag when the loop has attained lock. ‘Out
of lock’ is indicated by high impedance state.
The SP5024 contains 4 general purpose open collector
outputs, ports P1-P4, which are capable of sinking at least
10mA. These outputs are set by the remaining four bits within
the normal data word.
PIN COMPATIBILITY
The SP5024 may be used in SP5510 applications which
require 3-wire bus as opposed to I2C bus data format. In
SP5510applicationswherethereferencecrystalisconnected
to pin 3, a small modification is required to ground the crystal
as shown in Fig. 4.
Appropriate connections to the mode select input (pin 3)
must also be made.
generated comparison frequency, FCOMP
.
The FCOMP is obtained by dividing the output of an on-chip
crystal controlled oscillator. The crystal frequency used is
generally 4MHz, which gives an FCOMP of 6.25kHz/7.8125kHz
and, when multiplied back up to the synthesised LO, gives a
minimum step size of 50kHz/62.5kHz, respectively.
In mode 1 (pin 3 'HIGH') the SP5024 is programming and
step size compatible with the Toshiba TD6380, and in mode
2 (pin 3 'LOW') it is compatible with the TD6381. In both
modes a 4MHz crystal is used to derive FCOMP, unlike the
TD6381 which requires a 3.2MHz crystal.
CLOCK
CHIP
ENABLE
DATA
MODE 1 (PIN 3
HIGH)
217
P1
216
P2
215
P3
214
P4
213
212
22
21
20
MSB
LSB
FREQUENCY DATA (LSB = 62.5kHz, with 4MHz reference)
213 22 21
218
P1
217
P2
216
P3
215
P4
214
20
DATA
MODE 2 (PIN 3
LOW)
MSB
LSB
FREQUENCY DATA (LSB = 50kHz, with 4MHz reference)
CLOCK
CHIP
ENABLE
DATA
t
t
t
t
t
= ENABLE SET-UP TIME
= DATA SET-UP TIME
= DATA HOLD TIME
= CLOCK-TO ENABLE TIME
= ENABLE HOLD TIME
1
2
3
4
5
t1
t2
t5
t4
t3
Fig. 3 Data format and timing
4
SP5024
15V
130V
112V
22k
47n
22k
180n
10k
47k
VARACTOR
INPUT
2N3904
10n
4MHz
CRYSTAL 18p
18
17
16
15
1
2
3
4
5
6
7
8
9
1n
OSCILLATOR
OUTPUT
1n
TUNER
SP5024
14
13
12
11
10
P4
P3
P2
P1
CONTROL
MICRO
BAND
INPUTS
Fig. 4 Typical application (FSTEP = 50kHz)
300
37.5
25
OPERATING
WINDOW
12.5
500
1000
1500
FREQUENCY (MHz)
Fig. 5 Typical input sensitivity
V
CC
V
REF
CHARGE
PUMP
2 x 3k
RF INPUTS
170
DRIVE
OUTPUT
Loop amplifier
Fig.6a Input/Output interface circuits
RF input
5
SP5024
INPUT
CLOCK
Enable and data inputs
Clock input
OUTPUT
CRYSTAL
Reference oscillator
Output ports P1-P4 and Lock output
Fig.6b Input/Output interface circuits
Fig.7 Typical input impedance
6
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