SP5026 [ZARLINK]
1.0GHz 3-Wire Bus Controlled Synthesizer; 1.0GHz的3线总线控制合成
| 型号： | SP5026 |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | 1.0GHz 3-Wire Bus Controlled Synthesizer |
| 文件： | 总11页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SP5026
1.0GHz 3-Wire Bus Controlled Synthesizer
Data Sheet
DS5776
Issue 2
December 2002
Features
•
•
•
•
Complete 1.OGHz Single Chip System
Ordering Information
Dual Standard 62.5kHz or 31.25 kHz Step Size
Low power Consumption (5V 40mA)
SP5026 DP
Function Compatible with Toshiba TD6380 and
TD6381*
18-lead plastic package)
SP5026S MP
•
•
•
•
•
•
•
Pin Compatible with SP5510†
Low Radiation
Varactor Drive Amplifier Disable
Charge Pump Disable
Single Port 18/19 Bit Serial Data Entry
Four Controllable Outputs
ESD Protection‡
(16-lead miniature plastic package)
Description
The SP5026 is a programming variant of the SP5510,
allowing the design of one tuner with either 12C bus or
3-wire bus format depending on which device is
inserted. The SP5026, when used with a TV varicap
tuner, forms a complete phase locked loop tuning
system. The circuit consists of a divider-by-8 prescaler
with its own preamplifier and at 5-bit programmable
divider controlled by a serially-loaded data register.
Four open-collector outputs, each independently
programmable, are included. The device has two
modes of operation, selected by the “mode select”
input. In mode 1, the comparison frequency is
7.8125kHz and the programmable divider MSB is
† See notes on pin compatibility
‡ Normal ESD handling procedures should be observed
Applications
•
Satellite TV when combined with SP4902 2.5GHz
Prescaler
•
•
Cable tuning systems
VCRs
bypassed; mode
2
comparison frequency is
3.90625kHz. The comparison frequencies are both
obtained from a 4MHz crystal controlled on-chip
oscillator.
Figure 1 - Block Diagram
1
SP5026
Data Sheet
The comparator has a charge pump output with an amplifier stage around which feedback may be applied. Only
one external transistor is required for varicap line driving.
Figure 2 - Pin Connections - Top View
Functional Description
The SP5026 contains all the elements necessary, with the exception of reference crystal, loop filter and external
high voltage transistor to control a voltage controlled local oscillator, so forming a PLL frequency synthesized
source.
The system is controlled by a microprocessor via a standard data, clock enable three-wire bus. The data load
normally consists of a single word, which contains the frequency and port information and is only transferred to the
internal data shift register during an enable high period. The clock input is disabled during enable low periods.
New data words are only accepted by the internal data buffers from the shift register on a negative transition of the
enable, so giving improved fine tune facility for digital AFC etc.
The data sequence and timing follows the format shown in Figure 3.
The frequency is set by loading the programmable divider with the required 14/15 bit divisor word. The output of the
divider, FPD, is fed to the phase comparator where it is compared in phase and frequency domain to the internal
generated comparison frequency, FCOMP
.
2
Zarlink Semiconductor Inc.
Data Sheet
SP5026
The FCCOMP is obtained by dividing the output of an on-chip crystal controlled oscillator. The crystal frequency used
is generally 4MHz, which gives an FCOMP of 3.90625kHz/7.815kHz and, when multiplied back up to the synthesized
LO, gives a minimum step size of 31.25kHz/62.5kHz, respectively.
The programmable divider is preceded by an input RF preamplifier and high speed, low radiation prescaler. The
preamplifier is arranged to be self oscillating, so giving excellent input sensitivity. The input sensitivity and
impedance are shown in Figure 5 and Figure 7 respectively.
The SP5026 contains an improved lock detect circuit which generates a flag when the loop has attained lock. “Out
of Lock” is indicated by high impedance state.
The SP5026 contains 4 general purpose open collector outputs, ports P1-P4, which are capable of sinking at least
10mA. These outputs are set by the remaining four bits within the normal data word.
Pin Compatibility
The SP5026 may by used in SP5510 applications which require 3-wire bus as opposed to 12C bus data format. In
SP5510 applications where the reference crystal is connected to pin 3, a small modification is required to ground
the crystal as shown in Figure 4.
Appropriate connections to the mode select input (pin 3) must also be made.
In mode 1 (pin 3 “HIGH”) the SP5026 is programming and step size compatible with the Toshiba TD6380, and in
mode 2 (pin 3 “LOW”) it is compatible with the TD6381.
Zarlink Semiconductor Inc.
3
SP5026
Data Sheet
Figure 3 - Data Format and Timing
4
Zarlink Semiconductor Inc.
Data Sheet
SP5026
Figure 4 - Typical Application (FSTEP = 31.25kHz)
Figure 5 - Typical Input Sensitivity
Zarlink Semiconductor Inc.
5
SP5026
Data Sheet
Figure 6 - Input/Output Interface Circuits
Figure 7 - Input/Output Interface Circuits
6
Zarlink Semiconductor Inc.
Data Sheet
SP5026
Figure 8 - Typical Input Impedance
Electrical Characteristics
†
Electrical Characteristics Table
Value
Characteristics
Supply current
Symbol
Pin
Units
Conditions
VCC = 5V
Min.
Typ.
Max.
I
14
40
55
mA
mV
CC
Prescaler input voltage
15,16
12.5
300
50MHz to 1GHz
sinewave
RMS
Prescaler input impedance
Input capacitance
15,16
50
2
Ω
pF
V
High level input voltage
High level input voltage
Low level input voltage
High level input current
Low level input current
Low level input current
High level input current
Low level input current
4,5,10
3
4
0
V
V
CC
CC
3
V
3,4,5,10
0.7
1
V
4,5,10
µA
µA
µA
µA
µA
V
V
V
V
V
= 5.5V, V = 5.5V
CC
IN
IN
IN
IN
IN
5
4,10
3
5
= 0V, V = 5.5V
CC
250
150
1
= 0V, V = 5.5V
CC
= 5.5V, V = 5.5V
CC
3
= 0V, V = 5.5V
CC
Zarlink Semiconductor Inc.
7
SP5026
Data Sheet
†
Electrical Characteristics Table (continued)
Value
Characteristics
Symbol
Pin
Units
Conditions
Min.
Typ.
Max.
Clock input hysteresis
Clock rate
5
5
0.4
V
MHz
ns
0.5
Data set up time
t
t
t
t
t
4
300
600
300
600
300
See Figure 3
2
3
1
5
4
Data hold time
4
ns
See Figure 3
See Figure 3
See Figure 3
See Figure 4
V pin 1= 2.0V
V pin 1= 2.0V
Enable set up time
Enable hold time
Clock-to-enable time
Charge pump output current
10
10
10
1
ns
ns
ns
+150
6400
µA
nA
Charge pump output
leakage current
1
+5
5
Drift due to leakage
mV/s
mA
At collector of external
varicap drive transistor
Charge pump drive
output current
18
1
V pin 18 = 0.7V
Charge pump amplifier gain
Pin 18 Current 100µA
o
Oscillator temperature
stability
2
2
ppm/ C
Oscillator stability
with supply voltage
ppm/V
Recommended crystal
series resistance
10
200
Ω
“Parallel resonant” crystal
Nominal spread = +15%
Crystal oscillator drive level
2
2
40
mV p-p
Crystal oscillator source
impedance
-400
Ω
Port leakage current
6-9
11
10
4
10
10
µA
µA
µA
µA
V
V
V
V
= 13.2V
OUT
OUT
Lock leakage current
Varactor Drive Amp Disable
Charge Pump Disable
= V
CC
-350
-350
= <0V
= <0V
IN
IN
0
0
† T =-20 C to +80 C, V = +4.5V to +5.5V. Reference frequency = 4MHz. Pin numbers refer to SP5026 (DP package).
amb
CC
These characteristics are guaranteed by either test or design. They apply within the specified ambient temperature and supply voltage unless
otherwise stated.
8
Zarlink Semiconductor Inc.
Data Sheet
SP5026
Absolute Maximum Ratings
†
Absolute Maximum Ratings Table
Value
Max
Pin
Pin
Parameter
Units
Conditions
SP5024 SP5024S
Min
Supply voltage
Prescaler inputs
Output ports
14
15,16
6-9
12
13,14
6-9
-0.3
-6
V
2.5
Vp-p
-0.3
-0.3
14
6
V
V
Port in off state
Port in on state
Total port output current
Prescaler DC offset
6-9
15,16
1,18
2
6-9
13,14
1,16
2
50
mA
V
-0.3
-0.3
-0.3
-0.7
-55
V
V
V
V
+0.3
CC
CC
CC
CC
Loop amplifier DC offset
Crystal oscillator DC offset
Data bus inputs
+0.3
+0.3
+0.3
V
V
4,5,10
4,5,10
V
With V applied
CC
0
Storage temperature
+125
+150
78
C
0
Junction temperature
C
0
DP 18 thermal resistance, chip-to-ambient
DP 18 thermal resistance, chip-to-case
C/W
0
24
C/W
0
MP 16 thermal resistance, chip-to-ambient
MP 16 thermal resistance, chip-to-case
Power consumption at 5V
111
41
C/W
0
C/W
275
mW
All ports off.
† All voltages are referred to V = 0V.
EE
Zarlink Semiconductor Inc.
9
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