SP5610SMPAD [ZARLINK]
1.3GHz BI朌IRECTIONAL I2C BUS CONTROLLED SYNTHESISER; 1.3GHz的BI朌IRECTIONAL I2C总线控制合成器
| 型号： | SP5610SMPAD |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | 1.3GHz BI朌IRECTIONAL I2C BUS CONTROLLED SYNTHESISER |
| 文件： | 总15页 (文件大小：596K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
FEBRUARY 1997
ADVANCE INFORMATION
D.S. 3920 3.3
SP5610
1.3GHz BI–DIRECTIONAL I2C BUS CONTROLLED SYNTHESISER
(Supersedes edition in 1996 Media IC Handbook, HB4599–1.0)
The SP5610 is a single chip frequency synthesiser
designed for TV tuning systems. Control data is entered in the
2
standard
I
C BUS format. The device contains 1 addressable
1
2
3
16
15
14
13
12
11
10
9
DRIVE OUTPUT
current limited output and 4 addressable bi–directional open
collector ports one of which is a 3 bit ADC. The information on
CHARGE PUMP
CRYSTAL Q1
CRYSTAL Q2
VEE
2
these ports can be read via the I C BUS. The device has one
RF INPUT
fixed I2C BUS address and 3 programmable addresses,
programmed by applying a specific input voltage to the P3
current limited output. This enables 2 or more synthesisers to
be used in a system.
RF INPUT
VCC
4
5
SDA
SCL
NC
6
7
8
[ I/O PORT P7
P3 OUTPUT PORT/
ADD SELECT
* I/O PORT P6
FEATURES
J Complete 1.3GHz Single chip System
[ I/O PORT P5
I/O PORT P4
[
J
J
J
J
J
J
High Sensitivity RF Inputs
Programmable via I C Bus
MP16
2
On Chip oscillator with 1k
W
negative resistance
[ = Logic level I/O
* = 3–bit ADC input
Low power consumption (5V, 20mA)
Low Radiation
Phase Lock Detector
J Varactor Drive Amp Disable
Fig. 1 Pin connections – top view
J
5 Controllable Outputs
J
5 Level ADC
2
J Variable I C BUS Address For Multi Tuner
Applications
J
J
J
ESD Protection *
Switchable 512/1024 Reference Divider
Pin and Function Compatible with SP5510S
ꢀ
[
ORDERING INFORMATION
SP5610S/KG/MPAS (Tubes)
SP5610S/KG/MPAD (Tape and Reel)
*
Normal ESD handling procedures should be observed.
[
The SP5510S does not have a switchable
reference division ratio.
APPLICATIONS
J Satellite TV when combined with SP4902 2.5GHz
prescaler
J
Cable Tuning Systems
J VCR’s
SP5610
ELECTRICAL CHARACTERISTICS
Tamb= –40°C to )85°C, VCC=)4.5V to )5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by
either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless
otherwise stated.
Value
Characteristic
Supply current
Pin
Units
Conditions
Min
Typ
Max
27
12
20
mA
VCC = 4.5V to 5.5V
Prescaler Input Voltage
13, 14
12.5
300
mVrms 50MHz to 1.3GHz sinewave
See Fig. 5.
Prescaler Input Impedance
Input Capacitance
13, 14
50
2
W
pF
SDA, SCL Input High Voltage
Input Low Voltage
4, 5
4, 5
4, 5
4, 5
4, 5
3
0
5.5
1.5
10
–10
10
V
V
mA
mA
mA
Input High Current
Input Low Current
Leakage Current
Input Voltage = V
CC
Input Voltage = 0V
When V = 0V
CC
SDA
Output Voltage
4
1
1
1
0.4
V
Isink = 3mA
Charge Pump Current Low
Charge Pump Current High
mA
mA
nA
Byte 4 Bit 2 = 0, Pin 1 = 2V
Byte 4 Bit 2 = 1, Pin 1 = 2V
Byte 4 Bit 4 = 1, Pin 1 = 2V
"50
"170
Charge Pump Output Leakage
Current
"5
Charge Pump Drive Output
Current
16
500
10
mA
Vpin 16 = 0.7V
Charge Pump Amplifier Gain
6400
Recommended Crystal series
Resistance
200
W
‘‘Parallel Resonant” crystal.
Resistance specified is max
under all conditions
Crystal Oscillator Drive Level
2
2
80
mVp–p
Crystal Oscillator Negative
Resistance
750
2
1000
W
External Reference Input
Frequency
2
2
8
MHz
AC coupled sinewave
External Reference Input
amplitude
70
200
mVrms AC coupled sinewave
Output Ports
P3 Sink Current
10
10
0.7
10
1
1.5
10
mA
mA
Vout = 12V
Vout 13.2V
P3 Leakage Current
P4–P7 Sink Current
P4–P7 Leakage Current
Input Ports
=
9–6
9–6
mA
mA
Vout = 0.7V
10
Vout = 13.2V
P3 Input Current High
P3 Input Current Low
P4,P5,P7 Input Voltage Low
P4,P5,P7 Input Voltage High
P6 Input Current High
P6 Input Current Low
10
10
+10
–10
0.8
mA
mA
V
Vpin 10 = 13.2V
Vpin 10 = 0V
9,8,6
9,8,6
7
2.7
V
+10
–10
mA
mA
See Table 3 for ADC Levels
7
2
SP5610
PRE
AMP
Q 1
CRYSTAL
Q 2
15 BIT
PROGRAMMABLE
DIVIDER
OSC
FPD
FCOMP
PHASE
COMP
F
DIVIDER
13
14
PRESCALER
2
3
RF IN
ꢀ512/1024
ꢀ
8
LOCK
CHARGE
PUMP
DET
POWER
ON DET
15 BIT LATCH
DIVIDE
1
DOWN
UP
RATIO
POR
CHARGE
PUMP
DRIVE/
SCL
SDA
FL
16 VARICAP
5
4
I2 C BUS
TRANSCEIVER
OUT
CONTROL
DATA
LATCHES
AND CONTROL
LOGIC
CP
TO
5 BIT LATCH
PORT
LEVEL
3 TTL
COMP
ADDRESS 3 BIT
ADC
OS
INFORMATION
SELECT
4
1
4
12
V CC
PORT OUTPUT DRIVERS
15
V EE
10
P3
9
8
7
6
P4
P5
P6
P7
Fig 2. Block diagram
3
SP5610
FUNCTIONAL DESCRIPTION
The SP5610 is programmed from an I2C Bus. Data and
Clock are fed in on the SDA and SCL lines respectively as
defined by the I2C Bus format. The synthesiser can either
accept new data (write mode) or send data (read mode). The
LSB of the address byte (R/W) sets the device into write mode
if it is low and read mode if it is high. The Tables in Fig. 3
illustrate the format of the data. The device can be
programmed to respond to several addresses, which enables
the use of more than one synthesiser in an I2C Bus system.
Table 4 shows how the address is selected by applying a
voltage to P3. When the device receives a correct address
byte, it pulls the SDA line low during the acknowledge period,
and during following acknowledge periods after further data
bytes are programmed. When the device is programmed into
the read mode, the controller accepting the data must pull the
SDA line low during all status byte acknowledge periods to
read another status byte. If the controller fails to pull the SDA
line low during this period, the device generates an internal
STOP condition, which inhibits further reading.
the reference divider. The reference divider division ratio is
switchable from 512 to 1024, and is controlled by bit 7 of byte
4
(TS0); a logic 1 for 512; a logic 0 for 1024. The SP5610 differs
from the SP5510 in this respect, only 512 being available on
the SP5510. Note, the comparison frequency is 7.8125kHz
when a 4MHz reference is used, and divide by 512 is selected.
Bit 2 of byte 4 of the programming data (CP) controls the
current in the charge pump circuit, a logic 1 for "170mA and
a logic 0 for "50mA allowing compensation for the variable
tuning slope of the tuner and also to enable fast channel
changes over the full band. When the device is ‘frequency
locked’ the charge pump current is internally set to "50mA
regardless of CP
Bit 4 of byte 4 (T0) disables the charge pump when it is set
to a logic 1.
.
Bit 8 of byte 4 (OS) switches the charge pump drive
amplifier’s output off when it is set to a logic 1.
Bit 3 of byte 4 (T1) enables various test modes when set
high. These modes are selected by bits 5, 6, 7 of byte 4 (TS2,
TS1, TS0) as detailed in Table 5. When T1 is set low, TS2 and
TS1 are assigned a ‘don’t care’ condition, and TS0 selects the
reference divider ratio as previously described.
Byte 5 programs the output ports P3 to P7; a logic 0 for a
high impedance output and a logic 1 for low impedance (on).
WRITE MODE (Frequency Synthesis)
When the device is in write mode bytes 2+3 select the
synthesised frequency, while bytes 4+5 control the output port
states, charge pump, reference divider ratio and various test
modes.
Once the correct address is received and acknowledged,
the first bit of the next byte determines whether that byte is
interpreted as byte 2 or 4; a logic 0 for frequency information
and a logic 1 for control and output port information. When byte
READ MODE
When the device is in read mode the status byte read from
the device on the SDA line takes the form shown in Table 2.
Bit 1 (POR) is the power–on reset indicator and is set to
a
2
is received the device always expects byte 3 next. Similarly,
logic 1 if the V supply to the device has dropped below 3V
CC
when byte 4 is received the device expects byte 5 next.
Additional data bytes can be entered without the need to
re–address the device until an I2C stop condition is
recognised. This allows a smooth frequency sweep for fine
tuning or AFC purposes.
If the transmission of data is stopped mid–byte (e.g. by
another device on the bus) then the previously programmed
byte is maintained.
(at 25°C), e.g. when the device is initially turned on. The POR
is reset to 0 when the read sequence is terminated by a stop
command. When POR is set high (at low VCC), the
programmed information is lost and the output ports are all set
to high impedance.
Bit 2 (FL) indicates whether the device is phase locked, a
logic 1 is present if the device is locked, and a logic 0 if the
device is unlocked.
Frequency data from bytes 2 and 3 is stored in a 15–bit
register and is used to control the division ratio of the 15–bit
programmable divider. This is preceded by a divide–by–8
prescaler and amplifier to give excellent sensitivity at the local
oscillator input, see Fig. 5. The input impedance is shown in
Fig. 7.
Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports P7,
P5 and P4 respectively. A logic 0 indicates a low level and a
logic 1 a high level. If the ports are to be used as inputs they
should be programmed to a high impedance state (logic 1).
These inputs will then respond to data complying with TTL
type voltage levels.
Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of
the 5 level ADC. The ADC can be used to feed AFC
information to the microprocessor from the IF section of the
receiver, as illustrated in the typical application circuit.
The programmed frequency can be calculated by
multiplying the programmed division ratio by 8 times the
comparison frequency F
.
COMP
When frequency data is entered, the phase comparator, via
a charge pump and varicap drive amplifier, adjusts the local
oscillator control voltage until the output of the programmable
divider is frequency and phased locked to the comparison
frequency.
The reference frequency may be generated by an external
source capacitively coupled into pin 2, or provided by an
on–board crystal controlled oscillator. The comparison
APPLICATION
A typical application is shown in Fig. 4. All input/output
interface circuits are shown in Fig. 6. The SP5610 is function
and pin equivalent to the SP5510 device apart from the
switchable reference divider, and has much lower power
dissipation, improved RF sensitivity and better ESD
performance.
frequency
F
is derived from the reference frequency via
COMP
4
SP5610
MSB
1
LSB
0
ADDRESS
1
0
0
0
MA1
MA0
A
A
A
A
A
Byte
1
Byte 2
Byte 3
Byte 4
Byte 5
14
13
12
11
10
9
8
PROGRAMMABLE
DIVIDER
0
2
2
2
2
2
2
2
7
6
5
4
3
2
1
0
PROGRAMMABLE
DIVIDER
2
2
2
2
2
2
2
2
CONTROL DATA
1
CP
P6
T1
P5
T0
P4
TS2
P3
TS1
X
TS0
X
OS
X
IO PORT CONTROL
DATA
P7
Table 1 Write data format (MSB is transmitted first)
ADDRESS
1
1
0
0
0
MA1
A2
MA0
A1
1
A
A
Byte
1
STATUS BYTE
POR
FL
I2
I1
I0
A0
Byte 2
Table 2 Read data format (MSB is transmitted first)
A:
Acknowledge bit
MA1, MA0:
CP:
T1:
V
ariable address bits (see Table 4)
Charge pump current select
est mode enable
T
T0:
Charge pump disable
TS2, TS1, TS0:
OS:
Operation mode control bits (see Table 5)
Varactor drive Output disable Switch
P7,P6,P5,P4,P3:
POR:
Control output states
Power On Reset indicator
FL:
Phase Lock detect Flag
I2, I1, I0:
A2, A1, A0:
X :
Digital information from Ports P7, P5 and P4, respectively
5 Level ADC data from P6 (see Table 3)
Don’t care
A2
1
A1
0
A0
0
V
oltage input to P6
MA1
MA0
Voltage input to P3
0 – 0.2V
0.6V to 13.2V
0
0
1
1
0
1
0
1
CC
CC
0
1
1
0.45V to 0.6V
ALWAYS VALID
0.3V – 0.7V
CC
CC
CC
CC
CC
0
1
0
0.3V to 0.45V
CC
CC
0
0
1
0.15V to 0.3V
CC
0.8V – 13.2V
CC
0
0
0
0 to 0.15V
CC
Table 4 Address selection
Table 3 ADC levels
T1
TS2
X
TS1
X
TS0
OPERATION MODE DESCRIPTION
0
0
1
1
1
1
1
0
1
X
X
0
1
X
Normal operation, test modes disabled, reference divider ratio=1024
Normal operation, test modes disabled, reference divider ratio=512
Charge pump source (down). Status byte bit FL set to 0
Charge pump sink (up). Status byte bit FL set to 1
Ports P4,P5,P6,P7 set to state X
X
X
0
0
0
1
1
0
1
0
Port P7=F /2; P4,P5,P6 set to state X
PD
1
1
Port P7=F ; P6=F
; P4, P5 set to state X
COMP
PD
X=don’t care
For further details of test modes see Table 6.
Table 5 Operation modes
Fig. 3 Data formats
5
SP5610
+30V
+12V
+5V
IF SECTION
IF SIGNAL
AFC OUTPUT
TUNER
22k
P3
P7
P5
P4
BAND
INPUTS
9
8
7
6
5
4
3
2
1
P6
10
11
12
13
14
15
16
SCL
CONTROL
MICRO
OSCILLATOR
OUTPUT
1n
I2C BUS SDA
4MHz
CRYSTAL
1n
0.1m
18p
47k
10k
39n
V
T
VARICAP
INPUT
180n
10nF
22k
BCW31
Fig. 4 Typical application
300
37.5
25
VIN (mV RMS
INTO 50W)
OPERATING
WINDOW
12.5
50
500
1000
FREQUENCY (MHz)
1300 1500
Fig. 5 Typical input sensitivity
6
SP5610
VCC
VREF
CHARGE
PUMP
3K
3K
RF INPUTS
150
DRIVE
OUTPUT
OS
(O/P DISABLE)
Loop amplifier
RF input
VCC
VCC
67k
SCL/SDA
3k
CRYSTAL Q1
CRYSTAL Q2
ACK
SDA ONL
Y
Reference oscillator
SCL and SDA input
VCC
VCC
PORT
PORT
3k
3k
12k
Ports P7 – P4
Port P3
Fig. 6 Input/output interface circuits
7
SP5610
+j1
+j0.5
+j2
+j0.2
+j5
0
0.2
0.5
1
2
5
1.25GHz
–j5
–j0.2
–j2
–j0.5
FREQUENCY MARKER STEP = 250MHz
S
11
:Z = 50
W
–j1
0
NORMALISED
TO 50W
Fig. 7 Typical input impedance
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to V and pin 3 at 0V
.
EE
Value
Parameter
Supply voltage
Pin
Units
Conditions
Min
Max
7
12
– 0.3
V
RF input voltage
Port voltage
13, 14
2.5
Vp–p
6–10
6–9
10
– 0.3
– 0.3
– 0.3
14
6
14
V
V
V
Port in off state
Port in on state
Port in on state
T
otal port output current
6–10
13, 14
1
50
mA
V
RF input DC offset
– 0.3
– 0.3
– 0.3
– 0.3
– 0.3
– 55
VCC +0.3
VCC+0.3
VCC+0.3
VCC+0.3
6
Charge Pump DC offset
Drive DC offset
V
16
V
Crystal oscillator DC offset
SDA,SCL input voltage
Storage temperature
Junction temperature
2
V
4, 5
V
+150
°C
°C
°C/W
+150
MP16 thermal resistance,
chip–to–ambient
111
MP16 thermal resistance,
chip–to–case
41
°C/W
Power consumption at 5.5V
ESD protection
150
mW
kV
All ports of
f
ALL
4
MIL STD 883C TM 3015
8
SP5610
APPLICATION NOTES
A
generic set of application notes AN168 for designing with
The board can be used for the following purposes:
(A) Measuring RF sensitivity performance.
(B) Indicating port function.
synthesisers such as the SP5610 has been written. This
covers aspects such as loop filter design, decoupling and I2C
bus radiation problems.
(C) Synthesising a voltage controlled oscillator
.
This application note is featured in the Media October 1995
IC Handbook. A generic test/demo board has been produced
which can be used for the SP5610. A circuit diagram and
layout for the board is shown in Figs. 8 and 9.
(D) Testing of external reference sources.
The programming codes relevant to these tests are shown
Table 6.
in
+30V
+5V
+12V
C9
C8
C7/C8/C9 = 100nF
EXTERNAL REFERENCE
MODE SELECT
SKT2
R11 3K0
C6
C7
S1
10nF*
*(NOT FITTED)
C3 47nF
R7 22K
R8
22K
R12 1K0
S2
P3
VAR
GND
R9
R10
C2
10K
47K
C14
C1
220nF
X1
1
2
3
4
16
T1
2N3904
18pF
4MHz
10nF
15
TP1
RF INPUT
14
13
12
11
C4 1nF
C5 1nF
DATA/SDA
C12
100pF
5
6
7
8
C10
1nF
CLOCK/SCL
C13
100pF
R14
22K
10
9
ENABLE/
ADDRESS SEL
R13 12K
T2
2N3906
P1
P4
PIN NO:
6
7
8
C11
1nF
9
10 11
FOR EXTERNAL REFERENCE CAPACITOR
C6 SHOULD BE FITTED AND CAPACITOR C1
REMOVED FROM THE TEST BOARD
Fig. 8 Test board
9
SP5610
P2
P3
TP1 = PIN 3 DC BIAS
TP1
P4
P1
Top view (Ground plane)
Underside (surface mount components side)
NOTES:
CIRCUIT SCHEMATIC IS SHOWN IN FIG. 8.
ALL SURFACE MOUNT COMPONENTS
MOUNTED ON UNDERSIDE OF BOARD
Fig. 9 Test board (layout)
10
SP5610
TEST MODES
As explained earlier in the data sheet, the device can be programmed into a number of test modes. These are invoked by
programming the following HEX codes into Byte 4. The most commonly used codes are shown in Table 6
HEX CODE (BYTE 4)
DESCRIPTION
CP HI MODE
CP LO MODE
Normal operation, REF DIV =1024
Normal operation, REF DIV = 512
Charge Pump Source (Down), FL SET to 0
Charge Pump Sink (up), FL SET to 1
Port P7 = FPD/2
CC
CE
E2
E6
EA
EE
DE
CF
DF
8C
8E
A2
A6
AA
AE
9E
8F
9F
Port P7 = F ; P6 = F
PD
COMP
Charge Pump Disable, REF DIV ꢀ 512
Varactor Line Disable, REF DIV 512
ꢀ
Charge Pump and Varactor Line Disable, REF DIV
ꢀ
512
Table 6 Useful test modes.
Other codes will also apply due to ‘Don’t Care’ conditions,
which are assumed to be 1 in the above Table.
reference divider ratio, (see Table 6) then secondly to switch
on the chosen test mode.
The pulses can then be measured by simply connecting an
oscilloscope or counter to the relevant output pin on the test
board.
NOTE:
When looking at F or F
signals from Ports P7 and
COMP
PD
P6, Byte 4 should be sent twice, firstly to set the desired
11
SP5610
16 LEAD MINIATURE PLASTIC MP16
9.80/10.01
(0.386/0.394)
0.69 (0.027) NOM
T 4 PLACES
A
PIN 1
1.27 (0.050) NOM
PIN SPACING
PIN 1 IDENTIFICATION
0.25/0.51
(0.010/0.020) X45°
0.19/0.25
(0.007/0.010)
8°MAX
0.41/1.27
(0.016/0.050)
0.35/0.49
(0.014/0.019)
0.10/0.25
(0.004/0.010)
5.80/6.20
(0.228/0.244)
Purchase of GEC Plessey I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the
standard I2C Standard Specification as defined by Philips.
All brand names and product names used in this publication are trademarks,
registered trademarks or trade names of their respective owners.
Internet: http//www.gpsemi.com
HEADQUARTERS OPERATIONS
CUSTOMER SERVICE CENTRES
GEC PLESSEY SEMICONDUCTORS
F
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Cheney Manor, Swindon,
Fax: (1) 64 46 06 07
Wiltshire United Kingdom SN2 2QW
.
F GERMANY Munich Tel: (089) 3609 06 0 Fax: (089) 3609 06 55
T
el: (01793) 518000
F ITALY Milan Tel: (02) 6607151 Fax: (02) 66040993
Fax: (01793) 51841
1
F JAPAN Tokyo Tel: (03) 5276–5501 Fax: (03) 5276–5510
KOREA Seoul Tel: (2) 5668141 Fax: (2) 5697933
F
NORTH AMERICA Scotts Valley, USA
el: (408) 438 2900 Fax: (408) 438 7023
T
GEC PLESSEY SEMICONDUCTORS
.O. Box 660017 1500 Green Hills Road,
F
F
SOUTH EAST ASIA Singapore Tel: 3827708 Fax: 3828872
SWEDEN Stockholm Tel: (8) 702 97 70 Fax: (8) 640 47 36
P
Scotts Valley, California 95067–0017,
United States of America. Tel: (408) 438 5576/6231
Fax: (408) 438 5576
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F
UK, EIRE, DENMARK, FINLAND & NORWAY
Swindon Tel: (01793) 518527/518566 Fax: (01793) 518582
These are supported by Agents and Distributors in major countries world–wide.
E
GEC Plessey Semiconductors 1997 Publication No. D.S. 3920 Issue No. 3.3 February 1997
TECHNICAL DOCUMENT TION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM
A
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
相关型号：
SP5611E3
Trans Voltage Suppressor Diode, 1500W, 40.3V V(RWM), Unidirectional, 1 Element, Silicon, HERMETICALLY SEALED, GLASS PACKAGE-2
MICROSEMI
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