ZL30143GGG [ZARLINK]
Telecom IC;
| 型号： | ZL30143GGG |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Telecom IC ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总4页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL30143
SyncE SONET/SDH
G.8262/Stratum3 System Synchronizer/SETS
Short Form Data Sheet
July 2009
Features
Ordering Information
•
Supports the requirements of ITU-T G.8262 for
synchronous Ethernet Equipment slave Clocks
(EEC option 1 and 2)
ZL30143GGG 100 Pin CABGA
ZL30143GGG2 100 Pin CABGA*
Trays
Trays
*Pb Free Tin/Silver/Copper
•
Supports the requirements of Telcordia GR-1244
Stratum 3 and GR-253, ITU-T G.813, and G.781
SETS
-40oC to +85oC
•
•
•
Supports ITU-T G.823, G.824 and G.8261 for 2048
kbit/s and 1544 kbit/s interfaces
•
•
Internal state machine automatically controls
mode of operation (free-run, locked, holdover)
Meets the SONET/SDH jitter generation
requirements up to OC-48/STM-16
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
Synchronizes to telecom reference clocks (2 kHz,
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to
Ethernet reference clocks (25 MHz, 50 MHz,
62.5 MHz, 125 MHz)
•
•
Provides automatic reference switching and
holdover during loss of reference input
Supports master/slave configuration and dynamic
input to output delay compensation for
AdvancedTCATM
•
•
Supports composite clock inputs (64 kHz, 64 kHz +
8 kHz, 64kHz + 8 kHz + 400 Hz)
Generates standard SONET/SDH clock rates (e.g.,
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for
synchronizing Gigabit Ethernet PHYs
•
Configurable input to output delay and output to
output phase alignment
Applications
•
•
•
ITU-T G.8262 System Timing Cards which support
1 GbE and 10 GbE interfaces
•
Programmable output synthesizers (P0, P1)
generate telecom clock frequencies from any
multiple of 8 kHz up to 100 MHz
Telcordia GR-253 Carrier Grade SONET/SDH
Stratum 3 System Timing Cards
•
•
Generates several styles of telecom frame pulses
with selectable pulse width, polarity and frequency
System Timing Cards which supports ITU-T G.781
SETS (SDH Equipment Timing Source)
Provides two DPLLs which are independently
configurable through a serial interface
dpll2_ref
osci
osco
DPLL2
T4
P1
p1_clk0
p1_clk1
refm
Synthesizer
p0_clk0
p0_clk1
p0_fp0
p0_fp1
/N1
/N2
ref0
ref1
P0
Synthesizer
ref2
ref3
ref4
ref5
ref6
ref7
diff0
diff1
DPLL1
T0
refn/syncn
Input
Ports
SONET/SDH/
Ethernet
APLL
ref8
apll_clk0
apll_clk1
apll_fp0
apll_fp1
sync0
sync1
sync2
sync8
fb_clk
Feedback
Synthesizer
Ref/Sync
Monitors
ext_fb_clk
ext_fb_fp
I2C/SPI
hold
JTAG
mode
lock
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30143
Short Form Data Sheet
1.0 Overview
The ZL30143 System Synchronizer and SETS device is a highly integrated device that provides all of the
functionality that is required for a central timing card in carrier grade network equipment. The basic functions of a
central timing card include:
•
•
•
•
•
•
•
Input reference monitoring for both frequency accuracy and phase irregularities
Automatic input reference selection
Support of both external timing and line timing modes
Hitless reference switching
Wander and jitter filtering
Master/slave crossover for minimizing phase alignment between redundant timing cards
Independent derived output timing path for support of the SETS functionality
In a typical application, the main timing path uses DPLL1 to synchronize to either an external BITS source or to a
recovered line timed source. DPLL1 monitors all references and automatically selects the best available reference
based on configurable priority and revertive properties. DPLL1 provides the wander filtering function and the P0
synthesizer generates a jitter filtered clock and frame pulse for the system timing bus which supplies all line cards
with a common timing reference. The APLL is used to generate a reference clock for an Ethernet PHY which can be
used to synchronize remote equipment. A derived output timing path using DPLL2 is available to support the SETS
function. In this case DPLL2 uses a filter above 10 Hz to prevent it from filtering wander.
D erived
O u tp u t
D erived
O u tp u t
S yn cE
S yn cE
B ITS A
B ITS B
C en tral
T im in g
C ard
C en tral
T im in g
C ard
G bE
P H Y
G bE
P H Y
Z L30143
ZL30143
P 1
P 1
P 0
A P LL
A P LL
P 0
D P LL1
T0
D P LL2
T4
D P LL2
T4
D P LL1
T0
S
P
P
S
L in e R eco vered T im in g
S ystem T im ing B u s
S
P
B
A
B
A
A
B
T x
D P LL
T x
D P LL
ZL 30136
ZL 30117
G b E L in e
C ard
S O N E T /S D H
P H Y
P H Y
L in e C ard
Figure 2 - Typical Application of the ZL30143
2
Zarlink Semiconductor Inc.
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