ZL38001DGA [ZARLINK]
Low-Voltage Acoustic Echo Canceller with Low ERL Compensation; 低压声学回声消除器低ERL补偿
| 型号： | ZL38001DGA |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Low-Voltage Acoustic Echo Canceller with Low ERL Compensation |
| 文件： | 总47页 (文件大小：646K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL38001
Low-Voltage Acoustic Echo Canceller
with Low ERL Compensation
Data Sheet
June 2004
Features
•
Contains two echo cancellers: 112 ms acoustic
echo canceller
Ordering Information
•
Works with low cost voice codec. ITU-T G.711 or
signed mag µ/A-Law, or linear 2’s comp
ZL38001DGA 36 Pin QSOP
ZL38001QDC 48 Pin TQFP
•
•
Each port may operate in different format
-40°C to +85°C
Advanced NLP design - full duplex speech with
no switched loss on audio paths
•
•
ST-BUS, GCI, or variable-rate SSI PCM interfaces
•
•
•
•
•
Fast re-convergence time: tracks changing echo
environment quickly
User gain control provided for speaker path
(-24 dB to +48 dB in 3 dB steps)
Adaptation algorithm converges even during
Double-Talk
•
18 dB gain at Sout to compensate for high ERL
environments
Designed for exceptional performance in high
background noise environments
•
•
•
•
•
•
•
AGC on speaker path
Handles up to 0 dB acoustic echo return loss
Transparent data transfer and mute options
20 MHz master clock operation
Provides protection against narrow-band signal
divergence
Howling prevention stops uncontrolled oscillation
in high loop gain conditions
Low power mode during PCM Bypass
Bootloadable for future factory software upgrades
2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs
•
•
Offset nulling of all PCM channels
Serial micro-controller interface
Limiter
S1
S3
S2
+
µ/A-Law/
Linear
Linear/
µ/A-Law
ADV
NLP
18dB
Gain
Offset
Null
+
Sin
Sout
-
DATA1
DATA2
MD1
Program
RAM
NBSD
Micro
Interface
CONTROL
UNIT
Program
ROM
Adaptive
Filter
Double
Talk
Detector
Howling
Controller
NBSD
R1
R3
SCLK
CS
MD2
Rout
-24 -> +48dB
R2
Offset
Null
User
Gain
µ/A-Law/
Linear
Linear/
µ/A-Law
Rin
AGC
Limiter
VSS
VDD
BCLK/C4i
FORMAT
ENA1
MCLK
RESET
ENA2
LAW
F0i
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
ZL38001
Data Sheet
Applications
•
Handsfree in automobile applications
1
2
3
4
5
36 IC
ENA1
MD1
ENA2
MD2
Rin
Sin
IC
MCLK
35
IC
34
33
32
31
30
29
28
27
26
25
24
23
IC
MCLK2
NC
VSS
VDD2
VSS2
IC
36
38
34
32
30
28
26
NC
MCLK2
IC
IC
IC
NC
ENA1
NC
MD1
ENA2
MD2
Rin
24
22
20
18
16
14
Sout
VDD
NC
DATA1
NC
DATA2
NC
CS
6
7
8
9
10
11
12
13
14
15
16
17
18
40
42
44
46
48
IC
IC
IC
QSOP
TQFP
IC
BCLK/C4i
F0i
Rout
Sout
SCLK
NC
NC
LAW
FORMAT
RESET
NC
RESETB
22
VDD
2
4
6
8
10
12
21
20
19
NC
DATA1
DATA2
NC
SCLK
CS
Figure 2 - Pin Connections
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
Pin Description
QSOP
Pin #
TQFP
Pin #
Name
Description
1
43
ENA1
SSI Enable Strobe/ST-BUS & GCI Mode for Rin/Sout (Input). This pin
has dual functions depending on whether SSI or ST-BUS/GCI is selected.
For SSI, this strobe must be present for frame synchronization. This is an
active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for on Rin/Sout pins. Strobe period is 125
microseconds. For ST-BUS or GCI, this pin, in conjunction with the MD1
pin, selects the proper mode for Rin/Sout pins (see ST-BUS and GCI
Operation description).
2
3
45
46
MD1
ST-BUS & GCI Mode for Rin/Sout (Input). When in ST-BUS or GCI
operation, this pin, in conjunction with the ENA1 pin, will select the proper
mode for Rin/Sout pins (see ST-BUS and GCI Operation description).
Connect this pin to Vss in SSI mode.
ENA2
SSI Enable Strobe /ST-BUS & GCI Mode for Sin/Rout (Input). This pin
has dual functions depending on whether SSI or ST-BUS/GCI is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide,
enabling serial PCM data transfer on Sin/Rout pins. Strobe period is 125
microseconds. For ST-BUS/GCI, this pin, in conjunction with the MD2 pin,
selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation
description).
4
5
6
47
48
2
MD2
Rin
Sin
IC
ST-BUS & GCI Mode for Sin/Rout (Input). When in ST-BUS or GCI
operation, this pin in conjunction with the ENA2 pin, selects the proper
mode for Sin/Rout pins (see ST-BUS and GCI Operation description).
Connect this pin to Vss in SSI mode.
Receive PCM Signal Input (Input). 128 kbps to 4096 kbps serial PCM
input stream. Data may be in either companded or 2’s complement linear
format. This is the Receive Input channel from the line (or network) side.
Data bits are clocked in following SSI, GCI or ST-BUS timing requirements.
Send PCM Signal Input (Input). 128 kbps to 4096 kbps serial PCM input
stream. Data may be in either companded or 2’s complement linear format.
This is the Send Input channel (from the microphone). Data bits are
clocked in following SSI, GCI or ST-BUS timing requirements.
7
8
3
5
Internal Connection (Input). Must be tied to Vss.
MCLK Master Clock (Input). Nominal 20 MHz Master Clock input (may be
asynchronous relative to 8 KHz frame signal.) Tie together with MCLK2
(pin 33).
9,10,11
12
6, 7, 8
9
IC
Internal Connection (Input). Must be tied to Vss.
LAW
A/µ Law Select (Input). When low, selects µ−Law companded PCM.
When high, selects A-Law companded PCM. This control is for both serial
pcm ports.
13
14
11
13
FORMAT ITU-T/Sign Mag (Input). When low, selects sign-magnitude PCM code.
When high, selects ITU-T (G.711) PCM code. This control is for both serial
pcm ports.
RESET Reset / Power-down (Input). An active low resets the device and puts the
ZL38001 into a low-power stand-by mode.
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
Pin Description (continued)
QSOP
Pin #
TQFP
Pin #
Name
Description
17
18
19
16
17
19
SCLK
Serial Port Synchronous Clock (Input). Data clock for the serial
microport interface.
CS
Serial Port Chip Select (Input). Enables serial microport interface data
transfers. Active low.
DATA2 Serial Data Receive (Input). In Motorola/National serial microport
operation, the DATA2 pin is used for receiving data. In Intel serial microport
operation, the DATA2 pin is not used and must be tied to Vss or Vdd.
20
21
DATA1 Serial Data Port (Bidirectional). In Motorola/National serial microport
operation, the DATA1 pin is used for transmitting data. In Intel serial
microport operation, the DATA1 pin is used for transmitting and receiving
data.
22
23
23
24
VDD
Sout
Positive Power Supply (Input). Nominally 3.3 volts.
Send PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM
output stream. Data may be in either companded or 2’s complement linear
PCM format. This is the Send Out signal after acoustic echo cancellation
and non-linear processing. Data bits are clocked out following SSI, ST-
BUS or GCI timing requirements.
24
26
Rout
F0i
Receive PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM
output stream. Data may be in either companded or 2’s complement linear
PCM format. This is the Receive out signal after line echo cancellation non-
linear processing, AGC and gain control. Data bits are clocked out
following SSI, ST-BUS or GCI timing requirements.
25
26
27
29
Frame Pulse (Input). In ST-BUS (or GCI) operation, this is an active-low
(or active-high) frame alignment pulse, respectively. SSI operation is
enabled by connecting this pin to Vss.
BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz
to 4.096 MHz bit clock. This clock must be synchronous with ENA1 and
ENA2 enable strobes.
In ST-BUS or GCI operation, C4i pin must be connected to the 4.096 MHz
(C4) system clock.
27, 28
29
30, 31
33
IC
Internal Connection (Input). Tie to Vss.
Digital Ground (Input). Nominally 0 volts.
VSS2
30
34
VDD2 Positive Power Supply (Input). Nominally 3.3 volts (tie together with
VDD, pin 22).
31
33
35
38
VSS
Digital Ground (Input). Nominally 0 volts (tie together with VSS2, pin 29).
MCLK2 Master Clock (Input). Nominal 20 MHz master clock (tie together with
MCLK, pin 8).
34,35,36
39, 40, 41
IC
Internal Connection (Input). Tie to Vss.
15, 16, 21, 1, 4, 10, 12,
NC
No Connect (Output). This pin should be left unconnected.
32
14, 15, 18,
20, 22, 25,
28, 32, 36,
37, 42, 44
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
Table of Contents
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 Adaptation Speed Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Advanced Non-Linear Processor (ADV-NLP)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Narrow Band Signal Detector (NBSD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Howling Detector (HWLD)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Offset Null Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7 User Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.8 AGC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.9 18 dB Gain Pad at Sout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.10 Mute Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.11 Bypass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.12 Adaptation Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.13 ZL38001 Throughput Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.14 Power Down / Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.0 PCM Data I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 ST-BUS and GCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 SSI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 PCM Law and Format Control (LAW, FORMAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4 Linear PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 Bit Clock (BCLK/C4i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6 Master Clock (MCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.0 Microport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 Bootload Process and Execution from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.0 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 0 (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 2 (Mode 2) . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5 - ST-BUS and GCI 8-Bit Companded PCM I/O with D and C channels (Mode 3) . . . . . . . . . . . . . . . . . . 15
Figure 6 - ST-BUS and GCI 16-Bit 2’s Complement Linear PCM I/O (Mode 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7 - SSI Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8 - Serial Microport Timing for Intel Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9 - Serial Microport Timing for Motorola Mode 00 or National Microwire . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10 - Master Clock - MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11 - GCI Data Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12 - ST-BUS Data Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13 - SSI Data Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14 - INTEL Serial Microport Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15 - Motorola Serial Microport Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
List of Tables
Table 1 - Quiet PCM Code Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2 - ST-BUS & GCI Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3 - SSI Enable Strobe Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4 - Companded PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5 - Bootload RAM Control (BRC) Register States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6 - Reference Level Definition for Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
List of Register Tables
Register Table 1 - Main Control Register (MC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Register Table 2 - Acoustic Echo Canceller Control Register (AEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Register Table 3 - Line Echo Canceller Control Register (LEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Register Table 4 - Acoustic Echo Canceller Status Register (ASR) (* Do not write to this register) . . . . . . . . . . . . . 31
Register Table 5 - Line Echo Canceller Status Register (LSR) (* Do not write to this register) . . . . . . . . . . . . . . . . 32
Register Table 6 - Receive Gain Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Register Table 7 - Double Talk Gain Control Register 1 (DTGCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Register Table 8 - Double Talk Gain Control Register 2 (DTGCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Register Table 9 - Double Talk detection Threshold Register (DTDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Register Table 10 - Receive (Rin) Peak Detect Register 1 (RIPD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Register Table 11 - Receive (Rin) Peak Detect Register 2 (RIPD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Register Table 12 - Receive (Rin) ERROR Peak Detect Register 1 (REPD1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Register Table 13 - Receive (Rin) ERROR Peak Detect Register 2 (REPD2). . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Register Table 14 - Receive (Rout) Peak Detect Register 1 (ROPD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Register Table 15 - Receive (Rout) Peak Detect Register 2 (ROPD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Register Table 16 - Send (Sin) Peak Detect Register 1 (SIPD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Register Table 17 - Send (Sin) Peak Detect Register 2 (SIPD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Register Table 18 - Send ERROR Peak Detect Register 1 (SEPD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Register Table 19 - Send ERROR Peak Detect Register 2 (SEPD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Register Table 20 - Send (Sout) Peak Detect Register 1 (SOPD1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Register Table 21 - Send (Sout) Peak Detect Register 2 (SOPD2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Register Table 22 - Rout Limiter Register 1 (RL1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Register Table 23 - Rout Limiter Register 2 (RL2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Register Table 24 - Sout Limiter Register (SL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Register Table 25 - Firmware Revision Code Register (FRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Register Table 26 - Bootload RAM Control Register (BRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Register Table 27 - Bootload RAM Signature Register (SIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
1.0 Functional Description
The ZL38001 device contains an acoustic echo cancellers, as well as the many control functions necessary to
operate the echo canceller. The ZL38001 provides clear signal transmission in both audio path directions to ensure
reliable voice communication, even with low level signals. The ZL38001 does not use variable attenuators during
double-talk or single-talk periods of speech, as do many other acoustic echo cancellers for speakerphones.
Instead, the ZL38001 provides high performance full-duplex operation similar to network echo cancellers, so that
users experience clear speech and uninterrupted background signals during the conversation. This prevents
subjective sound quality problems associated with “noise gating” or “noise contrasting”.
The ZL38001 uses an advanced adaptive filter algorithm that is double-talk stable, which means that convergence
takes place even while both parties are talking1. This algorithm allows continual tracking of changes in the echo
path, regardless of double-talk, as long as a reference signal is available for the echo canceller.
The echo tail cancellation capability of the acoustic echo canceller has been sized appropriately (112 ms) to cancel
echo in an average sized office with a reverberation time of less than 112 ms.
In addition to the echo cancellers, the following functions are supported:
•
Control of adaptive filter convergence speed during periods of double-talk, far end single-talk and near-end
echo path changes
•
•
•
•
•
•
•
Control of Non-Linear Processor thresholds for suppression of residual non-linear echo
Howling detector to identify when instability is starting to occur and to take action to prevent oscillation
Narrow-Band Detector for preventing adaptive filter divergence caused by narrow-band signals
Offset Nulling filters for removal of DC components in PCM channels
Limiters that introduce controlled saturation levels
Serial controller interface compatible with Motorola, National and Intel microcontrollers
PCM encoder/decoder compatible with µ/A-Law ITU-T G.711, µ/A-Law Sign-Mag or linear 2’s complement
coding
•
Automatic gain control on the receive speaker path
1.1 Adaptation Speed Control
The adaptation speed of the acoustic echo canceller is designed to optimize the convergence speed versus
divergence caused by interfering near-end signals. Adaptation speed algorithm takes into account many different
factors such as relative double-talk condition, far end signal power, echo path change and noise levels to achieve
fast convergence.
1.2 Advanced Non-Linear Processor (ADV-NLP)1
After echo cancellation, there is likely to be residual echo which needs to be removed so that it will not be audible.
The ZL38001 uses an NLP to remove low level residual echo signals which are not comprised of background noise.
The operation of the NLP depends upon a dynamic activation threshold, as well as a double-talk detector which
disables the NLP during double-talk periods.
The ZL38001 keeps the perceived noise level constant, without the need for any variable attenuators or gain
switching that causes audible “noise gating”. The noise level is constant and identical to the original background
noise even when the NLP is activated.
The NLP can be disabled by setting the NLP- bit to 1 in the AEC control registers.
1. Patent pending.
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
1.3 Narrow Band Signal Detector (NBSD)1
Single or multi-frequency tones (e.g,. DTMF, or signalling tones) present in the reference input of an echo canceller
for a prolonged period of time may cause the adaptive filter to diverge. The Narrow Band Signal Detector (NBSD) is
designed to prevent this divergence by detecting single or multi-tones of arbitrary frequency, phase, and amplitude.
When narrow band signals are detected, the filter adaptation process is stopped but the echo canceller continues to
cancel echo.
The NBSD can be disabled by setting the NB- bit to 1 in the MC control registers.
1.4 Howling Detector (HWLD)1
The Howling detector is part of an Anti-Howling control, designed to prevent oscillation as a result of positive
feedback in the audio paths.
The HWLD can be disabled by setting the AH- bit to 1 in the (MC) control register.
1.5 Offset Null Filter
To ensure robust performance of the adaptive filters at all times, any DC offset that may be present on either the
Rin signal or the Sin signal, is removed by highpass filters. These filters have a corner frequency placed at 40 Hz.
The offset null filters can be disabled by setting the HPF- bit to 1 in the AEC control registers.
1.6 Limiters
To prevent clipping in the echo paths, two limiters with variable thresholds are provided at the outputs.
The Rout limiter threshold is in Rout Limiter Register 1 and 2. The Sout limiter threshold is in Sout Limiter Register.
Both output limiters are always enabled.
1.7 User Gain
The user gain function provides the ability for users to adjust the audio gain in the receive path (speaker path). This
gain is adjustable from -24 dB to +48 dB in 3 dB steps. It is important to use ONLY this user gain function to adjust
the speaker volume. The user gain function in the ZL38001 is optimally placed between the two echo cancellers
such that no reconvergence is necessary after gain changes.
The gain can be accessed through Receive Gain Control Register.
1. Patent Pending
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
1.8 AGC
The AGC function is provided to limit the volume in the speaker path. The gain of the speaker path is automatically
reduced during the following conditions:
•
•
•
•
When clipping of the receive signal occurs
When initial convergence of the acoustic echo canceller detects unusually large echo return
When howling is detected
The AGC can be disabled by setting the AGC- bit to 1 in MC control register
1.9 18 dB Gain Pad at Sout
The purpose of the 18 dB gain pad is to improve the subjective quality in low ERL environments. The ZL38001 can
cancel echo with a ERL as low as 0 dB (attenuation from Rout to Sin). In many hand free applications, the ERL can
be low (or negative). This is due to both speaker and microphone gain setting. The speaker gain has to be set high
enough for the speaker to be heard properly and the microphone gain needs to be set high enough to ensure
sufficient signal is sent to the far end. If the ERL (Acoustic Attenuation - speaker gain - microphone gain) is greater
than 0 dB, then the echo canceller cannot cancel echo. To overcome this limitation, the ZL38001 has a 18 dB gain
pad at Sout. The microphone gain can be reduced by 18 dB to allow either the speaker gain and/or the acoustic
coupling to be increased by a total of 18 dB allowing more flexibility in the design.
1.10 Mute Function
A pcm mute function is provided for independent control of the Receive and Send audio paths. Setting the MUTE_R
or MUTE_S bit in the MC register, causes quiet code to be transmitted on the Rout or Sout paths respectively.
Quiet code is defined according to the following table.
LINEAR
16 bits
SIGN/
MAGNITUDE
µ-Law
CCITT (G.711)
µ-Law
A-Law
2’s complement
A-Law
+Zero
0000h
80h
FFh
D5h
(quiet code)
Table 1 - Quiet PCM Code Assignment
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
1.11 Bypass Control
A PCM bypass function is provided to allow transparent transmission of pcm data through the ZL38001. When the
bypass function is active, pcm data passes transparently from Rin to Rout and from Sin to Sout, with bit-wise
integrity preserved.
When the Bypass function is selected, most internal functions are powered down to provide low power
consumption.
The BYPASS control bit is located in the main control MC register.
1.12 Adaptation Enable/Disable
Adaptation control bits are located in the AEC and LEC control registers. When the ADAPT- bit is set to 1, the
adaptive filter is frozen at the current state. In this state, the device continues to cancel echo with the current echo
model.
When the ADAPT- bit is set to 0, the adaptive filter is continually updated. This allows the echo canceller to adapt
and track changes in the echo path. This is the normal operating state.
1.13 ZL38001 Throughput Delay
In all modes, voice channels always have 2 frames of delay. In ST-BUS/GCI operation, the D and C channels have
a delay of one frame.
1.14 Power Down / Reset
Holding the RESET pin at logic low will keep the ZL38001 device in a power-down state. In this state all internal
clocks are halted, and the DATA1, Sout and Rout pins are tristated.
The user should hold the RESET pin low for at least 200 msec following power-up. This will insure that the device
powers up in a proper state. Following any return of RESET to logic high, the user must wait for 8 complete 8 KHz
frames prior to writing to the device registers. During this time, the initialization routines will execute and set the
ZL38001 to default operation (program execution from ROM using default register values).
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
2.0 PCM Data I/O
The PCM data transfer for the ZL38001 is provided through two PCM ports. One port consists of Rin and Sout pins
while the second port consists of Sin and Rout pins. The data are transferred through these ports according to
either ST-BUS, GCI or SSI conventions and the device automatically detects the correct convention. The device
determines the convention by monitoring the signal applied to the F0i pin. When a valid ST-BUS (active low) frame
pulse is applied to the F0i pin, the ZL38001 will assume ST-BUS operation. When a valid GCI (active high) frame
pulse is applied to the F0i pin, the device will assume GCI operation. If F0i is tied continuously to Vss, the device
will assume SSI operation. Figures 11 to 13 show timing diagrams of these 3 PCM-interface operation conventions.
2.1 ST-BUS and GCI Operation
The ST-BUS PCM interface conforms to Zarlink’s ST-BUS standard with an active-low frame pulse. Input data is
clocked in by the rising edge of the bit clock (C4i) three-quarters of the way into the bitcell and output data bit
boundaries (Rout, Sout) occur every second falling edge of the bit clock (see Figure 11.) The GCI PCM interface
corresponds to the GCI standard commonly used in Europe with an active-high frame pulse. Input data is clocked in
by the falling edge of the bit clock (C4i) three-quarters of the way into the bitcell and output data bit boundaries
(Rout, Sout) occur every second rising edge of the bit clock (see Figure 12.)
Either of these interfaces (STBUS or GCI) can be used to transport 8 bit companded PCM data (using one timeslot)
or 16 bit 2’s complement linear PCM data (using two timeslots). The MD1/ENA1 pins select the timeslot on the
Rin/Sout port while the MD2/ENA2 pin selects the timeslot on the Sin/Rout port, as in Table 2. Figures 3 to 6
illustrate the timeslot allocation for each of these four modes.
C4i
start of frame (stbus & GCI)
F0i (ST-BUS)
0
1
2
3
4
B
F0i (GCI)
PORT1
Rin
7 6 5 4 3 2 1 0
EC
Sout
7 6 5 4 3 2 1 0
PORT2
Sin
7 6 5 4 3 2 1 0
EC
7 6 5 4 3 2 1 0
Rout
outputs = High impedance
inputs = don’t care
In ST-BUS/GCI Mode 1, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 0. Note that the user can configure PORT1
and PORT2 into different modes.
Figure 3 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 0 (Mode 1)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
C4i
start of frame (stbus & GCI)
F0i (ST-BUS)
F0i (GCI)
0
1
2
3
4
B
PORT1
Rin
7 6 5 4 3 2 1 0
EC
Sout
7 6 5 4 3 2 1 0
PORT2
Sin
7 6 5 4 3 2 1 0
EC
7 6 5 4 3 2 1 0
Rout
outputs = High impedance
inputs = don’t care
In ST-BUS/GCI Mode 2, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 2. Note that the user can configure PORT1
and PORT2 into different modes.
Figure 4 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 2 (Mode 2)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
C4i
start of frame (stbus & GCI)
F0i (ST-BUS)
0
1
2
3
4
B
C
D
F0i (GCI)
PORT1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Rin
EC
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Sout
PORT2
Sin
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
EC
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Rout
outputs = High impedance
inputs = don’t care
indicates that an input channel is bypassed to an output channel
ST-BUS/GCI Mode 3 supports connection to 2 B+D devices where timeslots 0 and 1 transport D and C channels and echo canceller
(EC) I/O channels are assigned to ST-BUS timeslot 2 (B). Both PORT1 and PORT2 must be configured in Mode 3.
Figure 5 - ST-BUS and GCI 8-Bit Companded PCM I/O with D and C channels (Mode 3)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
C4i
start of frame (stbus & GCI)
F0i (stbus)
F0i (GCI)
Rin
S 141312 1110 9 8 7 6 5 4 3 2 1 0
PORT1
EC
S 141312 1110 9 8 7 6 5 4 3 2 1 0
Sout
Sin
S 141312 1110 9 8 7 6 5 4 3 2 1 0
PORT2
EC
S 141312 1110 9 8 7 6 5 4 3 2 1 0
Rout
outputs = High impedance
inputs = don’t care
ST-BUS/GCI Mode 4 allows 16 bit 2’s complement linear data to be transferred using ST-BUS/GCI I/O timing. Note that PORT1 and
PORT2 need not necessarily both be in mode 4.
Figure 6 - ST-BUS and GCI 16-Bit 2’s Complement Linear PCM I/O (Mode 4)
PORT1
ST-BUS/GCI Mode
Selection
PORT2
Rin/Sout
Sin/Rout
Enable Pins
Enable Pins
MD1
ENA1
MD2
ENA2
0
0
Mode 1. 8 bit companded PCM I/O on timeslot 0
Mode 2. 8 bit companded PCM I/O on timeslot 2.
0
0
0
1
1
0
0
1
1
0
Mode 3. 8 bit companded PCM I/O on timeslot 2.
Includes D & C channel bypass in timeslots 0 & 1.
1
1
Mode 4. 16-bit 2’s complement linear PCM I/O on
timeslots 0 & 1.
1
1
Table 2 - ST-BUS & GCI Mode Select
2.2 SSI Operation
The SSI PCM interface consists of data input pins (Rin, Sin), data output pins (Sout, Rout), a variable rate bit clock
(BCLK), and two enable pins (ENA1, ENA2) to provide strobes for data transfers. The active high enable may be
either 8 or 16 BCLK cycles in duration. Automatic detection of the data type (8 bit companded or 16-bit 2’s
complement linear) is accomplished internally. The data type cannot change dynamically from one frame to the
next.
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
In SSI operation, the frame boundary is determined by the rising edge of the ENA1 enable strobe (see Figure 7).
The other enable strobe (ENA2) is used for parsing input/output data and it must pulse within 125 microseconds of
the rising edge of ENA1.
In SSI operation, the enable strobes may be a mixed combination of 8 or 16 BCLK cycles allowing the flexibility to
mix 2’s complement linear data on one port (e.g., Rin/Sout) with companded data on the other port (e.g., Sin/Rout).
Enable Strobe Pin
Designated PCM I/O Port
ENA1
ENA2
Line Side Echo Path (PORT 1)
Acoustic Side Echo Path (PORT 2)
Table 3 - SSI Enable Strobe Pins
2.3 PCM Law and Format Control (LAW, FORMAT)
The PCM companding/coding law used by the ZL38001 is controlled through the LAW and FORMAT pins. ITU-T
G.711 companding curves for µ-Law and A-Law are selected by the LAW pin. PCM coding ITU-T G.711 and Sign-
Magnitude are selected by the FORMAT pin. See Table 4.
BCLK
start of frame (SSI)
PORT1
ENA1
8 or 16 bits
Rin
EC
Sout
8 or 16 bits
PORT2
ENA2
8 or 16 bits
Sin
EC
8 or 16 bits
Rout
outputs = High impedance
inputs = don’t care
Note that the two ports are independent so that, for example, PORT1 can operate with 8-bit enable strobes and PORT2 can operate
with 16-bit enable strobes.
Figure 7 - SSI Operations
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
Sign-Magnitude
ITU-T (G.711)
FORMAT=1
FORMAT=0
PCM Code
µ/A-LAW
µ-LAW
A-LAW
LAW = 0 or 1
1111 1111
LAW = 0
1000 0000
1111 1111
0111 1111
0000 0000
LAW =1
+ Full Scale
+ Zero
1010 1010
1101 0101
0101 0101
0010 1010
1000 0000
0000 0000
0111 1111
- Zero
- Full Scale
Table 4 - Companded PCM
2.4 Linear PCM
The 16-bit 2’s complement PCM linear coding permits a dynamic range beyond that which is specified in ITU-T
G.711 for companded PCM. The echo-cancellation algorithm will accept 16-bits 2’s complement linear code which
gives a maximum signal level of +15 dBm0.
2.5 Bit Clock (BCLK/C4i)
The BCLK/C4i pin is used to clock the PCM data for GCI and ST-BUS (C4i) interfaces, as well as for the SSI
(BCLK) interface.
In SSI operation, the bit rate is determined by the BCLK frequency. This input must contain either eight or sixteen
clock cycles within the valid enable strobe window. BCLK may be any rate between 128 KHz to 4.096 MHz and can
be discontinuous outside of the enable strobe windows defined by ENA1, ENA2 pins. Incoming PCM data (Rin, Sin)
are sampled on the falling edge of BCLK while outgoing PCM data (Sout, Rout) are clocked out on the rising edge
of BCLK. See Figure 13.
In ST-BUS and GCI operation, connect the system C4 (4.096 MHz) clock to the C4i pin.
2.6 Master Clock (MCLK)
A nominal 20 MHz, continuously-running master clock (MCLK) is required. MCLK may be asynchronous with the
8 KHz frame.
3.0 Microport
The serial microport provides access to all ZL38001 internal read and write registers, plus write-only access to the
bootloadable program RAM (see next section for bootload description.) This microport is compatible with Intel
MCS-51 (mode 0), Motorola SPI (CPOL=0, CPHA=0) and National Semiconductor Microwire specifications. The
microport consists of a transmit/receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (CS) and a
synchronous data clock pin (SCLK).
The ZL38001 automatically adjusts its internal timing and pin configuration to conform to Intel or Motorola/National
requirements. The microport dynamically senses the state of the SCLK pin each time CS pin becomes active (i.e.,
high to low transition). If SCLK pin is high during CS activation, then Intel mode 0 timing is assumed. In this case
DATA1 pin is defined as a bi-directional (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK
is low during CS activation, then Motorola/National timing is assumed and DATA1 is defined as the data transmit pin
while DATA2 becomes the data receive pin. The ZL38001 supports Motorola half-duplex processor mode (CPOL=0
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
and CPHA=0). This means that during a write to the ZL38001, by the Motorola processor, output data from the
DATA1 pin must be ignored. This also means that input data on the DATA2 pin is ignored by the ZL38001 during a
valid read by the Motorola processor.
All data transfers through the microport are two bytes long. This requires the transmission of a Command/Address
byte followed by the data byte to be written to or read from the addressed register. CS must remain low for the
duration of this two-byte transfer. As shown in Figures 8 and 9, the falling edge of CS indicates to the ZL38001 that
a microport transfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS are always used
to receive the Command/Address byte from the microcontroller. The Command/Address byte contains information
detailing whether the second byte transfer will be a read or a write operation and at what address. The next 8 clock
cycles are used to transfer the data byte between the ZL38001 and the microcontroller. At the end of the two-byte
transfer, CS is brought high again to terminate the session. The rising edge of CS will tri-state the DATA1 pin. The
DATA1 pin will remain tri-stated as long as CS is high.
Intel processors utilize Least Significant Bit (LSB) first transmission while Motorola/National processors use Most
Significant Bit (MSB) first transmission. The ZL38001 microport automatically accommodates these two schemes
for normal data bytes. However, to ensure timely decoding of the R/W and address information, the
Command/Address byte is defined differently for Intel and Motorola/National operations. Refer to the relative timing
diagrams of Figure 8 and Figure 9. Receive data bits are sampled on the rising edge of SCLK while transmit data is
clocked out on the falling edge of SCLK. Detailed microport timing is shown in Figure 14 and Figure 15.
3.1 Bootload Process and Execution from RAM
A bootloadable program RAM (BRAM) is available on the ZL38001 to support factory-issued software upgrades to
the built-in algorithm. To make use of this bootload feature, users must include 4096 X 8 bits of memory in their
microcontroller system (i.e., external to the ZL38001), from which the ZL38001 can be bootloaded. Registers and
program data are loaded into the ZL38001 in the same fashion via the serial microport. Both employ the same
command / address / data byte specification described in the previous section on serial microport. Either intel or
motorola mode may be transparently used for bootloading. There are also two registers relevant to bootloading
(BRC=control and SIG=signature, see Register Summary). The effect of these register values on device operation
is summarized in Table 5.
Bootload mode is entered and exited by writing to the bootload bit in the Bootload RAM Control (BRC) register at
address 3fh (see Register Summary). During bootload mode, any serial microport "write" (R/W command bit =0) to
an address other than that of the BRC register will contribute to filling the program BRAM. Call these transactions
"BRAM-fill" writes. Although a command/address byte must still precede each data byte (as described for the serial
microport), the values of the address fields for these "BRAM-fill" writes are ignored (except for the value 3fh, which
designates the BRC register.) Instead, addresses are internally generated by the ZL38001 for each "BRAM-fill"
write. Address generation for "BRAM-fill" writes resumes where it left off following any read transaction while
bootload mode is enabled. The first 4096 such "BRAM-fill" writes while bootload is enabled will load the memory,
but further ones after that are ignored. Following the write of the first 4096 bytes, the program BRAM will be filled.
Before bootload mode is disabled, it is recommended that users then read back the value from the signature
register (SIG) and compare it to the one supplied by the factory along with the code. Equality verifies that the
correct data has been loaded. The signature calculation uses an 8-bit MISR which only incorporates input from
"BRAM-fill" writes. Resetting the bootload bit (C2) in the BRC register to 0 (see Register Summary) exits bootload
mode, resetting the signature (SIG) register and internal address generator for the next bootload. A hardware reset
(RESET=0) similarly returns the ZL38001 to the ready state for the start of a bootload.
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ZL38001
Data Sheet
FUNCTIONAL DESCRIPTION FOR USING THE BOOTABLE RAM
BOOTLOAD MODE - Microport Access is to bootload RAM (BRAM)
R/W
W
Address
Data
3fh
Writes "data" to BRC reg.
(= 1 1 1 1 1 1 b)
- Bootload frozen; BRAM contents are NOT affected.
BRC Register
Bits
W
R
other than 3fh
1 x x x x x b
Writes "data" to next byte in BRAM (bootloading.)
C3C2C1C0
Reads back "data" = BRC reg value.
- Bootload frozen; BRAM contents are NOT affected.
X 1 0 0
R
0 x x x x x b
Reads back "data" = SIG reg value.
- Bootload frozen; BRAM contents are NOT affected.
NON-BOOTLOAD MODE - Microport Access is to device registers (DREGs)
BRC Register
Bits
R/W
W
Address
Data
any
Writes "data" to corresponding DREG.
C3C2C1C0
(= a5 a4 a3 a2 a1 a0 b)
R
any
Reads back "data" = corresponding DREG value.
X 0 0 0
(= a5 a4 a3 a2 a1 a0 b)
PROGRAM EXECUTION MODES
C3C2C1C0
0 0 0 0
Execute program in ROM, bootload mode disabled.
- BRAM address counter reset to initial (ready) state.
- SIG reg reseeded to initial (ready) state
C3C2C1C0
0 1 0 0
Execute program in ROM, while bootloading the RAM.
- BRAM address counter increments on microport writes (except to 3fh)
- SIG reg recalculates signature on microport writes (except to 3fh)
C3C2C1C0
1 0 0 0
Execute program in RAM, bootload mode disabled.
- BRAM address counter reset to initial (ready) state.
- SIG reg reseeded to initial (ready) state
C3C2C1C0
1 1 0 0
- NOT RECOMMENDED -
(Execute program in RAM, while bootloading the RAM)
Table 5 - Bootload RAM Control (BRC) Register States
Note: bits C1 C0 are reserved, and must be set to zero.
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ZL38001
Data Sheet
Once the program has been loaded, to begin execution from RAM, bootload mode must be disabled (BOOT bit,
C2=0) and execution from RAM enabled (RAM_ROMb bit, C3=1) by setting the appropriate bits in the BRC register.
During the bootload process, however, ROM program execution (RAM_ROMb bit, C3=0) should be selected. See
Table 5 for the effect of the BRC register settings on Microport accesses and on program execution.
Following program loading and enabling of execution from RAM, it is recommended that users set the software
reset bit in the Main Control (MC) register, to ensure that the device updates the default register values to those of
the new program in RAM. Note: it is important to use a software reset rather than a hardware (RESET=0) reset, as
the latter will return the device to its default settings (which includes execution from program ROM instead of RAM.)
To verify which code revision is currently running, users can access the Firmware Revision Code (FRC) register
(see Register Summary). This register reflects the identity code (revision number) of the last program to run register
initialization (which follows a software or hardware reset.)
ƒ
COMMAND/ADDRESS
DATA INPUT/OUTPUT
A0 A1 A2 A3 A4 A5
X
D0 D1 D2 D3 D4 D5 D6 D7
R/W
DATA 1
¿
¡
SCLK
CS
Ð
¬
¿
¡
This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to ZL38001.
The ZL38001: latches receive data on the rising edge of SCLK
outputs transmit data on the falling edge of SCLK
¬
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
Ð
ƒ
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
6 bits - Addressing Data
1 bit - Unused
Figure 8 - Serial Microport Timing for Intel Mode 0
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
COMMAND/ADDRESS ƒ
DATA INPUT
DATA 2
Receive
R/W A5 A4 A3 A2 A1 A0
X
D7 D6 D5 D4 D3 D2 D1 D0
DATA OUTPUT
DATA 1
Transmit
D7 D6 D5 D4 D3 D2 D1 D0
High Impedance
¿
¡
SCLK
CS
Ð
¬
¿
¡
This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to ZL38001.
The ZL38001: latches receive data on the rising edge of SCLK
outputs transmit data on the falling edge of SCLK
¬
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
Ð
ƒ
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
6 bits - Addressing Data
1 bit - Unused
Figure 9 - Serial Microport Timing for Motorola Mode 00 or National Microwire
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ZL38001
Data Sheet
Absolute Maximum Ratings*
Parameter
Symbol
DD-VSS
Vi
Min.
Max.
Units
1
2
3
4
5
6
Supply Voltage
Input Voltage
V
-0.5
5.0
5.5
V
V
VSS-0.3
VSS-0.3
Output Voltage Swing
Vo
5.5
V
Continuous Current on any digital pin
Storage Temperature
Ii/o
±20
mA
°C
mW
TST
PD
-65
150
Package Power Dissipation
90 (typ)
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Supply Voltage
Sym.
Min.
Typ. Max. Units
Test Conditions
1
2
3
4
VDD
2.7
1.4
VSS
-40
3.3
3.6
VDD
0.4
V
V
Input High Voltage
Input Low Voltage
V
Operating Temperature
TA
+85
°C
Echo Return Limits
Characteristics
Min.
Typ.
Max. Units
Test Conditions
1
2
Acoustic Echo Return
Line Echo Return
0
0
dB
dB
Measured from Rout -> Sin
Measured from Sout -> Rin
DC Electrical Characteristics*- Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Conditions/Notes
RESET = 0
Standby Supply Current:
Operating Supply Current:
Input HIGH voltage
ICC
IDD
VIH
VIL
3
70
µA
mA
V
1
20
RESET = 1, clocks active
2
3
4
5
6
7
8
9
0.7VDD
0.8VDD
Input LOW voltage
0.3VDD
10
V
Input leakage current
High level output voltage
Low level output voltage
High impedance leakage
Output capacitance
IIH/IIL
VOH
VOL
IOZ
0.1
µA
V
VIN=VSS to VDD
IOH=2.5 mA
0.4VDD
10
V
IOL=5.0 mA
1
10
8
µA
pF
pF
VIN=VSS to VDD
Co
Input capacitance
Ci
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*DC Electrical Characteristics are over recommended temperature and supply voltage.
23
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
AC Electrical Characteristics† - Serial Data Interfaces - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
MCLK Frequency
Sym.
Min.
Typ.
Max.
Units
Test Notes
1
2
fCLK
19.15
90
20.5
MHz
ns
BCLK/C4i Clock High
BCLK/C4i Clock Low
BCLK/C4i Period
tBCH,
tC4H
3
tBLL,
tC4L
90
ns
4
5
tBCP
tSD
240
80
7900
ns
ns
SSI Enable Strobe to Data Delay (first
bit)
CL = 150 pF
CL = 150 pF
CL = 150 pF
6
SSI Data Output Delay (excluding
first bit)
tDD
80
ns
7
8
SSI Output Active to High Impedance
SSI Enable Strobe Signal Setup
tAHZ
tSSS
80
10
ns
ns
tBCP
-15
9
SSI Enable Strobe Signal Hold
tSSH
15
tBCP
-10
ns
10 SSI Data Input Setup
11 SSI Data Input Hold
tDIS
tDIH
10
15
20
20
80
80
ns
ns
ns
ns
ns
ns
12 ST-BUS/GCI F0i Setup
13 ST-BUS/GCI F0i Hold
14 ST-BUS/GCI Data Output delay
tF0iS
tF0iH
tDSD
tASHZ
150
150
CL = 150 pF
CL = 150 pF
15 ST-BUS/GCI Output Active to High
Impedance
16 ST-BUS/GCI Data Input Hold time
tDSH
tDSS
20
20
ns
ns
17 ST-BUS/GCI Data Input Setup time
† Timing is over recommended temperature and power supply voltages.
24
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
AC Electrical Characteristics† - Microport Timing
Characteristics
Input Data Setup
Sym.
Min.
Typ.
Max.
Units
Test Notes
1
2
3
4
5
6
7
8
9
tIDS
tIDH
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input Data Hold
30
Output Data Delay
Serial Clock Period
SCLK Pulse Width High
SCLK Pulse Width Low
CS Setup-Intel
tODD
tSCP
tSCH
tSCL
100
500
250
250
200
100
100
100
CL = 150 pF
tCSSI
tCSSM
tCSH
tOHZ
CS Setup-Motorola
CS Hold
10 CS to Output High Impedance
CL = 150 pF
† Timing is over recommended temperature range and recommended power supply voltages.
Characteristic
CMOS reference level
Symbol
CMOS Level
Units
VCT
VH
0.5*VDD
0.9*VDD
0.1*VDD
0.7*VDD
0.3*VDD
V
V
V
V
V
Input HIGH level
Input LOW level
VL
Rise/Fall HIGH measurement point
Rise/Fall LOW measurement point
VHM
VLM
Table 6 - Reference Level Definition for Timing Measurements
T=1/fCLK
VH
VL
MCLK (I)
V
CT
Notes: O. CMOS output
I. CMOS input (5 V tolerant)
(see Table 8 for symbol definitions)
Figure 10 - Master Clock - MCLK
25
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
Bit 7
Bit 6
Sout/Rout (O)
V
CT
tASHZ
tDSD
tC4H
VH
VL
C4i (I)
V
CT
tF0iS tF0iH
tC4L
VH
VL
F0i (I)
V
CT
tDSS tDSH
start of frame
VH
VL
Rin/Sin (I)
V
CT
Bit 6
Bit 7
Figure 11 - GCI Data Port Timing
Bit 7
Bit 6
Sout/Rout (O)
V
CT
tDSD
tC4H
tASHZ
VH
VL
C4i (I)
V
CT
tF0iS tF0iH
tC4L
VH
VL
F0i (I)
V
CT
start of frame
tDSS tDSH
VH
VL
Rin/Sin (I)
V
CT
Bit 6
Bit 7
Figure 12 - ST-BUS Data Port Timing
26
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
Bit 7
Bit 6
Bit 5
Sout/Rout (O)
CT
V
tAHZ
tSD
tDD
tBCH
VH
VL
BCLK (I)
V
CT
tSSS
tBCP
tBCL
tSSH
VH
VL
ENA1 (I)
or
V
V
CT
CT
ENA2 (I)
tDIS
tDIH
start of frame
VH
VL
Rin/Sin (1)
Bit 7
Bit 6
Bit 5
Notes: O. CMOS output
I. CMOS input (5 V tolerant)
(see Table 8 for symbol definitions)
Figure 13 - SSI Data Port Timing
DATA OUTPUT
DATA INPUT
DATA1 (I,O)
V
V
V
CT
CT
CT
tIDS tIDH
tSCH
tODD
tOHZ
VH
SCLK (I)
VL
tCSSI
tSCL
tSCP
tCSH
VH
(
I)
CS
VL
Notes: O. CMOS output
I. CMOS input (5 V tolerant)
(see Table 8 for symbol definitions)
Figure 14 - INTEL Serial Microport Timing
27
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
VH
VL
DATA2 (I)
(Input)
V
CT
CT
CT
CT
tIDS tIDH
tSCH
tSCP
VH
VL
SCLK (I)
V
V
V
tCSSM
tSCL
tCSH
VH
VL
CS (I)
tODD
tOHZ
DATA1 (O)
(Output)
Notes: O. CMOS output
I. CMOS input (5 V tolerant)
(see Table 8 for symbol definitions)
Figure 15 - Motorola Serial Microport Timing
28
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
4.0 Register Summary
External Read/Write Address: 00H
Reset Value: 00H
7
6
5
4
3
2
1
0
LIMIT
MUTE_R
MUTE_S
BYPASS
NB-
AGC-
AH-
RESET
Bit
Name
Description
7
LIMIT
When high, the 2-bit shift mode is enabled in conjunction with bit 7 of LEC
register and when low 2-bit shift mode is disabled. Default limit for Rin and
Sin is 3.14 dBm0.
6
5
4
3
MUTE_R
MUTE_S
BYPASS
NB-
When high, the Rin path is muted to quite code (after the NLP) and when low
the Rin path is not muted.
When high, the Sin path is muted to quite code (after the NLP) and when low
the Sin path is not muted.
When high, the Send and Receive paths are transparently by-passed from
input to output and when low the Send and Receive paths are not bypassed.
When high, Narrowband signal detectors in Rin and Sin paths are disabled
and when low the signal detectors are enabled.
2
1
AGC-
AH-
When high, AGC is disabled and when low AGC is enabled.
When high, the Howling detector is disabled and when low the Howling
detector is enabled.
0
RESET
When high, the power initialization routine is executed presetting all registers
to default values.
This bit automatically clears itself to ’0’ when reset is complete.
Register Table 1 - Main Control Register (MC)
External Read/Write Address:21H
Reset Value: 00H
7
6
5
4
3
2
1
0
P-
ASC-
NLP-
INJ-
HPF-
HCLR
ADAPT-
ECBY
Bit
Name
Description
7
P-
When high, the Exponential weighting function for the adaptive filter is
disabled and when low the weighting function is enabled
6
5
ASC-
NLP-
When high, the Internal Adaptation speed control is disabled and when low
the Adaptation speed is enabled.
When high, the Non Linear Processor is disabled in the Sin/Sout path and
when low the NLP is enabled.
Register Table 2 - Acoustic Echo Canceller Control Register (AEC)
29
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read/Write Address:21H
Reset Value: 00H
7
6
5
4
3
2
1
0
P-
ASC-
NLP-
INJ-
HPF-
HCLR
ADAPT-
ECBY
Bit
Name
Description
4
INJ-
When high, the Noise filtering process is disabled in the NLP and when low
the Noise filtering process is enabled.
3
2
1
0
HPF-
HCLR
When high, Offset nulling filter is bypassed in the Sin/Sout path and when low
the Offset nulling filter in not bypassed.
When high, Adaptive filter coefficients are cleared and when low the filter
coefficients are not cleared
ADAPT-
ECBY
When high, the Echo canceller adaptation is disabled and when low the
adaptation is enabled.
When high, the Echo estimate from the filter is not subtracted from the input
(Sin), when low the estimate is subtracted.
Register Table 2 - Acoustic Echo Canceller Control Register (AEC) (continued)
External Read/Write Address: 01H
Reset Value: 00H
7
6
5
4
3
2
1
0
SHFT
ASC-
NLP-
INJ-
HPF-
HCLR
ADAPT-
ECBY
Bit
Name
Description
7
SHFT
When high the 16-bit linear mode, inputs Sin, Rin, are shift right by 2 and
outputs Sout, Rout are shift left by 2. This bit is ignored when 16-bit linear
mode is not selected in both ports. This bit is also ignored if bit 7 of MC
register is set to zero.
6
5
4
3
2
ASC-
NLP-
INJ-
When high, the Internal Adaptation speed control is disabled and when low
the Adaptation speed is enabled.
When high, the Non Linear Processor is disabled in the Rin/Rout path and
when low the NLP is enabled.
When high, the Noise filtering process is disabled in the NLP and when low
the Noise filtering process is enabled.
HPF-
HCLR
When high, Offset nulling filter is bypassed in the Rin/Rout path and when low
the Offset nulling filter in not bypassed.
When high, Adaptive filter coefficients are cleared and when low the filter
coefficients are not cleared.
Register Table 3 - Line Echo Canceller Control Register (LEC)
30
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read/Write Address: 01H
Reset Value: 00H
7
6
5
4
3
2
1
0
SHFT
ASC-
NLP-
INJ-
HPF-
HCLR
ADAPT-
ECBY
Bit
Name
Description
1
ADAPT-
When high, the Echo canceller adaptation is disabled and when low the
adaptation is enabled.
0
ECBY
When high, the Echo estimate from the filter is not substracted from the input
(Rin), when low the estimate is substracted.
Register Table 3 - Line Echo Canceller Control Register (LEC) (continued)
External Read Address: 22H
Reset Value: 00H
7
6
5
4
3
2
1
0
-
ACMUND
HWLNG
-
NLPDC
DT
NB
NBS
Bit
Name
Description
7
6
5
-
RESERVED.
ACMUND
HWLNG
When low, No active signal in the Rin/Rout path.
When high, Howling is occurring in the loop and when low, no Howling is
detected.
4
3
2
-
RESERVED.
NLPDC
DT
When high, the NLP is activated and when low the NLP is not activated.
When high the Double Talk is detected and when low, the Double talk is not
detected.
1
0
NB
LOGICAL OR of the status bit NBS + NBR from LSR Register.
NBS
When high, the Narrowband signal has been detected in the Sin/Sout path
and when low, the Narrowband signal has not been detected in the Sin/Sout
path.
Register Table 4 - Acoustic Echo Canceller Status Register (ASR) (* Do not write to this register)
31
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 02H
Reset Value: 00H
7
6
5
4
3
2
1
0
Bit
Name
Description
7
6
5
4
3
2
1
-
RESERVED.
-
-
-
NLPC
DT
NB
When high, NLP is activated and when low NLP is not activated.
When high, double-talk is detected and when low double-talk is not detected.
This bit indicates a LOGICAL-OR of Status bits NBR + NBS (from ASR
Register).
0
NBR
When high, a narrowband signal has been detected in the Receive (Rin) path.
When low no narrowband signal is not detected in the Rin path.
Register Table 5 - Line Echo Canceller Status Register (LSR) (* Do not write to this register)
32
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read/Write Address:20H
Reset Value: 6DH
7
6
5
4
3
2
1
0
-
-
-
G4
G3
G2
G1
G0
Bit
Name
Description
7
6
Reserved
Reserved
Reserved
G4-0
Must keep as Logic 0.
Must keep as Logic 1.
Must keep as Logic 1.
5
4-0
User Gain Control on the Rin/Rout path (Tolerance of gains: +/- 0.15 dB).
The hexadecimal number represents G3 to G0 value in the table below.
Register Value
0h
Gain
-24 dB
Register Value
10h
Gain
+24 dB
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
-21 dB
-18 dB
-15 dB
-12 dB
-9 dB
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
+27 dB
+30 dB
+33 dB
+36 dB
+39 dB
-6 dB
+42 dB
-3 dB
+45 dB
0 dB
+48 dB
+3 dB
+6 dB
+9 dB
+12 dB
+15 dB
+18 dB
+21 dB
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Register Table 6 - Receive Gain Control Register
33
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read/Write Address: 32H
Reset Value: 25H
7
6
5
4
3
2
1
0
HG2
HG1
HG0
DTGain
-
-
-
-
Bit
Name
Description
7
6
5
4
-
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
RESERVED. Must keep as 1.
-
-
DTRGain
This bit controls the gain level at Rout during double talk. When this bit is high
12 dB of attenuation is injected into the Rout path during double talk. When
this bit is low the gain pad is disabled.
3
2
1
0
-
-
-
-
RESERVED. Must keep as 0.
RESERVED. Must keep as 1.
RESERVED. Must keep as 0.
RESERVED. Must keep as 1.
Register Table 7 - Double Talk Gain Control Register 1 (DTGCR1)
External Read/Write Address: 12H
Reset Value: 00H
7
6
5
4
3
2
1
0
-
-
-
DTSGain
-
-
Bit
Name
Description
7
6
5
4
-
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
-
-
DTSGain
This bit controls the gain level at Sout during double talk. When this bit is high
12 dB of attenuation is injected into the Sout path during double talk. When
this bit is low the gain pad is disabled.
3
2
1
0
-
-
-
-
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
Register Table 8 - Double Talk Gain Control Register 2 (DTGCR2)
34
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read/Write Address: 31H
Reset Value: 21H
7
6
5
4
3
2
1
0
DTDT2
DTDT1
DTDT0
-
-
-
-
-
Bit
Name
Description
7
6
5
DTDT2
DTDT1
DTDT0
DTDT2, DTDT1, DTDT0 Value
DTDT
DTDT2, DTDT1, DTDT0 Value
DTDT
000
001
010
011
-12 dB
-6 dB
0 dB
100
101
110
111
+12 dB
+18 dB
+24 dB
+30 dB
+6 dB
4
3
2
1
0
-
-
-
-
-
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
RESERVED. Must keep as 0.
RESERVED. Must keep as 1.
Register Table 9 - Double Talk detection Threshold Register (DTDT)
External Read Address: 16H
Reset Value: 00H
7
6
5
4
3
2
1
0
RIPD7
RIPD6
RIPD5
RIPD4
RIPD3
RIPD2
RIPD1
RIPD0
Bit
Name
Description
7
6
5
4
3
2
1
0
RIPD7
RIPD6
RIPD5
RIPD4
RIPD3
RIPD2
RIPD1
RIPD0
These peak detector registers allow the user to monitor the receive in signal
(Rin) peak level at reference point R1 (see Figure 1). The information is in 16-
bit 2’s complement linear coded format presented in two 8-bit registers. The
high byte is in Register 2 and the low byte is in Register 1.
Register Table 10 - Receive (Rin) Peak Detect Register 1 (RIPD1)
35
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 17H
Reset Value: 00H
7
6
5
4
3
2
1
0
RIPD15
RIPD14
RIPD13
RIPD12
RIPD11
RIPD10
RIPD9
RIPD8
Bit
Name
Description
7
6
5
4
3
2
1
0
RIPD15
RIPD14
RIPD13
RIPD12
RIPD11
RIPD10
RIPD9
These peak detector registers allow the user to monitor the receive in signal
(Rin) peak level at reference point R1 (see Figure 1). The information is in 16-
bit 2’s complement linear coded format presented in two 8-bit registers. The
high byte is in Register 2 and the low byte is in Register 1.
RIPD8
Register Table 11 - Receive (Rin) Peak Detect Register 2 (RIPD2)
External Read Address: 18H
Reset Value: 00H
7
6
5
4
3
2
1
0
REPD7
REPD6
REPD5
REPD4
REPD3
REPD2
REPD1
REPD0
Bit
Name
Description
7
6
5
4
3
2
1
0
REPD7
REPD6
REPD5
REPD4
REPD3
REPD2
REPD1
REPD0
These peak detector registers allow the user to monitor the error signal peak
level at reference point R2 (see Figure 1). The information is in 16-bit 2’s
complement linear coded format presented in two 8-bit registers. The high
byte is in Register 2 and the low byte is in Register 1.
Register Table 12 - Receive (Rin) ERROR Peak Detect Register 1 (REPD1)
36
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 19H
Reset Value: 00H
7
6
5
4
3
2
1
0
REPD15
REPD14
REPD13
REPD12
REPD11
REPD10
REPD9
REPD8
Bit
Name
Description
7
6
5
4
3
2
1
0
REPD15
REPD14
REPD13
REPD12
REPD11
REPD10
REPD9
These peak detector registers allow the user to monitor the error signal peak
level at reference point R2 (see Figure 1). The information is in 16-bit 2’s
complement linear coded format presented in two 8-bit registers. The high
byte is in Register 2 and the low byte is in Register 1.
REPD8
Register Table 13 - Receive (Rin) ERROR Peak Detect Register 2 (REPD2)
External Read Address: 3AH
Reset Value: 00H
7
6
5
4
3
2
1
0
ROPD7
ROPD6
ROPD5
ROPD4
ROPD3
ROPD2
ROPD1
ROPD0
Bit
Name
Description
7
6
5
4
3
2
1
0
ROPD7
ROPD6
ROPD5
ROPD4
ROPD3
ROPD2
ROPD1
ROPD0
These peak detector registers allow the user to monitor the receive out signal
(Rout) peak level at reference point R3 (see Figure 1). The information is in
16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
Register Table 14 - Receive (Rout) Peak Detect Register 1 (ROPD1)
37
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 3BH
Reset Value: 00H
7
6
5
4
3
2
1
0
ROPD15
ROPD14
ROPD13
ROPD12
ROPD11
ROPD10
ROPD9
ROPD8
Bit
Name
Description
7
6
5
4
3
2
1
0
ROPD15
ROPD14
ROPD13
ROPD12
ROPD11
ROPD10
ROPD9
ROPD8
These peak detector registers allow the user to monitor the receive out signal
(Rout) peak level at reference point R3 (see Figure 1). The information is in
16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
Register Table 15 - Receive (Rout) Peak Detect Register 2 (ROPD2)
External Read Address: 36H
Reset Value: 00H
7
6
5
4
3
2
1
0
SIPD7
SIPD6
SIPD5
SIPD4
SIPD3
SIPD2
SIPD1
SIPD0
Bit
Name
Description
7
6
5
4
3
2
1
0
SIPD7
SIPD6
SIPD5
SIPD4
SIPD3
SIPD2
SIPD1
SIPD0
These peak detector registers allow the user to monitor the receive in signal
(Sin) peak level at reference point S1 (see Figure 1). The information is in 16-
bit 2’s complement linear coded format presented in two 8-bit registers. The
high byte is in Register 2 and the low byte is in Register 1.
Register Table 16 - Send (Sin) Peak Detect Register 1 (SIPD1)
38
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 37H
Reset Value: 00H
7
6
5
4
3
2
1
0
SIPD15
SIPD14
SIPD13
SIPD12
SIPD11
SIPD10
SIPD9
SIPD8
Bit
Name
Description
7
6
5
4
3
2
1
0
SIPD15
SIPD14
SIPD113
SIPD12
SIPD11
SIPD10
SIPD9
These peak detector registers allow the user to monitor the receive in signal
(Sin) peak level at reference point S1 (see Figure 1). The information is in 16-
bit 2’s complement linear coded format presented in two 8-bit registers. The
high byte is in Register 2 and the low byte is in Register 1.
SIPD8
Register Table 17 - Send (Sin) Peak Detect Register 2 (SIPD2)
External Read Address: 38H
Reset Value: 00H
7
6
5
4
3
2
1
0
SEPD7
SEPD6
SEPD5
SEPD4
SEPD3
SEPD2
SEPD1
SEPD0
Bit
Name
Description
7
6
5
4
3
2
1
0
SEPD7
SEPD6
SEPD5
SEPD4
SEPD3
SEPD2
SEPD1
SEPD0
These peak detector registers allow the user to monitor the error signal peak
level in the send path at reference point S2 (see Figure 1). The information is
in 16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
Register Table 18 - Send ERROR Peak Detect Register 1 (SEPD1)
39
Zarlink Semiconductor Inc.
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Data Sheet
External Read Address: 39H
Reset Value: 00H
7
6
5
4
3
2
1
0
SEPD15
SEPD14
SEPD13
SEPD12
SEPD11
SEPD10
SEPD9
SEPD8
Bit
Name
Description
7
6
5
4
3
2
1
0
SEPD15
SEPD14
SEPD13
SEPD12
SEPD11
SEPD10
SEPD9
These peak detector registers allow the user to monitor the error signal peak
level in the send path at reference point S2 (see Figure 1). The information is
in 16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
SEPD8
Register Table 19 - Send ERROR Peak Detect Register 2 (SEPD2)
External Read Address: 1AH
Reset Value: 00H
7
6
5
4
3
2
1
0
SOPD7
SOPD6
SOPD5
SOPD4
SOPD3
SOPD2
SOPD1
SOPD0
Bit
Name
Description
7
6
5
4
3
2
1
0
SOPD7
SOPD6
SOPD5
SOPD4
SOPD3
SOPD2
SOPD1
SOPD0
These peak detector registers allow the user to monitor the Send out signal
(Sout) peak level at reference point S3 (see Figure 1). The information is in
16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
Register Table 20 - Send (Sout) Peak Detect Register 1 (SOPD1)
40
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 1BH
Reset Value: 00H
7
6
5
4
3
2
1
0
SOPD15
SOPD14
SOPD13
SOPD12
SOPD11
SOPD10
SOPD9
SOPD8
Bit
Name
Description
7
6
5
4
3
2
1
0
SOPD15
SOPD14
SOPD13
SOPD12
SOPD11
SOPD10
SOPD9
SOPD8
These peak detector registers allow the user to monitor the Send out signal
(Sout) peak level at reference point S3 (see Figure 1). The information is in
16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
Register Table 21 - Send (Sout) Peak Detect Register 2 (SOPD2)
External Read Address: 24H
Reset Value: 80H
7
6
5
4
3
2
1
0
L0
-
-
-
-
-
-
-
Bit
Name
Description
7
L0
This bit is used in conjunction with Rout Limiter Register 2. (See description
below.)
6
5
4
3
2
1
0
-
-
-
-
-
-
-
RESERVED
Register Table 22 - Rout Limiter Register 1 (RL1)
41
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 25H
Reset Value: 3EH
7
6
5
4
3
2
1
0
L8
L7
L6
L5
L4
L3
L2
L1
Bit
Name
Description
7
6
5
4
3
2
1
0
L8
L7
L6
L5
L4
L3
L2
L1
In conjunction with bit 7 (L0) of the above (RL1) register, this register (RL2)
allows the user to program the output Limiter threshold value in the Rout path.
Default value is (07D)h which is equal to 3.14 dBmo
Maximum value is (1FF)h = 15 dBmo
Minimum value is (001)h = -38 dBmo
Register Table 23 - Rout Limiter Register 2 (RL2)
External Read Address: 26H
Reset Value: 3DH
7
6
5
4
3
2
1
0
L4
L3
L2
L1
L0
Bit
Name
Description
7
6
5
4
3
2
1
0
L4
L3
L2
L1
L0
-
This register allows the user to program the output Limiter threshold value in
the Rout path.
Default value is (1D)h which is equal to 3.14 dBmo
Maximum value is (1F)h
RESERVED. Must be keep as 1.
RESERVED. Must be keep as 0.
-
-
RESERVED. Must be keep as 1.
Register Table 24 - Sout Limiter Register (SL)
42
Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 03H
Reset Value: 00H
7
6
5
4
3
2
1
0
FRC2
FRC1
FRC0
-
-
-
-
-
Bit
Name
Description
7
6
5
4
3
2
1
0
FRC2
Revision code of the firmware program currently being run (default=rom=00).
FRC1
FRC0
-
-
-
-
-
RESERVED
Register Table 25 - Firmware Revision Code Register (FRC)
External Read Address: 3FH
Reset Value: 00H
7
6
5
4
3
2
1
0
-
-
-
-
C3
C2
C1
C0
Bit
Name
Description
7
6
5
4
3
-
-
RESERVED
-
-
C3
RAM_ROMb bit. When high, device executes from RAM. When low, device
executes from ROM.
2
C2
BOOT bit. When high, puts device in bootload mode. When low, bootload is
disabled.
1
0
C1
C0
RESERVED. Must be set to zero.
RESERVED. Must be set to zero.
Register Table 26 - Bootload RAM Control Register (BRC)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 07H
Reset Value: 10H
7
6
5
4
3
2
1
0
SIG7
SIG6
SIG5
SIG4
SIG3
SIG2
SIG1
SIG0
Bit
Name
Description
7
6
5
4
3
2
1
0
SIG7
SIG6
SIG5
SIG4
SIG3
SIG2
SIG1
SIG0
This register provides the signature of the bootloaded data to verify error-free
delivery into the device.
Note: this register is only accessible if BOOT bit is high (bootload mode
enabled) in the above BRC register. While bootload is disabled, the register
value is held constant at its reset seed value of FFh.
Register Table 27 - Bootload RAM Signature Register (SIG)
44
Zarlink Semiconductor Inc.
Package Code
c Zarlink Semiconductor 2003 All rights reserved.
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DATE
APPRD.
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