ZN427E8 [ZARLINK]
MICROPROCESSOR COMPATIBLE 8-BIT SUCCESSIVE APPROXIMATION A-D CONVERTER; 微处理器兼容的8位逐次逼近模数转换器
| 型号： | ZN427E8 |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | MICROPROCESSOR COMPATIBLE 8-BIT SUCCESSIVE APPROXIMATION A-D CONVERTER |
| 文件： | 总17页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
DS3006 - 2.1
ZN427E8 / ZN427J8
MICROPROCESSOR COMPATIBLE
8-BIT SUCCESSIVE APPROXIMATION A-D CONVERTER
TheZN427isan8-bitsuccessiveapproximationconverter
with three-state outputs to permit easy interfacing to a
common data bus. The IC contains a voltage switching DAC,
a fast comparator, successive approximation logic and a
2.56V precision bandgap reference, the use of which is pin
optional to retain flexibility. An external fixed or varying
reference may therefore be substituted, thus allowing
ratiometic operation
BUSY (END OF CONVERSION)
RD (OUTPUT ENABLE)
CLOCK
1
2
3
4
18 BIT 8 (LSB)
17 BIT 7
16 BIT 6
15 BIT 5
WR (START CONVERSION)
Only passive external components are required for
operation of the converter.
R
EXT
IN
REF IN
REF OUT
5
6
7
14 BIT 4
13 BIT 3
12 BIT 2
V
V
FEATURES
■
Easy Interfacing to Microprocessor, or Operates as a
V
8
9
11 BIT 1 (MSB)
10 +VCC (+5V)
'Stand-Alone' Converter
GROUND
■
■
■
Fast: 10 microseconds Conversion time Guaranteed
No Missing Codes over Operating Temperature Range
ZN427J8 (DC18)
ZN427E8 (DP18)
Data Outputs Three-State TTL Compatible, other
Logic Inputs and Output TTL and CMOS Compatible
Fig.1 Pin connection - top view
■
■
■
■
■
Choice of On-Chip or External Reference Voltage
Ratiometric Operation
ORDERING INFORMATION
Unipolar or Bipolar Input Ranges
Complementary to ZN428 DAC
Operating temperature
Package
Device type
ZN427E8
ZN427J8
0°C to +70°C
DP18
DC18
Commercial or Military Temperature Range
-55°C to +125°C
8
V
OUT
REF
D TO A OUTPUT
R-2R LADDER
+2.5V
REFERENCE
COMPARATOR
-
9
7
GROUND
V IN
REF
ANALOGUE VOLTAGE SWITCHES
6
5
3
V
IN
+
R
EXT
4
1
WR (START CONVERSION)
BUSY (END CONVERSION)
SUCCESSIVE
APPROXIMATION REGISTER
CLOCK
INPUT
2
3-STATE BUFFERS
RD (OUTPUT ENABLE)
10
V
CC
(+5V)
11
MSB
12
13
14
15
16
17
18
LSB
Fig.2 System diagram
ZN427
ABSOLUTE MAXIMUM RATINGS
Supply voltage VCC
+7.0V
Max. voltage, logic and VREF input
Operating temperature range
+VCC
0°C to +70°C (ZN427E8)
-55°C to +125°C (ZN427J8)
-55°C to +125°C
Storage temperature range
ELECTRICAL CHARACTERISTICS (at VCC = 5V, Tamb = 25°C unless otherwise specified).
Min.
Typ.
Max.
Parameter
Units
Conditions
Converter
Resolution
Linearity error
-
-
Bits
LSB
8
-
-
±0.5
Differential non-linearity
Linearity error T.C.
Differential non-linearity T.C.
Full-scale (gain) T.C.
Zero T.C.
±0.5
±3
±6
±2.5
±8
15
LSB
-
-
-
-
-
-
-
-
-
-
ppm/°C
ppm/°C
ppm/°C
µV/°C
mV
External Ref. 2.5V
Zero transition
00000000
to 00000001
11111110
12
10
2.545
18
16
2.555
DC Package
DP Package
13
2.550
mV
V
F.S. transition
VREF IN = 2.560V
to 11111111
Conversion time
-
-
-
µs
V
V
mA
mW
-
1.5
4.5
-
10
3.0
5.5
40
-
See note 1
External reference voltage
Supply voltage (VCC)
Supply current
25
125
Power consumption
-
Comparator
Input current
1
100
-
-
-
µA
kΩ
µA
V
-
-
-
-
15
-30.0
3.5
VIN = +3V, REXT = 82kΩ
V - = -5V
Input resistance
Tail current, IEXT
Negative supply, V–
Input voltage
25
-3.0
-0.5
See comparator (page x-xx)
V
Internal voltagee reference
Output voltage
Slope resistance
2.475
-
-
2.560
0.5
50
2.625
2
-
V
Ω
RREF = 390Ω, CREF = 4µ7
VREF temperature coefficient
ppm/°C
mA
Reference current
4
-
15
See reference (page x-xx)
Logic (over operating temperature range)
High level input voltage VIH
Low level input voltage VIL
High level input current,
WR and RD inputs IIH
2.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.8
50
15
100
30
-5
-100
1.6
-
0.4
2
-1.5
250
250
-
V
V
µA
µA
µA
µA
µA
µA
mA
V
V
µA
V
ns
ns
ns
ns
ns
kHz
VIN = 5.5V, VCC = max.
VIN = 2.4V, VCC = max.
VIN = 5.5V, VCC = max.
VIN = 2.4V, VCC = max.
VIN = 0.4V, VCC = max.
High level input current,
Clock input IIH
Low level input current IIL
High level output current IOH
Low level output current IOL
High level output voltage VOH
Low level output voltage VOL
Disable output leakage
Input clamp diode voltage
Read input to data output
Enable/disable delay time tRD
Start pulse width tWR
-
2.4
-
-
-
-
IOH = max., VCC = min.
IOL = max., VCC = min.
VO = 2.4V
See Fig.9
See Fig.9
-
180
160
-
250
-
500
900
WR to BUSY propagation delay tBD
Clock pulse width
Maximum clock frequency
250
-
-
-
1000
See note 1
Note 1: A 900kHz clock gives a conversion time of 10µs (9 clock periods).
2
ZN427
GENERAL CIRCUIT OPERATION
to 1. This procedure is repeated for all eight bits. On the ninth
negative clock edge BUSY goes high indicating that the
conversion is complete.
The ZN427 utilises the successive approximation technique.
Upon receipt of a negative-going pulse at the WR input the
BUSY output goes low, the MSB is set to 1 and all other bits
aresetto0,whichproducesanoutputvoltageofVREF/2 fromthe
DAC. This is compared to the input voltage VIN; a decision is
made on the next negative clock edge to reset the
During a conversion the RD input will normally be held high to
keep the three-state buffers in their high impedance state.
Data can be read out by taking RD high, thus enabling the
three-state output. Readout is non-destructive. The BUSY
output may be tied to the RD input to automatically enable the
outputs when the data is valid.
VREF
2
VREF
2
MSB to 0 if
> VIN or leave it set to 1 if
< VIN.
Bit 2 is set to 1 on the same clock edge, producing an output
V
VREF
2
V
from the DAC of REF or
4
+
REF depending on the state
4
For reliable operation of the converter the start pulse applied
to the WR input must meet certain timing criteria with respect
to the converter clock. These are detailed in the timing
diagram of Fig.3.
of the MSB. This voltage is compared to VIN and on the next
clock edge a decision is made regarding bit 2, whilst bit 3 is set
Fig.3 Timing diagram
NOTES ON TIMING DIAGRAM
2. The BUSY output goes low during a conversion. When
BUSY goes high at the end of a conversion the output data is
valid. In a microprocessor system the BUSY output can be
used to generate an interrupt request when the conversion is
complete.
1. A conversion sequence is shown for the digital word
01100110. For clarity the three-state outputs are shown as
being enabled during the conversion, but normal practice
would be to disable them until the conversion was complete.
3
ZN427
3. In the timing diagram cross hatching indicates a 'don't
care' condition.
PRACTICAL CLOCK AND SYNCHRONISING
CIRCUITS
4. The start pulse operates as an asynchronous
(independent of clock) reset that sets the MSB output to 1 and
sets all other outputs and the end of conversion flag to 0. This
resetting occurs on the low-going edge of the start pulse and
as long as WR is low the converter is inhibited. Conversion
commences on the first active (negative going) clock edge
after the WR input has gone high again, when the MSB
decision is made. A number of timing constraints thus supply
to the start pulse.
The actual method of generating the clock signal and
synchronising it to the start conversion system in which the
ZN427 is incorporated.
When used with a microprocessor the ZN427 can be treated
as RAM and can be assigned a memory address using an
address decoder. If the µP clock is used to drive the ZN427
and the µP write pulse meets the ZN427 timing criteria with
respect to the µP clock then generating the start pulse is
simply a matter of gating the decoded address with the
microprocessor write pulse. Whilst the conversion is being
performed the microprocesor can perform other instructions
or No operation (NOP). when the conversion is complete the
outputs can be enabled onto the bus by gating the decoded
address with the read pulse. A timing diagram for this
sequence of operation is given in Fig.4.
(a) The minimum duration of the start pulse is 250ns, to allow
reliable resetting of the converter logic circuits.
(b) Thereisnolimittothemaximumdurationofthestartpulse.
(c) To allow the MSB to settle at least 1.5µs must elapse
betweenthenegativegoingedgeofthestartpulseandthefirst
active clock edge that indicates the MSB desicion.
An advantage of using the microprocessor clock is that the
conversion time is known precisely in terms of machine
cycles. the data outputs may therefore be read after a fixed
delay of at least nine clock cycles after the end of the WR
pulse, when the conversion will be complete.
(d) To ensure relaible clocking the positive-going edge of the
start pulse should not occur within 200ns of an active
(negative-going) clock edge. The ideal place for the positive-
goingedgeofthestartpulseiscoincidentwithapositive-going
clock edge. As a special case of the above conditions that
start pulse may be synchronous with a negative-going clock
pulse.
Alternatively the read operation may be initiated by using the
BUSY output to generate interrupt request.
Fig.4 Typical timing diagram using µP clock and write pulse
(a) The MPU clock is not available externally.
(b) The clock frequency is too high.
In some systems, for example single-chip microcomputers
such as the 8048, this simple method may not be feasible for
one or more of the following reasons:
4
ZN427
(c) The write pulse timing criteria make it unsuitable for direct
use as a start conversion pulse.
If any of these conditions apply then the self-synchronising
clock circuit of Fig.5a is recommended.
Fig.5a Self-synchronising clock circuit
Fig.5b Timing diagram for circuit of Fig.5a
5
ZN427
N1 is connected as an astable multivibrator which, when the
BUSY output is high, is inhibited by the output of N2 holding
one of its inputs low. The start conversion pulse resets the
BUSY flag and N1 begins to oscillate. When the conversion
is complete BUSY goes high and the clock is inhibited.
C1 starts from a fully charged condition whereas on
subsequent cycles it changes between the upper and lower
threshold (VT+ and VT) of the Schmitt trigger.
LOGIC INPUTS AND OUTPUTS
Since the start pulse starts the clock it may occur at any time.
The only constraints on the start pulse are that it must be
longerthan250nsbutatleast200nsshorterthanthefirstclock
pulse. The first clock pulse is in fact longer than the rest since
The logic inputs of the ZN427 utilise the emitter-follower
configuration shown in Fig.6. This gives extremely low input
currents for CMOS as well as TTL compatibility.
Fig.6 Equivalent circuit of all inputs
The BUSY output, shown in Fig.7, utilises a passive pullup for CMOS/TTL compatibility.
Fig.7
impedance state. When RD is high the data output will
assume the appropriate logic state (0 or 1).
The data outputs have three-state buffers, an equivalent
circuit of which is shown in Fig.8. Whilst the RD input is low
bothoutputtransistorsareturnedoffandtheoutputisinahigh
6
ZN427
V
CC
500Ω
20k
BITS 1-8
(PINS 11-18)
10k
RD
(PIN 2)
GROUND
Fig.8 Equivalent circuit of data outputs
A test circuit and timing diagram for the output enable/disable delays are given in Fig.9.
Fig.9 Output enable/disable waveforms
7
ZN427
ANALOG CIRCUITS
D-A converter
IThe converter is of the voltage switching type and uses an R-
2R ladder network as shown in Fig.10. Each element is
connectedtoeither0VorVREFINbytransistorvoltageswitches
specially designed for low offset voltage (<1mV).
VOS is a small offset voltage that is produced by the device
supply current flowing in the package lead resistance. The
value of VOS is typically 2mV for the ZN427E8 and 4mV for the
ZN427J8.
A binary weighted voltage is produced at the output of the R-
2R ladder.
This offset will normally be removed by the setting up
procedure and since the offset temperature coefficient is low
(8µV/°C), the effect on accuaracy will be negligible.
D to A output = n (VREF IN -VOS) + VOS
256
The D-A output range can be considered to be 0 - VREF IN
through an output resistance R (4k).
where n is the digital input to the D-A from successive
approximation register.
R(4k)
2R
R
R
R
D TO A OUTPUT
2R
2R
2R
2R
V
IN
REF
(PIN 7)
VOLTAGE
SWITCHES
0 VOLTS
(PIN 9)
V
BIT 8
BIT 7
BIT 2
BIT 1
MSB
OS
Fig.10 R-2R ladder network
REFERENCE
(a) Internal reference
The internal reference is an active bandgap circuit which is
equivalent to a 2.5V Zener diode with a very low slope
impedance (Fig.11). A Resistor (RREF) should be connected
between pins 8 and 10. The recommended value of 390Ω will
supply a nominal reference current of (5.0 - 2.5)/0.39=6.4mA.
A stabilising/decoupling capacitor, CREF (4µ7), is required
between pins 8 and 9. For internal reference operation VREF
OUT (pin 8) is connected to VREF IN (pin 7).
UP to five ZN427's may be driven from one internal reference,
there being no need to reduce RREF. This useful feature saves
power and gives excellent gain tracking between the
converters.
Alternatively the internal reference can be used as the
reference voltage for other external circuits and can source or
sink up to 3mA.
8
ZN427
V
+5V
CC
(PIN 10)
R
REF
(390)
V
OUT
REF
(PIN 8)
C
REF
(4.7µ)
GROUND
(PIN 9)
Fig.11 Internal voltage reference
(b) External reference
same supply. The external reference can vary from +1.5 to
+3.0V. The ZN448/9 will operate if VREF IN is less than +1.5V
but reduced overdrive to the comparator will increase its delay
and so the conversion time will need to be increased.
If required an external reference in the range +1.5 to +3.0V
may be connected to VREF IN. The slope resistance of such a
reference source should be less than 2.5Ω, where n is the
n
number of converters supplied.
COMPARATOR
The ZN427 contains a fast comparator, the equivalent input
circuit of which is shown in Fig.12.
RATIOMETRIC OPERATION
If the output from a transducer varies with its supply then an
external reference for the ZN427 should be derived from the
+5V PIN 10
6k
6k
-
TO LOGIC
HIGH = 'RETAIN BIT'
+
R
IN
A
V
IN
IN
D TO A OUTPUT
(O - V
IN)
REF
PIN 6
4k
4k
PIN 5
R
EXT
I
EXT
V -
Fig.12 Comparator equivalent circuit
9
ZN427
The output from the D-A converter is connected through the
4kΩ ladder resistance to one side of the comparator. The
analoginputtobeconvertedcouldbeconnecteddirectlytothe
other comparator input (VIN, pin 6) but for optimum stability
with temperature the analog input should be applied through
a source resistance (RIN = 4kΩ) to match the ladder
resistance).
The comparator derives the tail current, IEXT, for its first stage
from an external resistor, REXT, which is taken to a negative
supply V–.
This arrangement allows the ZN427 to work with any negative
supply in the range -3 to -30 volts. the ZN427 is designed to
be insensitive to changes in IEXT from 25µA to 150µA. The
suggested nominal value of IEXT is 65µA and a suitable value
for REXT is given by REXT = |V_|15kΩ.
ANALOG INPUT RANGES
The basic connection of the ZN427 shown in Fig.13 has an
analog input range 0 to VREF IN which, in some applications,
may be made available from previous signal conditioning/
scaling circuits. Input voltage ranges greater than this are
accommodated by providing an attenuator on the comparator
input, whilst for smaller input ranges the signal must be
amplified to a suitable level.
V– (volts)
REXT (±10%)
-3
-5
47kΩ
82kΩ
-10
-12
-15
-20
-25
-30
150kΩ
180kΩ
220kΩ
330kΩ
390kΩ
470kΩ
Bipolar input ranges are accommodated by off-setting the
analog input input range so that the comparator always sees
a positive input voltage.
DIGITAL OUTPUTS
LSB
BIT 8
MSB
BIT 1
V
CC
(+5V)
7
6
5
4
3
2
18
17
16
15
14
13
12
11
10
R
REF
(390Ω)
1
2
3
4
5
6
7
8
9
V
IN
R
EXT
(82k)
R
(4k)
IN
C
REF
(4µ7)
BUSY
RD
CK
WR
V-
(-5V)
A
V
INV
REF
OUT GND
(0V)
IN
REF
NOMINAL A RANGE = 0 TO V
IN
IN
REF
Fig.13 External components for basic operation
10
ZN427
UNIPOLAR OPERATION
The general connection for unipolar operation is shown in
To match the ladder resistance R1/R2 (RIN) = 4kΩ.
Fig.14.
The required nominal values of R1 and R2 are given by
R1 = 4Gk, R2 = 4G kΩ
The values of R1 and R2 are chosen so that VIN = VREF IN when
the analogue input (AIN) is at full-scale.
G-1
The resulting full-scale range is given by:
R1
AINFS = 1 +
, VREF IN = G.VREF IN.
R2
A
V
IN
IN
REF
1M
ZERO
ADJUST
R1
680k
7
9
V
IN
6
ZN427
GROUND
R2
Fig.14 Unipolar operation - general connection
Zero adjustment
Using these relationships a table of nominal values of R1 and
R2 can be constructed for VREF IN = 2.5V.
Due to offsets in the DAC and comparator the zero (0 to 1)
code transition would occur with typically 15mV applied to the
comparator input, which correpsonds to 1.5LSB with a 2.56V
reference.
Input range
R1
R2
G
+5V
+10V
8kΩ
16kΩ
8kΩ
5.33kΩ
2
4
Zero adjustment must therefore be provided to set the zero
transition to its correct value of +0.5LSB or 5mV with a 2.56V
reference. Thisisachievedbyapplyinganadjustablepositive
offset to the comparator input via P2 and R3. The values
shown are suitable for all input ranges greater than 1.5 times
VREF IN.
Gain adjustment
Due to tolerance in R1 and R2, tolerance in VREF and the gain
(full-scale) error of the DAC, some adjustment should be
incorporated into R1 to calibrate the full-scale of the converter.
When used with the internal reference and 2% resistors a
preset capable of adjusting R1 by at least ±5% of its nominal
value is suggested.
Practical circuit values for +5 and +10V input ranges are given
in Fig.15, which incorporates both zero and gain adjustments.
11
ZN427
A
V
IN
A
V
IN
REF
IN
REF
IN
P2
P2
P1 5k
GAIN
1M
ZERO
P1 10k
GAIN
1M
ZERO
ADJUST
ADJUST
ADJUST
ADJUST
R1 5k6
680k
R1 11k
R2 5k6
680k
R3
R3
TO PIN 6
TO PIN 6
± 2% RESISTORS
R2 8k2
±20% POTENTIOMETERS
+5V FULL-SCALE
+10V FULL-SCALE
Fig.15 Unipolar operation - component values
Unipolar adjustment prodedure
(iii) Apply 0.5LSB) to AIN and adjust zero until 8 bit just flickers
between 0 and 1 with all other bits at 1.
(i) Apply continuous convert pulses at intervals long enough
to allow a complete conversion and monitor the digital
outputs.
(ii) Applyfull-scaleminus1.5LSB toAIN andadjustoff-setuntil
the 8 bit (LSB) output just flickers between 0 and 1 with all
other bits at 0.
Unipolar setting up points
FS - 1.5LSB
0.5LSB
Input range, +FS
1LSB = FS
256
4.9707V
9.9414V
9.8mV
19.5mV
+5V
+10V
Unipolar logic coding
Output code
Analogue input (AIN)
(offset binary)
(Nominal code centre value)
11111111
11111110
11000000
10000001
10000000
01111111
01000000
00000001
00000000
FS - 1LSB
FS - 2LSB
0.75FS
0.5FS + 1LSB
0.5FS
0.5FS - 1LSB
0.25FS
1LSB
0
12
ZN427
BIPOLAR OPERATION
For bipolar operation the input to the ZN427 is offset by half
full-scale by connecting a resistor R3 between VREF IN and VIN
(Fig.16).
A
V
IN
REF
IN
R1
R3
7
9
V
IN
6
ZN427
GROUND
R2
Fig.16 Bipolar operation - general connection
When AIN = -FS, VIN needs to be equal to zero.
When AIN = +FS, VIN needs to be equal to VREF IN.
Thus the nominal values of R1, R2, R3 are given by R1 = 8 GkΩ,
R2 = 8G/(G - 1)k, R3 = 8kΩ.
A bipolar range of ±VREF IN (which corresponds to the basic
If the full-scale range is ± G. VREF IN then R1 = (G - 1). R2 and
R1 = G. R3 fulfil the required conditions.
unipolar range 0 to +VREF IN) results if R1 = R3 = 8kΩ and R2 =
∞.
To match the ladder resistance, R1/R2/R3 (=RIN) = 4k.
Assuming the VREF IN = 2.5V the nominal values of resistors for
±5 and ±10V input ranges are given in the following table.
R3
Input range
R1
R2
G
8kΩ
8kΩ
+5V
+10V
16kΩ
32kΩ
16kΩ
10.66kΩ
2
4
Minusfull-scale(offset)issetbyadjustingR1 aboutitsnominal
value relative to R3. Plus full-scale (gain) is set by adjusting R2
relative to R1.
Note that in the±5V case R3 has been chosen as 7.5k (instead
of 8.2k) to obtain a more symmetrical range of adjustment
using standard potentiometers.
Practical circuit realisations are given in Fig.17.
13
ZN427
A
V
A
V
IN
REF
IN
REF
5k
OFFSET
ADJUST
10k
OFFSET
ADJUST
7k5
8k2
13k
27k
TO PIN 6
TO PIN 6
5k
5k
GAIN
GAIN
ADJUST
ADJUST
± 2% RESISTORS
±20% POTENTIOMETERS
13
8k2
±5VOLTS FULL SCALE
±10VOLTS FULL SCALE
Fig.17 Bipolar operation - component values
Bipolar adjustment prodedure
(iii) Apply +(FS -1.5LSB) to AIN and adjust gain until the 8 bit
just flickers between 0 and 1 with all other bits at 1.
(i) Apply continuous SC pulses at intervals long enough to
allow a complete conversion and monitor the digital
outputs.
(iv) Repeat step (ii).
(ii) Apply -(FS -0.5LSB) to AIN and adjust off-set until the 8 bit
(LSB)outputjustflickersbetween0and1withallotherbits
at 0.
Bipolar setting up points
+(FS -1.5LSB)
-(FS -0.5LSB)
Input range, ±FS
1LSB =2FS
265
+4.9414V
+9.8828V
-4.9805V
-9.9609V
+5V
+10V
Bipolar logic coding
Output code
Analogue input (AIN)
(offset binary)
(Nominal code centre value)
11111111
11111110
11000000
10000001
10000000
01111111
01000000
00000001
00000000
+(FS - 1LSB)
+(FS - 2LSB)
+0.5FS
+1LSB
0
-1LSB
-0.5FS
-(FS - 1LSB)
-FS
14
ZN427
SINGLE 5 V SUPPLY RAIL OPERATION
any clock frequency from 10kHz to 1MHz and can supply up
to five ZN427's.
TheZN427takesverylittlepowerfromthenegativerailandso
a suitable negative supply can be generated very easily using
a 'diode pump' circuit. The circuit shown in Fig.18 works with
Fig.18 single 5V supply operation
15
ZN427
CUSTOMER SERVICE CENTRES
HEADQUARTERS OPERATIONS
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire SN2 2QW, United Kingdom.
Tel: (0793) 518000
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax : (1) 64 46 06 07
• GERMANY Munich Tel: (089) 3609 06-0 Fax : (089) 3609 06-55
• ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
• JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510
• NORTH AMERICA Integrated Circuits and Microwave Products Scotts Valley, USA
Tel (408) 438 2900 Fax: (408) 438 7023.
Fax: (0793) 518411
Hybrid Products, Farmingdale, USA Tel (516) 293 8686 Fax: (516) 293 0061.
• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
• SWEDEN Stockholm, Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
• UK, EIRE, DENMARK, FINLAND & NORWAY
Swindon Tel: (0793) 518510 Fax : (0793) 518582
These are supported by Agents and Distributors in major countries world-wide.
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017
1500 Green Hills Road,
Scotts Valley, California 95067-0017,
United States of America.
Tel: (408) 438 2900
Fax: (408) 438 5576
© GEC Plessey Semiconductors 1994 Publication No. DS3006 Issue No. 2.1 May 1994
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded
as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company
reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information
and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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