EZ80F91AZ050SC_技术文档

eZ80Acclaim!^™Flash Microcontrollers

eZ80F91 MCU

Product Specification

PS019209-0504

P R E L I M I N A R Y

ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126

Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com

This publication is subject to replacement by a later edition. To determine whether a later edition

exists, or to request copies of publications, contact:

ZiLOG Worldwide Headquarters

532 Race Street

San Jose, CA 95126

Telephone: 408.558.8500

Fax: 408.558.8300

www.ZiLOG.com

ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or

service names mentioned herein may be trademarks of the companies with which they are associated.

Document Disclaimer

technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT

ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES,

OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR

INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES,

OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of

information, devices, or technology as critical components of life support systems is not authorized. No licenses or

other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.

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Table of Contents

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

System Clock Source Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SCLK Source Selection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

®

eZ80 CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

New Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

External Reset Input and Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

HALT Mode and the EMAC Function . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Clock Peripheral Power-Down Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 55

General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

GPIO Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

GPIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Level-Triggered Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Edge-Triggered Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

GPIO Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Port x Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Port x Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Port x Alternate Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Port x Alternate Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

GPIO Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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Chip Selects and Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Memory and I/O Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Memory Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Memory Chip Select Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Memory Chip Select Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

I/O Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

WAIT Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Chip Selects During Bus Request/Bus Acknowledge Cycles . . . . . . . . . . . 78

Bus Mode Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

eZ80 Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Z80 Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Intel Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Intel Bus Mode—Separate Address and Data Buses . . . . . . . . . . . . . . 82

Intel™ Bus Mode—Multiplexed Address and Data Bus . . . . . . . . . . . . 86

Motorola Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Switching Between Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Chip Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Chip Select x Lower Bound Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Chip Select x Upper Bound Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Chip Select x Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Chip Select x Bus Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . 96

Bus Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

RAM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

RAM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

RAM Address Upper Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

MBIST Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Flash Memory Arrangement in the eZ80F91 Device . . . . . . . . . . . . . . . . . 105

Flash Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Reading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Single-Byte I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Multibyte I/O Write (Row Programming) . . . . . . . . . . . . . . . . . . . . . . . 108

Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Information Page Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Flash Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

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Flash Key Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Flash Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Flash Address Upper Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Flash Frequency Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Flash Write/Erase Protection Register . . . . . . . . . . . . . . . . . . . . . . . . 115

Flash Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Flash Row Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Flash Column Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Flash Program Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Watch-Dog Timer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Watch-Dog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Enabling and Disabling the WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Time-Out Period Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

RESET Or NMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Watch-Dog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Watch-Dog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Watch-Dog Timer Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Programmable Reload Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Programmable Reload Timers Overview . . . . . . . . . . . . . . . . . . . . . . . . . 127

Basic Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Reading the Current Count Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Setting Timer Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Single Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Timer Input Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Timer Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Break Point Halting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Specialty Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Event Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

RTC Oscillator Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Timer Port Pin Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Basic Timer Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Register Set for Capture in Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Register Set for Capture/Compare/PWM in Timer 3 . . . . . . . . . . . . . . 137

Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Timer Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Timer Interrupt Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . 141

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Timer Data Register—Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Timer Data Register—High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Timer Reload Register—Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Timer Reload Register—High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Timer Input Capture Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 144

Timer Input Capture Value A Register—Low Byte . . . . . . . . . . . . . . . 145

Timer Input Capture Value A Register—High Byte . . . . . . . . . . . . . . . 146

Timer Input Capture Value B Register—Low Byte . . . . . . . . . . . . . . . 146

Timer Input Capture Value B Register—High Byte . . . . . . . . . . . . . . . 147

Timer Output Compare Control Register 1 . . . . . . . . . . . . . . . . . . . . . 147

Timer Output Compare Control Register 2 . . . . . . . . . . . . . . . . . . . . . 148

Timer Output Compare Value Register—Low Byte . . . . . . . . . . . . . . . 149

Timer Output Compare Value Register—High Byte . . . . . . . . . . . . . . 150

Multi-PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Multi-PWM Mode Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

PWM Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Modification of Edge Transition Values . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

AND/OR Gating of the PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

PWM Nonoverlapping Output Pair Delays . . . . . . . . . . . . . . . . . . . . . . . . 155

Multi-PWM Power-Trip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Multi-PWM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Pulse-Width Modulation Control Register 1 . . . . . . . . . . . . . . . . . . . . . 158

Pulse-Width Modulation Control Register 2 . . . . . . . . . . . . . . . . . . . . . 159

Pulse-Width Modulation Control Register 3 . . . . . . . . . . . . . . . . . . . . . 161

Pulse-Width Modulation Rising Edge—Low Byte . . . . . . . . . . . . . . . . 162

Pulse-Width Modulation Rising Edge—High Byte . . . . . . . . . . . . . . . . 163

Pulse-Width Modulation Falling Edge—Low Byte . . . . . . . . . . . . . . . . 164

Pulse-Width Modulation Falling Edge—High Byte . . . . . . . . . . . . . . . 165

Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Real-Time Clock Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Real-Time Clock Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Real-Time Clock Oscillator and Source Selection . . . . . . . . . . . . . . . . . . . 167

Real-Time Clock Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Real-Time Clock Recommended Operation . . . . . . . . . . . . . . . . . . . . . . . 167

Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Real-Time Clock Seconds Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Real-Time Clock Minutes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Real-Time Clock Hours Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Real-Time Clock Day-of-the-Week Register . . . . . . . . . . . . . . . . . . . . 171

Real-Time Clock Day-of-the-Month Register . . . . . . . . . . . . . . . . . . . . 172

Real-Time Clock Month Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Real-Time Clock Year Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Real-Time Clock Century Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Real-Time Clock Alarm Seconds Register . . . . . . . . . . . . . . . . . . . . . 176

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Real-Time Clock Alarm Minutes Register . . . . . . . . . . . . . . . . . . . . . . 177

Real-Time Clock Alarm Hours Register . . . . . . . . . . . . . . . . . . . . . . . . 178

Real-Time Clock Alarm Day-of-the-Week Register . . . . . . . . . . . . . . . 179

Real-Time Clock Alarm Control Register . . . . . . . . . . . . . . . . . . . . . . . 180

Real-Time Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . 183

UART Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

UART Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

UART Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

UART Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

UART Modem Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

UART Transmitter Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

UART Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

UART Modem Status Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

UART Recommended Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Module Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

BRG Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

UART Baud Rate Generator Register—Low and High Bytes . . . . . . . 189

UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

UART Transmit Holding Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

UART Receive Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

UART Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

UART Interrupt Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . 193

UART FIFO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

UART Line Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

UART Modem Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

UART Line Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

UART Modem Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

UART Scratch Pad Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Infrared Encoder/Decoder Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Loopback Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Infrared Encoder/Decoder Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

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Master In, Slave Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Master Out, Slave In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

SPI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

SPI Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Mode Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Write Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Baud Rate Generator Functional Description . . . . . . . . . . . . . . . . . . . 213

Data Transfer Procedure with SPI Configured as a Master . . . . . . . . . . . 214

Data Transfer Procedure with SPI Configured as a Slave . . . . . . . . . . . . 214

SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

SPI Baud Rate Generator Registers—Low Byte and High Byte . . . . . 215

SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

SPI Transmit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

SPI Receive Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

2

I C Serial I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

2

I C General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Clocking Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Bus Arbitration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Transferring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Clock Synchronization for Handshake . . . . . . . . . . . . . . . . . . . . . . . . . 224

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Master Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Master Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Slave Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Slave Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

2

I C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

2

Resetting the I C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

2

I C Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

I2C Extended Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . 232

2

I C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

2

I C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

2

I C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

2

I C Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

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Bus Clock Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

2

I C Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Ethernet Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

EMAC Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

TxDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

RxDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

EMAC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

EMAC Shared Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

EMAC and the System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

EMAC Operation in HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

EMAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

EMAC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

EMAC Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

EMAC Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

EMAC Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

EMAC Configuration Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

EMAC Station Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

EMAC Transmit Pause Timer Value Register—Low and High Bytes . 257

EMAC Interpacket Gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

EMAC Interpacket Gap Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

EMAC Interpacket Gap Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

EMAC Non-Back-To-Back IPG Register—Part 1 . . . . . . . . . . . . . . . . 260

EMAC Non-Back-To-Back IPG Register—Part 2 . . . . . . . . . . . . . . . . 261

EMAC Maximum Frame Length Register—Low and High Bytes . . . . 261

EMAC Address Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

EMAC Hash Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

EMAC MII Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

EMAC PHY Configuration Data Register—Low Byte . . . . . . . . . . . . . 266

EMAC PHY Configuration Data Register—High Byte . . . . . . . . . . . . . 267

EMAC PHY Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

EMAC PHY Unit Select Address Register . . . . . . . . . . . . . . . . . . . . . . 268

EMAC Transmit Polling Timer Register . . . . . . . . . . . . . . . . . . . . . . . . 268

EMAC Reset Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

EMAC Transmit Lower Boundary Pointer Register—Low and

High Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

EMAC Boundary Pointer Register—Low and High Bytes . . . . . . . . . . 271

EMAC Boundary Pointer Register—Upper Byte . . . . . . . . . . . . . . . . . 272

EMAC Receive High Boundary Pointer Register—Low and

High Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

EMAC Receive Read Pointer Register—Low and High Bytes . . . . . . 273

EMAC Buffer Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

EMAC Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

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EMAC Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

EMAC PHY Read Status Data Register—Low and High Bytes . . . . . 278

EMAC MII Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

EMAC Receive Write Pointer Register—Low Byte . . . . . . . . . . . . . . . 280

EMAC Receive Write Pointer Register—High Byte . . . . . . . . . . . . . . . 281

EMAC Transmit Read Pointer Register—Low Byte . . . . . . . . . . . . . . 281

EMAC Transmit Read Pointer Register—High Byte . . . . . . . . . . . . . . 282

EMAC Receive Blocks Left Register—Low and High Bytes . . . . . . . . 282

EMAC FIFO Data Register—Low and High Bytes . . . . . . . . . . . . . . . 284

EMAC FIFO Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

ZiLOG Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

ZDI-Supported Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

ZDI Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

ZDI Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

ZDI Single-Bit Byte Separator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

ZDI Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

ZDI Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

ZDI Single-Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

ZDI Block Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

ZDI Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

ZDI Single-Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

ZDI Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Operation of the eZ80F91 Device during ZDI Break Points . . . . . . . . . . . 293

Bus Requests During ZDI Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Potential Hazards of Enabling Bus Requests During Debug Mode . . . 294

ZDI Write Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

ZDI Read Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

ZDI Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

ZDI Address Match Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

ZDI Break Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

ZDI Master Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

ZDI Write Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

ZDI Read/Write Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

ZDI Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Instruction Store 4:0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

ZDI Write Memory Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

eZ80 Product ID Low and High Byte Registers . . . . . . . . . . . . . . . . . . 305

eZ80 Product ID Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

ZDI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

ZDI Read Register Low, High, and Upper . . . . . . . . . . . . . . . . . . . . . . 308

ZDI Bus Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

ZDI Read Memory Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

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On-Chip Instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Introduction to On-Chip Instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . 311

OCI Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

OCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Pin Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Boundary Scan Cell Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Chain Sequence and Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Boundary Scan Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Phase Frequency Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

MUX/CLK Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

PLL Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Power Requirement to the Phase-Locked Loop Function . . . . . . . . . . . . . 323

PLL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

PLL Divider Control Register—Low and High Bytes . . . . . . . . . . . . . . 323

PLL Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

PLL Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

®

eZ80 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Op-Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Primary Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

32KHz Real-Time Clock Crystal Oscillator Operation . . . . . . . . . . . . . . . . 343

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

POR and VBO Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

External Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

External Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

External I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

External I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

Wait State Timing for Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

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Wait State Timing for Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

General Purpose I/O Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . 357

General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 357

External Bus Acknowledge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

External System Clock Driver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

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List of Figures

Figure 1. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 2. Example: Memory Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 3. Wait Input Sampling Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 4. Example: Z80 Bus Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 5. Example: Z80 Bus Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 6. Intel Bus Mode Signal and Pin Mapping . . . . . . . . . . . . . . . . . . . . . . 82

Figure 7. Motorola Bus Mode Signal and Pin Mapping . . . . . . . . . . . . . . . . . . . 89

Figure 8. Example: eZ80F91 On-Chip RAM Memory Addressing . . . . . . . . . 101

Figure 9. Programmable Reload Timer Block Diagram . . . . . . . . . . . . . . . . . . 127

Figure 10. PWM AND/OR Gating Functional Diagram . . . . . . . . . . . . . . . . . . 155

Figure 11. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 12. SPI Master Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 13. SPI Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

2

Figure 14. I C Clock and Data Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . 220

2

Figure 15. START and STOP Conditions In I C Protocol . . . . . . . . . . . . . . . . 220

2

Figure 16. I C Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

2

Figure 17. I C Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

2

Figure 18. Clock Synchronization In I C Protocol . . . . . . . . . . . . . . . . . . . . . . 223

Figure 19. internal Ethernet Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 20. Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 21. Descriptor Table Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 22. Typical ZDI Debug Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Figure 23. Schematic For Building a Target Board ZPAK Connector . . . . . . . 287

Figure 24. ZDI Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

Figure 25. ZDI Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

Figure 26. Normal PLL Programming Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Figure 27. Recommended Crystal Oscillator Configuration—50MHz

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Figure 28. Recommended Crystal Oscillator Configuration—32KHz

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

Figure 29. External I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

Figure 30. Wait State Timing for Read Operations . . . . . . . . . . . . . . . . . . . . . 355

Figure 31. Wait State Timing for Write Operations . . . . . . . . . . . . . . . . . . . . . 356

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List of Tables

Table 1. Clock Peripheral Power-Down Register 1 . . . . . . . . . . . . . . . . . . . . 56

Table 2. Clock Peripheral Power-Down Register 2 . . . . . . . . . . . . . . . . . . . . 57

Table 3. Port x Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 4. Port x Alternate Registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 5. Port x Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 6. Port x Alternate Registers 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 7. Interrupt Vector Sources by Priority . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 8. Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 9. Interrupt Vector Priority Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 10. Example: Maskable Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 11. Example: Priority Levels for Maskable Interrupts . . . . . . . . . . . . . . . 71

Table 12. Chip Select x Lower Bound Register . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 13. Chip Select x Upper Bound Register . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 14. Chip Select x Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 15. Chip Select x Bus Mode Control Register . . . . . . . . . . . . . . . . . . . . 96

Table 16. eZ80F91 Pin Status During Bus Acknowledge Cycles. . . . . . . . . . . 98

Table 17. RAM Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 18. RAM Address Upper Byte Register . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 19. MBIST Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 20. Flash Key Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 21. Flash Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 22. Flash Address Upper Byte Register . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 23. Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 24. Flash Frequency Divider Values. . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 25. Flash Frequency Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 26. Flash Write/Erase Protection Register . . . . . . . . . . . . . . . . . . . . . . 115

Table 27. Flash Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 28. Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 29. Flash Row Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 30. Flash Column Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 31. Flash Program Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 32. Watch-Dog Timer Approximate Time-Out Delays . . . . . . . . . . . . . 123

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Table 33. Watch-Dog Timer Approximate Time-Out Delays w/ Internal

RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 34. Watch-Dog Timer Control Register. . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 35. Watch-Dog Timer Reset Register. . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 36. Example: PRT Single Pass Mode Parameters. . . . . . . . . . . . . . . . 129

Table 37. Example : PRT Continuous Mode Parameters. . . . . . . . . . . . . . . . 130

Table 38. Example: PRT Timer Out Parameters . . . . . . . . . . . . . . . . . . . . . . 132

Table 39. GPIO Mode Selection When Using Timer Pins . . . . . . . . . . . . . . . 135

Table 40. Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 41. Timer Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 42. Timer Interrupt Identification Register. . . . . . . . . . . . . . . . . . . . . . . 141

Table 43. Timer Data Register—Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 44. Timer Reload Register—Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 45. Timer Data Register—High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 46. Timer Reload Register—High Byte. . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 47. Timer Input Capture Control Register. . . . . . . . . . . . . . . . . . . . . . . 144

Table 48. Timer Input Capture Value Register A—Low Byte . . . . . . . . . . . . . 145

Table 49. Timer Input Capture Value Register A—High Byte . . . . . . . . . . . . 146

Table 50. Timer Input Capture Value Register B—Low Byte . . . . . . . . . . . . . 146

Table 51. Timer Input Capture Value Register B—High Byte . . . . . . . . . . . . 147

Table 52. Timer Output Compare Control Register 1. . . . . . . . . . . . . . . . . . . 147

Table 53. Timer Output Compare Control Register 2. . . . . . . . . . . . . . . . . . . 148

Table 54. Compare Value Register—Low Byte . . . . . . . . . . . . . . . . . . . . . . . 149

Table 55. Compare Value Register—High Byte . . . . . . . . . . . . . . . . . . . . . . . 150

Table 56. Enabling PWM Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 57. PWM Nonoverlapping Output Addressing . . . . . . . . . . . . . . . . . . . 156

Table 58. PWM Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 59. PWM Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 60. PWM Control Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 61. PWMx Rising-Edge Register—Low Byte . . . . . . . . . . . . . . . . . . . . 162

Table 62. PWMx Rising-Edge Register—High Byte. . . . . . . . . . . . . . . . . . . . 163

Table 63. PWMx Falling-Edge Register—Low Byte . . . . . . . . . . . . . . . . . . . . 164

Table 64. PWMx Falling-Edge Register—High Byte . . . . . . . . . . . . . . . . . . . 165

Table 65. Real-Time Clock Seconds Register . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 66. Real-Time Clock Minutes Register . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 67. Real-Time Clock Hours Register . . . . . . . . . . . . . . . . . . . . . . . . . . 170

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Table 68. Real-Time Clock Day-of-the-Week Register. . . . . . . . . . . . . . . . . . 171

Table 69. Real-Time Clock Day-of-the-Month Register . . . . . . . . . . . . . . . . . 172

Table 70. Real-Time Clock Month Register . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 71. Real-Time Clock Year Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 72. Real-Time Clock Century Register . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 73. Real-Time Clock Alarm Seconds Register . . . . . . . . . . . . . . . . . . . 176

Table 74. Real-Time Clock Alarm Minutes Register. . . . . . . . . . . . . . . . . . . . 177

Table 75. Real-Time Clock Alarm Hours Register . . . . . . . . . . . . . . . . . . . . . 178

Table 76. Real-Time Clock Alarm Day-of-the-Week Register . . . . . . . . . . . . 179

Table 77. Real-Time Clock Alarm Control Register . . . . . . . . . . . . . . . . . . . . 180

Table 78. Real-Time Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 79. UART Baud Rate Generator Register—Low Bytes . . . . . . . . . . . . 190

Table 80. UART Baud Rate Generator Register—High Bytes . . . . . . . . . . . . 190

Table 81. UART Transmit Holding Registers . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 82. UART Receive Buffer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 83. UART Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 84. UART Interrupt Identification Registers . . . . . . . . . . . . . . . . . . . . . 193

Table 85. UART Interrupt Status Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 86. UART FIFO Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 87. UART Line Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 88. UART Character Parameter Definition . . . . . . . . . . . . . . . . . . . . . . 197

Table 89. UART Modem Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 90. Parity Select Definition for Multidrop Communications. . . . . . . . . . 198

Table 91. UART Line Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 92. UART Modem Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 93. UART Scratch Pad Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 94. Infrared Encoder/Decoder Control Registers . . . . . . . . . . . . . . . . . 207

Table 95. SPI Clock Phase and Clock Polarity Operation . . . . . . . . . . . . . . . 211

Table 96. SPI Baud Rate Generator Register—Low Byte . . . . . . . . . . . . . . . 215

Table 97. SPI Baud Rate Generator Register—High Byte . . . . . . . . . . . . . . . 215

Table 98. SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 99. SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Table 100. SPI Receive Buffer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 101. SPI Transmit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

2

Table 102. I C Master Transmit Status Codes. . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 103. I²C 10-Bit Master Transmit Status Codes. . . . . . . . . . . . . . . . . . . . 226

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Table 104. I²C Master Transmit Status Codes For Data Bytes . . . . . . . . . . . . 227

Table 105. I²C Master Receive Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 106. I²C Master Receive Status Codes For Data Bytes. . . . . . . . . . . . . 229

Table 107. I²C Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Table 108. I²C Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Table 109. I²C Extended Slave Address Register . . . . . . . . . . . . . . . . . . . . . . 233

Table 110. I²C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Table 111. I²C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Table 112. I²C Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Table 113. I²C Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Table 114. I²C Clock Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Table 115. I²C Software Reset Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Table 116. Arbiter Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Table 117. EMAC Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Table 118. EMAC Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Table 119. EMAC Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Table 120. EMAC Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Table 121. EMAC Configuration Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Table 122. EMAC Station Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Table 123. EMAC Transmit Pause Timer Value Register—Low Byte . . . . . . . 257

Table 124. EMAC Transmit Pause Timer Value Register—High Byte . . . . . . . 257

Table 125. EMAC_IPGT Non-Back-to-Back Settings for Full/Half Duplex

Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Table 126. EMAC Non-Back-To-Back IPG Register—Part 1 . . . . . . . . . . . . . . 260

Table 127. EMAC Interpacket Gap Register . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Table 128. EMAC Non-Back-To-Back IPG Register—Part 2 . . . . . . . . . . . . . . 261

Table 129. EMAC Maximum Frame Length Register—High Byte. . . . . . . . . . 262

Table 130. EMAC Maximum Frame Length Register—Low Byte . . . . . . . . . . 262

Table 131. EMAC Address Filter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Table 132. EMAC Hash Table Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Table 133. EMAC MII Management Register . . . . . . . . . . . . . . . . . . . . . . . . . 265

Table 134. EMAC PHY Configuration Data Register—Low Byte . . . . . . . . . . 266

Table 135. EMAC PHY Configuration Data Register—High Byte . . . . . . . . . . 267

Table 136. EMAC PHY Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Table 137. EMAC PHY Unit Select Address Register. . . . . . . . . . . . . . . . . . . 268

Table 138. EMAC Transmit Polling Timer Register. . . . . . . . . . . . . . . . . . . . . 268

PS019209-0504

P R E L I M I N A R Y

List of Tables

eZ80F91 MCU

Product Specification

xviii

Table 139. EMAC Reset Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Table 140. EMAC Transmit Lower Boundary Pointer Register—Low Byte. . . 270

Table 141. EMAC Transmit Lower Boundary Pointer Register—High Byte . . 270

Table 142. EMAC Boundary Pointer Register—Low Byte. . . . . . . . . . . . . . . . 271

Table 143. EMAC Boundary Pointer Register—High Byte . . . . . . . . . . . . . . . 271

Table 144. EMAC Boundary Pointer Register—Upper Byte . . . . . . . . . . . . . . 272

Table 145. EMAC Receive High Boundary Pointer Register—Low Byte . . . . 272

Table 146. EMAC Receive Read Pointer Register—Low Byte . . . . . . . . . . . . 273

Table 147. EMAC Receive High Boundary Pointer Register—High Byte . . . . 273

Table 148. EMAC Receive Read Pointer Register—High Byte. . . . . . . . . . . . 274

Table 149. EMAC Buffer Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Table 150. EMAC Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Table 151. EMAC Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Table 152. EMAC PHY Read Status Data Register—Low Byte. . . . . . . . . . . . 278

Table 153. EMAC MII Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Table 154. EMAC PHY Read Status Data Register—High Byte . . . . . . . . . . . 279

Table 155. EMAC Receive Write Pointer Register—Low Byte. . . . . . . . . . . . . 280

Table 156. EMAC Receive Write Pointer Register—High Byte . . . . . . . . . . . . 281

Table 157. EMAC Transmit Read Pointer Register—Low Byte . . . . . . . . . . . . 281

Table 158. EMAC Transmit Read Pointer Register—High Byte. . . . . . . . . . . . 282

Table 159. EMAC Receive Blocks Left Register—High Byte . . . . . . . . . . . . . . 283

Table 160. EMAC Receive Blocks Left Register—Low Byte . . . . . . . . . . . . . . 283

Table 161. EMAC FIFO Data Register—Low Byte. . . . . . . . . . . . . . . . . . . . . . 284

Table 162. EMAC FIFO Data Register—High Byte . . . . . . . . . . . . . . . . . . . . . 284

Table 163. EMAC FIFO Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Table 164. Recommend ZDI Clock vs. System Clock Frequency . . . . . . . . . . 287

Table 165. ZDI Write Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Table 166. ZDI Address Match Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Table 167. ZDI Break Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Table 168. ZDI Master Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Table 169. ZDI Write Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Table 170. ZDI Read/Write Control Register Functions . . . . . . . . . . . . . . . . . . 301

Table 171. ZDI Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Table 172. Instruction Store 4:0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

Table 173. eZ80 Product ID Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . . 305

Table 174. ZDI Write Memory Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

PS019209-0504

P R E L I M I N A R Y

List of Tables

eZ80F91 MCU

Product Specification

xix

Table 175. eZ80 Product ID Revision Register . . . . . . . . . . . . . . . . . . . . . . . . 306

Table 176. eZ80 Product ID High Byte Register . . . . . . . . . . . . . . . . . . . . . . . 306

Table 177. ZDI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Table 178. ZDI Read Register Low, High and Upper . . . . . . . . . . . . . . . . . . . . 308

Table 179. ZDI Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

Table 180. ZDI Read Memory Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Table 181. PLL Divider Register—Low Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . 324

Table 182. PLL Divider Register—High Bytes . . . . . . . . . . . . . . . . . . . . . . . . . 324

Table 183. PLL Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Table 184. PLL Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Table 185. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Table 186. Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Table 187. Block Transfer and Compare Instructions . . . . . . . . . . . . . . . . . . . 330

Table 188. Exchange Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Table 189. Input/Output Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Table 190. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Table 191. Logical Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Table 192. Processor Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Table 193. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Table 194. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Table 195. Recommended Crystal Oscillator Specifications—1MHz

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

Table 196. Recommended Crystal Oscillator Specifications—10MHz

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

Table 197. Recommended Crystal Oscillator Specifications—32KHz

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

Table 198. Typical 144-LQFP Package Electrical Characteristics . . . . . . . . . . 348

Table 199. External Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

Table 200. External Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Table 201. External I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

Table 202. External I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

Table 203. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

Table 204. Bus Acknowledge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

Table 205. PHI System Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

PS019209-0504

P R E L I M I N A R Y

List of Tables

eZ80F91 MCU

Product Specification

1

Architectural Overview

™

The eZ80F91 device is a member of ZiLOG’s family of eZ80Acclaim! Flash

Microcontrollers. The eZ80F91 is a high-speed single-cycle instruction-fetch

microcontroller with a maximum clock speed of 50MHz. It can operate in Z80-

compatible addressing mode (64KB) or full 24-bit addressing mode (16MB). The

rich peripheral set of the eZ80F91 makes it suitable for a variety of applications,

including industrial control, embedded communication, and point-of-sale termi-

nals.

Features

®

1

•

Single-cycle instruction fetch, high-performance, pipelined eZ80 CPU core

10/100 BaseT Ethernet Media Access Controller with Media-Independent

Interface (MII)

•

256KB Flash memory and 16 KB SRAM (8KB user, 8KB EMAC)

Low power features including SLEEP mode, HALT mode, and selective

peripheral power-down control

•

Two UARTs with independent baud rate generators

SPI with independent clock rate generator

2

I C with independent clock rate generator

IrDA-compliant infrared encoder/decoder

Glueless external peripheral interface with 4 Chip Selects, individual Wait

State generators, and an external WAIT input pin—supports Z80-, Intel-, and

Motorola-style buses

•

Fixed-priority vectored interrupts (both internal and external) and interrupt

controller

Real-time clock with on-chip 32KHz oscillator, selectable 50/60Hz input, and

separate V_DDpin for battery backup

•

Four 16-bit Counter/Timers with prescalers and direct input/output drive

Watch-Dog Timer with internal oscillator clocking option

32 bits of General-Purpose I/O

OCI™ and ZDI debug interfaces

®

1. For simplicity, the term eZ80 CPU is referred to as CPU for the bulk of this

document.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

2

•

1149.1-compatible JTAG

144-pin LQFP and BGA packages

3.0–3.6V supply voltage with 5V tolerant inputs

Operating Temperature Range:

–

Standard: 0ºC to +70ºC

Extended: –40ºC to +105ºC

All signals with an overline are active Low. For example, B/W, for which WORD is

active Low, and B/W, for which BYTE is active Low.

Note:

Power connections follow these conventional descriptions:

Connection

Power

Circuit

Device

V_DD

V

CC

Ground

GND

V_SS

Block Diagram

Figure 1 illustrates a block diagram of the eZ80F91 microcontroller.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

3

MII Interface

Signals (18)

Ethernet

MAC

8KB

SRAM

Arbiter

Real-Time

RTC_VDD

RTC_XIN

Clock and

32KHz

BUSACK

BUSREQ

RTC_XOUT

Oscillator

INSTRD

IORQ

Bus

Controller

I2C

Serial

Interface

MREQ

RD

SCL

SDA

WR

SCK

SS

NMI

SPI

Serial

Parallel

Interface

eZ80

CPU

HALT_SLP

MISO

MOSI

256KB

Flash

JTAG/ZDI

Debug

JTAG / ZDI Signals (5)

Memory

Interface

WP

WAIT

CTS0/1

DSR0/1

DCD0/1

DTR0/1

RI0/1

Interrupt

Vector

[8:0]

Chip Select

&

CS0

CS1

CS2

CS3

8KB

SRAM

UART

Universal

Asynchronous

Receiver/

Transmitter

(2)

Wait State

Generator

Interrupt

Controller

RTS0/1

RxD0/1

TxD0/1

DATA[7:0]

ADDR[23:0]

WDT

Internal

RC

Osc.

GPIO

8-bit General

Purpose

I/O Port

(4)

Crystal

Oscillator,

PLL, and

System Clock

Generator

Programmable

Watchdog

Timer

IrDA

Encoder/

Decoder

Reload

Timer/Counter

(4)

POR/VBO

RESET

Figure 1. eZ80F91 Block Diagram

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

4

Pin Description

Table 1 details the pin configuration of the eZ80F91 device in the 144-ball BGA

package.

Table 1. eZ80F91 144-Ball BGA Pin Configuration

12

SDA SCL

PHI

11

10

9

8

7

6

5

4

3

2

1

A

B

C

PA0

PA1

PA4

PA3

PA5

PA7

COL

TxD3

TxD2

TxD0

V

Rx_DV MDC WPn

RxD1 MDIO A2

A0

A1

DD

V

Tx_EN

Tx_CLK

V

SS

DD

PB6 PB7

V

Rx_

CLK

RxD3

A3

V

DD

SS

D

E

F

PB1 PB3

PB5

PB0

PC5

PC1

V

CRS

PA2

PB2

PC6

TxD1

Tx_ER

PA6

Rx_ER

RxD0

A9

RxD2

A5

A4

A8

A6

A7

SS

PC7

V

PB4

A11

A15

A20

V

A10

A12

A16

DD

SS

DD

PC3 PC4

V

A17

A23

A14

A13

SS

G

V

PC0

PC2

PLL_

V

DD

SS

V

SS

H

J

X

PLL_

V

PD7

TMS

V

D5

V

A21

A19

A18

A22

DD

SS

OUT

IN

V

DD

V

LOOP

FILT_

OUT

PD4 TRIGOUT

RTC_

NMIn

WRn

D2

CS0n

V

DD

SS

DD

V

DD

K

L

PD5 PD6

PD3

TDI

V

RESETn RDn

V

D1

D4

CS2n CS1n

D0 CS3n

SS

DD

PD1 PD2 TRSTn TCK

RTC_ BUSACKn WAITn MREQn D6

XOUT

M

PD0

V

TDO HALT_

SLPn

RTC_ BUSREQn INSTRDn IORQn

XIN

D7

D3

V

DD

SS

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

5

Figure 2 illustrates the pin layout of the eZ80F91 device in the 144-pin LQFP

package.

108 V_SS

1

A0

A1

A2

A3

A4

V_DD

V_SS

A5

PB7/MOSI

PB6/MISO

PB5/IC3

PB4/IC2

PB3/SCK

PB2/SS

PB1/IC1

100 PB0/IC0/EC0

V_SS

A6

A7 10

A8

V_DD

PC7/RI1

A9

A10

V_DD

V_SS

A11

A12

A13

A14

PC6/DCD1

PC5/DSR1

PC4/DTR1

PC3/CTS1

PC2/RTS1

PC1/RxD1

144-Pin LQFP

90 PC0/TxD1

V_SS

V_DD

PLL_V_DD

X_IN

X_OUT

PLL_V_SS

LOOP_FILT

V_SS

A15 20

A16

V_DD

V_SS

A17

A18

A19

A20

A21

V_DD

80 PD7/RI0

PD6/DCD0

PD5/DSR0

PD4/DTR0

PD3/CTS0

PD2/RTS0

PD1/RxD0/IR_RxD

73 PD0/TxD0/IR_TxD

A22

A23 30

V_DD

V_SS

CS0

CS1

CS2

CS3 36

Figure 2. 144-Pin LQFP Configuration of the eZ80F91

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

6

Pin Characteristics

Table 2 describes the pins and functions of the eZ80F91 MCU’s 144-pin LQFP

package and 144-ball BGA package.

Table 2. Pin Identification on the eZ80F91 Device

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

1

2

3

4

A1

B1

B2

C3

ADDR0

Address Bus Bidirectional

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

ADDR1

ADDR2

ADDR3

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

7

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

5

D4

ADDR4

Address Bus Bidirectional

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

6

7

8

C1

C2

E5

V_DD

Power Supply

Power Supply.

Ground.

V_SS

Ground

ADDR5

Address Bus Bidirectional

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

9

D2

ADDR6

Address Bus Bidirectional

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

10

D1

ADDR7

Address Bus Bidirectional

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

8

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

11

12

13

D3

F6

E1

ADDR8

Address Bus Bidirectional

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

ADDR9

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

ADDR10

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

14

15

16

E2

E3

E4

V_DD

Power Supply

Power Supply.

Ground.

V_SS

Ground

ADDR11

Address Bus Bidirectional

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

9

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

17

18

19

20

F1

F2

F3

F4

ADDR12

Address Bus Bidirectional

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

ADDR13

ADDR14

ADDR15

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

10

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

21

G1

ADDR16

Address Bus Bidirectional

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

22

23

24

G2

G3

F5

V_DD

Power Supply

Power Supply.

Ground.

V_SS

Ground

ADDR17

Address Bus Bidirectional

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

25

H1

ADDR18

Address Bus Bidirectional

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

26

H2

ADDR19

Address Bus Bidirectional

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

11

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

27

28

29

30

G4

H3

J1

ADDR20

Address Bus Bidirectional

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

ADDR21

ADDR22

ADDR23

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

G5

Configured as an output in

normal operation. The address

bus selects a location in memory

or I/O space to be read or written.

Configured as an input during bus

acknowledge cycles. Drives the

Chip Select/Wait State Generator

block to generate Chip Selects.

31

32

33

J2

H4

J3

V_DD

V_SS

CS0

Power Supply

Power Supply.

Ground.

Ground

Chip Select 0 Output, Active Low

CS0 Low indicates that an access

is occurring in the defined CS0

memory or I/O address space.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

12

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

34

35

36

K1

K2

L1

CS1

Chip Select 1 Output, Active Low

Chip Select 2 Output, Active Low

Chip Select 3 Output, Active Low

CS1 Low indicates that an access

is occurring in the defined CS1

memory or I/O address space.

CS2

CS3

CS2 Low indicates that an access

is occurring in the defined CS2

memory or I/O address space.

CS3 Low indicates that an access

is occurring in the defined CS3

memory or I/O address space.

37

38

39

M1

M2

L2

V_DD

Power Supply

Ground

Power Supply.

Ground.

V_SS

DATA0

Data Bus

Bidirectional

The data bus transfers data to

and from I/O and memory

devices. The eZ80F91 drives

these lines only during Write

cycles when the eZ80F91 is the

bus master.

40

41

42

K3

J4

DATA1

DATA2

DATA3

The data bus transfers data to

and from I/O and memory

devices. The eZ80F91 drives

these lines only during Write

cycles when the eZ80F91 device

is the bus master.

The data bus transfers data to

and from I/O and memory

devices. The eZ80F91 drives

these lines only during Write

cycles when the eZ80F91 is the

bus master.

M3

The data bus transfers data to

and from I/O and memory

devices. The eZ80F91 drives

these lines only during Write

cycles when the eZ80F91 is the

bus master.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

13

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

43

44

45

46

L3

H5

L4

M4

DATA4

Data Bus

Bidirectional

The data bus transfers data to

and from I/O and memory

devices. The eZ80F91 drives

these lines only during Write

cycles when the eZ80F91 is the

bus master.

DATA5

DATA6

DATA7

Data Bus

Bidirectional

The data bus transfers data to

and from I/O and memory

devices. The eZ80F91 drives

these lines only during Write

cycles when the eZ80F91 is the

bus master.

The data bus transfers data to

and from I/O and memory

devices. The eZ80F91 drives

these lines only during Write

cycles when the eZ80F91 is the

bus master.

The data bus transfers data to

and from I/O and memory

devices. The eZ80F91 drives

these lines only during Write

cycles when the eZ80F91 is the

bus master.

47

48

49

K4

G6

M5

V_DD

Power Supply

Ground

Power Supply.

Ground.

V_SS

IORQ

Input/Output

Request

Bidirectional, Active IORQ indicates that the CPU is

Low

accessing a location in I/O space.

RD and WR indicate the type of

access. The eZ80F91 device

does not drive this line during

RESET. It is an input in bus

acknowledge cycles.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

14

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

50 L5

MREQ

Memory

Request

Bidirectional, Active MREQ Low indicates that the

Low

CPU is accessing a location in

memory. The RD, WR, and

INSTRD signals indicate the type

of access. The eZ80F91 device

does not drive this line during

RESET. It is an input in bus

acknowledge cycles.

51

K5

RD

Read

Write

Output, Active Low

RD Low indicates that the

eZ80F91 device is reading from

the current address location. This

pin is tristated during bus

acknowledge cycles.

52

53

J5

WR

Output, Active Low

WR indicates that the CPU is

writing to the current address

location. This pin is tristated

during bus acknowledge cycles.

M6

INSTRD

Instruction

Read Indicator

INSTRD (with MREQ and RD)

indicates the eZ80F91 device is

fetching an instruction from

memory. This pin is tristated

during bus acknowledge cycles.

54

55

L6

K6

WAIT

WAIT Request Schmitt-trigger input, Driving the WAIT pin Low forces

Active Low

the CPU to wait additional clock

cycles for an external peripheral

or external memory to complete

its Read or Write operation.

RESET

Reset

Schmitt-trigger input, This signal is used to initialize the

Active Low

eZ80F91 device. This input must

be Low for a minimum of 3

system clock cycles, and must be

held Low until the clock is stable.

This input includes a Schmitt

trigger to allow RC rise times.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

15

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

56

J6

NMI

Nonmaskable Schmitt-trigger input, The NMI input is a higher priority

Interrupt

Active Low

input than the maskable

interrupts. It is always recognized

at the end of an instruction,

regardless of the state of the

interrupt enable control bits. This

input includes a Schmitt trigger to

allow RC rise times.

57

58

M7

L7

BUSREQ

BUSACK

Bus Request Schmitt-trigger input, External devices can request the

Active Low

eZ80F91 device to release the

memory interface bus for their

use, by driving this pin Low.

Bus

Acknowledge

Output, Active Low

The eZ80F91 device responds to

a Low on BUSREQ, by tristating

the address, data, and control

signals, and by driving the

BUSACK line Low. During bus

acknowledge cycles ADDR[23:0],

IORQ, and MREQ are inputs.

59

60

61

K7

H6

M8

V_DD

V_SS

Power Supply

Ground

Power Supply.

Ground.

RTC_X

Real-Time

Clock Crystal

Input

This pin is the input to the low-

power 32KHz crystal oscillator for

the Real-Time Clock.

IN

62

L8

RTC_X

Real-Time

Clock Crystal

Output

Bidirectional

This pin is the output from the

low-power 32KHz crystal

OUT

oscillator for the Real-Time Clock.

This pin is an input when the RTC

is configured to operate from 50/

60Hz input clock signals and the

32KHz crystal oscillator is

disabled.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

16

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

63

J7

RTC_V_DDReal-Time

Clock Power

Power supply for the Real-Time

Clock and associated 32KHz

oscillator. Isolated from the power

supply to the remainder of the

chip. A battery can be connected

to this pin to supply constant

power to the Real-Time Clock

and 32KHz oscillator.

Supply

64

65

K8

V_SS

Ground

Ground.

M9

HALT_SLP HALT and

SLEEP

Output, Active Low

A Low on this pin indicates that

the CPU has entered either HALT

or SLEEP mode because of

execution of either a HALT or

SLP instruction.

Indicator

66

67

68

69

H7

L9

J8

TMS

TCK

JTAG Test

Mode Select

Input

JTAG Mode Select Input.

JTAG Test

Clock

Input

JTAG and ZDI clock input.

TRIGOUT JTAG Test

Trigger Output

Output

Bidirectional

Active High trigger event

indicator.

K9

TDI

JTAG Test

Data In

JTAG data input pin. Functions

as ZDI data I/O pin when JTAG is

disabled.

70

71

72

M10

L10

TDO

TRST

V_SS

JTAG Test

Data Out

Output

JTAG data output pin.

JTAG Reset

Schmitt-trigger input, JTAG reset input pin.

Active Low

M11

Ground

Ground.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

17

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

73 M12

PD0

GPIO Port D Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port D

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

D is multiplexed with one UART.

TxD0

IR_TxD

PD1

UART

Transmit Data

Output

This pin is used by the UART to

transmit asynchronous serial

data. This signal is multiplexed

with PD0.

IrDA Transmit Output

Data

This pin is used by the IrDA

encoder/decoder to transmit

serial data. This signal is

multiplexed with PD0.

74

L12

GPIO Port D Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port D

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

D is multiplexed with one UART.

RxD0

Receive Data Input

This pin is used by the UART to

receive asynchronous serial data.

This signal is multiplexed with

PD1.

IR_RxD

IrDA Receive Input

Data

This pin is used by the IrDA

encoder/decoder to receive serial

data. This signal is multiplexed

with PD1.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

18

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

75

76

77

L11

K10

J9

PD2

GPIO Port D Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port D

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

D is multiplexed with one UART.

RTS0

PD3

Request to

Send

Output, Active Low

Modem control signal from

UART. This signal is multiplexed

with PD2.

GPIO Port D Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port D

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

D is multiplexed with one UART.

CTS0

PD4

Clear to Send Input, Active Low

GPIO Port D Bidirectional

Modem status signal to the

UART. This signal is multiplexed

with PD3.

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port D

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

D is multiplexed with one UART.

DTR0

Data Terminal Output, Active Low

Ready

Modem control signal to the

UART. This signal is multiplexed

with PD4.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

19

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

78

79

80

K12

K11

H8

PD5

GPIO Port D Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port D

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

D is multiplexed with one UART.

DSR0

PD6

Data Set

Ready

Input, Active Low

Modem status signal to the

UART. This signal is multiplexed

with PD5.

GPIO Port D Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port D

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

D is multiplexed with one UART.

DCD0

PD7

Data Carrier

Detect

Input, Active Low

Modem status signal to the

UART. This signal is multiplexed

with PD6.

GPIO Port D Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port D

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

D is multiplexed with one UART.

RI0

Ring Indicator Input, Active Low

Modem status signal to the

UART. This signal is multiplexed

with PD7.

81

82

J11

J12

V_DD

V_SS

Power Supply

Ground

Power Supply.

Ground.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

20

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

83

J10

LOOP_FILT PLL Loop

Filter

Analog

Loop Filter pin for the Analog

PLL.

84

85

G7

PLL_V_SS

Ground

Ground for Analog PLL.

H12

X

System Clock Output

Oscillator

Output

This pin is the output of the

onboard crystal oscillator. When

used, a crystal should be

OUT

connected between X and

IN

X

.

OUT

86

H11

X

System Clock Input

Oscillator Input

This pin is the input to the

IN

onboard crystal oscillator for the

primary system clock. If an

external oscillator is used, its

clock output should be connected

to this pin. When a crystal is

used, it should be connected

between X and X

.

IN

OUT

87

88

89

90

H10

H9

PLL_V_DD

V_DD

Power Supply

Power Supply for Analog PLL.

Power Supply.

Power Supply

G12

G11

V_SS

Ground

Ground.

PC0

GPIO Port C Bidirectional with

This pin can be used for general-

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port C

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

C is multiplexed with one UART.

TxD1

Transmit Data Output

This pin is used by the UART to

transmit asynchronous serial

data. This signal is multiplexed

with PC0.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

21

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

This pin can be used for general-

91

G10

PC1

GPIO Port C Bidirectional with

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port C

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

C is multiplexed with one UART.

RxD1

PC2

Receive Data Schmitt-trigger input This pin is used by the UART to

receive asynchronous serial data.

This signal is multiplexed with

PC1.

92

G9

GPIO Port C Bidirectional with

This pin can be used for general-

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port C

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

C is multiplexed with one UART.

RTS1

PC3

Request to

Send

Output, Active Low

Modem control signal from

UART. This signal is multiplexed

with PC2.

93

F12

GPIO Port C Bidirectional with

This pin can be used for general-

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port C

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

C is multiplexed with one UART.

CTS1

Clear to Send Schmitt-trigger input, Modem status signal to the

Active Low

UART. This signal is multiplexed

with PC3.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

22

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

This pin can be used for general-

94

95

96

F11

F10

G8

PC4

GPIO Port C Bidirectional with

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port C

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

C is multiplexed with one UART.

DTR1

PC5

Data Terminal Output, Active Low

Modem control signal to the

UART. This signal is multiplexed

with PC4.

Ready

GPIO Port C Bidirectional with

This pin can be used for general-

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port C

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

C is multiplexed with one UART.

DSR1

PC6

Data Set

Ready

Schmitt-trigger input, Modem status signal to the

Active Low

UART. This signal is multiplexed

with PC5.

GPIO Port C Bidirectional with

This pin can be used for general-

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port C

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

C is multiplexed with one UART.

DCD1

Data Carrier

Detect

Schmitt-trigger input, Modem status signal to the

Active Low

UART. This signal is multiplexed

with PC6.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

23

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

This pin can be used for general-

97

E12

PC7

GPIO Port C Bidirectional with

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port C

pin, when programmed as output,

can be selected to be an open-

drain or open-source output. Port

C is multiplexed with one UART.

RI1

Ring Indicator Schmitt-trigger input, Modem status signal to the

Active Low

UART. This signal is multiplexed

with PC7.

98

E11

F9

V_DD

V_SS

PB0

Power Supply

Ground

Power Supply.

99

Ground.

100

E10

GPIO Port B

Bidirectional with

This pin can be used for general-

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port B

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

IC0

Input Capture Schmitt-trigger input Input Capture A Signal to Timer

1. This signal is multiplexed with

PB0.

EC0

Event Counter Schmitt-trigger input Event Counter Signal to Timer 1.

This signal is multiplexed with

PB0.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

24

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

This pin can be used for general-

101 D12

PB1

GPIO Port B

Bidirectional with

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port B

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

IC1

Input Capture Schmitt-trigger input Input Capture B Signal to Timer

1. This signal is multiplexed with

PB1.

102

F8

PB2

GPIO Port B

Bidirectional with

This pin can be used for general-

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port B

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

SS

SPI Slave

Select

Schmitt-trigger input, The slave select input line is used

Active Low

to select a slave device in SPI

mode. This signal is multiplexed

with PB2.

103

D11

PB3

GPIO Port B

Bidirectional with

This pin can be used for general-

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port B

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

SCK

SPI Serial

Clock

Bidirectional with

Schmitt-trigger input multiplexed with PB3.

SPI serial clock. This signal is

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

25

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

This pin can be used for general-

104

105

106

E9

PB4

GPIO Port B

Bidirectional with

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port B

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

IC2

Input Capture Schmitt-trigger input Input Capture A Signal to Timer

3. This signal is multiplexed with

PB4.

D10

PB5

GPIO Port B

Bidirectional with

This pin can be used for general-

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port B

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

IC3

Input Capture Schmitt-trigger input Input Capture B Signal to Timer

3. This signal is multiplexed with

PB5.

C12

PB6

GPIO Port B

Bidirectional with

This pin can be used for general-

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port B

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

MISO

SPI Master In Bidirectional with

The MISO line is configured as an

Slave Out

Schmitt-trigger input input when the eZ80F91 device is

an SPI master device and as an

output when eZ80F91 is an SPI

slave device. This signal is

multiplexed with PB6.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

26

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

This pin can be used for general-

107

C11

PB7

GPIO Port B

Bidirectional with

Schmitt-trigger input purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port B

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

MOSI

SPI Master

Bidirectional with

The MOSI line is configured as an

Out Slave In

Schmitt-trigger input output when the eZ80F91 device

is an SPI master device and as

an input when the eZ80F91

device is an SPI slave device.

This signal is multiplexed with

PB7.

108

109

B12

A12

V_SS

Ground

Ground.

2

SDA

I C Serial Data Bidirectional

This pin carries the I C data

signal.

2

110

111

A11

B11

SCL

PHI

I C Serial

Clock

Bidirectional

This pin is used to receive and

transmit the I C clock.

2

System Clock Output

This pin is an output driven by the

internal system clock. It can be

used by the system for

synchronization with the eZ80F91

device.

112

113

C10

D9

V_DD

V_SS

Power Supply

Ground

Power Supply.

Ground.

Note: *PHY represents the physical layer of the OSI model.

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Architectural Overview

eZ80F91 MCU

Product Specification

27

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

114 A10

PA0

GPIO Port A

Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port A

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

PWM0

OC0

PWM Output 0 Output

This pin is used by Timer 3 for

PWM 0. This signal is multiplexed

with PA0.

Output

This pin is used by Timer 3 for

Output Compare 0. This signal is

multiplexed with PA0.

Compare 0

115

B10

PA1

GPIO Port A

Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port A

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

PWM1

OC1

PWM Output 1 Output

This pin is used by Timer 3 for

PWM 1. This signal is multiplexed

with PA1.

Output

This pin is used by Timer 3 for

Output Compare 1. This signal is

multiplexed with PA1.

Compare 1

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

28

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

116 E8

PA2

GPIO Port A

Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port A

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

PWM2

OC2

PWM Output 2 Output

This pin is used by Timer 3 for

PWM 2. This signal is multiplexed

with PA2.

Output

This pin is used by Timer 3 for

Output Compare 2. This signal is

multiplexed with PA2.

Compare 2

117

B9

PA3

GPIO Port A

Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port A

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

PWM3

OC3

PWM Output 3 Output

This pin is used by Timer 3 for

PWM 3. This signal is multiplexed

with PA3.

Output

This pin is used by Timer 3 for

Output Compare 3 This signal is

multiplexed with PA3.

Compare 3

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

29

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

118 A9

PA4

GPIO Port A

Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port A

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

PWM0

TOUT0

PA5

PWM Output 0 Output

Inverted

This pin is used by Timer 3 for

Negative PWM 0. This signal is

multiplexed with PA4.

Timer Out

Output

This pin is used by Timer 0 timer-

out signal. This signal is

multiplexed with PA4.

119

C9

GPIO Port A

Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port A

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

PWM1

TOUT1

PWM Output 1 Output

Inverted

This pin is used by Timer 3 for

Negative PWM 1. This signal is

multiplexed with PA5.

Timer Out

Output

This pin is used by Timer 1 timer-

out signal. This signal is

multiplexed with PA5.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

30

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

120 F7

PA6

GPIO Port A

Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port A

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

PWM2

EC1

PWM Output 2 Output

Inverted

This pin is used by Timer 3 for

Negative PWM 2. This signal is

multiplexed with PA6.

Event Counter Input

Event Counter Signal to Timer 2.

This signal is multiplexed with

PA6.

121

A8

PA7

GPIO Port A

Bidirectional

This pin can be used for general-

purpose I/O. It can be individually

programmed as input or output

and can also be used individually

as an interrupt input. Each Port A

pin, when programmed as output,

can be selected to be an open-

drain or open-source output.

PWM3

PWM Output 3 Output

Inverted

This pin is used by Timer 3 for

Negative PWM 3. This signal is

multiplexed with PA7.

122

123

124

B8

C8

D8

V_DD

V_SS

CRS

Power Supply

Ground

Power Supply.

Ground.

MII Carrier

Sense

Input

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY*. Carrier Sense is an

asynchronous signal.

125

A7

COL

MII Collision

Detect

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Collision Detect is an

asynchronous signal.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

31

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

126

127

128

129

130

131

132

B7

C7

D7

A6

B6

C6

E7

TxD3

MII Transmit

Data

Output

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Transmit Data is

synchronous to the rising-edge of

Tx_CLK.

TxD2

MII Transmit

Data

Output

Input

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Transmit Data is

synchronous to the rising-edge of

Tx_CLK.

TxD1

MII Transmit

Data

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Transmit Data is

synchronous to the rising-edge of

Tx_CLK.

TxD0

MII Transmit

Data

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Transmit Data is

synchronous to the rising-edge of

Tx_CLK.

Tx_EN

Tx_CLK

Tx_ER

MII Transmit

Enable

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Transmit Enable is

synchronous to the rising-edge of

Tx_CLK.

MII Transmit

Clock

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Transmit Clock is the

Nibble or Symbol Clock provided

by the MII PHY Interface.

MII Transmit

Error

Output

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Transmit Error is

synchronous to the rising-edge of

Tx_CLK.

133

134

A5

B5

V_DD

V_SS

Power Supply

Ground

Power Supply.

Ground.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

32

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

135

D6

Rx_ER

MII Receive

Error

Input

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Receive Error is provided

by the MII PHY Interface

synchronous to the rising-edge of

Rx_CLK.

136

137

C5

A4

Rx_CLK

Rx_DV

MII Receive

Clock

Input

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Receive Clock is the Nibble

or Symbol Clock provided by the

MII PHY Interface.

MII Receive

Data Valid

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Receive Data Valid is

provided by the MII PHY Interface

synchronous to the rising-edge of

Rx_CLK.

138

139

140

E6

B4

D5

RxD0

RxD1

RxD2

MII Receive

Data

Input

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Receive Data is provided

by the MII PHY Interface

synchronous to the rising-edge of

Rx_CLK.

MII Receive

Data

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Receive Data is provided

by the MII PHY Interface

synchronous to the rising-edge of

Rx_CLK.

MII Receive

Data

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Receive Data is provided

by the MII PHY Interface

synchronous to the rising-edge of

Rx_CLK.

Note: *PHY represents the physical layer of the OSI model.

PS019209-0504

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Architectural Overview

eZ80F91 MCU

Product Specification

33

Table 2. Pin Identification on the eZ80F91 Device (Continued)

LQFP BGA

Pin # Pin#

Symbol

Function

Signal Direction

Description

141

142

143

C4

A3

B3

RxD3

MII Receive

Data

Input

This pin is used by the Ethernet

MAC for the MII Interface to the

PHY. Receive Data is provided

by the MII PHY Interface

synchronous to the rising-edge of

Rx_CLK.

MDC

MII

Output

This pin is used by the Ethernet

MAC for the MII Management

Interface to the PHY. The

Ethernet MAC provides the MII

Management Data Clock to the

MII PHY Interface.

Management

Data Clock

MDIO

MII

Bidirectional

This pin is used by the Ethernet

MAC for the MII Management

Interface to the PHY. The

Ethernet MAC sends and

receives the MII Management

Data to and from the MII PHY

Interface.

Management

Data

144

A2

WP

Write Protect Schmitt-trigger input, The Write Protect input is used by

Active Low

the Flash Controller to protect the

Boot Block from Write and

ERASE operations.

Note: *PHY represents the physical layer of the OSI model.

System Clock Source Options

System Clock. The eZ80F91 device’s internal clock, SCLK, is responsible for

clocking all internal logic. The SCLK source can be an external crystal oscillator,

an internal PLL, or an internal 32kHz RTC oscillator. The SCLK source is selected

by PLL Control Register 0. RESET default is provided by the external crystal oscil-

lator. Refer to the CLK_MUX values in the PLL Control Register 0, Table 207 on

page 325 for details.

PHI. PHI is a device output driven by SCLK that can be used for system synchro-

nization to the eZ80F91 device. PHI is used as the reference clock for all AC

Characteristics.

External Crystal Oscillator. An externally-driven oscillator that can operate in two

modes. In one mode, the X pin can be driven by a can oscillator from DC up to

IN

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Architectural Overview

eZ80F91 MCU

Product Specification

34

50Mhz while the X

pin is unconnected. In the other mode, the X and X

IN OUT

OUT

pins can be driven by a crystal circuit.

Crystals recommended by ZiLOG are defined to be a 50Mhz–3 overtone circuit or

1–10MHz range fundamental for PLL operation. For details, refer to the On-Chip

Oscillators section on page 342.

Real Time Clock. An internal 32KHz real-time clock crystal oscillator driven by

either the on-chip 32768Hz crystal oscillator or a 50/60Hz power-line frequency

input. While intended for timekeeping, the RTC 32KHz oscillator can be selected

as an SCLK. RTC_V_DDand RTC_V_SSprovide an isolated power supply to ensure

RTC operation in the event of loss of line power when a battery is provided. For

details, refer to the On-Chip Oscillators section on page 342.

PLL Clock. The eZ80F91 internal PLL driven by external crystals or can oscillators

in the 1MHz to 10MHz range to generate an SCLK up to 50MHz. For details, refer

to the Phase-Locked Loop section on page 320.

SCLK Source Selection Example

If an application must run the eZ80F91 device at 40MHz, the following solutions

are possible:

•

Use a 40MHz–3rd overtone crystal (not recommended due to its weak funda-

mental rating)

•

Use a 40MHz can oscillator (expensive)

Use an 8MHz fundamental two-pin crystal and program the internal PLL with

a multiplier of five to achieve 40MHz (inexpensive).

PS019209-0504

P R E L I M I N A R Y

Architectural Overview

eZ80F91 MCU

Product Specification

35

Register Map

All on-chip peripheral registers are accessed in the I/O address space. All I/O

operations employ 16-bit addresses. The upper byte of the 24-bit address bus is

undefined during all I/O operations (ADDR[23:16] = UU). All I/O operations using

16-bit addresses within the range 0000h–00FFhare routed to the on-chip periph-

erals. External I/O Chip Selects are not generated if the address space pro-

grammed for the I/O Chip Selects overlaps the 0000h–00FFhaddress range.

Registers at unused addresses within the 0000h–00FFhrange assigned to on-

chip peripherals are not implemented. Read access to such addresses returns

unpredictable values and Write access produces no effect. Table 3 diagrams the

register map for the eZ80F91 device.

Table 3. Register Map

Address

(hex)

Reset

(hex)

CPU

Access

Page

#

Mnemonic

Name

Product ID

0000

0001

0002

ZDI_ID_L

eZ80 Product ID Low Byte Register

eZ80 Product ID High Byte Register

eZ80 Product ID Revision Register

08

00

XX

R

305

306

ZDI_ID_H

ZDI_ID_REV

Interrupt Priority

0010

0011

0012

0013

0014

0015

Notes:

INT_P0

INT_P1

INT_P2

INT_P3

INT_P4

INT_P5

Interrupt Priority Register—Byte 0

Interrupt Priority Register—Byte 1

Interrupt Priority Register—Byte 2

Interrupt Priority Register—Byte 3

Interrupt Priority Register—Byte 4

Interrupt Priority Register—Byte 5

00

R/W

69

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

36

Table 3. Register Map (Continued)

Address

Reset

(hex)

CPU

Access

Page

#

(hex)

Mnemonic

Name

Ethernet Media Access Controller

0020

0021

0022

0023

0024

0025

0026

0027

0028

0029

002A

002B

EMAC_TEST

EMAC Test Register

00

37

0F

00

R/W

249

251

253

254

255

256

257

EMAC_CFG1

EMAC Configuration Register

EMAC Station Address—Byte 0

EMAC Station Address—Byte 1

EMAC Station Address—Byte 2

EMAC Station Address—Byte 3

EMAC Station Address—Byte 4

EMAC Station Address—Byte 5

EMAC_CFG2

EMAC_CFG3

EMAC_CFG4

EMAC_STAD_0

EMAC_STAD_1

EMAC_STAD_2

EMAC_STAD_3

EMAC_STAD_4

EMAC_STAD_5

EMAC_TPTV_L

EMAC Transmit Pause Timer Value—

Low Byte

002C

EMAC_TPTV_H

EMAC Transmit Pause Timer Value—

High Byte

00

R/W

257

002D

002E

002F

0030

EMAC_IPGT

EMAC Inter-Packet Gap

EMAC Non-Back-Back IPG

15

0C

12

00

R/W

258

260

261

EMAC_IPGR1

EMAC_IPGR2

EMAC_MAXF_L

EMAC Maximum Frame Length—Low

Byte

0031

EMAC_MAXF_H

EMAC Maximum Frame Length—High

Byte

06

R/W

262

0032

0033

Notes:

EMAC_AFR

EMAC Address Filter Register

EMAC Hash Table—Byte 0

00

R/W

263

264

EMAC_HTBL_0

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

37

Table 3. Register Map (Continued)

Address

Reset

(hex)

CPU

Access

Page

#

(hex)

Mnemonic

Name

Ethernet Media Access Controller, continued

0034

0035

0036

0037

0038

0039

003A

003B

003C

EMAC_HTBL_1

EMAC_HTBL_2

EMAC_HTBL_3

EMAC_HTBL_4

EMAC_HTBL_5

EMAC_HTBL_6

EMAC_HTBL_7

EMAC_MIIMGT

EMAC_CTLD_L

EMAC Hash Table—Byte 1

EMAC Hash Table—Byte 2

EMAC Hash Table—Byte 3

EMAC Hash Table—Byte 4

EMAC Hash Table—Byte 5

EMAC Hash Table—Byte 6

EMAC Hash Table—Byte 7

EMAC MII Management Register

00

R/W

264

265

266

EMAC PHY Configuration Data—Low

Byte

003D

EMAC_CTLD_H

EMAC PHY Configuration Data—High

Byte

00

R/W

267

003E

003F

EMAC_RGAD

EMAC_FIAD

EMAC PHY Register Address Register

00

R/W

267

268

EMAC PHY Unit Select Address

Register

0040

0041

0042

EMAC_PTMR

EMAC_RST

EMAC Transmit Polling Timer Register

EMAC Reset Control Register

00

R/W

268

269

270

EMAC_TLBP_L

EMAC Transmit Lower Boundary

Pointer—Low Byte

0043

EMAC_TLBP_H

EMAC Transmit Lower Boundary

Pointer—High Byte

00

R/W

270

0044

0045

0046

Notes:

EMAC_BP_L

EMAC_BP_H

EMAC_BP_U

EMAC Boundary Pointer—Low Byte

EMAC Boundary Pointer—High Byte

EMAC Boundary Pointer—Upper Byte

00

C0

FF

R/W

271

272

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

38

Table 3. Register Map (Continued)

Address

Reset

(hex)

CPU

Access

Page

#

(hex)

Mnemonic

Name

Ethernet Media Access Controller, continued

0047

0048

0049

004A

EMAC_RHBP_L

EMAC_RHBP_H

EMAC_RRP_L

EMAC_RRP_H

EMAC Receive High Boundary

Pointer—Low Byte

00

R/W

272

273

274

EMAC Receive High Boundary

Pointer—High Byte

EMAC Receive Read Pointer—Low

Byte

EMAC Receive Read Pointer—High

Byte

004B

004C

004D

004E

EMAC_BUFSZ

EMAC_IEN

EMAC Buffer Size Register

00

R/W

274

275

277

278

EMAC Interrupt Enable Register

EMAC Interrupt Status Register

EMAC_ISTAT

EMAC_PRSD_L

EMAC PHY Read Status Data—Low

Byte

004F

EMAC_PRSD_H

EMAC PHY Read Status Data—High

Byte

00

R/W

279

0050

0051

EMAC_MIISTAT

EMAC_RWP_L

EMAC MII Status Register

00

R/W

279

280

EMAC Receive Write Pointer—Low

Byte

0052

0053

0054

0055

Notes:

EMAC_RWP_H

EMAC_TRP_L

EMAC_TRP_H

EMAC Receive Write Pointer—High

Byte

00

R/W

281

282

EMAC Transmit Read Pointer—Low

Byte

EMAC Transmit Read Pointer—High

Byte

EMAC_BLKSLFT_L EMAC Receive Blocks Left Register—

Low Byte

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

39

Table 3. Register Map (Continued)

Address

Reset

(hex)

CPU

Access

Page

#

(hex)

Mnemonic

Name

Ethernet Media Access Controller, continued

0056

EMAC_BLKSLFT_H EMAC Receive Blocks Left Register—

High Byte

00

R/W

283

0057

0058

0059

EMAC_FDATA_L

EMAC_FDATA_H

EMAC_FFLAGS

EMAC FIFO Data—Low Byte

EMAC FIFO Data—High Byte

EMAC FIFO Flags Register

0X

XX

33

R/W

284

285

PLL

005C

005D

005E

005F

PLL_DIV_L

PLL_DIV_H

PLL_CTL0

PLL_CTL1

PLL Divider Register—Low Byte

PLL Divider Register—High Byte

PLL Control Register 0

00

W

324

325

326

R/W

PLL Control Register 1

Timers and PWM

0060

0061

0062

0063

TMR0_CTL

Timer 0 Control Register

00

R/W

R

138

139

141

142

143

144

138

139

141

142

143

TMR0_IER

TMR0_IIR

Timer 0 Interrupt Enable Register

Timer 0 Interrupt Identification Register

Timer 0 Data Register—Low Byte

Timer 0 Reload Register—Low Byte

Timer 0 Data Register—High Byte

Timer 0 Reload Register—High Byte

Timer 1 Control Register

00

TMR0_DR_L

TMR0_RR_L

TMR0_DR_H

TMR0_RR_H

TMR1_CTL

TMR1_IER

TMR1_IIR

XX

00

W

0064

R

W

0065

0066

0067

0068

R/W

R

Timer 1 Interrupt Enable Register

Timer 1 Interrupt Identification Register

Timer 1 Data Register—Low Byte

Timer 1 Reload Register—Low Byte

00

TMR1_DR_L

TMR1_RR_L

XX

W

Notes:

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

40

Table 3. Register Map (Continued)

Address

Reset

(hex)

CPU

Access

Page

#

(hex)

Mnemonic

Name

Timers and PWM, continued

0069

TMR1_DR_H

Timer 1 Data Register—High Byte

Timer 1 Reload Register—High Byte

Timer 1 Input Capture Control Register

XX

R

143

144

145

TMR1_RR_H

W

006A

006B

TMR1_CAP_CTL

TMR1_CAPA_L

R/W

Timer 1 Capture Value A Register—

Low Byte

006C

006D

006E

TMR1_CAPA_H

TMR1_CAPB_L

TMR1_CAPB_H

Timer 1 Capture Value A Register—

High Byte

XX

R/W

146

147

Timer 1 Capture Value B Register—

Low Byte

Timer 1 Capture Value B Register—

High Byte

006F

0070

0071

0072

TMR2_CTL

TMR2_IER

TMR2_IIR

Timer 2 Control Register

00

R/W

R

138

139

141

142

143

144

138

139

141

142

143

Timer 2 Interrupt Enable Register

Timer 2 Interrupt Identification Register

Timer 2 Data Register—Low Byte

Timer 2 Reload Register—Low Byte

Timer 2 Data Register—High Byte

Timer 2 Reload Register—High Byte

Timer 3 Control Register

00

TMR2_DR_L

TMR2_RR_L

TMR2_DR_H

TMR2_RR_H

TMR3_CTL

TMR3_IER

TMR3_IIR

XX

00

W

0073

R

W

0074

0075

0076

0077

R/W

R

Timer 3 Interrupt Enable Register

Timer 3 Interrupt Identification Register

Timer 3 Data Register—Low Byte

Timer 3 Reload Register—Low Byte

00

TMR3_DR_L

TMR3_RR_L

XX

W

Notes:

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

41

Table 3. Register Map (Continued)

Address

Reset

(hex)

CPU

Access

Page

#

(hex)

Mnemonic

Name

Timers and PWM, continued

0078

TMR3_DR_H

TMR3_RR_H

PWM_CTL1

PWM_CTL2

PWM_CTL3

TMR3_CAP_CTL

PWM0R_L

Timer 3 Data Register—High Byte

Timer 3 Reload Register—High Byte

PWM Control Register 1

XX

00

XX

R

143

144

158

159

161

144

162

W

0079

007A

007B

R/W

PWM Control Register 2

PWM Control Register 3

Timer 3 Input Capture Control Register

007C

007D

007E

007F

0080

Notes:

PWM 0 Rising-Edge Register—Low

Byte

TMR3_CAPA_L

PWM0R_H

Timer 3 Capture Value A Register—

Low Byte

XX

00

R/W

145

163

146

162

146

163

147

162

138

PWM 0 Rising-Edge Register—High

Byte

TMR3_CAPA_H

PWM1R_L

Timer 3 Capture Value A Register—

High Byte

PWM 1 Rising-Edge Register—Low

Byte

TMR3_CAPB_L

PWM1R_H

Timer 3 Capture Value B Register—

Low Byte

PWM 1 Rising-Edge Register—High

Byte

TMR3_CAPB_H

PWM2R_L

Timer 3 Capture Value B Register—

High Byte

PWM 2 Rising-Edge Register—Low

Byte

TMR3_OC_CTL1

Timer 3 Output Compare Control

Register 1

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

42

Table 3. Register Map (Continued)

Address

Reset

(hex)

CPU

Access

Page

#

(hex)

Mnemonic

Name

Timers and PWM, continued

0081

0082

0083

0084

0085

0086

Notes:

PWM2R_H

PWM 2 Rising-Edge Register—High

Byte

XX

00

R/W

163

138

162

149

163

150

164

149

165

150

164

149

TMR3_OC_CTL2

PWM3R_L

Timer 3 Output Compare Control

Register 2

PWM 3 Rising-Edge Register—Low

Byte

XX

TMR3_OC0_L

PWM3R_H

Timer 3 Output Compare 0 Value

Register—Low Byte

PWM 3 Rising-Edge Register—High

Byte

TMR3_OC0_H

PWM0F_L

Timer 3 Output Compare 0 Value

Register—High Byte

PWM 0 Falling-Edge Register—Low

Byte

TMR3_OC1_L

PWM0F_H

Timer 3 Output Compare 1 Value

Register—Low Byte

PWM 0 Falling-Edge Register—High

Byte

TMR3_OC1_H

PWM1F_L

Timer 3 Output Compare 1 Value

Register—High Byte

PWM 1 Falling-Edge Register—Low

Byte

TMR3_OC2_L

Timer 3 Output Compare 2 Value

Register—Low Byte

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

43

Table 3. Register Map (Continued)

Address

Reset

(hex)

CPU

Access

Page

#

(hex)

Mnemonic

Name

Timers and PWM, continued

0087

0088

0089

PWM1F_H

PWM 1 Falling-Edge Register—High

Byte

XX

R/W

165

150

164

149

165

150

164

165

TMR3_OC2_H

PWM2F_L

Timer 3 Output Compare 2 Value

Register—High Byte

PWM 2 Falling-Edge Register—Low

Byte

TMR3_OC3_L

PWM2F_H

Timer 3 Output Compare 3 Value

Register—Low Byte

PWM 2 Falling-Edge Register—High

Byte

TMR3_OC3_H

PWM3F_L

Timer 3 Output Compare 3 Value

Register—High Byte

008A

008B

PWM 3 Falling-Edge Register—Low

Byte

PWM3F_H

PWM 3 Falling-Edge Register—High

Byte

Watch-Dog Timer

1

0093

0094

WDT_CTL

WDT_RR

Watch-Dog Timer Control Register

Watch-Dog Timer Reset Register

00/20

XX

R/W

W

124

126

General-Purpose Input/Output Ports

2

0096

0097

0098

0099

009A

Notes:

PA_DR

Port A Data Register

XX

FF

00

XX

R/W

63

64

63

PA_DDR

PA_ALT1

PA_ALT2

PB_DR

Port A Data Direction Register

Port A Alternate Register 1

Port A Alternate Register 2

Port B Data Register

R/W

2

R/W

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

44

Table 3. Register Map (Continued)

Address

Reset

(hex)

CPU

Access

Page

#

(hex)

Mnemonic

Name

General-Purpose Input/Output Ports, continued

009B

009C

009D

009E

009F

00A0

00A1

00A2

00A3

00A4

00A5

PB_DDR

PB_ALT1

PB_ALT2

PC_DR

Port B Data Direction Register

Port B Alternate Register 1

Port B Alternate Register 2

Port C Data Register

FF

00

XX

FF

00

XX

FF

00

R/W

63

64

63

64

63

64

2

R/W

PC_DDR

PC_ALT1

PC_ALT2

PD_DR

Port C Data Direction Register

Port C Alternate Register 1

Port C Alternate Register 2

Port D Data Register

R/W

2

R/W

PD_DDR

PD_ALT1

PD_ALT2

Port D Data Direction Register

Port D Alternate Register 1

Port D Alternate Register 2

R/W

Chip Select/Wait State Generator

00A8

00A9

00AA

00AB

00AC

00AD

00AE

00AF

00B0

00B1

Notes:

CS0_LBR

CS0_UBR

CS0_CTL

CS1_LBR

CS1_UBR

CS1_CTL

CS2_LBR

CS2_UBR

CS2_CTL

CS3_LBR

Chip Select 0 Lower Bound Register

Chip Select 0 Upper Bound Register

Chip Select 0 Control Register

00

FF

E8

00

R/W

93

94

95

93

94

95

93

94

95

93

Chip Select 1 Lower Bound Register

Chip Select 1 Upper Bound Register

Chip Select 1 Control Register

Chip Select 2 Lower Bound Register

Chip Select 2 Upper Bound Register

Chip Select 2 Control Register

Chip Select 3 Lower Bound Register

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

45

Table 3. Register Map (Continued)

Address

Reset

(hex)

CPU

Access

Page

#

(hex)

Mnemonic

Name

Chip Select/Wait State Generator, continued

00B2

00B3

CS3_UBR

CS3_CTL

Chip Select 3 Upper Bound Register

Chip Select 3 Control Register

00

R/W

94

95

Random Access Memory Control

00B4

00B5

00B6

00B7

RAM_CTL

RAM Control Register

80

FF

00

R/W

102

103

104

RAM_ADDR_U

MBIST_GPR

MBIST_EMR

RAM Address Upper Byte Register

General Purpose RAM MBIST Control

Ethernet MAC RAM MBIST Control

Serial Peripheral Interface

00B8

SPI_BRG_L

SPI Baud Rate Generator Register—

Low Byte

02

00

R/W

215

00B9

SPI_BRG_H

SPI Baud Rate Generator Register—

High Byte

00BA

00BB

00BC

SPI_CTL

SPI_SR

SPI Control Register

04

00

R/W

R

216

217

218

SPI Status Register

SPI_TSR

SPI_RBR

SPI Transmit Shift Register

SPI Receive Buffer Register

XX

W

R

Infrared Encoder/Decoder

00BF IR_CTL

Infrared Encoder/Decoder Control

00

R/W

207

Universal Asynchronous Receiver/Transmitter 0 (UART0)

00C0

UART0_RBR

UART0_THR

UART0_BRG_L

UART 0 Receive Buffer Register

UART 0 Transmit Holding Register

XX

02

R

W

192

191

190

UART 0 Baud Rate Generator

Register—Low Byte

R/W

Notes:

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

46

Table 3. Register Map (Continued)

Address

Reset

(hex)

CPU

Access

Page

#

(hex)

Mnemonic

Name

Universal Asynchronous Receiver/Transmitter 0 (UART0), continued

00C1

00C2

UART0_IER

UART 0 Interrupt Enable Register

00

R/W

192

190

UART0_BRG_H

UART 0 Baud Rate Generator

Register—High Byte

UART0_IIR

UART 0 Interrupt Identification

Register

01

R

193

UART0_FCTL

UART0_LCTL

UART0_MCTL

UART0_LSR

UART0_MSR

UART0_SPR

UART 0 FIFO Control Register

UART 0 Line Control Register

UART 0 Modem Control Register

UART 0 Line Status Register

UART 0 Modem Status Register

UART 0 Scratch Pad Register

00

60

XX

00

W

R/W

R

195

196

198

200

202

203

00C3

00C4

00C5

00C6

00C7

R

R/W

2

I C

2

00C8

00C9

00CA

00CB

00CC

I2C_SAR

I2C_XSAR

I2C_DR

I C Slave Address Register

00

F8

00

XX

R/W

R

232

233

235

236

238

239

2

I C Extended Slave Address Register

2

I C Data Register

2

I2C_CTL

I2C_SR

I C Control Register

2

I C Status Register

2

I2C_CCR

I2C_SRR

I C Clock Control Register

W

2

00CD

Notes:

I C Software Reset Register

W

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

47

Table 3. Register Map (Continued)

Address

Reset

(hex)

CPU

Access

Page

#

(hex)

Mnemonic

Name

Universal Asynchronous Receiver/Transmitter 1 (UART1)

00D0

UART1_RBR

UART1_THR

UART1_BRG_L

UART 1 Receive Buffer Register

UART 1 Transmit Holding Register

XX

02

R

W

192

191

190

UART 1 Baud Rate Generator

Register—Low Byte

R/W

00D1

00D2

UART1_IER

UART 1 Interrupt Enable Register

00

R/W

192

190

UART1_BRG_H

UART 1 Baud Rate Generator

Register—High Byte

UART1_IIR

UART 1 Interrupt Identification

Register

01

R

193

UART1_FCTL

UART1_LCTL

UART1_MCTL

UART1_LSR

UART1_MSR

UART1_SPR

UART 1 FIFO Control Register

UART 1 Line Control Register

UART 1 Modem Control Register

UART 1 Line Status Register

UART 1 Modem Status Register

UART 1 Scratch Pad Register

00

60

XX

00

W

195

196

198

200

202

203

00D3

00D4

00D5

00D6

00D7

R/W

Low-Power Control

00DB

CLK_PPD1

Clock Peripheral Power-Down Register

1

00

R/W

56

57

00DC

CLK_PPD2

Clock Peripheral Power-Down Register

2

Real-Time Clock

3

00E0

00E1

00E2

Notes:

RTC_SEC

RTC Seconds Register

RTC Minutes Register

RTC Hours Register

XX

R/W

168

169

170

3

RTC_MIN

RTC_HRS

R/W

3

R/W

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

48

Table 3. Register Map (Continued)

Address

Reset

(hex)

CPU

Access

Page

#

(hex)

Mnemonic

Name

Real-Time Clock, continued

3

00E3

00E4

00E5

00E6

00E7

00E8

00E9

00EA

00EB

00EC

00ED

RTC_DOW

RTC_DOM

RTC_MON

RTC_YR

RTC Day-of-the-Week Register

RTC Day-of-the-Month Register

RTC Month Register

0X

XX

0X

00

R/W

171

172

173

174

175

176

177

178

179

180

181

3

R/W

3

R/W

3

RTC Year Register

R/W

3

RTC_CEN

RTC_ASEC

RTC_AMIN

RTC_AHRS

RTC_ADOW

RTC_ACTRL

RTC_CTRL

RTC Century Register

R/W

RTC Alarm Seconds Register

RTC Alarm Minutes Register

RTC Alarm Hours Register

RTC Alarm Day-of-the-Week Register

RTC Alarm Control Register

RTC Control Register

R/W

x0xxxx00

b/

x0xxxx10

4

b

Chip Select Bus Mode Control

00F0

00F1

00F2

00F3

CS0_BMC

CS1_BMC

CS2_BMC

CS3_BMC

Chip Select 0 Bus Mode Control

Register

02

R/W

96

Chip Select 1 Bus Mode Control

Register

Chip Select 2 Bus Mode Control

Register

Chip Select 3 Bus Mode Control

Register

Flash Memory Control

00F5

FLASH_KEY

Flash Key Register

00

W

110

Notes:

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

49

Table 3. Register Map (Continued)

Address

Reset

(hex)

CPU

Access

Page

#

(hex)

Mnemonic

Name

Flash Memory Control, continued

00F6

00F7

00F8

00F9

00FA

00FB

00FC

00FD

00FE

00FF

Notes:

FLASH_DATA

FLASH_ADDR_U

FLASH_CTL

Flash Data Register

XX

00

88

01

FF

00

R/W

111

112

113

114

115

116

118

119

120

Flash Address Upper Byte Register

Flash Control Register

5

FLASH_FDIV

FLASH_PROT

FLASH_IRQ

Flash Frequency Divider Register

Flash Write/Erase Protection Register

Flash Interrupt Control Register

Flash Page Select Register

Flash Row Select Register

R/W

5

R/W

FLASH_PAGE

FLASH_ROW

FLASH_COL

FLASH_PGCTL

Flash Column Select Register

Flash Program Control Register

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC is locked; Read/Write if RTC is unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After a

an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

PS019209-0504

P R E L I M I N A R Y

Register Map

eZ80F91 MCU

Product Specification

50

®

eZ80 CPU Core

®

The eZ80 CPU is the first 8-bit CPU to support 16MB linear addressing. Each

software module or task under a real-time executive or operating system can

operate in Z80-compatible (64KB) mode or full 24-bit (16MB) address mode.

The CPU instruction set is a superset of the instruction sets for the Z80™ and

®

Z180™ CPUs. Z80 and Z180 programs can be executed on an eZ80 CPU with

little or no modification.

Features

•

Code-compatible with Z80 and Z180 products

24-bit linear address space

•

Single-cycle instruction fetch

Pipelined fetch, decode, and execute

Dual Stack Pointers for ADL (24-bit) and Z80 (16-bit) memory modes

24-bit CPU registers and ALU (Arithmetic Logic Unit)

Debug support

Nonmaskable Interrupt (NMI), plus support for 128 maskable vectored inter-

rupts

New Instructions

•

Loads/unloads the I register with a 16-bit value. These new instructions are:

–

LD I,HL (ED C7)

LD HL,I (ED D7)

For more information on the CPU, its instruction set, and eZ80 programming,

please refer to the eZ80 CPU User Manual (UM0077), available on zilog.com.

®

PS019209-0504

P R E L I M I N A R Y

eZ80 CPU Core

eZ80F91 MCU

Product Specification

51

Reset

Reset Operation

The Reset controller within the eZ80F91 device features a consistent reset func-

tion for all types of resets that can affect the system. A system reset, referred to in

this document as RESET, returns the eZ80F91 to a defined state. All internal reg-

isters affected by a RESET return to their default conditions. RESET configures

the GPIO port pins as inputs and clears the CPU’s Program Counter to 000000h.

Program code execution ceases during RESET.

The events that can cause a RESET are:

•

Power-On Reset (POR)

Low-voltage brown-out (VBO)

External RESET pin assertion

Watch-Dog Timer (WDT) time-out when configured to generate a RESET

Real-Time Clock alarm with the CPU in low-power SLEEP mode

Execution of a Debug RESET command

During RESET, an internal RESET mode timer holds the system in RESET for

1025 system clock (SCLK) cycles to allow sufficient time for the primary crystal

oscillator to stabilize. For internal RESET sources, the RESET mode timer begins

incrementing on the next rising edge of SCLK following deactivation of the signal

that is initiating the RESET event. For external RESET pin assertion, the RESET

mode timer begins on the next rising edge of SCLK following assertion of the

RESET pin for three consecutive SCLK cycles.

The default clock source for SCLK on RESET is the crystal input (X ). Refer to

Note:

IN

the CLK_MUX values in the PLL Control Register 0, Table 207 on page 325.

External Reset Input and Indicator

The eZ80F91 RESET pin functions as both an open-drain (active Low) RESET

mode indicator and as an active Low RESET input. When a RESET event occurs,

the internal circuitry begins driving the RESET pin Low. The RESET pin is held

Low by the internal circuitry until the internal RESET mode timer times out. If the

external reset signal is released prior to the end of the 1025-count time-out, pro-

gram execution begins following the RESET mode time-out. If the external reset

signal is released after the end of the 1025 count time-out, then program execu-

tion begins following release of the RESET input (the RESET pin is High for four

consecutive SCLK cycles).

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Power-On Reset

A Power-On Reset (POR) occurs each time the supply voltage to the part rises

from below the voltage brown-out threshold (V ) to above the POR voltage

VBO

threshold (V

). The internal bandgap-referenced voltage detector sends a con-

POR

tinuous RESET signal to the Reset controller until the supply voltage (V

)

CC

exceeds the POR voltage threshold. After V_CCrises above V

, an on-chip ana-

POR

log delay element briefly maintains the RESET signal to the Reset controller. After

this analog delay element times out, the Reset controller holds the eZ80F91 in

RESET until the RESET mode timer expires. POR operation is illustrated in

Figure 3. The signals in Figure 3 are not drawn to scale, but are for illustration pur-

poses only.

V

= 3.3V

CC

V

POR

V

VBO

Program Execution

V

= 0.0V

CC

System Clock

Oscillator

Startup

Internal RESET

Signal

T

RESET mode timer delay

ANA

Figure 3. Power-On Reset Operation

Voltage Brown-Out Reset

If, after program execution begins, the supply voltage (V ) drops below the volt-

CC

age brown-out threshold (V

), the eZ80F91 device resets. The VBO protection

VBO

circuitry detects the low supply voltage and initiates a RESET via the Reset con-

troller. The eZ80F91 remains in RESET until the supply voltage again returns

above the POR voltage threshold (V

) and the Reset controller releases the

POR

internal RESET signal. The VBO circuitry rejects very short negative brown-out

pulses to prevent spurious RESET events.

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VBO operation is illustrated in Figure 4. The signals in the figure are not drawn to

scale, and are for illustration purposes only.

V

= 3.3V

V

= 3.3V

CC

V

POR

V

VBO

Voltage

Brown-out

Program Execution

System Clock

Internal RESET

Signal

RESET mode

timer delay

T

ANA

Figure 4. Voltage Brown-Out Reset Operation

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Low Power Modes

Overview

The eZ80F91 device provides a range of power-saving features. The highest level

of power reduction is provided by SLEEP mode. The next level of power reduction

is provided by the HALT instruction. The most basic level of power reduction is

provided by the clock peripheral power-down registers.

SLEEP Mode

Execution of the CPU’s SLP instruction places the eZ80F91 device into SLEEP

mode. In SLEEP mode, the operating characteristics are:

•

The primary crystal oscillator is disabled

The system clock is disabled

The CPU is idle

The Program Counter (PC) stops incrementing

The 32KHz crystal oscillator continues to operate and drive the Real-Time

Clock and the Watch-Dog Timer (if WDT is configured to operate from the

32KHz oscillator)

The CPU can be brought out of SLEEP mode by any of the following operations:

•

A RESET via the external RESET pin driven Low

A RESET via a Real-Time Clock alarm

A RESET via a Watch-Dog Timer time-out (if running off of the 32KHz oscilla-

tor and configured to generate a RESET upon time-out)

•

A RESET via execution of a Debug RESET command

After exiting SLEEP mode, the standard RESET delay occurs to allow the primary

crystal oscillator to stabilize. Refer to the Reset section on page 51 for more infor-

mation.

HALT Mode

Execution of the CPU’s HALT instruction places the eZ80F91 device into HALT

mode. In HALT mode, the operating characteristics are:

•

The primary crystal oscillator is enabled and continues to operate

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•

The system clock is enabled and continues to operate

The CPU is idle

The Program Counter (PC) stops incrementing

The CPU can be brought out of HALT mode by any of the following operations:

•

A nonmaskable interrupt (NMI)

A maskable interrupt

A RESET via the external RESET pin driven Low

A Watch-Dog Timer time-out (if configured to generate either an NMI or

RESET upon time-out)

•

A RESET via execution of a Debug RESET command

To minimize current in HALT mode, the system clock should be gated off for all

unused on-chip peripherals via the Clock Peripheral Power-Down Registers.

HALT Mode and the EMAC Function

When the CPU is in HALT mode, the eZ80F91 device’s EMAC block cannot be

disabled as can other peripherals. Upon receipt of an Ethernet packet, a

maskable Receive interrupt is generated by the EMAC block, just as it would be in

a non-halt mode. Accordingly, the processor wakes up and continues with the

user-defined application.

Clock Peripheral Power-Down Registers

To reduce power, the Clock Peripheral Power-Down Registers allow the system

clock to be blocked to unused on-chip peripherals. Upon RESET, all peripherals

are enabled. The clock to unused peripherals can be gated off by setting the

appropriate bit in the Clock Peripheral Power-Down Registers to 1. When pow-

ered down, the peripherals are completely disabled. To reenable, the bit in the

Clock Peripheral Power-Down Registers must be cleared to 0.

Many peripherals feature separate enable/disable control bits that must be appro-

priately set for operation. These peripheral specific enable/disable bits do not pro-

vide the same level of power reduction as the Clock Peripheral Power-Down

Registers. When powered down, the individual peripheral control register is not

accessible for Read or Write acess. See Tables 4 and 5.

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Table 4. Clock Peripheral Power-Down Register 1

(CLK_PPD1 = 00DBh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value Description

7

1

System clock to GPIO Port D is powered down.

GPIO_D_OFF

Port D alternate functions do not operate correctly.

0

1

System clock to GPIO Port D is powered up.

6

System clock to GPIO Port C is powered down.

Port C alternate functions do not operate correctly.

GPIO_C_OFF

0

1

System clock to GPIO Port C is powered up.

5

System clock to GPIO Port B is powered down.

Port B alternate functions do not operate correctly.

GPIO_B_OFF

0

1

System clock to GPIO Port B is powered up.

4

System clock to GPIO Port A is powered down.

Port A alternate functions do not operate correctly.

GPIO_A_OFF

0

1

0

1

0

1

0

1

0

System clock to GPIO Port A is powered up.

System clock to SPI is powered down.

System clock to SPI is powered up.

3

SPI_OFF

2

System clock to I C is powered down.

I2C_OFF

2

System clock to I C is powered up.

1

System clock to UART1 is powered down.

System clock to UART1 is powered up.

UART1_OFF

0

System clock to UART0 and IrDA endec is powered down.

System clock to UART0 and IrDA endec is powered up.

UART0_OFF

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Table 5. Clock Peripheral Power-Down Register 2

(CLK_PPD2 = 00DCh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

R

R/W

Note: R = Read Only; R/W = Read/Write.

Bit

Position

Value Description

7

1

PHI Clock output is disabled (output is high-impedance).

PHI Clock output is enabled.

PHI_OFF

0

[6:4]

000

1

Reserved.

3

System clock to TIMER3 is powered down.

System clock to TIMER3 is powered up.

System clock to TIMER2 is powered down.

System clock to TIMER2 is powered up.

System clock to TIMER1 is powered down.

System clock to TIMER1 is powered up.

System clock to TIMER0 is powered down.

System clock to TIMER0 is powered up.

TIMER3_OFF

0

2

1

TIMER2_OFF

0

1

TIMER1_OFF

0

1

TIMER0_OFF

0

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General-Purpose Input/Output

GPIO Overview

The eZ80F91 device features 32 General-Purpose Input/Output (GPIO) pins. The

GPIO pins are assembled as four 8-bit ports— Port A, Port B, Port C, and Port D.

All port signals can be configured for use as either inputs or outputs. In addition,

all of the port pins can be used as vectored interrupt sources for the CPU.

®

The eZ80F91 microcontroller’s GPIO ports are slightly modified from its eZ80

predecessors. Specifically, Port A pins now can source 8mA and sink 10mA. In

addition, the Port B and C inputs now feature Schmitt-trigger input buffers.

GPIO Operation

GPIO operation is the same for all four GPIO ports (Ports A, B, C, and D). Each

port features eight GPIO port pins. The operating mode for each pin is controlled

by four bits that are divided between four 8-bit registers. These GPIO mode con-

trol registers are:

•

Port x Data Register (Px_DR)

Port x Data Direction Register (Px_DDR)

Port x Alternate Register 1 (Px_ALT1)

Port x Alternate Register 2 (Px_ALT2)

where x can be A, B, C, or D representing any of the four GPIO ports A, B, C, or D.

The mode for each pin is controlled by setting each register bit pertinent to the pin

to be configured. For example, the operating mode for Port B Pin 7 (PB7) is set by

the values contained in PB_DR[7], PB_DDR[7], PB_ALT1[7], and PB_ALT2[7].

The combination of the GPIO control register bits allows individual configuration of

each port pin for nine modes. In all modes, reading of the Port x Data register

returns the sampled state, or level, of the signal on the corresponding pin. Table 6

indicates the function of each port signal based upon these four register bits. After

a RESET event, all GPIO port pins are configured as standard digital inputs

(GPIO Mode 2), with interrupts disabled.

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Table 6. GPIO Mode Selection

GPIO Px_ALT2 Px_ALT1 Px_DDR Px_DR

Mode

Bits7:0

Bits7:0 Bits7:0 Port Mode

Output

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Output

0

Output

1

2

3

4

Input from pin

Open-drain output

Open-drain I/O

Open-source I/O

Open-source output

Reserved

High impedance

0

High impedance

1

5

6

7

High impedance

Interrupt—dual edge-triggered High impedance

Port B, C, or D—alternate function controls port I/O.

8

9

Interrupt—active Low

Interrupt—active High

High impedance

Interrupt—falling edge-triggered High impedance

Interrupt—rising edge-triggered High impedance

GPIO Mode 1. The port pin is configured as a standard digital output pin. The

value written to the Port x Data register (Px_DR) is presented on the pin.

GPIO Mode 2. The port pin is configured as a standard digital input pin. The output

is tristated (high impedance). The value stored in the Port x Data register pro-

duces no effect. As in all modes, a Read from the Port x Data register returns the

pin’s value. GPIO Mode 2 is the default operating mode following a RESET.

GPIO Mode 3. The port pin is configured as open-drain I/O. The GPIO pins do not

feature an internal pull-up to the supply voltage. To employ the GPIO pin in

OPEN-DRAIN mode, an external pull-up resistor must connect the pin to the sup-

ply voltage. Writing a 0 to the Port x Data register outputs a Low at the pin. Writing

a 1 to the Port x Data register results in high-impedance output.

GPIO Mode 4. The port pin is configured as open-source I/O. The GPIO pins do

not feature an internal pull-down to the supply ground. To employ the GPIO pin in

OPEN-SOURCE mode, an external pull-down resistor must connect the pin to the

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supply ground. Writing a 1 to the Port x Data register outputs a High at the pin.

Writing a 0 to the Port x Data register results in a high-impedance output.

GPIO Mode 5. Reserved. This pin produces high-impedance output.

GPIO Mode 6. This bit enables a dual edge-triggered interrupt mode. Both a rising

and a falling edge on the pin cause an interrupt request to be sent to the CPU.

Writing a 1 to the Port x Data register bit position resets the corresponding inter-

rupt request. Writing a 0 produces no effect. The programmer must set the Port x

Data register before entering the edge-triggered interrupt mode.

GPIO Mode 7. For Ports B, C, and D, the port pin is configured to pass control over

to the alternate (secondary) functions assigned to the pin. For example, the alter-

nate mode function for PC7 is RI1 and the alternate mode function for PB4 is the

Timer 4 output. When GPIO Mode 7 is enabled, the pin output data and pin

tristated control come from the alternate function's data output and tristate control,

respectively. The value in the Port x Data register produces no effect on operation.

Input signals are sampled by the system clock before being passed to the alter-

nate function input.

Alternate function inputs are routed to the associated functional block regardless

of the GPIO mode setting.

Note:

Px_DDR does not indicate the GPIO direction in all alternate function modes.

GPIO Mode 8. The port pin is configured for level-sensitive interrupt modes. An

interrupt request is generated when the level at the pin is the same as the level

stored in the Port x Data register. The port pin value is sampled by the system

clock. The input pin must be held at the selected interrupt level for a minimum of 2

clock periods to initiate an interrupt. The interrupt request remains active as long

as this condition is maintained at the external source.

GPIO Mode 9. The port pin is configured for single edge-triggered interrupt mode.

The value in the Port x Data register determines if a positive or negative edge

causes an interrupt request. Writing a 0 to the Port x Data register bit sets the

selected pin to generate an interrupt request for falling edges. Writing a 1 to the

Port x Data register bit sets the selected pin to generate an interrupt request for

rising edges. Any time a port pin is configured for an edge-trigger interrupt, writing

a 1 to the Port x Data register causes a reset of the edge-trigger interrupt. Writing

a 0 produces no effect on operation. The programmer must set the Port x Data

register before entering the single- or dual-edge-triggered interrupt mode.

A simplified block diagram of a GPIO port pin is illustrated in Figure 5.

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GPIO Register

Data (Input)

Q

D

Q

D

System Clock

V_DD

Mode 1

Mode 4

Data Bus

D

Q

Port

System Clock

GPIO Register

Data (Output)

Mode 1

Mode 3

GND

Figure 5. GPIO Port Pin Block Diagram

GPIO Interrupts

Each port pin can be used as an interrupt source. Interrupts can be either level- or

edge-triggered.

Level-Triggered Interrupts

When the port is configured for level-triggered interrupts, the corresponding port

pin is tristated. An interrupt request is generated when the level at the pin is the

same as the level stored in the Port x Data register. The port pin value is sampled

by the system clock. The input pin must be held at the selected interrupt level for a

minimum of 2 clock periods to initiate an interrupt. The interrupt request remains

active as long as this condition is maintained at the external source.

For example, if PA3 is programmed for low-level interrupt and the pin is forced

Low for 2 clock cycles, an interrupt request signal is generated from that port pin

and sent to the CPU. The interrupt request signal remains active until the external

device driving PA3 forces the pin High. The CPU must be enabled to respond to

interrupts for the interrupt request signal to be acted upon.

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Edge-Triggered Interrupts

When the port is configured for edge-triggered interrupts, the corresponding port

pin is tristated. If the pin receives the correct edge from an external device, the

port pin generates an interrupt request signal to the CPU. Any time a port pin is

configured for an edge-triggered interrupt, writing a 1 to that pin’s Port x Data reg-

ister causes a reset of an edge-detected interrupt. The programmer must set the

bit in the Port x Data register to 1 before entering either single or dual edge-trig-

gered interrupt mode for that port pin.

When configured for dual edge-triggered interrupt mode (GPIO Mode 6), both a

rising and a falling edge on the pin cause an interrupt request to be sent to the

CPU.

When configured for single edge-triggered interrupt mode (GPIO Mode 9), the

value in the Port x Data register determines if a positive or negative edge causes

an interrupt request. A 0 in the Port x Data register bit sets the selected pin to gen-

erate an interrupt request for falling edges. A 1 in the Port x Data register bit sets

the selected pin to generate an interrupt request for rising edges.

GPIO Control Registers

The 16 GPIO Control Registers operate in groups of four with a set for each Port

(A, B, C, and D). Each GPIO port features a Port Data register, Port Data Direc-

tion register, Port Alternate register 1, and Port Alternate register 2.

Port x Data Registers

When the port pins are configured for one of the output modes, the data written to

the Port x Data registers, detailed in Table 7, is driven on the corresponding pins.

In all modes, reading from the Port x Data registers always returns the current

sampled value of the corresponding pins. When the port pins are configured as

edge-triggered interrupt sources, writing a 1 to the corresponding bit in the Port x

Data register clears the interrupt signal that is sent to the CPU. When the port pins

are configured for edge-selectable interrupts or level-sensitive interrupts, the

value written to the Port x Data register bit selects the interrupt edge or interrupt

level. See Table 6 for more information.

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Table 7. Port x Data Registers

(PA_DR = 0096h, PB_DR = 009Ah, PC_DR = 009Eh, PD_DR = 00A2h)

Bit

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

X

Reset

CPU Access

R/W

Note: X = Undefined; R/W = Read/Write.

Port x Data Direction Registers

In conjunction with the other GPIO Control Registers, the Port x Data Direction

registers, detailed in Table 8, control the operating modes of the GPIO port pins.

See Table 6 for more information. Px_DDR does not indicate the GPIO direction in

all alternate function modes.

Table 8. Port x Data Direction Registers

(PA_DDR = 0097h, PB_DDR = 009Bh, PC_DDR = 009Fh, PD_DDR = 00A3h)

Bit

7

1

6

1

5

1

4

1

3

1

2

1

0

1

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Port x Alternate Register 1

In conjunction with the other GPIO Control Registers, the Port x Alternate

Register 1, detailed in Table 9, controls the operating modes of the GPIO port

pins. Px_DDR does not indicate the GPIO direction in all alternate function

modes. See Table 6 for more information.

Table 9. Port x Alternate Registers 1

(PA_ALT1 = 0098h, PB_ALT1 = 009Ch, PC_ALT1 = 00A0h, PD_ALT1 = 00A4h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

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Port x Alternate Register 2

In conjunction with the other GPIO Control Registers, the Port x Alternate

Register 2, detailed in Table 10, controls the operating modes of the GPIO port

pins. See Table 6 for more information.

Table 10. Port x Alternate Registers 2

(PA_ALT2 = 0099h, PB_ALT2 = 009Dh, PC_ALT2 = 00A1h, PD_ALT2 = 00A5h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

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Interrupt Controller

The interrupt controller on the eZ80F91 device routes the interrupt request signals

from the internal peripherals, external devices (via the internal port I/O), and the

nonmaskable interrupt (NMI) pin to the CPU.

Maskable Interrupts

On the eZ80F91 device, all maskable interrupts use the CPU’s vectored interrupt

function. The size of the I register is modified to 16 bits in the eZ80F91 device, dif-

®

fering from that of previous versions of the eZ80 CPU, to allow for a 16MB range

of interrupt vector table placement. Additionally, the size of the IVECT register is

increased from 8 bits to 9 bits to provide an interrupt vector table that can be

expanded and is more easily integrated with other interrupts.

The vectors are 4 bytes (32 bits) apart, even though only 3 bytes (24 bits) are

required. A fourth byte is implemented for both programmability and expansion

purposes.

Starting the interrupt vectors at 40hallows for easy implementation of the interrupt

controller vectors with the RST vectors. Table 11 lists the low-byte vector for each

of the maskable interrupt sources. The maskable interrupt sources are listed in

order of their priority, with vector 40h being the highest-priority interrupt. In ADL

mode, the full 24-bit interrupt vector is located at starting address {I[15:1],

IVECT[8:0]}, where I[15:0] is the CPU’s Interrupt Page Address Register.

Table 11. Interrupt Vector Sources by Priority

Priority

Vector

040h

044h

048h

04Ch

050h

054h

058h

05Ch

060h

Source

EMAC Rx

EMAC Tx

EMAC SYS

PLL

Priority

24

Vector

0A0h

0A4h

0A8h

0ACh

0B0h

0B4h

0B8h

0BCh

0C0h

Source

Port B 0

Port B 1

Port B 2

Port B 3

Port B 4

Port B 5

Port B 6

Port B 7

Port C 0

0

1

2

3

4

5

6

7

8

25

26

27

Flash

28

Timer 0

Timer 1

Timer 2

Timer 3

29

30

31

32

Note: *The vector addresses 064h and 068h are left unused to avoid conflict with the nonmaskable

interrupt (NMI) address 066h. The NMI is prioritized higher than all maskable interrupts.

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Table 11. Interrupt Vector Sources by Priority (Continued)

Priority

9

Vector

064h

068h

06Ch

070h

074h

078h

07Ch

080h

084h

088h

08Ch

090h

094h

098h

09Ch

Source

unused*

RTC

Priority

33

Vector

Source

Port C 1

Port C 2

Port C 3

Port C 4

Port C 5

Port C 6

Port C 7

Port D 0

Port D 1

Port D 2

Port D 3

Port D 4

Port D 5

Port D 6

Port D 7

0C4h

0C8h

0CCh

0D0h

0D4h

0D8h

0DCh

0E0h

0E4h

0E8h

0ECh

0F0h

0F4h

0F8h

0FCh

10

11

34

35

12

13

14

15

16

17

18

19

20

21

22

23

UART 0

UART 1

36

37

2

I C

38

SPI

39

Port A 0

Port A 1

Port A 2

Port A 3

Port A 4

Port A 5

Port A 6

Port A 7

40

41

42

43

44

45

46

47

Note: *The vector addresses 064h and 068h are left unused to avoid conflict with the nonmaskable

interrupt (NMI) address 066h. The NMI is prioritized higher than all maskable interrupts.

The user’s program should store the interrupt service routine starting address in

the four-byte interrupt vector locations. As an example, in ADL mode, the three-

byte address for the SPI interrupt service routine is be stored at {I[15:1], 07Ch},

{I[15:1], 07Dh} and {I[15:1], 07Eh}. In Z80 mode, the two-byte address for the SPI

interrupt service routine is be stored at {MBASE[7:0], I[7:1], 07Ch} and {MBASE,

I[7:1], 07Dh}. The least-significant byte is stored at the lower address.

When any one or more of the interrupt requests (IRQs) become active, an inter-

rupt request is generated by the interrupt controller and sent to the CPU. The cor-

responding 9-bit interrupt vector for the highest-priority interrupt is placed on the

9-bit interrupt vector bus, IVECT[8:0]. The interrupt vector bus is internal to the

eZ80F91 device and is therefore not visible externally. The response time of the

CPU to an interrupt request is a function of the current instruction being executed

as well as the number of wait states being asserted. The interrupt vector, {I[15:1],

IVECT[8:0]}, is visible on the address bus, ADDR[23:0], when the interrupt service

routine begins. The response of the CPU to a vectored interrupt on the eZ80F91

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device is explained in Table 12. Interrupt sources are required to be active until

the interrupt service routine (ISR) starts.

The lower bit of the I register is replaced with the MSB of the IVECT from the inter-

rupt controller. As a result, the interrupt vector table is required to be placed onto a

512-byte boundary. Setting the LSB of the I register produces no effect on the

interrupt vector address.

Note:

Table 12. Vectored Interrupt Operation

Memory

Mode

ADL MADL

Bit

Operation

Z80 Mode

0

Read the LSB of the interrupt vector placed on the internal vectored

interrupt bus, IVECT [8:0], by the interrupting peripheral.

• IEF1

←

0

• IEF2

•

The Starting Program Counter is effectively {MBASE, PC[15:0]}.

Push the 2-byte return address PC[15:0] onto the ({MBASE,SPS}) stack.

The ADL mode bit remains cleared to 0.

The interrupt vector address is located at { MBASE, I[7:1], IVECT[8:0] }.

PC[23:0] ← ( { MBASE, I[7:1], IVECT[8:0] } )

.

The interrupt service routine must end with RETI.

ADL Mode

1

0

Read the LSB of the interrupt vector placed on the internal vectored

interrupt bus, IVECT [8:0], by the interrupting peripheral.

• IEF1

←

0

• IEF2

•

The Starting Program Counter is PC[23:0].

Push the 3-byte return address, PC[23:0], onto the SPL stack.

The ADL mode bit remains set to 1.

The interrupt vector address is located at { I[15:1], IVECT[8:0] }.

PC[23:0] ← ( { I[15:1], IVECT[8:0] } )

.

The interrupt service routine must end with RETI.

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Table 12. Vectored Interrupt Operation (Continued)

Memory

Mode

ADL MADL

Bit

Operation

Z80 Mode

0

1

Read the LSB of the interrupt vector placed on the internal vectored

interrupt bus, IVECT[8:0], bus by the interrupting peripheral.

• IEF1

←

0

• IEF2

•

The Starting Program Counter is effectively {MBASE, PC[15:0]}.

Push the 2-byte return address, PC[15:0], onto the SPL stack.

Push a 00h byte onto the SPL stack to indicate an interrupt from Z80 mode

(because ADL = 0).

•

Set the ADL mode bit to 1.

The interrupt vector address is located at { I[15:1], IVECT[8:0] }.

PC[23:0] ← ( { I[15:1], IVECT[8:0] } )

The interrupt service routine must end with RETI.L

.

ADL Mode

1

Read the LSB of the interrupt vector placed on the internal vectored

interrupt bus, IVECT [8:0], by the interrupting peripheral.

• IEF1

←

0

• IEF2

•

The Starting Program Counter is PC[23:0].

Push the 3-byte return address, PC[23:0], onto the SPL stack.

Push a 01h byte onto the SPL stack to indicate a restart from ADL mode

(because ADL = 1).

•

The ADL mode bit remains set to 1.

The interrupt vector address is located at {I[15:1], IVECT[8:0]}.

PC[23:0] ← ( { I[15:1], IVECT[8:0] } )

The interrupt service routine must end with RETI.L

.

Interrupt Priority Registers

The eZ80F91 provides two interrupt priority levels for the maskable interrupts.

The default priority (or Level 0) is indicated in Table 11. The default priority of any

maskable interrupt can increase to Level 1 (a higher priority than any Level 0

interrupt) by setting the appropriate bit in the Interrupt Priority Registers, which

are shown in Table 13.

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Table 13. Interrupt Priority Registers

(INT_P0 = 0010h, INT_P1 = 0011h, INT_P2 = 0012h,

INT_P3 = 0013h, INT_P4 = 0014h, INT_P5 = 0015h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

INT_P0 Reset

INT_P1 Reset

INT_P2 Reset

INT_P3 Reset

INT_P4 Reset

INT_P5 Reset

CPU Access

0

0*

0

0*

0

R/W

Note: X = Undefined; R/W = Read/Write, *Unused.

Bit

Position

Value Description

Default Interrupt Priority

Level One Interrupt Priority

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

INT_PX

6

Default Interrupt Priority

Level One Interrupt Priority

Default Interrupt Priority

Level One Interrupt Priority

Default Interrupt Priority

Level One Interrupt Priority

Default Interrupt Priority

Level One Interrupt Priority

Default Interrupt Priority

Level One Interrupt Priority

Default Interrupt Priority

Level One Interrupt Priority

Default Interrupt Priority

Level One Interrupt Priority

INT_PX

5

INT_PX

4

INT_PX

3

INT_PX

2

INT_PX

1

INT_PX

0

INT_PX

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The Interrupt Priority Control bits are shown in Table 14.

Table 14. Interrupt Vector Priority Control Bits

Priority

Control Bit Vector

Priority

Control Bit Vector

Source

EMAC Rx

EMAC Tx

EMAC SYS

PLL

Source

Port B 0

Port B 1

Port B 2

Port B 3

Port B 4

Port B 5

Port B 6

Port B 7

Port C 0

Port C 1

Port C 2

Port C 3

Port C 4

Port C 5

Port C 6

Port C 7

Port D 0

Port D 1

Port D 2

Port D 3

Port D 4

Port D 5

Port D 6

Port D 7

INT_P0[0]

INT_P0[1]

INT_P0[2]

INT_P0[3]

INT_P0[4]

INT_P0[5]

INT_P0[6]

INT_P0[7]

INT_P1[0]

INT_P1[1]

INT_P1[2]

INT_P1[3]

INT_P1[4]

INT_P1[5]

INT_P1[6]

INT_P1[7]

INT_P2[0]

INT_P2[1]

INT_P2[2]

INT_P2[3]

INT_P2[4]

INT_P2[5]

INT_P2[6]

INT_P2[7]

040h

044h

048h

04Ch

050h

054h

058h

05Ch

060h

064h

068h

06Ch

070h

074h

078h

07Ch

080h

084h

088h

08Ch

090h

094h

098h

09Ch

INT_P3[0]

INT_P3[1]

INT_P3[2]

INT_P3[3]

INT_P3[4]

INT_P3[5]

INT_P3[6]

INT_P3[7]

INT_P4[0]

INT_P4[1]

INT_P4[2]

INT_P4[3]

INT_P4[4]

INT_P4[5]

INT_P4[6]

INT_P4[7]

INT_P5[0]

INT_P5[1]

INT_P5[2]

INT_P5[3]

INT_P5[4]

INT_P5[5]

INT_P5[6]

INT_P5[7]

0A0h

0A4h

0A8h

0ACh

0B0h

0B4h

0B8h

0BCh

0C0h

0C4h

0C8h

0CCh

0D0h

0D4h

0D8h

0DCh

0E0h

0E4h

0E8h

0ECh

0F0h

0F4h

0F8h

0FCh

Flash

Timer 0

Timer 1

Timer 2

Timer 3

unused*

RTC

UART 0

UART 1

2

I C

SPI

Port A 0

Port A 1

Port A 2

Port A 3

Port A 4

Port A 5

Port A 6

Port A 7

Note: *The vector addresses 064hand 068hare left unused to avoid conflict with the NMI

vector address 066h.

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If more than one maskable interrupt is prioritized to a higher level (Level 1), the

higher-priority interrupts follow the priority order described in Table 11. For exam-

ple, Table 15 shows the maskable interrupts 044h(EMAC Tx), 084h(Port A 1),

and 06Ch(RTC) as elevated to Priority Level 1. Table 16 shows the new interrupt

priority for the top ten maskable interrupts.

Table 15. Example: Maskable Interrupt Priority

Priority

Register

INT_P0

INT_P1

INT_P2

INT_P3

INT_P4

INT_P5

Setting Description

02h

08h

02h

00h

Increase 044h (EMAC Tx) to Priority Level 1

Increase 06Ch (RTC) to Priority Level 1

Increase 084h (Port A1) to Priority Level 1

Default priority

Table 16. Example: Priority Levels for Maskable Interrupts

Priority

Vector

044h

06Ch

084h

040h

048h

04Ch

050h

054h

058h

05Ch

Source

EMAC Tx

RTC

0

1

2

3

4

5

6

7

8

9

Port A 1

EMAC Rx

EMAC SYS

PLL

Flash

Timer 0

Timer 1

Timer 2

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GPIO Port Interrupts

All interrupts are latched. In effect, an interrupt is held even if the interrupt occurs

while another interrupt is being serviced and interrupts are disabled, or if the inter-

rupt is of a lower priority. However, before the latched ISR completes its task or

reenables interrupts, the ISR must clear the interrupt. For on-chip peripherals, the

interrupt is cleared when the data register is accessed. For GPIO-level interrupts,

the interrupt signal must be removed before the ISR completes its task. For GPIO-

edge interrupts (single and dual), the interrupt is cleared by writing a 1 to the cor-

responding bit position in the data register. See the Edge-Triggered Interrupts

section on page 62.

Care must be taken using a GPIO data register when it is configured for inter-

rupts. For edge-interrupt modes (Modes 6 and 9) as discussed above, writing a 1

clears the interrupt. However, a 1 in the data register also conveys a particular

configuration. For example, when the data register Px_DR is set first, followed by

the Px_ALT2, Px_ALT1, and Px_DDR registers, then the configuration is per-

formed correctly. Writing a 1 to the register later to clear interrupts does not

change the configuration.

Note:

In Mode 9 operation, if the GPIO is already configured for Mode 9 and the trigger

edge must be changed (from falling to rising or from rising to falling), the configu-

ration must be changed to another mode, such as Mode 2, and then changed

back to Mode 9. For example, enter Mode 2 by writing the registers in the

sequence PxDR, Px_ALT2, Px_ALT1, Px_DDR. Next, change back to Mode 9 by

writing the registers in the sequence PxDR, Px_ALT2, Px_ALT1, Px_DDR.

In Mode 8 operation, if the GPIO is configured for level-sensitive interrupts, a

Write value to Px_DR after configuration must be the same Write value used

when configuring the GPIO.

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Chip Selects and Wait States

The eZ80F91 generates four Chip Selects for external devices. Each Chip Select

can be programmed to access either memory space or I/O space. The Memory

Chip Selects can be individually programmed on a 64KB boundary. The I/O Chip

Selects can each choose a 256-byte section of I/O space. In addition, each Chip

Select can be programmed for up to 7 wait states.

Memory and I/O Chip Selects

Each of the Chip Selects can be enabled for either the memory address space or

the I/O address space, but not both. To select the memory address space for a

particular Chip Select, CSX_IO (CSx_CTL[4]) must be reset to 0. To select the I/O

address space for a particular Chip Select, CSX_IO must be set to 1. After

RESET, the default is for all Chip Selects to be configured for the memory address

space. For either the memory address space or the I/O address space, the indi-

vidual Chip Selects must be enabled by setting CSX_EN (CSx_CTL[3]) to 1.

Memory Chip Select Operation

Operation of each of the Memory Chip Selects is controlled by three control regis-

ters. To enable a particular Memory Chip Select, the following conditions must be

met:

•

The Chip Select is enabled by setting CSx_EN to 1

The Chip Select is configured for memory by clearing CSX_IO to 0

The address is in the associated Chip Select range:

CSx_LBR[7:0] ≤ ADDR[23:16] ≤ CSx_UBR[7:0]

•

On-chip Flash is not configured for the same address space, because on-chip

Flash is prioritized higher than all Memory Chip Selects

On-chip RAM is not configured for the same address space, because on-chip

RAM is prioritized higher than Flash and all Memory Chip Selects

•

No higher priority (lower number) Chip Select meets the above conditions

A memory access instruction must be executing

If all of the foregoing conditions are met to generate a Memory Chip Select, then

the following actions occur:

•

The appropriate Chip Select—CS0, CS1, CS2, or CS3—is asserted (driven

Low)

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•

MREQ is asserted (driven Low)

Depending upon the instruction, either RD or WR is asserted (driven Low)

If the upper and lower bounds are set to the same value (CSx_UBR = CSx_LBR),

then a particular Chip Select is valid for a single 64KB page.

Memory Chip Select Priority

A lower-numbered Chip Select is granted priority over a higher-numbered Chip

Select. For example, if the address space of Chip Select 0 overlaps the Chip

Select 1 address space, Chip Select 0 is active. If the address range programmed

for any Chip Select signal overlaps with the address of internal memory, the inter-

nal memory is accorded higher priority. If the particular Chip Select(s) are config-

ured with an address range that overlaps with an internal memory address, then

when the internal memory is accessed, the Chip Select signal is not asserted.

Reset States

On RESET, Chip Select 0 is active for all addresses, because its Lower Bound

register resets to 00hand its Upper Bound register resets to FFh. All of the other

Chip Select Lower and Upper Bound registers reset to 00h.

Memory Chip Select Example

The use of Memory Chip Selects is demonstrated in Figure 6. The associated

control register values are indicated in Table 17. In this example, all 4 Chip

Selects are enabled and configured for memory addresses. Also, CS1 overlaps

with CS0. Because CS0 is prioritized higher than CS1, CS1 is not active for much

of its defined address space.

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Memory

Location

CS3_UBR = FFh

FFFFFFh

CS3 Active

3 MB Address Space

CS3_LBR = D0h

CS2_UBR = CFh

D00000h

CFFFFFh

CS2 Active

3 MB Address Space

CS2_LBR = A0h

CS1_UBR = 9Fh

A00000h

9FFFFFh

CS1 Active

2 MB Address Space

800000h

7FFFFFh

CS0_UBR = 7Fh

CS0 Active

8 MB Address Space

CS0_LBR = CS1_LBR = 00h

000000h

Figure 6. Example: Memory Chip Select

Table 17. Example: Register Values for Figure 6 Memory Chip Select

Chip

CSx_CTL[3] CSx_CTL[4]

Select

CSx_EN

CSx_IO

CSx_LBR CSx_UBR Description

CS0

CS1

CS2

CS3

1

0

00h

A0h

D0h

7Fh

9Fh

CFh

FFh

CS0 is enabled as a Memory Chip

Select. Valid addresses range from

000000h–7FFFFFh.

1

0

CS1 is enabled as a Memory Chip

Select. Valid addresses range from

800000h–9FFFFFh.

CS2 is enabled as a Memory Chip

Select. Valid addresses range from

A00000h–CFFFFFh.

CS3 is enabled as a Memory Chip

Select. Valid addresses range from

D00000h–FFFFFFh.

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I/O Chip Select Operation

I/O Chip Selects can only be active when the CPU is performing I/O instructions.

Because the I/O space is separate from the memory space in the eZ80F91

device, there can never be a conflict between I/O and memory addresses.

The eZ80F91 supports a 16-bit I/O address. The I/O Chip Select logic decodes

the High byte of the I/O address, ADDR[15:8]. Because the upper byte of the

address bus, ADDR[23:16], is ignored, the I/O devices can always be accessed

from within either memory mode (ADL or Z80). The MBASE offset value used for

setting the Z80 MEMORY mode page is also always ignored.

Four I/O Chip Selects are available with the eZ80F91 device. To generate a par-

ticular I/O Chip Select, the following conditions must be met:

•

The Chip Select is enabled by setting CSx_EN to 1

The Chip Select is configured for I/O by setting CSX_IO to 1

An I/O Chip Select address match occurs—ADDR[15:8] = CSx_LBR[7:0]

No higher-priority (lower-number) Chip Select meets the above conditions

The I/O address is not within the on-chip peripheral address range 0080h–

00FFh. On-chip peripheral registers assume priority for all addresses where:

0080h≤ ADDR[15:0] ≤ 00FFh

•

An I/O instruction must be executing

If all of the foregoing conditions are met to generate an I/O Chip Select, then the

following actions occur:

•

The appropriate Chip Select—CS0, CS1, CS2, or CS3—is asserted (driven

Low)

•

IORQ is asserted (driven Low)

Depending upon the instruction, either RD or WR is asserted (driven Low)

Wait States

For each of the Chip Selects, programmable wait states can be asserted to pro-

vide external devices with additional clock cycles to complete their Read or Write

operations. The number of wait states for a particular Chip Select is controlled by

the 3-bit field CSx_WAIT (CSx_CTL[7:5]). The wait states can be independently

programmed to provide 0 to 7 wait states for each Chip Select. The wait states

idle the CPU for the specified number of system clock cycles.

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WAIT Input Signal

Similar to the programmable wait states, an external peripheral can drive the

WAIT input pin to force the CPU to provide additional clock cycles to complete its

Read or Write operation. Driving the WAIT pin Low stalls the CPU. The CPU

resumes operation on the first rising edge of the internal system clock following

deassertion of the WAIT pin.

If the WAIT pin is to be driven by an external device, the corresponding Chip Select for

the device must be programmed to provide at least one wait state. Due to input sampling

of the WAIT input pin (shown in Figure 7), one programmable wait state is required to

allow the external peripheral sufﬁcient time to assert the WAIT pin. It is recommended

that the corresponding Chip Select for the external device be programmed to provide the

maximum number of wait states (seven).

Caution:

eZ80

CPU

Wait

D

Q

System Clock

Figure 7. Wait Input Sampling Block Diagram

An example of wait state operation is illustrated in Figure 8. In this example, the

Chip Select is configured to provide a single wait state. The external peripheral

being accessed drives the WAIT pin Low to request assertion of an additional wait

state. If the WAIT pin is asserted for additional system clock cycles, wait states

are added until the WAIT pin is deasserted (active High).

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T_CLK

T_WAIT

SCLK

ADDR[23:0]

DATA[7:0]

(output)

CSx

MREQ

RD

INSTRD

Figure 8. Example: Wait State Read Operation

Chip Selects During Bus Request/Bus Acknowledge Cycles

When the CPU relinquishes the address bus to an external peripheral in response

to an external bus request (BUSREQ), it drives the bus acknowledge pin

(BUSACK) Low. The external peripheral can then drive the address bus (and data

bus). The CPU continues to generate Chip Select signals in response to the

address on the bus. External devices cannot access the internal registers of the

eZ80F91.

Bus Mode Controller

The bus mode controller allows the address and data bus timing and signal for-

mats of the eZ80F91 to be configured to connect seamlessly with external

®

eZ80 -, Z80™-, Intel™-, or Motorola-compatible devices. Bus modes for each of

the chip selects can be configured independently using the Chip Select Bus Mode

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Control Registers. The number of CPU system clock cycles per bus mode state is

also independently programmable. For Intel bus mode, multiplexed address and

data can be selected, in which the lower byte of the address and the data byte

both use the data bus, DATA[7:0]. Each of the bus modes is explained in more

detail in the following sections.

eZ80 Bus Mode

Chip selects configured for eZ80 bus mode do not modify the bus signals from the

CPU. The timing diagrams for external Memory and I/O Read and Write opera-

tions are shown in the AC Characteristics section on page 348. The default mode

for each chip select is eZ80 mode.

Z80 Bus Mode

®

Chip selects configured for Z80 mode modify the eZ80 bus signals to match the

Z80 microprocessor address and data bus interface signal format and timing. Dur-

ing Read operations, the Z80 Bus mode employs three states—T1, T2, and T3—

as described in Table 18.

Table 18. Z80 Bus Mode Read States

STATE T1 The Read cycle begins in State T1. The CPU drives the address onto the address bus

and the associated Chip Select signal is asserted.

STATE T2 During State T2, the RD signal is asserted. Depending upon the instruction, either the

MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU

system clock cycle prior to the end of State T2, additional wait states (T

until the WAIT pin is driven High.

) are asserted

WAIT

STATE T3 During State T3, no bus signals are altered. The data is latched by the eZ80F91 at the

rising edge of the CPU system clock at the end of State T3.

During Write operations, Z80 Bus mode employs 3 states—T1, T2, and T3—as

described in Table 19.

Table 19. Z80 Bus Mode Write States

STATE T1 The Write cycle begins in State T1. The CPU drives the address onto the address bus,

and the associated Chip Select signal is asserted.

STATE T2 During State T2, the WR signal is asserted. Depending upon the instruction, either the

MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU

system clock cycle prior to the end of State T2, additional wait states (T

until the WAIT pin is driven High.

) are asserted

WAIT

STATE T3 During State T3, no bus signals are altered.

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Z80 bus mode Read and Write timing is illustrated in Figures 9 and 10 . The Z80

bus mode states can be configured for 1 to 15 CPU system clock cycles. In the

figures, each Z80 bus mode state is two CPU system clock cycles in duration. Fig-

ures 9 and 10 also illustrate the assertion of 1 wait state (T

peripheral during each Z80 bus mode cycle.

) by the external

WAIT

T

T1

T2

T3

CLK

System Clock

ADDR[23:0]

DATA[7:0]

CSx

RD

WAIT

WR

MREQ

or IORQ

Figure 9. Example: Z80 Bus Mode Read Timing

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T

T1

T2

T3

CLK

System Clock

ADDR[23:0]

DATA[7:0]

CSx

RD

WAIT

WR

MREQ

or IORQ

Figure 10. Example: Z80 Bus Mode Write Timing

Intel Bus Mode

Chip selects configured for Intel bus mode modify the CPU bus signals to dupli-

cate a four-state memory transfer similar to that found on Intel-style microcontrol-

lers. The bus signals and eZ80F91 pins are mapped as illustrated in Figure 11. In

Intel bus mode, the user can select either multiplexed or nonmultiplexed address

and data buses. In nonmultiplexed operation, the address and data buses are

separate. In multiplexed operation, the lower byte of the address, ADDR[7:0], also

appears on the data bus, DATA[7:0], during State T1 of the Intel bus mode cycle.

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Bus Mode

Controller

eZ80 Bus Mode

Signals (Pins)

Intel Bus

Signal Equvalents

INSTRD

RD

ALE

RD

WR

WAIT

READY

MREQ

IORQ

ADDR[23:0]

ADDR[7:0]

Multiplexed

Bus

Controller

DATA[7:0]

Figure 11. Intel Bus Mode Signal and Pin Mapping

Intel Bus Mode—Separate Address and Data Buses

During Read operations with separate address and data buses, the Intel bus

mode employs 4 states—T1, T2, T3, and T4—as described in Table 20.

Table 20. Intel Bus Mode Read States—Separate Address and Data Buses

STATE T1 The Read cycle begins in State T1. The CPU drives the address onto the address bus and

the associated Chip Select signal is asserted. The CPU drives the ALE signal High at the

beginning of T1. During the middle of T1, the CPU drives ALE Low to facilitate the latching

of the address.

STATE T2 During State T2, the CPU asserts the RD signal. Depending on the instruction, either the

MREQ or IORQ signal is asserted.

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Table 20. Intel Bus Mode Read States—Separate Address and Data Buses (Continued)

STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven

Low at least one CPU system clock cycle prior to the beginning of State T3, additional wait

states (T

) are asserted until the READY pin is driven High.

WAIT

STATE T4 The CPU latches the Read data at the beginning of State T4. The CPU deasserts the RD

signal and completes the Intel bus mode cycle.

During Write operations with separate address and data buses, the Intel bus

mode employs 4 states—T1, T2, T3, and T4—as described in Table 21.

Table 21. Intel Bus Mode Write States—Separate Address and Data Buses

STATE T1 The Write cycle begins in State T1. The CPU drives the address onto the address bus, the

associated Chip Select signal is asserted, and the data is driven onto the data bus. The

CPU drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU

drives ALE Low to facilitate the latching of the address.

STATE T2 During State T2, the CPU asserts the WR signal. Depending on the instruction, either the

MREQ or IORQ signal is asserted.

STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven

Low at least one CPU system clock cycle prior to the beginning of State T3, additional wait

states (T

) are asserted until the READY pin is driven High.

WAIT

STATE T4 The CPU deasserts the WR signal at the beginning of State T4. The CPU holds the data

and address buses through the end of T4. The bus cycle is completed at the end of T4.

Intel™ bus mode timing is illustrated for a Read operation in Figure 12 and for a

Write operation in Figure 13. If the READY signal (external WAIT pin) is driven

Low prior to the beginning of State T3, additional wait states (T

) are asserted

WAIT

until the READY signal is driven High. The Intel bus mode states can be config-

ured for 2 to 15 CPU system clock cycles. In the figures, each Intel™ bus mode

state is 2 CPU system clock cycles in duration. Figures 12 and 13 also illustrate

the assertion of one wait state (T

) by the selected peripheral.

WAIT

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T

WAIT

T1

T2

T3

T4

System Clock

ADDR[23:0]

DATA[7:0]

CSx

ALE

RD

READY

WR

MREQ

or IORQ

Figure 12. Example: Intel Bus Mode Read Timing—Separate Address and Data Buses

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T

WAIT

T1

T2

T3

T4

System Clock

ADDR[23:0]

DATA[7:0]

CSx

ALE

WR

READY

RD

MREQ

or IORQ

Figure 13. Example: Intel Bus Mode Write Timing—Separate Address and Data Buses

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eZ80F91 MCU

Product Specification

86

Intel™ Bus Mode—Multiplexed Address and Data Bus

During Read operations with multiplexed address and data, the Intel™ bus mode

employs 4 states—T1, T2, T3, and T4—as described in Table 22.

Table 22. Intel™ Bus Mode Read States—Multiplexed Address and Data Bus

STATE T1 The Read cycle begins in State T1. The CPU drives the address onto the DATA bus and

the associated Chip Select signal is asserted. The CPU drives the ALE signal High at the

beginning of T1. During the middle of T1, the CPU drives ALE Low to facilitate the latching

of the address.

STATE T2 During State T2, the CPU removes the address from the DATA bus and asserts the RD

signal. Depending upon the instruction, either the MREQ or IORQ signal is asserted.

STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven

Low at least one CPU system clock cycle prior to the beginning of State T3, additional wait

states (T

) are asserted until the READY pin is driven High.

WAIT

STATE T4 The CPU latches the Read data at the beginning of State T4. The CPU deasserts the RD

signal and completes the Intel™ bus mode cycle.

During Write operations with multiplexed address and data, the Intel™ bus mode

employs 4 states—T1, T2, T3, and T4—as described in Table 23.

Table 23. Intel™ Bus Mode Write States—Multiplexed Address and Data Bus

STATE T1 The Write cycle begins in State T1. The CPU drives the address onto the DATA bus and

drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU drives

ALE Low to facilitate the latching of the address.

STATE T2 During State T2, the CPU removes the address from the DATA bus and drives the Write

data onto the DATA bus. The WR signal is asserted to indicate a Write operation.

STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven

Low at least one CPU system clock cycle prior to the beginning of State T3, additional wait

states (T

) are asserted until the READY pin is driven High.

WAIT

STATE T4 The CPU deasserts the Write signal at the beginning of T4 identifying the end of the Write

operation. The CPU holds the data and address buses through the end of T4. The bus

cycle is completed at the end of T4.

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Chip Selects and Wait States

eZ80F91 MCU

Product Specification

87

Signal timing for Intel™ bus mode with multiplexed address and data is illustrated

for a Read operation in Figure 14 and for a Write operation in Figure 15. In these

figures, each Intel™ bus mode state is 2 CPU system clock cycles in duration.

Figures 14 and 15 also illustrate the assertion of one wait state (T

selected peripheral.

) by the

WAIT

T

WAIT

T1

T2

T3

T4

System Clock

ADDR[23:0]

DATA[7:0]

CSx

ALE

RD

READY

WR

MREQ

or IORQ

Figure 14. Example: Intel™ Bus Mode Read Timing—Multiplexed Address and Data Bus

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Chip Selects and Wait States

eZ80F91 MCU

Product Specification

88

T

WAIT

T1

T2

T3

T4

System Clock

ADDR[23:0]

DATA[7:0]

CSx

ALE

WR

READY

RD

MREQ

or IORQ

Figure 15. Example: Intel™ Bus Mode Write Timing—Multiplexed Address and Data Bus

Motorola Bus Mode

Chip selects configured for Motorola bus mode modify the CPU bus signals to

duplicate an eight-state memory transfer similar to that found on Motorola-style

microcontrollers. The bus signals (and eZ80F91 I/O pins) are mapped as illus-

trated in Figure 16.

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Chip Selects and Wait States

eZ80F91 MCU

Product Specification

89

Bus Mode

Controller

eZ80 Bus Mode

Signals (Pins)

Motorola Bus

Signal Equvalents

INSTRD

RD

AS

DS

R/W

WR

WAIT

DTACK

MREQ

IORQ

ADDR[23:0]

DATA[7:0]

Figure 16. Motorola Bus Mode Signal and Pin Mapping

During Write operations, the Motorola bus mode employs 8 states—S0, S1, S2,

S3, S4, S5, S6, and S7—as described in Table 24.

Table 24. Motorola Bus Mode Read States

STATE S0 The Read cycle starts in state S0. The CPU drives R/W High to identify a Read cycle.

STATE S1 Entering state S1, the CPU drives a valid address on the address bus, ADDR[23:0].

STATE S2 On the rising edge of state S2, the CPU asserts AS and DS.

STATE S3 During state S3, no bus signals are altered.

STATE S4 During state S4, the CPU waits for a cycle termination signal DTACK (WAIT), a peripheral

signal. If the termination signal is not asserted at least one full CPU clock period prior to

the rising clock edge at the end of S4, the CPU inserts WAIT (T

asserted. Each wait state is a full bus mode cycle.

) states until DTACK is

WAIT

STATE S5 During state S5, no bus signals are altered.

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Chip Selects and Wait States

eZ80F91 MCU

Product Specification

90

Table 24. Motorola Bus Mode Read States (Continued)

STATE S6 During state S6, data from the external peripheral device is driven onto the data bus.

STATE S7 On the rising edge of the clock entering state S7, the CPU latches data from the

addressed peripheral device and deasserts AS and DS. The peripheral device deasserts

DTACK at this time.

The eight states for a Write operation in Motorola bus mode are described in

Table 25.

Table 25. Motorola Bus Mode WRITE States

STATE S0 The Write cycle starts in S0. The CPU drives R/W High (if a preceding Write cycle leaves

R/W Low).

STATE S1 Entering S1, the CPU drives a valid address on the address bus.

STATE S2 On the rising edge of S2, the CPU asserts AS and drives R/W Low.

STATE S3 During S3, the data bus is driven out of the high-impedance state as the data to be written

is placed on the bus.

STATE S4 At the rising edge of S4, the CPU asserts DS. The CPU waits for a cycle termination signal

DTACK (WAIT). If the termination signal is not asserted at least one full CPU clock period

prior to the rising clock edge at the end of S4, the CPU inserts WAIT (T

DTACK is asserted. Each wait state is a full bus mode cycle.

) states until

WAIT

STATE S5 During S5, no bus signals are altered.

STATE S6 During S6, no bus signals are altered.

STATE S7 Upon entering S7, the CPU deasserts AS and DS. As the clock rises at the end of S7, the

CPU drives R/W High. The peripheral device deasserts DTACK at this time.

Signal timing for Motorola bus mode is illustrated for a Read operation in

Figure 17 and for a Write operation in Figure 18. In these two figures, each Motor-

ola bus mode state is 2 CPU system clock cycles in duration.

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Chip Selects and Wait States

eZ80F91 MCU

Product Specification

91

S3

S6

S7

S0

S1

S2

S4

S5

System Clock

ADDR[23:0]

DATA[7:0]

CSx

AS

DS

R/W

DTACK

MREQ

or IORQ

Figure 17. Motorola Bus Mode Read Timing Example

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Chip Selects and Wait States

eZ80F91 MCU

Product Specification

92

S3

S6

S7

S0

S1

S2

S4

S5

System Clock

ADDR[23:0]

DATA[7:0]

CSx

AS

DS

R/W

DTACK

MREQ

or IORQ

Figure 18. Motorola Bus Mode Write Timing Example

Switching Between Bus Modes

When switching bus modes between Intel™ to Motorola, Motorola to Intel™, eZ80

to Motorola, or eZ80 to Intel™, there is one extra SCLK cycle added to the bus

access. An extra clock cycle is not required for repeated access in any of the bus

modes (for example Intel™ to Intel™). An extra clock cycle is not required for

Intel™ (or Motorola) to eZ80 bus mode (under normal operation). The extra clock

cycle is not shown in the timing examples. Due to the asynchronous nature of

these bus protocols, the extra delay does not impact peripheral communication.

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Chip Selects and Wait States

eZ80F91 MCU

Product Specification

93

Chip Select Registers

Chip Select x Lower Bound Register

For Memory Chip Selects, the Chip Select x Lower Bound register, detailed in

Table 26, defines the lower bound of the address range for which the correspond-

ing Memory Chip Select (if enabled) can be active. For I/O Chip Selects, this reg-

ister defines the address to which ADDR[15:8] is compared to generate an I/O

Chip Select. All Chip Select lower bound registers reset to 00h.

Table 26. Chip Select x Lower Bound Register

(CS0_LBR = 00A8h, CS1_LBR = 00ABh, CS2_LBR = 00AEh, CS3_LBR = 00B1h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

CS0_LBR Reset

CS1_LBR Reset

CS2_LBR Reset

CS3_LBR Reset

CPU Access

0

R/W

Note: R/W = Read/Write.

Bit

Position

Value Description

00h– For Memory Chip Selects (CSx_IO = 0)

[7:0]

CSX_LBR

FFh

This byte specifies the lower bound of the Chip Select address

range. The upper byte of the address bus, ADDR[23:16], is

compared to the values contained in these registers for

determining whether a Memory Chip Select signal should be

generated.

For I/O Chip Selects (CSx_IO = 1)

This byte specifies the Chip Select address value. ADDR[15:8] is

compared to the values contained in these registers for

determining whether an I/O Chip Select signal should be

generated.

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Chip Selects and Wait States

eZ80F91 MCU

Product Specification

94

Chip Select x Upper Bound Register

For Memory Chip Selects, the Chip Select x Upper Bound registers, detailed in

Table 27, defines the upper bound of the address range for which the correspond-

ing Chip Select (if enabled) can be active. For I/O Chip Selects, this register pro-

duces no effect. The reset state for the Chip Select 0 Upper Bound register is FFh,

while the reset state for the other Chip Select upper bound registers is 00h.

Table 27. Chip Select x Upper Bound Register

(CS0_UBR = 00A9h, CS1_UBR = 00ACh, CS2_UBR = 00AFh, CS3_UBR = 00B2h)

Bit

7

1

6

1

5

1

4

1

3

1

2

1

0

1

CS0_UBR Reset

CS1_UBR Reset

CS2_UBR Reset

CS3_UBR Reset

CPU Access

0

R/W

Note: R/W = Read/Write.

Bit

Position

Value Description

00h– For Memory Chip Selects (CSX_IO = 0)

[7:0]

CSX_UBR

FFh

This byte specifies the upper bound of the Chip Select

address range. The upper byte of the address bus,

ADDR[23:16], is compared to the values contained in these

registers for determining whether a Chip Select signal should

be generated.

For I/O Chip Selects (CSx_IO = 1)

No effect.

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Chip Selects and Wait States

eZ80F91 MCU

Product Specification

95

Chip Select x Control Register

The Chip Select x Control register, detailed in Table 28, enables the Chip Selects,

specifies the type of Chip Select, and sets the number of wait states. The reset

state for the Chip Select 0 Control register is E8h, while the reset state for the 3

other Chip Select control registers is 00h.

Table 28. Chip Select x Control Register

(CS0_CTL = 00AAh, CS1_CTL = 00ADh, CS2_CTL = 00B0h, CS3_CTL = 00B3h)

Bit

7

1

6

1

5

1

4

0

3

1

2

0

R

1

0

R

0

R

CS0_CTL Reset

CS1_CTL Reset

CS2_CTL Reset

CS3_CTL Reset

CPU Access

0

R/W

Note: R/W = Read/Write; R = Read Only.

Bit

Position

Value Description

[7:5]

CSX_WAIT

000

001

010

011

100

101

110

111

0

0 wait states are asserted when this Chip Select is active.

1 wait state is asserted when this Chip Select is active.

2 wait states are asserted when this Chip Select is active.

3 wait states are asserted when this Chip Select is active.

4 wait states are asserted when this Chip Select is active.

5 wait states are asserted when this Chip Select is active.

6 wait states are asserted when this Chip Select is active.

7 wait states are asserted when this Chip Select is active.

Chip Select is configured as a Memory Chip Select.

Chip Select is configured as an I/O Chip Select.

Chip Select is disabled.

4

CSX_IO

1

3

0

CSX_EN

1

Chip Select is enabled.

[2:0]

000

Reserved.

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Chip Selects and Wait States

eZ80F91 MCU

Product Specification

96

Chip Select x Bus Mode Control Register

The Chip Select Bus Mode register, detailed in Table 29, configures the Chip

Select for eZ80, Z80, Intel™, or Motorola bus modes. Changing the bus mode

allows the eZ80F91 device to interface to peripherals based on the Z80-, Intel™-,

or Motorola-style asynchronous bus interfaces. When a bus mode other than

eZ80 is programmed for a particular Chip Select, the CSx_WAIT setting in that

Chip Select Control Register is ignored.

Table 29. Chip Select x Bus Mode Control Register

(CS0_BMC = 00F0h, CS1_BMC = 00F1h, CS2_BMC = 00F2h, CS3_BMC = 00F3h)

Bit

7

0

6

0

5

0

4

0

R

3

0

2

0

1

0

CS0_BMC Reset

CS1_BMC Reset

CS2_BMC Reset

CS3_BMC Reset

CPU Access

0

1

0

1

0

1

0

R/W

Note: R/W = Read/Write; R = Read Only.

Bit

Position

Value Description

[7:6]

BUS_MODE

00

01

10

11

0

eZ80 bus mode.

Z80 bus mode.

Intel™ bus mode.

Motorola bus mode.

5

Separate address and data.

AD_MUX

1

Multiplexed address and data—appears on data bus

DATA[7:0].

4

0

Reserved.

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Chip Selects and Wait States

eZ80F91 MCU

Product Specification

97

Bit

Position

Value Description

[3:0]

0000 Not valid.

BUS_CYCLE

®

1, 2, 3

0001 Each bus mode state is 1 eZ80 clock cycle in duration.

®

0010 Each bus mode state is 2 eZ80 clock cycles in duration.

®

0011 Each bus mode state is 3 eZ80 clock cycles in duration.

®

0100 Each bus mode state is 4 eZ80 clock cycles in duration.

®

0101 Each bus mode state is 5 eZ80 clock cycles in duration.

®

0110 Each bus mode state is 6 eZ80 clock cycles in duration.

®

0111 Each bus mode state is 7 eZ80 clock cycles in duration.

®

1000 Each bus mode state is 8 eZ80 clock cycles in duration.

®

1001 Each bus mode state is 9 eZ80 clock cycles in duration.

®

1010 Each bus mode state is 10 eZ80 clock cycles in duration.

®

1011 Each bus mode state is 11 eZ80 clock cycles in duration.

®

1100 Each bus mode state is 12 eZ80 clock cycles in duration.

®

1101 Each bus mode state is 13 eZ80 clock cycles in duration.

®

1110 Each bus mode state is 14 eZ80 clock cycles in duration.

®

1111 Each bus mode state is 15 eZ80 clock cycles in duration.

Notes:

1. Setting the BUS_CYCLE to 1 in Intel bus mode causes the ALE pin to not function properly.

2. Use of the external WAIT input pin in Z80 Mode requires that BUS_CYCLE is set to a value

greater than 1.

3. BUS_CYCLE produces no effect in eZ80 mode.

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Chip Selects and Wait States

eZ80F91 MCU

Product Specification

98

Bus Arbiter

The Bus Arbiter within the eZ80F91 allows external bus masters to gain control of

the CPU memory interface bus. During normal operation, the eZ80F91 device is

the bus master. External devices can request master use of the bus by asserting

the BUSREQ pin. The Bus Arbiter forces the CPU to release the bus after com-

pleting the current instruction. When the CPU releases the bus, the Bus Arbiter

asserts the BUSACK pin to notify the external device that it can master the bus.

When an external device assumes control of the memory interface bus, the bus

acknowledge cycle is complete. Table 30 shows the status of the pins on the

eZ80F91 device during bus acknowledge cycles.

During a bus acknowledge cycle, the bus interface pins of the eZ80F91 device

can be used by an external bus master to control the memory and I/O Chip

Selects.

Table 30. eZ80F91 Pin Status During Bus Acknowledge Cycles

Pin Symbol

Signal Direction

Description

ADDR23..ADDR0

Input

Allows external bus master to utilize the

Chip Select logic of the eZ80F91.

CS0

Output

Tristate

Normal operation.

CS1

CS2

CS3

DATA7..0

Allows external bus master to communicate

with external peripherals.

IORQ

MREQ

RD

Input

Allows external bus master to utilize the

Chip Select logic of the eZ80F91.

Input

Allows external bus master to utilize the

Chip Select logic of the eZ80F91.

Tristate

Allows external bus master to communicate

with external peripherals.

WR

Allows external bus master to communicate

with external peripherals.

INSTRD

Allows external bus master to communicate

with external peripherals.

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Bus Arbiter

eZ80F91 MCU

Product Specification

99

Normal bus operation of the eZ80F91 device using CS0 to communicate to an

external peripheral is shown in Figure 19. Figure 20 shows an external bus mas-

ter communicating with an external peripheral during bus acknowledge cycles.

WAIT

RD

WR

eZ80F91 MCU

External

Peripheral

DATA

ADDRESS

IORQ

eZ80F91

MREQ

Chip Select

Wait State

Generator

CS0

CS1

CS2

CS3

Figure 19. Memory Interface Bus Operation During CPU Bus Cycles, Normal Operation

WAIT

RD

WR

External

Master

External

Peripheral

DATA

ADDRESS

IORQ

eZ80F91

MREQ

Chip Select

Wait State

Generator

CS0

CS1

CS2

CS3

Figure 20. Memory Interface Bus Operation During Bus Acknowledge Cycles

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Bus Arbiter

eZ80F91 MCU

Product Specification

100

During bus acknowledge cycles, the Memory and I/O Chip Select logic is con-

trolled by the external address bus and external IORQ and MREQ signals.

The following Chip Select features are not available during bus acknowledge

cycles:

1. The Chip Select logic does not insert wait states during bus acknowledge

cycles regardless of the WAIT configuration for the decoded Chip Select.

2. The bus mode controller does not function during bus acknowledge cycles.

3. Internal registers and memory addresses in the eZ80F91 device are not

accessible during bus acknowledge cycles.

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Bus Arbiter

eZ80F91 MCU

Product Specification

101

Random Access Memory

The eZ80F91 device features 8KB (8192 bytes) of single-port data Random

Access Memory (RAM) for general-purpose use and 8KB of RAM for the Ethernet

MAC. RAM can be enabled or disabled, and it can be relocated to the top of any

64KB page in memory. Data is passed to and from RAM via the 8-bit data bus.

On-chip RAM operates with zero wait states. EMAC RAM is accessed via the bus

arbiter and can execute with zero or one wait states.

General-purpose RAM occupies memory addresses in the RAM Address Upper

Byte register, in the range {RAM_ADDR_U[7:0], E000h} to {RAM_ADDR_U[7:0],

FFFFh}.EMAC RAM occupies memory addresses in the range

{RAM_ADDR_U[7:0], C000h} to {RAM_ADDR_U[7:0], DFFFh}. Following a

RESET, RAM is enabled when RAM_ADDR_U is set to FFh. Figure 21 illustrates

a memory map for on-chip RAM. In this example, RAM_ADDR_U is set to 7Ah.

Figure 21 is not drawn to scale, as RAM occupies only a very small fraction of the

available 16MB address space.

Memory

Location

FFFFFFh

7AFFFFh

8 KB

General-Purpose

RAM

RAM_ADDR_U

7Ah

7AE000h

7ADFFFh

8 KB

EMAC SRAM

7AC000h

000000h

Figure 21. Example: eZ80F91 On-Chip RAM Memory Addressing

When enabled, on-chip RAM assumes priority over on-chip Flash Memory and

any Memory Chip Selects that can also be enabled in the same address space. If

an address is generated in a range that is covered by both the RAM address

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Random Access Memory

eZ80F91 MCU

Product Specification

102

space and a particular Memory Chip Select address space, the Memory Chip

Select is not activated. On-chip RAM is not accessible to external devices during

bus acknowledge cycles.

RAM Control Registers

RAM Control Register

Internal data RAM can be disabled by clearing the GPRAM_EN bit. The default

upon RESET is for RAM to be enabled. See Table 31.

Table 31. RAM Control Register

(RAM_CTL=00B4h)

Bit

7

1

6

1

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

R

Note: R/W = Read/Write; R = Read Only.

Bit

Position

Value

Description

7

0

1

0

1

On-chip general-purpose RAM is disabled.

On-chip general-purpose RAM is enabled.

On-chip EMAC RAM is disabled.

GPRAM_EN

6

ERAM_EN

On-chip EMAC RAM is enabled.

[5:0]

000000 Reserved

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Random Access Memory

eZ80F91 MCU

Product Specification

103

RAM Address Upper Byte Register

The RAM_ADDR_U register defines the upper byte of the address for on-chip

RAM. If enabled, RAM addresses assume priority over all Chip Selects. The

external Chip Select signals are not asserted if the corresponding RAM address is

enabled. See Table 32.

Table 32. RAM Address Upper Byte Register

(RAM_ADDR_U=00B5h)

Bit

7

1

6

1

5

1

4

1

3

1

2

1

0

1

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value Description

00h– This byte defines the upper byte of the RAM address. When

[7:0]

RAM_ADDR_U FFh

enabled, the general-purpose RAM address space ranges

from {RAM_ADDR_U, E000h} to {RAM_ADDR_U, FFFFh}.

When enabled, the EMAC RAM address space ranges from

{RAM_ADDR_U, C000h} to {RAM_ADDR_U, DFFFh}.

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Random Access Memory

eZ80F91 MCU

Product Specification

104

MBIST Control

There are two Memory Built-In Self-Test (MBIST) controllers for the RAM blocks

on the eZ80F91. MBIST_GPR is for General Purpose RAM and MBIST_EMR is

for EMAC RAM. Writing a 1 to MBIST_ON starts the MBIST testing. Writing a 0 to

MBIST_ON stops the MBIST testing. Upon completion of the MBIST testing,

MBIST_ON is automatically reset to 0. If RAM passes MBIST testing,

MBIST_PASS is 1. The value in MBIST_PASS is only valid when MBIST_DONE

is High. See Table 33.

Table 33. MBIST Control Register

(MBIST_GPR=00B6h, MBIST_EMR=00B7h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

R

Note: R/W = Read/Write; R = Read Only.

Bit

Position

Value

Description

7

0

MBIST Testing of the RAM is disabled.

MBIST Testing of the RAM is enabled.

MBIST Testing has not completed.

MBIST Testing has completed.

MBIST Testing has failed.

MBIST_ON

1

6

0

MBIST_DONE

1

5

0

MBIST_PASS

1

MBIST Testing has passed.

Reserved

[4:0]

00000

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Random Access Memory

eZ80F91 MCU

Product Specification

105

Flash Memory

Flash Memory Arrangement in the eZ80F91 Device

The eZ80F91 device features 256KB (262,144 bytes) of nonvolative Flash mem-

ory with Read/Write/Erase capability. The main Flash memory array is arranged in

128 pages with 8 rows per page and 256 bytes per row. In addition to main Flash

memory, there are two separately-addressable rows which comprise a 512-byte

information page.

256KB of main storage can be protected in eight 32KB blocks. Protecting a 32KB

block prevents Write or Erase operations. The lower 32KB block (00000h

–

07FFFh can be protected using the external WP pin. This portion of memory is

)

called the Boot Block because the CPU always starts executing code from this

location at startup. If the application requires external program memory, then the

Boot Block must at least contain a jump instruction to move the Program Counter

outside of the Flash memory space.

The Flash memory arrangement is illustrated in Figure 22.

16

8

2 KB pages

per block

256-byte rows

per page

32 KB blocks

F

E

D

C

B

A

9

8

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

256

single-byte columns

per row

255 254

1

0

Figure 22. eZ80F91 Flash Memory Arrangement

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Flash Memory

eZ80F91 MCU

Product Specification

106

Flash Memory Overview

The eZ80F91 device includes a Flash memory controller that automatically con-

verts standard CPU Read and Write cycles to the specific protocol required for the

Flash memory array. As such, standard memory Read and Write instructions

access the Flash memory array as if it is internal RAM. The controller also sup-

ports I/O access to the Flash memory array, in effect presenting it as an indirectly-

addressable bank of I/O registers. These access methods are also supported via

the ZDI and OCI interfaces.

In addition, eZ80Acclaim! Flash Microcontrollers support a Flash Read–While–

®

Write methodology. In essence, the eZ80 CPU can continue to read and execute

code from an area of Flash memory while a nonconflicting area of Flash memory

is being programmed.

The Flash memory controller contains a frequency divider, a Flash register inter-

face, and a Flash control state machine. A simplified block diagram of the Flash

controller is illustrated in Figure 23.

Clock Divider

8-bit downcounter

System Clock

17

8

ADDR

D_OUT

FD_OUT

8

eZ80 Core

Interface

FADDR

FD_IN

17

8

Flash

256 KB

+

FCNTL

9

Flash

State

Machine

512 bytes

MAIN_INFO

Flash

Control

Registers

CPUD_OUT

8

FLASH_IRQ

Figure 23. Flash Memory Block Diagram

Reading Flash Memory

The main Flash memory array can be read using both Memory and I/O opera-

tions. As an auxiliary storage area, the information page is only accessible via I/O

operations. In all cases, wait states are automatically inserted to allow for read

access time.

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Memory Read

A memory Read operation uses the address bus and data bus of the eZ80F91

device to read a single data byte from Flash memory. This Read operation is sim-

ilar to reads from RAM. To perform Flash memory reads, the FLASH_CTRL regis-

ter must be configured to enable memory access to Flash with the appropriate

number of wait states. See Table 37 on page 113.

Only the main area of Flash memory is accessible via memory reads. The infor-

mation page must be read using I/O access.

I/O Read

A single-byte I/O Read operation uses I/O registers for setting the column, page,

and row address to be read. A Read of the FLASH_DATA register returns the con-

tents of Flash memory at the designated address. Each access to the

FLASH_DATA register causes an autoincrement of the Flash address stored in

the Flash address registers (FLASH_PAGE, FLASH_ROW, FLASH_COL). To

allow for Flash memory access time, the FLASH_CTRL register must be config-

ured with the appropriate number of wait states. See Table 37 on page 113.

Programming Flash Memory

Flash memory is programmed using standard I/O or memory Write operations that

the Flash memory controller automatically translates to the detailed timing and

protocol required for Flash memory. The more efficient multibyte (row) program-

ming mode is only available via I/O Writes.

To ensure data integrity and device reliability, two main restrictions exist on pro-

gramming of Flash memory:

Note:

1. The cumulative programming time since the last erase cannot exceed 31ms

for any given row.

2. The same byte cannot be programmed more than twice since the last erase.

Single-Byte I/O Write

A single-byte I/O Write operation uses I/O registers for setting the column, page,

and row address to be written. The FLASH_DATA register stores the data to be

written. While the CPU executes an I/O instruction to load the data into the

FLASH_DATA register, the Flash controller asserts the internal WAIT signal to

stall the CPU until the Flash Write operation is complete. A single-byte Write takes

between 66µs and 85µs to complete. Programming an entire row (256 bytes)

using single-byte Writes therefore takes no more than 21.8ms. This duration of

time does not include the time required by the CPU to transfer data to the regis-

ters, which is a function of the instructions employed and the system clock fre-

quency. Each access to the FLASH_DATA register causes an autoincrement of

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the Flash address stored in the Flash Address registers (FLASH_PAGE,

FLASH_ROW, FLASH_COL).

A typical sequence that performs a single-byte I/O Write is shown below. Because

the Write is self-timed, Step 2 of the sequence can be repeated back-to-back

without requiring polling or interrupts.

1. Write the FLASH_PAGE, FLASH_ROW, and FLASH_COL registers with the

address of the byte to be written.

2. Write the data value to the FLASH_DATA register.

Multibyte I/O Write (Row Programming)

Multibyte I/O Write operations use the same I/O registers as single-byte Writes.

Multibyte I/O Writes allow the programming of a full row and are enabled by set-

ting the ROW_PGM bit of the Flash Program Control Register. For multibyte I/O

Writes, the CPU sets the address registers, enables row programming, and then

executes an I/O instruction (with repeat) to load the block of data into the

FLASH_DATA register. For each individual byte written to the FLASH_DATA reg-

ister during the block move, the Flash controller asserts the internal WAIT signal

to stall the CPU until the current byte is programmed. Each access to the

FLASH_DATA register causes an autoincrement of the Flash address stored in

the Flash Address registers (FLASH_PAGE, FLASH_ROW, FLASH_COL).

During row programming, the Flash controller continuously asserts the Flash

memory’s high voltage signal until all bytes are programmed (column address <

255). As a result, the row programs more quickly than if the high-voltage signal is

toggled for each byte. The per-byte programming time during row programming is

between 41µs and 52µs. As such, programming 256 bytes of a row in this mode

takes no more than 13.4ms, leaving 17.6ms for CPU instruction overhead to fetch

the 256 bytes.

A typical sequence that performs a multibyte I/O Write is shown below.

1. Check the FLASH_IRQ register to ensure that any previous row program is

completed.

2. Write the FLASH_PAGE, FLASH_ROW, and FLASH_COL registers with the

address of the first byte to be written.

3. Set the ROW_PGM bit in the FLASH_PGCTL register to enable row

programming mode.

4. Write the next data value to the FLASH_DATA register.

5. If the end of the row has not been reached, return to Step 4.

During row programming, software must monitor the row time-out error bit either

by enabling this interrupt or via polling. If a row time-out occurs, the Flash control-

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ler aborts the row programming operation, and software must assure that no fur-

ther Writes are performed to the row without it first being erased. It is suggested

that row programming only be used one time per row and not in combination with

single-byte Writes to the same row without first erasing it. Otherwise, the burden

is on software to ensure that the 31ms maximum cumulative programming time

between erases is not exceeded for a row.

Memory Write

A single-byte memory Write operation uses the address bus and data bus of the

eZ80F91 device for programming a single data byte to Flash memory. While the

CPU executes a Load instruction, the Flash controller asserts the internal WAIT

signal to stall the CPU until the Write is complete. A single-byte Write takes

between 66µs and 85µs to complete. Programming an entire row using memory

Writes therefore takes no more than 21.8ms. This duration of time does not

include time required by the CPU to transfer data to the registers, which is a func-

tion of the instructions employed and the system clock frequency.

The memory Write function does not support multibyte row programming.

Because memory Writes are self-timed, they can be performed back-to-back with-

out requiring polling or interrupts.

Erasing Flash Memory

Erasing bytes in Flash memory returns them to a value of FFh. Both the MASS

and PAGE ERASE operations are self-timed by the Flash controller, leaving the

CPU free to execute other operations in parallel. The DONE status bit in the Flash

Interrupt Control Register can be polled by software or used as an interrupt

source to signal completion of an Erase operation. If the CPU attempts to access

Flash memory while an erase is in progress, the Flash controller forces a wait

state until the Erase operation is completed.

Mass Erase

Performing a MASS ERASE operation on Flash memory erases all bits contained

in Flash, including the information page. This self-timed operation takes approxi-

mately 200ms to complete.

Page Erase

The smallest erasable unit in Flash memory is a page. The pages to be erased,

whether they are the 128 main Flash memory pages or the information page, is

determined by the setting of the FLASH_PAGE register. This self-timed operation

takes approximately 10ms to complete.

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Information Page Characteristics

As noted earlier, the information page is not accessible using memory access

instructions and must be accessed via the I/O register. The Flash Page Select

Register contains a bit which selects the information page for I/O access.

There are two ways to erase the information page. The user can execute a MASS

ERASE operation, or the user can configure the Flash Page Select Register to

select the information page, and then execute a PAGE ERASE.

Flash Control Registers

The Flash Control Register interface contains all of the registers used in Flash

memory. The definitions in this section describe each register.

Flash Key Register

Writing the two-byte sequence B6h, 49h in immediate succession to this register

unlocks the Flash Divider and Flash Write/Erase Protection registers. If these val-

ues are not written by consecutive CPU I/O Writes (I/O reads and memory Read/

Writes have no effect), the Flash Divider and Flash Write/Erase Protection regis-

ters remain locked. This prevents accidental overwrites of these critical Flash con-

trol register settings. Writing a value to either the Flash Frequency Divider register

or the Flash Write/Erase Protection register automatically relocks both of the reg-

isters. See Table 34.

Table 34. Flash Key Register

(FLASH_KEY = 00F5h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: W = Write Only.

W

Bit

Position

Value Description

B6h, Sequential Write operations of the values B6h, 49h to this

[7:0]

FLASH_KEY

49h

register will unlock the Flash Frequency Divider and Flash

Write/Erase Protection registers.

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Flash Data Register

The Flash Data register stores the data values to be programmed into Flash

memory via I/O Write operations. An I/O Read of the Flash Data register returns

data from Flash memory. The Flash memory address used for I/O access is deter-

mined by the contents of the page, row, and column registers. Each access to the

FLASH_DATA register causes an autoincrement of the Flash address stored in

the Flash Address registers (FLASH_PAGE, FLASH_ROW, FLASH_COL). See

Table 35.

Table 35. Flash Data Register

(FLASH_DATA = 00F6h)

Bit

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

X

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value Description

00h-

[7:0]

Data value to be written to Flash memory during an I/O Write

operation, or the data value that is read in Flash memory,

indicated by the Flash Address registers (FLASH_PAGE,

FLASH_ROW, FLASH_COL).

FLASH_DATA FFh

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Flash Address Upper Byte Register

The FLASH_ADDR_U register defines the upper 6 bits of the Flash memory

address space. Changing the value of FLASH_ADDR_U allows on-chip 256KB

Flash memory to be mapped to any location within the 16MB linear address

space of the eZ80F91 device. If on-chip Flash memory is enabled, the Flash

address assumes priority over any external Chip Selects. The external Chip

Select signals are not asserted if the corresponding Flash address is enabled.

Internal Flash memory does not hold priority over internal SRAM. See Table 36.

Table 36. Flash Address Upper Byte Register

(FLASH_ADDR_U = 00F7h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

R

Note: R/W = Read/Write; R = Read Only.

Bit

Position

Value Description

00h– These bits define the upper byte of the Flash address. When

[7:2]

FLASH_ADDR_U FCh

on-chip Flash is enabled, the Flash address space begins at

address {FLASH_ADDR_U, 00b, 0000h}. On-chip Flash has

priority over all external Chip Selects.

[1:0]

00

Reserved (enforces alignment on a 256KB boundary).

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Flash Control Register

The Flash Control register enables or disables memory access to Flash memory.

I/O access to the Flash control registers and to Flash memory is still possible

while Flash memory space access is disabled.

The minimum access time of internal Flash memory is 60ns. The Flash Control

Register must be configured to provide the appropriate number of wait states

based on the system clock frequency of the eZ80F91 device. Because the maxi-

mum SCLK frequency is 50MHZ (20ns), the default upon RESET is for four wait

states to be inserted for Flash memory access (Flash memory access + one eZ80

Bus Cycle = 60ns + 20ns = 80ns; 80ns ÷ 20ns = 4 wait states). See Table 37.

Table 37. Flash Control Register

(FLASH_CTRL = 00F8h)

Bit

7

1

6

0

5

0

4

0

3

1

2

0

1

0

Reset

CPU Access

R/W

R

R/W

R

Note: R/W = Read/Write, R = Read Only.

Bit

Position

Value Description

[7:5]

FLASH_WAIT

000

001

010

011

100

101

110

111

0

0 wait states are inserted when the Flash is active.

1 wait state is inserted when the Flash is active.

2 wait states are inserted when the Flash is active.

3 wait states are inserted when the Flash is active.

4 wait states are inserted when the Flash is active.

5 wait states are inserted when the Flash is active.

6 wait states are inserted when the Flash is active.

7 wait states are inserted when the Flash is active.

Reserved

[4]

[3]

0

Flash memory access is disabled.

FLASH_EN

1

Flash memory access is enabled.

[2:0]

000

Reserved

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Flash Frequency Divider Register

The 8-bit frequency divider allows the programming of Flash memory over a

range of system clock frequencies. Flash can be programmed with system clock

frequencies ranging from 154kHz to 50MHz. The Flash controller requires an

input clock with a period that falls within the range of 5.1−6.5µs. The period of the

Flash controller clock is set in the Flash Frequency Divider Register. Writes to this

register are allowed only after it is unlocked via the FLASH_KEY register. The

Flash Frequency Divider Register value required vs. the system clock frequency

is shown in Table 38. System clock frequencies outside of the ranges shown are

not supported. Register values for the Flash Frequency Divider are shown in

Table 39.

Table 38. Flash Frequency Divider Values

System Clock Frequency

154–196kHz

Flash Frequency Divider Value

1

308–392kHz

2

462–588kHz

3

616kHz–50MHz

CEILING [System Clock Frequency (MHz) x 5.1 (µs)]*

Note: *The CEILING function rounds fractional values up to the next whole number. For example,

CEILING(3.01) is 4.

Table 39. Flash Frequency Divider Register

(FLASH_FDIV = 00F9h)

Bit

7

6

5

4

3

2

1

0

Reset

0

1

CPU Access

R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W

Note: R/W = Read/Write, R = Read Only. *Key sequence required to enable Writes

Bit

Position

Value Description

[7:0]

01h– Divider value for generating the required 5.1-6.5µs Flash

FLASH_FDIV

FFh

controller clock period.

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Flash Write/Erase Protection Register

The Flash Write/Erase Protection register prevents accidental Write or Erase

operations. The protection is limited to a resolution of eight 32KB blocks. Setting a

bit to 1 protects that 32KB block of Flash memory from accidental Writes or

erases. The default upon RESET is for all Flash memory blocks to be protected.

The WP pin works in conjunction with FLASH_PROT[0] to protect the lowest

block (also called the Boot Block) of Flash memory. If either the WP is held

asserted or FLASH_PROT[0] is set, the Boot Block is protected from Write and

Erase operations.

A protect bit is not available for the information page. The information page is,

however, protected from a MASS ERASE if any pages are protected in

FLASH_PROT or WP is asserted.

Note:

Writes to this register are allowed only after it is unlocked via the FLASH_KEY

register. Any attempted Writes to this register while locked will set it to FFh,

thereby protecting all blocks. See Table 40.

Table 40. Flash Write/Erase Protection Register

(FLASH_PROT = 00FAh)

Bit

7

6

5

4

3

2

1

0

Reset

1

CPU Access

R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*

Note: R/W = Read/Write if unlocked, R = Read Only if locked. *Key sequence required to unlock.

Bit

Position

Value Description

[7]

0

1

0

1

0

1

0

1

Disable Write/Erase Protect on block 38000h to 3FFFFh.

BLK7_PROT

Enable Write/Erase Protect on block 38000h to 3FFFFh.

Disable Write/Erase Protect on block 30000h to 37FFFh.

Enable Write/Erase Protect on block 30000h to 37FFFh.

Disable Write/Erase Protect on block 28000h to 2FFFFh.

Enable Write/Erase Protect on block 28000h to 2FFFFh.

Disable Write/Erase Protect on block 20000h to 27FFFh.

Enable Write/Erase Protect on block 20000h to 27FFFh.

[6]

BLK6_PROT

[5]

BLK5_PROT

[4]

BLK4_PROT

Note: The lower 32KB block (00000h to 07FFFh—BLK0) is called the Boot Block and can be

protected using the external WP pin.

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Bit

Position

Value Description

[3]

0

1

0

1

0

1

0

1

Disable Write/Erase Protect on block 18000h to 1FFFFh.

Enable Write/Erase Protect on block 18000h to 1FFFFh.

Disable Write/Erase Protect on block 10000h to 17FFFh.

Enable Write/Erase Protect on block 10000h to 17FFFh.

Disable Write/Erase Protect on block 08000h to 0FFFFh.

Enable Write/Erase Protect on block 08000h to 0FFFFh.

Disable Write/Erase Protect on block 00000h to 07FFFh.

Enable Write/Erase Protect on block 00000h to 07FFFh.

BLK3_PROT

[2]

BLK2_PROT

[1]

BLK1_PROT

[0]

BLK0_PROT

Note: The lower 32KB block (00000h to 07FFFh—BLK0) is called the Boot Block and can be

protected using the external WP pin.

Flash Interrupt Control Register

There are two sources of interrupts from the Flash controller. These two sources

are:

•

Page Erase, Mass Erase, or Row Program completed successfully.

An error condition occurred

Either or both of these two interrupt sources can be enabled by setting the appro-

priate bits in the Flash Interrupt Control register.

The Flash Interrupt Control register contains four status bits to indicate the follow-

ing error conditions:

Row Program Time-Out. This bit signals a time-out during Row Programming. If

the current row program operation does not complete within 4864 Flash controller

clocks, the Flash controller terminates the row program operation by clearing bit 2

of the Flash Program Control Register and setting the RP_TM0 error bit to 1.

Write Violation. This bit indicates an attempt to write to a protected block of Flash

memory (the Write was not performed).

Page Erase Violation. This bit indicates an attempt to erase a protected block of

Flash memory (the requested page was not erased).

Mass Erase Violation. This bit indicates an attempt to MASS ERASE when there

are one or more protected blocks in Flash memory (the MASS ERASE was not

performed).

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If the error condition interrupt is enabled, any of these four error conditions result

in an interrupt request being sent to the eZ80F91device’s interrupt controller.

Reading the Flash Interrupt Control register clears all error condition flags and the

DONE flag. See Table 41.

Table 41. Flash Interrupt Control Register

(FLASH_IRQ = 00FBh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

R

Note: R/W = Read/Write, R = Read Only. Read resets bits [5] and [3:0].

Bit

Position

Value Description

[7]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Flash Erase/Row Program Done Interrupt is disabled.

Flash Erase/Row Program Done Interrupt is enabled.

Error Condition Interrupt is disabled.

DONE_IEN

[6]

ERR_IEN

Error Condition Interrupt is enabled.

[5]

DONE

Erase/Row Program Done Flag is not set.

Erase/Row Program Done Flag is set.

Reserved.

[4]

[3]

WR_VIO

The Write Violation Error Flag is not set.

The Write Violation Error Flag is set.

[2]

RP_TMO

The Row Program Time-Out Error Flag is not set.

The Row Program Time-Out Error Flag is set.

The Page Erase Violation Error Flag is not set.

The Page Erase Violation Error Flag is set.

The Mass Erase Violation Error Flag is not set.

The Mass Erase Violation Error Flag is set.

[1]

PG_VIO

[0]

MASS_VIO

Note: The lower 32KB block (00000h to 07FFFh) is called the Boot Block and can be protected

using the external WP pin. Attempts to page erase BLK0 or mass erase Flash when WP is

asserted result in failure and signal an erase violation.

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Flash Page Select Register

The msb of this register is used to select whether I/O Flash access and PAGE

ERASE operations are directed to the 512-byte information page or to the main

Flash memory array. The lower 7 bits are used to select one of the main 128

pages for PAGE ERASE or I/O operations.

To perform a PAGE ERASE, the software must set the proper page value prior to

setting the page erase bit in the Flash Control Register. In addition, each access

to the FLASH_DATA register causes an autoincrement of the Flash address

stored in the Flash Address registers (FLASH_PAGE, FLASH_ROW,

FLASH_COL). See Table 42.

Table 42. Flash Page Select Register

(FLASH_PAGE = 00FCh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

Note: R/W = Read/Write, R = Read Only.

Bit

Position

Value Description

[7]

INFO_EN

0

1

Flash I/O access to main Flash memory.

Flash I/O access to the information page. PAGE ERASE and

MASS ERASE operations only affect the information page.

[6:0]

00h– Page address of Flash memory to be used during the PAGE

FLASH_PAGE FFh

ERASE or I/O access of main Flash memory. When INFO_EN

is set to 1, this field is ignored.

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Flash Row Select Register

The Flash Row Select Register is a 3-bit value used to define one of the 8 rows of

Flash on a single page. This register is used for all I/O access to Flash memory. In

addition, each access to the FLASH_DATA register causes an autoincrement of

the Flash address stored in the Flash Address registers (FLASH_PAGE,

FLASH_ROW, FLASH_COL). See Table 43.

Table 43. Flash Row Select Register

(FLASH_ROW = 00FDh)

Bit

7

X

R

6

X

R

5

X

R

4

X

R

3

X

R

2

0

1

0

Reset

CPU Access

R/W

Note: R/W = Read/Write, R = Read Only.

Bit

Position

Value Description

00h Reserved.

[7:3]

[2:0]

FLASH_ROW

0h–7h Row address of Flash memory to be used during an I/O access

of Flash memory. When INFO_EN is 1 in the Flash Page

Select Register, values for this field are restricted to 0h–1h,

which selects between the two rows in the information page.

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Flash Column Select Register

The Flash Column Select Register is an 8-bit value used to define one of the 256

bytes of Flash memory contained in a single row. This register is used for all I/O

access to Flash memory. In addition, each access to the FLASH_DATA register

causes an autoincrement of the Flash address stored in the Flash Address regis-

ters (FLASH_PAGE, FLASH_ROW, FLASH_COL). See Table 44.

Table 44. Flash Column Select Register

(FLASH_COL = 00FEh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

Note: R/W = Read/Write, R = Read Only.

Bit

Position

Value Description

00h– Column address of Flash memory to be used during an I/O

FFh access of Flash memory.

[7:0]

FLASH_COL

Flash Program Control Register

The Flash Program Control Register is used to perform the functions of MASS

ERASE, PAGE ERASE, and ROW PROGRAM.

MASS ERASE and PAGE ERASE are self-clearing functions. MASS ERASE

requires approximately 200ms to erase the full 256KB of main Flash and the 512-

byte information page. PAGE ERASE requires approximately 10ms to erase a

2KB page. Upon completion of either a MASS ERASE or PAGE ERASE, the

value of each corresponding bit is reset to 0.

While Flash is being erased, any Read or Write access to Flash forces the CPU

into a wait state until the Erase operation is complete and the Flash can be

accessed. Reads and Writes to areas other than Flash memory can proceed as

usual while an Erase operation is underway.

During row programming, any reads of Flash memory force a WAIT condition until

the row programming operation completes or times out. See Table 45.

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Table 45. Flash Program Control Register

(FLASH_PGCTL = 00FFh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R

R/W

Note: R/W = Read/Write, R = Read Only.

Bit

Position

Value Description

[7:3]

00h

0

Reserved.

Row Program Disable or Row Program completed.

[2]

ROW_PGM

1

Row Program Enable. This bit automatically resets to 0 when

the row address reaches 256 or when the Row Program

operation times out.

[1]

0

1

Page Erase Disable (Page Erase completed).

PG_ERASE

Page Erase Enable. This bit automatically resets to 0 when

the PAGE ERASE operation is complete.

[0]

0

1

Mass Erase Disable (Mass Erase completed).

MASS_ERASE

Mass Erase Enable. This bit automatically resets to 0 when

the MASS ERASE operation is complete.

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Watch-Dog Timer

Watch-Dog Timer Overview

The Watch-Dog Timer (WDT) helps protect against corrupt or unreliable software,

power faults, and other system-level problems which can place the CPU into

unsuitable operating states. The eZ80F91 WDT features:

18 22 25

27

•

Four programmable time-out periods: 2 , 2 , 2 , and 2 clock cycles

Three selectable WDT clock sources:

–

Internal RC oscillator

System clock

Real-Time Clock source (on-chip 32Khz crystal oscillator or 50/60Hz

signal)

•

A selectable time-out response: a time-out can be configured to generate

either a RESET or a nonmaskable interrupt (NMI)

A WDT time-out RESET indicator flag

Figure 24 illustrates a block diagram of the Watch-Dog Timer.

Data[7:0]

Control Register/

Reset Register

WDT_CLK

RTC Clock

28-Bit

Upcounter

System Clock

WDT Control Logic

Time-out Compare Logic

(WDT_PERIOD)

WDT

Oscillator

RESET

®

NMI to eZ80 CPU

Figure 24. Watch-Dog Timer Block Diagram

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Watch-Dog Timer Operation

Enabling and Disabling the WDT

The Watch-Dog Timer is disabled upon a RESET. To enable the WDT, the applica-

tion program must set WDT_EN, which corresponds to bit 7 of the WDT_CTL reg-

ister. After WDT_EN is set, no Writes are allowed to the WDT_CTL register. When

enabled, the WDT cannot be disabled, except by a RESET.

Time-Out Period Selection

18 22 25

27

There are four choices of time-out periods for the WDT—2 , 2 , 2 , and 2

timer clock cycles. The WDT time-out period is defined by the WDT_PERIOD field

of the WDT_CTL register (WDT_CTL[1:0]). The approximate time-out periods for

two different WDT clock sources are listed in Table 46. The approximate time-out

period for the third WDT clock source is listed in Table 47.

Table 46. Watch-Dog Timer Approximate Time-Out Delays

Divider

Value

Time Out

Delay

Clock Source

18

32.768KHz Crystal Oscillator

50MHz System Clock

2

8.00s

128s

22

2

25

2

1024s

4096s

5.2ms

83.9ms

0.67s

2.68s

27

2

18

2

22

50MHz System Clock

2

25

50MHz System Clock

2

27

50MHz System Clock

2

Table 47. Watch-Dog Timer Approximate Time-Out Delays w/ Internal RC Oscillator

Divider

Value

Minimum

Time-Out Delay Time-Out Delay

Typical

Clock Source

18

Internal RC Oscillator

2

16s

26s

419s

22

2

262s

25

2

2100s

8390s

3360s

13400s

27

2

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RESET Or NMI Generation

A WDT time-out causes a RESET or sends a nonmaskable interrupt (NMI) signal

to the CPU. The default operation is for the WDT to cause a RESET.

If the NMI_OUT bit in the WDT_CTL register is set to 0, then upon a WDT time-

out, the RST_FLAG bit in the WDT_CTL register is set to 1. The RST_FLAG bit

can be polled by the CPU to determine the source of the RESET event.

If the NMI_OUT bit in the WDT_CTL register is set to 1, then upon time-out, the

WDT asserts an NMI for CPU processing. The NMI_FLAG bit can be polled by the

CPU to determine the source of the NMI event.

Watch-Dog Timer Registers

Watch-Dog Timer Control Register

The Watch-Dog Timer Control register, detailed in Table 48, is an 8-bit Read/Write

register used to enable the Watch-Dog Timer, set the time-out period, indicate the

source of the most recent RESET or NMI, and select the required operation upon

WDT time-out.

The default clock source for the Watch-Dog Timer is the WDT oscillator

(WDT_CLK = 10b). To power-down the WDT oscillator, another clock source must

be selected. The power-up sequence of the WDT oscillator takes approximately

20ms.

Table 48. Watch-Dog Timer Control Register

(WDT_CTL = 0093h)

Bit

7

0

6

0

5

0/1

R

4

0

3

1

2

0

1

0

Reset

CPU Access

R/W

R

R/W

Note: R = Read only; R/W = Read/Write.

Bit

Position

Value Description

7

0

1

WDT is disabled.

WDT_EN

WDT is enabled. When enabled, the WDT cannot be disabled

without a RESET.

6

0

1

WDT time-out resets the CPU.

NMI_OUT

WDT time-out generates a nonmaskable interrupt (NMI) to the

CPU.

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Bit

Position

Value Description

5

0

1

RESET caused by external full-chip reset or ZDI reset.

RST_FLAG

RESET caused by WDT time-out. This flag is set by the WDT

time-out, only if the NMI_OUT flag is set to 0. The CPU can

poll this bit to determine the source of the RESET. This flag is

cleared by a non-WDT generated reset.

4

0

1

NMI caused by external source.

NMI_FLAG

NMI caused by WDT time-out. This flag is set by the WDT

time-out, only if the NMI_OUT flag is set to 1. The CPU can

poll this bit to determine the source of the NMI. This flag is

cleared by a non-WDT NMI.

[3:2]

WDT_CLK

00

01

WDT clock source is system clock.

WDT clock source is Real-Time Clock source (32KHz on-chip

oscillator or 50/60Hz input as set by RTC_CTRL[4]).

10

11

00

01

10

11

WDT clock source is internal RC oscillator (10KHz typical).

Reserved

27

[1:0]

WDT_PERIOD

WDT time-out period is 2 clock cycles.

25

WDT time-out period is 2 clock cycles.

22

WDT time-out period is 2 clock cycles.

18

WDT time-out period is 2 clock cycles.

Note: When the WDT is enabled, no Writes are allowed to the WDT_CTL register.

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Watch-Dog Timer Reset Register

The Watch-Dog Timer Reset register, detailed in Table 49, is an 8-bit Write Only

register. The Watch-Dog Timer is reset when an A5hvalue followed by a 5Ahvalue

is written to this register. Any amount of time can occur between the writing of the

A5hvalue and the 5Ahvalue, so long as the WDT time-out does not occur prior to

completion. Any value other than 5Ahwritten to the Watch-Dog Timer Reset regis-

ter after the A5hvalue requires that the sequence of Writes (A5h,5Ah) be restarted

for the timer to be reset.

Table 49. Watch-Dog Timer Reset Register

(WDT_RR = 0094h)

Bit

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

X

Reset

CPU Access

W

Note: X = Undefined; W = Write Only.

Bit

Position

Value Description

[7:0]

WDT_RR

A5h

The first Write value required to reset the WDT prior to a time-

out.

5Ah

The second Write value required to reset the WDT prior to a

time-out. If an A5h,5Ah sequence is written to WDT_RR, the

WDT timer is reset to its initial count value, and counting

resumes.

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Programmable Reload Timers

Programmable Reload Timers Overview

The eZ80F91 device features four programmable reload timers. The core of each

timer is a 16-bit downcounter. In addition, each timer features a selectable clock

source, adjustable prescaling and can operate in either SINGLE PASS or CON-

TINUOUS mode.

In addition to the basic timer functionality, some of the timers support specialty

modes that perform event counting, input capture, output compare, and PWM

generation functions. PWM mode supports four individually-configurable outputs

and a power trip function.

Each of the 4 timers available on the eZ80F91 device can be controlled individu-

ally. They do not share the same counters, reload registers, control registers, or

interrupt signals. A simplified block diagram of a programmable reload timer is

illustrated in Figure 25.

Each timer features its own interrupt, which is triggered either by the timer reach-

ing zero or after a successful comparison occurs. As with the other eZ80F91 inter-

rupts, the priority is fully programmable.

Input Capture

Registers

CONTROL

ICx

R

E

L

O

A

D

16-Bit

Down Counter

Comparator

OCx

16

SCLK

DIV

Output Compare

Registers

M

U

X

RTC CLK

ECx

PWM

OC PWR Trip

PWM

Control

PWM

EOC

IC

IRQ Control

IRQ

Figure 25. Programmable Reload Timer Block Diagram

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Basic Timer Operation

Basic timer operation is controlled by a timer control register and a programmable

reload value. The CPU uses the control register to set up the prescaling, the input

clock source, the end-of-count behavior, and to start the timer. The 16-bit reload

value is used to determine the duration of the timer’s count before either halting or

reloading.

After choosing a timer period and writing the appropriate values to the reload reg-

isters, the CPU must set the timer enable bit (TMRx_CTL[TIM_EN]), allowing the

count to begin. The reload bit (TMRx_CTL[RLD]) should also be asserted so that

the timer counts down from the reload value, rather than from 0000h. On the sys-

tem clock cycle, after the assertion of the reload bit, the timer loads with the 16-bit

reload value and begins counting down. The reload bit is automatically cleared

after the loading operation. The timer can be enabled and reloaded on the same

cycle; however, the timer does not require disabling to reload; reloading can be

performed at any time. It is also possible to halt the timer by deasserting the timer

enable bit and resuming the count at a later time from the same point by reassert-

ing the bit.

Reading the Current Count Value

The CPU can read the current count value while the timer is running. Because the

count is a 16-bit value, the hardware latches the value of the upper byte into tem-

porary storage when the lower byte is read. This value in temporary storage is the

value returned when the upper byte is read. Therefore, the firmware should read

the lower byte first. If it attempts to read the upper byte first, it does not obtain the

current upper byte of the count. Instead, it obtains the last latched value. This

Read operation does not affect timer operation.

Setting Timer Duration

There are three factors to consider when determining Programmable Reload

Timer duration: clock frequency, clock divider ratio, and initial count value. Mini-

mum duration of the timer is achieved by loading 0001h. Maximum duration is

achieved by loading 0000h, because the timer first rolls over to FFFFh, then con-

tinues counting down to 0000hbefore the end-of-count is signaled. Depending

upon the TMRx_CTL[CLK_SEL] bits of the control register, the clock is either the

system clock, the on-chip RC oscillator output or an input from a pin.

The time-out period of the timer is returned by the following equation:

Clock Divider Ratio x Reload Value

Time-Out Period

=

System Clock Frequency

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To calculate the time-out period with the above equation when using an initial

value of 0000h, enter a reload value of 65536 (FFFFh+ 1).

Minimum time-out duration is 4 times longer than the input clock period and is

generated by setting the clock divider ratio to 1:4 and the reload value to 0001h.

24

Maximum time-out duration is 2 (16,777,216) times longer than the input clock

period, and is generated by setting the clock divider ratio to 1:256 and the reload

value to 0000h.

Single Pass Mode

In SINGLE PASS mode, when the end-of-count value (0000h), is reached, count-

ing halts, the timer is disabled, and the TMRx_CTL[TIM_EN] bit resets to 0. To

reenable the timer, the CPU must set the TIM_EN bit to 1. An example of a PRT

operating in SINGLE PASS mode is illustrated in Figure 26. Timer register infor-

mation is indicated in Table 50.

System Clock

Clock Enable

TMR3_CTL Write

(Timer Enable)

T3 Count

0

4

3

2

1

0

Interrupt Request

Figure 26. Example: PRT SINGLE PASS Mode Operation

Table 50. Example: PRT SINGLE PASS Mode Parameters

Parameter

Control Register(s)

Value

Timer Enable

TMR

x

_CTL[TIM_EN]

_CTL[RLD]

1

Reload

1

Prescaler Divider = 4

SINGLE PASS Mode

End of Count Interrupt Enable

Timer Reload Value

_CTL[CLK_DIV]

_CTL[TIM_CONT]

00b

0

_IER[IRQ_EOC_EN]

_RR_H, TMRx_RR_L}

1

{TMR

x

0004h

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Continuous Mode

In CONTINUOUS mode, when the end-of-count value, 0000h, is reached, the

timer automatically reloads the 16-bit start value from the Timer Reload registers,

TMRx_RR_H and TMRx_RR_L. Downcounting continues on the next clock edge

and the timer continues to count until disabled. An example of the timer operating

in CONTINUOUS mode is illustrated in Figure 27. Timer register information is

indicated in Table 51.

System Clock

Clock Enable

TMR3_CTL Write

(Timer Enable)

T3 Count

X

4

3

2

1

4

3

2

1

Interrupt

Request

Figure 27. Example: PRT CONTINUOUS Mode Operation

Table 51. Example : PRT CONTINUOUS Mode Parameters

Parameter

Control Register(s)

Value

Timer Enable

TMR

x

_CTL[TIM_EN]

_CTL[RLD]

1

Reload

1

Prescaler Divider = 4

CONTINUOUS Mode

End of Count Interrupt Enable

Timer Reload Value

_CTL[CLK_DIV]

_CTL[TIM_CONT]

_IER[IRQ_EOC_EN]

00b

1

{TMR

x

_RR_H, TMR

x

_RR_L}

0004h

Timer Interrupts

The terminal count flag, TMRx_IIR[EOC], is set to 1 whenever the timer reaches

0000h, its end-of-count value in SINGLE PASS mode, or when the timer reloads

the start value in CONTINUOUS mode. The terminal count flag is only set when

the timer reaches 0000h(or reloads) from 0001h. The timer interrupt flag is not set

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to 1 when the timer is loaded with the value 0000h, which selects the maximum

time-out period.

The CPU can be programmed to poll the EOC bit for the time-out event. Alterna-

tively, an interrupt service request signal can be sent to the CPU by setting the

TMRx_IER[EOC] bit to 1. Then, when the end-of-count value (0000h) is reached

and the EOC bit is set to 1, an interrupt service request signal is passed to the

CPU. The interrupt service request signal is deactivated by an CPU Read of the

timer interrupt identification register, TMRx_IIR. All bits in that register are reset by

the Read.

The response of the CPU to this interrupt service request is a function of the

CPU’s interrupt enable flag, IEF1. For more information about this flag, refer to the

®

eZ80 CPU User Manual (UM0077), which is available on zilog.com.

Timer Input Source Selection

Timers 0–3 feature programmable input source selection. By default, the input is

taken from the eZ80F91’s system clock. The timers can also use the Real-Time

Clock source (50, 60, or 32768Hz) as their clock sources. The input source for

these timers is set using the timer control register. (TMRx_CTL[CLK_SEL])

Timer Output

The timer count can be directed to the GPIO output pins if required. To enable the

Timer Out feature, the GPIO port pin must be configured as an output and for

alternate functions. The GPIO output pin toggles each time the timer reaches its

end-of-count value. In CONTINUOUS mode operation, enabling the Timer Output

feature results in a Timer Output signal period that is twice the timer time-out

period. Examples of the Timer Output operation are illustrated in Figure 28 and

Table 52. The initial value for the timer output is zero.

Logic to support timer output exists in all timers, but for the eZ80F91 device, only

Timer 0 and 2 route the actual timer output to the pins. Because Timer 3 uses the

T

pins for PWMxN signals, the timer outputs are not available when using

OUT

complementary PWM outputs. See Table 53 for details.

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System Clock

Clock Enable

TMR3_CTL Write

(Timer Enable)

T3 Count

0

4

3

2

1

4

3

2

1

Timer Out

(internal)

Timer Out

(at pad)

Figure 28. Example: PRT Timer Output Operation

Table 52. Example: PRT Timer Out Parameters

Parameter

Control Register(s)

Value

Timer Enable

TMR

x

_CTL[TIM_EN]

_CTL[RLD]

1

Reload

1

Prescaler Divider = 4

CONTINUOUS Mode

Timer Reload Value

_CTL[CLK_DIV]

_CTL[TIM_CONT]

00b

1

{TMR

x

_RR_H, TMRx_RR_L}

0003h

Break Point Halting

When the eZ80F91 device is running in DEBUG mode, encountering a break

point causes all CPU functions to halt. By default, however, the timers keep run-

ning. This instance can make debugging timer-related firmware much more diffi-

cult. Therefore, the control register contains a BRK_STP bit. Setting this bit

causes the count value to be held during debug break points.

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Specialty Timer Modes

The features described above are common to all timers in the eZ80F91 device. In

addition to these common features, some of the timers have additional functional-

ity. The following is a list of the special features for each timer.

•

Timer 0

–

no special functions

•

Timer 1

–

1 event counter (EC0)

2 input captures (IC0 and IC1)

•

Timer 2

–

1 event counter (EC1)

Timer 3

–

2 input captures (IC2 and IC3)

4 output compares (OC0, OC1, OC2, and OC3)

4 PWM outputs (PWM0, PWM1, PWM2, and PWM3)

Timer 3 contains three specialty modes. Each of these modes is enabled using

bits in their respective control registers (TMR3_CAP_CTL, TMR3_OC_CTL1,

TMR3_PWM_CTL1). When PWM mode is enabled, the OUTPUT COMPARE and

INPUT CAPTURE modes are not available. This instance is due to address space

sharing requirements. However, INPUT CAPTURE and OUTPUT COMPARE

modes can run concurrently.

Timers with specialty modes offer multiple ways to generate an interrupt. When

the interrupt controller services a timer interrupt, the firmware must read the

timer’s interrupt identification register (TMRx_IIR) to determine the cause, or

causes, for an interrupt request. This register is cleared each time it is read, allow-

ing subsequent events to be identified without interference from prior events.

Event Counter

When a timer is configured to take its input from a port input pin (ECx), it functions

as an event counter. For event counting, the clock prescaler is automatically

bypassed and edges (events) cause the timer to decrement. The user must select

the rising or the falling edge for counting. Also, the port pins must be configured as

inputs.

Input sampling on the port pins results in the counter being updated on the third

rising edge of the system clock after the edge event occurs at the port pin. Due to

the sampling, the frequency of the event input is limited to one-half the system

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clock frequency under ideal conditions. In practice, the event frequency must be

less than this value, due to duty cycle variation and system clock jitter.

This EVENT COUNT mode is identical to basic timer operation, except for the

clock source. Therefore, interrupts are managed in the same manner.

RTC Oscillator Input

When the timer clock source is the Real-Time Clock signal, the timer functions

just as it does in EVENT COUNT mode, except that it samples the internal RTC

clock rather than the ECx pin.

Input Capture

INPUT CAPTURE mode allows the CPU to determine the timing of specified

events on a set of external pins.

A timer intended for use in INPUT CAPTURE mode is set up the same way as in

BASIC mode, with one exception. The CPU must also write the TMRx_CAP_CTL

register to select the edge on which to capture: rising, falling, or both. When one

of these events occurs on an input capture pin, the current 16 bit timer value is

latched into the capture value register pair (TMRx_CAP_A or TMRx_CAP_B

depending on the IC pin exhibiting the event).

Reading the Low byte of the register pair causes the timer to ignore other capture

events on the associated external pin until the High byte is read. This instance

prevents a subsequent capture event from overwriting the High byte between the

two Reads and generating an invalid capture value. The capture value registers

are Read Only.

A capture flag (ICA or ICB) in the TMRx_IIR register is set whenever a capture

event occurs. Setting the interrupt identification register bit

TMRx_IER[IRQ_ICx_EN] enables the capture event to generate a timer interrupt.

Output Compare

The output compare function reverses the input capture function. Rather than

store a timer value when an external event occurs, OUTPUT COMPARE mode

waits until the timer reaches a specified value, then generates an external event.

Although the same base timer is used, up to four separate external pins can be

driven, each with its own compare value.

To use OUTPUT COMPARE mode, the CPU must first configure the basic timer

parameters. Then it must load up to four 16-bit compare values into the four

TMR3_OCx register pairs. Next, it must load the TMR3_ OC_CTL2 register to

specify the event that occurs upon comparison. The user can select the following

events: SET, CLEAR, and TOGGLE. Finally, the CPU must enable OUTPUT

COMPARE mode by asserting TMR3_OC_CTL1[OC_EN].

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The initial value for the OCx pins in OUTPUT COMPARE mode is 0 by default. It

is possible to initialize this value to 1, or force a value at a later time. Setting the

TMR3_OC_CTL2[OCx_MODE] value to 0 forces the OCx pin to the selected state

provided by the TMR3_OC_CTL1[OCx_INIT] bits. Regardless of any compare

events, the pin stays at the forced value until OCx_MODE is changed. After

release, it retains the forced value until modified by an OUTPUT COMPARE

event.

Asserting TMR3_OC_CTL1[MAST_MODE] selects MASTER MODE for all OUT-

PUT COMPARE events, and sets output 0 as the master. As a result, outputs 1, 2,

and 3 are caused to disregard output-specific configuration and comparison val-

ues and instead mimic the current settings for output 0.

The OCx bits in the TMR3_IIR register are set whenever the corresponding timer

compares occur. TMR3_IER[IRQ_OCx_EN] allows the compare event to gener-

ate a timer interrupt.

Timer Port Pin Allocation

The eZ80F91 device timers interface to the outside world via Ports A and B.

These ports are also used for general purpose I/O as well as other assorted func-

tions. Table 53 lists the timer pins and their respective functions.

Table 53. GPIO Mode Selection When Using Timer Pins

Timer Function

GPIO Port GPIO Port

PWM_CTL1

Port

A

Bits

PA0

PA1

PA2

PA3

Mode

MPWM_EN = 0

MPWM_EN = 1

7

OC0

OC1

OC2

OC3

PWM0

PWM1

PWM2

PWM3

PWM_CTL1

PAIR_EN = 0

PWM_CTL1

PAIR_EN = 1

PA4

PA5

PA6

PA7

7

TOUT0

TOUT1

EC1

PWM0

PWM1

PWM2

PWM3

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Table 53. GPIO Mode Selection When Using Timer Pins (Continued)

Timer Function

GPIO Port GPIO Port

PWM_CTL1

MPWM_EN = 0

PWM_CTL1

MPWM_EN = 1

Port

B

Bits

PB0

PB1

PB4

PB5

Mode

7

IC0/EC0

IC1

IC2

IC3

Timer Registers

The CPU monitors and controls the timer using seven 8-bit registers. These regis-

ters are the control register, the interrupt identification register, the interrupt

enable register and the reload register pair (High and Low byte). There are also a

pair of data registers used to read the current timer count value.

The variable x can be 0, 1, 2, or 3 to represent each of the 4 available timers.

Basic Timer Register Set

Each timer requires a different set of registers for configuration and control. How-

ever, all timers contain the following seven registers, each of which is necessary

for basic operation:

•

Timer Control Register (TMRx_CTL)

Interrupt Identification Register (TMRx_IIR)

Interrupt Enable Register (TMRx_IER)

Timer Data Registers (TMRx_DR_H and TMRx_DR_L)

Timer Reload Registers (TMRx_RR_H and TMRx_RR_L)

The Timer Data Register is Read Only, while the Timer Reload Register is Write

Only. The address space for these two registers is shared.

Register Set for Capture in Timer 1

In addition to the basic register set, Timer 1 uses the following five registers for its

INPUT CAPTURE mode:

•

Capture Control Register (TMR1_CAP_CTL)

Capture Value Registers (TMR1_CAP_B_H, TMR1_CAP_B_L,

TMR1_CAP_A_H, TMR1_CAP_A_L)

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Register Set for Capture/Compare/PWM in Timer 3

In addition to the basic register set, Timer 3 uses 19 registers for INPUT CAP-

TURE, OUTPUT COMPARE, and PWM modes. PWM and capture/compare func-

tions cannot be used concurrently, so their register address space is shared.

INPUT CAPTURE and OUTPUT COMPARE can be used concurrently—their

address space is not shared.

The INPUT CAPTURE mode registers are equivalent to those used in Timer 1

above (substitute TMR3 for TMR1).

OUTPUT COMPARE mode uses the following nine registers:

•

Output Compare Control Registers

–

TMR3_OC_CTL1

TMR3_OC_CTL2

Compare Value Registers

–

TMR3_OC3_H

TMR3_OC3_L

TMR3_OC2_H

TMR3_OC2_L

TMR3_OC1_H

TMR3_OC1_L

TMR3_OC0_H

TMR3_OC0_L

Multiple PWM mode uses the following 19 registers:

•

PWM Control Registers

–

TMR3_PWM_CTL1

TMR3_PWM_CTL2

TMR3_PWM_CTL3

•

PWM Rising Edge Values

–

TMR3_PWM3R_H

TMR3_PWM3R_L

TMR3_PWM2R_H

TMR3_PWM2R_L

TMR3_PWM1R_H

TMRx_PWM1R_L

TMR3_PWM0R_H

TMR3_PWM0R_L

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•

PWM Falling Edge Values

–

TMR3_PWM3F_H

TMRx_PWM3F_L

TMR3_PWM2F_H

TMR3_PWM2F_L

TMR3_PWM1F_H

TMR3_PWM1F_L

TMR3_PWM0F_H

TMR3_PWM0F_L

Timer Control Register

The Timer x Control Register, detailed in Table 54, is used to control operation of

the timer, including enabling the timer, selecting the clock source, selecting the

clock divider, selecting between CONTINUOUS and SINGLEPASS modes, and

enabling the auto-reload feature.

Table 54. Timer Control Register

(TMR0_CTL = 0060h, TMR1_CTL = 0065h, TMR2_CTL = 006Fh, TMR3_CTL = 0074h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

Note: R = Read only; R/W = Read/Write.

Bit

Position

Value

Description

7

0

1

The timer continues to operate during debug break points.

BRK_STOP

The timer stops operation and holds count value during debug

break points.

[6:5]

CLK_SEL

00

01

10

Timer source is the system clock divided by the prescaler.

Timer source is the Real Time Clock Input.

Timer source is the Event Count (ECx) input—falling edge.

For Timer 1 this is EC0.

For Timer 2, this is EC1.

11

Timer source is the Event Count (ECx) input—rising edge.

For Timer 1 this is EC0.

For Timer 2, this is EC1.

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Product Specification

139

[4:3]

CLK_DIV

00

01

10

11

0

System clock divider = 4.

System clock divider = 16.

System clock divider = 64.

System clock divider = 256.

2

The timer operates in SINGLE PASS mode. TIM_EN (bit 0) is

reset to 0, and counting stops when the end-of-count value is

reached.

TIM_CONT

1

The timer operates in CONTINUOUS mode. The timer reload

value is written to the counter when the end-of-count value is

reached.

1

RLD

0

1

Reload function is not forced.

Force reload. When a 1 is written to this bit, the values in the

reload registers are loaded into the downcounter.

0

1

The programmable reload timer is disabled.

The programmable reload timer is enabled.

TIM_EN

Timer Interrupt Enable Register

The Timer x Interrupt Enable Register, detailed in Table 55, is used to control

operation of the timer interrupts. Only bits related to functions present in a given

timer are active.

Table 55. Timer Interrupt Enable

(TMR0_IER = 0061h, TMR1_IER = 0066h, TMR2_IER = 0070h, TMR3_IER = 0075h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

Note: R = Read only; R/W = Read/Write.

Bit

Position

Value

Description

7

0

Unused.

6

Interrupt requests for OC3 are disabled (valid only in

IRQ_OC3_EN

OUTPUT COMPARE mode). OC operations occur in Timer

3.

1

Interrupt requests for OC3 are enabled (valid only in

OUTPUT COMPARE mode). OC operations occur in Timer

3.

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Product Specification

140

5

0

1

0

1

0

1

0

Interrupt requests for OC2 are disabled (valid only in

OUTPUT COMPARE mode). OC operations occur in Timer

3.

IRQ_OC2_EN

Interrupt requests for OC2 are enabled (valid only in

OUTPUT COMPARE mode). OC operations occur in Timer

3.

4

Interrupt requests for OC1 are disabled (valid only in

OUTPUT COMPARE mode). OC operations occur in Timer

3.

IRQ_OC1_EN

Interrupt requests for OC1 are enabled (valid only in

OUTPUT COMPARE mode). OC operations occur in Timer

3.

3

Interrupt requests for OC0 are disabled (valid only in

OUTPUT COMPARE mode). OC operations occur in Timer

3.

IRQ_OC0_EN

Interrupt requests for OC0 are enabled (valid only in

OUTPUT COMPARE mode). OC operations occur in Timer

3.

2

Interrupt requests for ICx are disabled (valid only in INPUT

CAPTURE mode).

IRQ_ICB_EN

Timer 1: the capture pin is IC1.

Timer 3: the capture pin is IC3.

1

0

1

Interrupt requests for ICx are enabled (valid only in INPUT

CAPTURE mode).

For Timer 1: the capture pin is IC1.

For Timer 3: the capture pin is IC3.

1

Interrupt requests for ICA or PWM power trip are disabled

(valid only in INPUT CAPTURE and PWM modes).

For Timer 1: the capture pin is IC0.

IRQ_ICA_EN

For Timer 3: the capture pin is IC2.

Interrupt requests for ICA or PWM power trip are enabled

(valid only in INPUT CAPTURE and PWM modes).

For Timer 1: the capture pin is IC0.

For Timer 3: the capture pin is IC2.

0

1

Interrupt on end-of-count is disabled.

Interrupt on end-of-count is enabled.

IRQ_EOC_EN

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Programmable Reload Timers

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141

Timer Interrupt Identification Register

The TImer x Interrupt Identification Register, detailed in Table 56, is used to flag

timer events so that the CPU can determine the cause of a timer interrupt. This

register is cleared by a CPU Read.

Table 56. Timer Interrupt Identification Register

(TMR0_IIR = 0062h, TMR1_IIR = 0067h, TMR2_IIR = 0071h, TMR3_IIR = 0076h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read only;

R

Bit

Position

Value

Description

7

0

1

0

1

0

1

0

1

0

Unused.

6

OC3

Output compare, OC3, does not occur.

Output compare, OC3, occurs.

5

OC3

Output compare, OC2, does not occur.

Output compare, OC2, occurs.

4

OC1

Output compare, OC1, does not occur.

Output compare, OC1, occurs.

3

OC0

Output compare, OC0, does not occur.

Output compare, OC0, occurs.

2

ICB

Input capture, ICB, does not occur.

For Timer 1, the capture pin is IC1.

For Timer 3, the capture pin is IC3.

1

0

1

Input capture, ICB, occurs.

For Timer 1, the capture pin is IC1.

For Timer 3, the capture pin is IC3.

1

ICA

Input capture, ICA, or PWM power trip does not occur.

For Timer 1, the capture pin is IC0.

For Timer 3, the capture pin is IC2.

Input capture, ICA, or PWM power trip occurs.

For Timer 1, the capture pin is IC0.

For Timer 3, the capture pin is IC2.

0

EOC

0

1

End-of-count does not occur.

End-of-count occurs.

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Timer Data Register—Low Byte

The Timer x Data Register—Low Byte returns the Low byte of the current count

value of the selected timer. The Timer Data Register—Low Byte, detailed in Table

57, can be read while the timer is in operation. Reading the current count value

does not affect timer operation. To read the 16-bit data of the current count value,

{TMRx_DR_H[7:0], TMRx_DR_L[7:0]}, first read the Timer Data Register—Low

Byte, followed by the Timer Data Register—High Byte. The Timer Data Register—

High Byte value is latched into temporary storage when a Read of the Timer Data

Register—Low Byte occurs.

This register shares its address with the corresponding timer reload register.

Table 57. Timer Data Register—Low Byte

(TMR0_DR_L = 0063h, TMR1_DR_L = 0068h, TMR2_DR_L = 0072h,

TMR3_DR_L = 0077h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read only.

R

Bit

Position

Value

Description

[7:0]

TMR_DR_L

00h–FFh These bits represent the Low byte of the 2-byte timer data

value, {TMR _DR_H[7:0], TMR _DR_L[7:0]}. Bit 7 is bit 7

x

of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the 16-

bit timer data value.

Timer Data Register—High Byte

The Timer x Data Register—High Byte returns the High byte of the count value of

the selected timer as it existed at the time that the Low byte was read. The Timer

Data Register—High Byte, detailed in Table 58, can be read while the timer is in

operation. Reading the current count value does not affect timer operation. To

read the 16-bit data of the current count value, {TMRx_DR_H[7:0],

TMRx_DR_L[7:0]}, first read the Timer Data Register—Low Byte followed by the

Timer Data Register—High Byte. The Timer Data Register—High Byte value is

latched into temporary storage when a Read of the Timer Data Register—Low

Byte occurs.

This register shares its address with the corresponding timer reload register.

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Table 58. Timer Data Register—High Byte

(TMR0_DR_H = 0064h, TMR1_DR_H = 0069h, TMR2_DR_H = 0073h,

TMR3_DR_H = 0078h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read only.

R

Bit

Position

Value

00h–FFh These bits represent the High byte of the 2-byte timer data

value, {TMR _DR_H[7:0], TMR _DR_L[7:0]}. Bit 7 is bit 15

Description

[7:0]

TMR_DR_H

x

(msb) of the 16-bit timer data value. Bit 0 is bit 8 of the 16-bit

timer data value.

Timer Reload Register—Low Byte

The Timer x Reload Register—Low Byte, detailed in Table 59, stores the least-sig-

nificant byte (LSB) of the 2-byte timer reload value. In CONTINUOUS mode, the

timer reload value is reloaded into the timer upon end-of-count. When the reload

bit (TMRx_CTL[RLD]) is set to 1 forcing the reload function, the timer reload value

is written to the timer on the next rising edge of the clock.

This register shares its address with the corresponding timer data register.

Table 59. Timer Reload Register—Low Byte

(TMR0_RR_L = 0063h, TMR1_RR_L = 0068h, TMR2_RR_L = 0072h,

TMR3_RR_L = 0077h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: W = Write Only.

W

Bit

Position

Value

Description

[7:0]

TMR_RR_L

00h–FFh These bits represent the Low byte of the 2-byte timer

reload value, {TMR _RR_H[7:0], TMR _RR_L[7:0]}. Bit 7

x

is bit 7 of the 16-bit timer reload value. Bit 0 is bit 0 (lsb) of

the 16-bit timer reload value.

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Programmable Reload Timers

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144

Timer Reload Register—High Byte

The Timer x Reload Register—High Byte, detailed in Table 60, stores the most-

significant byte (MSB) of the 2-byte timer reload value. In CONTINUOUS mode,

the timer reload value is reloaded into the timer upon end-of-count. When the

reload bit (TMRx_CTL[RLD]) is set to 1, thereby forcing the reload function, the

timer reload value is written to the timer on the next rising edge of the clock.

This register shares its address with the corresponding timer data register.

Table 60. Timer Reload Register—High Byte

(TMR0_RR_H = 0064h, TMR1_RR_H = 0069h, TMR2_RR_H = 0073h,

TMR3_RR_H = 0078h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: W = Write Only.

W

Bit

Position

Value

Description

[7:0]

TMR_RR_H

00h–FFh These bits represent the High byte of the 2-byte timer

reload value, {TMR _RR_H[7:0], TMR _RR_L[7:0]}. Bit 7

x

is bit 15 (msb) of the 16-bit timer reload value. Bit 0 is bit 8

of the 16-bit timer reload value.

Timer Input Capture Control Register

The Timer x Input Capture Control Register, detailed in Table 61, is used to select

the edge or edges to be captured. For Timer 1, CAP_EDGE_B is used for IC1,

and CAP_EDGE_A is for IC0. For Timer 3, CAP_EDGE_B is for IC3, and

CAP_EDGE_A is for IC2.

Table 61. Timer Input Capture Control Register

(TMR1_CAP_CTL = 006Ah, TMR3_CAP_CTL = 007Bh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

Note: R = Read only; R/W = Read/Write.

Bit

Position

Value

Description

[7:4]

0000

Reserved

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Programmable Reload Timers

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Product Specification

145

[3:2]

CAP_EDGE_B

00

01

10

11

00

01

10

11

Disable capture on ICB.

Enable capture only on the falling edge of ICB.

Enable capture only on the rising edge of ICB.

Enable capture on both edges of ICB.

Disable capture on ICA.

[1:0]

CAP_EDGE_A

Enable capture only on the falling edge of ICA

Enable capture only on the rising edge of ICA.

Enable capture on both edges of ICA.

Timer Input Capture Value A Register—Low Byte

The Timer x Input Capture Value A Register—Low Byte, detailed in Table 62,

stores the Low byte of the capture value for external input A. For Timer 1, the

external input is IC0. For Timer 3, it is IC2.

Table 62. Timer Input Capture Value Register A—Low Byte

(TMR1_CAPA_L = 006Bh, TMR3_CAPA_L = 007Ch)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read only.

R

Bit

Position

Value

Description

[7:0]

TMR

00h–FFh These bits represent the Low byte of the 2-byte capture

value, {TMR _CAPA_H[7:0], TMR _CAPA_L[7:0]}. Bit 7

x

_CAPA_L

x

is bit 7 of the 16-bit data value. Bit 0 is bit 0 (lsb) of the 16-

bit timer data value.

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Timer Input Capture Value A Register—High Byte

The Timer x Input Capture Value A Register—High Byte, detailed in Table 63,

stores the High byte of the capture value for external input A. For Timer 1, the

external input is IC0. For Timer 3, it is IC2.

Table 63. Timer Input Capture Value Register A—High Byte

(TMR1_CAPA_H = 006Ch, TMR3_CAPA_H = 007Dh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read only.

R

Bit

Position

Value

Description

[7:0]

TMR

00h–FFh These bits represent the High byte of the 2-byte capture

value, {TMR _CAPA_H[7:0], TMR _CAPA_L[7:0]}. Bit 7

x

_CAPA_H

x

is bit 15 (msb) of the 16-bit data value. Bit 0 is bit 8 of the

16-bit timer data value.

Timer Input Capture Value B Register—Low Byte

The Timer x Input Capture Value B Register—Low Byte, detailed in Table 64,

stores the Low byte of the capture value for external input B. For Timer 1, the

external input is IC1. For Timer 3, it is IC3.

Table 64. Timer Input Capture Value Register B—Low Byte

(TMR1_CAPB_L = 006Dh, TMR3_CAPB_L = 007Eh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read only.

R

Bit

Position

Value

Description

[7:0]

TMR

00h–FFh These bits represent the Low byte of the 2-byte capture

value, {TMR _CAPB_H[7:0], TMR _CAPB_L[7:0]}. Bit 7

x

_CAPB_L

x

is bit 7 of the 16-bit data value. Bit 0 is bit 0 (lsb) of the 16-

bit timer data value.

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Programmable Reload Timers

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147

Timer Input Capture Value B Register—High Byte

The Timer x Input Capture Value B Register—High Byte, detailed in Table 65,

stores the High byte of the capture value for external input B. For Timer 1, the

external input is IC0. For Timer 3, it is IC3.

Table 65. Timer Input Capture Value Register B—High Byte

(TMR1_CAPB_H = 006Eh, TMR3_CAPB_H = 007Fh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read only.

R

Bit

Position

Value

Description

[7:0]

TMR

00h–FFh These bits represent the High byte of the 2-byte capture

value, {TMR _CAPB_H[7:0], TMR _CAPB_L[7:0]}. Bit 7

x

_CAPB_H

x

is bit 15 (msb) of the 16-bit data value. Bit 0 is bit 8 of the

16-bit timer data value.

Timer Output Compare Control Register 1

The Timer3 Output Compare Control Register 1, detailed in Table 66, is used to

select the Master Mode and to provide initial values for the OC pins.

Table 66. Timer Output Compare Control Register 1

(TMR3_OC_CTL1 = 0080h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

Note: R = Read only; R/W = Read/Write.

Bit

Position

Value

Description

[7:6]

00

0

Unused

5

OC pin cleared when initialized.

OC pin set when initialized.

OC pin cleared when initialized.

OC pin set when initialized.

OC3_INIT

1

4

0

OC2_INIT

1

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Programmable Reload Timers

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148

3

0

1

0

1

0

1

0

1

OC pin cleared when initialized.

OC pin set when initialized.

OC pin cleared when initialized.

OC pin set when initialized.

OC pins are independent.

OC pins all mimic OC0.

OC1_INIT

2

OC0_INIT

1

MAST_MODE

0

OUTPUT COMPARE mode is disabled.

OUTPUT COMPARE mode is enabled.

OC_EN

Timer Output Compare Control Register 2

The Timer3 Output Compare Control Register 2, detailed in Table 67, is used to

select the event that will occur on the output compare pins when a timer compare

happens.

Table 67. Timer Output Compare Control Register 2

(TMR3_OC_CTL2 = 0081h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

[7:6]

OC3_MODE

00

Initialize OC pin to value specified in

TMR3_OC_CTL1[OC3_INT].

01

10

11

00

OC pin is cleared upon timer compare.

OC pin is set upon timer compare.

OC pin toggles upon timer compare.

[5:4]

OC2_MODE

Initialize OC pin to value specified in

TMR3_OC_CTL1[OC2_INT].

01

10

11

OC pin is cleared upon timer compare.

OC pin is set upon timer compare.

OC pin toggles upon timer compare.

PS019209-0504

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Product Specification

149

[3:2]

00

Initialize OC pin to value specified in

OC1_MODE

TMR3_OC_CTL1[OC1_INT].

01

10

11

00

OC pin is cleared upon timer compare.

OC pin is set upon timer compare.

OC pin toggles upon timer compare.

[1:0]

OC0_MODE

Initialize OC pin to value specified in

TMR3_OC_CTL1[OC0_INT].

01

10

11

OC pin is cleared upon timer compare.

OC pin is set upon timer compare.

OC pin toggles upon timer compare.

Timer Output Compare Value Register—Low Byte

The Timer3 Output Compare x Value Register—Low Byte, detailed in Table 68,

stores the Low byte of the compare value for OC0–OC3.

Table 68. Compare Value Register—Low Byte

(TMR3_OC0_L = 0082h, TMR3_OC1_L = 0084h,

TMR3_OC2_L = 0086h, TMR3_OC3_L = 0088h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

[7:0]

TMR3_OCx_L

00h–FFh These bits represent the Low byte of the 2-byte compare

value, {TMR3_OCx_H[7:0], TMR3_OCx_L[7:0]}. Bit 7 is

bit 7 of the 16-bit data value. Bit 0 is bit 0 (lsb) of the 16-bit

timer compare value.

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eZ80F91 MCU

Product Specification

150

Timer Output Compare Value Register—High Byte

The Timer3 Output Compare x Value Register—High Byte, detailed in Table 69,

stores the High byte of the compare value for OC0–OC3.

Table 69. Compare Value Register—High Byte

(TMR3_OC0_H = 0083h, TMR3_OC1_H = 0085h,

TMR3_OC2_H = 0087h, TMR3_OC3_H = 0089h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

[7:0]

TMR3_OCx_H

00h–FFh These bits represent the High byte of the 2-byte compare

value, {TMR3_OCx_H[7:0], TMR3_OCx_L[7:0]}. Bit 7 is

bit 15 (msb) of the 16-bit data value. Bit 0 is bit 8

of the 16-bit timer compare value.

Multi-PWM Mode

Multi-PWM Mode Overview

The special Multi-PWM mode uses the Timer 3 16-bit counter as the primary time-

keeper to control up to 4 pulse-width modulated (PWM) generators. The 16-bit

reload value for Timer 3 sets a common period for each of the PWM signals. How-

ever, the duty cycle and phase for each generator are independent—that is, the

High and Low periods for each PWM generator are set independently. In addition,

each of the 4 PWM generators is enabled independently. The 8 PWM signals (4

PWM output signals and their inverses) are output via Port A. A functional block

diagram of the Multi-PWM is illustrated in Figure 29.

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eZ80F91 MCU

Product Specification

151

16

PA0

PA4

PWM0 Output

PWM0

Generator

16

Timer 3

16-Bit Binary

Downcounter

PA1

PA5

PWM1 Output

PWM1

Generator

16

Timer 3

Clock Input

Count Value

16

PA2

PA6

PWM2 Output

PWM2

Generator

16

PA3

PA7

PWM3 Output

PWM3

Generator

Figure 29. Multi-PWM Simplified Block Diagram

Setting TMR3_PWM_CTL1[MPWM_EN] to 1 enables Multi-PWM mode. The

TMR3_PWM_CTL1 register bits enable the 4 individual PWM generators by

adjusting settings according to the list provided in Table 70.

Table 70. Enabling PWM Generators

Enable PWM generator 0 by setting TMR3_PWM_CTL1[PWM0_EN] to 1.

Enable PWM generator 1 by setting TMR3_PWM_CTL1[PWM1_EN] to 1.

Enable PWM generator 2 by setting TMR3_PWM_CTL1[PWM2_EN] to 1.

Enable PWM generator 3 by setting TMR3_PWM_CTL1[PWM3_EN] to 1.

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Product Specification

152

The inverted PWM outputs PWM0, PWM1, PWM2, and PWM3 are globally

enabled by setting TMR3_PWM_CTL1[PAIR_EN] to 1. The individual PWM gen-

erators must be enabled for the associated inverted PWM signals to be output.

For each of the 4 PWM generators, there is a 16-bit rising edge value

{TMR3_PWMxR_H[PWMxR_H], TMR3_PWMxR_L[PWMxR_L]} and a 16-bit fall-

ing edge value {TMR3_PWMxF_H[PWMxF_H], TMR3_PWMxF_L[PWMxF_L]} for

a total of 16 registers. The rising-edge byte pairs define the timer count at which

the PWMx output transitions from Low to High. Conversely, the falling-edge byte

pairs define the timer count at which the PWMx output transitions from High to

Low. Upon reset, all enabled PWM outputs begin Low and all PWMx outputs

begin High. When the PWMx output is Low, the logic is looking for a match

between the timer count and the rising edge value, and vice versa. Therefore, in a

case in which the rising edge value is the same as the falling edge value, the

PWM output frequency is one-half the rate at which the counter passes through its

entire count cycle (from reload value down to 0000h).

Figures 30 and 31 demonstrate a simple multi-PWM output and an expanded

view of the timing, respectively. Associated control values are listed in Table 71.

T3 Count

PWM0

C B

A

9

8

7

6

5

4

3

2

1

C B

A

9

8

7

6

5

4

3

2

1

C B

A

9

8

7

6

5

4

3

2

1 C B A

0

PWM0

PWM1

Figure 30. Multi-PWM Operation

System Clock

Clock Enable

T3 Count

Figure 31. Multi-PWM Operation—Expanded View of Timing

A

9

8

7

6

5

4

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Table 71. Example: Multi-PWM Addressing

Parameter

Control Register(s)

Value

000Ch

0008h

Timer Reload Value

PWM0 rising edge

{TMR3_RR_H, TMR3_RR_L}

{TMR3_PWM0R_H,

TMR3_PWM0R_L}

PWM0 falling edge

PWM1 rising edge

PWM1 falling edge

{TMR3_PWM0F_H,

TMR3_PWM0F_L}

0004h

0006h

0007h

{TMR3_PWM1R_H,

TMR3_PWM1R_L}

{TMR3_PWM1F_H,

TMR3_PWM1F_L}

PWM enable

TMR3_PWM_CTL1[PAIR_EN]

TMR3_PWM_CTL1[PWM0_EN]

TMR3_PWM_CTL1[PWM1_EN]

TMR3_PWM_CTL1[MPWM_EN]

TMR3_CTL[CLK_DIV]

1

PWM0 enable

1

PWM1 enable

1

Multi-PWM enable

Prescaler Divider = 4

PWM nonoverlapping delay = 0

1

00b

0000b

TMR3_PWM_CTL2[PWM_DLY]

PWM Master Mode

In PWM Master mode, the pair of output signals generated from the PWM0 gener-

ator (PWM0 and PWM0) are directed to all four sets of PWM output pairs. Setting

TMR3_PWM_CTL1[MM_EN] to 1 enables PWM Master mode. Assuming the out-

puts are all enabled and no AND/OR gating is used, all four PWM output pairs

transition simultaneously under the direction of PWM0 and PWM0. In PWM Mas-

ter mode, the outputs can still be gated individually using the AND/OR gating func-

tions described in the next section. Multi-PWM mode and the individual PWM

outputs must be enabled along with PWM Master mode. It is possible to enable or

disable any combination of the 4 PWM outputs while running in PWM Master

mode.

Modification of Edge Transition Values

Special circuitry is included for the update of the PWM edge transition values.

Normal use requires that these values be updated while the PWM generator is

running.

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Under certain circumstances, electric motors driven by the PWM logic can

Note:

encounter rough operation. In essence, cycles can be skipped if the PWM wave-

form edge is not carefully modified.

Without special consideration, if a PWM generator looks for a particular count to

make a state transition, and if the edge transition value changes to a value that

already occurred in the current counter count-down cycle, then the transition is

missed. The PWM generator holds the current output state until the counter

reloads and cycles through to the appropriate edge transition value again. In

effect, an entire cycle of the PWM waveform can be skipped with the signal held

at a DC value. The change in PWM waveform duty cycle from cycle to cycle must

be limited to some fraction of a period to avoid rough running. To avoid uninten-

tional roughness due to timing of the load operation for the register values in

question, the PWM edge transition values are double-buffered and exhibit the fol-

lowing behavior:

1. When the PWM generators are disabled, PWM edge transition values written

by the CPU are immediately loaded into the PWM edge transition registers.

2. When the PWM generators are enabled, a PWM edge transition value is

loaded into a buffer register and transferred to its destination register only

upon a specific transition event. A rising edge transition value is only loaded

upon a falling edge transition event, and a falling edge transition value is only

loaded upon a rising edge transition event.

AND/OR Gating of the PWM Outputs

When in Multi-PWM mode, it is possible for the user to turn off PWM propagation

to the pins without disabling the PWM generator. This feature is global and applies

to all enabled PWM generators. The function is implemented by applying digital

logic (AND or OR functions) to combine the corresponding bits in the port output

register with the PWM and PWM outputs.

The AND or OR functions are enabled on all PWM outputs by setting

TMR3_PWM_CTL2[AO_EN] to either a 01b(AND) or 10b(OR). Any other value

disables this feature. Likewise, the AND or OR functions are enabled on all PWM

outputs by setting TMR3_PWM_CTL2[AON_EN] to either a 01b(AND) or 10b

(OR). Any other value disables this feature. A functional block diagram for the

AND/OR gating feature for PWM0 and PWM0 is illustrated in Figure 32. The func-

tionality for the other three PWM pairs is identical.

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00

01

10

11

PA0

PWM0 Output

PWM0 Signal

PADR0

2

TMR3_PWM_CTL2[5:4]

00

01

10

PWM0 Output

PWM0 Signal

PADR4

PA4

11

2

TMR3_PWM_CTL2[7:6]

Figure 32. PWM AND/OR Gating Functional Diagram

If the user enables the OR function on all PWM outputs and PADR0 is set to 1,

then the PWM0 output on PA0 is forced High. Similarly, if the user selects the

AND function on all PWM outputs and PADR0 is set to a 0, then the PWM0 output

on PA0 is forced Low.

PWM Nonoverlapping Output Pair Delays

A delay can be added between the falling edge of the PWM (PWM) outputs and

the rising edge of the PWM (PWM) outputs. This delay can be set to assure that

even with load and output drive variations there will be no overlap between the

falling edge of a PWM (PWM) output and the rising edge of its paired output. The

selected delay is global to all four PWM pairs. The delay duration is software-

selectable using the 4-bit field TMR3_PWM_CTL2[PWM_DLY]. The duration is

programmable in units of the system clock (SCLK), from 0 SCLK periods to 15

SCLK periods. The TMR3_PWM_CTL2[PWM_DLY] bits are mapped directly to a

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counter, such that a setting of 0000brepresents a delay of 0 system clock peri-

ods, and a setting of 1111brepresents a delay of 15 system clock periods. The

PWM delay feature is illustrated in Figure 33, with associated addressing listed in

Table 72.

The PWM nonoverlapping delay time must always be defined to be less than the

delay between the rising and falling edges (and the delay between the falling and

rising edges) of all Multi-PWM outputs. In other words, a rising (falling) edge can-

not be delayed beyond the time at which it is subsequently scheduled to fall (rise).

Note:

System Clock

Clock Enable

A

9

8

7

6

5

4

3

2

1

C

TMR3_Count

PWM0

3 x SCLK

Figure 33. PWM Nonoverlapping Output Delay

Table 72. PWM Nonoverlapping Output Addressing

Parameter

Control Register(s)

TMR3_CTL[CLK_DIV]

{TMR3_RR_H, TMR3_RR_L}

Value

Timer clock is SCLK ÷ 4

Timer reload value

PWM0 rising edge

PWM0 falling edge

Prescaler divider = 4

00b

000Ch

{TMR3_PWM0R_H, TMR3_PWM0R_L} 0008h

{TMR3_PWM0F_H, TMR3_PWM0F_L} 0004h

TMR3_CTL[CLK_DIV]

00b

PWM nonoverlapping delay = 3 TMR3_PWM_CTL2[PWM_DLY]

0011b

PWM enable

TMR3_PWM_CTL1[PAIR_EN]

TMR3_PWM_CTL1[PWM0_EN]

TMR3_PWM_CTL1[MPWN_EN]

1

PWM0 enable

Multi-PWM enable

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Multi-PWM Power-Trip Mode

When enabled, the Multi-PWM power-trip feature forces the enabled PWM out-

puts to a predetermined state when an interrupt is generated from an external

source via IC0, IC1, IC2, or IC3. One or multiple external interrupt sources can be

enabled at any given time. If multiple sources are enabled, any of the selected

external sources can trigger an interrupt. Configuring the PWM_CTL3 register

enables or disables interrupt sources. See Table 75 on page 161.

The possible interrupt sources for a Multi-PWM power-trip are:

•

IC0—digital input

IC1—digital input

IC2—digital input

IC3—digital input

When the power trip is detected, TMR3_PWM_CTL3[PTD] is set to 1 to indicate

detection of the power-trip. A value of 0 signifies that no power-trip is detected.

The PWMs can only be released after a power-trip when

TMR3_PWM_CTL3[PTD] is written back to 0 by software. As a result, the user is

allowed to check the conditions of the motor being controlled before releasing the

PWMs. The explicit release also prevents noise glitches after a power-trip from

causing an accidental exit or reentry of the PWM power-trip state.

The programmable power-trip states of the PWMs are globally grouped for the

PWM outputs and the inverting PWM outputs. Upon detection of a power-trip, the

PWM outputs can be forced to either a High state, a Low state, or tristate. The set-

tings for the power-trip states are made with power-trip control bits

TMR3_PWM_CTL3[PT_LVL], TMR3_PWM_CTL3[PT_LVL_N], and

TMR3_PWM_CTL3[PT_TRI].

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Multi-PWM Control Registers

Pulse-Width Modulation Control Register 1

The PWM Control Register 1, detailed in Table 73, controls PWM function

enables.

Table 73. PWM Control Register 1

(PWM_CTL1 = 0079h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

7

0

Global disable of the PWM outputs (PWM outputs

enabled only).

PAIR_EN

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Global enable of the PWM and PWM output pairs.

Disable power-trip feature.

Enable power-trip feature.

Disable Master mode.

6

PT_EN

5

MM_EN

Enable Master mode.

4

Disable PWM generator 3.

Enable PWM generator 3.

Disable PWM generator 2.

Enable PWM generator 2.

Disable PWM generator 1.

Enable PWM generator 1.

Disable PWM generator 0.

Enable PWM generator 0.

Disable Multi-PWM mode.

Enable Multi-PWM mode.

PWM3_EN

3

PWM2_EN

2

PWM1_EN

1

PWM0_EN

0

MPWM_EN

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Pulse-Width Modulation Control Register 2

The PWM Control Register 2, detailed in Table 74, controls PWM AND/OR and

edge delay functions.

Table 74. PWM Control Register 2

(PWM_CTL2 = 007Ah)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

[7:6]

AON_EN

00

01

10

11

00

01

10

11

Disable AND/OR features on PWM.

Enable AND logic on PWM.

Enable OR logic on PWM.

Disable AND/OR features on PWM.

Enable AND logic on PWM.

[5:4]

AO_EN

Enable OR logic on PWM.

Disable AND/OR features on PWM.

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[3:0]

PWM_DLY

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

No delay between falling edge of PWM (PWM) and rising

edge of PWM (PWM)

Delay of 1 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

Delay of 2 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

Delay of 3 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

Delay of 4 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

Delay of 5 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

Delay of 6 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

Delay of 7 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

Delay of 8 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

Delay of 9 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

Delay of 10 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

Delay of 11 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

Delay of 12 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

Delay of 13 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

Delay of 14 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

Delay of 15 SCLK periods between falling edge of PWM

(PWM) and rising edge of PWM (PWM)

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Pulse-Width Modulation Control Register 3

The PWM Control Register 3, detailed in Table 75, is used to configure the PWM

power trip functionality.

Table 75. PWM Control Register 3

(PWM_CTL3 = 007Bh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

R

Note: R/W = Read/Write; R = Read only;

Bit

Position

Value

Description

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Power trip disabled on IC3.

Power trip enabled on IC3.

Power trip disabled on IC2.

Power trip enabled on IC2.

Power trip disabled on IC1.

Power trip enabled on IC1.

Power trip disabled on IC0.

Power trip enabled on IC0.

All PWM trip levels are tristate

PT_IC3_EN

6

PT_IC2_EN

5

PT_IC1_EN

4

PT_IC0_EN

3

PT_TRI

All PWM trip levels are defined by PT_LVL and PT_LVL_N

After power trip, PWMx outputs are set to one.

After power trip, PWMx outputs are set to zero.

After power trip, PWMx outputs are set to one.

After power trip, PWMx outputs are set to zero.

Power trip has been cleared.

2

PT_LVL

1

PT_LVL_N

0

PTD

This bit is set after power trip event.

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Pulse-Width Modulation Rising Edge—Low Byte

A parallel 16-bit Write of {TMR3_PWMxR_H[7–0], TMR3_PWMxR_L[7–0]} occurs

when software initiates a Write to TMR3_PWMxR_L. The register is detailed in

Table 76.

Table 76. PWMx Rising-Edge Register—Low Byte

(TMR3_PWM0R_L = 007Ch, TMR3_PWM1R_L = 007Eh, TMR3_PWM2R_L = 0080h,

TMR3_PWM3R_L = 0082h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

[7:0]

PWMXR_L

00h–FFh These bits represent the Low byte of the 16-bit value to set

the rising edge COMPARE value for PWMx,

{TMR3_PWMXR_H[7:0], TMR3_PWMXR_L[7:0]}. Bit 7 is bit 7

of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the 16-bit

timer data value.

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Pulse-Width Modulation Rising Edge—High Byte

Writing to TMR3_PWMxR_H stores the value in a temporary holding register. A

parallel 16-bit Write of {TMR3_PWMxR_H[7–0], TMR3_PWMxR_L[7–0]} occurs

when software initiates a Write to TMR3_PWMxR_L. The register is detailed in

Table 77.

Table 77. PWMx Rising-Edge Register—High Byte

(TMR3_PWM0R_H = 007Dh, TMR3_PWM1R_H = 007Fh, TMR3_PWM2R_H = 0081h,

TMR3_PWM3R_H = 0083h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

[7:0]

PWMXR_H

00h–FFh These bits represent the High byte of the 16-bit value to set

the rising edge COMPARE value for PWMx,

{TMR3_PWMXR_H[7:0], TMR3_PWMXR_L[7:0]}. Bit 7 is bit

15 (msb) of the 16-bit timer data value. Bit 0 is bit 8 of the 16-

bit timer data value.

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Pulse-Width Modulation Falling Edge—Low Byte

A parallel 16-bit Write of {TMR3_PWMxF_H[7–0], TMR3_PWMxF_L[7–0]} occurs

when software initiates a Write to TMR3_PWMxF_L. The register is detailed in

Table 78.

Table 78. PWMx Falling-Edge Register—Low Byte

(TMR3_PWM0F_L = 0084h, TMR3_PWM1F_L = 0086h, TMR3_PWM2F_L = 0088h,

TMR3_PWM3F_L = 008Ah)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

[7:0]

PWMXF_L

00h–FFh These bits represent the Low byte of the 16-bit value to set

the falling edge COMPARE value for PWMx,

{TMR3_PWMXF_H[7:0], TMR3_PWMXF_L[7:0]}. Bit 7 is bit 7

of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the 16-bit

timer data value.

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Pulse-Width Modulation Falling Edge—High Byte

Writing to TMR3_PWMxF_H stores the value in a temporary holding register. A

parallel 16-bit Write of {TMR3_PWMxF_H[7–0], TMR3_PWMxF_L[7–0]} occurs

when software initiates a Write to TMR3_PWMxF_L. The register is detailed in

Table 79.

Table 79. PWMx Falling-Edge Register—High Byte

(TMR3_PWM0F_H = 0085h, TMR3_PWM1F_H = 0087h, TMR3_PWM2F_H = 0089h,

TMR3_PWM3F_H = 008Bh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

[7:0]

PWMXF_H

00h–FFh These bits represent the High byte of the 16-bit value to set

the falling edge COMPARE value for PWMx,

{TMR3_PWMXF_H[7:0], TMR3_PWMXF_L[7:0]}. Bit 7 is bit

15 (msb) of the 16-bit timer data value. Bit 0 is bit 8 of the 16-

bit timer data value.

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Real-Time Clock

Real-Time Clock Overview

The Real-Time Clock (RTC) keeps time by maintaining a count of seconds, min-

utes, hours, day-of-the-week, day-of-the-month, year, and century. The current

time is kept in 24-hour format. The format for all count and alarm registers is

selectable between binary and binary-coded-decimal (BCD) operations. The cal-

endar operation maintains the correct day of the month and automatically com-

pensates for leap year. A simplified block diagram of the RTC and the associated

on-chip, low-power, 32KHz oscillator is illustrated in Figure 34. Connections to an

external battery supply and 32KHz crystal network are also demonstrated in

Figure 34.

RTC_V_DD

Battery

V_DD

IRQ

Real-Time Clock

ADDR[15:0]

DATA[7:0]

RTC Clock

R1

RTC_X_OUT

C

System Clock

Low-Power

32 KHz Oscillator

V_DD

32 KHz

Crystal

Enable

CLK_SEL

(RTC_CTRL[4])

RTC_X_IN

C

Figure 34. Real-Time Clock and 32KHz Oscillator Block Diagram

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Real-Time Clock Alarm

The clock can be programmed to generate an alarm condition when the current

count matches the alarm set-point registers. Alarm registers are available for sec-

onds, minutes, hours, and day-of-the-week. Each alarm can be independently

enabled. To generate an alarm condition, the current time must match all enabled

alarm values. For example, if the day-of-the-week and hour alarms are both

enabled, the alarm only occurs at the specified hour on the specified day. The

alarm triggers an interrupt if the interrupt enable bit, INT_EN, is set to 1. The

alarm flag, ALARM, and corresponding interrupt to the CPU are cleared by read-

ing the RTC_CTRL register.

Alarm value registers and alarm control registers can be written at any time. Alarm

conditions are generated when the count value matches the alarm value. The

comparison of alarm and count values occurs whenever the RTC count incre-

ments (one time every second). The RTC can also be forced to perform a compar-

ison at any time by writing a 0 to the RTC_UNLOCK bit (the RTC_UNLOCK bit is

not required to be changed to a 1 first).

Real-Time Clock Oscillator and Source Selection

The RTC count is driven by either the on-chip 32768Hz crystal oscillator or a 50/

60Hz power-line frequency input connected to the 32KHz RTC_X

pin. An

OUT

internal divider compensates for each of these options. The clock source and

power-line frequencies are selected in the RTC_CTRL register. Writing to the

RTC_CTRL register resets the clock divider.

Real-Time Clock Battery Backup

The power supply pin (RTC_V_DD) for the Real-Time Clock and associated low-

power 32KHz oscillator is isolated from the other power supply pins on the

eZ80F91 device. To ensure that the RTC continues to keep time in the event of

loss of line power to the application, a battery can be used to supply power to the

RTC and the oscillator via the RTC_V_DDpin. All V_SS(ground) pins should be con-

nected together on the printed circuit assembly.

Real-Time Clock Recommended Operation

Following a initial system reset from a powered-down condition of V_DDand

V_DD_RTC, the counter values of the RTC are undefined and all alarms are dis-

abled. The following procedure is recommended to initialize the Real-Time Clock:

•

Write to RTC_CTRL to set RTC_UNLOCK and disable the RTC counter; this

action also clears the clock divider

Write values to the RTC count registers to set the current time

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•

Write values to the RTC alarm registers to set the appropriate alarm condi-

tions

Write to RTC_CTRL to clear RTC_UNLOCK; clearing the RTC_UNLOCK bit

resets and enables the clock divider

Real-Time Clock Registers

The Real-Time Clock registers are accessed via the address and data buses

using I/O instructions. The RTC_UNLOCK control bit controls access to the RTC

count registers. When unlocked (RTC_UNLOCK = 1), the RTC count is disabled

and the count registers are Read/Write. When locked (RTC_UNLOCK = 0), the

RTC count is enabled and the count registers are Read Only. The default, at

RESET, is for the RTC to be locked.

Real-Time Clock Seconds Register

This register contains the current seconds count. The value in the RTC_SEC reg-

ister is unchanged by a RESET. The current setting of BCD_EN determines

whether the values in this register are binary (BCD_EN = 0) or binary-coded deci-

mal (BCD_EN = 1). Access to this register is Read Only if the RTC is locked and

Read/Write if the RTC is unlocked. See Table 80.

Table 80. Real-Time Clock Seconds Register

(RTC_SEC = 00E0h)

Bit

7

6

5

4

3

2

1

0

Reset

X

CPU Access

R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*

Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.

Binary-Coded-Decimal Operation (BCD_EN = 1)

Bit

Position

Value Description

[7:4]

0–5

The tens digit of the current seconds count.

TEN_SEC

[3:0]

SEC

0–9

The ones digit of the current seconds count.

Binary Operation (BCD_EN = 0)

Bit

Position

Value Description

[7:0]

SEC

00h– The current seconds count.

3Bh

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Product Specification

169

Real-Time Clock Minutes Register

This register contains the current minutes count. The value in the RTC_MIN regis-

ter is unchanged by a RESET. The current setting of BCD_EN determines

whether the values in this register are binary (BCD_EN = 0) or binary-coded deci-

mal (BCD_EN = 1). Access to this register is Read Only if the RTC is locked and

Read/Write if the RTC is unlocked. See Table 81.

Table 81. Real-Time Clock Minutes Register

(RTC_MIN = 00E1h)

Bit

7

6

5

4

3

2

1

0

Reset

X

CPU Access

R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*

Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.

Binary-Coded-Decimal Operation (BCD_EN = 1)

Bit

Position

Value Description

[7:4]

0–5

The tens digit of the current minutes count.

TEN_MIN

[3:0]

MIN

0–9

The ones digit of the current minutes count.

Binary Operation (BCD_EN = 0)

Bit

Position

Value Description

[7:0]

MIN

00h– The current minutes count.

3Bh

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P R E L I M I N A R Y

Real-Time Clock

eZ80F91 MCU

Product Specification

170

Real-Time Clock Hours Register

This register contains the current hours count. The value in the RTC_HRS register

is unchanged by a RESET. The current setting of BCD_EN determines whether

the values in this register are binary (BCD_EN = 0) or binary-coded decimal

(BCD_EN = 1). Access to this register is Read Only if the RTC is locked and

Read/Write if the RTC is unlocked. See Table 82.

Table 82. Real-Time Clock Hours Register

(RTC_HRS = 00E2h)

Bit

7

6

5

4

3

2

1

0

Reset

X

CPU Access

R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*

Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.

Binary-Coded-Decimal Operation (BCD_EN = 1)

Bit

Position

Value Description

[7:4]

0–2

The tens digit of the current hours count.

TEN_HRS

[3:0]

HRS

0–9

The ones digit of the current hours count.

Binary Operation (BCD_EN = 0)

Bit

Position

Value Description

[7:0]

HRS

00h– The current hours count.

17h

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Real-Time Clock

eZ80F91 MCU

Product Specification

171

Real-Time Clock Day-of-the-Week Register

This register contains the current day-of-the-week count. The RTC_DOW register

begins counting at 01h. The value in the RTC_DOW register is unchanged by a

RESET. The current setting of BCD_EN determines whether the value in this reg-

ister is binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). Access to

this register is Read Only if the RTC is locked and Read/Write if the RTC is

unlocked. See Table 83.

Table 83. Real-Time Clock Day-of-the-Week Register

(RTC_DOW = 00E3h)

Bit

7

0

6

0

5

0

4

0

3

2

1

0

Reset

X

CPU Access

R

R/W* R/W* R/W* R/W*

Note: X = Unchanged by RESET; R = Read Only; R/W* = Read Only if RTC locked, Read/Write if

RTC unlocked.

Binary-Coded-Decimal Operation (BCD_EN = 1)

Bit

Position

Value Description

[7:4]

0000 Reserved.

[3:0]

1–7

The current day-of-the-week.count.

DOW

Binary Operation (BCD_EN = 0)

Bit

Position

Value Description

[7:4]

0000 Reserved.

[3:0]

DOW

01h– The current day-of-the-week count.

07h

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Real-Time Clock

eZ80F91 MCU

Product Specification

172

Real-Time Clock Day-of-the-Month Register

This register contains the current day-of-the-month count. The RTC_DOM regis-

ter begins counting at 01h. The value in the RTC_DOM register is unchanged by a

RESET. The current setting of BCD_EN determines whether the values in this

register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). Access

to this register is Read Only if the RTC is locked and Read/Write if the RTC is

unlocked. See Table 84.

Table 84. Real-Time Clock Day-of-the-Month Register

(RTC_DOM = 00E4h)

Bit

7

6

5

4

3

2

1

0

Reset

X

CPU Access

R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*

Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.

Binary-Coded-Decimal Operation (BCD_EN = 1)

Bit

Position

Value Description

[7:4]

0–3

The tens digit of the current day-of-the-month count.

TENS_DOM

[3:0]

0–9

The ones digit of the current day-of-the-month count.

DOM

Binary Operation (BCD_EN = 0)

Bit

Position

Value Description

[7:0]

DOM

01h– The current day-of-the-month count.

1Fh

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Real-Time Clock

eZ80F91 MCU

Product Specification

173

Real-Time Clock Month Register

This register contains the current month count. The RTC_MON register begins

counting at 01h. The value in the RTC_MON register is unchanged by a RESET.

The current setting of BCD_EN determines whether the values in this register are

binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). Access to this reg-

ister is Read Only if the RTC is locked and Read/Write if the RTC is unlocked. See

Table 85.

Table 85. Real-Time Clock Month Register

(RTC_MON = 00E5h)

Bit

7

6

5

4

3

2

1

0

Reset

X

CPU Access

R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*

Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.

Binary-Coded-Decimal Operation (BCD_EN = 1)

Bit

Position

Value Description

[7:4]

0–1

The tens digit of the current month count.

TENS_MON

[3:0]

0–9

The ones digit of the current month count.

MON

Binary Operation (BCD_EN = 0)

Bit

Position

Value Description

[7:0]

MON

01h– The current month count.

0Ch

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Real-Time Clock

eZ80F91 MCU

Product Specification

174

Real-Time Clock Year Register

This register contains the current year count. The value in the RTC_YR register is

unchanged by a RESET. The current setting of BCD_EN determines whether the

values in this register are binary (BCD_EN = 0) or binary-coded decimal

(BCD_EN = 1). Access to this register is Read Only if the RTC is locked and

Read/Write if the RTC is unlocked. See Table 86.

Table 86. Real-Time Clock Year Register

(RTC_YR = 00E6h)

Bit

7

6

5

4

3

2

1

0

Reset

X

CPU Access

R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*

Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.

Binary-Coded-Decimal Operation (BCD_EN = 1)

Bit

Position

Value Description

[7:4]

0–9

The tens digit of the current year count.

TENS_YR

[3:0]

YR

0–9

The ones digit of the current year count.

Binary Operation (BCD_EN = 0)

Bit

Position

Value Description

[7:0]

YR

00h– The current year count.

63h

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Real-Time Clock

eZ80F91 MCU

Product Specification

175

Real-Time Clock Century Register

This register contains the current century count. The value in the RTC_CEN regis-

ter is unchanged by a RESET. The current setting of BCD_EN determines

whether the values in this register are binary (BCD_EN = 0) or binary-coded deci-

mal (BCD_EN = 1). Access to this register is Read Only if the RTC is locked and

Read/Write if the RTC is unlocked. See Table 87.

Table 87. Real-Time Clock Century Register

(RTC_CEN = 00E7h)

Bit

7

6

5

4

3

2

1

0

Reset

X

CPU Access

R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*

Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.

Binary-Coded-Decimal Operation (BCD_EN = 1)

Bit

Position

Value Description

[7:4]

0–9

The tens digit of the current century count.

TENS_CEN

[3:0]

CEN

0–9

The ones digit of the current century count.

Binary Operation (BCD_EN = 0)

Bit

Position

Value Description

[7:0]

CEN

00h– The current century count.

63h

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P R E L I M I N A R Y

Real-Time Clock

eZ80F91 MCU

Product Specification

176

Real-Time Clock Alarm Seconds Register

This register contains the alarm seconds value. The value in the RTC_ASEC reg-

ister is unchanged by a RESET. The current setting of BCD_EN determines

whether the values in this register are binary (BCD_EN = 0) or binary-coded deci-

mal (BCD_EN = 1). See Table 88.

Table 88. Real-Time Clock Alarm Seconds Register

(RTC_ASEC = 00E8h)

Bit

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

X

Reset

CPU Access

R/W

Note: X = Unchanged by RESET; R/W = Read/Write.

Binary-Coded-Decimal Operation (BCD_EN = 1)

Bit

Position

Value Description

[7:4]

0–5

The tens digit of the alarm seconds value.

ATEN_SEC

[3:0]

0–9

The ones digit of the alarm seconds value.

ASEC

Binary Operation (BCD_EN = 0)

Bit

Position

Value Description

[7:0]

ASEC

00h– The alarm seconds value.

3Bh

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eZ80F91 MCU

Product Specification

177

Real-Time Clock Alarm Minutes Register

This register contains the alarm minutes value. The value in the RTC_AMIN regis-

ter is unchanged by a RESET. The current setting of BCD_EN determines

whether the values in this register are binary (BCD_EN = 0) or binary-coded deci-

mal (BCD_EN = 1). See Table 89.

Table 89. Real-Time Clock Alarm Minutes Register

(RTC_AMIN = 00E9h)

Bit

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

X

Reset

CPU Access

R/W

Note: X = Unchanged by RESET; R/W = Read/Write.

Binary-Coded-Decimal Operation (BCD_EN = 1)

Bit

Position

Value Description

[7:4]

0–5

The tens digit of the alarm minutes value.

ATEN_MIN

[3:0]

0–9

The ones digit of the alarm minutes value.

AMIN

Binary Operation (BCD_EN = 0)

Bit

Position

Value Description

[7:0]

AMIN

00h– The alarm minutes value.

3Bh

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P R E L I M I N A R Y

Real-Time Clock

eZ80F91 MCU

Product Specification

178

Real-Time Clock Alarm Hours Register

This register contains the alarm hours value. The value in the RTC_AHRS register

is unchanged by a RESET. The current setting of BCD_EN determines whether

the values in this register are binary (BCD_EN = 0) or binary-coded decimal

(BCD_EN = 1). See Table 90.

Table 90. Real-Time Clock Alarm Hours Register

(RTC_AHRS = 00EAh)

Bit

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

X

Reset

CPU Access

R/W

Note: X = Unchanged by RESET; R/W = Read/Write.

Binary-Coded-Decimal Operation (BCD_EN = 1)

Bit

Position

Value Description

[7:4]

0–2

The tens digit of the alarm hours value.

ATEN_HRS

[3:0]

0–9

The ones digit of the alarm hours value.

AHRS

Binary Operation (BCD_EN = 0)

Bit

Position

Value Description

[7:0]

AHRS

00h– The alarm hours value.

17h

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P R E L I M I N A R Y

Real-Time Clock

eZ80F91 MCU

Product Specification

179

Real-Time Clock Alarm Day-of-the-Week Register

This register contains the alarm day-of-the-week value. The value in the

RTC_ADOW register is unchanged by a RESET. The current setting of BCD_EN

determines whether the value in this register is binary (BCD_EN = 0) or binary-

coded decimal (BCD_EN = 1). See Table 91.

Table 91. Real-Time Clock Alarm Day-of-the-Week Register

(RTC_ADOW = 00EBh)

Bit

7

0

6

0

5

0

4

0

3

2

1

0

Reset

X

CPU Access

R

R/W* R/W* R/W* R/W*

Note: X = Unchanged by RESET; R = Read Only; R/W* = Read Only if RTC locked, Read/Write if

RTC unlocked.

Binary-Coded-Decimal Operation (BCD_EN = 1)

Bit

Position

Value Description

[7:4]

0000 Reserved.

[3:0]

1–7

The alarm day-of-the-week.value.

ADOW

Binary Operation (BCD_EN = 0)

Bit

Position

Value Description

[7:4]

0000 Reserved.

[3:0]

ADOW

01h– The alarm day-of-the-week value.

07h

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P R E L I M I N A R Y

Real-Time Clock

eZ80F91 MCU

Product Specification

180

Real-Time Clock Alarm Control Register

This register contains control bits for the Real-Time Clock. The RTC_ACTRL reg-

ister is cleared by a RESET. See Table 92.

Table 92. Real-Time Clock Alarm Control Register

(RTC_ACTRL = 00ECh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R

R/W

Note: X = Unchanged by RESET; R = Read Only; R/W = Read/Write

Bit

Position

Value Description

[7:4]

0000 Reserved.

3

0

1

0

1

0

1

0

1

The day-of-the-week alarm is disabled.

ADOW_EN

The day-of-the-week alarm is enabled.

The hours alarm is disabled.

The hours alarm is enabled.

2

AHRS_EN

1

The minutes alarm is disabled.

The minutes alarm is enabled.

The seconds alarm is disabled.

The seconds alarm is enabled.

AMIN_EN

0

ASEC_EN

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Real-Time Clock

eZ80F91 MCU

Product Specification

181

Real-Time Clock Control Register

This register contains control and status bits for the Real-Time Clock. Some bits in

the RTC_CTRL register are cleared by a RESET. The ALARM bit flag and associ-

ated interrupt (if INT_EN is enabled) are cleared by reading this register. The

ALARM bit flag is updated by clearing (locking) the RTC_UNLOCK bit or by an

increment of the RTC count. Writing to the RTC_CTRL register also resets the

RTC count prescaler allowing the RTC to be synchronized to another time source.

SLP_WAKE indicates if an RTC alarm condition initiated the CPU recovery from

SLEEP mode. This bit can be checked after RESET to determine if a sleep-mode

recovery is caused by the RTC. SLP_WAKE is cleared by a Read of the

RTC_CTRL register.

Setting the BCD_EN bit causes the RTC to use BCD counting in all registers

including the alarm set points.

The CLK_SEL and FREQ_SEL bits select the RTC clock source. If the 32KHz

crystal option is selected the oscillator is enabled and the internal prescaler is set

to divide by 32768. If the power-line frequency option is selected, the prescale

value is set by the FREQ_SEL bit, and the 32Khz oscillator is disabled. See Table

93.

Table 93. Real-Time Clock Control Register

(RTC_CTRL = 00EDh)

Bit

7

X

R

6

0

5

X

4

X

3

X

2

X

1

0/1

R

0

Reset

CPU Access

R/W

Note: X = Unchanged by RESET; R = Read Only; R/W = Read/Write.

Bit

Position

Value Description

7

0

1

0

1

0

1

Alarm interrupt is inactive.

ALARM

Alarm interrupt is active.

6

Interrupt on alarm condition is disabled.

Interrupt on alarm condition is enabled.

INT_EN

5

RTC count and alarm value registers are binary.

BCD_EN

RTC count and alarm value registers are binary-coded

decimal (BCD).

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Real-Time Clock

eZ80F91 MCU

Product Specification

182

Bit

Position

Value Description

4

0

RTC clock source is crystal oscillator output (32768Hz).

On-chip 32768Hz oscillator is enabled.

CLK_SEL

1

RTC clock source is power-line frequency input.

On-chip 32768Hz oscillator is disabled.

3

0

1

0

1

0

1

0

Power-line frequency is 60Hz.

FREQ_SEL

Power-line frequency is 50Hz.

2

Daylight Savings Time not selected.

Daylight Savings Time selected.

DAY_SAV

1

RTC did not generate a sleep-mode recovery reset.

RTC Alarm generated a sleep-mode recovery reset.

SLP_WAKE

0

RTC count registers are locked to prevent write access.

RTC counter is enabled.

RTC_UNLOCK

1

RTC count registers are unlocked to allow write access.

RTC counter is disabled.

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eZ80F91 MCU

Product Specification

183

Universal Asynchronous Receiver/

Transmitter

The UART module implements all of the logic required to support the asynchro-

nous communications protocol. The module also implements two separate 16-

byte-deep FIFOs for both transmission and reception. A block diagram of the

UART is illustrated in Figure 35.

System Clock

Receive

RxD0/RxD1

Buffer

I/O Address

Transmit

Buffer

Data

TxD0/TxD1

Interrupt Signal

CTS0/CTS1

RTS0/RTS1

DSR0/DSR1

DTR0/DTR1

DCD0/DCD1

RI0/RI1

Modem

Control

Logic

Figure 35. UART Block Diagram

The UART module provides the following asynchronous communications proto-

col-related features and functions:

•

5-, 6-, 7-, 8- or 9-bit data transmission

Even/odd, space/mark, address/data, or no parity bit generation and detection

Start and stop bit generation and detection (supports up to two stop bits)

Line break detection and generation

Receiver overrun and framing errors detection

Logic and associated I/O to provide modem handshake capability

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eZ80F91 MCU

Product Specification

184

UART Functional Description

The UART Baud Rate Generator creates the clock for the serial transmit and

receive functions. The UART module supports all of the various options in the

asynchronous transmission and reception protocol including:

•

5- to 9-bit transmit/receive

Start bit generation and detection

Parity generation and detection

Stop bit generation and detection

Break generation and detection

The UART contains 16-byte-deep FIFOs in each direction. The FIFOs can be

enabled or disabled by the application. The receive FIFO features trigger-level

detection logic, which enables the CPU to block-transfer data bytes from the

receive FIFO.

UART Functions

The UART function implements:

•

The transmitter and associated control logic

The receiver and associated control logic

The modem interface and associated logic

UART Transmitter

The transmitter block controls the data transmitted on the TxD output. It imple-

ments the FIFO, access via the UARTx_THR register, the transmit shift register,

the parity generator, and control logic for the transmitter to control parameters for

the asynchronous communications protocol.

The UARTx_THR is a Write Only register. The CPU writes the data byte to be

transmitted into this register. In FIFO mode, up to 16 data bytes can be written via

the UARTx_THR register. The data byte from the FIFO is transferred to the trans-

mit shift register at the appropriate time and transmitted via TxD output. After

SYNC_RESET, the UARTx_THR register is empty. Therefore, the Transmit Hold-

ing Register Empty (THRE) bit (bit 5 of the UARTx_LSR register) is 1. An interrupt

is sent to the CPU if interrupts are enabled. The CPU can reset this interrupt by

loading data into the UARTx_THR register, which clears the transmitter interrupt.

The transmit shift register places the byte to be transmitted on the TxD signal seri-

ally. The least-significant bit of the byte to be transmitted is shifted out first and the

most-significant bit is shifted out last. The control logic within the block adds the

asynchronous communications protocol bits to the data byte being transmitted.

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eZ80F91 MCU

Product Specification

185

The transmitter block obtains the parameters for the protocol from the bits pro-

grammed via the UARTx_LCTL register. When enabled, an interrupt is generated

after the final protocol bit is transmitted, which the CPU can reset by loading data

into the UARTx_THR register. The TxD output is set to 1 if the transmitter is idle

(i.e., the transmitter does not contain any data to be transmitted).

The transmitter operates with the Baud Rate Generator (BRG) clock. The data

bits are placed on the TxD output one time every 16 BRG clock cycles. The trans-

mitter block also implements a parity generator that attaches the parity bit to the

byte, if programmed. For 9-bit data, the host CPU programs the parity bit genera-

tor so that it marks the byte as either address (mark parity) or data (space parity).

UART Receiver

The receiver block controls the data reception from the RxD signal. The receiver

block implements a receiver shift register, receiver line error condition monitoring

logic and receiver data ready logic. It also implements the parity checker.

The UARTx_RBR is a Read Only register of the module. The CPU reads received

data from this register. The condition of the UARTx_RBR register is monitored by

the DR bit (bit 0 of the UARTx_LSR register). The DR bit is 1 when a data byte is

received and transferred to the UARTx_RBR register from the receiver shift regis-

ter. The DR bit is reset only when the CPU reads all of the received data bytes. If

the number of bits received is less than eight, the unused most-significant bits of

the data byte Read are 0.

For 9-bit data, the receiver checks incoming bytes for space parity. A line status

interrupt is generated when an address byte is received, because address bytes

maintain high parity bits. The CPU clears the interrupt by determining if the

address matches its own, then configures the receiver to either accept the subse-

quent data bytes if the address matches, or ignore the data if the address does

not match.

The receiver uses the clock from the BRG for receiving the data. This clock must

operate at 16 times the appropriate baud rate. The receiver synchronizes the shift

clock on the falling edge of the RxD input start bit. It then receives a complete byte

according to the set parameters. The receiver also implements logic to detect

framing errors, parity errors, overrun errors, and break signals.

UART Modem Control

The modem control logic provides two outputs and four inputs for handshaking

with the modem. Any change in the modem status inputs, except RI, is detected

and an interrupt can be generated. For RI, an interrupt is generated only when the

trailing edge of the RI is detected. The module also provides LOOP mode for self-

diagnostics.

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eZ80F91 MCU

Product Specification

186

UART Interrupts

There are six different sources of interrupts from the UART. The six sources of

interrupts are:

•

Transmitter (two different interrupts)

Receiver (three different interrupts)

Modem status

UART Transmitter Interrupt

A Transmitter Hold Register Empty interrupt is generated if there is no data avail-

able in the hold register. By the same token, a transmission complete interrupt is

generated after the data in the shift register is sent. Both interrupts can be dis-

abled using individual interrupt enable bits, or cleared by writing data into the

UARTx_THR register.

UART Receiver Interrupts

A receiver interrupt can be generated by three possible events. The first event, a

receiver data ready interrupt event, indicates that one or more data bytes are

received and are ready to be read. Next, this interrupt is generated if the number

of bytes in the receiver FIFO is greater than or equal to the trigger level. If the

FIFO is not enabled, the interrupt is generated if the receive buffer contains a data

byte. This interrupt is cleared by reading the UARTx_RBR.

The second interrupt source is the receiver time-out. A receiver time-out interrupt

is generated when there are fewer data bytes in the receiver FIFO than the trigger

level and there are no Reads and Writes to or from the receiver FIFO for four con-

secutive byte times. When the receiver time-out interrupt is generated, it is

cleared only after emptying the entire receive FIFO.

The first two interrupt sources from the receiver (data ready and time-out) share

an interrupt enable bit. The third source of a receiver interrupt is a line status error,

indicating an error in byte reception. This error can result from:

•

Incorrect received parity

For 9-bit data, incorrect parity indicates detection of an address byte.

Note:

•

Incorrect framing (i.e., the stop bit) is not detected by receiver at the end of the

byte

•

Receiver overrun condition

A BREAK condition being detected on the receive data input

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eZ80F91 MCU

Product Specification

187

An interrupt due to one of the above conditions is cleared when the UARTx_LSR

register is read. In case of FIFO mode, a line status interrupt is generated only

after the received byte with an error reaches the top of the FIFO and is ready to be

read.

A line status interrupt is activated (provided this interrupt is enabled) as long as

the Read pointer of the receiver FIFO points to the location of the FIFO that con-

tains a byte with the error. The interrupt is immediately cleared when the

UARTx_LSR register is read. The ERR bit of the UARTx_LSR register is active as

long as an erroneous byte is present in the receiver FIFO.

UART Modem Status Interrupt

The modem status interrupt is generated if there is any change in state of the

modem status inputs to the UART. This interrupt is cleared when the CPU reads

the UARTx_MSR register.

UART Recommended Usage

The following standard sequence of events occurs in the UART block of the

eZ80F91 device. A description of each follows.

1. Module reset.

2. Control transfers to configure UART operation.

3. Data transfers.

Module Reset

Upon reset, all internal registers are set to their default values. All command sta-

tus registers are programmed with their default values, and the FIFOs are flushed.

Control Transfers

Based on the requirements of the application, the data transfer baud rate is deter-

mined and the BRG is configured to generate a 16X clock frequency. Interrupts

are disabled and the communication control parameters are programmed in the

UARTx_LCTL register. The FIFO configuration is determined and the receive trig-

ger levels are set in the UARTx_FCTL register. The status registers, UARTx_LSR

and UARTx_MSR, are read to ensure that none of the interrupt sources are

active. The interrupts are enabled (except for the transmit interrupt) and the appli-

cation is ready to use the module for transmission/reception.

Data Transfers

Transmit. To transmit data, the application enables the transmit interrupt. An inter-

rupt is immediately expected in response. The application reads the UARTx_IIR

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register and determines whether the interrupt occurs due to either an empty

UARTx_THR register or a completed transmission. When the application makes

this determination, it writes the transmit data bytes to the UARTx_THR register.

The number of bytes that the application writes depends on whether or not the

FIFO is enabled. If the FIFO is enabled, the application can write 16 bytes at a

time. If not, the application can write one byte at a time. As a result of the first

Write, the interrupt is deactivated. The CPU then waits for the next interrupt.

When the interrupt is raised by the UART module, the CPU repeats the same pro-

cess until it exhausts all of the data for transmission.

To control and check the modem status, the application sets up the modem by

writing to the UARTx_MCTL register and reading the UARTx_MCTL register

before starting the process described above.

Receive. The receiver is always enabled, and it continually checks for the start bit

on the RxD input signal. When an interrupt is raised by the UART module, the

application reads the UARTx_IIR register and determines the cause for the inter-

rupt. If the cause is a line status interrupt, the application reads the UARTx_LSR

register, reads the data byte and then can discard the byte or take other appropri-

ate action. If the interrupt is caused by a receive-data-ready condition, the appli-

cation alternately reads the UARTx_LSR and UARTx_RBR registers and

removes all of the received data bytes. It reads the UARTx_LSR register before

reading the UARTx_RBR register to determine that there is no error in the

received data.

To control and check modem status, the application sets up the modem by writing

to the UARTx_MCTL register and reading the UARTx_MSR register before start-

ing the process described above.

Poll Mode Transfers. When interrupts are disabled, all data transfers are referred

to as poll mode transfers. In poll mode transfers, the application must continually

poll the UARTx_LSR register to transmit or receive data without enabling the

interrupts. The same holds true for the UARTx_MSR register. If the interrupts are

not enabled, the data in the UARTx_IIR register cannot be used to determine the

cause of interrupt.

Baud Rate Generator

The Baud Rate Generator consists of a 16-bit downcounter, two registers, and

associated decoding logic. The initial value of the Baud Rate Generator is defined

by the two BRG Divisor Latch registers, {UARTx_BRG_H, UARTx_BRG_L}. At

the rising edge of each system clock, the BRG decrements until it reaches the

value 0001h. On the next system clock rising edge, the BRG reloads the initial

value from {UARTx_BRG_H, UARTx_BRG_L) and outputs a pulse to indicate the

end-of-count.

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Calculate the UART data rate with the following equation:

System Clock Frequency

UART Data Rate (bits/s)

=

16 X UART Baud Rate Generator Divisor

Upon RESET, the 16-bit BRG divisor value resets to the smallest allowable value

of 0002h. Therefore, the minimum BRG clock divisor ratio is 2. A software Write to

either the Low- or High-byte registers for the BRG Divisor Latch causes both the

Low and High bytes to load into the BRG counter, and causes the count to restart.

The divisor registers can only be accessed if bit 7 of the UART Line Control regis-

ter (UARTx_LCTL) is set to 1. After reset, this bit is reset to 0.

Recommended Use of the Baud Rate Generator

The following is the normal sequence of operations that should occur after the

eZ80F91 is powered on to configure the Baud Rate Generator:

1. Assert and deassert RESET.

2. Set UARTx_LCTL[7] to 1 to enable access of the BRG divisor registers.

3. Program the UARTx_BRG_L and UARTx_BRG_H registers.

4. Clear UARTx_LCTL[7] to 0 to disable access of the BRG divisor registers.

BRG Control Registers

UART Baud Rate Generator Register—Low and High Bytes

The registers hold the Low and High bytes of the 16-bit divisor count loaded by

the CPU for UART baud rate generation. The 16-bit clock divisor value is returned

by {UARTx_BRG_H, UARTx_BRG_L}, where x is either 0 or 1 to identify the two

available UART devices. Upon RESET, the 16-bit BRG divisor value resets to

0002h. The initial 16-bit divisor value must be between 0002hand FFFFh,

because the values 0000hand 0001hare invalid and proper operation is not guar-

anteed at these two values. As a result, the minimum BRG clock divisor ratio is 2.

A Write to either the Low- or High-byte registers for the BRG Divisor Latch causes

both bytes to be loaded into the BRG counter. The count is then restarted.

Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to

1 to access this register. See Tables 94 and 95. Refer to the UART Line Control

Register (UARTx_LCTL) on page 196 for more information.

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The UARTx_BRG_L registers share the same address space with the

Note:

UARTx_RBR and UARTx_THR registers. The UARTx_BRG_H registers share

the same address space with the UARTx_IER registers. Bit 7 of the associated

UART Line Control register (UARTx_LCTL) must be set to 1 to enable access to

the BRG registers.

Table 94. UART Baud Rate Generator Register—Low Bytes

(UART0_BRG_L = 00C0h, UART1_BRG_L = 00D0h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

Note: R = Read only; R/W = Read/Write.

Bit

Position

Value

Description

[7:0]

00h–

These bits represent the Low byte of the 16-bit Baud Rate

Generator divider value. The complete BRG divisor value is

returned by {UART_BRG_H, UART_BRG_L}.

UART_BRG_L FFh

Table 95. UART Baud Rate Generator Register—High Bytes

(UART0_BRG_H = 00C1h, UART1_BRG_H = 00D1h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

Note: R = Read only; R/W = Read/Write.

Bit

Position

Value

Description

[7:0]

00h–

These bits represent the High byte of the 16-bit Baud Rate

Generator divider value. The complete BRG divisor value is

returned by {UART_BRG_H, UART_BRG_L}.

UART_BRG_H FFh

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UART Registers

After a system reset, all UART registers are set to their default values. Any Writes

to unused registers or register bits are ignored and reads return a value of 0. For

compatibility with future revisions, unused bits within a register should always be

written with a value of 0. Read/Write attributes, reset conditions, and bit descrip-

tions of all of the UART registers are provided in this section.

UART Transmit Holding Register

If less than eight bits are programmed for transmission, the lower bits of the byte

written to this register are selected for transmission. The Transmit FIFO is

mapped at this address. The user can write up to 16 bytes for transmission at one

time to this address if the FIFO is enabled by the application. If the FIFO is dis-

abled, this buffer is only one byte deep.

These registers share the same address space as the UARTx_RBR and

UARTx_BRG_L registers. See Table 96.

Table 96. UART Transmit Holding Registers

(UART0_THR = 00C0h, UART1_THR = 00D0h)

Bit

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

X

Reset

CPU Access

Note: W = Write Only.

W

Bit

Position

Value

Description

Transmit data byte.

[7:0]

TxD

00h–

FFh

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UART Receive Buffer Register

The bits in this register reflect the data received. If less than eight bits are pro-

grammed for reception, the lower bits of the byte reflect the bits received, whereas

upper unused bits are 0. The Receive FIFO is mapped at this address. If the FIFO

is disabled, this buffer is only one byte deep.

These registers share the same address space as the UARTx_THR and

UARTx_BRG_L registers. See Table 97.

Table 97. UART Receive Buffer Registers

(UART0_RBR = 00C0h, UART1_RBR = 00D0h)

Bit

7

X

R

6

X

R

5

X

R

4

X

R

3

X

R

2

X

R

1

X

R

0

X

R

Reset

CPU Access

Note: R = Read only.

Bit

Position

Value

Description

Receive data byte.

[7:0]

RxD

00h–

FFh

UART Interrupt Enable Register

The UARTx_IER register is used to enable and disable the UART interrupts. The

UARTx_IER registers share the same I/O addresses as the UARTx_BRG_H reg-

isters. See Table 98.

Table 98. UART Interrupt Enable Registers

(UART0_IER = 00C1h, UART1_IER = 00D1h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

000

0

Description

[7:5]

Reserved

4

Transmission complete interrupt is disabled

TCIE

1

Transmission complete interrupt is generated when both the

transmit hold register and the transmit shift register are empty

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Bit

Position

Value

Description

3

MIIE

0

1

0

1

Modem interrupt on edge detect of status inputs is disabled.

Modem interrupt on edge detect of status inputs is enabled.

Line status interrupt is disabled.

2

LSIE

Line status interrupt is enabled for receive data errors:

incorrect parity bit received, framing error, overrun error, or

break detection.

1

TIE

0

1

Transmit interrupt is disabled.

Transmit interrupt is enabled. Interrupt is generated when the

transmit FIFO/buffer is empty indicating no more bytes

available for transmission.

0

RIE

0

1

Receive interrupt is disabled.

Receive interrupt and receiver time-out interrupt are enabled.

Interrupt is generated if the FIFO/buffer contains data ready to

be read or if the receiver times out.

UART Interrupt Identification Register

The Read Only UARTx_IIR register allows the user to check whether the FIFO is

enabled and the status of interrupts. These registers share the same I/O

addresses as the UARTx_FCTL registers. See Tables 99 and 100.

Table 99. UART Interrupt Identification Registers

(UART0_IIR = 00C2h, UART1_IIR = 00D2h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

Reset

CPU Access

Note: R = Read only.

R

Bit

Position

Value

Description

[7:6]

FSTS

00

10

11

00

FIFO is disabled.

Receive FIFO is disabled (Multidrop Mode)

FIFO is enabled.

[5:4]

Reserved

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Bit

Position

Value

Description

[3:1]

INSTS

000–

110

Interrupt Status Code

The code indicated in these three bits is valid only if INTBIT is

1. If two internal interrupt sources are active and their

respective enable bits are High, only the higher priority

interrupt is seen by the application. The lower-priority interrupt

code is indicated only after the higher-priority interrupt is

serviced. Table 100 lists the interrupt status codes.

0

1

There is an active interrupt source within the UART.

There is not an active interrupt source within the UART.

INTBIT

Table 100. UART Interrupt Status Codes

INSTS

Value

011

010

110

101

001

000

Priority

Highest

Second

Third

Interrupt Type

Receiver Line Status

Receive Data Ready or Trigger Level

Character Time-out

Fourth

Fifth

Transmission Complete

Transmit Buffer Empty

Modem Status

Lowest

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UART FIFO Control Register

This register is used to monitor trigger levels, clear FIFO pointers, and enable or

disable the FIFO. The UARTx_FCTL registers share the same I/O addresses as

the UARTx_IIR registers. See Table 101.

Table 101. UART FIFO Control Registers

(UART0_FCTL = 00C2h, UART1_FCTL = 00D2h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: W = Write Only.

W

Bit

Position

Value

Description

[7:6]

TRIG

00

01

10

11

Receive FIFO trigger level set to 1. Receive data interrupt is

generated when there is 1 byte in the FIFO. Valid only if FIFO

is enabled.

Receive FIFO trigger level set to 4. Receive data interrupt is

generated when there are 4bytes in the FIFO. Valid only if

FIFO is enabled.

Receive FIFO trigger level set to 8. Receive data interrupt is

generated when there are 8 bytes in the FIFO. Valid only if

FIFO is enabled.

Receive FIFO trigger level set to 14. Receive data interrupt is

generated when there are 14 bytes in the FIFO. Valid only if

FIFO is enabled.

[5:3]

000b

Reserved—must be 000b.

No effect.

2

0

1

CLRTxF

Clear the transmit FIFO and reset the transmit FIFO pointer.

Valid only if the FIFO is enabled.

1

0

1

No effect.

CLRRxF

Clear the receive FIFO, clear the receive error FIFO, and

reset the receive FIFO pointer. Valid only if the FIFO is

enabled.

0

1

Transmit and receive FIFOs are disabled. Transmit and

receive buffers are only 1 byte deep.

FIFOEN

Transmit and receive FIFOs are enabled. Note: Receive FIFO

will not be enabled during Multidrop Mode.

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UART Line Control Register

This register is used to control the communication control parameters. See

Tables 102 and 103.

Table 102. UART Line Control Registers

(UART0_LCTL = 00C3h, UART1_LCTL = 00D3h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

7

0

Access to the UART registers at I/O addresses C0h, C1h,

D0h and D1h is enabled.

DLAB

1

Access to the Baud Rate Generator registers at I/O addresses

C0h, C1h, D0h and D1h is enabled.

6

SB

0

1

Do not send a BREAK signal.

Send Break

UART sends continuous zeroes on the transmit output from

the next bit boundary. The transmit data in the transmit shift

register is ignored. After forcing this bit High, the

is 0 only after the bit boundary is reached. Just before forcing

to 0, the transmit FIFO is cleared. Any new data written

TxD output

TxD

to the transmit FIFO during a break should be written only

after the THRE bit of UARTx_LSR register goes High. This

new data is transmitted after the UART recovers from the

break. After the break is removed, the UART recovers from

the break for the next BRG edge.

5

FPE

0

1

Do not force a parity error.

Force a parity error. When this bit and the party enable bit

(pen) are both 1, an incorrect parity bit is transmitted with the

data byte.

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Bit

Position

Value

Description

4

0

Even Parity Select

EPS

Use odd parity for transmit and receive. The total number of 1

bits in the transmit data plus parity bit is odd. Used as SPACE

bit in Multidrop Mode. See Table 104 for parity select

definitions. Note: Receive Parity is set to SPACE in multidrop

mode.

1

Use even parity for transmit and receive. The total number of

1 bits in the transmit data plus parity bit is even. Used as

MARK bit in Multidrop Mode. See Table 104 for parity select

definitions.

3

PEN

0

1

Parity bit transmit and receive is disabled.

Parity bit transmit and receive is enabled. For transmit, a

parity bit is generated and transmitted with every data

character. For receive, the parity is checked for every

incoming data character. In Multidrop Mode, receive parity is

checked for space parity.

[2:0]

CHAR

000–

111

UART Character Parameter Selection

See Table 103 for a description of the values.

Table 103. UART Character Parameter Definition

Character Length

(Tx/Rx Data Bits)

Stop Bits

(Tx Stop Bits)

CHAR[2:0]

000

5

6

7

8

5

6

7

8

1

2

001

010

011

100

101

110

111

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Table 104. Parity Select Definition for Multidrop Communications

Multidrop

Mode

Even Parity

Select

Parity Type

odd

0

1

0

1

even

0

space

mark

1*

Note: *In Multidrop Mode, EPS resets to 0 after the

first character is sent.

UART Modem Control Register

This register is used to control and check the modem status. See Table 105.

Table 105. UART Modem Control Registers

(UART0_MCTL = 00C4h, UART1_MCTL = 00D4h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R

R/W

Note: R = Read Only; R/W = Read/Write.

Bit

Position

Value

Description

7

0

1

0

1

Reserved

6

TxD and RxD signals—Normal Polarity.

Invert Polarity of TxD and RxD signals.

Multidrop Mode disabled.

POLARITY

5

MDM

Multidrop Mode enabled. See Table 104 for parity select

definitions.

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Bit

Position

Value

Description

4

0

1

LOOP BACK mode is not enabled.

LOOP BACK mode is enabled.

LOOP

The UART operates in internal LOOP BACK mode. The

transmit data output port is disconnected from the internal

transmit data output and set to 1. The receive data input port

is disconnected and internal receive data is connected to

internal transmit data. The modem status input ports are

disconnected and the four bits of the modem control register

are connected as modem status inputs. The two modem

control output ports (OUT1&2) are set to their inactive state

3

0–1

No function in normal operation.

In LOOP BACK mode, this bit is connected to the DCD bit in

the UART Status Register.

OUT2

2

No function in normal operation.

In LOOP BACK mode, this bit is connected to the RI bit in the

UART Status Register.

OUT1

1

Request to Send

RTS

In normal operation, the RTS output port is the inverse of this

bit. In LOOP BACK mode, this bit is connected to the CTS bit

in the UART Status Register.

0

0–1

Data Terminal Ready.

DTR

In normal operation, the DTR output port is the inverse of this

bit. In LOOP BACK mode, this bit is connected to the DSR bit

in the UART Status Register.

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UART Line Status Register

This register is used to show the status of UART interrupts and registers. See

Table 106.

Table 106. UART Line Status Registers

(UART0_LSR = 00C5h, UART1_LSR = 00D5h)

Bit

7

0

6

1

5

1

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read only.

R

Bit

Position

Value

Description

7

ERR

0

Always 0 when operating in with the FIFO disabled. With the

FIFO enabled, this bit is reset when the UARTx_LSR register

is read and there are no more bytes with error status in the

FIFO.

1

0

1

Error detected in the FIFO. There is at least 1 parity, framing

or break indication error in the FIFO.

6

Transmit holding register/FIFO is not empty or transmit shift

register is not empty or transmitter is not idle.

TEMT

Transmit holding register/FIFO and transmit shift register are

empty; and the transmitter is idle. This bit cannot be set to 1

during the BREAK condition. This bit only becomes 1 after the

BREAK command is removed.

5

0

1

Transmit holding register/FIFO is not empty.

THRE

Transmit holding register/FIFO. This bit cannot be set to 1

during the BREAK condition. This bit only becomes 1 after the

BREAK command is removed.

4

BI

0

1

Receiver does not detect a BREAK condition. This bit is reset

to 0 when the UARTx_LSR register is read.

Receiver detects a BREAK condition on the receive input line.

This bit is 1 if the duration of BREAK condition on the receive

data is longer than one character transmission time, the time

depends on the programming of the UARTx_LSR register. In

case of FIFO only one null character is loaded into the

receiver FIFO with the framing error. The framing error is

revealed to the eZ80 whenever that particular data is read

from the receiver FIFO.

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Bit

Position

Value

Description

3

FE

0

No framing error detected for character at the top of the FIFO.

This bit is reset to 0 when the UARTx_LSR register is read.

1

0

Framing error detected for the character at the top of the

FIFO. This bit is set to 1 when the stop bit following the data/

parity bit is logic 0.

2

PE

The received character at the top of the FIFO does not

contain a parity error. In multidrop mode, this indicates that

the received character is a data byte. This bit is reset to 0

when the UARTx_LSR register is read.

1

0

1

The received character at the top of the FIFO contains a parity

error. In multidrop mode, this indicates that the received

character is an address byte.

1

OE

The received character at the top of the FIFO does not

contain an overrun error. This bit is reset to 0 when the

UARTx_LSR register is read.

Overrun error is detected. If the FIFO is not enabled, this

indicates that the data in the receive buffer register was not

read before the next character was transferred into the

receiver buffer register. If the FIFO is enabled, this indicates

the FIFO was already full when an additional character was

received by the receiver shift register. The character in the

receiver shift register is not put into the receiver FIFO.

0

DR

0

1

This bit is reset to 0 when the UARTx_RBR register is read or

all bytes are read from the receiver FIFO.

Data ready. If the FIFO is not enabled, this bit is set to 1 when

a complete incoming character is transferred into the receiver

buffer register from the receiver shift register. If the FIFO is

enabled, this bit is set to 1 when a character is received and

transferred to the receiver FIFO.

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UART Modem Status Register

This register is used to show the status of the UART signals. See Table 107.

Table 107. UART Modem Status Registers

(UART0_MSR = 00C6h, UART1_MSR = 00D6h)

Bit

7

X

R

6

X

R

5

X

R

4

X

R

3

X

R

2

X

R

1

X

R

0

X

R

Reset

CPU Access

Note: R = Read only.

Bit

Position

Value

Description

Data Carrier Detect

In NORMAL mode, this bit reflects the inverted state of the

DCDx input pin. In LOOP BACK mode, this bit reflects the

value of the UARTx_MCTL[3] = out2.

7

DCD

0–1

6

RI

Ring Indicator

In NORMAL mode, this bit reflects the inverted state of the RIx

input pin. In LOOP BACK mode, this bit reflects the value of

the UARTx_MCTL[2] = out1.

5

DSR

Data Set Ready

In NORMAL mode, this bit reflects the inverted state of the

DSRx input pin. In LOOP BACK mode, this bit reflects the

value of the UARTx_MCTL[0] = DTR.

4

Clear to Send

CTS

In NORMAL mode, this bit reflects the inverted state of the

CTSx input pin. In LOOP BACK mode, this bit reflects the

value of the UARTx_MCTL[1] = RTS.

3

0–1

Delta Status Change of DCD

This bit is set to 1 whenever the DCDx pin changes state. This

bit is reset to 0 when the UARTx_MSR register is read.

DDCD

2

Trailing Edge Change on RI.

TERI

This bit is set to 1 whenever a falling edge is detected on the

RIx pin. This bit is reset to 0 when the UARTx_MSR register is

read.

1

0–1

Delta Status Change of DSR

This bit is set to 1 whenever the DSRx pin changes state. This

bit is reset to 0 when the UARTx_MSR register is read.

DDSR

0

Delta Status Change of CTS

DCTS

This bit is set to 1 whenever the CTSx pin changes state.

This bit is reset to 0 when the UARTx_MSR register is read.

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eZ80F91 MCU

Product Specification

203

UART Scratch Pad Register

The UARTx_SPR register can be used by the system as a general-purpose Read/

Write register. See Table 108.

Table 108. UART Scratch Pad Registers

(UART0_SPR = 00C7h, UART1_SPR = 00D7h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

[7:0]

SPR

00h–

FFh

UART scratch pad register is available for use as a general-

purpose Read/Write register.

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P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter

eZ80F91 MCU

Product Specification

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Infrared Encoder/Decoder

The eZ80F91 device contains a UART to an infrared encoder/decoder (endec).

The endec is integrated with the on-chip UART0 to allow easy communication

between the CPU and IrDA Physical Layer Specification Version 1.4-compatible

infrared transceivers, as illustrated in Figure 36. Infrared communication provides

secure, reliable, high-speed, low-cost, point-to-point communication between

PCs, PDAs, mobile telephones, printers and other infrared-enabled devices.

eZ80F91

System

Clock

Infrared

Transceiver

RxD

TxD

IR_RxD

IR_TxD

RxD

TxD

Infrared

Encoder/Decoder

UART0

Baud Rate

Clock

Interrupt

I/O

Data

I/O

Address

Data

Signal Address

®

To eZ80 CPU

Figure 36. Infrared System Block Diagram

Functional Description

When the endec is enabled, the transmit data from the on-chip UART is encoded

as digital signals in accordance with the IrDA standard and output to the infrared

transceiver. Likewise, data received from the infrared transceiver is decoded by

the endec and passed to the UART. Communication is half-duplex, meaning that

simultaneous data transmission and reception is not allowed.

The baud rate is set by the UART Baud Rate Generator, which supports IrDA

standard baud rates from 9600 bits/s to 115.2 KBPS. Higher baud rates are possi-

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Infrared Encoder/Decoder

eZ80F91 MCU

Product Specification

205

ble, but do not meet IrDA specifications. The UART must be enabled to use the

endec. Refer to the section covering the Universal Asynchronous Receiver/Trans-

mitter on page 183 for more information on the UART and its Baud Rate Genera-

tor.

Transmit

The data to be transmitted via the IR transceiver is first data sent to UART0. The

UART transmit signal, TxD, and Baud Rate Clock are used by the endec to gener-

ate the modulation signal, IR_TxD, that drives the infrared transceiver. Each

UART bit is 16 clocks wide. If the data to be transmitted is a logical 1 (High), the

IR_TxD signal remains Low (0) for the full 16-clock period. If the data to be trans-

mitted is a logical 0, a 3-clock High (1) pulse is output following a 7-clock Low (0)

period. Following the 3-clock High pulse, a 6-clock Low pulse completes the full

16-clock data period. Data transmission is illustrated in Figure 37. During data

transmission, the IR receive function should be disabled by clearing the IR_RxEN

bit in the IR_CTL reg to 0 to prevent transmitter-to-receiver crosstalk.

16-clock

period

Baud Rate

Clock

UART_TxD

IR_TxD

Start Bit = 0

Data Bit 0 = 1

Data Bit 1 = 0

Data Bit 2 = 1

Data Bit 3 = 1

3-clock

pulse

7-clock

delay

Figure 37. Infrared Data Transmission

Receive

Data received from the IR transceiver via the IR_RxD signal is decoded by the

endec and passed to the UART. The IR_RxEN bit in the IR_CTL register must be

set to enable the receiver decoder. The SIR data format uses half duplex commu-

nication. Therefore, the UART should not be allowed to transmit while the receiver

decoder is enabled. The UART Baud Rate Clock is used by the endec to generate

the demodulated signal, RxD, that drives the UART. Each UART bit is 16 clocks

wide. If the data to be received is a logical 1 (High), the IR_RxD signal remains

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Product Specification

206

High (1) for the full 16-clock period. If the data to be received is a logical 0, a 3-

clock Low (0) pulse is output following a 7-clock High (1) period. Following the 3-

clock Low pulse is a 6-clock High pulse to complete the full 16-clock data period.

Data transmission is illustrated in Figure 38.

16-clock

period

Baud Rate

Clock

Start Bit = 0

1.6 µs

Data Bit 0 = 1

Data Bit 1 = 0

Data Bit 2 = 1

Data Bit 3 = 1

IR_RxD

min. pulse

UART_RxD

16-clock

period

16-clock

period

16-clock

period

16-clock

period

8-clock

delay

Figure 38. Infrared Data Reception

The infrared encoder/decoder samples the incoming IR pulses using the baud

rate clock divided by 16. This sampling rate can be insufficient to capture the

incoming pulses when they use a short pulse (1.6µs) format and low data rates.

When the external transmitter sends a short pulse of 3 clocks of 16 clock periods

(IR_RxD), the infrared encoder/decoder receives the data properly.

Note:

Jitter

Due to the inherent sampling of the received IR_RxD signal by the Bit Rate Clock,

some jitter can be expected on the first bit in any sequence of data. However, all

subsequent bits in the received data stream are a fixed 16 clock periods wide.

Infrared Encoder/Decoder Signal Pins

The endec signal pins, IR_TxD and IR_RxD, are multiplexed with General-Pur-

pose I/O (GPIO) pins. These GPIO pins must be configured for alternate function

operation for the endec to operate.

The remaining six UART0 pins, CTS0, DCD0, DSR0, DTR0, RTS and RI0, are not

required for use with the endec. The UART0 modem status interrupt should be

disabled to prevent unwanted interrupts from these pins. The GPIO pins corre-

sponding to these six unused UART0 pins can be used for inputs, outputs, or

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interrupt sources. Recommended GPIO Port D control register settings are pro-

vided in Table 109. Refer to the section covering the General-Purpose Input/Out-

put, on page 58 for additional information on setting the GPIO Port modes.

Table 109. GPIO Mode Selection when using the IrDA Encoder/Decoder

GPIO Port D Allowable GPIO

Bits

Port Mode

Allowable Port Mode Functions

Alternate Function

PD0

7

PD1

Alternate Function

PD2–PD7

Any other than GPIO Mode 7

(1, 2, 3, 4, 5, 6, 8, or 9)

Output, Input, Open-Drain, Open-Source, Level-

sensitive Interrupt Input, or Edge-Triggered Interrupt

Input

Loopback Testing

Both internal and external loopback testing can be accomplished with the endec

on the eZ80F91 device. Internal loopback testing is enabled by setting the

LOOP_BACK bit to 1. During internal loopback, the IR_TxD output signal is

inverted and connected on-chip to the IR_RxD input. External loopback testing of

the off-chip IrDA transceiver can be accomplished by transmitting data from the

UART while the receiver is enabled (IR_RxEN set to 1).

Infrared Encoder/Decoder Register

After a RESET, the Infrared Encoder/Decoder Register is set to its default value.

Any Writes to unused register bits are ignored and reads return a value of 0. The

IR_CTL register is described in Table 110.

Table 110. Infrared Encoder/Decoder Control Registers

(IR_CTL = 00BFh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R

R/W

Note: R = Read only; R/W = Read/Write.

Bit

Position

Value

Description

[7:3]

00000 Reserved.

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P R E L I M I N A R Y

Infrared Encoder/Decoder

eZ80F91 MCU

Product Specification

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Bit

Position

Value

Description

2

0

1

Internal LOOP BACK mode is disabled.

LOOP_BACK

Internal LOOP BACK mode is enabled.

IR_TxD output is inverted and connected to IR_RxD input for

internal loop back testing.

1

0

1

0

1

IR_RxD data is ignored.

IR_RxEN

IR_RxD data is passed to UART0

Endec is disabled.

RxD.

0

IR_EN

Endec is enabled.

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Product Specification

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Serial Peripheral Interface

The Serial Peripheral Interface (SPI) is a synchronous interface allowing several

SPI-type devices to be interconnected. The SPI is a full-duplex, synchronous,

character-oriented communication channel that employs a four-wire interface. The

SPI block consists of a transmitter, receiver, baud rate generator, and control unit.

During an SPI transfer, data is sent and received simultaneously by both the mas-

ter and the slave SPI devices.

In a serial peripheral interface, separate signals are required for data and clock.

The SPI can be configured as either a master or a slave. The connection of two

SPI devices (one master and one slave) and the direction of data transfer is dem-

onstrated in Figures 39 and 40 .

MASTER

SS

MISO

Bit 0

Bit 7

DATAOUT

CLKOUT

DATAIN

SCK

8-Bit Shift Register

Baud Rate

Generator

Figure 39. SPI Master Device

SLAVE

SS

ENABLE

MOSI

SCK

Bit 0

Bit 7

MISO

DATAOUT

DATAIN

CLKIN

8-Bit Shift Register

Figure 40. SPI Slave Device

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P R E L I M I N A R Y

Serial Peripheral Interface

eZ80F91 MCU

Product Specification

210

SPI Signals

The four basic SPI signals are:

•

MISO (Master In, Slave Out)

MOSI (Master Out, Slave In)

SCK (SPI Serial Clock)

SS (Slave Select)

These SPI signals are discussed in the following paragraphs. Each signal is

described in both MASTER and SLAVE modes.

Master In, Slave Out

The Master In, Slave Out (MISO) pin is configured as an input in a master device

and as an output in a slave device. It is one of the two lines that transfer serial

data, with the most-significant bit sent first. The MISO pin of a slave device is

placed in a high-impedance state if the slave is not selected. When the SPI is not

enabled, this signal is in a high-impedance state.

Master Out, Slave In

The Master Out, Slave In (MOSI) pin is configured as an output in a master device

and as an input in a slave device. It is one of the two lines that transfer serial data,

with the most-significant bit sent first. When the SPI is not enabled, this signal is in

a high-impedance state.

Slave Select

The active Low Slave Select (SS) input signal is used to select the SPI as a slave

device. It must be Low prior to all data communication and must stay Low for the

duration of the data transfer.

The SS input signal must be High for the SPI to operate as a master device. If the

SS signal goes Low, a Mode Fault error flag (MODF) is set in the SPI_SR register.

See the SPI Status Register (SPI_SR) on page 217 for more information.

When the Clock Phase (CPHA) is set to 0, the shift clock is the logical OR of SS

with SCK. In this clock phase mode, SS must go High between successive char-

acters in an SPI message. When CPHA is set to 1, SS can remain Low for several

SPI characters. In cases where there is only one SPI slave, its SS line could be

tied Low as long as CPHA is set to 1. See the SPI Control Register (SPI_CTL) on

page 216 for more information on CPHA.

Serial Clock

The Serial Clock (SCK) is used to synchronize data movement both in and out of

the device via its MOSI and MISO pins. The master and slave are each capable of

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exchanging a byte of data during a sequence of eight clock cycles. Because SCK

is generated by the master, the SCK pin becomes an input on a slave device. The

SPI contains an internal divide-by-two clock divider. In MASTER mode, the SPI

serial clock is one-half the frequency of the clock signal created by the SPI’s Baud

Rate Generator.

As demonstrated in Figure 41 and Table 111, four possible timing relations can be

chosen by using the clock polarity (CPOL) and CPHA control bits in the SPI Con-

trol register. See the SPI Control Register (SPI_CTL) on page 216. Both the mas-

ter and slave must operate with the identical timing, CPOL, and CPHA. The

master device always places data on the MOSI line a half-cycle before the clock

edge (SCK signal), for the slave device to latch the data.

Number of Cycles on the SCK Signal

1

2

3

4

5

6

7

8

SCK (CPOL bit = 0)

SCK (CPOL bit = 1)

Sample Input

(CPHA bit = 0) Data Out

MSB

6

5

4

3

2

1

LSB

Sample Input

(CPHA bit = 1) Data Out

MSB

6

5

4

3

2

1

LSB

ENABLE (To Slave)

Figure 41. SPI Timing

Table 111. SPI Clock Phase and Clock Polarity Operation

SS High

SCK

Transmit

Edge

SCK

Receive

Edge

SCK

Idle

State

Between

Characters?

CPHA

CPOL

0

1

Falling

Rising

Falling

Low

Yes

High

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Table 111. SPI Clock Phase and Clock Polarity Operation (Continued)

SS High

SCK

Transmit

Edge

SCK

Receive

Edge

SCK

Idle

State

Between

Characters?

CPHA

CPOL

1

0

1

Rising

Falling

Rising

Low

No

High

SPI Functional Description

When a master transmits to a slave device via the MOSI signal, the slave device

responds by sending data to the master via the master's MISO signal. The result-

ing implication is a full-duplex transmission, with both data out and data in syn-

chronized with the same clock signal. As a result, the byte transmitted is replaced

by the byte received to eliminate the requirement for separate transmit-empty and

receive-full status bits. A single status bit, SPIF, is used to signify that the I/O oper-

ation is complete. See the SPI Status Register (SPI_SR) on page 217.

The SPI is double-buffered during reads, but not during Writes. If a Write is per-

formed during data transfer, the transfer occurs uninterrupted, and the Write is

unsuccessful. This condition causes the write collision (WCOL) status bit in the

SPI_SR register to be set. After a data byte is shifted, the SPIF flag of the SPI_SR

register is set to 1.

In SPI MASTER mode, the SCK pin functions as an output. It idles High or Low

depending on the CPOL bit in the SPI_CTL register until data is written to the shift

register. Data transfer is initiated by writing to the transmit shift register, SPI_TSR.

Eight clocks are then generated to shift the eight bits of transmit data out via the

MOSI pin while shifting in eight bits of data via the MISO pin. After transfer, the

SCK signal becomes idle.

In SPI SLAVE mode, the start logic receives a logic Low from the SS pin and a

clock input at the SCK pin; as a result, the slave is synchronized to the master.

Data from the master is received serially from the slave MOSI signal and is loaded

into the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel-

transferred to the Read buffer. During a Write cycle, data is written into the shift

register. Next, the slave waits for the SPI master to initiate a data transfer, supply

a clock signal, and shift the data out on the slave's MISO signal.

If the CPHA bit in the SPI_CTL register is 0, a transfer begins when the SS pin

signal goes Low. The transfer ends when SS goes High after eight clock cycles on

SCK. When the CPHA bit is set to 1, a transfer begins the first time SCK becomes

active while SS is Low. The transfer ends when the SPIF flag is set to 1.

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SPI Flags

Mode Fault

The Mode Fault flag (MODF) indicates that there can be a multimaster conflict in

the system control. The MODF bit is normally cleared to 0 and is only set to 1

when the master device’s SS pin is pulled Low. When a mode fault is detected,

the following sequence occurs:

1. The MODF flag (SPI_SR[4]) is set to 1.

2. The SPI device is disabled by clearing the SPI_EN bit (SPI_CTL[5]) to 0.

3. The MASTER_EN bit (SPI_CTL[4]) is cleared to 0, forcing the device into

SLAVE mode.

4. If the SPI interrupt is enabled by setting IRQ_EN (SPI_CTL[7]) High, an SPI

interrupt is generated.

Clearing the Mode Fault flag is performed by reading the SPI Status register. The

other SPI control bits (SPI_EN and MASTER_EN) must be restored to their origi-

nal states by user software after the Mode Fault flag is cleared to 0.

Write Collision

The write collision flag, WCOL (SPI_SR[5]), is set to 1 when an attempt is made to

write to the SPI Transmit Shift register (SPI_TSR) while data transfer occurs.

Clearing the WCOL bit is performed by reading SPI_SR with the WCOL bit set to

1.

SPI Baud Rate Generator

The SPI’s Baud Rate Generator creates a lower frequency clock from the high-fre-

quency system clock. The Baud Rate Generator output is used as the clock

source by the SPI.

Baud Rate Generator Functional Description

The SPI’s Baud Rate Generator consists of a 16-bit downcounter, two 8-bit regis-

ters, and associated decoding logic. The Baud Rate Generator’s initial value is

defined by the two BRG Divisor Latch registers {SPI_BRG_H, SPI_BRG_L}. At

the rising edge of each system clock, the BRG decrements until it reaches the

value 0001h. On the next system clock rising edge, the BRG reloads the initial

value from {SPI_BRG_H, SPI_BRG_L) and outputs a pulse to indicate the end of

the count.

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The SPI Data Rate can be calculated using the following equation:

System Clock Frequency

SPI Data Rate (bits/s)

=

2 X SPI Baud Rate Generator Divisor

Upon RESET, the 16-bit BRG divisor value resets to 0002h. When the SPI is oper-

ating as a Master, the BRG divisor value must be set to a value of 0003hor

greater. When the SPI is operating as a Slave, the BRG divisor value must be set

to a value of 0004hor greater. A software Write to either the Low- or High-byte

registers for the BRG Divisor Latch causes both the Low and High bytes to load

into the BRG counter, and causes the count to restart.

Data Transfer Procedure with SPI Configured as a Master

The sequence that follows details the procedure for transferring data from a mas-

ter SPI device to a slave SPI device.

1. Load the SPI Baud Rate Generator Registers, SPI_BRG_H and SPI_BRG_L.

The external device must deassert the SS pin if currently asserted.

2. Load the SPI Control Register, SPI_CTL.

3. Assert the ENABLE pin of the slave device using a GPIO pin.

4. Load the SPI Transmit Shift Register, SPI_TSR.

5. When the SPI data transfer is complete, deassert the ENABLE pin of the slave

device.

Data Transfer Procedure with SPI Configured as a Slave

The sequence that follows details the procedure for transferring data from a slave

SPI device to a master SPI device.

1. Load the SPI Baud Rate Generator Registers, SPI_BRG_H and SPI_BRG_L.

2. Load the SPI Transmit Shift Register, SPI_TSR. This load cannot occur while

the SPI slave is currently receiving data.

3. Wait for the external SPI Master device to initiate the data transfer by

asserting SS.

SPI Registers

There are six registers in the Serial Peripheral Interface that provide control, sta-

tus, and data storage functions. The SPI registers are described in the following

paragraphs.

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SPI Baud Rate Generator Registers—Low Byte and High Byte

These registers hold the Low and High bytes of the 16-bit divisor count loaded by

the CPU for baud rate generation. The 16-bit clock divisor value is returned by

{SPI_BRG_H, SPI_BRG_L}. Upon RESET, the 16-bit BRG divisor value resets to

0002h. When configured as a Master, the 16-bit divisor value must be between

0003hand FFFFh, inclusive. When configured as a Slave, the 16-bit divisor value

must be between 0004hand FFFFh, inclusive.

A Write to either the Low- or High-byte registers for the BRG Divisor Latch causes

both bytes to be loaded into the BRG counter and a restart of the count. See

Tables 112 and 113.

Table 112. SPI Baud Rate Generator Register—Low Byte

(SPI_BRG_L = 00B8h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

[7:0]

SPI_BRG_L

00h–

FFh

These bits represent the Low byte of the 16-bit Baud Rate

Generator divider value. The complete BRG divisor value is

returned by {SPI_BRG_H, SPI_BRG_L}.

Table 113. SPI Baud Rate Generator Register—High Byte

(SPI_BRG_H = 00B9h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

[7:0]

SPI_BRG_H

00h–

FFh

These bits represent the High byte of the 16-bit Baud Rate

Generator divider value. The complete BRG divisor value is

returned by {SPI_BRG_H, SPI_BRG_L}.

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SPI Control Register

This register is used to control and setup the serial peripheral interface. The SPI

should be disabled prior to making any changes to CPHA or CPOL. See Table

114.

Table 114. SPI Control Register

(SPI_CTL = 00BAh)

Bit

7

0

6

0

5

0

4

0

3

0

2

1

0

Reset

CPU Access

R/W

R

R/W

R

Note: R = Read Only; R/W = Read/Write.

Bit

Position

Value Description

7

0

1

0

1

0

1

0

1

0

1

00

SPI system interrupt is disabled.

SPI system interrupt is enabled.

Reserved.

IRQ_EN

6

5

SPI is disabled.

SPI_EN

SPI is enabled.

4

When enabled, the SPI operates as a slave.

When enabled, the SPI operates as a master.

Master SCK pin idles in a Low (0) state.

Master SCK pin idles in a High (1) state.

MASTER_EN

3

CPOL

2

SS must go High after transfer of every byte of data.

CPHA

SS can remain Low to transfer any number of data bytes.

Reserved.

[1:0]

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SPI Status Register

The SPI Status Read Only register returns the status of data transmitted using the

serial peripheral interface. Reading the SPI_SR register clears Bits 7, 6, and 4 to

a logical 0. See Table 115.

Table 115. SPI Status Register

(SPI_SR = 00BBh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value Description

7

SPIF

0

1

SPI data transfer is not finished.

SPI data transfer is finished. If enabled, an interrupt is

generated. This bit flag is cleared to 0 by a Read of the

SPI_SR register.

6

0

1

An SPI write collision is not detected.

WCOL

An SPI write collision is detected. This bit flag is cleared to 0

by a Read of the SPI_SR registers.

5

0

1

Reserved.

4

A mode fault (multimaster conflict) is not detected.

MODF

A mode fault (multimaster conflict) is detected. This bit flag is

cleared to 0 by a Read of the SPI_SR register.

[3:0]

0000 Reserved.

SPI Transmit Shift Register

The SPI Transmit Shift register (SPI_TSR) is used by the SPI master to transmit

data over SPI serial bus to the slave device. A Write to the SPI_TSR register

places data directly into the shift register for transmission. A Write to this register

within an SPI device configured as a master initiates transmission of the byte of

the data loaded into the register. At the completion of transmitting a byte of data,

the SPIF status bit (SPI_SR[7]) is set to 1 in both the master and slave devices.

The SPI Transmit Shift Write Only register shares the same address space as the

SPI Receive Buffer Read Only register. See Table 116.

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Table 116. SPI Transmit Shift Register

(SPI_TSR = 00BCh)

Bit

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

X

Reset

CPU Access

Note: W = Write Only.

W

Bit

Position

Value Description

[7:0]

TX_DATA

00h– SPI transmit data.

FFh

SPI Receive Buffer Register

The SPI Receive Buffer register (SPI_RBR) is used by the SPI slave to receive

data from the serial bus. The SPIF bit must be cleared prior to a second transfer of

data from the shift register; otherwise, an overrun condition exists. In the event of

an overrun, the byte that causes the overrun is lost.

The SPI Receive Buffer Read Only register shares the same address space as

the SPI Transmit Shift Write Only register. See Table 117.

Table 117. SPI Receive Buffer Register

(SPI_RBR = 00BCh)

Bit

7

X

R

6

X

R

5

X

R

4

X

R

3

X

R

2

X

R

1

X

R

0

X

R

Reset

CPU Access

Note: R = Read Only.

Bit

Position

Value Description

[7:0]

RX_DATA

00h– SPI received data.

FFh

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2

I C Serial I/O Interface

I²C General Characteristics

2

The Inter-Integrated Circuit (I C) serial I/O bus is a two-wire communication inter-

face that can operate in four modes:

•

MASTER TRANSMIT

MASTER RECEIVE

SLAVE TRANSMIT

SLAVE RECEIVE

2

The I C interface consists of a Serial Clock (SCL) and Serial Data (SDA). Both

SCL and SDA are bidirectional lines connected to a positive supply voltage via an

external pull-up resistor. When the bus is free, both lines are High. The output

stages of devices connected to the bus must be configured as open-drain outputs.

2

Data on the I C bus can be transferred at a rate of up to 100kbps in STANDARD

mode, or up to 400kbps in FAST mode. One clock pulse is generated for each

data bit transferred.

Clocking Overview

2

If another device on the I C bus drives the clock line when the I C is in MASTER

2

mode, the I C synchronizes its clock to the I C bus clock. The High period of the

clock is determined by the device that generates the shortest High clock period.

The Low period of the clock is determined by the device that generates the long-

est Low clock period.

A slave can stretch the Low period of the clock to slow down the bus master. The

Low period can also be stretched for handshaking purposes. This result can be

2

accomplished after each bit transfer or each byte transfer. The I C stretches the

clock after each byte transfer until the IFLG bit in the I2C_CTL register is cleared

to 0.

Bus Arbitration Overview

2

In MASTER mode, the I C checks that each transmitted logic 1 appears on the

2

I C bus as a logic 1. If another device on the bus overrules and pulls the SDA sig-

nal Low, arbitration is lost. If arbitration is lost during the transmission of a data

2

byte or a Not Acknowledge (NACK) bit, the I C returns to an idle state. If arbitra-

2

tion is lost during the transmission of an address, the I C switches to SLAVE

mode so that it can recognize its own slave address or the general call address.

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Data Validity

The data on the SDA line must be stable during the High period of the clock. The

High or Low state of the data line can only change when the clock signal on the

SCL line is Low, as illustrated in Figure 42.

SDA Signal

SCL Signal

Data Line

Stable

Change of

Data Allowed

Data Valid

2

Figure 42. I C Clock and Data Relationship

START and STOP Conditions

2

Within the I C bus protocol, unique situations arise which are defined as START

and STOP conditions. Figure 43 illustrates a High-to-Low transition on the SDA

line while SCL is High, indicating a START condition. A Low-to-High transition on

the SDA line while SCL is High defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is

considered to be busy after a START condition. The bus is considered to be free

for a defined time after a STOP condition.

SDA Signal

SCL Signal

S

P

START Condition

STOP Condition

2

Figure 43. START and STOP Conditions In I C Protocol

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Transferring Data

Byte Format

Every character transferred on the SDA line must be a single 8-bit byte. The num-

ber of bytes that can be transmitted per transfer is unrestricted. Each byte must

1

be followed by an Acknowledge (ACK) . Data is transferred with the most-signifi-

cant bit (msb) first. Figure 44 illustrates a receiver that holds the SCL line Low to

force the transmitter into a wait state. Data transfer then continues when the

receiver is ready for another byte of data and releases SCL.

SDA Signal

SCL Signal

MSB

1

Acknowledge from

Receiver

Acknowledge from

Receiver

2

8

9

1

9

S

P

ACK

START Condition

STOP Condition

Clock Line Held Low By Receiver

2

Figure 44. I C Frame Structure

Acknowledge

Data transfer with an ACK function is obligatory. The ACK-related clock pulse is

generated by the master. The transmitter releases the SDA line (High) during the

ACK clock pulse. The receiver must pull down the SDA line during the ACK clock

pulse so that it remains stable (Low) during the High period of this clock pulse.

See Figure 45.

A receiver that is addressed is obliged to generate an ACK after each byte is

received. When a slave receiver does not acknowledge the slave address (for

example, unable to receive because it is performing some real-time function), the

data line must be left High by the slave. The master then generates a STOP con-

dition to abort the transfer.

If a slave receiver acknowledges the slave address, but cannot receive any more

data bytes, the master must abort the transfer. The abort is indicated by the slave

generating the Not Acknowledge (NACK) on the first byte to follow. The slave

leaves the data line High and the master generates the STOP condition.

2

1. ACK is defined as a general Acknowledge bit. By contrast, the I C

2

Acknowledge bit is represented as AAK, bit 2 of the I C Control Register,

which identifies which ACK signal to transmit. See Table 127 on page 235.

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If a master receiver is involved in a transfer, it must signal the end of the data

stream to the slave transmitter by not generating an ACK on the final byte that is

clocked out of the slave. The slave transmitter must release the data line to allow

the master to generate a STOP or a repeated START condition.

Data Output

by Transmitter

MSB

Data Output

by Receiver

1

S

SCL Signal

from Master

1

2

8

9

START Condition

Clock Pulse for Acknowledge

2

Figure 45. I C Acknowledge

Clock Synchronization

All masters generate their own clocks on the SCL line to transfer messages on the

2

I C bus. Data is only valid during the High period of each clock.

2

Clock synchronization is performed using the wired AND connection of the I C

interfaces to the SCL line, meaning that a High-to-Low transition on the SCL line

causes the relevant devices to start counting from their Low period. When a

device clock goes Low, it holds the SCL line in that state until the clock High state

is reached. See Figure 46. The Low-to-High transition of this clock, however, can

not change the state of the SCL line if another clock is still within its Low period.

The SCL line is held Low by the device with the longest Low period. Devices with

shorter Low periods enter a High wait state during this time.

When all devices count off the Low period, the clock line is released and goes

High. There is no difference between the device clocks and the state of the SCL

line; all of the devices start counting the High periods. The first device to complete

its High period again pulls the SCL line Low. In this way, a synchronized SCL

clock is generated with its Low period determined by the device with the longest

clock Low period, and its High period determined by the device with the shortest

clock High period.

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Wait

State

Start Counting

High Period

CLK1 Signal

Counter

Reset

CLK2 Signal

SCL Signal

2

Figure 46. Clock Synchronization In I C Protocol

Arbitration

Any master can initiate a transfer if the bus is free. As a result, multiple masters

can each generate a START condition if the bus is free within a minimum period. If

multiple masters generate a START condition, a START is defined for the bus.

However, arbitration defines which MASTER controls the bus. Arbitration takes

place on the SDA line. As mentioned, START conditions are initiated only while

the SCL line is held High. If, during this period, a master (M1) initiates a High-to-

Low transition—i.e., a START condition—while a second master (M2) transmits a

Low signal on the line, then the first master, M1, cannot take control of the bus. As

a result, the data output stage for M1 is disabled.

Arbitration can continue for many bits. Its first stage is comparison of the address

bits. If the masters are each trying to address the same device, arbitration contin-

ues with a comparison of the data. Because address and data information on the

2

I C bus is used for arbitration, no information is lost during this process. A master

that loses the arbitration can generate clock pulses until the end of the byte in

which it loses the arbitration.

If a master also incorporates a slave function and it loses arbitration during the

addressing stage, it is possible that the winning master is trying to address it. The

losing master must switch over immediately to its slave receiver mode. Figure 46

illustrates the arbitration procedure for two masters. Of course, more can be

involved, depending on how many masters are connected to the bus. The

moment there is a difference between the internal data level of the master gener-

ating DATA 1 and the actual level on the SDA line, its data output is switched off,

which means that a High output level is then connected to the bus. As a result, the

data transfer initiated by the winning master is not affected. Because control of the

2

I C bus is decided solely on the address and data sent by competing masters,

there is no central master, nor any order of priority on the bus.

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Special attention must be paid if, during a serial transfer, the arbitration procedure

is still in progress at the moment when a repeated START condition or a STOP

2

condition is transmitted to the I C bus. If it is possible for such a situation to occur,

the masters involved must send this repeated START condition or STOP condition

at the same position in the format frame. In other words, arbitration is not allowed

between:

•

A repeated START condition and a data bit

A STOP condition and a data bit

A repeated START condition and a STOP condition

Clock Synchronization for Handshake

The clock-synchronizing mechanism can function as a handshake, enabling

receivers to cope with fast data transfers, on either a byte or a bit level. The byte

level allows a device to receive a byte of data at a fast rate, but allows the device

more time to store the received byte or to prepare another byte for transmission.

Slaves hold the SCL line Low after reception and acknowledge the byte, forcing

the master into a wait state until the slave is ready for the next byte transfer in a

handshake procedure.

Operating Modes

Master Transmit

2

In MASTER TRANSMIT mode, the I C transmits a number of bytes to a slave

receiver.

Enter MASTER TRANSMIT mode by setting the STA bit in the I2C_CTL register

2

to 1. The I C then tests the I C bus and transmits a START condition when the

bus is free. When a START condition is transmitted, the IFLG bit is 1 and the sta-

tus code in the I2C_SR register is 08h. Before this interrupt is serviced, the

I2C_DR register must be loaded with either a 7-bit slave address or the first part

of a 10-bit slave address, with the lsb cleared to 0 to specify TRANSMIT mode.

The IFLG bit should now be cleared to 0 to prompt the transfer to continue.

After the 7-bit slave address (or the first part of a 10-bit address) plus the Write bit

are transmitted, the IFLG is set again. A number of status codes are possible in

the I2C_SR register. See Table 118.

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2

Table 118. I C Master Transmit Status Codes

2

Code

I C State

Microcontroller Response

Next I C Action

18h

Addr+W transmitted

ACK received

For a 7-bit address: write byte Transmit data byte,

1

to DATA, clear IFLG

receive ACK.

Or set STA, clear IFLG

Transmit repeated

START.

Or set STP, clear IFLG

Transmit STOP.

Or set STA & STP, clear IFLG Transmit STOP

then START.

For a 10-bit address: write

Transmit extended

extended address byte to data, address byte.

clear IFLG

20h

38h

Addr+W transmitted, Same as code 18h

ACK not received

Same as code 18h.

Arbitration lost

Clear IFLG

Return to idle.

Or set STA, clear IFLG

Transmit START

when bus is free.

2

68h

Arbitration lost,

+W received,

Clear IFLG, AAK = 0

Receive data byte,

transmit NACK.

ACK transmitted

Or clear IFLG, AAK = 1

Same as code 68h

Receive data byte,

transmit ACK.

78h

B0h

Arbitration lost,

General call address

received, ACK

transmitted

Same as code 68h.

Arbitration lost,

SLA+R received,

ACK transmitted

Write byte to DATA, clear

IFLG, clear AAK = 0

Transmit last byte,

receive ACK.

3

Or write byte to DATA, clear

IFLG, set AAK = 1

Transmit data byte,

receive ACK.

Notes:

1. W is defined as the Write bit; i.e., the lsb is cleared to 0.

2

2. AAK is an I C control bit that identifies which ACK signal to transmit.

3. R is defined as the Read bit; i.e., the lsb is set to 1.

If 10-bit addressing is used, the status code is 18hor 20hafter the first part of a

10-bit address, plus the Write bit, are successfully transmitted.

After this interrupt is serviced and the second part of the 10-bit address is trans-

mitted, the I2C_SR register contains one of the codes listed in Table 119.

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2

Table 119. I C 10-Bit Master Transmit Status Codes

2

Code

I C State

Microcontroller Response

Clear IFLG

Next I C Action

38h

Arbitration lost

Return to idle

Or set STA, clear IFLG

Transmit START

when bus free

2

68h

B0h

D0h

Arbitration lost,

SLA+W received,

ACK transmitted

Clear IFLG, clear AAK = 0

Receive data byte,

transmit NACK

1

Or clear IFLG, set AAK = 1

Receive data byte,

transmit ACK

Arbitration lost,

SLA+R received,

ACK transmitted

Write byte to DATA,

clear IFLG, clear AAK = 0

Transmit last byte,

receive ACK

3

Or write byte to DATA,

clear IFLG, set AAK = 1

Transmit data byte,

receive ACK

Second address byte Write byte to data,

+ W transmitted,

ACK received

Transmit data byte,

receive ACK

clear IFLG

Or set STA, clear IFLG

Transmit repeated

START

Or set STP, clear IFLG

Transmit STOP

Or set STA & STP,

clear IFLG

Transmit STOP

then

START

D8h

Second address byte Same as code D0h

+ W transmitted,

Same as code D0h

ACK not received

Notes:

1. W is defined as the Write bit; i.e., the lsb is cleared to 0.

2

2. AAK is an I C control bit that identifies which ACK signal to transmit.

3. R is defined as the Read bit; i.e., the lsb is set to 1.

If a repeated START condition is transmitted, the status code is 10hinstead of

08h.

After each data byte is transmitted, the IFLG is set to 1 and one of the status

codes listed in Table 120 is loaded into the I2C_SR register.

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2

Table 120. I C Master Transmit Status Codes For Data Bytes

2

Code

I C State

Microcontroller Response

Next I C Action

28h

Data byte transmitted, Write byte to data,

Transmit data byte,

receive ACK.

ACK received

clear IFLG

Or set STA, clear IFLG

Transmit repeated

START.

Or set STP, clear IFLG

Transmit STOP.

Or set STA & STP,

clear IFLG

Transmit START

then STOP.

30h

38h

Data byte transmitted, Same as code 28h

ACK not received

Same as code 28h.

Arbitration lost

Clear IFLG

Return to idle.

Or set STA, clear IFLG

Transmit START

when bus free.

When all bytes are transmitted, the microcontroller should write a 1 to the STP bit

2

in the I2C_CTL register. The I C then transmits a STOP condition, clears the STP

bit and returns to an idle state.

Master Receive

2

In MASTER RECEIVE mode, the I C receives a number of bytes from a slave

transmitter.

After the START condition is transmitted, the IFLG bit is 1 and the status code 08h

is loaded into the I2C_SR register. The I2C_DR register should be loaded with the

slave address (or the first part of a 10-bit slave address), with the lsb set to 1 to

signify a Read. The IFLG bit should be cleared to 0 as a prompt for the transfer to

continue.

When the 7-bit slave address (or the first part of a 10-bit address) and the Read

bit are transmitted, the IFLG bit is set and one of the status codes listed in Table

121 is loaded into the I2C_SR register.

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2

Table 121. I C Master Receive Status Codes

2

Code

I C State

Microcontroller Response

Next I C Action

40h

Addr + R transmitted, For a 7-bit address,

Receive data byte,

transmit NACK

1

ACK received

clear IFLG, AAK = 0

Or clear IFLG, AAK = 1

Receive data byte,

transmit ACK

For a 10-bit address

Write extended address

byte to data, clear IFLG

Transmit extended

address byte

48h

Addr + R transmitted, For a 7-bit address:

Transmit repeated

START

2

ACK not received

Set STA, clear IFLG

Or set STP, clear IFLG

Transmit STOP

Or set STA & STP,

clear IFLG

Transmit STOP

then START

For a 10-bit address:

Transmit extended

Write extended address byte to address byte

data, clear IFLG

38h

68h

Arbitration lost

Clear IFLG

Return to idle

Or set STA, clear IFLG

Transmit START

when bus is free

Arbitration lost,

SLA+W received,

ACK transmitted

Clear IFLG, clear AAK = 0

Or clear IFLG, set AAK = 1

Same as code 68h

Receive data byte,

transmit NACK

3

Receive data byte,

transmit ACK

78h

B0h

Arbitration lost,

General call addr

received, ACK

transmitted

Same as code 68h

Arbitration lost,

SLA+R received,

ACK transmitted

Write byte to DATA,

clear IFLG, clear AAK = 0

Transmit last byte,

receive ACK

Or write byte to DATA,

clear IFLG, set AAK = 1

Transmit data byte,

receive ACK

Notes:

2

1. AAK is an I C control bit that identifies which ACK signal to transmit.

2. R is defined as the Read bit; i.e., the lsb is set to 1.

3. W is defined as the Write bit; i.e., the lsb is cleared to 0.

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If 10-bit addressing is being used, the slave is first addressed using the full 10-bit

address, plus the Write bit. The master then issues a restart followed by the first

part of the 10-bit address again, this time with the Read bit. The status code then

becomes 40hor 48h. It is the responsibility of the slave to remember that it had

been selected prior to the restart.

If a repeated START condition is received, the status code is 10hinstead of 08h.

After each data byte is received, the IFLG is set to 1 and one of the status codes

listed in Table 122 is loaded into the I2C_SR register.

2

Table 122. I C Master Receive Status Codes For Data Bytes

2

Code

I C State

Microcontroller Response

Next I C Action

50h

Data byte received,

ACK transmitted

Read data, clear IFLG,

clear AAK = 0*

Receive data byte,

transmit NACK

Or read data, clear IFLG,

set AAK = 1

Receive data byte,

transmit ACK

58h

Data byte received,

NACK transmitted

Read data, set STA,

clear IFLG

Transmit repeated

START

Or read data, set STP,

clear IFLG

Transmit STOP

Or read data, set

STA & STP, clear IFLG

Transmit STOP

then

START

38h

Arbitration lost in

NACK bit

Same as master transmit

Same as master

transmit

2

Note: AAK is an I C control bit that identifies which ACK signal to transmit.

When all bytes are received, a NACK should be sent, then the microcontroller

2

should write a 1 to the STP bit in the I2C_CTL register. The I C then transmits a

STOP condition, clears the STP bit and returns to an idle state.

Slave Transmit

In SLAVE TRANSMIT mode, a number of bytes are transmitted to a master

receiver.

2

The I C enters SLAVE TRANSMIT mode when it receives its own slave address

2

and a Read bit after a START condition. The I C then transmits an ACK bit (if the

AAK bit is set to 1); it then sets the IFLG bit in the I2C_CTL register. As a result,

the I2C_SR register contains the status code A8h.

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2

When I C contains a 10-bit slave address (signified by the address range F0h–

F7hin the I2C_SAR register), it transmits an ACK when the first address byte is

received after a restart. An interrupt is generated and IFLG is set to 1; however,

the status does not change. No second address byte is sent by the master. It is up

to the slave to remember it had been selected prior to the restart.

Note:

2

I C goes from MASTER mode to SLAVE TRANSMIT mode when arbitration is

lost during the transmission of an address, and the slave address and Read bit

are received. This action is represented by the status code B0hin the I2C_SR reg-

ister.

The data byte to be transmitted is loaded into the I2C_DR register and the IFLG bit

2

is cleared to 0. After the I C transmits the byte and receives an ACK, the IFLG bit

is set to 1 and the I2C_SR register contains B8h. When the final byte to be trans-

mitted is loaded into the I2C_DR register, the AAK bit is cleared when the IFLG is

cleared to 0. After the final byte is transmitted, the IFLG is set and the I2C_SR reg-

2

ister contains C8hand the I C returns to an idle state. The AAK bit must be set to

1 before reentering SLAVE mode.

If no ACK is received after transmitting a byte, the IFLG is set and the I2C_SR reg-

2

ister contains C0h. The I C then returns to an idle state.

2

If a STOP condition is detected after an ACK bit, the I C returns to an idle state.

Slave Receive

In SLAVE RECEIVE mode, a number of data bytes are received from a master

transmitter.

2

The I C enters SLAVE RECEIVE mode when it receives its own slave address

2

and a Write bit (lsb = 0) after a START condition. The I C transmits an ACK bit and

sets the IFLG bit in the I2C_CTL register and the I2C_SR register contains the sta-

2

tus code 60h. The I C also enters SLAVE RECEIVE mode when it receives the

general call address 00h(if the GCE bit in the I2C_SAR register is set). The status

code is then 70h.

2

When the I C contains a 10-bit slave address (signified by F0h–F7hin the

Note:

I2C_SAR register), it transmits an acknowledge after the first address byte is

received but no interrupt is generated. IFLG is not set and the status does not

2

change. The I C generates an interrupt only after the second address byte is

2

received. The I C sets the IFLG bit and loads the status code as described above.

2

I C goes from MASTER mode to SLAVE RECEIVE mode when arbitration is lost

during the transmission of an address, and the slave address and Write bit (or the

general call address if the CGE bit in the I2C_SAR register is set to 1) are

received. The status code in the I2C_SR register is 68hif the slave address is

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received or 78hif the general call address is received. The IFLG bit must be

cleared to 0 to allow data transfer to continue.

If the AAK bit in the I2C_CTL register is set to 1 then an ACK bit (Low level on

SDA) is transmitted and the IFLG bit is set after each byte is received. The I2C_SR

register contains the two status codes 80hor 90hif SLAVE RECEIVE mode is

entered with the general call address. The received data byte can be read from

the I2C_DR register and the IFLG bit must be cleared to allow the transfer to con-

tinue. If a STOP condition or a repeated START condition is detected after the

acknowledge bit, the IFLG bit is set and the I2C_SR register contains status code

A0h.

2

If the AAK bit is cleared to 0 during a transfer, the I C transmits a NACK bit (High

level on SDA) after the next byte is received, and sets the IFLG bit to 1. The

I2C_SR register contains the two status codes 88hor 98hif SLAVE RECEIVE

2

mode is entered with the general call address. The I C returns to an idle state

when the IFLG bit is cleared to 0.

I²C Registers

Addressing

The CPU interface provides access to six 8-bit registers: four Read/Write regis-

ters, one Read Only register and two Write Only registers, as indicated in Table

123.

2

Table 123. I C Register Descriptions

Register

I2C_SAR

I2C_XSAR

I2C_DR

Description

Slave address register

Extended slave address register

Data byte register

I2C_CTL

I2C_SR

Control register

Status register (Read Only)

Clock Control register (Write Only)

Software reset register (Write Only)

I2C_CCR

I2C_SRR

2

Resetting the I C Registers

2

Hardware Reset. When the I C is reset by a hardware reset of the eZ80F91

device, the I2C_SAR, I2C_XSAR, I2C_DR, and I2C_CTL registers are cleared to

00h; while the I2C_SR register is set to F8h.

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Software Reset. Perform a software reset by writing any value to the I C Software

Reset Register (I2C_SRR). A software reset clears the STP, STA, and IFLG bits of

2

the I2C_CTL register to 0 and sets the I C back to an idle state.

2

I C Slave Address Register

2

The I2C_SAR register provides the 7-bit address of the I C when in SLAVE mode

and allows 10-bit addressing in conjunction with the I2C_XSAR register.

2

I2C_SAR[7:1] = SLA[6:0] is the 7-bit address of the I C when in 7-bit SLAVE

2

mode. When the I C receives this address after a START condition, it enters

2

SLAVE mode. I2C_SAR[7] corresponds to the first bit received from the I C bus.

When the register receives an address starting with F7hto F0h(I2C_SAR[7:3] =

2

11110b), the I C recognizes that a 10-bit slave addressing mode is being selected.

2

The I C sends an ACK after receiving the I2C_SAR byte (the device does not

generate an interrupt at this point). After the next byte of the address (I2C_XSAR)

2

is received, the I C generates an interrupt and enters SLAVE mode.Then

I2C_SAR[2:1] are used as the upper 2 bits for the 10-bit extended address. The

full 10-bit address is supplied by {I2C_SAR[2:1], I2C_XSAR[7:0]}. See Table 124.

2

Table 124. I C Slave Address Register

(I2C_SAR = 00C8h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value Description

00h– 7-bit slave address or upper 2 bits,I2C_SAR[2:1], of address

[7:1]

SLA

7Fh

when operating in 10-bit mode.

2

0

I C not enabled to recognize the General Call Address.

GCE

2

1

I C enabled to recognize the General Call Address.

2

I C Extended Slave Address Register

The I2C_XSAR register is used in conjunction with the I2C_SAR register to pro-

2

vide 10-bit addressing of the I C when in SLAVE mode. The I2C_SAR value

forms the lower 8 bits of the 10-bit slave address. The full 10-bit address is sup-

plied by {I2C_SAR[2:1], I2C_XSAR[7:0]}.

When the register receives an address starting with F7hto F0h(I2C_SAR[7:3] =

2

11110b), the I C recognizes that a 10-bit slave addressing mode is being selected.

2

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2

The I C sends an ACK after receiving the I2C_XSAR byte (the device does not

generate an interrupt at this point). After the next byte of the address (I2C_XSAR)

2

is received, the I C generates an interrupt and enters SLAVE mode.Then

I2C_SAR[2:1] are used as the upper 2 bits for the 10-bit extended address. The

full 10-bit address is supplied by {I2C_SAR[2:1], I2C_XSAR[7:0]}. See Table 125.

2

Table 125. I C Extended Slave Address Register

(I2C_XSAR = 00C9h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value Description

[7:0]

SLAX

00h– Least-significant 8 bits of the 10-bit extended slave address.

FFh

2

I C Data Register

This register contains the data byte/slave address to be transmitted or the data

byte just received. In TRANSMIT mode, the most-significant bit of the byte is

transmitted first. In RECEIVE mode, the first bit received is placed in the most-sig-

nificant bit of the register. After each byte is transmitted, the I2C_DR register con-

tains the byte that is present on the bus in case a lost arbitration event occurs.

See Table 126.

2

Table 126. I C Data Register

(I2C_DR = 00CAh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value Description

2

[7:0]

00h– I C data byte.

DATA

FFh

2

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2

I C Control Register

The I2C_CTL register is a control register that is used to control the interrupts and

2

the master slave relationships on the I C bus.

When the Interrupt Enable bit (IEN) is set to 1, the interrupt line goes High when

the IFLG is set to 1. When IEN is cleared to 0, the interrupt line always remains

Low.

2

When the Bus Enable bit (ENAB) is set to 0, the I C bus inputs SCLx and SDAx

2

are ignored and the I C module does not respond to any address on the bus.

2

When ENAB is set to 1, the I C responds to calls to its slave address and to the

general call address if the GCE bit (I2C_SAR[0]) is set to 1.

2

When the Master Mode Start bit (STA) is set to 1, the I C enters MASTER mode

and sends a START condition on the bus when the bus is free. If the STA bit is set

2

to 1 when the I C module is already in MASTER mode and one or more bytes are

transmitted, then a repeated START condition is sent. If the STA bit is set to 1

2

when the I C block is being accessed in SLAVE mode, the I C completes the data

transfer in SLAVE mode and then enters MASTER mode when the bus is

released. The STA bit is automatically cleared after a START condition is set.

Writing a 0 to the STA bit produces no effect.

If the Master Mode Stop bit (STP) is set to 1 in MASTER mode, a STOP condition

2

is transmitted on the I C bus. If the STP bit is set to 1 in slave move, the I C mod-

ule operates as if a STOP condition is received, but no STOP condition is trans-

2

mitted. If both STA and STP bits are set, the I C block first transmits the STOP

condition (if in MASTER mode), then transmits the START condition. The STP bit

is cleared to 0 automatically. Writing a 0 to this bit produces no effect.

2

The I C Interrupt Flag (IFLG) is set to 1 automatically when any of 30 of the possi-

2

ble 31 I C states is entered. The only state that does not set the IFLG bit is state

F8h. If IFLG is set to 1 and the IEN bit is also set, an interrupt is generated. When

2

IFLG is set by the I C, the Low period of the I C bus clock line is stretched and the

data transfer is suspended. When a 0 is written to IFLG, the interrupt is cleared

2

and the I C clock line is released.

2

When the I C Acknowledge bit (AAK) is set to 1, an acknowledge is sent during

2

the acknowledge clock pulse on the I C bus if:

•

Either the whole of a 7-bit slave address or the first or second byte of a 10-bit

slave address is received

The general call address is received and the General Call Enable bit in

I2C_SAR is set to 1

A data byte is received while in MASTER or SLAVE modes

2

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When AAK is cleared to 0, a NACK is sent when a data byte is received in MAS-

TER or SLAVE mode. If AAK is cleared to 0 in SLAVE TRANSMIT mode, the byte

in the I2C_DR register is assumed to be the final byte. After this byte is transmit-

2

ted, the I C block enters the C8hstate, then returns to an idle state. The I C mod-

ule does not respond to its slave address unless AAK is set to 1. See Table 127.

2

Table 127. I C Control Register

(I2C_CTL = 00CBh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

R

Note: R/W = Read/Write; R = Read Only.

Bit

Position

Value Description

2

7

IEN

0

1

0

I C interrupt is disabled.

2

I C interrupt is enabled.

2

6

The I C bus (SCL/SDA) is disabled and all inputs are

ignored.

ENAB

2

1

0

1

0

1

0

1

0

1

00

The I C bus (SCL/SDA) is enabled.

5

STA

Master mode START condition is sent.

Master mode start-transmit START condition on the bus.

Master mode STOP condition is sent.

4

STP

Master mode stop-transmit STOP condition on the bus.

2

3

IFLG

I C interrupt flag is not set.

2

I C interrupt flag is set.

2

AAK

Not Acknowledge.

Acknowledge.

Reserved.

[1:0]

2

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2

I C Status Register

The I2C_SR register is a Read Only register that contains a 5-bit status code in

the five most-significant bits; the three least-significant bits are always 0. The

Read Only I2C_SR registers share the same I/O addresses as the Write Only

I2C_CCR registers. See Table 128.

2

Table 128. I C Status Registers

(I2C_SR = 00CCh)

Bit

7

1

6

1

5

1

4

1

3

1

2

0

1

0

Reset

CPU Access

Note: R = Read only.

R

Bit

Position

Value

Description

2

[7:3]

STAT

00000– 5-bit I C status code.

11111

[2:0]

000

Reserved.

There are 29 possible status codes, as listed in Table 129. When the I2C_SR reg-

ister contains the status code F8h, no relevant status information is available, no

interrupt is generated, and the IFLG bit in the I2C_CTL register is not set. All other

2

status codes correspond to a defined state of the I C.

When each of these states is entered, the corresponding status code appears in

this register and the IFLG bit in the I2C_CTL register is set to 1. When the IFLG bit

is cleared, the status code returns to F8h.

2

Table 129. I C Status Codes

Code

00h

08h

10h

18h

20h

28h

30h

Status

Bus error.

START condition transmitted.

Repeated START condition transmitted.

Address and Write bit transmitted, ACK received.

Address and Write bit transmitted, ACK not received.

Data byte transmitted in MASTER mode, ACK received.

Data byte transmitted in MASTER mode, ACK not received.

2

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2

Table 129. I C Status Codes (Continued)

Code

38h

40h

48h

50h

58h

60h

68h

Status

Arbitration lost in address or data byte.

Address and Read bit transmitted, ACK received.

Address and Read bit transmitted, ACK not received.

Data byte received in MASTER mode, ACK transmitted.

Data byte received in MASTER mode, NACK transmitted.

Slave address and Write bit received, ACK transmitted.

Arbitration lost in address as master, slave address and Write bit received,

ACK transmitted.

70h

78h

General Call address received, ACK transmitted.

Arbitration lost in address as master, General Call address received, ACK

transmitted.

80h

88h

90h

98h

A0h

A8h

B0h

Data byte received after slave address received, ACK transmitted.

Data byte received after slave address received, NACK transmitted.

Data byte received after General Call received, ACK transmitted.

Data byte received after General Call received, NACK transmitted.

STOP or repeated START condition received in SLAVE mode.

Slave address and Read bit received, ACK transmitted.

Arbitration lost in address as master, slave address and Read bit received,

ACK transmitted.

B8h

C0h

C8h

D0h

D8h

F8h

Data byte transmitted in SLAVE mode, ACK received.

Data byte transmitted in SLAVE mode, ACK not received.

Last byte transmitted in SLAVE mode, ACK received.

Second Address byte and Write bit transmitted, ACK received.

Second Address byte and Write bit transmitted, ACK not received.

No relevant status information, IFLG = 0.

2

If an illegal condition occurs on the I C bus, the bus error state is entered (status

code 00h). To recover from this state, the STP bit in the I2C_CTL register must be

2

set and the IFLG bit cleared. The I C then returns to an idle state. No STOP con-

2

dition is transmitted on the I C bus.

The STP and STA bits can be set to 1 at the same time to recover from the bus

error. The I C then sends a START condition.

Note:

2

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2

I C Clock Control Register

The I2C_CCR register is a Write Only register. The seven LSBs control the fre-

2

quency at which the I C bus is sampled and the frequency of the I C clock line

2

(SCL) when the I C is in MASTER mode. The Write Only I2C_CCR registers

share the same I/O addresses as the Read Only I2C_SR registers. See Table

130.

2

Table 130. I C Clock Control Registers

(I2C_CCR = 00CCh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: W = Read only.

W

Bit

Position

Value Description

7

0

Reserved.

2

[6:3]

M

0000– I C clock divider scalar value.

1111

2

[2:0]

N

000– I C clock divider exponent.

111

2

The I C clocks are derived from the system clock of the eZ80F91 device. The fre-

2

quency of this system clock is f

. The I C bus is sampled by the I C block at the

SCK

frequency f

supplied by the following equation:

SAMP

f

SCLK

f

=

SAMP

N

2

In MASTER mode, the I C clock output frequency on SCL (f

) is supplied by the

SCL

following equation:

f

SCLK

f

=

SCL

N

10 • (M + 1)(2)

The use of two separately-programmable dividers allows the MASTER mode out-

2

put frequency to be set independently of the frequency at which the I C bus is

sampled. This feature is particularly useful in multimaster systems because the

2

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2

frequency at which the I C bus is sampled must be at least 10 times the frequency

of the fastest master on the bus to ensure that START and STOP conditions are

always detected. By using two programmable clock divider stages, a high sam-

pling frequency can be ensured while allowing the MASTER mode output to be

set to a lower frequency.

Bus Clock Speed

2

The I C bus is defined for bus clock speeds up to 100kbps (400kbps in FAST

mode).

2

To ensure correct detection of START and STOP conditions on the bus, the I C

2

must sample the I C bus at least ten times faster than the bus clock speed of the

fastest master on the bus. The sampling frequency should therefore be at least

1MHz (4MHz in FAST mode) to guarantee correct operation with other bus mas-

ters.

2

The I C sampling frequency is determined by the frequency of the eZ80F91 sys-

tem clock and the value in the I2C_CCR bits 2 to 0. The bus clock speed gener-

2

ated by the I C in MASTER mode is determined by the frequency of the input

clock and the values in I2C_CCR[2:0] and I2C_CCR[6:3].

2

I C Software Reset Register

The I2C_SRR register is a Write Only register. Writing any value to this register

2

performs a software reset of the I C module. See Table 131.

2

Table 131. I C Software Reset Register

(I2C_SRR = 00CDh)

Bit

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

X

Reset

CPU Access

Note: W = Write Only.

W

Bit

Position

Value Description

00h– Writing any value to this register performs a software reset of

[7:0]

SRR

2

FFh

the I C module.

2

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Ethernet Media Access Controller

The Ethernet Media Access Controller (EMAC) is a full-function 10/100 Mbps

media access control module with a Media-Independent Interface (MII). This

EMAC and interface combination is called a EMACMII module. Figure 47 pre-

sents an illustration of the EMAC block.

MDIO

TxDMA

MDC

TxD

TxCLK

TxFIFO

TxER

TxEN

COL

CRS

MII Interface

RxD

RxCLK

RxDV

RxD

RxD/CTRL

RxER

RxFIFO

Accept

CTRL

RxDMA

Reject

Figure 47. EMAC Block Diagram

The EMACMII module consists of six submodules that represent the Transmit and

Receive portions of the Ethernet MAC, plus the EMAC sublayer module. In addi-

tion, there is a host interface module, a central clock and reset module, and an MII

management module. There are many different applications possible, including

network interface designs, Ethernet switching designs, and test equipment

designs.

The EMAC functions are contained in the Transmit and Receive modules. These

modules represent the core MAC. 802.3x flow control implemented by the EMAC

sublayer module.

The MII management module provides a two-wire control/status path to the MII

PHY. Read and Write communication to and from registers within the PHY is

accomplished via the host interface.

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MII PHY is a Physical Layer transceiver device; PHY does not refer to the

Note:

eZ80F91 system clock output pin, PHI.

The MII management module provides a two-wire control/status path to the MII .

Read and Write communication to and from registers within the PHY is accom-

plished via the host interface.

EMAC Functional Description

The EMAC block implements memory, arbiter, and transmit and receive direct

memory access functions, as described in this section.

Memory

EMAC memory is the shared Ethernet memory location of the Transmit and

Receive buffers. This memory is broken into two parts: the Tx buffer and the Rx

buffer. The Transmit Lower Boundary Pointer Register, EmacTLBP, is the register

that holds the starting address of the Tx buffer. The Boundary Pointer Register,

EmacBP, points to the start of the Rx buffer (end of Tx buffer + 1). The Receive

High Boundary Pointer Register, EmacRHBP, points to the end of the Rx buffer +

1. The Tx and Receive buffers are divided into packet buffers of either 256, 128,

64, or 32 bytes. These buffer sizes are selected by EmacBufSize register bits 7

and 6.

The EmacBlksLeft register contains the number of Receive packet buffers remain-

ing in the Rx buffer. This buffer can be used for software flow control. If the

Block_Level is nonzero (bits 5:0 of the EmacBufSize register), hardware flow con-

trol is enabled. If in Full Duplex Mode, the EMAC transmits a pause control frame

when the EmacBlksLeft register is less than the Block_Level. In Half Duplex

mode, the EMAC continually transmits a nibble pattern of hexadecimal 5’s to jam

the channel.

Four pointers are defined for reading and writing the Tx and Rx buffers. The

Transmit Write Pointer, TWP, is a software pointer that points to the next available

packet buffer. The TWP is reset to the value stored in EmacTLBP. The Transmit

Read Pointer, TRP, is a hardware pointer in the Transmit Direct Memory Access

Register, TxDMA, that contains the address of the next packet to be transmitted. It

is automatically reset to the EmacTLBP. The Receive Write Pointer, RWP, is a

hardware pointer in the Receive Direct Memory Access Register, RxDMA, which

contains the storage address of the incoming packet. The RWP pointer is auto-

matically initialized to the Boundary Pointer registers. The Receive Read Pointer,

RRP, is a software pointer to where the next packet should be read from. The

RRP pointer should be initialized to the Boundary Pointer registers. For the hard-

ware flow control to function properly, the software must update the hardware

RRP (EmacRrp) pointer whenever the software version is updated. The RxDMA

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uses RWP and the RRP to determine how many packet buffers remain in the Rx

buffer.

Arbiter

The arbiter controls access to EMAC memory. It prioritizes the requests for mem-

ory access between the CPU, the TxDMA, and the RxDMA. The TxDMA offers

two levels of priority: a high priority when the TxFIFO is less than half full and a

Low priority when the TxFIFO is more than half full. Similarly, the RxDMA offers

two levels of priority: a high priority when the RxFIFO is more than half full and a

Low priority when the RxFIFO is less than half full.

The arbiter determines resolution between the CPU, the RxDMA, and the TxDMA

requests to access EMAC memory. Post writing for CPU Writes results in zero-

wait-state write access timing when the CPU assumes the highest priority. CPU

Reads require a minimum of 1 wait state and can take more when the CPU does

not hold the highest priority. The CPU Read wait state is not a user-controllable

operation, because it is controlled by the arbiter. The RxDMA and TxDMA

requests are not allowed to occur back-to-back. Therefore, the maximum through-

put rate for the two Direct Memory Access (DMA) ports is 25 megabytes per sec-

ond each (one byte every 2 clocks) when the system clock is running at 50MHz.

The rate is reduced to 20 megabytes per second for a 40MHz system clock. The

arbiter uses the internal WAIT signal to add wait states to CPU access when

required. See Table 132.

Table 132. Arbiter Priority

Priority Device

Level

Serviced

Flags

0

1

2

3

4

RxDMA High RxFIFO > half full (FAF)

TxDMA High TxFIFO < half full (FAE)

®

eZ80 CPU

RxDMA Low

TxDMA Low

RxFIFO < half full (FAE)

TxFIFO > half full (FAF)

TxDMA

The TxDMA module moves the next packet to be transmitted from EMAC memory

into the TxFIFO. Whenever the polling timer expires, the TxDMA reads the High

status byte from the Tx descriptor table pointed to by the Transmit Read Pointer,

TRP. Polling continues until the High status Read reaches bit 7, when the

Emac_Owns ownership semaphore, bit 15 of the descriptor table (see Table 134)

is set to 1. The TxDMA then initializes the packet length counter with the size of

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the packet from descriptor table bytes 3 and 4. The TxDMA moves the data into

the TxFIFO until the packet length counter downcounts to zero. The TxDMA then

waits for Transmission Complete signal to be asserted to indicate that the packet

is sent and that the Transmit status from the EMAC is valid. The TxDMA updates

the descriptor table status and resets the ownership semaphore, bit 15. Finally,

the Tx_DONE_STAT bit of the EMAC Interrupt Status Register is set to 1, the

address field, DMA_Address, is updated from the descriptor table next pointer, NP

(see Figure 50). The High byte of the status is read to determine if the next packet

is ready to be transmitted.

While the TxDMA is filling the TxFIFO, it monitors two signals from the Transmit

FIFO State Machine (TxFifoSM) to detect error conditions and to determine if the

packet is to be retransmitted (TxDMA_Retry asserted) or the packet is aborted

(TxDMA_Abort asserted). If the packet is aborted, the TxDMA updates the

descriptor status and moves to the next packet. If the packet is to be retried, the

DMA_Address is reset to the start of the packet, the packet length counter is

reloaded from the descriptor table, bytes 3 and 4, and the packet is moved into

the TxFIFO again. When an abort or retry event occurs, the TxDMA asserts the

appropriate signal to reset the TxFIFO Read and Write pointers which clears out

any data that is in the FIFO. The TxFifoSM negates the TxDMA_Abort and/or

TxDMA_Retry signal(s) when the TxFCWP signal is High. This handshaking

maintains synchronization between the TxDMA and the TxFifoSM.

RxDMA

The RxDMA reads the data from the RxFIFO and stores it in the EMAC memory

Receive buffer. When the end of the packet is detected, the RxDMA reads the

next two bytes from the RxFIFO and writes them into the Rx descriptor status LSB

and MSB. The packet length counter is stored into the descriptor table packet

length field, the descriptor table next pointer is written into the Rx descriptor table

and finally the Rx_DONE_STAT bit in the EMAC Interrupt Status Register register

is set to 1.

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EMAC Interrupts

Eight different sources of interrupts from the EMAC are described in Table 133.

Table 133. EMAC Interrupts

Interrupt

Description

EMAC System Interrupts

Transmit State Machine Error

Bit 7 (TxFSMERR_STAT) of the EMAC Interrupt Status Register

(EMAC_ISTAT). A Transmit State Machine Error should never

occur. However, if this bit is set, the entire transmitter module

must be reset.

MIIMGT Done

Bit 6 (MGTDONE_STAT) of the Interrupt Status Register

(EMAC_ISTAT). This bit is set when communicating to the PHY

over the MII during a Read or Write operation.

Receive Overrun

Bit 2 (Rx_OVR_STAT) of the Interrupt Status Register

(EMAC_ISTAT). If this bit is set, all incoming packets are ignored

until this bit is cleared by software.

EMAC Transmitter Interrupts

Transmit Control Frame

Transmit Control Frame = Bit 1 (Tx_CF_STAT) of the Interrupt

Status Register (EMAC_ISTAT). Denotes when control frame

transmission is complete.

Transmit Done

Bit 0 (Tx_DONE_STAT) of the Interrupt Status Register

(EMAC_ISTAT). Denotes when packet transmission is complete.

EMAC Receiver Interrupts

Receive Control Frame

Bit 5 (Rx_CF_STAT) of the Interrupt Status Register

(EMAC_ISTAT). Denotes when control frame reception is

complete.

Receive Pause Control Frame

Receive Done

Bit 4 (Rx_PCF_STAT) of the Interrupt Status Register

(EMAC_ISTAT). Denotes when pause control frame reception is

complete.

Bit 3 (Rx_DONE_STAT) of the Interrupt Status Register

(EMAC_ISTAT). Denotes when control frame reception is

complete.

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EMAC Shared Memory Organization

Internal Ethernet SRAM shares memory with the CPU. This memory is divided

into the Transmit buffer and the Receive buffer by defining three registers, as

listed below.

•

Transmit Lower Boundary Pointer (TLBP)—this register points to the start of

the Transmit buffer in the internal Ethernet shared memory space

•

Boundary Pointer (BP)—this register points to the start of the Receive buffer

Receive High Boundary Pointer (RHBP)—this register points to the end of the

Receive buffer + 1

This internal Ethernet shared memory is depicted in Figure 48.

TLBP

Tx Buffer

BP

Rx Buffer

RHBP

Figure 48. internal Ethernet Shared Memory

The Transmit and Receive buffers are able to be subdivided into packet buffers of

32, 64, 128, or 256 bytes in size. The packet buffer size is set in bits 7 and 6 of the

EmacBufSize register. An Ethernet packet can accommodate multiple packet buff-

ers. At the start of each packet is a descriptor table that describes the packet.

Each actual Ethernet packet follows the descriptor table, as illustrated in

Figure 49.

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Offset

TWP

0000h

Descriptor

Table

0007h

Ethernet

Packet

Figure 49. Descriptor Table

The descriptor table contains three entries: the next pointer (NP), the packet size

(Pkt_Size) and the packet status (Stat), as illustrated in Figure 50.

Offset

TWP

0000h

0003h

NP

Pkt_Size

Stat

0005h

Figure 50. Descriptor Table Entries

NP is a 24-bit pointer to the start of the next packet. Pkt_Size contains the number

of bytes of data in the Ethernet packet, including the four CRC bytes, but does not

contain the seven descriptor table bytes. Stat contains the status of the packet.

Stat differs for Transmit and Receive packets. See Tables 134 and 135.

Table 134. Transmit Descriptor Status

Bit

15

14

13

Name

Description

®

TxOwner

TxAbort

TxBPA

0 = Host (eZ80 ) owns, 1 = EMAC owns.

1 = Packet aborted (not transmitted).

1 = Back pressure applied.

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Table 134. Transmit Descriptor Status

Bit

12

11

10

Name

Description

TxHuge

TxLOOR

TxLCError

1 = Packet size is very large (Pkt_Size > EmacMaxf).

1 = Type/Length field is out of range (larger than 1518 bytes).

1 = Type/Length field is not a Type field and it does not match the

actual data byte length of the Ethernet packet. The data byte length is

the number of bytes of data in the Ethernet packet between the Type/

Length field and the FCS.

9

TxCrcError

1 = The packet contains an invalid FCS (CRC). This flag is set when

CRCEN = 0 and the last 4 bytes of the packet are not the valid FCS.

8

7

TxPktDeferred

TxXsDfr

1 = Packet is deferred.

1 = Packet is excessively deferred. (> 6071 nibble times in 100BaseT

or 24,287 bit times in 10BaseT).

6

5

TxFifoUnderRun

TxLateCol

1 = TxFIFO experiences Underrun. Check the TxAbort bit to see if the

packet is aborted or retried.

1 = A late collision occurs. Collision is detected at a byte count >

EmacCfg2[5:0]. Collisions detected before the byte count reaches

EmacCfg2[5:0] are early collisions and retried.

4

TxMaxCol

1 = The maximum number of collisions occurs. #Collisions >

EmacCfg3[3:0]. These packets are aborted.

[3:0] TxNumberOfCollisions

This field contains the number of collisions that occur while

transmitting the packet.

Table 135. Receive Descriptor Status

Bit

15

14

13

12

Name

Description

RxOK

1 = Packet received intact.

1 = An odd number of nibbles is received.

1 = The CRC (FCS) is in error.

RxAlignError

RxCrcError

RxLongEvent

1 = A Long or Dropped Event occurs. A Long Event is when a packet

over 50,000 bit times occurs. A Dropped Packet can occur if the

minimum interpacket gap is not met, the preamble is not pure, and the

EmacCfg3[PUREP] bit is set, or if a preamble over 11 bytes in length

is detected and the EmacCfg3[LONGP] bit is set to 1.

11

10

RxPCF

RxCF

1 = The packet is a pause control frame.

1 = The packet is a control frame.

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Table 135. Receive Descriptor Status (Continued)

Bit

9

Name

Description

RxMcPkt

RxBcPkt

RxVLAN

RxUOpCode

1 = The packet contains a multicast address.

1 = The packet contains a broadcast address.

1 = The packet is a VLAN packet.

8

7

6

1 = An unsupported Op Code is indicated in the Op Code field of the

Ethernet packet.

5

4

RxLOOR

1 = The Type/Length field is out of range (larger than 1518 bytes).

RxLCError

1 = Type/Length field is not a Type field and it does not match the

actual data byte length of the Ethernet packet. The data byte length is

the number of bytes of data in the Ethernet packet between the Type/

Length field and the FCS.

3

2

RxCodeV

RxCEvent

1 = A code violation is detected. The PHY asserts Rx error (RxER).

1 = A carrier event is previously seen. This event is defined as Rx

error RxER = 1, receive data valid (RxDV) = 0 and receive data (RxD)

= Eh.

1

0

RxDvEvent

RxOVR

1 = A receive data (RxDV) event is previously seen. Indicates that the

last Receive event is not long enough to be a valid packet.

1 = A Receive Overrun occurs in this packet. An overrun occurs when

all of the EMAC Receive buffers are in use and the Receive FIFO is

full. The hardware ignores all incoming packets until the EmacIStat

Register [Rx_Ovr] bit is cleared by the software. There is no indication

as to how many packets are ignored.

EMAC and the System Clock

Effective Ethernet throughput in any given system is dependent upon factors such

as system clock speed, network protocol overhead, application complexity, and

network traffic conditions at any given moment. The following information provides

a general guideline about the effects of system clock speed on Ethernet opera-

tion.

The eZ80F91 MCU's EMAC block performs a synchronous function that is

designed to operate over a wide range of system clock frequencies. To under-

stand its maximum data transfer capabilities at certain system operating frequen-

cies, the user must first understand the internal data bus bandwidth that is

required under ideal conditions.

For 10BaseT Ethernet connectivity, the data rate is 10Mbits per second, which

equates to 1.25Mbytes per second. If the eZ80F91 MCU is operating in full duplex

mode over 10BaseT, the data rate for RX data and TX data is 1.25Mbytes per

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second. Because raw data transfers at this rate consume a certain amount of

CPU bandwidth, the CPU must support traffic from both directions as well as

operate at a minimum clock frequency of (1.25 + 1.25) * 2 = 5Mhz while transfer-

ring Ethernet packets to and from the physical layer.

Similarly, for 100BaseT Ethernet, the data rate is 100Mbits per second, which

equates to 12.5Mbytes per second. If the eZ80F91 MCU is operating in full duplex

mode over 100BaseT, the data rate for RX data and TX data is 12.5Mbytes per

second. Because raw data transfers at this rate consume a certain amount of

CPU bandwidth, the CPU must support traffic from both directions as well as

operate at a minimum clock frequency of (12.5 + 12.5) x 2 = 50Mhz while trans-

ferring Ethernet packets to and from the physical layer. Consequently, 50MHz is

®

the minimum system clock speed that the eZ80 CPU requires to sustain EMAC

®

data transfers while not also including any software overhead or additional eZ80

tasks.

The FIFO functionality of the EMAC operates at any frequency as long as the user

application avoids overrun and underrun errors via higher-level flow control.

Actual application requirements will dictate Ethernet modes of operation (full-

duplex, half-duplex, etc.). Because each user and application is different, it

becomes the user’s responsibility to control the data flow with these parameters.

Under ideal conditions, the system clock will operate somewhere between 5MHz

and 50MHz to handle the EMAC data rates.

EMAC Operation in HALT Modes

When the CPU is in HALT mode, the eZ80F91 device’s EMAC block cannot be

disabled as can other peripherals. Upon receipt of an Ethernet packet, a

maskable Receive interrupt is generated by the EMAC block, just as it would be in

a non-halt mode. Accordingly, the processor wakes up and continues with the

user-defined application.

EMAC Registers

After a system reset, all EMAC registers are set to their default values. Any Writes

to unused registers or register bits are ignored and reads return a value of 0. For

compatibility with future revisions, unused bits within a register should always be

written with a value of 0. Read/Write attributes, reset conditions, and bit descrip-

tions of all of the EMAC registers are provided in this section.

EMAC Test Register

The EMAC Test Register allows test functionality of the EMAC module. Available

test modes are defined for bits [6:0]. See Table 136.

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Table 136. EMAC Test Register

(EMAC_TEST = 0020h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R

R/W

Note: R/W = Read/Write, R = Read Only.

Bit

Position

Value

Description

7

0

1

0

1

0

1

Reserved.

6

FIFO test mode disabled—normal operation.

FIFO test mode enabled.

TEST_FIFO

5

Select the Receive FIFO when FIFO test mode is enabled.

Select the Transmit FIFO when FIFO test mode is enabled.

Normal operation.

TxRx_SEL

4

SSTC

Short Cut Slot Timer Counter. Slot time is shortened to

speed up simulation.

3

0

1

0

1

0

1

0

1

Normal operation.

SIMR

Simulation Reset.

2

Normal operation.

FRC_OVR_ERR

Force Overrun error in Receive FIFO.

Normal operation.

1

FRC_UND_ERR

Force Underrun error in Transmit FIFO.

Normal operation.

0

LPBK

EMAC Transmit interface is looped back into EMAC

Receive interface.

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EMAC Configuration Register 1

The EMAC Configuration Register 1 allows control of the padding, autodetection,

cyclic redundancy checking (CRC) control, full duplex, field length checking, max-

imum packet ignores, and proprietary header options. See Table 137.

Table 137. EMAC Configuration Register 1

(EMAC_CFG1 = 0021h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

7

0

No padding. Assume all frames presented to EMAC have

proper length.

PADEN

1

EMAC pads all short frames by adding zeroes to the end of

the data field. This bit is used in conjunction with ADPADN

and VLPAD.

6

0

1

Disable autodetection.

ADPADN

Enable frame detection by comparing the two octets following

the source address with 0x8100 (VLAN Protocol ID) and pad

accordingly. This bit is ignored if PADEN is cleared to 0.

5

0

1

Do not pad all short frames.

VLPAD

EMAC pads all short frames to 64 bytes and append a valid

CRC. This bit is ignored if PADEN is cleared to 0.

4

0

1

0

1

0

1

Do not append CRC.

CRCEN

Append CRC to every frame regardless of padding options.

Half-duplex mode. CSMA/CD is enabled.

Enable full duplex mode. CSMA/CD is disabled.

Ignore the length field within Transmit/Receive frames.

3

FULLD

2

FLCHK

Both Transmit and Receive frame lengths are compared to

the length/type field. If the length/type field represents a

length then the frame length check is performed.

1

0

1

Limit the Receive frame-size to the number of bytes specified

in the MAXF[15:0] field.

HUGEN

Allow unlimited sized frames to be received. Ignore the

MAXF[15:0] field.

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Bit

Position

Value

Description

0

1

No proprietary header. Normal operation.

DCRCC

Four bytes of proprietary header (ignored by CRC) exists on

the front of IEEE 802.3 frames.

Table 138 shows the results of different settings for bits [7:4} of EMAC Configura-

tion Register 1.

Table 138. CRC/PAD Features of EMAC Configuration Register

ADPADN VLPADN PADEN CRCEN Result

0

1

0

1

0

No pad or CRC appended.

CRC appended.

Pad to 60 bytes if necessary; append CRC (min. size =

64).

0

1

Pad to 60 bytes if necessary; append CRC (min. size =

64).

0

1

0

1

0

1

0

No pad or CRC appended.

CRC appended.

Pad to 64 bytes if necessary, append CRC (min. size =

68).

0

1

Pad to 64 bytes if necessary, append CRC (min. size =

68).

1

0

1

0

1

0

No pad or CRC appended.

CRC appended.

If VLAN not detected, pad to 60, add CRC.

If VLAN detected, pad to 64, add CRC.

1

0

1

If VLAN not detected, pad to 60, add CRC.

If VLAN detected, pad to 64, add CRC.

1

0

1

0

1

0

No pad or CRC appended.

CRC appended.

If VLAN not detected, pad to 60, add CRC.

If VLAN detected, pad to 64, add CRC.

1

If VLAN not detected, pad to 60, add CRC.

If VLAN detected, pad to 64, add CRC.

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EMAC Configuration Register 2

The EMAC Configuration Register 2 controls the behavior of the back pressure

and late collision data from the Descriptor table. See Table 139.

Table 139. EMAC Configuration Register 2

(EMAC_CFG2 = 0022h)

Bit

7

0

6

0

5

1

4

1

3

0

2

1

0

1

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

7

0

Use normal back-off algorithm prior to transmitting packet. No

back pressure applied.

BPNB

1

After incidentally causing a collision during back pressure, the

EMAC immediately (i.e., no back-off) retransmits the packet

without back-off, which reduces the chance of further

collisions and ensures that the Transmit packets are sent.

6

0

1

Enable exponential back-off.

NOBO

The EMAC immediately retransmits following a collision rather

than use the binary exponential backfill algorithm, as specified

in the IEEE 802.3 specification.

[5:0]

LCOL

00h–

3Fh

Sets the number of bytes after Start Frame Delimiter (SFD)

for which a late collision can occur. By default, all late

collisions are aborted.

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EMAC Configuration Register 3

The EMAC Configuration Register 3 controls preamble length and value, exces-

sive deferment, and the number of retransmission tries. See Table 140.

Table 140. EMAC Configuration Register 3

(EMAC_CFG3 = 0023h)

Bit

7

0

6

0

5

0

4

0

3

1

2

1

0

1

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

7

0

The EMAC allows any preamble length as per the IEEE 802.3

specification.

LONGP

1

The EMAC only allows Receive packets that contain

preamble fields less than 12 bytes in length.

6

0

1

No preamble error checking is performed.

PUREP

The EMAC verifies the content of the preamble to ensure that

it contains a value of 55h and that it is error-free. Packets

containing an errored preamble are discarded.

5

0

1

The EMAC aborts when the excessive deferral limit is

reached.

XSDFR

The EMAC defers to the carrier indefinitely as per the IEEE

802.3 specification.

4

0

1

Disable 10Mbps ENDEC mode.

Enable 10Mbps ENDEC mode.

BITMD

[3:0]

RETRY

0h–Fh A programmable field specifying the number of retransmission

attempts following a collision before aborting the packet due

to excessive collisions.

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EMAC Configuration Register 4

The EMAC Configuration Register 4 controls pause control frame behavior, back

pressure, and receive frame acceptance. See Table 141.

Table 141. EMAC Configuration Register 4

(EMAC_CFG4 = 0024h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R

R/W

Note: R = Read Only; R/W = Read/Write.

Bit

Position

Value

Description

7

0

1

Reserved.

6

Do not transmit a pause control frame.

TPCF

Transmit pause control frame (full duplex mode). TPCF

continually sends pause control frames until negated.

5

0

1

Disable back pressure.

THDF

EMAC asserts back pressure on the link. Back pressure

causes preamble to be transmitted, raising carrier sense (half

duplex mode).

4

0

1

Only accept frames that meet preset criteria (i.e. address,

CRC, length, etc.).

PARF

All frames are received regardless of address, CRC, length,

etc.

3

0

1

0

1

0

1

0

1

EMAC ignores received pause control frames.

EMAC acts upon pause control frames received.

PAUSE control frames are NOT allowed to be transmitted.

PAUSE control frames are allowed to be transmitted.

Do not force a pause condition.

RxFC

2

TxFC

1

TPAUSE

Force a pause condition while this bit is asserted.

Do not receive frames.

0

RxEN

Allow Receive frames to be received.

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EMAC Station Address Register

The EMAC Station Address register is used for two functions. In the address rec-

ognition logic for Receive frames, EMAC_STAD_0–EMAC_STAD_5 are matched

against the 6-byte Destination Address (DA) field of the Receive frame.

EMAC_STAD_0 is matched against the first byte of the Receive frame, and

EMAC_STAD_5 is matched against the sixth byte of the Receive frame. Bit 0 of

EMAC_STAD_0 (STAD[40]) is matched against the first bit (Unicast/Multicast bit)

of the first byte of the Receive frame. This bit ordering is used to logically map the

PE-MACMII station address, as exemplified below.

EMAC_STAD0[7:0] contains STAD[47:40]

•

EMAC_STAD5[7:0] contains STAD[7:0]

The second function of the EMAC Station Address registers is to provide the

Source Address (SA) field of Transmit Pause frames when these frames are

transmitted by the EMAC. EMAC_STAD_0 provides the first byte of the 6-byte SA

field and EMAC_STAD_5 provides the final byte of the SA field in order of trans-

mission. The LSB is the first byte sent out. The EMAC Station Address register is

detailed in Table 142.

Table 142. EMAC Station Address Register

(EMAC_STAD_0 = 0025h, EMAC_STAD_1 = 0026h, EMAC_STAD_2 = 0027h,

EMAC_STAD_3 = 0028h, EMAC_STAD_4 = 0029h, EMAC_STAD_5 = 002Ah)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

EMAC_STAD_0 Reset

EMAC_STAD_1 Reset

EMAC_STAD_2 Reset

EMAC_STAD_3 Reset

EMAC_STAD_4 Reset

EMAC_STAD_5 Reset

CPU Access

0

R/W

Note: R/W = Read/Write.

Bit

Position

Value

Description

[7:0]

00h–

This 48-bit station address comprises {EMAC_STAD_5,

EMAC_STAD_4, EMAC_STAD_3, EMAC_STAD_2,

EMAC_STAD_1, EMAC_STAD_0}.

EMAC_STAD_x FFh

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EMAC Transmit Pause Timer Value Register—Low and High Bytes

The Low and High bytes of the EMAC Transmit Pause Timer Value Register are

inserted into outgoing pause control frames. See Tables 143 and 144.

Table 143. EMAC Transmit Pause Timer Value Register—Low Byte

(EMAC_TPTV_L = 002Bh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

00h–

Description

[7:0]

The 16-bit value, {EMAC_TPTV_H, EMAC_TPTV_L}, is

inserted into outgoing pause control frames as the pause

timer value upon asserting TPCF.

EMAC_TPTV_L FFh

Table 144. EMAC Transmit Pause Timer Value Register—High Byte

(EMAC_TPTV_H = 002Ch)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

00h–

Description

[7:0]

The 16-bit value, {EMAC_TPTV_H, EMAC_TPTV_L}, is

inserted into outgoing pause control frames as the pause

timer value upon asserting TPCF.

EMAC_TPTV_H FFh

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EMAC Interpacket Gap

EMAC Interpacket Gap Overview

Interpacket gap (IPG) is measured between the last nibble of the frame check

sequence (FCS) and the first nibble of the preamble of the next packet. Three reg-

isters are available to fine tune the IPG, the EMAC_IPGT, EMAC_IPGR1, and the

EMAC_IPGR2. The first register EMAC_IPGT determines the back-to-back

Transmit IPG. The other two registers determine the non-back-to-back IPG in two

parts. Table 145 shows the values for the EMAC_IPGT and the corresponding

IPGs for both full-duplex and half-duplex modes.

Table 145. EMAC_IPGT Back-to-Back Settings for Full/Half Duplex Modes*

MII, RMII/SMII, PMD

(100Mbps)

MII, RMII/SMII

(10Mbps)

ENDEC Mode

(10Mbps)

Clock Period = 40 nsec

IPGT[6:0]

Clock Period = 400 nsec

IPGT[6:0]

Clock Period = 100 nsec

IPGT[6:0]

Half

Full

Interpacket

Half

Full

Interpacket

Half

Full

Interpacket

Duplex Duplex

Gap

Duplex Duplex

Gap

1.2µs

4.4µs

6.0µs

7.5µs

9.6µs

14.0µs

Duplex Duplex

Gap

1.9µs

2.7µs

3.5µs

6.7µs

9.6µs

13.0µs

0Dh

0Bh

0Ch

10h

0.12µs

0.44µs

0.60µs

0.76µs

0.96µs

1.40µs

00h

08h

0Ch

10h

18h

20h

40h

12h

15h

20h

12h

15h

20h

5Ah

5Dh

20h

Note: *The IEEE 802.3, 802.3(u) minimum values are shaded.

The equations for back-to-back Transmit IPG are determined by the following:

Full Duplex Mode (3 clocks + IPGT clocks) * clock period = IPG

Half Duplex Mode (6 clocks + IPGT clocks) * clock period = IPG

Table 146 shows the IPGR2 settings for the non-back-to-back packets.

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Table 146. EMAC_IPGT Non-Back-to-Back Settings for Full/Half Duplex Modes*

MII, RMII/SMII, PMD

(100Mbps)

MII, RMII/SMII

(10Mbps)

ENDEC Mode

(10Mbps)

Clock Period = 40 nsec

Clock Period = 400 nsec Clock Period = 100 nsec

IPGR2[6:0] Interpacket IPGR2[6:0] Interpacket IPGR2[6:0] Interpacket

Gap

2.4µs

8.8µs

9.6µs

15.2µs

28.0µs

53.2µs

Gap

0.6µs

2.2µs

3.8µs

7.0µs

9.6µs

13.3µs

00h

10h

12h

20h

40h

7Fh

0.24µs

0.88µs

0.96µs

1.52µs

2.80µs

5.32µs

00h

10h

12h

20h

40h

7Fh

00h

10h

20h

40h

5Ah

7Fh

Note: *The IEEE 802.3, 802.3(u) minimum values are shaded.

A non-back-to-back Transmit IPG is determined by the following formula:

(6 clocks + IPGR2 clocks) * clock period = IPG

The difference in values between Tables 145 and 146 is due to the asynchronous

nature of the Carrier Sense (CRS). The CRS must undergo a 2-clock synchroni-

zation before the internal Tx state machine can detect it. This synchronization

equates to a 6-clock intrinsic delay between packets instead of the 3-clock intrin-

sic delay in the back-to-back packet mode. More information covering this topic

can be found in the IEEE 802.3/4.2.3.2.1 Carrier Deference section.

EMAC Interpacket Gap Register

The EMAC Interpacket Gap is a programmable field representing the interpacket

gap (IPG) between back-to-back packets. It is the IPG parameter used in full-

duplex and half-duplex modes between back-to-back packets. Set this field to the

appropriate number of IPG octets. The default setting of 15hrepresents the mini-

mum IPG of 0.96µs (at 100Mbps) or 9.6 µs (at 10Mbps). See Table 147.

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Table 147. EMAC Interpacket Gap Register

(EMAC_IPGT = 002Dh)

Bit

7

0

6

0

5

0

4

1

3

0

2

1

0

1

Reset

CPU Access

R

R/W

Note: R = Read Only; R/W = Read/Write

Bit

Position

Value

Description

7

0

Reserved.

[6:0]

IPGT

00h–

7Fh

The number of octets of IPG.

EMAC Non-Back-To-Back IPG Register—Part 1

Part 1 of the EMAC Non-Back-To-Back IPG Register is a programmable field rep-

resenting the optional carrier sense window referenced in IEEE 802.3/4.2.3.2.1

Carrier Deference. If a carrier is detected during the timing of IPGR1, the EMAC

defers to the carrier. If, however, the carrier becomes active after IPGR1, the

EMAC continues timing for IPGR2 and transmits, knowingly causing a collision.

This collision acts to ensure fair access to the medium. Its range of values is 00h

to IPGR2. See Table 148. The default setting of 0Ch represents the Carrier Sense

Window Referencing depicted tin IEEE 802.3, Section 4.2.3.2.1.

Table 148. EMAC Non-Back-To-Back IPG Register—Part 1

(EMAC_IPGR1 = 002Eh)

Bit

7

0

6

0

5

0

4

0

3

1

2

1

0

Reset

CPU Access

Note: R/W = Read/Write

R/W

Bit

Position

Value

Description

7

0

Reserved.

[6:0]

IPGR 1

00h–

7Fh

This is a programmable field representing the optional carrier

sense window referenced in IEEE 802.3/4.2.3.2.1 Carrier

Deference.

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EMAC Non-Back-To-Back IPG Register—Part 2

Part 2 of the EMAC Non-Back-To-Back IPG Register is a programmable field rep-

resenting the non-back-to-back interpacket gap. Its default is 12h, which repre-

sents the minimum IPG of 0.96µs at 100Mbps or 9.6µs at 10Mbps. See Table

149.

Table 149. EMAC Non-Back-To-Back IPG Register—Part 2

(EMAC_IPGR2 = 002Fh)

Bit

7

0

6

0

5

0

4

1

3

0

2

0

1

0

Reset

CPU Access

R

R/W

Note: R = Read Only; R/W = Read/Write

Bit

Position

Value

Description

7

0

Reserved.

[6:0]

IPGR2

00h–

7Fh

This is a programmable field representing the non-back-to-

back interpacket gap.

EMAC Maximum Frame Length Register—Low and High Bytes

The 16-bit field resets to 0600h, which represents a maximum Receive frame of

1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged

frame adds four octets for a total of 1522 octets. If a shorter maximum length

restriction is more appropriate, program this field. See Tables 150 and 151.

If a proprietary header is allowed, this field should be adjusted accordingly. For

example, if 12-byte headers are prepended to frames, MAXF should be set to

1524 octets to allow the maximum VLAN tagged frame plus the 12-byte header.

Note:

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Table 150. EMAC Maximum Frame Length Register—Low Byte

(EMAC_MAXF_L = 0030h

Bit

7

6

0

5

0

4

0

3

0

2

0

1

0

Reset

0

CPU Access

R/W

Note: R/W = Read/Write.

Bit

Position

Value

00h–

Description

[7:0]

These bits represent the Low byte of the 2-byte MAXF

value, {EMAC_MAXF_H, EMAC_MAXF_L}. Bit 7 is bit 7 of

the 16-bit value. Bit 0 is bit 0 (lsb) of the 16-bit value.

EMAC_MAXF_L FFh

Table 151. EMAC Maximum Frame Length Register—High Byte

(EMAC_MAXF_H = 0031h)

Bit

7

0

6

0

5

0

4

0

3

0

2

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

00h–

Description

[7:0]

These bits represent the High byte of the 2-byte MAXF

value, {EMAC_MAXF_H, EMAC_MAXF_L}. Bit 7 is bit 15

(msb) of the 16-bit value. Bit 0 is bit 8 of the 16-bit value.

EMAC_MAXF_H FFh

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263

EMAC Address Filter Register

The EMAC Address Filter Register functions as a filter to control promiscuous

mode, and multicast and broadcast messaging. See Table 152.

Table 152. EMAC Address Filter Register

(EMAC_AFR = 0032h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R

R/W

Note: R = Read Only; R/W = Read/Write.

Bit

Position

Value

0h

Description

[7:4]

Reserved.

3

1

Enable Promiscuous Mode. Receive all incoming packets

regardless of station address. Disables station address

filtering.

PROM

0

1

Disable Promiscuous Mode.

2

MC

Accept any multicast message. A multicast packet is

determined by the first bit in the destination address. If the first

LSB is a 1, it is a group address and is globally or locally

administered depending on the 2nd bit. See IEEE 802.3/3.2.3

for more information.

0

1

Do not accept multicast messages of any type.

1

Accept only qualified multicast (QMC) messages as

determined by the hash table.

QMC

0

1

Do not accept qualified multicast messages.

0

BC

Accept broadcast messages. Broadcast messages have the

destination address set to FFFFFFFFFFFFh.

0

Do not accept broadcast messages.

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264

EMAC Hash Table Register

The EMAC Hash Table Register represents the 8x8 hash table matrix. This table

is used as an option to select between different multicast addresses. If a multicast

address is received, the first 6 bits of the CRC are decoded and added to a table

that points to a single bit within the hash table matrix. If the selected bit = 1, the

multicast packet is accepted. If the bit = 0, the multicast packet is rejected. See

Table 153.

Table 153. EMAC Hash Table Register

(EMAC_HTBL_0 = 0033h, EMAC_HTBL_1 = 0034h, EMAC_HTBL_2 = 0035h,

EMAC_HTBL_3 = 0036h, EMAC_HTBL_4 = 0037h, EMAC_HTBL_5 = 0038h,

EMAC_HTBL_6 = 0039h, EMAC_HTBL_7 = 003Ah)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

EMAC_HTBL_0 Reset

EMAC_HTBL_1 Reset

EMAC_HTBL_2 Reset

EMAC_HTBL_3 Reset

EMAC_HTBL_4 Reset

EMAC_HTBL_5 Reset

EMAC_HTBL_6 Reset

EMAC_HTBL_7 Reset

CPU Access

0

R/W

Note: R/W = Read/Write

Bit

Position

Value

Description

[7:0]

00h–

This field is the hash table. The 64-bit hash table is

{EMAC_HTBL_7, EMAC_HTBL_6, EMAC_HTBL_5,

EMAC_HTBL_4, EMAC_HTBL_3, EMAC_HTBL_2,

EMAC_HTBL_1, EMAC_HTBL_0}.

EMAC_HTBL_x FFh

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265

EMAC MII Management Register

The EMAC MII Management Register is used to control the external PHY

attached to the MII. See Table 154.

Table 154. EMAC MII Management Register

(EMAC_MIIMGT = 003Bh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

7

1

Rising edge causes the CTLD control data to be transmitted

to external PHY if MII is not busy. This bit is self clearing.

LCTLD

0

1

No operation.

6

Rising edge causes status to be read from external PHY via

PRSD[15:0] bus if MII is not busy. This bit is self clearing.

RSTAT

0

1

No operation.

6

Scan PHY address increments upon SCAN cycle. The SCAN

bit must also be set for the PHY address to increment after

each scan. The scanning starts at the EmacFiad and

increments up to 1fh. It then rolls back to the EmacFiad

address.

SCINC

0

1

Normal operation.

5

Perform continuous Read cycles via MII management. While

in scan mode, the EmacIStat[MGTDONE] bit is set when the

current PHY Read has completed. At this time, the EmacPsrd

register holds the Read data and the EmacMIIStat[4:0] holds

the address of the PHY for which the EmacPrsd data pertains.

SCAN

0

1

0

Normal operation.

4

Suppress MDO preamble.

Normal preamble.

SPRE

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Bit

Position

Value

Description

[2:0]

Programmable divisor that produces MDC from SCLK.

CLKS

000

001

010

011

100

101

110

111

MDC = SCLK ÷ 4.

MDC = SCLK ÷ 6.

MDC = SCLK ÷ 8.

MDC = SCLK ÷ 10.

MDC = SCLK ÷ 14.

MDC = SCLK ÷ 20.

MDC = SCLK ÷ 28.

EMAC PHY Configuration Data Register—Low Byte

The Low Byte of the EMAC PHY Configuration Data Register represents the con-

figuration data written to the external PHY. See Table 155.

Table 155. EMAC PHY Configuration Data Register—Low Byte

(EMAC_CTLD_L = 003Ch)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

00h–

Description

[7:0]

These bits represent the Low byte of the 2-byte PHY

configuration data value, {EMAC_CTLD_H,

EMAC_CTLD_L FFh

EMAC_CTLD_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is bit

0 (lsb) of the 16-bit value.

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EMAC PHY Configuration Data Register—High Byte

The High Byte of the EMAC PHY Configuration Data Register represents the con-

figuration data written to the external PHY. See Table 156.

Table 156. EMAC PHY Configuration Data Register—High Byte

(EMAC_CTLD_H = 003Dh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

00h–

Description

[7:0]

These bits represent the High byte of the 2-byte PHY

configuration data value, {EMAC_CTLD_H,

EMAC_CTLD_H FFh

EMAC_CTLD_L}. Bit 7 is bit 15 (msb) of the 16-bit value.

Bit 0 is bit 8 of the 16-bit value.

EMAC PHY Address Register

The EMAC PHY Address Register allows access to the external PHY registers.

See Table 157.

Table 157. EMAC PHY Address Register

(EMAC_RGAD = 003Eh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R

R/W

Note: R = Read Only; R/W = Read/Write.

Bit

Position

Value

Description

[7:5]

000

Reserved.

[4:0]

RGAD

00h–

1Fh

Programmable 5-bit value which selects address within the

selected external PHY.

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268

EMAC PHY Unit Select Address Register

The EMAC PHY Unit Select Address Register allows the selection of multiple con-

nected external PHY devices. See Table 158.

Table 158. EMAC PHY Unit Select Address Register

(EMAC_FIAD = 003Fh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R

R/W

Note: R = Read Only; R/W = Read/Write.

Bit

Position

Value

Description

[7:5]

000

Reserved.

[4:0]

FIAD

00h–

1Fh

Programmable 5-bit value that selects an external PHY.

EMAC Transmit Polling Timer Register

This register sets the Transmit Polling Period in increments of TPTMR =

SYSCLK ÷ 256. Whenever this register is written, the status of the Transmit Buffer

Descriptor is checked to determine if the EMAC owns the Transmit buffer. It then

rechecks this status every TPTMR (calculated by TPTMR * EMAC_PTMR[7:0]).

The Transmit Polling Timer is disabled if this register is set to 00h(which also dis-

ables the transmitting of packets). If a transmission is in progress when

EMAC_PTMR is set to 00h, the transmission will complete. See Table 159.

Table 159. EMAC Transmit Polling Timer Register

(EMAC_PTMR = 0040h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

The Transmit polling period.

[7:0]

00h–

EMAC_PTMR FFh

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269

EMAC Reset Control Register

The bit values in the EMAC Reset Control Register are not self-clearing bits. The

user is responsible for controlling their state. See Table 160.

Table 160. EMAC Reset Control Register

(EMAC_RST = 0041h)

Bit

7

0

6

0

5

1

4

0

3

0

2

0

1

0

Reset

CPU Access

R

R/W

Note: R = Read Only; R/W = Read/Write.

Bit

Position

Value

00

Description

[7:6]

Reserved.

5

1

Software Reset Active—resets Receive, Transmit, EMAC

Control and EMAC MII_MGT functions.

SRST

0

1

0

1

0

1

0

1

0

1

0

Normal operation.

4

Reset Transmit function.

Normal operation.

HRTFN

3

Reset Receive function.

Normal operation.

HRRFN

2

Reset EMAC Transmit Control function.

Normal operation.

HRTMC

1

Reset EMAC Receive Control function.

Normal operation.

HRRMC

0

Reset EMAC Management function.

Normal operation.

HRMGT

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EMAC Transmit Lower Boundary Pointer Register—Low and High Bytes

The EMAC Transmit Lower Boundary Pointer is set to the start of the Transmit

buffer in EMAC shared memory. See Tables 161 and 162.

Table 161. EMAC Transmit Lower Boundary Pointer Register—Low Byte

(EMAC_TLBP_L = 0042h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

00h–

Description

[7:0]

These bits represent the Low byte of the 2-byte Transmit

Lower Boundary Pointer value, {EMAC_TLBP_H,

EMAC_TLBP_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is bit

0 (lsb) of the 16-bit value.

EMAC_TLBP_L FFh

Table 162. EMAC Transmit Lower Boundary Pointer Register—High Byte

(EMAC_TLBP_H = 0043h)*

Bit

7

1

6

1

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R

R/W

Bit

Position

Value

00h–

Description

[7:0]

These bits represent the High byte of the 2-byte Transmit

Lower Boundary Pointer value, {EMAC_TLBP_H,

EMAC_TLBP_L}. Bit 7 is bit 15 (msb) of the 16-bit value.

Bit 0 is bit 8 of the 16-bit value.

EMAC_TLBP_H FFh

Note: *Bits 7:5 are not used by the EMAC; these bits return 000.

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EMAC Boundary Pointer Register—Low and High Bytes

The Boundary Pointer is set to the start of the Receive buffer (end of Transmit

buffer +1) in EMAC shared memory. This pointer is 24 bits and determined by

{RAM_ADDR_U, EMAC_BP_H, EMAC_BP_L}. The upper 3 bits of the

EMAC_BP_H register are hard-wired inside the eZ80F91 device to locate the

base of EMAC shared memory. The last 5 bits of the EMAC_BP_L register value

are hard-wired to keep the addressing aligned to a 32-byte boundary. See

Tables 163 and 164.

Table 163. EMAC Boundary Pointer Register—Low Byte

(EMAC_BP_L = 0044h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

R

Note: R = Read Only, R/W = Read/Write.

Bit

Position

Value

Description

[7:0]

00h–

These bits represent the Low byte of the 3-byte EMAC

Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,

EMAC_BP_L FFh

EMAC_BP_L}. Bit 7 is bit 7 of the 24-bit value. Bit 0 is bit 0 of

the 24-bit value.

Table 164. EMAC Boundary Pointer Register—High Byte

(EMAC_BP_H = 0045h)

Bit

15:13

12:8

0

Reset

1

0

CPU Access

R

R/W

Note: R = Read Only, R/W = Read/Write.

Bit

Position

Value

Description

[7:0]

00h–

These bits represent the High byte of the 3-byte EMAC

Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,

EMAC_BP_H FFh

EMAC_BP_L}. Bit 7 is bit 15 of the 24-bit value. Bit 0 is bit 8 of

the 24-bit value.

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EMAC Boundary Pointer Register—Upper Byte

The EMAC Boundary Pointer Register maps directly to the RAM_ADDR_U regis-

ter within the eZ80F91 device. This register value is Read Only. See Table 165.

Table 165. EMAC Boundary Pointer Register—Upper Byte

(EMAC_BP_U = 0046h)

Bit

7

1

6

1

5

1

4

1

3

1

2

1

0

1

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value

00h–

Description

[7:0]

These bits represent the upper byte of the 3-byte EMAC

Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,

EMAC_BP_U FFh

EMAC_BP_L}. Bit 7 is bit 23 of the 24-bit value. Bit 0 is bit 16

of the 24-bit value.

EMAC Receive High Boundary Pointer Register—Low and High Bytes

The Receive High Boundary Pointer Register should be set to the end of the

Receive buffer +1 in EMAC shared memory. This RHBP uses the same

RAM_ADDR_U as the EMAC_BP_U pointer above. See Tables 166 and 167.

Table 166. EMAC Receive High Boundary Pointer Register—Low Byte

(EMAC_RHBP_L = 0047h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

R

Note: R = Read Only, R/W = Read/Write

Bit

Position

Value

Description

These bits represent the Low byte of the 2-byte EMAC

[7:0]

00h–

EMAC_RHBP_L E0h

Receive High Boundary Pointer value, {EMAC_RHBP_H,

EMAC_RHBP_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is

bit 0 (lsb) of the 16-bit value.

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Table 167. EMAC Receive High Boundary Pointer Register—High Byte

(EMAC_RHBP_H = 0048h)

Bit

7

1

6

1

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R

R/W

Note: R = Read Only, R/W = Read/Write

Bit

Position

Value

Description

[7:0]

00h–

These bits represent the High byte of the 2-byte EMAC

Receive High Boundary Pointer value, {EMAC_RHBP_H,

EMAC_RHBP_L}. Bit 7 is bit 15 (msb) of the 16-bit value.

Bit 0 is bit 8 of the 16-bit value.

EMAC_RHBP_H FFh

Note: *Bits 7:5 are not used by the EMAC; these bits return 000.

EMAC Receive Read Pointer Register—Low and High Bytes

The Receive Read Pointer Register should be initialized to the EMAC_BP value

(start of the Receive buffer). This register points to where the next Receive packet

is read from. The EMAC_BP[12:5] is loaded into this register whenever the

EMAC_RST [(HRRFN) is set to 1. The RxDMA block uses the Emac_Rrp[12:5] to

compare to EmacRwp[12:5] for determining how many buffers remain. The result

equates to the EmacBlksLeft register. See Tables 168 and 169.

Table 168. EMAC Receive Read Pointer Register—Low Byte

(EMAC_RRP_L = 0049h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

R

Note: R = Read Only, R/W = Read/Write

Bit

Position

Value

Description

[7:0]

EMAC_RRP_L

00h–

FFh

These bits represent the Low byte of the 2-byte EMAC

Receive Read Pointer value, {EMAC_RRP_H,

EMAC_RRP_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is bit

0 (lsb) of the 16-bit value.

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Table 169. EMAC Receive Read Pointer Register—High Byte

(EMAC_RRP_H = 004Ah)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R

R/W

Note: R = Read Only, R/W = Read/Write

Bit

Position

Value

Description

[7:0]

00h–

These bits represent the High byte of the 2-byte EMAC

Receive Read Pointer value, {EMAC_RRP_H,

EMAC_RRP_L}. Bit 7 is bit 15 (msb) of the 16-bit value. Bit 0

is bit 8 of the 16-bit value.

EMAC_RRP_ FFh

H

EMAC Buffer Size Register

The lower six bits of this register set the level at which the EMAC either transmits

a pause control frame or jams the Ethernet bus, depending on the mode selected.

When these bits each contain a zero, this feature is disabled.

In Full Duplex Mode, a Pause Control Frame is transmitted as a one-shot opera-

tion. The software must free up a number of Rx buffers so that the number of buff-

ers remaining, EmacBlksLeft, is greater than TCPF_LEV.

In Half Duplex Mode, the EMAC jams the Ethernet by sending a continuous

stream of hexadecimal 5s (5fh). When the software frees up the Rx buffers and

the number of buffers remaining, EmacBlksLeft, is greater than TCPF_LEV, the

EMAC stops jamming.

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Table 170. EMAC Buffer Size Register

(EMAC_BUFSZ = 004Bh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

00

Description

[7:6]

Set EMAC Rx/Tx buffer size to 256 bytes.

Set EMAC Rx/Tx buffer size to 128 bytes.

Set EMAC Rx/Tx buffer size to 64 bytes.

Set EMAC Rx/Tx buffer size to 32 bytes.

Transmit Pause Control Frame level.*

BUFSZ

01

10

11

[5:0]

TPCF_LEV

00h–

3Fh

Note: *00h disables the hardware-generated Transmit Pause Control Frame.

EMAC Interrupt Enable Register

Enabling the Receive Overrun interrupt allows software to detect an overrun con-

dition as soon as it occurs. If this interrupt is not set, then an overrun cannot be

detected until the software processes the Receive packet with the overrun and

checks the Receive status in the Rx descriptor table. Because the receiver is dis-

abled by an overrun error until the Rx_OVR bit is cleared in the EMAC_ISTAT reg-

ister, this packet is the final packet in the Receive buffer. To reenable the receiver

before all of the Receive packets are processed and the Receive buffer is empty,

software can enable this interrupt to detect the overrun condition early. As it pro-

cesses the Receive packets, it can reenable the receiver when the number of free

buffers is greater than the number of minimum buffers. See Table 171.

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Table 171. EMAC Interrupt Enable Register

(EMAC_IEN = 004Ch)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

7

1

Enable Transmit State Machine Error Interrupt (system

interrupt).

TxFSMERR

0

Disable Transmit State Machine Error Interrupt (system

interrupt).

6

1

0

1

0

1

Enable MII Mgmt. Done Interrupt (system Interrupt).

Disable MII Mgmt. Done Interrupt (system Interrupt).

MGTDONE

5

Enable Receive Control Frame Interrupt (Receive interrupt).

Disable Receive Control Frame Interrupt (Receive interrupt).

Rx_CF

4

Enable Receive Pause Control Frame interrupt (Receive

interrupt).

Rx_PCF

0

Disable Receive Pause Control Frame interrupt (Receive

interrupt).

3

1

0

1

0

1

0

1

0

Enable Receive Done interrupt (Receive interrupt).

Disable Receive Done interrupt (Receive interrupt).

Enable Receive Overrun interrupt (System interrupt).

Disable Receive Overrun interrupt (System interrupt).

Enable Transmit Control Frame Interrupt (Transmit interrupt).

Disable Transmit Control Frame Interrupt (Transmit interrupt).

Enable Transmit Done interrupt (Transmit interrupt).

Disable Transmit Done Interrupt (Transmit interrupt).

Rx_DONE

2

Rx_OVR

1

Tx_CF

0

Tx_DONE

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Product Specification

277

EMAC Interrupt Status Register

When a Receive overrun occurs, all incoming packets are ignored until the

Rx_OVR_STAT status bit is cleared by software. Consequently, software controls

when the receiver can be reenabled after an overrun. Enable the Rx_OVR inter-

rupt to detect overrun conditions when they occur. Clear this condition when the

Rx buffers are freed to avoid additional overrun errors. See Table 172.

Status bits are not self-clearing. Each status bit is cleared by writing a 1 into the

selected bit.

Note:

Table 172. EMAC Interrupt Status Register

(EMAC_ISTAT = 004Dh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

Description

7

1

An internal error occurs in the EMAC Transmit path. The

Transmit path must be reset to reset this error condition.

TxFSMERR_STAT

0

1

Normal operation—no Transmit state machine errors.

6

The MII Mgmt. interrupt has completed a Read (RSTAT

or SCAN) or a Write (LDCTLD) access to the PHY.

MGTDONE_STAT

0

1

The MII Mgmt. interrupt does not occur.

5

Receive Control Frame interrupt (Receive Interrupt)

occurs.

Rx_CF_STAT

0

1

Receive Control Frame interrupt does not occur.

4

Receive Pause Control Frame interrupt (Receive

Interrupt) occurs.

Rx_PCF_STAT

0

Disable Receive Pause Control Frame interrupt

(Receive Interrupt) does not occur.

3

1

0

Receive Done interrupt (Receive Interrupt) occurs.

Rx_DONE_STAT

Disable Receive Done interrupt (Receive Interrupt) does

not occur.

2

1

0

Receive Overrun interrupt (System Interrupt) occurs.

Rx_OVR_STAT

Receive Overrun interrupt (System Interrupt) does not

occur.

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Bit

Position

Value

Description

1

Transmit Control Frame Interrupt (Transmit Interrupt)

occurs.

Tx_CF_STAT

0

Transmit Control Frame Interrupt (Transmit Interrupt)

does not occur.

0

1

0

Transmit Done interrupt (Transmit Interrupt) occurs.

Tx_DONE_STAT

Transmit Done interrupt (Transmit Interrupt) does not

occur.

EMAC PHY Read Status Data Register—Low and High Bytes

The PHY MII Management Data Register is where the data Read from the PHY is

stored. See Tables 173 and 174.

Table 173. EMAC PHY Read Status Data Register—Low Byte

(EMAC_PRSD_L = 004Eh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value

00h–

Description

[7:0]

These bits represent the Low byte of the 2-byte EMAC

PHY Read Status Data value, {EMAC_PRSD_H,

EMAC_PRSD_L FFh

EMAC_PRSD_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is

bit 0 (lsb) of the 16-bit value.

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Table 174. EMAC PHY Read Status Data Register—High Byte

(EMAC_PRSD_H = 004Fh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value

00h–

Description

[7:0]

These bits represent the High byte of the 2-byte EMAC

PHY Read Status Data value, {EMAC_PRSD_H,

EMAC_PRSD_L}. Bit 7 is bit 15 (msb) of the 16-bit value.

Bit 0 is bit 8 of the 16-bit value.

EMAC_PRSD_H FFh

EMAC MII Status Register

The EMAC MII Status Register is used to determine the current state of the exter-

nal PHY device. See Table 175.

Table 175. EMAC MII Status Register

(EMAC_MIISTAT = 0050h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value

Description

7

1

MII management operation in progress—Busy. This status bit

goes busy whenever the LCTLD (PHY Write) or the RSTAT

(PHY Read) is set in the EMAC_MIIMGT register. It is

negated when the Write or Read operation to the PHY has

completed. In SCAN mode, the BUSY will be asserted until

the SCAN is disabled. Use the EmacIStat[MGTDONE]

interrupt status bit to determine when the data is valid.

BUSY

0

1

0

Not Busy.

6

Local copy of PHY Link fail bit.

PHY Link OK.

MIILF

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5

1

0

MII Scan result is not valid Emac_PRSD is invalid

NVALID

Emac_PRSD is valid.

[4:0]

RDADR

00h–

1Fh

Denotes PHY addressed in current scan cycle.

EMAC Receive Write Pointer Register—Low Byte

The Read Only Receive-Write-Pointer register reports the current RxDMA

Receive Write pointer. This pointer gets initialized to EmacTLBP whenever

Emac_RST bits SRST or HRRTN are set. Because the size of the packet is lim-

ited to a minimum of 32 bytes, the last five bits are always zero. See Tables 176

and 177.

Table 176. EMAC Receive Write Pointer Register—Low Byte

(EMAC_RWP_L = 0051h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value

00h–

Description

These bits represent the Low byte of the 2-byte EMAC

[7:0]

EMAC_RWP_L E0h

RxDMA Receive Write Pointer value, {EMAC_RWP_H,

EMAC_RWP_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is bit

0 (lsb) of the 16-bit value.

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EMAC Receive Write Pointer Register—High Byte

Because of the size of the EMAC’s 8KB SRAM, the upper three bits of the EMAC

Receive Write Pointer Register are always zero.

Table 177. EMAC Receive Write Pointer Register—High Byte

(EMAC_RWP_H = 0052h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value

00h–

Description

[7:0]

These bits represent the High byte of the 2-byte EMAC

RxDMA Receive Write Pointer value, {EMAC_RWP_H,

EMAC_RWP_L}. Bit 7 is bit 15 (msb) of the 16-bit value. Bit

0 is bit 8 of the 16-bit value.

EMAC_RWP_H 1Fh

EMAC Transmit Read Pointer Register—Low Byte

The Low byte of the Transmit Read Pointer register reports the current TxDMA

Transmit Read pointer.This pointer is initialized to EmacTLBP whenever

Emac_RST bits SRST or HRRTN are set. Because the size of the packet is lim-

ited to a minimum of 32 bytes, the last five bits are always zero. See Table 178.

Table 178. EMAC Transmit Read Pointer Register—Low Byte

(EMAC_TRP_L = 0053h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value

00h–

Description

These bits represent the Low byte of the 2-byte EMAC

[7:0]

EMAC_TRP_L E0h

TxDMA Transmit Read Pointer value, {EMAC_TRP_H,

EMAC_TRP_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is bit 0

(lsb) of the 16-bit value.

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EMAC Transmit Read Pointer Register—High Byte

Because of the size of the EMAC’s 8KB SRAM, the upper three bits of the EMAC

Transmit Read Pointer Register are always zero. See Table 179.

Table 179. EMAC Transmit Read Pointer Register—High Byte

(EMAC_TRP_H = 0054h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R/W = Read/Write.

RO

Bit

Position

Value

Description

[7:0]

EMAC_TRP_H

00h–

1Fh

These bits represent the High byte of the 2-byte EMAC

TxDMA Transmit Read Pointer value, {EMAC_TRP_H,

EMAC_TRP_L}. Bit 7 is bit 15 (msb) of the 16-bit value. Bit

0 is bit 8 of the 16-bit value.

EMAC Receive Blocks Left Register—Low and High Bytes

This register reports the number of buffers left in the Receive EMAC shared mem-

ory. The hardware uses this information, along with the Block-Level set in the

EMAC_BUFSZ register, to determine when to transmit a pause control frame.

Software can use this information to determine when it should request that a

pause control frame be transmitted (by setting bit 6 of the EMAC_CFG4 register).

For the BlksLeft logic to operate properly, the Receive buffer must contain at least

one more packet buffer than the number of packet buffers required for the largest

packet. That is, one packet cannot fill the entire Receive buffer. Otherwise, the

BlksLeft will be in error. See Tables 180 and 181.

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Table 180. EMAC Receive Blocks Left Register—Low Byte

(EMAC_BLKSLFT_L = 0055h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value

Description

[7:0]

00h–

These bits represent the Low byte of the 2-byte EMAC

Receive Blocks Left value, {EMAC_BLKSLFT_H,

EMAC_BLKSLFT_L}. Bit 7 is bit 7 of the 16-bit value.

Bit 0 is bit 0 (lsb) of the 16-bit value.

EMAC_BLKSLFT_L FFh

Table 181. EMAC Receive Blocks Left Register—High Byte

(EMAC_BLKSLFT_H = 0056h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value

Description

[7:0]

00h–

These bits represent the High byte of the 2-byte EMAC

Receive Blocks Left value, {EMAC_BLKSLFT_H,

EMAC_BLKSLFT_L}. Bit 7 is bit 15 (msb) of the 16-bit

value. Bit 0 is bit 8 of the 16-bit value.

EMAC_BLKSLFT_H FFh

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EMAC FIFO Data Register—Low and High Bytes

The FIFO Read/Write Test Access Data Register allows writing and reading the

FIFO selected by the EMAC_TEST TxRx_SEL bit when the EMAC_TEST register

TEST_FIFO bit is set. See Tables 182 and 183.

Table 182. EMAC FIFO Data Register—Low Byte

(EMAC_FDATA_L = 0057h)

Bit

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

X

Reset

CPU Access

Note: R/W = Read/Write.

R/W

Bit

Position

Value

00h–

Description

[7:0]

These bits represent the Low byte of the 10-bit EMAC

FIFO data value, {EMAC_FDATA_H[1:0],

EMAC_FDATA_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is

bit 0 (lsb) of the 10-bit value.

EMAC_FDATA_L FFh

Table 183. EMAC FIFO Data Register—High Byte

(EMAC_FDATA_H = 0058h)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

X

0

X

Reset

CPU Access

R

R/W

Note: R = Read Only; R/W = Read/Write.

Bit

Position

Value

Description

[7:2]

00h

Reserved.

[1:0]

0h–3h These bits represent the upper two bits of the 10-bit

EMAC FIFO data value, {EMAC_FDATA_H[1:0],

EMAC_FDATA_H

EMAC_FDATA_L}. Bit 1 is bit 9 (msb) of the 16-bit value.

Bit 0 is bit 8 of the 10-bit value.

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EMAC FIFO Flags Register

The FIFO Flags value is set in the EMAC module hardware to half full, or 16

bytes. See Table 184.

Table 184. EMAC FIFO Flags Register

(EMAC_FFLAGS = 0059h)

Bit

7

0

6

0

5

1

4

1

3

0

2

0

1

0

1

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value

Description

7

TFF

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Transmit FIFO full.

Transmit FIFO not full.

Reserved.

6

5

Transmit FIFO almost empty.

Transmit FIFO not almost empty.

Transmit FIFO empty.

TFAE

4

TFE

Transmit FIFO not empty.

Receive FIFO full.

3

RFF

Receive FIFO not full.

2

Receive FIFO almost full.

Receive FIFO not almost full.

Receive FIFO almost empty.

Receive FIFO not almost empty.

Receive FIFO empty.

RFAF

1

RFAE

0

RFE

Receive FIFO not empty.

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ZiLOG Debug Interface

Introduction

The ZiLOG Debug Interface (ZDI) provides a built-in debugging interface to the

CPU. ZDI provides basic in-circuit emulation features including:

•

Examining and modifying internal registers

Examining and modifying memory

Starting and stopping the user program

Setting program and data break points

Single-stepping the user program

Executing user-supplied instructions

Debugging the final product with the inclusion of one small connector

Downloading code into SRAM

C source-level debugging using ZiLOG Developer Studio II (ZDSII)

The above features are built into the silicon. Control is provided via a two-wire

interface that is connected to the ZPAKII emulator. Figure 51 illustrates a typical

setup using a a target board, ZPAKII, and the host PC running ZiLOG Developer

Studio II. Refer to the ZiLOG website for more information on ZPAKII and ZDSII.

Target Board

C

O

N

E

C

T

O

R

ZiLOG

Developer

Studio

ZPAK

Emulator

eZ80

Product

Figure 51. Typical ZDI Debug Setup

ZDI allows reading and writing of most internal registers without disturbing the

state of the machine. Reads and Writes to memory can occur as fast as the ZDI

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downloads and uploads data, with a maximum frequency of one-half the eZ80F91

system clock frequency, or less. See Table 185 for recommended values.

Table 185. Recommend ZDI Clock vs. System Clock Frequency

System Clock Frequency

3–10 MHz

ZDI Clock Frequency

1MHz

2MHz

4MHz

8MHz

8–16 MHz

12–24 MHz

20–50 MHz

ZDI-Supported Protocol

ZDI supports a bidirectional serial protocol. The protocol defines any device that

sends data as the transmitter and any receiving device as the receiver. The

device controlling the transfer is the master and the device being controlled is the

slave. The master always initiates the data transfers and provides the clock for

both receive and transmit operations. The ZDI block on the eZ80F91 device is

considered a slave in all data transfers.

Figure 52 illustrates the schematic for building a connector on a target board. This

connector allows the user to connect directly to the ZPAK emulator using a six-pin

header.

TV_DD

(Target V_DD

)

330 KΩ

2

4

6

1

3

5

TCK (ZCL)

TDI (ZDA)

eZ80F91

6-Pin Target Connector

Figure 52. Schematic For Building a Target Board ZPAK Connector

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ZDI Clock and Data Conventions

The two pins used for communication with the ZDI block are the ZDI clock pin

(ZCL) and the ZDI data pin (ZDA). On the eZ80F91, the ZCL pin is shared with

the TCK pin while the ZDA pin is shared with the TDI pin. The ZCL and ZDA pin

functions are only available when the On-Chip Instrumentation is disabled and the

ZDI is therefore enabled. For general data communication, the data value on the

ZDA pin can change only when ZCL is Low (0). The only exception is the ZDI

START bit, which is indicated by a High-to-Low transition (falling edge) on the

ZDA pin while ZCL is High.

Data is shifted into and out of ZDI, with the most-significant bit (bit 7) of each byte

being first in time, and the least-significant bit (bit 0) last in time. All information is

passed between the master and the slave in 8-bit (single-byte) units. Each byte is

transferred with nine clock cycles: eight to shift the data, and the ninth for internal

operations.

ZDI START Condition

All ZDI commands are preceded by the ZDI START signal, which is a High-to-Low

transition of ZDA when ZCL is High. The ZDI slave on the eZ80F91 device contin-

ually monitors the ZDA and ZCL lines for the START signal and does not respond

to any command until this condition is met. The master pulls ZDA Low, with ZCL

High, to indicate the beginning of a data transfer with the ZDI block. Figures 53

and 54 illustrate a valid ZDI START signal prior to writing and reading data,

respectively. A Low-to-High transition of ZDA while the ZCL is High produces no

effect.

Data is shifted in during a Write to the ZDI block on the rising edge of ZCL, as

illustrated in Figure 53. Data is shifted out during a Read from the ZDI block on

the falling edge of ZCL as illustrated in Figure 54. When an operation is com-

pleted, the master stops during the ninth cycle and holds the ZCL signal High.

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ZDI Data In

(Write)

ZDI Data In

(Write)

ZCL

ZDA

Start Signal

Figure 53. ZDI Write Timing

ZDI Data Out

(Read)

ZDI Data Out

(Read)

ZCL

ZDA

Start Signal

Figure 54. ZDI Read Timing

ZDI Single-Bit Byte Separator

Following each 8-bit ZDI data transfer, a single-bit byte separator is used. To ini-

tiate a new ZDI command, the single-bit byte separator must be High (logical 1) to

allow for a new ZDI START command to be sent. For all other cases, the single-bit

byte separator can be either Low (logical 0) or High (logical 1). When ZDI is con-

figured to allow the CPU to accept external bus requests, the single-bit byte sepa-

rator should be Low (logical 0) during all ZDI commands. This Low value indicates

that ZDI is still operating and is not ready to relinquish the bus. The CPU does not

accept the external bus requests until the single-bit byte separator is a High (logi-

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cal 1). For more information on accepting bus requests in ZDI DEBUG mode,

please see the Bus Requests During ZDI Debug Mode section on page 293.

ZDI Register Addressing

Following a START signal the ZDI master must output the ZDI register address.

All data transfers with the ZDI block use special ZDI registers. The ZDI control

registers that reside in the ZDI register address space should not be confused

with the eZ80F91 device peripheral registers that reside in the I/O address space.

Many locations in the ZDI control register address space are shared by two regis-

ters—one for Read Only access and one for Write Only access. As an example, a

Read from ZDI register address 00hreturns the eZ80 Product ID Low Byte, while

a Write to this same location, 00h, stores the Low byte of one of the address

match values used for generating break points.

The format for a ZDI address is seven bits of address, followed by one bit for

Read or Write control, and completed by a single-bit byte separator. The ZDI exe-

cutes a Read or Write operation depending on the state of the R/W bit (0 = Write,

1 = Read). If no new START command is issued at completion of the Read or

Write operation, the operation can be repeated. This allows repeated Read or

Write operations without having to resend the ZDI command. A START signal

must follow to initiate a new ZDI command. Figure 55 illustrates the timing for

address Writes to ZDI registers.

Single-Bit

Byte Separator

or new ZDI

START Signal

ZDI Address Byte

ZCL

ZDA

S

1

2

3

4

5

6

7

8

9

A6

A5

A4

A3

A2

A1

A0

lsb

R/W 0/1

msb

START

Signal

0 = WRITE

1 = READ

Figure 55. ZDI Address Write Timing

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ZDI Write Operations

ZDI Single-Byte Write

For single-byte Write operations, the address and write control bit are first written

to the ZDI block. Following the single-bit byte separator, the data is shifted into the

ZDI block on the next 8 rising edges of ZCL. The master terminates activity after 8

clock cycles.Figure 56 illustrates the timing for ZDI single-byte Write operations.

ZDI Data Byte

ZCL

ZDA

7

8

9

1

2

3

4

5

6

7

8

9

A0

Write

0/1

D7

D6

D5

D4

D3

D2

D1

D0

1

msb

of DATA

lsb

of DATA

lsb of

Single-Bit

End of Data

or New ZDI

START Signal

ZDI Address Byte Separator

Figure 56. ZDI Single-Byte Data Write Timing

ZDI Block Write

The block Write operation is initiated in the same manner as the single-byte Write

operation, but instead of terminating the Write operation after the first data byte is

transferred, the ZDI master can continue to transmit additional bytes of data to the

ZDI slave on the eZ80F91 device. After the receipt of each byte of data the ZDI

register address increments by 1. If the ZDI register address reaches the end of

the Write Only ZDI register address space (30h), the address stops incrementing.

Figure 57 illustrates the timing for ZDI block Write operations.

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ZDI Data Bytes

ZCL

ZDA

7

8

9

1

2

3

7

8

9

1

2

9

A0

Write

0/1

D7

D6

D5

D1

D0

0/1

D7

D6

1

msb

of DATA

Byte 1

lsb

of DATA

Byte 1

msb

of DATA

Byte 2

lsb of

Single-Bit

Byte Separator

ZDI Address Byte Separator

Figure 57. ZDI Block Data Write Timing

ZDI Read Operations

ZDI Single-Byte Read

Single-byte Read operations are initiated in the same manner as single-byte Write

operations, with the exception that the R/W bit of the ZDI register address is set to

1. Upon receipt of a slave address with the R/W bit set to 1, the eZ80F91 device’s

ZDI block loads the selected data into the shifter at the beginning of the first cycle

following the single-bit data separator. The most-significant bit (msb) is shifted out

first. Figure 58 illustrates the timing for ZDI single-byte Read operations.

ZDI Data Byte

ZCL

ZDA

7

8

9

1

2

3

4

5

6

7

8

9

A0

Read

0/1

D7

D6

D5

D4

D3

D2

D1

D0

1

msb

of DATA

lsb

of DATA

lsb of

Single-Bit

End of Data

or New ZDI

START Signal

ZDI Address Byte Separator

Figure 58. ZDI Single-Byte Data Read Timing

ZDI Block Read

A block Read operation is initiated in the same manner as a single-byte Read;

however, the ZDI master continues to clock in the next byte from the ZDI slave as

the ZDI slave continues to output data. The ZDI register address counter incre-

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ments with each Read. If the ZDI register address reaches the end of the Read

Only ZDI register address space (20h), the address stops incrementing. Figure 59

illustrates the ZDI’s block Read timing.

ZDI Data Bytes

ZCL

ZDA

7

8

9

1

2

3

7

8

9

1

2

9

A0

Read

0/1

D7

D6

D5

D1

D0

0/1

D7

D6

1

msb

of DATA

Byte 1

lsb

of DATA

Byte 1

msb

of DATA

Byte 2

lsb of

Single-Bit

Byte Separator

ZDI Address Byte Separator

Figure 59. ZDI Block Data Read Timing

Operation of the eZ80F91 Device during ZDI Break Points

If the ZDI forces the CPU to break, only the CPU suspends operation. The system

clock continues to operate and drive other peripherals. Those peripherals that can

operate autonomously from the CPU can continue to operate, if so enabled. For

example, the Watch-Dog Timer and Programmable Reload Timers continue to

count during a ZDI break point.

When using the ZDI interface, any Write or Read operations of peripheral regis-

ters in the I/O address space produces the same effect as Read or Write opera-

tions using the CPU. Because many register Read/Write operations exhibit

secondary effects, such as clearing flags or causing operations to commence, the

effects of the Read/Write operations during a ZDI break must be taken into con-

sideration.

Bus Requests During ZDI Debug Mode

The ZDI block on the eZ80F91 device allows an external device to take control of

the address and data bus while the eZ80F91 device is in DEBUG mode.

ZDI_BUSACK_EN causes ZDI to allow or prevent acknowledgement of bus

requests by external peripherals. The bus acknowledge only occurs at the end of

the current ZDI operation (indicated by a High during the single-bit byte separa-

tor). The default reset condition is for bus acknowledgement to be disabled. To

allow bus acknowledgement, the ZDI_BUSACK_EN must be written.

When an external bus request (BUSREQ pin asserted) is detected, ZDI waits until

completion of the current operation before responding. ZDI acknowledges the bus

request by asserting the bus acknowledge (BUSACK) signal. If the ZDI block is

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not currently shifting data, it acknowledges the bus request immediately. ZDI uses

the single-bit byte separator of each data word to determine if it is at the end of a

ZDI operation. If the bit is a logical 0, ZDI does not assert BUSACK to allow addi-

tional data Read or Write operations. If the bit is a logical 1, indicating completion

of the ZDI commands, BUSACK is asserted.

Potential Hazards of Enabling Bus Requests During Debug Mode

There are some potential hazards that the user must be aware of when enabling

external bus requests during ZDI DEBUG mode. First, when the address and data

bus are being used by an external source, ZDI must only access ZDI registers

and internal CPU registers to prevent possible bus contention. The bus acknowl-

edge status is reported in the ZDI_BUS_STAT register. The BUSACK output pin

also indicates the bus acknowledge state.

A second hazard is that when a bus acknowledge is granted, the ZDI is subject to

any wait states that are assigned to the device currently being accessed by the

external peripheral. To prevent data errors, ZDI should avoid data transmission

while another device is controlling the bus.

Finally, exiting ZDI Debug mode while an external peripheral controls the address

and data buses, as indicated by BUSACK assertion, can produce unpredictable

results.

ZDI Write Only Registers

Table 186 lists the ZDI Write Only registers. Many of the ZDI Write Only

addresses are shared with ZDI Read Only registers.

Table 186. ZDI Write Only Registers

Reset

ZDI Address ZDI Register Name ZDI Register Function

Value

XXh

00h

01h

02h

04h

05h

06h

08h

09h

0Ah

0Ch

ZDI_ADDR0_L

ZDI_ADDR0_H

ZDI_ADDR0_U

ZDI_ADDR1_L

ZDI_ADDR1_H

ZDI_ADDR1_U

ZDI_ADDR2_L

ZDI_ADDR2_H

ZDI_ADDR2_U

ZDI_ADDR3_L

Address Match 0 Low Byte

Address Match 0 High Byte

Address Match 0 Upper Byte

Address Match 1 Low Byte

Address Match 1 High Byte

Address Match 1 Upper Byte

Address Match 2 Low Byte

Address Match 2 High Byte

Address Match 2 Upper Byte

Address Match 3 Low Byte

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Table 186. ZDI Write Only Registers (Continued)

Reset

Value

ZDI Address ZDI Register Name ZDI Register Function

0Dh

0Eh

10h

11h

13h

14h

15h

16h

17h

21h

22h

23h

24h

25h

30h

ZDI_ADDR3_H

ZDI_ADDR3_U

ZDI_BRK_CTL

Address Match 3 High Byte

XXh

00h

XXh

00h

XXh

Address Match 4 Upper Byte

Break Control Register

ZDI_MASTER_CTL Master Control Register

ZDI_WR_DATA_L

ZDI_WR_DATA_H

ZDI_WR_DATA_U

ZDI_RW_CTL

ZDI_BUS_CTL

ZDI_IS4

Write Data Low Byte

Write Data High Byte

Write Data Upper Byte

Read/Write Control Register

Bus Control Register

Instruction Store 4

ZDI_IS3

Instruction Store 3

ZDI_IS2

Instruction Store 2

ZDI_IS1

Instruction Store 1

ZDI_IS0

Instruction Store 0

ZDI_WR_MEM

Write Memory Register

ZDI Read Only Registers

Table 187 lists the ZDI Read Only registers. Many of the ZDI Read Only

addresses are shared with ZDI Write Only registers.

Table 187. ZDI Read Only Registers

Reset

Value

ZDI Address

00h

ZDI Register Name

ZDI_ID_L

ZDI Register Function

eZ80 Product ID Low Byte Register

eZ80 Product ID High Byte Register

eZ80 Product ID Revision Register

Status Register

08h

00h

XXh

00h

XXh

01h

ZDI_ID_H

02h

ZDI_ID_REV

ZDI_STAT

03h

10h

ZDI_RD_L

Read Memory Address Low Byte Register

Read Memory Address High Byte Register

Read Memory Address Upper Byte Register

11h

ZDI_RD_H

ZDI_RD_U

12h

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Table 187. ZDI Read Only Registers (Continued)

Reset

Value

ZDI Address

17h

ZDI Register Name

ZDI_BUS_STAT

ZDI_RD_MEM

ZDI Register Function

Bus Status Register

00h

20h

Read Memory Data Value

XXh

ZDI Register Definitions

ZDI Address Match Registers

The four sets of address match registers are used for setting the addresses for

generating break points. When the accompanying BRK_ADDRX bit is set in the

ZDI Break Control register to enable the particular address match, the current

eZ80F91 address is compared with the 3-byte address set, {ZDI_ADDRx_U,

ZDI_ADDRx_H, ZDI_ADDR_x_L}. If the CPU is operating in ADL mode, the

address is supplied by ADDR[23:0]. If the CPU is operating in Z80 mode, the

address is supplied by {MBASE[7:0], ADDR[15:0]}. If a match is found, ZDI issues

a break to the eZ80F91 device placing the CPU in ZDI mode pending further

instructions from the ZDI interface block. If the address is not the first op-code

fetch, the ZDI break is executed at the end of the instruction in which it is exe-

cuted. There are four sets of address match registers. They can be used in con-

junction with each other to break on branching instructions. See Table 188.

Table 188. ZDI Address Match Registers

ZDI_ADDR0_L = 00h, ZDI_ADDR0_H = 01h, ZDI_ADDR0_U = 02h,

ZDI_ADDR1_L = 04h, ZDI_ADDR1_H = 05h, ZDI_ADDR1_U = 06h,

ZDI_ADDR2_L = 08h, ZDI_ADDR2_H = 09h, ZDI_ADDR2_U = 0Ah,

ZDI_ADDR3_L = 0Ch, ZDI_ADDR3_H = 0Dh, and ZDI_ADDR3_U = 0Eh

in the ZDI Register Write Only Address Space

Bit

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

X

Reset

CPU Access

Note: W = Write Only.

W

Bit

Position

Value Description

00h– The four sets of ZDI address match registers are used for

[7:0]

ZDI_ADDRX_L,

ZDI_ADDRX_H,

or

FFh

setting the addresses for generating break points. The 24-

bit addresses are supplied by {ZDI_ADDRx_U,

ZDI_ADDRx_H, ZDI_ADDRx_L, where x is 0, 1, 2, or 3.

ZDI_ADDRX_U

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ZDI Break Control Register

The ZDI Break Control register is used to enable break points. ZDI asserts a

break when the CPU instruction address, ADDR[23:0], matches the value in the

ZDI Address Match 3 registers, {ZDI_ADDR3_U, ZDI_ADDR3_H,

ZDI_ADDR3_L}. BREAKs can only occur on an instruction boundary. If the

instruction address is not the beginning of an instruction (that is, for multibyte

instructions), then the break occurs at the end of the current instruction. The

BRK_NEXT bit is set to 1. The BRK_NEXT bit must be reset to 0 to release the

break. See Table 189.

Table 189. ZDI Break Control Register

(ZDI_BRK_CTL = 10h in the ZDI Write Only Register Address Space)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: W = Write Only.

W

Bit

Position

Value Description

7

0

The ZDI break on the next CPU instruction is disabled.

Clearing this bit releases the CPU from its current BREAK

condition.

BRK_NEXT

1

The ZDI break on the next CPU instruction is enabled.

The CPU can use multibyte Op Codes and multibyte

operands. Break points only occur on the first Op Code in

a multibyte Op Code instruction. If the ZCL pin is High and

the ZDA pin is Low at the end of RESET, this bit is set to 1

and a break occurs on the first instruction following the

RESET. This bit is set automatically during ZDI break on

address match. A break can also be forced by writing a 1

to this bit.

6

0

1

0

1

The ZDI break, upon matching break address 3, is

disabled.

BRK_ADDR3

The ZDI break, upon matching break address 3, is

enabled.

5

The ZDI break, upon matching break address 2, is

disabled.

BRK_ADDR2

The ZDI break, upon matching break address 2, is

enabled.

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Bit

Position

Value Description

4

0

1

0

1

0

The ZDI break, upon matching break address 1, is

disabled.

BRK_ADDR1

The ZDI break, upon matching break address 1, is

enabled.

3

The ZDI break, upon matching break address 0, is

disabled.

BRK_ADDR0

The ZDI break, upon matching break address 0, is

enabled.

2

The Ignore the Low Byte function of the ZDI Address

Match 1 registers is disabled. If BRK_ADDR1 is set to 1,

ZDI initiates a break when the entire 24-bit address,

ADDR[23:0], matches the 3-byte value {ZDI_ADDR1_U,

ZDI_ADDR1_H, ZDI_ADDR1_L}.

IGN_LOW_1

1

The Ignore the Low Byte function of the ZDI Address

Match 1 registers is enabled. If BRK_ADDR1 is set to 1,

ZDI initiates a break when only the upper 2 bytes of the

24-bit address, ADDR[23:8], match the 2-byte value

{ZDI_ADDR1_U, ZDI_ADDR1_H}. As a result, a break

can occur anywhere within a 256-byte page.

1

0

1

The Ignore the Low Byte function of the ZDI Address

Match 1 registers is disabled. If BRK_ADDR0 is set to 1,

ZDI initiates a break when the entire 24-bit address,

ADDR[23:0], matches the 3-byte value {ZDI_ADDR0_U,

ZDI_ADDR0_H, ZDI_ADDR0_L}.

IGN_LOW_0

The Ignore the Low Byte function of the ZDI Address

Match 1 registers is enabled. If the BRK_ADDR1 is set to

0, ZDI initiates a break when only the upper 2 bytes of the

24-bit address, ADDR[23:8], match the 2 bytes value

{ZDI_ADDR0_U, ZDI_ADDR0_H}. As a result, a break

can occur anywhere within a 256-byte page.

0

1

ZDI SINGLE STEP mode is disabled.

SINGLE_STEP

ZDI SINGLE STEP mode is enabled. ZDI asserts a break

following execution of each instruction.

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ZDI Master Control Register

The ZDI Master Control register provides control of the eZ80F91 device. It is

capable of forcing a RESET and waking up the eZ80F91 from the low-power

modes (HALT or SLEEP). See Table 190.

Table 190. ZDI Master Control Register

(ZDI_MASTER_CTL = 11h in ZDI Register Write Address Spaces)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: W = Write Only.

W

Bit

Position

Value

Description

7

0

1

No action.

ZDI_RESET

Initiate a RESET of the eZ80F91. This bit is

automatically cleared at the end of the RESET event.

[6:0]

0000000 Reserved.

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ZDI Write Data Registers

These three registers are used in the ZDI Write Only register address space to

store the data that is written when a Write instruction is sent to the ZDI Read/Write

Control register (ZDI_RW_CTL). The ZDI Read/Write Control register is located at

ZDI address 16himmediately following the ZDI Write Data registers. As a result,

the ZDI Master is allowed to write the data to {ZDI_WR_U, ZDI_WR_H,

ZDI_WR_L} and the Write command in one data transfer operation. See Table

191.

Table 191. ZDI Write Data Registers

(ZDI_WR_U = 13h, ZDI_WR_H = 14h, and ZDI_WR_L = 15h

in the ZDI Register Write Only Address Space)

Bit

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

X

Reset

CPU Access

W

Note: X = Undefined; W = Write.

Bit

Position

Value Description

00h– These registers contain the data that is written during

[7:0]

ZDI_WR_L,

ZDI_WR_H,

or

FFh

execution of a Write operation defined by the

ZDI_RW_CTL register. The 24-bit data value is stored as

{ZDI_WR_U, ZDI_WR_H, ZDI_WR_L}. If less than 24 bits

of data are required to complete the required operation,

the data is taken from the least-significant byte(s).

ZDI_WR_L

ZDI Read/Write Control Register

The ZDI Read/Write Control register is used in the ZDI Write Only Register

address to read data from, write data to, and manipulate the CPU’s registers or

memory locations. When this register is written, the eZ80F91 device immediately

performs the operation corresponding to the data value written as described in

Table 192. When a Read operation is executed via this register, the requested

data values are placed in the ZDI Read Data registers {ZDI_RD_U, ZDI_RD_H,

ZDI_RD_L}. When a Write operation is executed via this register, the Write data is

taken from the ZDI Write Data registers {ZDI_WR_U, ZDI_WR_H, ZDI_WR_L}.

See Table 192. Refer to the eZ80 CPU User Manual (UM0077) on zilog.com for

information regarding the CPU registers.

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Table 192. ZDI Read/Write Control Register Functions*

(ZDI_RW_CTL = 16h in the ZDI Register Write Only Address Space)

Hex

Value

Command

Value

Command

00

01

02

03

04

05

Read {MBASE, A, F}

ZDI_RD_U ← MBASE

ZDI_RD_H ← F

80

81

82

83

84

85

Write AF

MBASE ← ZDI_WR_U

F

A

← ZDI_WR_H

← ZDI_WR_L

ZDI_RD_L ← A

Read BC

Write BC

BCU ← ZDI_WR_U

ZDI_RD_U ← BCU

ZDI_RD_H ← B

ZDI_RD_L ← C

B

C

← ZDI_WR_H

← ZDI_WR_L

Read DE

Write DE

DEU ← ZDI_WR_U

ZDI_RD_U ← DEU

ZDI_RD_H ← D

ZDI_RD_L ← E

D

E

← ZDI_WR_H

← ZDI_WR_L

Read HL

Write HL

HLU ← ZDI_WR_U

ZDI_RD_U ← HLU

ZDI_RD_H ← H

ZDI_RD_L ← L

H

L

← ZDI_WR_H

← ZDI_WR_L

Read IX

Write IX

ZDI_RD_U ← IXU

ZDI_RD_H ← IXH

ZDI_RD_L ← IXL

IXU ← ZDI_WR_U

IXH ← ZDI_WR_H

IXL ← ZDI_WR_L

Read IY

Write IY

ZDI_RD_U ← IYU

ZDI_RD_H ← IYH

ZDI_RD_L ← IYL

IYU ← ZDI_WR_U

IYH ← ZDI_WR_H

IYL ← ZDI_WR_L

06

07

Read SP

In ADL mode, SP = SPL.

In Z80 mode, SP = SPS.

86

87

Write SP

In ADL mode, SP = SPL.

In Z80 mode, SP = SPS.

Read PC

Write PC

ZDI_RD_U ← PC[23:16]

ZDI_RD_H ← PC[15:8]

ZDI_RD_L ← PC[7:0]

PC[23:16] ← ZDI_WR_U

PC[15:8] ← ZDI_WR_H

PC[7:0] ← ZDI_WR_L

08

Set ADL

88

Reserved

ADL

← 1

Note: *The CPU’s alternate register set (A’, F’, B’, C’, D’, E’, HL’) cannot be read directly. The ZDI

programmer must execute the exchange instruction (EXX) to gain access to the alternate

CPU register set.

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Table 192. ZDI Read/Write Control Register Functions*

(ZDI_RW_CTL = 16h in the ZDI Register Write Only Address Space) (Continued)

Hex

Value

Command

Value

Command

09

Reset ADL

89

Reserved

ADL

← 0

0A

Exchange CPU register sets 8A

Reserved

AF

BC

DE

HL

←

AF’

BC’

DE’

HL’

0B

Read memory from current

PC value, increment PC

8B

Write memory from current PC

value, increment PC

Note: *The CPU’s alternate register set (A’, F’, B’, C’, D’, E’, HL’) cannot be read directly. The ZDI

programmer must execute the exchange instruction (EXX) to gain access to the alternate

CPU register set.

ZDI Bus Control Register

The ZDI Bus Control register controls bus requests during DEBUG mode. It

enables or disables bus acknowledge in ZDI DEBUG mode and allows ZDI to

force assertion of the BUSACK signal. This register should only be written during

ZDI Debug mode (that is, following a break). See Table 193.

Table 193. ZDI Bus Control Register

(ZDI_BUS_CTL = 17h in the ZDI Register Write Only Address Space)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: W = Write Only.

W

Bit

Position

Value

Description

7

0

Bus requests by external peripherals using the BUSREQ

pin are ignored. The bus acknowledge signal, BUSACK,

is not asserted in response to any bus requests.

ZDI_BUSAK_EN

1

Bus requests by external peripherals using the BUSREQ

pin are accepted. A bus acknowledge occurs at the end of

the current ZDI operation. The bus acknowledge is

indicated by asserting the BUSACK pin in response to a

bus request.

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Bit

Position

Value

Description

6

0

Deassert the bus acknowledge pin (BUSACK) to return

control of the address and data buses back to ZDI.

ZDI_BUSAK

1

Assert the bus acknowledge pin (BUSACK) to pass

control of the address and data buses to an external

peripheral.

[5:0]

000000 Reserved.

Instruction Store 4:0 Registers

The ZDI Instruction Store registers are located in the ZDI Register Write Only

address space. They can be written with instruction data for direct execution by

the CPU. When the ZDI_IS0 register is written, the eZ80F91 device exits the ZDI

break state and executes a single instruction. The Op Codes and operands for the

instruction come from these Instruction Store registers. The Instruction Store Reg-

ister 0 is the first byte fetched, followed by Instruction Store registers 1, 2, 3, and

4, as necessary. Only the bytes the CPU requires to execute the instruction must

be stored in these registers. Some CPU instructions, when combined with the

MEMORY mode suffixes (.SIS, .SIL, .LIS, or .LIL), require 6 bytes to operate.

These 6-byte instructions cannot be executed directly using the ZDI Instruction

Store registers. See Table 194.

The Instruction Store 0 register is located at a higher ZDI address than the other

Instruction Store registers. This feature allows the use of the ZDI auto-address

increment function to load and execute a multibyte instruction with a single data

stream from the ZDI master. Execution of the instruction commences with writing

the final byte to ZDI_IS0.

Note:

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Table 194. Instruction Store 4:0 Registers

(ZDI_IS4 = 21h, ZDI_IS3 = 22h, ZDI_IS2 = 23h, ZDI_IS1 = 24h, and ZDI_IS0 = 25h

in the ZDI Register Write Only Address Space)

Bit

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

X

Reset

CPU Access

W

Note: X = Undefined; W = Write.

Bit

Position

Value Description

00h– These registers contain the Op Codes and operands for

[7:0]

ZDI_IS4,

ZDI_IS3,

ZDI_IS2,

ZDI_IS1,

or

FFh

immediate execution by the CPU following a Write to

ZDI_IS0. The ZDI_IS0 register contains the first Op Code

of the instruction. The remaining ZDI_ISx registers

contain any additional Op Codes or operand dates

required for execution of the required instruction.

ZDI_IS0

ZDI Write Memory Register

A Write to the ZDI Write Memory register causes the eZ80F91 device to write the

8-bit data to the memory location specified by the current address in the Program

Counter. In Z80 MEMORY mode, this address is {MBASE, PC[15:0]}. In ADL

MEMORY mode, this address is PC[23:0]. The Program Counter, PC, increments

after each data Write. However, the ZDI register address does not increment auto-

matically when this register is accessed. As a result, the ZDI master is allowed to

write any number of data bytes by writing to this address one time followed by any

number of data bytes. See Table 195.

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Table 195. ZDI Write Memory Register

(ZDI_WR_MEM = 30h in the ZDI Register Write Only Address Space)

Bit

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

X

Reset

CPU Access

W

Note: X = Undefined; W = Write.

Bit

Position

Value Description

00h– The 8-bit data that is transferred to the ZDI slave following

[7:0]

ZDI_WR_MEM

FFh

a Write to this address is written to the address indicated

by the current Program Counter. The Program Counter is

incremented following each 8 bits of data. In Z80

MEMORY mode, ({MBASE, PC[15:0]})

← 8 bits of

transferred data. In ADL MEMORY mode, (PC[23:0])

←

8-bits of transferred data.

eZ80 Product ID Low and High Byte Registers

The eZ80 Product ID Low and High Byte registers combine to provide a means for

®

an external device to determine the particular eZ80 product being addressed.

See Tables 196 and 197.

Table 196. eZ80 Product ID Low Byte Register

(ZDI_ID_L = 00h in the ZDI Register Read Only Address Space,

ZDI_ID_L = 0000h in the I/O Register Address Space)

Bit

7

0

6

0

5

0

4

0

3

1

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value Description

[7:0]

ZDI_ID_L

08h

{ZDI_ID_H, ZDI_ID_L} = {00h, 08h} indicates the

eZ80F91 product.

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Table 197. eZ80 Product ID High Byte Register

(ZDI_ID_H = 01h in the ZDI Register Read Only Address Space,

ZDI_ID_H = 0001h in the I/O Register Address Space)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value Description

[7:0]

ZDI_ID_H

00h

{ZDI_ID_H, ZDI_ID_L} = {00h, 08h} indicates the

eZ80F91 device.

eZ80 Product ID Revision Register

The eZ80 Product ID Revision register identifies the current revision of the

eZ80F91 product. See Table 198. The revision register use the same numbering

used in the mask revision of the die. The first nibble (most-significant) corre-

sponds to a full mask revision, while the second nibble refers to a partial mask

revision.

Table 198. eZ80 Product ID Revision Register

(ZDI_ID_REV = 02h in the ZDI Register Read Only Address Space,

ZDI_ID_REV = 0002h in the I/O Register Address Space)

Bit

7

X

R

6

X

R

5

X

R

4

X

R

3

X

R

2

X

R

1

X

R

0

X

R

Reset

CPU Access

Note: X = Undetermined; R = Read Only.

Bit

Position

Value Description

[7:0]

ZDI_ID_REV

00h– Identifies the current revision of the eZ80F91 product.

FFh

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ZDI Status Register

The ZDI Status register provides current information on the eZ80F91 device and

the CPU. See Table 199.

Table 199. ZDI Status Register

(ZDI_STAT = 03h in the ZDI Register Read Only Address Space)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value Description

7

0

1

0

1

0

The CPU is not functioning in ZDI mode.

ZDI_ACTIVE

The CPU is currently functioning in ZDI mode.

Reserved.

6

5

The CPU is not currently in HALT or SLEEP mode.

The CPU is currently in HALT or SLEEP mode.

halt_SLP

4

ADL

The CPU is operating in Z80 MEMORY mode.

(ADL bit = 0)

1

The CPU is operating in ADL MEMORY mode.

(ADL bit = 1)

3

0

1

0

The CPU’s Mixed-Memory mode (MADL) bit is reset to 0.

The CPU’s Mixed-Memory mode (MADL) bit is set to 1.

MADL

2

IEF1

The CPU’s Interrupt Enable Flag 1 is reset to 0. Maskable

interrupts are disabled.

1

The CPU’s Interrupt Enable Flag 1 is set to 1. Maskable

interrupts are enabled.

[1:0]

00

Reserved.

RESERVED

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ZDI Read Register Low, High, and Upper

The ZDI register Read Only address space offers Low, High, and Upper functions,

which contain the value read by a Read operation from the ZDI Read/Write Con-

trol register (ZDI_RW_CTL). This data is valid only while in ZDI BREAK mode and

only if the instruction is read by a request from the ZDI Read/Write Control regis-

ter. See Table 200.

Table 200. ZDI Read Register Low, High and Upper

(ZDI_RD_L = 10h, ZDI_RD_H = 11h, and ZDI_RD_U = 12h

in the ZDI Register Read Only Address Space)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value Description

00h– Values read from the memory location as requested by

[7:0]

ZDI_RD_L,

ZDI_RD_H,

or

FFh

the ZDI Read Control register during a ZDI Read

operation. The 24-bit value is supplied by {ZDI_RD_U,

ZDI_RD_H, ZDI_RD_L}.

ZDI_RD_U

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ZDI Bus Status Register

The ZDI Bus Status register monitors BUSACKs during DEBUG mode. See Table

201.

Table 201. ZDI Bus Control Register

(ZDI_BUS_STAT = 17h in the ZDI Register Read Only Address Space)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value

Description

7

0

Bus requests by external peripherals using the

BUSREQ pin are ignored. The bus acknowledge

signal, BUSACK, is not asserted.

ZDI_BUSACK_EN

1

Bus requests by external peripherals using the

BUSREQ pin are accepted. A bus acknowledge occurs

at the end of the current ZDI operation. The bus

acknowledge is indicated by asserting the BUSACK

pin.

6

0

1

Address and data buses are not relinquished to an

external peripheral. bus acknowledge is deasserted

(BUSACK pin is High).

ZDI_BUS_STAT

Address and data buses are relinquished to an external

peripheral. bus acknowledge is asserted (BUSACK pin

is Low).

[5:0]

000000 Reserved.

ZDI Read Memory Register

When a Read is executed from the ZDI Read Memory register, the eZ80F91

device fetches the data from the memory address currently pointed to by the Pro-

gram Counter, PC; the Program Counter is then incremented. In Z80 MEMORY

mode, the memory address is {MBASE, PC[15:0]}. In ADL MEMORY mode, the

memory address is PC[23:0]. Refer to the eZ80 CPU User Manual (UM0077),

available on zilog.com, for more information regarding Z80 and ADL MEMORY

modes. The Program Counter, PC, increments after each data Read. However,

the ZDI register address does not increment automatically when this register is

accessed. As a result, the ZDI master can read any number of data bytes out of

memory via the ZDI Read Memory register. See Table 202.

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Table 202. ZDI Read Memory Register

(ZDI_RD_MEM = 20h in the ZDI Register Read Only Address Space)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: R = Read Only.

R

Bit

Position

Value Description

00h– 8-bit data Read from the memory address indicated by

[7:0]

ZDI_RD_MEM

FFh

the CPU’s Program Counter. In Z80 MEMORY mode, 8-

bit data is transferred out from address {MBASE,

PC[15:0]}. In ADL Memory mode, 8-bit data is transferred

out from address PC[23:0].

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On-Chip Instrumentation

Introduction to On-Chip Instrumentation

1

®

On-Chip Instrumentation (OCI™) for the eZ80 CPU core enables powerful

debugging features. The OCI provides run control, memory and register visibility,

complex break points, and trace history features.

The OCI employs all of the functions of the ZiLOG Debug Interface (ZDI) as

described in the ZDI section. It also adds the following debug features:

•

Control via a 4-pin JTAG port that conforms to IEEE Standard 1149.1 (Test

Access Port and Boundary Scan Architecture)

•

Complex break point trigger functions

Break point enhancements, such as the ability to:

–

Define two break point addresses that form a range

Break on masked data values

Start or stop trace

Assert a trigger output signal

•

Trace history buffer

Software break point instruction

There are four sections to the OCI:

•

JTAG interface

ZDI debug control

Trace buffer memory

Complex triggers

This document contains information to activate the OCI for JTAG boundary scan

register operations. For additional information regarding OCI features, or to order

OCI debug tools, please contact:

First Silicon Solutions, Inc.

5440 SW Westgate Drive, Suite 240

Portland, OR 97221

Phone: (503) 292-6730

Fax: (503) 292-5840

www.fs2.com

1. On-Chip Instrumentation and OCI are trademarks of First Silicon Solutions,

Inc.

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OCI Activation

OCI features clock initialization circuitry so that external debug hardware can be

detected during power-up. The external debugger must drive the OCI clock pin

(TCK) Low at least two system clock cycles prior to the end of the RESET to acti-

vate the OCI block. If TCK is High at the end of the RESET, the OCI block shuts

down so that it does not draw power in normal product operation. When the OCI is

shut down, ZDI is enabled directly and can be accessed via the clock (TCK) and

data (TDI) pins. See the ZiLOG Debug Interface section on page 286 for more

information on ZDI.

OCI Interface

There are six dedicated pins on the eZ80F91 for the OCI interface. Four pins—

TCK, TMS, TDI, and TDO—are required for IEEE Standard 1149.1-compliant

JTAG ports. A fifth pin, TRSTn, is optional for IEEE 1149.1 and utilized by the

eZ80F91 device. The TRIGOUT pin provides additional testability features. These

six OCI pins are described in Table 203.

Table 203. OCI Pins

Symbol

Name

Type

Description

TCK

Clock.

Input

Asynchronous to the primary eZ80F91 system clock.

The TCK period must be at least twice the system

clock period. During RESET, this pin is sampled to

select either OCI or ZDI DEBUG modes. If Low

during RESET, the OCI is enabled. If High during

RESET, the OCI is powered down and ZDI DEBUG

mode is enabled. When ZDI DEBUG mode is active,

this pin is the ZDI clock. On-chip pull-up ensures a

default value of 1 (High).

TRSTn

TMS

TAP Reset

Input

Active Low asynchronous reset for the Test Access

Port state register. On-chip pull-up ensures a default

value of 1 (High).

Test Mode Select Input

This serial test mode input controls JTAG mode

selection. On-chip pull-up ensures a default value of

1 (High). The TMS signal is sampled on the rising

edge of the TCK signal.

TDI

Data In

Input

Serial test data input. This pin is input-only when the

(OCI enabled) OCI is enabled. The input data is sampled on the

rising edge of the TCK signal.

I/O

When the OCI is disabled, this pin functions as the

(OCI disabled) ZDA (ZDI Data) I/O pin. NORMAL mode, following

RESET, configures TDI as an input.

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Table 203. OCI Pins (Continued)

Symbol

Name

Type

Description

TDO

Data Out

Output

The output data changes on the falling edge of the

TCK signal.

TRIGOUT Trigger Output

Output

Generates an active High trigger pulse when valid

OCI trigger events occur. Output is tristate when no

data is being driven out.

JTAG Boundary Scan

Introduction

This section describes coverage, implementation, and usage of the eZ80F91

boundary scan register based on the Joint Test Action Group (JTAG) standard. A

working knowledge of the IEEE 1149.1 specification, particularly Clause 11, is

assumed.

Pin Coverage

All pins are included in the boundary scan chain, except for the following:

•

TCK

TMS

TDI

TDO

TRSTN

V_DD

V_SS

PLL_V_DD

PLL_V_SS

RTC_V_DD

X

IN

X

OUT

RTC_X

IN

RTC_X

OUT

LOOP_FILT

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Boundary Scan Cell Functionality

The boundary scan cells implemented are analogous to cell BC_1, defined in the

Standard VHDL Package STD_1149_1_2001.

All boundary scan cells are of the type control-and-observe; they provide both

controllability and observability for the pins to which they are connected. For

tristate outputs and bidirectional pins, this type includes controllability and observ-

ability of output enables.

Chain Sequence and Length

When enabled to shift data, the boundary scan shift register is connected to TDI

at the input line for TRIGOUT and to TDO at PD0. The shift register is arranged so

that data is shifted via the pins starting to the left of the OCI interface pins and pro-

ceeding clockwise around the chip. If a pin features multiple scannable bits (e.g.,

bidirectional pins or tristate output pins), the data is shifted first into the input sig-

nal, then the output, then the output enable (OEN).

The boundary scan register is 213 bits wide. Table 204 shows the ordering of bits

in the shift register, numbering them in clockwise order.

Table 204. Pin to Boundary Scan Cell Mapping

Direction

Input

Scan Cell #

Direction

Output

Input

Scan Cell #

107

TRIGOUT

HALT_SLP

BUSACK

BUSREQ

NMI

0

1

MII_TxD2

MII_TxD3

MII_COL

MII_CRS

PA7

Output

OEN

108

2

109

Output

Input

3

Input

110

4

Input

111

5

PA7

Output

OEN

112

Input

6

PA7

113

RESET

Input

7

PA6

Input

114

RESET_OUT

WAIT

Output

Input

8

PA6

Output

OEN

115

9

PA6

116

INSTRD

Notes:

Output

10

PA5

Input

117

1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are

shown to be associated with the least-significant bit that they control.

2. Direction on the data bus is controlled by a single output enable. It is shown in this table as being associated

with D[0].

3. MREQ, IORQ, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.

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Table 204. Pin to Boundary Scan Cell Mapping (Continued)

WR

RD

Direction

Output

OEN

Scan Cell #

11

Direction

Output

OEN

Scan Cell #

118

PA5

PA4

PA3

PA2

PA1

PA0

PHI

12

119

Output

Input

13

Input

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

MREQ

IORQ

D7

14

Output

OEN

Output

Input

15

16

Input

Output

Input

17

Output

OEN

18

D7

Output

Input

19

Input

D6

20

Output

OEN

D6

Output

Input

21

D5

22

Input

D5

Output

Input

23

Output

OEN

D4

24

D4

Output

Input

25

Input

D3

26

Output

OEN

D3

Output

Input

27

D2

28

Output

OEN

D2

Output

Input

29

PHI

D1

30

SCL

SDA

PB7

Input

D1

Output

Input

31

Output

Input

D0

32

D0

Output

OEN

33

Output

Input

D0

34

CS3

Notes:

Output

35

Output

1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are

shown to be associated with the least-significant bit that they control.

2. Direction on the data bus is controlled by a single output enable. It is shown in this table as being associated

with D[0].

3. MREQ, IORQ, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.

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Table 204. Pin to Boundary Scan Cell Mapping (Continued)

Direction

Output

Input

Scan Cell #

36

Direction

OEN

Scan Cell #

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

CS2

CS1

CS0

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

Notes:

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PC7

37

Input

38

Output

OEN

39

Output

Input

40

Input

41

Output

OEN

Output

Input

42

43

Input

Output

Input

44

Output

OEN

45

Output

Input

46

Input

47

Output

OEN

Output

Input

48

49

Input

Output

Input

50

Output

OEN

51

Output

Input

52

Input

53

Output

OEN

Output

OEN

54

55

Input

56

Output

OEN

Output

Input

57

58

Input

Output

Input

59

Output

OEN

60

1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are

shown to be associated with the least-significant bit that they control.

2. Direction on the data bus is controlled by a single output enable. It is shown in this table as being associated

with D[0].

3. MREQ, IORQ, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.

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Table 204. Pin to Boundary Scan Cell Mapping (Continued)

A13

A12

A11

A10

A9

Direction

Output

Input

Scan Cell #

61

Direction

Input

Scan Cell #

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PD7

PD6

62

Output

OEN

Output

Input

63

64

Input

Output

Input

65

Output

OEN

66

Output

Input

67

Input

68

Output

OEN

A9

Output

Input

69

A8

70

Input

A8

Output

OEN

71

Output

OEN

A8

72

A7

Input

73

Input

A7

Output

Input

74

Output

OEN

A6

75

A6

Output

Input

76

Input

A5

77

Output

OEN

A5

Output

Input

78

A4

79

Input

A4

Output

Input

80

Output

OEN

A3

81

A3

Output

Input

82

Input

A2

83

Output

OEN

A2

Output

Input

84

A1

85

Input

Notes:

1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are

shown to be associated with the least-significant bit that they control.

2. Direction on the data bus is controlled by a single output enable. It is shown in this table as being associated

with D[0].

3. MREQ, IORQ, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.

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Table 204. Pin to Boundary Scan Cell Mapping (Continued)

Direction

Output

Input

Scan Cell #

86

Direction

Output

OEN

Scan Cell #

193

A1

PD6

PD5

PD4

PD3

PD2

PD1

PD0

A0

87

194

A0

Output

OEN

88

Input

195

A0

89

Output

OEN

196

WP

Input

90

197

MII_MDIO

MII_MDC

MII_RxD3

MII_RxD2

MII_RxD1

MII_RxD0

MII_Rx_DV

MII_Rx_CLK

MII_Rx_ER

MII_Tx_ER

MII_Tx_CLK

MII_Tx_EN

MII_TxD0

MII_TxD1

Notes:

Input

91

Input

198

Output

OEN

92

Output

OEN

199

93

200

Output

Input

94

Input

201

95

Output

OEN

202

Input

96

203

Input

97

Input

204

Input

98

Output

OEN

205

Input

99

206

Input

100

101

102

103

104

105

106

Input

207

Input

Output

OEN

208

Output

Input

209

Input

210

Output

OEN

211

212

1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are

shown to be associated with the least-significant bit that they control.

2. Direction on the data bus is controlled by a single output enable. It is shown in this table as being associated

with D[0].

3. MREQ, IORQ, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.

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Usage

Boundary scan functionality is utilized by issuing the appropriate Test Access Port

(TAP) instruction and shifting data accordingly. Both of these steps are accom-

plished using the JTAG interface. To activate the TAP (see the OCI Activation sec-

tion on page 312), the TCK pin must be driven Low at least two CPU system clock

cycles prior to the deassertion of the RESET pin. Otherwise, the OCI-JTAG fea-

tures are disabled.

As per the IEEE 1149.1 specification, the boundary scan cells capture system I/O

on the rising edge of TCK during the CAPTURE_DR state. This captured data is

shifted on the rising edge of TCK while in the SHIFT_DR state. Pins and logic

receive shifted data only when enabled, and only on the falling edge of TCK dur-

ing the UPDATE_DR state, after shifting is completed.

®

Refer to the Application Note titled Using BSDL Files with eZ80 and

eZ80Acclaim!™ Devices (AN0114) on the ZiLOG website for more information

about eZ80F91 boundary scan support.

Boundary Scan Instructions

The eZ80F91 device’s boundary scan architecture supports the following instruc-

tions:

•

BYPASS (required)

SAMPLE (required)

EXTEST (required)

PRELOAD (required)

IDCODE (optional)

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Phase-Locked Loop

Overview

The Phase-Locked-Loop (PLL) is a programmable frequency multiplier that satis-

fies the equation SCLK (Hz) = N * F

in Figure 60.

(Hz). A diagram of the PLL block is shown

OSC

System Clock

(F

< SCLK < F

* N)

OSC

PLL_CTL1[0] = PLL Enable

SCLK-MUX

RTC_CLK

(1MHz < F

< 10MHz)

OSC

x2

Charge

Pump

Off-Chip

Loop Filter

Oscillator

PFD

VCO

x1

R_PLL

C_PLL1

PLL_CTL0[7:6]

Lock

Detect

C_PLL2

PLL_INT

Div N

PLL_CTL0[3:2]

{PLL_DIV_H, PLL_DIV_L}

Figure 60. Phase-Locked Loop Block Diagram

The seven main blocks of the PLL are:

•

Phase Frequency Detector

Charge Pump

Voltage Controlled Oscillator

Loop Filter

Divider

MUX/CLK Sync

Lock Detect

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Each of these blocks is described in this overview section.

Phase Frequency Detector

The Phase Frequency Detector (PFD) is a digital block. The 2 inputs are the refer-

ence clock (XTAL oscillator; see the On-Chip Oscillators section on page 342)

and the PLL divider output. The 2 outputs drive the internal charge pump and rep-

resent the error (or difference) between the falling edges of the PFD inputs.

Charge Pump

The Charge Pump is an analog block that is driven by 2 digital inputs from the

PFD that control its programmable current sources. The internal current source

contains four programmable values: 1.5mA, 1mA, 500µA, and 100µA. These val-

ues are selected by PLL_CTRL1[7:6]. The selected current drive is sinked/

sourced onto the loop-filter node according to the error (or difference) between

the falling edges of the PFD inputs. Ideally, when the PLL is locked, there are no

errors (error = 0) and no current is sourced/sinked onto the loop-filter node.

Voltage Controlled Oscillator

The Voltage Controlled Oscillator is an analog block that exhibits an output fre-

quency proportional to its input voltage. The VCO input is driven from the charge

pump and filtered via the off-chip loop filter.

Loop Filter

The Loop Filter comprises off-chip passive components (usually 1 resistor and 2

capacitors) that filter/integrate charge from the internal charge pump. The filtered

node also drives the VCO input, which creates a proportional frequency output.

When the PLL is not used, the Loop Filter pin should be a No Connect.

Divider

The Divider is a digital, programmable downcounter. The divider input is driven by

the VCO. The divider output drives the PFD. The function of the Divider is to

divide the frequency of its input signal by a programmable factor N and supply the

result in its output.

MUX/CLK Sync

The MUX/CLK Sync is a digital, software-controllable multiplexer that selects

between PLL or the XTAL oscillator as the system clock (SCLK). A PLL source

can only be selected after the PLL is locked (via the lock detect block) to allow

glitch-free clock switching.

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Lock Detect

The Lock Detect digital block analyzes the PFD output for a locked condition. The

PLL block of the eZ80F91 device is considered locked when the error (or differ-

ence) between the reference clock and divided-down VCO is less than the mini-

mum timing lock criteria for the number of consecutive reference clock cycles. The

lock criteria is selected in the PLL Control Register, PLL_CTL0[LDS_CTL]. When

the locked condition is met, this block outputs a logic High signal (lock) that can

interrupt the CPU.

PLL Normal Operation

By default (after system reset) the PLL is disabled and SCLK = XTAL oscillator.

Assuming the proper loop filter, supply voltages and external oscillator are cor-

rectly configured, the PLL can be enabled. The SCLK/Timer cannot choose the

PLL as its source until the PLL is locked, as determined by the lock detect block.

By forcing the PLL to be locked prior to enabling the PLL as a SCLK/Timer

source, it is assured to be stable and accurate.

The programming flow for normal PLL operation is shown in Figure 61.

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POR/System

Reset

Execute instructions with

SCLK = XTAL Oscillator

Program:

{PLL Divider}

PLL_DIV_L then PLL_DIV_H

{Charge Pump & Lock criteria}

PLL_CTL0

Enable:

{Interrupts & PLL}

PLL_CTL1

Upon Lock Interrupt:

Set SCLK MUX to PLL (PLL_CTL0)

Disable Lock Interrupt Mask

(PLL_CTL1)

Execute Application Code

Figure 61. Normal PLL Programming Flow

Power Requirement to the Phase-Locked Loop Function

Regardless of whether or not the developer chooses to use the PLL module block

as a clock source for the eZ80F91 device, the PLL_V (pin 87) must be con-

DD

nected to a V supply and the PLL_V (pin 84) must be connected to a V

DD

SS

supply for proper operation of the eZ80F91 using any system clock source.

PLL Registers

PLL Divider Control Register—Low and High Bytes

This register is designed such that the 11-bit divider value is loaded into the

divider module whenever the PLL_DIV_H register is written. Therefore, the proce-

dure should be to load the PLL_DIV_L register, followed by the PLL_DIV_H regis-

ter, for the divider to receive the appropriate value.

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The divider is designed such that any divider value less than 2 is ignored; a value

of 2 is used in its place.

The least-significant byte of PLL divider N is set via the corresponding bits in the

PLL_DIV_L register. See Tables 205 and 206.

The PLL divider register can only be written to when the PLL is disabled. A read-

back of the PLL Divider registers returns 0.

Note:

Table 205. PLL Divider Register—Low Bytes

(PLL_DIV_L = 005Ch)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

Note: W = Write only.

W

Bit

Position

Value

Description

[7:0]

PLL_DIV_L

00h–

FFh

These bits represent the Low byte of the 11-bit PLL divider

value. The complete PLL divider value is returned by

{PLL_DIV_H, PLL_DIV_L}.

Table 206. PLL Divider Register—High Bytes

(PLL_DIV_H = 005Dh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

W

Note: R = Read only; R/W = Read/Write.

Bit

Position

Value

Description

[7:3]

00h

Reserved

[2:0]

PLL_DIV_H

0h–7h These bits represent the High byte of the 11-bit PLL divider

value. The complete PLL divider value is returned by

{PLL_DIV_H, PLL_DIV_L}.

PS019209-0504

P R E L I M I N A R Y

Phase-Locked Loop

eZ80F91 MCU

Product Specification

325

PLL Control Register 0

The charge pump program, lock detect sensitivity, and system clock source selec-

tions can be set using this register. A brief description of each of these PLL Con-

trol Register 0 attributes is listed below, and further described in Table 207.

Charge Pump Program (CHRP_CTL). Selects one of four values of charge pump

current.

Lock Detect Sensitivity (LDS_CTL). Determines the lock criteria for the PLL.

System Clock Source (CLK_MUX). Selects the system clock source from a choice

of the external crystal oscillator (XTAL), PLL, or Real-Time Clock crystal oscillator.

Table 207. PLL Control Register 0

(PLL_CTL0 = 005Eh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R/W

R

R/W

Note: R = Read Only; R/W = Read/Write.

Bit

Position

Value Description

[7:6]

CHRP_CTL1

00

01

10

11

00

01

10

11

00

01

10

11

Charge pump current = 100µA.

Charge pump current = 500µA.

Charge pump current = 1.0mA.

Charge pump current = 1.5mA.

Reserved.

[5:4]

[3:2]

LDS_CTL1

Lock criteria—8 consecutive cycles of 20ns.

Lock criteria—16 consecutive cycles of 20ns.

Lock criteria—8 consecutive cycles of 400ns.

Lock criteria—16 consecutive cycles of 400ns.

[1:0]

CLK_MUX

System clock source is the external crystal oscillator.

2

System clock source is the PLL. .

System clock source is the Real-Time Clock crystal oscillator.

Reserved (previous select is preserved).

Notes:

1. Bits can only be programmed when the PLL is disabled. The PLL is disabled when PLL_CTL1

bit 0 is equal to 0.

2. PLL cannot be selected when disabled or out of lock.

PS019209-0504

P R E L I M I N A R Y

Phase-Locked Loop

eZ80F91 MCU

Product Specification

326

PLL Control Register 1

The PLL is enabled using this register. PLL lock-detect status, the PLL interrupt

signals and the PLL interrupt enables are accessed via this register. A brief

description of each of these PLL Control Register 1 attributes is listed below, and

further described in Table 208.

Lock Status (LCK_STATUS). The current lock bit out of the PLL is synchronized

and can be read via this bit.

Interrupt Lock (INT_LOCK). This signal feeds the interrupt line out of the CLKGEN

module and indicates that a rising edge on the lock signal out of the PLL has been

observed.

Interrupt Unlock (INT_UNLOCK). This signal feeds the interrupt line out of the clk-

gen module and indicates that a falling edge on the lock signal out of the PLL has

been observed.

Interrupt Lock Enable (INT_LOCK_EN). This signal enables the interrupt lock bit.

Interrupt Unlock Enable (INT_UNLOCK_EN). This signal enables the interrupt

unlock bit.

PLL Enable (PLL_ENABLE). Enables/disables the PLL.

.

Table 208. PLL Control Register 1

(PLL_CTL1 = 005Fh)

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

CPU Access

R

R/W

Note: R = Read Only; R/W = Read/Write.

Bit

Position

Value Description

[7:6]

00

0

Reserved

5

PLL is currently out of lock.

PLL is currently locked.

LCK_STATUS

1

4

0

Lock signal from PLL has not risen since last time register

was read.

INT_LOCK

1

Interrupt generated when PLL enters lock mode. Held until

register is read.

PS019209-0504

P R E L I M I N A R Y

Phase-Locked Loop

eZ80F91 MCU

Product Specification

327

Bit

Position

Value Description

3

0

1

0

Lock signal from PLL has not fallen since last time register

was read

INT_UNLOCK

Interrupt generated when PLL goes out of lock. Held until

register is read.

2

Interrupt generation for PLL locked condition (Bit 4) is

disabled.

INT_LOCK_EN

1

0

Interrupt generation for PLL locked condition is enabled.

1

Interrupt generation for PLL unlocked condition (Bit 3) is

disabled.

INT_UNLOCK_

EN

1

0

1

Interrupt generation for PLL unlocked condition is enabled.

1

0

PLL is disabled.

PLL_ENABLE

PLL is enabled.

Notes:

1. PLL cannot be disabled if the CLK_MUX bit of PLL_CTL0[1:0] is set to 01, because the PLL is

selected as the clock source.

PLL Characteristics

The operating and testing characteristics for the PLL are described in Table 209.

Not all conditions are tested in production test. The values in Table 209 are for

design and characterization only.

Note:

Table 209. PLL Characteristics

Symbol

Parameter

Test Condition

Min

Typ

Max Units

I_{OHCP_OUT}

High level output current for 3.0 < V_DD< 3.6

–0.86 –1.50 –2.13 mA

CP_OUT pin (programmed

value ±42%)

0.6 < PD_OUT < V_DD– 0.6

PLL_CTL0[7:6] = 11

I_{OLCP_OUT}

Low level output current for 3.0 < V_DD<3.6

0.86 1.50 2.13

mA

CP_OUT pin (programmed

value ±42%)

0.6 < PD_OUT < V_DD– 0.6

PLL_CTL0[7:6] = 11

I_{OHCP_OUT}

High level output current for 3.0 < V_DD<3.6

–0.42 –1.0 –1.42 mA

CP_OUT pin (programmed

value ±42%)

0.6 < PD_OUT < V_DD– 0.6

PLL_CTL0[7:6] = 10

PS019209-0504

P R E L I M I N A R Y

Phase-Locked Loop

eZ80F91 MCU

Product Specification

328

Table 209. PLL Characteristics (Continued)

Symbol

Parameter

Test Condition

Min

Typ

Max Units

I_{OLCP_OUT}

Low level output current for 3.0 < V_DD<3.6

0.42

1.0

1.42

mA

µA

%

CP_OUT pin (programmed

value ±42%)

0.6 < PD_OUT <V_DD– 0.6

PLL_CTL0[7:6] = 10

I_{OHCP_OUT}

I_{OLCP_OUT}

I_{OHCP_OUT}

I_{OLCP_OUT}

Match

High level output current for 3.0 < V_DD<3.6

–210 –500 –710

CP_OUT pin (programmed

value ±42%)

0.6 < PD_OUT <V_DD– 0.6

PLL_CTL0[7:6] = 01

Low level output current for 3.0 < V_DD<3.6

210

500

710

CP_OUT pin (programmed

value ±42%)

0.6 < PD_OUT <V_DD– 0.6

PLL_CTL0[7:6] = 01

High level output current for 3.0 < V_DD<3.6

–42 –100 –142

CP_OUT pin (programmed

value ±42%)

0.6 < PD_OUT <V_DD– 0.6

PLL_CTL0[7:6] = 00

Low level output current for 3.0 < V_DD<3.6

42

100

142

+15

CP_OUT pin (programmed

0.6 < PD_OUT <V_DD– 0.6

value ±42%)

PLL_CTL0[7:6] = 00

I_{OHCP_OUT}–I_{OLCP_OUT}

current match

3.0 < V_DD<3.6

0.6 < CP_OUT <V_DD– 0.6

PLL_CTL0[7:6] = XX

–15

I_{LCP_OUT}

Tristate leakage on CP_OUT CP_OUT tristated

output pin

–1

1

µA

F_OSC

F_VCO

Crystal oscillator frequency

VCO frequency

PLL_CTL0[5:4] = 01

1M

10M

Hz

Recommended operating

conditions

50

MHz

G_VCO

D1

VCO Gain

Recommended operating

conditions

36

45

120 MHz/

V

SCLK Duty Cycle from PLL Recommended operating

or XTALOSC source.

50

55

%

ps

s

conditions

T1A

PLL Clock Jitter

F_VCO= 50MHz. XTALOSC

= 10MHz

350

500

Lock2

PLL Lock-Time

F_VCO= 50MHz. XTALOSC

= 3.579MHz

C_PLL1= 220pF, R_PLL

=

499Ω, C_PLL2= 0.056µF

I_OH1

(XTL)

High-level Output Current for V_OH= V_DD–0.4V

XTAL2 pin PLL_CTL0[5:4] = 01

–0.3

0.6

mA

I_OL1

(XTL)

Low-level Output Current for V_OL= 0.4V

XTAL2 pin PLL_CTL0[5:4] = 01

PS019209-0504

P R E L I M I N A R Y

Phase-Locked Loop

eZ80F91 MCU

Product Specification

329

Table 209. PLL Characteristics (Continued)

Symbol

Parameter

High-level Output Current for V_OH= V_DD–0.4V

XTAL2 pin PLL_CTL0[5:4] = 11

Low-level Output Current for V_OL= 0.4V

Test Condition

Min

Typ

Max Units

I_OH2

(XTL)

mA

I_OL2

(XTL)

mA

V

XTAL2 pin

PLL_CTL0[5:4] = 11

F = 3.579MHz

OSC

V_PP3M

(XTL)

Peak-to-peak voltage under

oscillator conditions for

XTAL2 pin

Cx1 = 10pF

Cx2 = 10pF

V_PP10M

(XTL)

Peak-to-peak voltage under

oscillator conditions for

XTAL2 pin

F

= 10MHz

V

OSC

Cx1 = 10pF

Cx2 = 10pF

C_XTAL1

(package

type)

Capacitance measured from T = 25ºC

XTAL1 pin to GND

pF

C

Capacitance measured from T = 25ºC

XTAL2 pin to GND

XTAL2

(package

type)

C_LOOP

(package

type)

Capacitance measured from T = 25ºC

loop filter pin to GND

PS019209-0504

P R E L I M I N A R Y

Phase-Locked Loop

eZ80F91 MCU

Product Specification

330

eZ80^®CPU Instruction Set

Tables 210 through 219 indicate the CPU instructions available for use with the

eZ80F91 device. The instructions are grouped by class. More detailed information

is available in the eZ80 CPU User Manual (UM0077), available on zilog.com.

Table 210. Arithmetic Instructions

Mnemonic

ADC

ADD

CP

Instruction

Add with Carry

Add without Carry

Compare with Accumulator

Decimal Adjust Accumulator

Decrement

DAA

DEC

INC

Increment

MLT

Multiply

NEG

SBC

SUB

Negate Accumulator

Subtract with Carry

Subtract without Carry

Table 211. Bit Manipulation Instructions

Mnemonic

BIT

Instruction

Bit Test

RES

Reset Bit

Set Bit

SET

Table 212. Block Transfer and Compare Instructions

Mnemonic

CPD (CPDR)

CPI (CPIR)

Instruction

Compare and Decrement (with Repeat)

Compare and Increment (with Repeat)

®

PS019209-0504

P R E L I M I N A R Y

eZ80 CPU Instruction Set

eZ80F91 MCU

Product Specification

331

Table 212. Block Transfer and Compare Instructions

Mnemonic

LDD (LDDR)

LDI (LDIR)

Instruction

Load and Decrement (with Repeat)

Load and Increment (with Repeat)

Table 213. Exchange Instructions

Mnemonic

EX

Instruction

Exchange registers

EXX

Exchange CPU Multibyte register banks

Table 214. Input/Output Instructions

Mnemonic

IN

Instruction

Input from I/O

IN0

Input from I/O on Page 0

IND (INDR)

INDRX

Input from I/O and Decrement (with Repeat)

Input from I/O and Decrement Memory Address with Stationary

I/O Address

IND2 (IND2R)

INDM (INDMR)

INI (INIR)

Input from I/O and Decrement (with Repeat)

Input from I/O and Increment (with Repeat)

INIRX

Input from I/O and Increment Memory Address with Stationary

I/O Address

INI2 (INI2R)

INIM (INIMR)

OTDM (OTDMR)

OTDRX

Input from I/O and Increment (with Repeat)

Output to I/O and Decrement (with Repeat)

Output to I/O and Decrement Memory Address with Stationary

I/O Address

OTIM (OTIMR)

OTIRX

Output to I/O and Increment (with Repeat)

Output to I/O and Increment Memory Address with Stationary I/

O Address

OUT

Output to I/O

®

PS019209-0504

P R E L I M I N A R Y

eZ80 CPU Instruction Set

eZ80F91 MCU

Product Specification

332

Table 214. Input/Output Instructions

Mnemonic

Instruction

OUT0

Output to I/0 on Page 0

OUTD (OTDR)

OUTD2 (OTD2R)

OUTI (OTIR)

OUTI2 (OTI2R)

TSTIO

Output to I/O and Decrement (with Repeat)

Output to I/O and Increment (with Repeat)

Test I/O

Table 215. Load Instructions

Mnemonic

LD

Instruction

Load

LEA

Load Effective Address

PEA

Push Effective Address

POP

Pop

PUSH

Push

Table 216. Logical Instructions

Mnemonic

AND

Instruction

Logical AND

CPL

Complement Accumulator

Logical OR

OR

TST

Test Accumulator

Logical Exclusive OR

XOR

Table 217. Processor Control Instructions

Mnemonic

CCF

Instruction

Complement Carry Flag

Disable Interrupts

DI

®

PS019209-0504

P R E L I M I N A R Y

eZ80 CPU Instruction Set

eZ80F91 MCU

Product Specification

333

Table 217. Processor Control Instructions

Mnemonic

EI

Instruction

Enable Interrupts

Halt

HALT

IM

Interrupt Mode

No Operation

NOP

RSMIX

SCF

Reset Mixed-Memory Mode Flag

Set Carry Flag

Sleep

SLP

STMIX

Set Mixed-Memory Mode Flag

Table 218. Program Control Instructions

Mnemonic

CALL

CALL cc

DJNZ

JP

Instruction

Call Subroutine

Conditional Call Subroutine

Decrement and Jump if Nonzero

Jump

JP cc

JR

Conditional Jump

Jump Relative

JR cc

RET

Conditional Jump Relative

Return

RET cc

RETI

Conditional Return

Return from Interrupt

Return from Nonmaskable interrupt

Restart

RETN

RST

Table 219. Rotate and Shift Instructions

Mnemonic

RL

Instruction

Rotate Left

RLA

Rotate Left–Accumulator

®

PS019209-0504

P R E L I M I N A R Y

eZ80 CPU Instruction Set

eZ80F91 MCU

Product Specification

334

Table 219. Rotate and Shift Instructions

Mnemonic

RLC

Instruction

Rotate Left Circular

RLCA

RLD

Rotate Left Circular–Accumulator

Rotate Left Decimal

Rotate Right

RR

RRA

Rotate Right–Accumulator

Rotate Right Circular

Rotate Right Circular–Accumulator

Rotate Right Decimal

Shift Left Arithmetic

RRC

RRCA

RRD

SLA

SRA

Shift Right Arithmetic

Shift Right Logical

SRL

®

PS019209-0504

P R E L I M I N A R Y

eZ80 CPU Instruction Set

eZ80F91 MCU

Product Specification

335

Op-Code Map

®

Tables 220 through 226 indicate the hex values for each of the eZ80 instructions.

Table 220. Op Code Map—First Op Code

Legend

Lower Op Code Nibble

4

Upper

Op Code

Nibble

AND

A,H

Mnemonic

A

Second Operand

First Operand

0

Lower Nibble (Hex)

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

LD

(BC),A

INC

BC

INC

B

DEC

B

LD

B,n

EX

ADD

LD

DEC

BC

INC

C

DEC

C

LD

C,n

0

1

2

3

NOP

BC,

Mmn

LD

DE,

Mmn

LD

HL, (Mmn),

Mmn

LD

RLCA

RRCA

AF,AF’ HL,BC A,(BC)

DJNZ

d

LD

(DE),A

INC

DE

INC

D

DEC

D

LD

D,n

JR

d

ADD

HL,DE A,(DE)

LD

DEC

DE

INC

E

DEC

E

LD

E,n

RLA

DAA

SCF

RRA

CPL

LD

ADD

HL,HL

JR

NZ,d

INC

HL

INC

H

DEC

H

LD

H,n

JR

Z,d

DEC

HL

INC

L

DEC

L

LD

L,n

HL,

(Mmn)

LD

HL

LD

JR

NC,d

INC

SP

INC

(HL)

DEC

(HL) (HL),n

LD

JR

ADD

A,

DEC

SP

INC

A

DEC

A

LD

A,n

SP, (Mmn),

Mmn

CCF

LD

C,(HL) C,A

LD LD

E,(HL) E,A

LD LD

L,(HL) L,A

LD LD

CF,d HL,SP

A

(Mmn)

.SIS

suffix

LD

D,B

LD

H,B

LD

B,C

LD

D,C

LD

H,C

LD

B,E

LD

D,E

LD

H,E

LD

B,H

LD

D,H

LD

H,H

LD

B,L

LD

D,L

LD

H,L

LD

B,(HL)

LD

D,(HL) D,A

LD LD

LD

B,A

LD

C,B

LD

E,B

LD

L,B

LD

A,B

ADC

A,B

SBC

A,B

XOR

A,B

CP

.LIS

suffix

LD

E,C

LD

L,C

LD

A,C

ADC

A,C

SBC

A,C

XOR

A,C

CP

LD

C,D

LD

E,D

LD

L,D

LD

A,D

ADC

A,D

SBC

A,D

XOR

A,D

CP

A,D

JP

Z,

Mmn

LD

C,E

.LIL

suffix

LD

L,E

LD

A,E

ADC

A,E

SBC

A,E

XOR

A,E

CP

LD

C,H

LD

E,H

LD

L,H

LD

C,L

LD

E,L

LD

L,L

LD

A,L

ADC

A,L

SBC

A,L

XOR

A,L

CP

LD

4

5

6

7

8

9

A

B

B,D

.SIL

suffix

LD

H,D

LD

H,(HL) H,A

LD

(HL),A

ADD

A,A

SUB

A,A

AND

A,A

OR

HALT

(HL),B (HL),C (HL),D (HL),E (HL),H (HL),L

ADD

A,B

SUB

A,B

AND

A,B

A,H

ADC

A,H

SBC

A,H

XOR

A,H

CP

A,H

CALL

Z,

Mmn

CALL

CF,

Mmn

CALL

PE,

Mmn

CALL

M,

A,(HL) A,A

ADC ADC

A,(HL) A,A

ADD

A,C

SUB

A,C

AND

A,C

OR

ADD

A,D

SUB

A,D

AND

A,D

OR

ADD

A,E

SUB

A,E

AND

A,E

OR

ADD

A,H

SUB

A,H

AND

A,H

OR

A,H

CALL

NZ,

Mmn

CALL

NC,

Mmn

CALL

PO,

ADD

A,L

SUB

A,L

AND

A,L

OR

ADD

A,(HL)

SUB

A,(HL)

AND

A,(HL)

OR

A,(HL)

SBC

A,(HL) A,A

XOR XOR

A,(HL) A,A

OR

A,B

CP

A,C

A,D

JP

A,E

A,L

A,A

A,B

A,C

A,E

A,L

A,(HL) A,A

RET

NZ

POP

BC

JP

Mmn

PUSH ADD

BC A,n

RST

00h

RET

Z

Table

221

CALL ADC

Mmn

RST

08h

C

D

E

F

NZ,

Mmn

JP

NC,

Mmn

JP

PO,

Mmn

JP

RET

EXX

A,n

JP

RET

NC

POP

DE

OUT

(n),A

PUSH SUB

DE A,n

RST

10h

RET

CF

IN

A,(n)

Table

222

SBC

A,n

RST

18h

CF,

Mmn

JP

PE,

Mmn

JP

RET

PO

POP

HL

EX

(SP),HL

PUSH AND

HL

RST

20h

RET

PE

JP

(HL)

EX

DE,HL

Table

223

XOR

A,n

RST

28h

A,n

Mmn

CALL

P,

RET

P

POP

AF

PUSH

AF

OR

A,n

RST

30h

RET

M

LD

SP,HL

Table

224

CP

A,n

RST

38h

P,

Mmn

DI

M,

Mmn

EI

Mmn

Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.

PS019209-0504

P R E L I M I N A R Y

Op-Code Map

eZ80F91 MCU

Product Specification

336

Table 221. Op Code Map—Second Op Code after 0CBh

Legend

Lower Nibble of 2nd Op Code

Upper

Nibble

of Second

Op Code

4

RES

4,H

Mnemonic

A

First Operand

0

Second Operand

Lower Nibble (Hex)

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

RLC

B

RLC

C

RLC

D

RLC

E

RLC

H

RLC

L

RLC

(HL)

RLC

A

RRC

B

RRC

C

RRC

D

RRC

E

RRC

H

RRC

L

RRC

(HL)

RRC

A

0

RL

B

RL

C

RL

D

RL

E

RL

H

RL

L

RL

(HL)

RL

A

RR

B

RR

C

RR

D

RR

E

RR

H

RR

L

RR

(HL)

RR

A

1

SLA

B

SLA

C

SLA

D

SLA

E

SLA

H

SLA

L

SLA

(HL)

SLA

A

SRA

B

SRA

C

SRA

D

SRA

E

SRA

H

SRA

L

SRA

(HL)

SRA

A

2

SRL

B

SRL

C

SRL

D

SRL

E

SRL

H

SRL

L

SRL

(HL)

SRL

A

3

BIT

0,B

BIT

0,C

BIT

0,D

BIT

0,E

BIT

0,H

BIT

0,L

BIT

0,(HL)

BIT

0,A

BIT

1,B

BIT

1,C

BIT

1,D

BIT

1,E

BIT

1,H

BIT

1,L

BIT

1,(HL)

BIT

1,A

4

BIT

2,B

BIT

2,C

BIT

2,D

BIT

2,E

BIT

2,H

BIT

2,L

BIT

2,(HL)

BIT

2,A

BIT

3,B

BIT

3,C

BIT

3,D

BIT

3,E

BIT

3,H

BIT

3,L

BIT

3,(HL)

BIT

3,A

5

BIT

4,B

BIT

4,C

BIT

4,D

BIT

4,E

BIT

4,H

BIT

4,L

BIT

4,(HL)

BIT

4,A

BIT

5,B

BIT

5,C

BIT

5,D

BIT

5,E

BIT

5,H

BIT

5,L

BIT

5,(HL)

BIT

5,A

6

BIT

6,B

BIT

6,C

BIT

6,D

BIT

6,E

BIT

6,H

BIT

6,L

BIT

6,(HL)

BIT

6,A

BIT

7,B

BIT

7,C

BIT

7,D

BIT

7,E

BIT

7,H

BIT

7,L

BIT

7,(HL)

BIT

7,A

7

RES

0,B

RES

0,C

RES

0,D

RES

0,E

RES

0,H

RES

0,L

RES

0,(HL)

RES

0,A

RES

1,B

RES

1,C

RES

1,D

RES

1,E

RES

1,H

RES

1,L

RES

1,(HL)

RES

1,A

8

RES

2,B

RES

2,C

RES

2,D

RES

2,E

RES

2,H

RES

2,L

RES

2,(HL)

RES

2,A

RES

3,B

RES

3,C

RES

3,D

RES

3,E

RES

3,H

RES

3,L

RES

3,(HL)

RES

3,A

9

RES

4,B

RES

4,C

RES

4,D

RES

4,E

RES

4,H

RES

4,L

RES

4,(HL)

RES

4,A

RES

5,B

RES

5,C

RES

5,D

RES

5,E

RES

5,H

RES

5,L

RES

5,(HL)

RES

5,A

A

RES

6,B

RES

6,C

RES

6,D

RES

6,E

RES

6,H

RES

6,L

RES

6,(HL)

RES

6,A

RES

7,B

RES

7,C

RES

7,D

RES

7,E

RES

7,H

RES

7,L

RES

7,(HL)

RES

7,A

B

SET

0,B

SET

0,C

SET

0,D

SET

0,E

SET

0,H

SET

0,L

SET

0,(HL)

SET

0,A

SET

1,B

SET

1,C

SET

1,D

SET

1,E

SET

1,H

SET

1,L

SET

1,(HL)

SET

1,A

C

SET

2,B

SET

2,C

SET

2,D

SET

2,E

SET

2,H

SET

2,L

SET

2,(HL)

SET

2,A

SET

3,B

SET

3,C

SET

3,D

SET

3,E

SET

3,H

SET

3,L

SET

3,(HL)

SET

3,A

D

SET

4,B

SET

4,C

SET

4,D

SET

4,E

SET

4,H

SET

4,L

SET

4,(HL)

SET

4,A

SET

5,B

SET

5,C

SET

5,D

SET

5,E

SET

5,H

SET

5,L

SET

5,(HL)

SET

5,A

E

SET

6,B

SET

6,C

SET

6,D

SET

6,E

SET

6,H

SET

6,L

SET

6,(HL)

SET

6,A

SET

7,B

SET

7,C

SET

7,D

SET

7,E

SET

7,H

SET

7,L

SET

7,(HL)

SET

7,A

F

Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.

PS019209-0504

P R E L I M I N A R Y

Op-Code Map

eZ80F91 MCU

Product Specification

337

Table 222. Op Code Map—Second Op Code After 0DDh

Legend

Lower Nibble of 2nd Op Code

Upper

9

LD

SP,IX

Nibble

of Second

Op Code

Mnemonic

F

Second Operand

First Operand

Lower Nibble (Hex)

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

LD

(IX+d),

BC

LD BC,

(IX+d)

ADD

IX,BC

0

LD

(IX+d),

DE

LD DE,

(IX+d)

ADD

IX,DE

1

2

3

LD

IX,

Mmn

LD

(Mmn),

IX

LD

IX,

(Mmn)

LD

(IX+d),

HL

INC

IX

INC

IXH

DEC

IXH

LD

LD HL,

ADD

IX,IX

DEC

IX

INC

IXL

DEC

IXL

LD

IXL,n

IXH,n (IX+d)

LD

LD IY,

(IX+d)

INC

DEC LD (IX LD IX,

ADD

IX,SP

(IX+d), (IX+d),

(IX+d) (IX+d) +d),n (IX+d)

IY

IX

LD LD LD B,

LD

LD C,

4

5

B,IXH B,IXL (IX+d)

LD LD LD D,

D,IXH D,IXL (IX+d)

LD LD LD H,

C,IXH C,IXL (IX+d)

LD LD LD E,

E,IXH E,IXL (IX+d)

LD LD LD L,

LD

6

LD

IXH,B IXH,C IXH,D IXH,E IXH,IXH IXH,IXL (IX+d) IXH,A IXL,B IXL,C IXL,D IXL,E IXL,IXH IXL,IXL (IX+d) IXL,A

LD

(IX+d),A

LD

A,IXH A,IXL (IX+d)

ADC ADC ADC A,

A,IXH A,IXL (IX+d)

SBC SBC SBC A,

A,IXH A,IXL (IX+d)

XOR XOR XOR A,

A,IXH A,IXL (IX+d)

CP CP CP A,

A,IXH A,IXL (IX+d)

LD

LD A,

7

8

(IX+d),B(IX+d),C(IX+d),D(IX+d),E(IX+d),H (IX+d),L

ADD

ADD ADD A,

A,IXH A,IXL (IX+d)

SUB

A,IXH A,IXL (IX+d)

AND AND AND A,

A,IXH A,IXL (IX+d)

OR OR OR A,

SUB SUB A,

9

A

B

C

D

E

F

A,IXH A,IXL (IX+d)

Table

225

POP

IX

EX

(SP),IX

PUSH

IX

JP

(IX)

LD

SP,IX

Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.

PS019209-0504

P R E L I M I N A R Y

Op-Code Map

eZ80F91 MCU

Product Specification

338

Table 223. Op Code Map—Second Op Code After 0EDh

Legend

Lower Nibble of 2nd Op Code

Upper

2

Nibble

of Second

Op Code

SBC

HL,BC

Mnemonic

4

First Operand

Second Operand

Lower Nibble (Hex)

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

LEA

BC,

IX+d

LEA

DE,

LEA

BC,

IY+d

LEA

DE,

LD

(HL),

BC

IN0

B,(n)

OUT0

(n),B

TST

A,B

LD BC, IN0

(HL) C,(n)

OUT0

(n),C

TST

A,C

0

1

2

3

4

5

6

7

IN0

D,(n)

OUT0

(n),D

TST

A,D

LD DE, IN0

(HL) E,(n)

OUT0

(n),E

TST

A,E

LD(HL),

DE

IX+d

IY+d

LD

(HL),

HL

LD

(HL),

IX

IN0

H,(n)

OUT0 LEA HL LEA HL TST

(n),H ,IX+d ,IY+d A,H

LD HL, IN0

OUT0

(n),L

TST

A,L

(HL)

L,(n)

LD IY, LEA IX LEA IY TST

LD IX,

(HL)

IN0

A,(n)

OUT0

(n),A

TST

A,A

LD

(HL),IY

(HL)

,IX+d ,IY+d A,(HL)

LD

BC,

(Mmn)

LD

DE,

(Mmn)

LD

HL,

(Mmn)

IN

OUT

SBC

LD

I,A

IN

OUT

ADC

MLT

BC

LD

R,A

(Mmn), NEG RETN IM 0

BC

LD

(Mmn),

DE

LD

(Mmn),

HL

LD

(Mmn),

SP

RETI

LD

B,(BC) (BC),B HL,BC

C,(C) (C),C HL,BC

IN

OUT

SBC

LEA IX, LEA IY,

IY+d

LD

A,I

IN

OUT

ADC

MLT

DE

LD

A,R

IM 1

IM 2

LD

D,(BC) (BC),D HL,DE

IX+d

E,(C) (C),E HL,DE

IBN

OUT

SBC

TST

A,n

PEA

IX+d

PEA

IY+d

IN

L,(C)

OUT

(C),L HL,HL

ADC

MLT

HL

RRD

RLD

H,(C) (BC),H HL,HL

MB,A A,MB

LD

SP,

(Mmn)

SBC

HL,SP

TSTIO

n

IN

OUT

ADC

MLT

SP

SLP

STMIX RSMIX

A,(C) (C),A HL,SP

8

9

INIM OTIM

INI2

INDM OTDM IND2

INDMR OTDMR IND2R

IND OUTD OUTD2

INIMR OTIMR INI2R

A

B

C

D

E

F

LDI

CPI

INI

OUTI OUTI2

OTIR OTI2R

LDD

CPD

LDIR CPIR

INIR

LDDR CPDR INDR OTDR OTD2R

INDRX OTDRX

LD

I,HL

INIRX OTIRX

LD

HL,I

Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.

PS019209-0504

P R E L I M I N A R Y

Op-Code Map

eZ80F91 MCU

Product Specification

339

Table 224. Op Code Map—Second Op Code After 0FDh

Legend

Lower Nibble of 2nd Op Code

Upper

9

Nibble

of Second

Op Code

LD

SP,IY

Mnemonic

F

First Operand

Second Operand

Lower Nibble (Hex)

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

LD BC,

(IY+d)

ADD

IY,BC

LD (IY

+d),BC

0

LD DE,

(IY+d)

ADD

IY,DE

LD (IY

+d),DE

1

2

LD

(Mmn),I

Y

LD

IY,

(Mmn)

LD

IY,Mmn

INC

IY

INC

IYH

DEC

IYH

LD

LD HL,

IYH,n (IY+d)

ADD

IY,IY

DEC

IY

INC

IYL

DEC

IYL

LD

LD (IY

IYL,n +d),HL

LD IX,

(IY+d)

INC

DEC LD (IY LD IY,

ADD

IY,SP

LD (IY LD (IY

+d),IX +d),IY

3

4

(IY+d) (IY+d) +d),n (IY+d)

LD LD LD B,

B,IYH B,IYL (IY+d)

LD LD LD D,

D,IYH D,IYL (IY+d)

LD LD LD H,

LD

LD C,

C,IYH C,IYL (IY+d)

LD LD LD E,

E,IYH E,IYL (IY+d)

LD LD LD L,

5

LD

6

IYH,B IYH,C IYH,D IYH,E IYH,IYH IYH,IYL (IY+d) IYH,A IYL,B IYL,C IYL,D IYL,E IYL,IYH IYL,IYL (IY+d) IYL,A

LD (IY LD (IY LD (IY LD (IY LD (IY LD (IY

+d),B +d),C +d),D +d),E +d),H +d),L

LD (IY

+d),A

LD

A,IYH A,IYL (IY+d)

ADC ADC ADC A,

A,IYH A,IYL (IY+d)

SBC SBC SBC A,

A,IYH A,IYL (IY+d)

XOR XOR XOR A,

A,IYH A,IYL (IY+d)

CP CP CP A,

A,IYH A,IYL (IY+d)

LD

LD A,

7

ADD

ADD ADD A,

8

A,IYH A,IYL (IY+d)

SUB

A,IYH A,IYL (IY+d)

AND AND AND A,

A,IYH A,IYL (IY+d)

OR OR OR A,

SUB SUB A,

9

A

B

C

D

E

F

A,IYH A,IYL (IY+d)

Table

226

POP

IY

EX

(SP),IY

PUSH

IY

JP

(IY)

LD

SP,IY

Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.

PS019209-0504

P R E L I M I N A R Y

Op-Code Map

eZ80F91 MCU

Product Specification

340

Table 225. Op Code Map—Fourth Byte After 0DDh, 0CBh, and dd

Legend

Lower Nibble of 4th Byte

Upper

Nibble

of Fourth

Byte

6

BIT

0,(IX+d)

Mnemonic

4

First Operand

Second Operand

Lower Nibble (Hex)

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

RLC

(IX+d)

RRC

(IX+d)

0

RL

(IX+d)

RR

(IX+d)

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

SLA

(IX+d)

SRA

(IX+d)

SRL

(IX+d)

BIT 0,

(IX+d)

BIT 1,

(IX+d)

BIT 2,

(IX+d)

BIT 3,

(IX+d)

BIT 4,

(IX+d)

BIT 5,

(IX+d)

BIT 6,

(IX+d)

BIT 7,

(IX+d)

RES 0,

(IX+d)

RES 1,

(IX+d)

RES 2,

(IX+d)

RES 3,

(IX+d)

RES 4,

(IX+d)

RES 5,

(IX+d)

RES 6,

(IX+d)

RES 7,

(IX+d)

SET 0,

(IX+d)

SET 1,

(IX+d)

SET 2,

(IX+d)

SET 3,

(IX+d)

SET 4,

(IX+d)

SET 5,

(IX+d)

SET 6,

(IX+d)

SET 7,

(IX+d)

Notes: d = 8-bit two’s-complement displacement.

PS019209-0504

P R E L I M I N A R Y

Op-Code Map

eZ80F91 MCU

Product Specification

341

Table 226. Op Code Map—Fourth Byte After 0FDh, 0CBh, and dd*

Legend

Lower Nibble of 4th Byte

Upper

Nibble

of Fourth

Byte

6

BIT

0,(IY+d)

Mnemonic

4

1

First Operand

Second Operand

Lower Nibble (Hex)

0

2

3

4

5

6

7

8

9

A

B

C

D

E

F

RLC

(IY+d)

RRC

(IY+d)

0

RL

(IY+d)

RR

(IY+d)

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

SLA

(IY+d)

SRA

(IY+d)

SRL

(IY+d)

BIT 0,

(IY+d)

BIT 1,

(IY+d)

BIT 2,

(IY+d)

BIT 3,

(IY+d)

BIT 4,

(IY+d)

BIT 5,

(IY+d)

BIT 6,

(IY+d)

BIT 7,

(IY+d)

RES 0,

(IY+d)

RES 1,

(IY+d)

RES 2,

(IY+d)

RES 3,

(IY+d)

RES 4,

(IY+d)

RES 5,

(IY+d)

RES 6,

(IY+d)

RES 7,

(IY+d)

SET 0,

(IY+d)

SET 1,

(IY+d)

SET 2,

(IY+d)

SET 3,

(IY+d)

SET 4,

(IY+d)

SET 5,

(IY+d)

SET 6,

(IY+d)

SET 7,

(IY+d)

Notes: d = 8-bit two’s-complement displacement.

PS019209-0504

P R E L I M I N A R Y

Op-Code Map

eZ80F91 MCU

Product Specification

342

On-Chip Oscillators

The eZ80F91 features two on-chip oscillators for use with an external crystal. The

primary oscillator generates the system clock for the internal CPU and the major-

ity of the on-chip peripherals. Alternatively, the X input pin can also accept a

IN

CMOS-level clock input signal. If an external clock generator is used, the X

OUT

pin should be left unconnected. The secondary oscillator can drive a 32KHz crys-

tal to generate the time-base for the Real-Time Clock.

Primary Crystal Oscillator Operation

Figure 62 illustrates a recommended configuration for connection with an external

rd

50MHz, 3 -overtone, parallel-resonant crystal. Recommended crystal specifica-

tions are provided in Tables 227 and 228. Printed circuit board layout should add

no more than 4pF of stray capacitance to either the X or X

pins. If oscillation

IN

OUT

does not occur, the user should try removing C1 for testing and decreasing the

value of C by the estimated stray capacitance to decrease loading.

2

On-Chip Oscillator

X_IN

X_OUT

50 MHz Crystal

(Third Overtone)

R = 100 KΩ

C₁= 5 pF

C₂= 10-15 pF

L = 33 µH ( 10%)

C₃= .01-0.1 µF

Figure 62. Recommended Crystal Oscillator Configuration—50MHz Operation

PS019209-0504

P R E L I M I N A R Y

On-Chip Oscillators

eZ80F91 MCU

Product Specification

343

Table 227. Recommended Crystal Oscillator Specifications—1MHz Operation

Frequency

Parameter

Frequency

Resonance

Mode

Dependent Value

Units

Comments

1

MHz

Parallel

Fundamental

Series Resistance (R )

750

13

7

Ohms

pF

Maximum

S

Load Capacitance (C )

L

Shunt Capacitance (C )

pF

0

Drive Level

1

mW

Table 228. Recommended Crystal Oscillator Specifications—10MHz Operation

Frequency

Parameter

Frequency

Resonance

Mode

Dependent Value

Units

Comments

10

MHz

Parallel

Fundamental

Series Resistance (R )

35

30

7

Ohms

pF

Maximum

S

Load Capacitance (C )

L

Shunt Capacitance (C )

pF

0

Drive Level

1

mW

32KHz Real-Time Clock Crystal Oscillator Operation

Figure 63 illustrates a recommended configuration for connecting the Real-Time

Clock oscillator with an external 32KHz, fundamental-mode, parallel-resonant

crystal. The recommended crystal specifications are provided in Table 229. A

printed circuit board layout should add no more than 4pF of stray capacitance to

either the RTC_X or RTC_X

pins. If oscillation does not occur, reduce the

IN

OUT

values of capacitors C and C to decrease loading.

1

2

An on-chip MOS resistor sets the crystal drive current limit. This configuration

does not require an external bias resistor across the crystal. An on-chip MOS

resistor provides the biasing.

PS019209-0504

P R E L I M I N A R Y

On-Chip Oscillators

eZ80F91 MCU

Product Specification

344

On-Chip Oscillator

RTC_X_IN

RTC_X_OUT

32 kHz Crystal

(Fundamental Mode)

C₁= 10 pF

C₂= 10 pF

Figure 63. Recommended Crystal Oscillator Configuration—32KHz Operation

Table 229. Recommended Crystal Oscillator Specifications—32KHz Operation

Parameter

Frequency

Resonance

Mode

Value

Units

Comments

32

KHz

32768 Hz

Parallel

Fundamental

Series Resistance (R )

40

12.5

3

kΩ

pF

µW

Maximum

S

Load Capacitance (C )

L

Shunt Capacitance (C )

0

Drive Level

1

PS019209-0504

P R E L I M I N A R Y

On-Chip Oscillators

eZ80F91 MCU

Product Specification

345

Electrical Characteristics

Absolute Maximum Ratings

Stresses greater than those listed in Table 230 can cause permanent damage to

the device. These ratings are stress ratings only. Operation of the device at any

condition outside those indicated in the operational sections of these specifica-

tions is not implied. Exposure to absolute maximum rating conditions for extended

periods can affect device reliability. For improved reliability, unused inputs should

be tied to one of the supply voltages (V_DDor V_SS).

Table 230. Absolute Maximum Ratings

Parameter

Min

–40

–65

–0.3

Max

+105

+150

+5.5

+3.6

830

Units

ºC

Notes

Ambient temperature under bias (ºC)

Storage temperature (ºC)

1

C

Voltage on any pin with respect to V_SS

Voltage on V_DDpin with respect to V_SS

Total power dissipation

V

2

V

mW

mA

µA

mA

Maximum current out of V_SS

230

Maximum current into V_DD

230

Maximum current on input and/or inactive output pin

Maximum output current from active output pin

–15

–8

+15

+8

Notes:

1. Operating temperature is specified in DC Characteristics.

2. This voltage applies to all pins except where noted otherwise.

PS019209-0504

P R E L I M I N A R Y

Electrical Characteristics

eZ80F91 MCU

Product Specification

346

DC Characteristics

Table 231 lists the DC characteristics of the eZ80F91 device.

All data is preliminary and subject to change following completion of production

characterization.

Note:

Table 231. DC Characteristics

T =

A

0ºC to 70ºC

–40ºC to 105ºC

Symbol

Parameter

Min

Max

Min

Max

Units Conditions

Supply Voltage

3.0

3.6

3.0

3.6

V

DD

Low Level

Input Voltage

–0.3

0.3 x V

–0.3

0.3 x V

V

DD

IL

High Level

Input Voltage

0.7xV

5.5

0.7xV

5.5

V

DD

IH

Low Level

Output Voltage

0.4

V

V_DD= 3.0V;

I = 1mA

OL

OH

RTC

High Level

Output Voltage

2.4

2.0

2.4

2.0

V_DD= 3.0V;

I = –1mA

OH

RTC Supply

Voltage

3.6

+10

3.6

+10

µ

Input Leakage

Current

–10

A

V_DD= 3.6V;

V = V_DDor V_SS

IN

1

I

IL

µ

Tristate Leakage

Current

V_DD= 3.6V

I

TL

Active Current

230

120

mA

CCa

HALT Mode

Current

I

CCh

CCs

RTC

µ

SLEEP Mode

Current

850

10

A

RTC Supply

Current

2.5

Typical

10

2.5

Typical

Supply current into

V

RTC

1

Note: This condition excludes all pins with on-chip pull-ups when driven Low.

PS019209-0504

P R E L I M I N A R Y

Electrical Characteristics

eZ80F91 MCU

Product Specification

347

POR and VBO Electrical Characteristics

Table 232 lists the Power-On Reset and Voltage Brown-Out characteristics of the

eZ80F91 device.

Table 232. POR and VBO Electrical Characteristics

T = –40ºC to 105ºC

A

Symbol Parameter

Min

2.45

Typ

2.77

Max

2.90

Unit Conditions

V

VBO Voltage Threshold

POR Voltage Threshold

POR/VBO Hysteresis

V

= V

VBO

CC

VBO

POR

2.55

55

2.70

75

2.95

95

.

POR

mV

µs

HYST

T

POR/VBO analog RESET duration 40

VBO pulse reject period

100

ANA

10

40

µs

VBO_MIN

POR_VBO

I

POR/VBO DC current consumption

50

µA

V/ms

VCC

V_CCramp rate requirements to

guarantee proper RESET occurs

0.1

100

RAMP

Flash Memory Characteristics

Table 233 lists the Flash memory characteristics of the eZ80F91 device.

Table 233. Flash Memory Electrical Characteristics and Timing

V

= 3.0 to 3.6V; T = –40ºC to 105ºC

DD

A

Symbol

Minimum

Typical

—

Maximum

Units

ns

Notes

Flash Byte Read Time

Flash Byte Program Time

Flash Page Erase Time

Flash Mass Erase Time

Writes to Single Address

Flash Row Program Time

Data Retention

60

65

—

85

—

ns

—

10

ms

2KB

—

200

—

2

Before Next Erase

ROW mode

25ºC

—

13.4

—

ms

100

10,000

—

years

cycles

Endurance

—

PS019209-0504

P R E L I M I N A R Y

Electrical Characteristics

eZ80F91 MCU

Product Specification

348

AC Characteristics

The section provides information about the AC characteristics and timing of the

eZ80F91 device. All AC timing information assumes a standard load of 50pF on

all outputs. See Table 234.

All data is preliminary and subject to change following completion of production

characterization.

Note:

Table 234. AC Characteristics

T =

A

0ºC to 70ºC

–40ºC to 105ºC

Symbol Parameter

Min

Max

Min

Max

Units

Conditions

T

System Clock

Cycle Time

20

1000

20

1000 ns

V_DD= 3.0 – 3.6V

XIN

System Clock

High Time

8

ns

V_DD= 3.0 – 3.6V;

XINH

XINL

XINR

XINF

T

= 20ns

CLK

System Clock

Low Time

8

V_DD= 3.0 – 3.6V;

= 20ns

T

CLK

System Clock

Rise Time

3

ns

pF

V_DD= 3.0 – 3.6V;

= 20ns

T

CLK

System Clock

Fall Time

V_DD= 3.0 – 3.6V;

= 20ns

T

CLK

C

Input capacitance

10 typical

Pad library

simulation

IN

Table 235 shows simulated inductance, capacitance, and resistance results for

the 144-pin LQFP package at 100MHz operating frequency.

Table 235. Typical 144-LQFP Package Electrical Characteristics*

Lead

Inductance (nH)

6.430

Capacitance (pF)

1.100

Resistance (mΩ)

Longest

Shortest

62.9

52.6

4.230

1.070

Note: *Package vendor-supplied; 100MHz operating frequency.

PS019209-0504

P R E L I M I N A R Y

Electrical Characteristics

eZ80F91 MCU

Product Specification

349

External Memory Read Timing

Figure 64 and Table 236 diagram the timing for external memory reads.

T_CLK

PHI

T₁

T₂

ADDR[23:0]

T₃

T₄

DATA[7:0]

(input)

T₅

T₈

CSx

T₇

T₉

T₈

MREQ

RD

T₁₀

Figure 64. External Memory Read Timing

Table 236. External Memory Read Timing

Delay (ns)

Parameter Abbreviation

Min.

Max.

6.8

—

T

PHI Clock Rise to ADDR Valid Delay

PHI Clock Rise to ADDR Hold Time

—

1

2

3

4

5

6

7

8

2.2

0.2

0.9

2.6

2.4

2.6

2.3

Input DATA Valid to PHI Clock Rise Setup Time

PHI Clock Rise to DATA Hold Time

—

PHI Clock Rise to CSx Assertion Delay

PHI Clock Rise to CSx Deassertion Delay

PHI Clock Rise to MREQ Assertion Delay

PHI Clock Rise to MREQ Deassertion Delay

10.8

8.8

7.0

6.3

PS019209-0504

P R E L I M I N A R Y

Electrical Characteristics

eZ80F91 MCU

Product Specification

350

Table 236. External Memory Read Timing (Continued)

Parameter Abbreviation

Delay (ns)

Min.

2.7

Max.

7.0

T

PHI Clock Rise to RD Assertion Delay

PHI Clock Rise to RD Deassertion Delay

9

2.4

6.3

10

External Memory Write Timing

Figure 65 and Table 237 diagram the timing for external memory Writes.

T_CLK

PHI

T₂

T₄

T₁

ADDR[23:0]

T₃

DATA[7:0]

(output)

T₅

T₆

CSx

T₇

T₈

MREQ

WR

T₉

T₁₀

Figure 65. External Memory Write Timing

PS019209-0504

P R E L I M I N A R Y

Electrical Characteristics

eZ80F91 MCU

Product Specification

351

Table 237. External Memory Write Timing

Parameter Abbreviation

Delay (ns)

Min.

Max.

6.8

T

PHI Clock Rise to ADDR Valid Delay

PHI Clock Rise to ADDR Hold Time

PHI Clock Fall to Output DATA Valid Delay

PHI Clock Rise to DATA Hold Time

PHI Clock Rise to CSx Assertion Delay

PHI Clock Rise to CSx Deassertion Delay

PHI Clock Rise to MREQ Assertion Delay

PHI Clock Rise to MREQ Deassertion Delay

PHI Clock Fall to WR Assertion Delay

PHI Clock Rise to WR Deassertion Delay*

WR Deassertion to ADDR Hold Time

WR Deassertion to DATA Hold Time

WR Deassertion to CSx Hold Time

—

1

2

3

4

5

6

7

8

9

10

2.2

—

7.5

—

2.3

2.6

2.4

2.6

2.3

1.8

1.6

0.4

0.5

1.2

0.5

10.8

8.8

7.0

6.3

4.5

4.4

—

WR Deassertion to MREQ Hold Time

—

* At the conclusion of a Write cycle, deassertion of WR always occurs before any

change to ADDR, DATA, CSx, or MREQ.

PS019209-0504

P R E L I M I N A R Y

Electrical Characteristics

eZ80F91 MCU

Product Specification

352

External I/O Read Timing

Figure 66 and Table 238 diagram the timing for external I/O reads. PHI clock rise/

fall to signal transition timing is independent of the particular bus mode employed

(eZ80, Z80, Intel, or Motorola).

T_CLK

PHI

T₁

T₂

ADDR[23:0]

T₃

T₄

DATA[7:0]

(input)

T₅

T₈

CSx

T₇

T₉

T₈

IORQ

T₁₀

RD

Figure 66. External I/O Read Timing

Table 238. External I/O Read Timing

Delay (ns)

Min Max

Parameter Abbreviation

T

PHI Clock Rise to ADDR Valid Delay

PHI Clock Rise to ADDR Hold Time

—

6.8

—

1

2

3

4

5

6

7

2.2

0.2

0.9

2.6

2.4

2.6

Input DATA Valid to PHI Clock Rise Setup Time

PHI Clock Rise to DATA Hold Time

—

PHI Clock Rise to CSx Assertion Delay

PHI Clock Rise to CSx Deassertion Delay

PHI Clock Rise to IORQ Assertion Delay

10.8

8.8

7.0

PS019209-0504

P R E L I M I N A R Y

Electrical Characteristics

eZ80F91 MCU

Product Specification

353

Table 238. External I/O Read Timing (Continued)

Parameter Abbreviation

Delay (ns)

Min

2.3

Max

6.3

T

PHI Clock Rise to IORQ Deassertion Delay

PHI Clock Rise to RD Assertion Delay

PHI Clock Rise to RD Deassertion Delay

8

2.7

2.4

7.0

6.3

9

10

External I/O Write Timing

Figure 67 and Table 239 diagram the timing for external I/O Writes. PHI clock rise/

fall to signal transition timing is independent of the particular bus mode employed

(eZ80, Z80, Intel, or Motorola).

T_CLK

PHI

T₂

T₄

T₁

ADDR[23:0]

T₃

DATA[7:0]

(output)

T₅

T₆

CSx

T₇

T₈

IORQ

WR

T₉

T₁₀

Figure 67. External I/O Write Timing

PS019209-0504

P R E L I M I N A R Y

Electrical Characteristics

eZ80F91 MCU

Product Specification

354

Table 239. External I/O Write Timing

Parameter Abbreviation

Delay (ns)

Min

—

Max

6.8

—

T

PHI Clock Rise to ADDR Valid Delay

PHI Clock Rise to ADDR Hold Time

PHI Clock Fall to Output DATA Valid Delay

PHI Clock Rise to DATA Hold Time

PHI Clock Rise to CSx Assertion Delay

PHI Clock Rise to CSx Deassertion Delay

PHI Clock Rise to IORQ Assertion Delay

PHI Clock Rise to IORQ Deassertion Delay

PHI Clock Fall to WR Assertion Delay

PHI Clock Rise to WR Deassertion Delay*

WR Deassertion to ADDR Hold Time

WR Deassertion to DATA Hold Time

WR Deassertion to CSx Hold Time

1

2

3

4

5

6

7

8

9

10

2.2

—

7.5

—

2.3

2.6

2.4

2.6

2.3

1.8

1.6

0.4

0.5

1.2

0.5

10.8

8.8

7.0

6.3

4.5

4.4

—

WR Deassertion to IORQ Hold Time

—

Note: *At the conclusion of a Write cycle, deassertion of WR always occurs before any change to

ADDR, DATA, CSx, or IORQ.

PS019209-0504

P R E L I M I N A R Y

Electrical Characteristics

eZ80F91 MCU

Product Specification

355

Wait State Timing for Read Operations

Figure 68 illustrates the extension of the memory access signals using a single

WAIT state for a Read operation. This wait state is generated by setting CS_WAIT

to 001 in the Chip Select Control Register.

T_CLK

T_WAIT

SCLK

ADDR[23:0]

DATA[7:0]

(output)

CSx

MREQ

RD

INSTRD

Figure 68. Wait State Timing for Read Operations

PS019209-0504

P R E L I M I N A R Y

Electrical Characteristics

eZ80F91 MCU

Product Specification

356

Wait State Timing for Write Operations

Figure 69 illustrates the extension of the memory access signals using a single

WAIT state for a Write operation. This wait state is generated by setting CS_WAIT

to 001 in the Chip Select Control Register.

T_CLK

T_WAIT

PHI

ADDR[23:0]

DATA[7:0]

(output)

CSx

MREQ

WR

Figure 69. Wait State Timing for Write Operations

PS019209-0504

P R E L I M I N A R Y

Electrical Characteristics

eZ80F91 MCU

Product Specification

357

General Purpose I/O Port Input Sample Timing

Figure 70 illustrates timing of the GPIO input sampling. The input value on a GPIO

port pin is sampled on the rising edge of the system clock. The port value is then

available to the CPU on the second rising clock edge following the change of the

port value.

T_CLK

PHI

Port Value

Changes to 0

GPIO Pin

Input Value

GPIO Input

Data Latch

0 Latched

Into GPIO

Data Register

GPIO Data Register

Value 0 Read

by eZ80

GPIO Data

READ on Data Bus

Figure 70. Port Input Sample Timing

General Purpose I/O Port Output Timing

Figure 71 and Table 240 provide timing information for GPIO port pins.

T_CLK

PHI

Port Output

T₁

T₂

Figure 71. GPIO Port Output Timing

PS019209-0504

P R E L I M I N A R Y

Electrical Characteristics

eZ80F91 MCU

Product Specification

358

Table 240. GPIO Port Output Timing

Parameter Abbreviation

Delay (ns)

Min

—

Max

9.3

—

T

PHI Clock Rise to Port Output Valid Delay

PHI Clock Rise to Port Output Hold Time

1

2

2.0

External Bus Acknowledge Timing

Table 241 provides information on the bus acknowledge timing.

Table 241. Bus Acknowledge Timing

Delay (ns)

Parameter Abbreviation

Min

2.8

2.5

Max

7.1

T

PHI Clock Rise to BUSACK Assertion Delay

PHI Clock Rise to BUSACK Deassertion Delay

1

6.5

2

External System Clock Driver Timing

Table 242 provides timing information for the PHI pin. The PHI pin allows external

peripherals to synchronize with the internal system clock driver on the eZ80F91

device.

Table 242. PHI System Clock Timing

Delay (ns)

Parameter Abbreviation

Min

1.6

1.8

Max

4.6

T

PHI Clock Rise to PHI Rise

PHI Clock Fall to PHI Fall

1

2

4.3

PS019209-0504

P R E L I M I N A R Y

Electrical Characteristics

eZ80F91 MCU

Product Specification

359

Packaging

Figure 72 illustrates the 144-pin LQFP (low-profile quad flat pack) package for the

eZ80F91 device.

HD

D

A

A2

A1

C

L

F

E

HE

DETAIL

A

C

L

LE

c

b

e

L

Figure 72. 144-Lead Plastic Low-Profile Quad Flat Package (LQFP)

PS019209-0504

P R E L I M I N A R Y

Packaging

eZ80F91 MCU

Product Specification

360

Figure 73 illustrates the 144-pin BGA (chip array Ball Grid Array) package for the

eZ80F91 device.

Figure 73. 144-Lead Chip Array Ball Grid Array (BGA)

PS019209-0504

P R E L I M I N A R Y

Packaging

eZ80F91 MCU

Product Specification

361

Ordering Information

Table 243 provides a part name, a product specification index code, and a brief

description of each part.

Table 243. Ordering Information

Part

PSI

Description

eZ80F91

eZ80F91AZ050SC

144-pin LQFP, 256KB Flash memory, 8KB

SRAM, 50MHz, Standard Temperature.

eZ80F91AZ050EC

eZ80F91NA050SC

eZ80F91NA050EC

144-pin LQFP, 256KB Flash memory, 8KB

SRAM, 50MHz, Extended Temperature.

144-pin BGA, 256KB Flash memory, 8KB

SRAM, 50MHz, Standard Temperature.

144-pin BGA, 256KB Flash memory, 8KB

SRAM, 50MHz, Extended Temperature.

eZ80F91 Development Kit eZ80F910200ZCO

Complete Development Kit.

Navigate your browser to ZiLOG’s website to order the eZ80F91 microcontroller.

Or, contact your local ZiLOG Sales Office. ZiLOG provides additional assistance

on its Customer Service page, and is also here to help with Technical Support

issues.

For ZILOG’s valuable development tools and downloadable software, visit the

ZiLOG website.

Part Number Description

ZiLOG part numbers consist of a number of components, as indicated in the fol-

lowing examples:

ZiLOG Base Products

®

eZ80

F91

AZ

ZiLOG eZ80 CPU

Product Number

Package

050

S or E

C

Speed

Temperature

Environmental Flow

PS019209-0504

P R E L I M I N A R Y

Ordering Information

eZ80F91 MCU

Product Specification

362

Package

AZ = LQFP (also called the VQFP)

050 = 50 MHz

S = 0 C to +70

E = –40 C to +105

C = Plastic Standard

Speed

Standard Temperature

Extended Temperature

Environmental Flow

º

ºC

º

ºC

Example: Part number eZ80F91AZ050SC is an eZ80F91 product in a LQFP package,

operating with a 50-MHz external clock frequency over a 0ºC to +70ºC temperature range

and built using the Plastic Standard environmental flow.

Precharacterization Product

The product represented by this document is newly introduced and ZiLOG has not

completed the full characterization of the product. The document states what

ZiLOG knows about this product at this time, but additional features or nonconfor-

mance with some aspects of the document might be found, either by ZiLOG or its

customers in the course of further application and characterization work. In addi-

tion, ZiLOG cautions that delivery might be uncertain at times, due to start-up

yield issues.

ZiLOG, Inc.

532 Race Street

San Jose, CA

95126-3432

USA

Telephone (408) 558-8500

FAX 408 558-8300

Internet: www.zilog.com

PS019209-0504

P R E L I M I N A R Y

Ordering Information

eZ80F91 MCU

Product Specification

363

Document Information

Document Number Description

The Document Control Number that appears in the footer on each page of this

document contains unique identifying attributes, as indicated in the following

table:

PS

Product Specification

Unique Document Number

Revision Number

0192

09

0504

Month and Year Published

Change Log

Rev Date

Purpose

By

01

02

03

04

05

06

07

08

09

12/02

Original issue

J. Eversmann, B. Metzler, R. Beebe

B. Metzler, R. Beebe

P. Clark, R. Beebe

01/03

02/03

03/03

06/03

07/03

10/03

05/04

Minor content changes

Modified INT_P0:5

Minor modifications

Added BGA info

R. Beebe

B. Metzler, R. Beebe

C. Bender, R. Beebe

R. Xue, C. Bender, B. Metzler, R. Beebe

Minor content changes

PS019209-0504

P R E L I M I N A R Y

Document Information

eZ80F91 MCU

Product Specification

364

Index

address bus 6–11, 66, 76, 78–79, 82–83, 86,

89–90, 93–94, 168, 293–294, 303, 309

24-bit 35

Addressing, I C 231

alarm bit flag 167, 181

Numerics

100-pin LQFP package 4, 5

16-bit clock divisor value 189, 215

16-bit divisor count 189, 215

32 KHz Real-Time Clock Crystal Oscillator

Operation 343

2

alarm condition 167–168, 181

AND/OR Gating of the PWM Outputs 153–154

Arbiter, EMAC 242

2

Arbitration, I C 223

A

Architectural Overview 1

asynchronous communications protocol 183–

184

2

AAK—see I C Acknowledge

Absolute Maximum Ratings 345

AC Characteristics 348

ACK—see Acknowledge

asynchronous serial data 17, 20–21

Acknowledge 221, 225–229, 232, 236–237

2

I C 221

ADDR0 6

B

Basic Timer Operation 128

Basic Timer Register Set 136

Baud Rate Generator 188

Functional Description 213

BCD—see Binary-Coded-Decimal Operation

binary operation 166

Binary-Coded-Decimal Operation 166, 168–

179, 181

bit generation 183–184

ADDR1 6

ADDR2 6

ADDR3 6

ADDR4 7

ADDR5 7

ADDR6 7

ADDR7 7

ADDR8 8

ADDR9 8

Block Diagram 2

ADDR10 8

ADDR11 8

ADDR12 9

ADDR13 9

ADDR14 9

ADDR15 9

ADDR16 10

ADDR17 10

ADDR18 10

ADDR19 10

ADDR20 11

ADDR21 11

ADDR22 11

ADDR23 11

Boot Block 33, 105, 115, 117

Boundary Scan Cell Functionality 314

Boundary Scan Instructions 319

Boundary-Scan Architecture 311

break detection 183, 193

Break Point Halting 132

break point trigger functions 311

BRG Control Registers 189

bus acknowledge 15, 78, 98, 293–294, 302–

303, 309, 358

cycle 6–9, 11, 14–15, 78, 98–100, 102

Bus Arbiter 98

Bus Arbitration Overview 219

2

Bus Clock Speed, I C 239

PS019209-0504

P R E L I M I N A R Y

Index

eZ80F91 MCU

Product Specification

365

Bus Mode Controller 78

Clocking Overview 219

bus mode state 79–80, 83

bus modes 78–79, 92, 96

COL—see Collision Detect, MII

Collision Detect, MII 30

Complex triggers 311

Switching Between 92

bus request 15, 78, 98, 293, 302, 309

Bus Requests During ZDI Debug Mode 293

bus timing 78

CONTINUOUS mode 127, 130–132, 139,

143–144

Control Transfers, UART 187

CPHA—see Clock Phase

CPOL—see Clock Polarity

CRC—see cyclic redundancy check 246–247,

251–252, 264

BUSACK—see bus acknowledge

BUSREQ—see bus request

2

Byte Format, I C 221

CRS—see Carrier Sense, MII

CS0 11, 73–76

CS1 12, 73–76

CS2 12, 73, 75–76

CS3 12, 73, 75–76

CTS—see Clear To Send

CTS0 18, 206

CTS1 21

Customer Feedback Form 379

cycle termination signal 89–90

C

C source-level debugging 286

capture flag 134

carrier sense 255, 259–260

Window Referencing 260

MII 30, 259

Chain Sequence and Length, JTAG Boundary

Scan 314

Change Log 363

Characteristics, Electrical

Charge Pump 320, 325

PLL 321

Chip Select Registers 93

D

data bus 12, 78–79, 81–83, 86, 90, 96, 168,

293–294, 303, 309

Chip Select x Bus Mode Control Register 96

Chip Select x Control Register 95

Chip Select x Lower Bound Register 93

Chip Select x Upper Bound Register 94

Chip Select/Wait State Generator block 6–8,

10–11

Chip Selects and Wait States 73

Chip Selects During Bus Request/Bus

Acknowledge Cycles 78

Data Carrier Detect 19, 22, 199, 202

Delta Status Change Of 202

Data Set Ready 19, 22, 199, 202

Delta Status Change Of 202

Data Terminal Ready 18, 22, 199, 202

Data Transfer Procedure with SPI configured

as a Slave 214

Data Transfer Procedure with SPI Configured

as the Master 214

data transfer, SPI 217

Clear To Send 18, 21, 199, 202

Delta Status Change Of 202

CLK_MUX 325

Data Transfers, UART 187

2

clock divisor value, 16-bit 189, 215

clock initialization circuitry 312

Clock Peripheral Power-Down Registers 55

Clock Phase 210–212, 216

Clock Polarity 211–212, 216

Clock Synchronization for Handshake 224

Data Validity, I C 220

DATA0 12

DATA1 12

DATA2 12

DATA3 12

DATA4 13

DATA5 13

2

Clock Synchronization, I C 222

PS019209-0504

P R E L I M I N A R Y

Index

eZ80F91 MCU

Product Specification

366

DATA6 13

DATA7 13

Boundary Pointer Register—Low and High

Bytes 271

DC Characteristics 346

DCD—see Data Carrier Detect

DCD0 19, 206

Boundary Pointer Register—Upper Byte

272

Buffer Size Register 274

Configuration Register 1 251

Configuration Register 2 253

Configuration Register 3 254

Configuration Register 4 255

FIFO Data Register—Low and High Bytes

284

FIFO Flags Register 285

Functional Description 241

functions 240

DCD1 22

DCTS—see Clear To Send, Delta Status

Change Of

DDCD—see Data Carrier Detect, Delta Status

Change Of

DDSR—see Data Set Ready, Delta Status

Change Of

Divider, PLL 321

divisor count 215

16-bit 189

Hash Table Register 264

Interpacket Gap 258

Interpacket Gap Register 259

Interrupt Enable Register 275

Interrupt Status Register 277

Interrupts 244

Document Information 363

Document Number Description 363

DSR—see Data Set Ready

DSR0 19, 206

DSR1 22

DTACK—see cycle termination signal

DTR—see Data Terminal Ready

DTR0 18, 206

Maximum Frame Length Register—Low

and High Bytes 261

memory 241, 242

DTR1 22

MII Management Register 265

MII Status Register 279

Non-Back-To-Back IPG Register—Part 1

260

Non-Back-To-Back IPG Register—Part 2

261

E

EC0 23, 133, 136, 138

EC1 30, 133, 135, 138

PHY Address Register 267

PHY Configuration Data Register—High

Byte 267

PHY Configuration Data Register—Low

Byte 266

PHY Read Status Data Register—Low and

High Bytes 278

PHY Unit Select Address Register 268

RAM 101–104

edge-selectable interrupts 62

Edge-Triggered Interrupts 60, 62

Electrical Characteristics 345

EMAC—see Ethernet Media Access Controller

EMACMII module 240

Enabling and Disabling the WDT 123

encoder/decoder 204–205, 207–208

signal pins 206

IrDA 56

endec—see encoder/decoder

ENDEC Mode 254, 258

Receive Blocks Left Register—Low and

High Bytes 282

Receive High Boundary Pointer Register—

Low and High Bytes 272

Receive Read Pointer Register—Low and

High Bytes 273

Erasing Flash Memory 109

Ethernet Media Access Controller 240

Address Filter Register 263

PS019209-0504

P R E L I M I N A R Y

Index

eZ80F91 MCU

Product Specification

367

Receive Write Pointer Register—High Byte

281

Receive Write Pointer Register—Low Byte

280

Receiver Interrupts 244

Registers 249

Reset Control Register 269

Shared Memory Organization 245

Station Address Register 256

sublayer module 240

System Interrupts 244

Test Register 249

Transmit Lower Boundary Pointer

Register—Low and High Bytes 270

Transmit Pause Timer Value Register—

Low and High Bytes 257

Transmit Polling Timer Register 268

Transmit Read Pointer Register—High

Byte 282

F

falling edge 152–153, 155, 160

FAST mode 219, 239

FCS—see frame check sequence

Features 1

Features, eZ80 CPU Core 50

FIFO mode 184, 187

Flash Address registers 107–108, 111, 118

Flash Address Upper Byte Register 112

Flash Column Select Register 120

Flash Control Register 110, 113

Flash controller 106–108, 114, 116

clock 114

Flash Data Register 111

Flash Frequency Divider Register 114

Flash Interrupt Control Register 116

Flash Key Register 110

Flash Memory 105

Arrangement in the eZ80F91 Device 105

array 106, 118

Overview 106

Transmit Read Pointer Register—Low

Byte 281

Transmitter Interrupts 244

event count input 138

event count mode 134

Flash Page Select Register 118

Flash Program Control Register 120

Flash Row Select Register 119

Flash Write/Erase Protection Register 115

frame check sequence 247–248, 258

framing error 183, 185, 193, 200

frequency divider 106, 114

full-duplex transmission 212

Functional Description, Infrared Encoder/

Decoder 204

event counter 131, 133

External Bus Acknowledge Timing 358

external bus master 98–99

external bus request 78, 289, 293

External I/O Read Timing 352

External I/O Write Timing 353

External Memory Read Timing 349

External Memory Write Timing 350

external pull-down resistor 59

External Reset Input and Indicator 51

External System Clock Driver (PHI) Timing 358

eZ80 Bus Mode 79, 96

eZ80 CPU 14, 77–78, 82, 89, 204, 296, 311

Core 50

Instruction Set 330

eZ80 Product ID Low and High Byte Registers

305

Functional Description, SPI 212

G

General Purpose Input/Output 58

Control Registers 62

Interrupts 61

modes 59–60

Operation 58

Port Input Sample Timing 357

Port Output Timing 357

port pins 51, 58, 63, 357

GND—see Ground

eZ80 Product ID Revision Register 306

eZ80Acclaim!™ Flash Microcontrollers 1, 106

eZ80F91 device 4–5, 35, 347

PS019209-0504

P R E L I M I N A R Y

Index

eZ80F91 MCU

Product Specification

368

GPIO—see General Purpose Input/Output

Ground 2

IEEE 802.3 specification 253–254, 263

frames 252

IEEE 802.3, 802.3(u) minimum values 258

IEEE 802.3/4.2.3.2.1 Carrier Deference 259–

260

IEEE Standard 1149.1 311–312

IEF1 67–68, 131, 307

H

HALT instruction 16, 54, 307, 333

Op-Code Map 335

HALT Mode 1, 54–55, 299, 307

HALT_SLP 16, 307, 314

handshake 183, 185, 224

hash table 263

IEF2 67–68

IFLG—see I C Interrupt Flag

2

IM 0, Op Code Map 338

IM 1, Op Code Map 338

IM 2, Op Code Map 338

Information Page Characteristics 110

Infrared Data Association 204

Receive Data 17

I

I/O Chip Select Operation 76

I/O Chip Selects, External 35

I/O Read 107

specifications 205

standard 204

standard baud rates 204

transceiver 207

Transmit Data 17

I/O space 6–8, 10–11, 13, 73, 76

2

I C Acknowledge 221, 225–226, 228–231,

234–235

2

Infrared Encoder/Decoder 17, 56, 204, 207

Register 207

I C bus 219, 222–224

clock 219

protocol 220

Signal Pins 206

2

Input capture mode 133–134, 136, 140

Input/Output Request 13, 15, 76, 79, 82–83, 86

Assertion Delay 352, 354

Deassertion Delay 353–354

Hold Time 354

INSTRD—see Instruction Read

Instruction Read 14

Instruction Store 4

I C Clock Control Register 238

2

I C control bit 225–226, 228

2

I C Control Register 234

2

I C Data Register 233

2

I C Extended Slave Address Register 232

2

I C General Characteristics 219

2

I C Interrupt Flag 219, 224, 227, 229–232,

234, 237

2

0 Registers 303

Intel Bus Mode 81

I C Registers 231

2

I C Serial Clock 26, 219–221, 238

2

Separate Address and Data Buses 82

internal pull-up 59

Internal RC oscillator 122–123, 125

internal system clock 77

interpacket gap 247, 258–259, 261

Interrupt Controller 65

Interrupt Enable bit 15, 167, 186, 234

Interrupt Enable Flag 131, 307

interrupt input 17–19, 21–22, 24–27, 29, 207

Interrupt Priority 69, 71

I C Serial I/O Interface 219

2

I C Slave Address Register 232

2

I C Software Reset Register 239

2

I C Status Register 236

IC0 23, 133, 136, 140–141, 144–147, 157, 161

IC1 24, 133, 136, 140–141, 144, 146, 157, 161

IC2 25, 133, 136, 140–141, 144–146, 157, 161

IC3 25, 133, 136, 140–141, 144, 146–147,

157, 161

levels 68

IEEE 1149.1 specification 313, 319

PS019209-0504

P R E L I M I N A R Y

Index

eZ80F91 MCU

Product Specification

369

Registers 68

Interrupt request 60–62, 66, 117, 133, 139–

140

L

least-significant bit 142–143, 145–146, 149,

162, 164, 224–228, 230, 262, 266, 270,

272–273, 278, 280–281

least-significant byte 66–68, 143, 238, 243,

256, 263

level-sensitive interrupt modes 60

level-sensitive interrupts 62, 207

Level-Triggered Interrupts 61

Line break detection 183

line status error 186

enable 213, 216

signals 65

interrupt service routine 66–68

SPI 66

interrupt sources 157

interrupt vector 65–66

address 67, 68

bus 65–68

locations 66

table 67

line status interrupt 185, 187–188, 193

Lock Detect 320, 322

interrupt, higher-priority 71, 194

interrupt, highest-priority 65–66

interrupts, edge-selectable 62

interrupts, level-sensitive 62

Introduction to On-Chip Instrumentation 311

Introduction, ZiLOG Debug Interface 286

IORQ—see Input/Output Request

IR_RXD modulation signal 205–208

IR_TxD modulation signal 17, 205–207

IrDA—see Infrared Data Association 204

IRQ—see interrupt request

IRQ_EN—see interrupt request enable

ISR—see interrupt service routine

IVECT—see interrupt vector bus

sensitivity 325

PLL 322

Loop Filter 320, 322, 329

PLL 20, 321

LOOP Mode 185

LOOP_FILT 313

Loopback Testing, Infrared Encoder/Decoder

207

low-byte vector 65

Low-Power Modes 54

LSB—see least-significant byte

lsb—see least-significant bit

M

maskable interrupt 55, 65, 68, 71

MASS ERASE operation 109–110, 115–116,

118, 120–121

MASTER mode 211, 219, 230, 234–239

Start bit 234

J

Jitter, Infrared Encoder/Decoder 206

Joint Test Action Group 313

Boundary Scan 313

interface 311, 319

mode selection 312

Test Clock 288, 312–313, 319

Test Data In 312–314

Test Data Out 312–314

Test Mode 16

Stop bit 234

SPI 212

MASTER RECEIVE Mode 219, 227

MASTER TRANSMIT Mode 219, 224

MASTER_EN bit 213

Master-In, Slave-Out 25, 210, 212

Master-Out, Slave-In 26, 210–212

MAXF—see Maximum Frame Length

Maximum Frame Length 251, 261

MBIST—see Memory Built-In Self-Test

controllers

Test Mode Select 312–313

JTAG—see Joint Test Action Group

PS019209-0504

P R E L I M I N A R Y

Index

eZ80F91 MCU

Product Specification

370

MDC—see Media-Independent Interface

Management Data Clock

MDIO—see Media-Independent Interface

Management Data

Media-Independent Interface 240, 244, 258,

265, 276–279

Multi-PWM Control Registers 158

Multi-PWM Mode 150

Multi-PWM Power-Trip Mode 157

MUX/CLK Sync 320

PLL 321

Collision Detect 30

Management Data 33

N

Management Data Clock 33, 266

Memory and I/O Chip Selects 73

Memory Built-In Self-Test controllers 104

Memory Chip Select Example 74

Memory Chip Select Operation 73

Memory Chip Select Priority 74

Memory Read 107

Memory Request 14

memory space 73, 76

Memory Write 109

Memory, EMAC 241

NACK—see Not Acknowledge

New Instructions, eZ80 CPU Core 50

NMI—see Nonmaskable Interrupt

NMI_flag bit 124

NMI_OUT bit 124

Nonmaskable Interrupt 15, 50, 55, 65, 122,

124, 333

nonoverlapping delay, PWM 153, 156

Not Acknowledge 221, 225–226, 228–229,

235, 237

MII—see Media-Independent Interface

MISO—see Master-In, Slave-Out

Mode fault error flag 210, 213, 217

modem status 186–188, 194, 198, 202

interrupt 206

signal 18–19, 21–22

MODF—see Mode fault error flag

Module Reset, UART 187

MOSI—see Master-Out, Slave-In

most significant bit 118, 143–144, 146–147,

150, 163, 165, 221, 262, 270, 279, 281–283,

292

most significant byte 67, 144, 243

Motorola Bus Mode 88

O

OC0 27, 133, 135, 140–141, 148–150

OC1 27, 133, 135, 140–141

OC2 28, 133, 135, 140,–141

OC3 28, 133, 135, 139, 141, 149–150

OCI—see On-Chip Instrumentation

On-Chip Instrumentation 311

Activation 312

clock pin 312

Interface 312

Introduction to 311

On-Chip Oscillators 342

on-chip pull-up 346

on-chip RAM 73, 101–102

Op Code maps 335

Open source I/O 59

open-drain I/O 59

Motorola-compatible 78

MPWM_EN 151, 158

MREQ—see Memory Request 14–15, 74, 79,

82–83, 86, 349, 351

Hold Time 351

open-drain mode 59

MSB—see most significant byte

msb—see most significant bit

Multibyte I/O Write (Row Programming) 108

multicast address 248, 264

multicast packet 263, 264

open-drain output 59, 219

open-source mode 59

open-source output 17–19, 21–23, 25–27, 29,

59

Operating Modes, I C 224

Operation of the eZ80F91 Device during ZDI

2

multimaster conflict 213, 217

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P R E L I M I N A R Y

Index

eZ80F91 MCU

Product Specification

371

Break Points 293

PHI—see system clock output

Ordering Information 361

OUTPUT COMPARE mode 133, 134, 137,

139, 148

overrun condition, receiver 186

overrun error 183, 185, 193, 201

Overview, Low-Power Modes 54

Overview, Phase-Locked Loop 320

PHY—see Physical Layer, OSI Model

MII 240, 265

Physical Layer, OSI Model 6, 30–31, 32, 37–

38, 244, 248, 266–267, 277–279

Pin Characteristics 6

Pin Coverage, JTAG Boundary Scan 313

Pin Description 4

PLL Characteristics 327

PLL Control Register 0 325

PLL Control Register 1 326

PLL Divider Control Register—Low and High

Bytes 323

PLL Loop Filter 20

PLL Normal Operation 322

PLL Registers 323

PLL_V_DD323

PLL_V_SS323

Poll Mode Transfers 188

P

PA7 155

Packaging 359

Page Erase operation 109, 118, 120, 121

PAIR_EN 158–159

parity error 185, 196, 201

Part Number Description 361

PB0 23

PB1 24

POP, Op Code Map 335, 337, 339

POR—see Power-On Reset

Port A 27, 28, 29, 56, 58, 66, 70, 71, 150

Port x Alternate Register 1 63

Port x Alternate Register 2 64

Port x Data Direction Registers 63

Port x Data Registers 62

PB2 24

PB3 24

PB4 25

PB5 25

PB6 25

PB7 26

PC0 20, 27

Potential Hazards of Enabling Bus Requests

During Debug Mode 294

Power connections 2

Power-On Reset

Power Requirement to the Phase-Locked Loop

Function 323

PC1 21, 27

PC2 21, 28

PC3 21, 28

PC4 22, 29

PC5 22, 29

PC6 22, 30

Power-On Reset 51–52, 347

and VBO Electrical Characteristics 347

and VBO analog RESET duration 347

and VBO DC current consumption 347

and VBO Hysteresis 347

PC7 23, 30

PD0 17, 207

PD1 17, 207

PD2 18, 207

PD3 18

voltage threshold 52, 347

PD4 18

Power-Trip Mode, Multi-PWM 157–158

Precharacterization Product 362

Primary Crystal Oscillator Operation 342

Program Counter 51, 54–55, 67, 105, 304–

305, 309

PD5 19

PD6 19

PD7 19, 207

Phase Frequency Detector 320

PLL 321

Program Counter, Starting 68

Phase-Locked Loop 320

PS019209-0504

P R E L I M I N A R Y

Index

eZ80F91 MCU

Product Specification

372

Programmable Reload Timers 127

Programming Flash Memory 107

PROMISCUOUS Mode 263

PT_EN 158

pull-up resistor, external 59, 219

Pulse-Width Modulation

Control Register 1 158

PWM2 rising edge end-of-count 153

PWM2_EN 158

PWM2RH 153

PWM3 28, 30, 133, 135, 152

PWM3_EN 158

PWMCNTRL1 151

PWMCNTRL2 153

PWMCNTRL3 157

Control Register 2 159

Control Register 3 161

delay feature 156

edge transition values 153–154

Falling Edge—High Byte 165

Falling Edge—Low Byte 164

generator 150–154, 158

generators 151

Q

qualified multicast messages 263

R

Master Mode 153

RAM—see Random Access Memory

Random Access Memory 101

Address Upper Byte Register 103

Control Register 102

RD—see Read instruction

Read instruction 13–14, 74, 76, 79, 82–83, 86

Assertion Delay 350, 353

Deassertion Delay 350, 353

Reading Flash Memory 106

Reading the Current Count Value 128

Real-Time Clock 51, 54, 166–168, 180

Alarm 54, 167

mode 127, 133, 137, 140

mode, Multi- 150–151, 153–154, 158

nonoverlapping delay 153

nonoverlapping delay time 156

Nonoverlapping Output Pair Delays 155

output pairs 153

outputs 154–155, 157

Outputs, AND/OR Gating 153–154

outputs, inverted 152

pairs 154

power-trip state 157

Rising Edge—High Byte 163

Rising Edge—Low Byte 162

signals 150

Alarm Control Register 180

Alarm Day-of-the-Week Register 179

Alarm Hours Register 178

Alarm Minutes Register 177

Alarm Seconds Register 176

Battery Backup 167

Century Register 175

Control Register 181

Day-of-the-Month Register 172

Day-of-the-Week Register 171

Hours Register 170

Minutes Register 169

Month Register 173

Oscillator and Source Selection 167

Overview 166

Recommended Operation 167

Registers 168

trip levels 161

waveform 154

PUSH, Op Code Map 335, 337, 339

PWM—see Pulse-Width Modulation

PWM0 155

PWM1 27, 29, 133, 135, 152, 154

PWM1 falling edge end-of-count 153, 156

PWM1 rising edge end-of-count 153, 156

PWM1_EN 158

PWM1FH 153

PWM1RH 163, 165

PWM1RL 162–165

PWM2 28, 30, 133, 135, 152

PWM2 falling edge end-of-count 153

PS019209-0504

P R E L I M I N A R Y

Index

eZ80F91 MCU

Product Specification

373

Seconds Register 168

signal 134

RxD3 33

RxDMA 243

source 122, 125, 131

Year Register 174

Receive, Infrared Encoder/Decoder 205

Recommended Usage of the Baud Rate

Generator 189

S

Schmitt Trigger 14–15

Input 14–16, 20, 22–23, 25, 33

input buffers 58

Register Map 35

Register Set for Capture in Timer 1 136

Register Set for Capture/Compare/PWM in

Timer 3 137

SCK—see SPI Serial Clock

SCL—see I C Serial Clock

SCL line 222, 224

2

Request To Send 18, 21, 199, 202, 206

RESET 14, 51–52, 54–55, 59, 73, 101–102,

113, 115, 122–124, 168, 171–181, 189, 207,

214–215, 297, 299, 312, 314, 347

Reset controller 51–52

RESET event 51, 58

RESET mode timer 51–52

Reset Operation 51

SCLK—see System Clock

SDA 26, 219, 220, 221, 231

SDA line 223

see system reset 13

serial bus, SPI 217, 218

Serial Clock 219

2

Serial Clock, I C 26, 219–221, 238

Serial Clock, SPI 24, 210

Serial Data 210, 219

RESET Or NMI Generation 124

Reset States 74

2

Serial Data, I C 26

RESET_OUT 314

Serial Peripheral Interface 1, 56, 66, 70, 209–

210, 212

2

Resetting the I C Registers 231

RI—see Ring Indicator

RI0 19, 206

RI1 23, 60

Ring Indicator 19, 23, 185, 199, 202

Trailing Edge of 202

rising edge 152–153, 155, 160

RST_FLAG bit 124

RTC Oscillator Input 134

RTC Supply Voltage 346

RTC_V_DD16

Baud Rate Generator 213

Baud Rate Generator Registers—Low

Byte and High Byte 215

Control Register 216

Data Rate 214

Flags 213

Functional Description 212

interrupt service routine 66

master device 25–26, 214

MASTER mode 212

mode 24

Receive Buffer Register 218

Registers 214

serial bus 217

Signals 210

slave device 25, 26

SLAVE mode 212

Status Register 217

RTC_X 15

IN

RTC_X

15, 167

OUT

RTS—see Request To Send

RTS0 18

RTS1 21

Rx_CLK 32

Rx_DV 32

Rx_ER 32

RxD0 17, 32

RxD1 21, 32

RxD2 32

Status register 213

Transmit Shift Register 213–214, 217

Setting Timer Duration 128

PS019209-0504

P R E L I M I N A R Y

Index

eZ80F91 MCU

Product Specification

374

Shift Left Arithmetic 226, 228, 232, 334

Op Code Map 336, 340–341

Shift Right Arithmetic 334

Op Code Map 336, 340

System Clock 51, 54–57, 60–61, 122–123,

125, 131, 133, 138, 155, 188, 213, 238–239,

242, 266, 320–322, 357

Cycle Time 348

SINGLE PASS Mode 127, 129–130, 139

Single-Byte I/O Write 107

SLA—see Shift Left Arithmetic

SLAVE mode 219, 230, 232, 234, 237

SLAVE mode, SPI 212

cycles 14, 76, 79–80, 83, 86–87, 90, 123,

128, 312

divider 139

driver 358

Driver Timing, External 358

Fall Time 348

Slave Receive 219, 230

Slave Select 24, 210–212, 214, 216

Slave Transmit mode 219, 229–230, 235

SLEEP Mode 54, 181, 299, 307

sleep-mode recovery 181

reset 35, 182

Frequency 128, 189, 214

frequency 107, 109, 113–114, 287

High Time 348

jitter 134

Low Time 348

Software break point instruction 311

Specialty Timer Modes 133

SPI—see Serial Peripheral Interface

SPI Serial Clock 24, 210

Oscillator Input 20

Oscillator Output 20

output 26, 57, 315, 358

period 312

Flag 212, 217–218,

periods 156, 160

Idle State 211

Rise Time 348

pin 212, 216

Receive Edge 211

rising edge 188, 213

source 325

signal 212

Timing, PHI 358

Transmit Edge 211

SPIF—see SPI Flag

SRA—see Shift Right Arithmetic

SRAM—see Static RAM

system clock, high-frequency 213

system clock, internal 77

system RESET 51, 167, 169, 170, 191, 249,

322

SS—see Slave Select

STA—see MASTER Mode Start bit

STANDARD mode 219

Standard VHDL Package STD_1149_1_2001

314

T

T2 clock 156

T2 end-of-count 156

START and STOP Conditions 220

START condition 220, 222–224, 226–227,

229–237, 239

T23CLKCN 156

TAP—see Test Access Port

TCK—see JTAG Test Clock

TDI—see JTAG Test Data In

TDO—see JTAG Test Data Out

TERI—see Ring Indicator, Trailing Edge of

Test Access Port 311, 319

instruction 319

Reset 312–313

state register 312

Test Mode 312

ZDI 288

Starting Program Counter 67–68

Static RAM 1, 112, 281, 286, 361

internal Ethernet 245

STOP condition 220–221, 224, 227, 229–231,

234–235, 237, 239

supply voltage 2, 52, 59, 219, 322, 345–347

Switching Between Bus Modes 92

PS019209-0504

P R E L I M I N A R Y

Index

eZ80F91 MCU

Product Specification

375

Time-Out Period Selection 123

Timer Control Register 138

Timer Data Register—High Byte 142

Timer Data Register—Low Byte 142

Timer Input Capture Control Register 144

Timer Input Capture Value A Register—High

Byte 146

Timer Input Capture Value A Register—Low

Byte 145

Timer Input Capture Value B Register—High

Byte 147

TxD1 20, 31

TxD2 31

TxD3 31

TxDMA 242

U

UART—see Universal Asynchronous

Receiver/Transmitter

Universal Asynchronous Receiver/Transmitter

183

Timer Input Capture Value B Register—Low

Byte 146

Baud Rate Generator Register—Low and

High Bytes 189

Timer Input Source Selection 131

Timer Interrupt Enable Register 139

Timer Interrupt Identification Register 141

Timer Interrupts 130

FIFO Control Register 195

Functional Description 184

Functions 184

Interrupt Enable Register 192

Interrupt Identification Register 193

Interrupts 186

Line Control Register 196

Line Status Register 200

Modem Control 185

Modem Control Register 198

Modem Status Interrupt 187

Modem Status Register 202

Receive Buffer Register 192

Receiver 185

Receiver Interrupts 186

Recommended Usage 187

Registers 191

Scratch Pad Register 203

Transmit Holding Register 191

Transmitter 184

Timer Output 131

Compare Control Register 1 147

Compare Control Register 2 148

Compare Value Register—High Byte 150

Compare Value Register—Low Byte 149

Timer Port Pin Allocation 135

Timer Registers 136

Timer Reload Register—High Byte 144

Timer Reload Register—Low Byte 143

TMS—see JTAG Test Mode Select

TOUT0 29, 135

TOUT1 29, 135

Trace buffer memory 311

Trace history buffer 311

Transferring Data 221

transmit shift register 184, 192, 196, 200

Transmit Shift Register, SPI 212–214, 217–

218

Transmitter Interrupt 186

Usage, JTAG Boundary Scan 319

Transmit, Infrared Encoder/Decoder 205

trigger-level detection logic 184

TRIGOUT 312, 314

V

tristate 157

VBO—see Voltage Brown-Out

V_CC—see supply voltage

V_CCramp rate 347

VCO—see Voltage Controlled Oscillator

VLAN tagged frame 261

Voltage Brown-Out 51–53, 347

TRSTn—see Test Access Port Reset

Tx_CLK 31

Tx_EN 31

Tx_ER 31

TxD0 17, 31

PS019209-0504

P R E L I M I N A R Y

Index

eZ80F91 MCU

Product Specification

376

pulse reject period 347

Reset 52

Voltage Threshold 347

Voltage Controlled Oscillator 321, 328

PLL 321

voltage signal, high 108

voltage, input 321

voltage, peak-to-peak 329

voltage, supply 2, 59, 219, 322, 345, 346

Z

Z80 Bus Mode 79

ZCL—see ZiLOG Debug Interface Clock

ZDA—see ZiLOG Debug Interface Data

ZDI—see ZiLOG Debug Interface

ZDI_BUS_STAT 294, 296, 309

ZDI_BUSACK_EN 293, 309

ZDI-Supported Protocol 287

ZDS II—see ZiLOG Developer Studio II

ZiLOG Debug Interface 286–287, 311

Address Match Registers 296

Block Read 292

W

WAIT 1, 14, 83, 86, 89–90, 120

WAIT Input Signal 77

WAIT pin, external 79

Wait State Timing for Read Operations 355

Wait State Timing for Write Operations 356

WAIT states 66, 76, 80, 87, 83, 86, 95, 294,

355–356

Block Write 291

Break Control Register 297

Bus Control Register 302

Bus Status Register 309

Clock 288, 291, 297

lock and Data Conventions 288

clock pin 288

Watch-Dog Timer 1, 51, 54, 122–124, 293

clock source 122–123, 125

Control Register 35, 124

Operation 123

Data 288, 297, 312

data pin 288

debug control 311

Master Control Register 299

Read Memory Register 309

Read Operations 292

Read Register Low, High, and Upper 308

Read/Write Control Register 300

Read-Only Registers 295

Register Addressing 290

Register Definitions 296

Single-Bit Byte Separator 289

Single-Byte Read 292

Single-Byte Write 291

Start Condition 288

Status Register 307

Write Data Registers 300

Write Memory Register 304

Write Only Registers 294

Write Operations 291

oscillator 124

Overview 122

Registers 124

Reset Register 126

time-out 51, 54–55, 122–126

time-out reset 35

WCOL—see Write Collision

WDT—see Watch-Dog Timer

WP—see Write Protect pin

WR—see Write instruction

Write Collision 212–213, 217

SPI 217

Write instruction 13–14, 74, 76, 79, 83, 86,

351, 354

Write Protect pin 33, 105, 115, 117

ZiLOG Developer Studio II 286

X

input pin 342

output pin 342

IN

OUT

PS019209-0504

P R E L I M I N A R Y

Index

eZ80F91 MCU

Product Specification

377

Customer Feedback Form

The eZ80F91 Product Specification

If you experience any problems while operating this product, or if you note any inaccuracies while reading

this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return

Information, below). We also welcome your suggestions!

Customer Information

Name

Country

Phone

Fax

Company

Address

City/State/Zip

Email

Product Information

Serial # or Board Fab #/Rev. #

Software Version

Document Number

Host Computer Description/Type

Return Information

ZiLOG

System Test/Customer Support

532 Race Street

San Jose, CA 95126

Phone: (408) 558-8500

Fax: (408) 558-8536

Email: tools@zilog.com

Problem Description or Suggestion

Provide a complete description of the problem or your suggestion. If you are reporting a specific problem,

include all steps leading up to the occurrence of the problem. Attach additional pages as necessary.

_______________________________________________________________________________

PS019209-0504

P R E L I M I N A R Y

Customer Feedback Form


型号：	EZ80F91AZ050SC
厂家：	ZILOG, INC.
描述：	eZ80Acclaim-TM Flash Microcontrollers eZ80Acclaim -TM闪存微控制器闪存微控制器
文件：	总396页 (文件大小：4552K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EZ80F91AZ050SC [ZILOG]

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