EZ80F91AZA50EG [ZILOG]
IC 8-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP144, LEAD FREE, LQFP-144, Microcontroller;
| 型号： | EZ80F91AZA50EG |
| 厂家： | 
ZILOG, INC. |
| 描述： | IC 8-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP144, LEAD FREE, LQFP-144, Microcontroller 时钟 微控制器 外围集成电路 |
| 文件： | 总395页 (文件大小：1879K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
eZ80AcclaimPlus!™ Connectivity ASSP
eZ80F91 ASSP
Product Specification
PS027004-0613
Copyright ©2013 Zilog, Inc. All rights reserved.
www.zilog.com
eZ80F91 ASSP
Product Specification
ii
DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
Warning:
LIFE SUPPORT POLICY
ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti-
cal component is any component in a life support device or system whose failure to perform can be reason-
ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2013 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
eZ80, eZ80AcclaimPlus!, Z80, Zdots, and Z180 are trademarks or registered trademarks of Zilog, Inc. All
other product or service names are the property of their respective owners.
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Revision History
Each instance in the following revision history table reflects a change to this document
from its previous version. For more details, refer to the corresponding pages provided in
the table.
Revision
Date Level
Page
Number
Description
Jun
2013
04
03
02
Conditionally qualified the I
value in the DC Characteristics table.
338
RTC
May
2012
Updated to reference the eZ80AcclaimPlus! Development Kit
(eZ80F910300KITG).
354
2
Oct
Updated Table 1, Addressing section in I C Serial I/O Interface chapter,
4, 47,
2008
Part Number Description, Figure 6, Flash Program Control Register, UART 109, 173,
Transmitter, and Figure 40.
198, 220,
355
Jul
01
Original Issue.
All
2007
PS027004-0613
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xviii
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
System Clock Source Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SCLK Source Selection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
eZ80 CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
New Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
External Reset Input and Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
HALT Mode and the EMAC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Clock Peripheral Power-Down Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
GPIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Level-Triggered Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Edge-Triggered Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
GPIO Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Port x Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Port x Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Port x Alternate Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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Port x Alternate Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Port x Alternate Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
GPIO Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Chip Selects and Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Memory and I/O Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Memory Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Memory Chip Select Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Memory Chip Select Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Input/Output Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
WAIT Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Chip Selects During Bus Request/Bus Acknowledge Cycles . . . . . . . . . . . . . . . . . . 67
Bus Mode Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
eZ80 BUS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Z80 BUS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Intel Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Intel Bus Mode: Separate Address and Data Buses . . . . . . . . . . . . . . . . . . . . . . 72
Intel Bus Mode: Multiplexed Address and Data Bus . . . . . . . . . . . . . . . . . . . . . 76
Motorola Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Switching Between Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Chip Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Chip Select x Lower Bound Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Chip Select x Upper Bound Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Chip Select x Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Chip Select x Bus Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Bus Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
RAM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
RAM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
RAM Address Upper Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MBIST Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Flash Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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Reading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Single-Byte I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Multibyte I/O Write (Row Programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Information Page Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Flash Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Flash Key Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Flash Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Flash Address Upper Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Flash Frequency Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Flash Write/Erase Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Flash Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Flash Row Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Flash Column Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Flash Program Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Enabling and Disabling the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . 112
Time-Out Period Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
RESET or NMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Watchdog Timer Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Programmable Reload Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Basic Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Reading the Current Count Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Setting Timer Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SINGLE PASS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
CONTINUOUS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Timer Input Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
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Timer Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Break Point Halting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Specialty Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Event Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
RTC Oscillator Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Timer Port Pin Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Basic Timer Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Register Set for Capture in Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Register Set for Capture/Compare/PWM in Timer 3 . . . . . . . . . . . . . . . . . . . . 126
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Timer Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Timer Interrupt Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Timer Data Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Timer Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Timer Reload Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Timer Reload High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Timer Input Capture Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Timer Input Capture Value A Low Byte Register . . . . . . . . . . . . . . . . . . . . . . 136
Timer Input Capture Value A High Byte Register . . . . . . . . . . . . . . . . . . . . . . 137
Timer Input Capture Value B Low Byte Register . . . . . . . . . . . . . . . . . . . . . . 137
Timer Input Capture Value B High Byte Register . . . . . . . . . . . . . . . . . . . . . . 138
Timer Output Compare Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Timer Output Compare Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Timer Output Compare Value Low Byte Register . . . . . . . . . . . . . . . . . . . . . . 140
Timer Output Compare Value High Byte Register . . . . . . . . . . . . . . . . . . . . . 141
Multi-PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
PWM Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Modification of Edge Transition Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
AND/OR Gating of the PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
PWM Nonoverlapping Output Pair Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Multi-PWM Power-Trip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Multi-PWM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Pulse-Width Modulation Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Pulse-Width Modulation Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Pulse-Width Modulation Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Pulse-Width Modulation Rising Edge Low Byte Register . . . . . . . . . . . . . . . 153
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Pulse-Width Modulation Rising Edge High Byte Register . . . . . . . . . . . . . . . 153
Pulse-Width Modulation Falling Edge Low Byte Register . . . . . . . . . . . . . . . 154
Pulse-Width Modulation Falling Edge High Byte Register . . . . . . . . . . . . . . . 154
Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Real-Time Clock Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Real-Time Clock Oscillator and Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . 156
Real-Time Clock Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Real-Time Clock Recommended Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Real-Time Clock Seconds Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Real-Time Clock Minutes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Real-Time Clock Hours Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Real-Time Clock Day-of-the-Week Register . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Real-Time Clock Day-of-the-Month Register . . . . . . . . . . . . . . . . . . . . . . . . . 161
Real-Time Clock Month Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Real-Time Clock Year Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Real-Time Clock Century Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Real-Time Clock Alarm Seconds Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Real-Time Clock Alarm Minutes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Real-Time Clock Alarm Hours Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Real-Time Clock Alarm Day-of-the-Week Register . . . . . . . . . . . . . . . . . . . . 168
Real-Time Clock Alarm Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Real-Time Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
UART Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
UART Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
UART Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
UART Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
UART Modem Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
UART Transmitter Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
UART Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
UART Modem Status Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
UART Recommended Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Module Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Control Transfers to Configure UART Operation . . . . . . . . . . . . . . . . . . . . . . 176
Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Recommended Use of the Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . 179
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BRG Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
UART Baud Rate Generator High and Low Byte Registers . . . . . . . . . . . . . . 179
UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
UART Transmit Holding Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
UART Receive Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
UART Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
UART Interrupt Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
UART FIFO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
UART Line Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
UART Modem Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
UART Line Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
UART Modem Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
UART Scratch Pad Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Infrared Encoder/Decoder Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Loopback Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Infrared Encoder/Decoder Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Master In, Slave Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Master Out, Slave In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
SPI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
SPI Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Mode Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Write Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Baud Rate Generator Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 202
Data Transfer Procedure with SPI Configured as a Master . . . . . . . . . . . . . . . . . . 203
Data Transfer Procedure with SPI Configured as a Slave . . . . . . . . . . . . . . . . . . . 203
SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
SPI Baud Rate Generator Low Byte and High Byte Registers . . . . . . . . . . . . 204
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
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SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
SPI Transmit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
SPI Receive Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
I2C Serial I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Clocking Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Bus Arbitration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Transferring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Clock Synchronization for Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Master Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Master Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Slave Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Slave Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Resetting the I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
I2C Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
I2C Extended Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
I2C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
I2C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
I2C Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Bus Clock Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
I2C Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Zilog Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
ZDI-Supported Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
ZDI Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
ZDI Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
ZDI Single-Bit Byte Separator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
ZDI Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
ZDI Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
ZDI Single-Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
ZDI Block Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
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ZDI Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
ZDI Single-Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
ZDI Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Operation of the eZ80F91 Device During ZDI Break Points . . . . . . . . . . . . . . . . . 237
Bus Requests During ZDI Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Potential Hazards of Enabling Bus Requests During DEBUG Mode . . . . . . . 238
ZDI Write-Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
ZDI Read-Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
ZDI Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
ZDI Address Match Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
ZDI Break Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
ZDI Master Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
ZDI Write Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
ZDI Read/Write Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
ZDI Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Instruction Store 4:0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
ZDI Write Memory Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
eZ80 Product ID Low and High Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . 250
eZ80 Product ID Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
ZDI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
ZDI Read Register Low, High, and Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
ZDI Bus Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
ZDI Read Memory Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
On-Chip Instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
OCI Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
OCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Pin Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Boundary Scan Cell Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Chain Sequence and Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Boundary Scan Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Phase Frequency Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Voltage-Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
MUX/CLK Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
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Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
PLL Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Power Requirement to the Phase-Locked Loop Function . . . . . . . . . . . . . . . . . . . 268
PLL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
PLL Divider Control High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . 268
PLL Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
PLL Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
eZ80 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Ethernet Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
EMAC Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
TxDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
RxDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Signal Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
EMAC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
EMAC Shared Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
EMAC and the System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
EMAC Operation in HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
EMAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
EMAC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
EMAC Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
EMAC Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
EMAC Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
EMAC Configuration Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
EMAC Station Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
EMAC Transmit Pause Timer Value High and Low Byte Registers . . . . . . . . 304
EMAC Interpacket Gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
EMAC Interpacket Gap Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
EMAC Non-Back-To-Back IPG Register, Part 1 . . . . . . . . . . . . . . . . . . . . . . 307
EMAC Non-Back-To-Back IPG Register, Part 2 . . . . . . . . . . . . . . . . . . . . . . 307
EMAC Maximum Frame Length High and Low Byte Registers . . . . . . . . . . . 308
EMAC Address Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
EMAC Hash Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
EMAC MII Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
EMAC PHY Configuration Data Register, Low and High Byte . . . . . . . . . . . 312
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EMAC PHY Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
EMAC PHY Unit Select Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
EMAC Transmit Polling Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
EMAC Reset Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
EMAC Transmit Lower Boundary Pointer High and Low Byte Registers . . . 317
EMAC Boundary Pointer High and Low Byte Registers . . . . . . . . . . . . . . . . . 318
EMAC Boundary Pointer Register, Upper Byte . . . . . . . . . . . . . . . . . . . . . . . 319
EMAC Receive High Boundary Pointer High and Low Byte Registers . . . . . 319
EMAC Receive Read Pointer High and Low Byte Registers . . . . . . . . . . . . . 320
EMAC Buffer Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
EMAC Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
EMAC Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
EMAC PHY Read Status Data High and Low Byte Registers . . . . . . . . . . . . 325
EMAC MII Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
EMAC Receive Write Pointer Low Byte Register . . . . . . . . . . . . . . . . . . . . . . 327
EMAC Receive Write Pointer High Byte Register . . . . . . . . . . . . . . . . . . . . . 327
EMAC Transmit Read Pointer Low Byte Register . . . . . . . . . . . . . . . . . . . . . 328
EMAC Transmit Read Pointer High Byte Register . . . . . . . . . . . . . . . . . . . . . 328
EMAC Receive Blocks Left High and Low Byte Registers . . . . . . . . . . . . . . 329
EMAC FIFO Data High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . 330
EMAC FIFO Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Primary Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
32kHz Real-Time Clock Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . 334
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
POR and VBO Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Current Consumption Under Various Operating Conditions . . . . . . . . . . . . . . . . . 340
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
External Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
External Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
External I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
External I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Wait State Timing for Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Wait State Timing for Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
General-Purpose Input/Output Port Input Sample Timing . . . . . . . . . . . . . . . . . . . 351
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General-Purpose Input/Output Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . 351
External Bus Acknowledge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
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List of Figures
Figure 1. eZ80F91 ASSP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. 144-Pin LQFP Configuration of the eZ80F91 . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 4. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 5. GPIO Port Pin Block Diagram for Input and Interrupt Modes . . . . . . . . . . 47
Figure 6. GPIO Port Pin Block Diagram for Output and Input/Output Mode . . . . . . 47
Figure 7. Example: Memory Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 8. Wait Input Sampling Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 9. Example: Wait State Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 10. Example: Z80 Bus Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 11. Example: Z80 Bus Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 12. Intel Bus Mode Signal and Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 13. Example: Intel Bus Mode Read Timing: Separate Address and Data Buses 74
Figure 14. Example: Intel Bus Mode Write Timing: Separate Address
and Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 15. Example: Intel Bus Mode Read Timing: Multiplexed Address
and Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 16. Example: Intel Bus Mode Write Timing: Multiplexed Address
and Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 17. Motorola Bus Mode Signal and Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 18. Example: Motorola Bus Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 19. Example: Motorola Bus Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 20. Memory Interface Bus Operation During CPU Bus Cycles,
Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 21. Memory Interface Bus Operation During Bus Acknowledge Cycles . . . . . 89
Figure 22. Example: eZ80F91 On-Chip RAM Memory Addressing . . . . . . . . . . . . . . 90
Figure 23. eZ80F91 Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 24. Flash Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 25. Watchdog Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 26. Programmable Reload Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . 117
Figure 27. Example: PRT Single Pass Mode Operation . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 28. Example: PRT Continuous Mode Operation . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 29. Example: PRT Timer Output Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 121
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Figure 30. Multi-PWM Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 31. Multi-PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 32. Multi-PWM Operation: Expanded View of Timing . . . . . . . . . . . . . . . . . 143
Figure 33. PWM AND/OR Gating Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 34. PWM Nonoverlapping Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 35. Real-Time Clock and 32kHz Oscillator Block Diagram . . . . . . . . . . . . . . 155
Figure 36. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 37. Infrared System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 38. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 39. Infrared Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 40. SPI Master Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 41. SPI Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 42. SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 43. I2C Clock and Data Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 44. Start and Stop Conditions In I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 45. I2C Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 46. I2C Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 47. Clock Synchronization In I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 48. Typical ZDI Debug Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 49. Schematic For Building a Target Board ZPAK Connector . . . . . . . . . . . . 231
Figure 50. ZDI Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 51. ZDI Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 52. ZDI Address Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 53. ZDI Single-Byte Data Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 54. ZDI Block Data Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 55. ZDI Single-Byte Data Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 56. ZDI Block Data Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 57. Phase-Locked Loop Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 58. Normal PLL Programming Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 59. EMAC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 60. Internal Ethernet Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Figure 61. Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 62. Descriptor Table Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 63. Recommended Crystal Oscillator Configuration: 50MHz Operation . . . . 333
Figure 64. Recommended Crystal Oscillator Configuration: 32kHz Operation . . . . . 335
Figure 65. I vs. System Clock Frequency During ACTIVE Mode . . . . . . . . . . . . . 340
CC
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Figure 66. I vs. System Clock Frequency During HALT Mode . . . . . . . . . . . . . . . 341
CC
Figure 67. I vs. V During SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
CC
DD
Figure 68. External Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Figure 69. External Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 70. External I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Figure 71. External I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Figure 72. Wait State Timing for Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Figure 73. Wait State Timing for Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Figure 74. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Figure 75. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
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List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
eZ80F91 144-BGA Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Identification on the eZ80F91 ASSP Device . . . . . . . . . . . . . . . . . . . . . 6
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Clock Peripheral Power-Down Register 1 (CLK_PPD1) . . . . . . . . . . . . . . 43
Clock Peripheral Power-Down Register 2 (CLK_PPD2) . . . . . . . . . . . . . . 44
GPIO Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Port x Data Registers (Px_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Port x Data Direction Registers (Px_DDR) . . . . . . . . . . . . . . . . . . . . . . . . . 52
Port x Alternate Registers 0 (Px_ALT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 10. Port x Alternate Registers 1 (Px_ALT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 11. Port x Alternate Registers 2 (Px_ALT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 12. Interrupt Vector Sources by Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 13. Vectored Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 14. Interrupt Priority Registers (INT_Px) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 15. Interrupt Vector Priority Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 16. Example: Maskable Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 17. Example: Priority Levels for Maskable Interrupts . . . . . . . . . . . . . . . . . . . 60
Table 18. Example: Register Values for Figure 7 Memory Chip Select . . . . . . . . . . . 64
Table 19. Z80 BUS Mode Read States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 20. Z80 Bus Mode Write States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 21. Intel Bus Mode Read States: Separate Address and Data Buses . . . . . . . . . 72
Table 22. Intel Bus Mode Write States: Separate Address and Data Buses . . . . . . . . 73
Table 23. Intel Bus Mode Read States: Multiplexed Address and Data Bus . . . . . . . 76
Table 24. Intel Bus Mode Write States: Multiplexed Address and Data Bus . . . . . . . 76
Table 25. Motorola Bus Mode Read States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 26. Motorola Bus Mode Write States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 27. Chip Select x Lower Bound Register (CSx_LBR) . . . . . . . . . . . . . . . . . . . 83
Table 28. Chip Select x Upper Bound Register (CSx_UBR) . . . . . . . . . . . . . . . . . . . 84
Table 29. Chip Select x Control Register (CSx_CTL) . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 30. Chip Select x Bus Mode Control Register (CSx_BMC) . . . . . . . . . . . . . . . 86
Table 31. eZ80F91 Pin Status During Bus Acknowledge Cycles . . . . . . . . . . . . . . . . 87
Table 32. RAM Control Register (RAM_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 33. RAM Address Upper Byte Register (RAM_ADDR_U) . . . . . . . . . . . . . . . 92
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Table 34. MBIST Control Register (MBIST_GPR, MBIST_EMR) . . . . . . . . . . . . . . 93
Table 35. Flash Key Register (FLASH_KEY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 36. Flash Data Register (FLASH_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 37. Flash Address Upper Byte Register (FLASH_ADDR_U) . . . . . . . . . . . . 101
Table 38. Flash Control Register (FLASH_CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 39. Flash Frequency Divider Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 40. Flash Frequency Divider Register (FLASH_FDIV) . . . . . . . . . . . . . . . . . 103
Table 41. Flash Write/erase Protection Register (FLASH_PROT) . . . . . . . . . . . . . . 104
Table 42. Flash Interrupt Control Register (FLASH_IRQ) . . . . . . . . . . . . . . . . . . . . 106
Table 43. Flash Page Select Register (FLASH_PAGE) . . . . . . . . . . . . . . . . . . . . . . 107
Table 44. Flash Row Select Register (FLASH_ROW) . . . . . . . . . . . . . . . . . . . . . . . 108
Table 45. Flash Column Select Register (FLASH_COL) . . . . . . . . . . . . . . . . . . . . . 109
Table 46. Flash Program Control Register (FLASH_PGCTL) . . . . . . . . . . . . . . . . . 110
Table 47. WDT Approximate Time-Out Delays for Possible Clock Sources . . . . . . 113
Table 48. Watchdog Timer Control Register (WDT_CTL) . . . . . . . . . . . . . . . . . . . 114
Table 49. Watchdog Timer Reset Register (WDT_RR) . . . . . . . . . . . . . . . . . . . . . . 116
Table 50. Example: PRT Single Pass Mode Parameters . . . . . . . . . . . . . . . . . . . . . . 119
Table 51. Example: PRT Continuous Mode Parameters . . . . . . . . . . . . . . . . . . . . . . 120
Table 52. Example: PRT Timer Out Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 53. GPIO Mode Selection Using Timer Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 54. Timer Control Register (TMRx_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 55. Timer Interrupt Enable (TMRx_IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 56. Timer Interrupt Identification Register (TMRx_IIR) . . . . . . . . . . . . . . . . 130
Table 57. Timer Data Low Byte Register (TMRx_DR_L) . . . . . . . . . . . . . . . . . . . . 132
Table 58. Timer Data High Byte Register (TMRx_DR_H) . . . . . . . . . . . . . . . . . . . 133
Table 59. Timer Reload Low Byte Register (TMRx_RR_L) . . . . . . . . . . . . . . . . . . 134
Table 60. Timer Reload High Byte Register (TMRx_RR_H) . . . . . . . . . . . . . . . . . . 135
Table 61. Timer Input Capture Control Register
(TMR1_CAP_CTL, TMR3_CAP_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 62. Timer Input Capture Value Low Byte Register A
(TMR1_CAPA_L, TMR3_CAPA_L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 63. Timer Input Capture Value High Byte Register A
(TMR1_CAPA_H, TMR3_CAPA_H) . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 64. Timer Input Capture Value Low Byte Register B
(TMR1_CAPB_L, TMR3_CAPB_L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 65. Timer Input Capture Value High Byte Register B
(TMR1_CAPB_H, TMR3_CAPB_H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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xx
Table 66. Timer Output Compare Control Register 1 (TMR3_OC_CTL1) . . . . . . . 138
Table 67. Timer Output Compare Control Register 2 (TMR3_OC_CTL2) . . . . . . . 139
Table 68. Compare Value Low Byte Register (TMR3_OCx_L) . . . . . . . . . . . . . . . . 140
Table 69. Compare Value High Byte Register (TMR3_OCx_H) . . . . . . . . . . . . . . . 141
Table 70. Enabling PWM Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 71. Example: Multi-PWM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 72. PWM Nonoverlapping Output Addressing . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 73. PWM Control Register 1 (PWM_CTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 74. PWM Control Register 2 (PWM_CTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 75. PWM Control Register 3 (PWM_CTL3) . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 76. PWMx Rising-Edge Low Byte Register (TMR3_PWMxR_L) . . . . . . . . . 153
Table 77. PWMx Rising-Edge High Byte Register (TMR3_PWMxR_H) . . . . . . . . 153
Table 78. PWMx Falling-Edge Low Byte Register (TMR3_PWMxF_L) . . . . . . . . 154
Table 79. PWMx Falling-Edge High Byte Register (TMR3_PWMxF_H) . . . . . . . . 154
Table 80. Real-Time Clock Seconds Register (RTC_SEC) . . . . . . . . . . . . . . . . . . . 157
Table 81. Real-Time Clock Minutes Register (RTC_MIN) . . . . . . . . . . . . . . . . . . . 158
Table 82. Real-Time Clock Hours Register (RTC_HRS) . . . . . . . . . . . . . . . . . . . . . 159
Table 83. Real-Time Clock Day-of-the-Week Register (RTC_DOW) . . . . . . . . . . . 160
Table 84. Real-Time Clock Day-of-the-Month Register (RTC_DOM) . . . . . . . . . . 161
Table 85. Real-Time Clock Month Register (RTC_MON) . . . . . . . . . . . . . . . . . . . . 162
Table 86. Real-Time Clock Year Register (RTC_YR) . . . . . . . . . . . . . . . . . . . . . . . 163
Table 87. Real-Time Clock Century Register (RTC_CEN) . . . . . . . . . . . . . . . . . . . 164
Table 88. Real-Time Clock Alarm Seconds Register (RTC_ASEC) . . . . . . . . . . . . 165
Table 89. Real-Time Clock Alarm Minutes Register (RTC_AMIN) . . . . . . . . . . . . 166
Table 90. Real-Time Clock Alarm Hours Register (RTC_AHRS) . . . . . . . . . . . . . . 167
Table 91. Real-Time Clock Alarm Day-of-the-Week Register (RTC_ADOW) . . . . 168
Table 92. Real-Time Clock Alarm Control Register (RTC_ACTRL) . . . . . . . . . . . 169
Table 93. Real-Time Clock Control Register (RTC_CTRL) . . . . . . . . . . . . . . . . . . . 170
Table 94. UART Baud Rate Generator Low Byte Registers (UARTx_BRG_L) . . . 180
Table 95. UART Baud Rate Generator High Byte Registers (UARTx_BRG_H) . . . 180
Table 96. UART Transmit Holding Registers (UARTx_THR) . . . . . . . . . . . . . . . . . 181
Table 97. UART Receive Buffer Registers (UARTx_RBR) . . . . . . . . . . . . . . . . . . . 182
Table 98. UART Interrupt Enable Registers (UARTx_IER) . . . . . . . . . . . . . . . . . . . 182
Table 99. UART Interrupt Identification Registers (UARTx_IIR) . . . . . . . . . . . . . . 183
Table 100. UART Interrupt Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 101. UART FIFO Control Registers (UARTx_FCTL) . . . . . . . . . . . . . . . . . . . 185
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Table 102. UART Line Control Registers (UARTx_LCTL) . . . . . . . . . . . . . . . . . . . . 186
Table 103. UART Character Parameter Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 104. Parity Select Definition for Multidrop Communications . . . . . . . . . . . . . 187
Table 105. UART Modem Control Registers (UARTx_MCTL) . . . . . . . . . . . . . . . . 188
Table 106. UART Line Status Registers (UARTx_LSR) . . . . . . . . . . . . . . . . . . . . . . 189
Table 107. UART Modem Status Registers (UARTx_MSR) . . . . . . . . . . . . . . . . . . . 191
Table 108. UART Scratch Pad Registers (UARTx_SPR) . . . . . . . . . . . . . . . . . . . . . . 192
Table 109. GPIO Mode Selection when using the IrDA Encoder/Decoder . . . . . . . . 196
Table 110. Infrared Encoder/Decoder Control Registers (IR_CTL) . . . . . . . . . . . . . . 197
Table 111. SPI Clock Phase and Clock Polarity Operation . . . . . . . . . . . . . . . . . . . . . 200
Table 112. SPI Baud Rate Generator Low Byte Register (SPI_BRG_L) . . . . . . . . . . 204
Table 113. SPI Baud Rate Generator High Byte Register (SPI_BRG_H) . . . . . . . . . 204
Table 114. SPI Control Register (SPI_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 115. SPI Status Register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 116. SPI Transmit Shift Register (SPI_TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 117. SPI Receive Buffer Register (SPI_RBR) . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 118. I2C Master Transmit Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 119. I2C 10-Bit Master Transmit Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 120. I2C Master Transmit Status Codes For Data Bytes . . . . . . . . . . . . . . . . . . 216
Table 121. I2C Master Receive Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 122. I2C Master Receive Status Codes For Data Bytes . . . . . . . . . . . . . . . . . . . 218
Table 123. I2C Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 124. I2C Slave Address Register (I2C_SAR) . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 125. I2C Data Register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 126. I2C Extended Slave Address Register (I2C_XSAR) . . . . . . . . . . . . . . . . . 223
Table 127. I2C Control Register (I2C_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 128. I2C Status Registers (I2C_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 129. I2C Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 130. I2C Clock Control Registers (I2C_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 131. I2C Software Reset Register (I2C_SRR) . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 132. Recommend ZDI Clock versus System Clock Frequency . . . . . . . . . . . . . 231
Table 133. ZDI Write-Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 134. ZDI Read-Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 135. ZDI Address Match Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 136. ZDI Address Match Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 137. ZDI Break Control Register (ZDI_BRK_CTL) . . . . . . . . . . . . . . . . . . . . . 243
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eZ80F91 ASSP
Product Specification
xxii
Table 138. ZDI Master Control Register (ZDI_MASTER_CTL) . . . . . . . . . . . . . . . . 244
Table 139. ZDI Write Data Registers (ZDI_WR_U, ZDI_WR_H, ZDI_WR_L) . . . . 245
Table 140. ZDI Read/Write Control Register Functions (ZDI_RW_CTL) . . . . . . . . . 246
Table 141. ZDI Bus Control Register (ZDI_BUS_CTL) . . . . . . . . . . . . . . . . . . . . . . 248
Table 142. Instruction Store 4:0 Registers
(ZDI_IS4, ZDI_IS3, ZDI_IS2, ZDI_IS1, ZDI_IS0) . . . . . . . . . . . . . . . . . 249
Table 143. ZDI Write Memory Register (ZDI_WR_MEM) . . . . . . . . . . . . . . . . . . . . 250
Table 144. eZ80 Product ID Low Byte Register (ZDI_ID_L) . . . . . . . . . . . . . . . . . . 250
Table 145. eZ80 Product ID High Byte Register (ZDI_ID_H) . . . . . . . . . . . . . . . . . . 251
Table 146. eZ80 Product ID Revision Register (ZDI_ID_REV) . . . . . . . . . . . . . . . . 251
Table 147. ZDI Status Register (ZDI_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 148. ZDI Read Register Low, High, and Upper
(ZDI_RD_L, ZDI_RD_H, ZDI_RD_U) . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 149. ZDI Bus Control Register (ZDI_BUS_STAT) . . . . . . . . . . . . . . . . . . . . . 254
Table 150. ZDI Read Memory Register (ZDI_RD_MEM) . . . . . . . . . . . . . . . . . . . . . 255
Table 151. OCI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 152. Pin to Boundary Scan Cell Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 153. PLL Divider Low Byte Registers (PLL_DIV_L) . . . . . . . . . . . . . . . . . . . 268
Table 154. PLL Divider High Byte Registers (PLL_DIV_H) . . . . . . . . . . . . . . . . . . . 269
Table 155. PLL Control Register 0 (PLL_CTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Table 156. PLL Control Register 1 (PLL_CTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 157. PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Table 158. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 159. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 160. Block Transfer and Compare Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 161. Exchange Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table 162. Input/Output Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table 163. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 164. Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 165. Processor Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 166. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 167. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 168. Op Code Map: First Op Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 169. Op Code Map: Second Op Code after 0CBh . . . . . . . . . . . . . . . . . . . . . . . 280
Table 170. Op Code Map: Second Op Code After 0DDh . . . . . . . . . . . . . . . . . . . . . . 281
Table 171. Op Code Map: Second Op Code After 0EDh . . . . . . . . . . . . . . . . . . . . . . 282
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eZ80F91 ASSP
Product Specification
xxiii
Table 172. Op Code Map: Second Op Code After 0FDh . . . . . . . . . . . . . . . . . . . . . . 283
Table 173. Op Code Map: Fourth Byte After 0DDh, 0CBh, and dd . . . . . . . . . . . . . . 284
Table 174. Op Code Map: Fourth Byte After 0FDh, 0CBh, and dd . . . . . . . . . . . . . . 285
Table 175. Arbiter Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 176. MII Signal Termination When EMAC is Not Used . . . . . . . . . . . . . . . . . 290
Table 177. EMAC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 178. Ethernet Packet Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 179. Transmit Descriptor Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 180. Receive Descriptor Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 181. EMAC Test Register (EMAC_TEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 182. EMAC Configuration Register 1 (EMAC_CFG1) . . . . . . . . . . . . . . . . . . 298
Table 183. CRC/PAD Features of EMAC Configuration Register . . . . . . . . . . . . . . . 299
Table 184. EMAC Configuration Register 2 (EMAC_CFG2) . . . . . . . . . . . . . . . . . . 300
Table 185. EMAC Configuration Register 3 (EMAC_CFG3) . . . . . . . . . . . . . . . . . . 301
Table 186. EMAC Configuration Register 4 (EMAC_CFG4) . . . . . . . . . . . . . . . . . . 302
Table 187. EMAC Station Address Register (EMAC_STAD_x) . . . . . . . . . . . . . . . . 303
Table 188. EMAC Transmit Pause Timer Value Low Byte Register
(EMAC_TPTV_L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 189. EMAC Transmit Pause Timer Value High Byte Register
(EMAC_TPTV_H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 190. EMAC_IPGT Back-to-Back Settings for Full- and Half-Duplex Modes . 305
Table 191. EMAC_IPGT Non-Back-to-Back Settings for Full- /Half-Duplex Modes 305
Table 192. EMAC Interpacket Gap Register (EMAC_IPGT) . . . . . . . . . . . . . . . . . . . 306
Table 193. EMAC Non-Back-To-Back IPG Register, Part 1 (EMAC_IPGR1) . . . . . 307
Table 194. EMAC Non-Back-To-Back IPG Register, Part 2 (EMAC_IPGR2) . . . . . 307
Table 195. EMAC Maximum Frame Length Low Byte Register (EMAC_MAXF_L) 309
Table 196. EMAC Maximum Frame Length High Byte Register
(EMAC_MAXF_H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Table 197. EMAC Address Filter Register (EMAC_AFR) . . . . . . . . . . . . . . . . . . . . . 310
Table 198. EMAC Hash Table Register (EMAC_HTBL_x) . . . . . . . . . . . . . . . . . . . . 311
Table 199. EMAC MII Management Register (EMAC_MIIMGT) . . . . . . . . . . . . . . 311
Table 200. EMAC PHY Configuration Data Low Byte Register (EMAC_CTLD_L) 313
Table 201. EMAC PHY Configuration Data High Byte Register (EMAC_CTLD_H) 313
Table 202. EMAC PHY Address Register (EMAC_RGAD) . . . . . . . . . . . . . . . . . . . 314
Table 203. EMAC PHY Unit Select Address Register (EMAC_FIAD) . . . . . . . . . . . 314
Table 204. EMAC Transmit Polling Timer Register (EMAC_PTMR) . . . . . . . . . . . . 315
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eZ80F91 ASSP
Product Specification
xxiv
Table 205. EMAC Reset Control Register (EMAC_RST) . . . . . . . . . . . . . . . . . . . . . 315
Table 206. EMAC Transmit Lower Boundary Pointer Low Byte Register
(EMAC_TLBP_L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Table 207. EMAC Transmit Lower Boundary Pointer High Byte Register
(EMAC_TLBP_H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Table 208. EMAC Boundary Pointer Low Byte Register (EMAC_BP_L) . . . . . . . . . 318
Table 209. EMAC Boundary Pointer High Byte Register (EMAC_BP_H) . . . . . . . . 318
Table 210. EMAC Boundary Pointer Register, Upper Byte (EMAC_BP_U) . . . . . . . 319
Table 211. EMAC Receive High Boundary Pointer Low Byte Register
(EMAC_RHBP_L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Table 212. EMAC Receive High Boundary Pointer High Byte Register
(EMAC_RHBP_H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Table 213. EMAC Receive Read Pointer Low Byte Register (EMAC_RRP_L) . . . . 320
Table 214. EMAC Receive Read Pointer High Byte Register (EMAC_RRP_H) . . . . 321
Table 215. EMAC Buffer Size Register (EMAC_BUFSZ) . . . . . . . . . . . . . . . . . . . . . 322
Table 216. EMAC Interrupt Enable Register (EMAC_IEN) . . . . . . . . . . . . . . . . . . . . 323
Table 217. EMAC Interrupt Status Register (EMAC_ISTAT) . . . . . . . . . . . . . . . . . . 324
Table 218. EMAC PHY Read Status Data Low Byte Register (EMAC_PRSD_L) . . 325
Table 219. EMAC PHY Read Status Data High Byte Register (EMAC_PRSD_H) . 325
Table 220. EMAC MII Status Register (EMAC_MIISTAT) . . . . . . . . . . . . . . . . . . . 326
Table 221. EMAC Receive Write Pointer Low Byte Register (EMAC_RWP_L) . . . 327
Table 222. EMAC Receive Write Pointer High Byte Register (EMAC_RWP_H) . . . 327
Table 223. EMAC Transmit Read Pointer Low Byte Register (EMAC_TRP_L) . . . 328
Table 224. EMAC Transmit Read Pointer High Byte Register (EMAC_TRP_H) . . . 328
Table 225. EMAC Receive Blocks Left Low Byte Register (EMAC_BLKSLFT_L) 329
Table 226. EMAC Receive Blocks Left High Byte Register (EMAC_BLKSLFT_H) 329
Table 227. EMAC FIFO Data Low Byte Register (EMAC_FDATA_L) . . . . . . . . . . 330
Table 228. EMAC FIFO Data High Byte Register (EMAC_FDATA_H) . . . . . . . . . 330
Table 229. EMAC FIFO Flags Register (EMAC_FFLAGS) . . . . . . . . . . . . . . . . . . . 331
Table 230. Recommended Crystal Oscillator Specifications: 1MHz Operation . . . . . 333
Table 231. Recommended Crystal Oscillator Specifications: 10 MHz Operation . . . 334
Table 232. Recommended Crystal Oscillator Specifications: 32kHz Operation . . . . 335
Table 233. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Table 234. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Table 235. POR and VBO Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 339
Table 236. Flash Memory Electrical Characteristics and Timing . . . . . . . . . . . . . . . . 339
Table 237. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
PS027004-0613
P R E L I M I N A R Y
List of Tables
eZ80F91 ASSP
Product Specification
xxv
Table 238. Typical 144-LQFP Package Electrical Characteristics . . . . . . . . . . . . . . . 343
Table 239. External Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Table 240. External Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Table 241. External I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Table 242. External I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Table 243. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Table 244. Bus Acknowledge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Table 245. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
PS027004-0613
P R E L I M I N A R Y
List of Tables
eZ80F91 ASSP
Product Specification
1
Architectural Overview
Zilog’s eZ80F91 device is a member of Zilog’s family of eZ80Acclaim! Flash Applica-
tion-Specific Standard Products (ASSPs). The eZ80F91 MCU is a high-speed ASSP with
a maximum clock speed of 50MHz and single-cycle instruction fetch. It operates in Z80-
compatible addressing mode (64KB) or full 24-bit addressing mode (16MB). The rich
peripheral set of the eZ80F91 makes it suitable for a variety of applications, including
industrial control, embedded communication, and point-of-sale terminals.
Features
The features of eZ80F91 ASSP device include:
•
•
Single-cycle instruction fetch, high-performance, pipelined eZ80 CPU core
10/100 BaseT ethernet media access controller with Media-Independent Interface
(MII)
•
•
•
256 KB Flash memory
16 KB SRAM (8KB user and 8 KB Ethernet)
Low-power features including SLEEP Mode, HALT Mode, and selective peripheral
power-down control
•
Two Universal Asynchronous Receiver/Transmitter (UART) with independent Baud
Rate Generators (BRG)
•
•
•
•
Serial Peripheral Interface (SPI) with independent clock rate generator
I2C with independent clock rate generator
IrDA-compliant infrared encoder/decoder
Glueless external peripheral interface with 4 chip selects, individual wait state genera-
tors, an external WAIT input pin; supports Z80-, Intel-, and Motorola-style buses
•
•
Fixed-priority vectored interrupts (both internal and external) and interrupt controller
Real-time clock with separate VDD pin for battery backup and selectable on-chip
32kHz oscillator or external 50/60Hz input
•
•
•
•
•
Four 16-bit Counter/Timers with prescalers and direct input/output drive
Watchdog Timer with internal oscillator clocking option
32 bits of General-Purpose Input/Output (GPIO)
On-Chip Instrumentation (OCI™) and Zilog Debug Interfaces (ZDI)
IEEE 1149.1-compatible JTAG
PS027004-0613
P R E L I M I N A R Y
Architectural Overview
eZ80F91 ASSP
Product Specification
2
•
•
•
144-pin LQFP and BGA packages
3.0V–3.6V supply voltage with 5V tolerant inputs
Operating Temperature Range:
–
–
Standard: 0ºC to +70ºC
Extended: –40ºC to +105ºC
All signals with an overline are active Low. For example, the signal DCD1 is active when
it is a logic 0 (Low) state.
Note:
Power connections follow these conventional descriptions:
Connection
Power
Circuit
Device
V
V
V
CC
DD
SS
Ground
GND
Block Diagram
Figure 1 shows a block diagram of the eZ80F91 ASSP device.
PS027004-0613
P R E L I M I N A R Y
Architectural Overview
eZ80F91 ASSP
Product Specification
3
MII Interface
Signals (18)
Ethernet
MAC
8KB
SRAM
Arbiter
RTC_VDD
RTC_XIN
Real-Time
Clock and
32 KHz
Oscillator
RTC_XOUT
BUSACK
BUSREQ
INSTRD
IORQ
MREQ
RD
Bus
Controller
SCL
SDA
I2C
Serial
Interface
WR
NMI
SCK
SS
SPI
Serial
Parallel
Interface
eZ80
CPU
HALT_SLP
MISO
MOSI
256KB
Flash
Memory
JTAG/ZDI
Debug
Interface
JTAG/ZDI Signals (5)
WP
WAIT
Chip Select
and
Wait State
Generator
CTS0/1
DSR0/1
DCD0/1
DTR0/1
RI0/1
Interrupt
CS0
CS1
CS2
CS3
Vector
(8:0)
UART
Universal
Asynchronous
Receiver/
Transmitter
(2)
8KB
SRAM
Interrupt
Controller
RTS0/1
RxD0/1
TxD0/1
DATA[7:0]
ADDR[23:0]
WDT
Watch-Dog
Timer
Internal
RC
Osc.
GPIO
8-Bit General-
Purpose
I/O Port
Crystal
Oscillator
PLL, and
System Clock
Generator
Programmable
Reload
Timer/Counter
(4)
IrDA
Encoder/
Decoder
(4)
POR/VBO
RESET
Figure 1. eZ80F91 ASSP Block Diagram
PS027004-0613
P R E L I M I N A R Y
Architectural Overview
eZ80F91 ASSP
Product Specification
4
Pin Description
Table 1 lists the pin configuration of the eZ80F91 ASSP device in the 144-BGA package.
Table 1. eZ80F91 144-BGA Pin Configuration
12
11
10
9
8
7
6
5
4
3
2
1
A SDA SCL PA0
PA4
PA3
PA5
PA7
COL
TxD3
TxD2
TxD0
V
Rx_DV MDC WPn
RxD1 MDIO A2
A0
A1
DD
B
C
V
PHI PA1
V
Tx_EN
Tx_CLK
V
SS
SS
DD
PB6 PB7
V
V
Rx_
CLK
RxD3
A3
V
V
DD
DD
SS
SS
D
E
F
PB1 PB3 PB5
PC7 PB0 PB4
PC3 PC4 PC5
V
CRS
PA2
PB2
PC6
TxD1
Tx_ER
PA6
Rx_ER
RxD0
A9
RxD2
A5
A4
A8
A6
A7
SS
V
A11
A15
A20
V
V
DD
A10
A12
A16
DD
SS
V
A17
A23
A14
A13
SS
G
V
PC0 PC1 PC2
PLL_
V
V
V
DD
SS
OUT
SS
SS
SS
V
SS
H X
X
PLL_
V
PD7
TMS
V
D5
V
A21
A19
A18
A22
DD
SS
SS
IN
V
DD
J
V
V
LOOP PD4 TRIGOUT
RTC_
NMIn
WRn
D2
CS0n
V
DD
DD
FILT_
OUT
V
DD
K
L
PD5 PD6 PD3
TDI
V
V
RESETn RDn
V
D1
D4
CS2n CS1n
D0 CS3n
SS
DD
DD
PD1 PD2 TRST TCK
n
RTC_ BUSACKn WAITn Marten
D6
X
OUT
M PD0
V
TDO HALT
RTC_ BUSREQn INSTRDn IORQn
D7
D3
V
V
DD
SS
SS
_
X
IN
SLPn
Note: Lowercase n suffix indicates an active-low signal in this table only
PS027004-0613
P R E L I M I N A R Y
Architectural Overview
eZ80F91 ASSP
Product Specification
5
Figure 2 shows the pin layout of the eZ80F91 device in the 144-pin LQFP package.
108 V
SS
1
A0
A1
A2
A3
A4
PB7/MOSI
PB6/MISO
PB5/IC3
PB4/IC2
PB3/SCK
V
DD
PB2/SS
PB1/IC1
V
SS
A5
A6
100 PB0/IC0/EC0
V
V
SS
A7 10
A8
DD
PC7/RI1
PC6/DCD1
PC5/DSR1
PC4/DTR1
PC3/CTS1
PC2/RTS1
PC1/RxD1
90 PC0/TxD1
A9
A10
V
DD
V
SS
A11
A12
A13
A14
144-Pin LQFP
V
V
SS
A15 20
A16
DD
PLL_V
X
X
PLL_V
LOOP_FILT
DD
V
DD
IN
V
SS
OUT
A17
A18
A19
A20
A21
A22
SS
V
V
SS
DD
80 PD7/RI0
PD6/DCD0
PD5/DSR0
PD4/DTR0
PD3/CTS0
A23 30
V
DD
V
SS
CS0
CS1
CS2
PD2/RTS0
PD1/RxD0/IR_RxD
73 PD0/TxD0/IR_TxD
CS3 36
Figure 2. 144-Pin LQFP Configuration of the eZ80F91
PS027004-0613
P R E L I M I N A R Y
Architectural Overview
eZ80F91 ASSP
Product Specification
6
Pin Characteristics
Table 2 describes the pins and functions of the eZ80F91 144-pin LQFP package and 144-
ball BGA package.
Table 2. Pin Identification on the eZ80F91 ASSP Device
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
1
2
3
4
5
A1
B1
B2
C3
D4
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles.
Drives the Chip Select/Wait State
Generator block to generate Chip
Selects.
6
C1
C2
E5
D2
D1
D3
F6
E1
E2
E3
E4
V
V
Power Supply
Ground
Power Supply.
Ground.
DD
SS
7
8
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Power Supply
Ground
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles.
Drives the Chip Select/Wait State
Generator block to generate Chip
Selects.
9
10
11
12
13
14
15
16
V
V
Power Supply.
Ground.
DD
SS
ADDR11
Address Bus
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles.
Drives the Chip Select/Wait State
Generator block to generate Chip
Selects.
PS027004-0613
P R E L I M I N A R Y
Architectural Overview
eZ80F91 ASSP
Product Specification
7
Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
17
18
19
20
21
F1
F2
F3
F4
G1
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles.
Drives the Chip Select/Wait State
Generator block to generate Chip
Selects.
22
23
24
25
26
27
28
29
30
31
32
33
G2
G3
F5
H1
H2
G4
H3
J1
V
V
Power Supply
Ground
Power Supply.
Ground.
DD
SS
ADDR17
ADDR18
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Power Supply
Ground
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles.
Drives the Chip Select/Wait State
Generator block to generate Chip
Selects.
G5
J2
V
V
Power Supply.
Ground.
DD
SS
H4
J3
CS0
CS1
CS2
CS3
Chip Select 0 Output, Active
Low
CS0 Low indicates that an access is
occurring in the defined CS0 memory
or I/O address space.
34
35
36
K1
K2
L1
Chip Select 1 Output, Active
Low
CS1 Low indicates that an access is
occurring in the defined CS1 memory
or I/O address space.
Chip Select 2 Output, Active
Low
CS2 Low indicates that an access is
occurring in the defined CS2 memory
or I/O address space.
Chip Select 3 Output, Active
Low
CS3 Low indicates that an access is
occurring in the defined CS3 memory
or I/O address space.
37
38
M1
M2
V
V
Power Supply
Ground
Power Supply.
Ground.
DD
SS
PS027004-0613
P R E L I M I N A R Y
Architectural Overview
eZ80F91 ASSP
Product Specification
8
Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Power Supply
Ground
Signal Direction Description
39
40
41
42
43
44
45
46
47
48
49
L2
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
The data bus transfers data to and
from I/O and memory devices. The
eZ80F91 drives these lines only dur-
ing write cycles when the eZ80F91 is
the bus master.
K3
J4
M3
L3
H5
L4
M4
K4
G6
M5
V
V
Power Supply.
Ground.
DD
SS
IORQ
Input/Output
Request
Bidirectional,
Active Low
IORQ indicates that the CPU is
accessing a location in I/O space. RD
and WR indicate the type of access.
The eZ80F91 device does not drive
this line during RESET. It is an input
during bus acknowledge cycles.
50
L5
MREQ
Memory
Request
Bidirectional,
Active Low
MREQ Low indicates that the CPU is
accessing a location in memory. The
RD, WR, and INSTRD signals indicate
the type of access. The eZ80F91
device does not drive this line during
RESET. It is an input during bus
acknowledge cycles.
51
52
K5
J5
RD
Read
Write
Output,
Active Low
RD Low indicates that the eZ80F91
device is reading from the current
address location. This pin is in a high-
impedance state during bus acknowl-
edge cycles.
WR
Output, Active
Low
WR indicates that the CPU is writing
to the current address location. This
pin is in a high-impedance state dur-
ing bus acknowledge cycles.
PS027004-0613
P R E L I M I N A R Y
Architectural Overview
eZ80F91 ASSP
Product Specification
9
Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
53
54
55
M6
INSTRD
Instruction
Read Indicator Low
Output, Active
INSTRD (with MREQ and RD) indi-
cates the eZ80F91 device is fetching
an instruction from memory. This pin
is in a high-impedance state during
bus acknowledge cycles.
L6
WAIT
WAIT Request Schmitt Trigger
Driving the WAIT pin Low forces the
input, Active Low CPU to wait additional clock cycles for
an external peripheral or external
memory to complete its read or write
operation.
K6
RESET
Reset
Bidirectional,
Active Low
Schmitt Trigger
input or open
drain output
This signal is used to initialize the
eZ80F91, and/or allow the eZ80F91 to
signal when it resets. See the Reset
chapter on page 38 for the timing
details. This Schmitt Trigger input
allows for RC rise times.
56
J6
NMI
Nonmaskable Schmitt Trigger
The NMI input is a higher priority input
Interrupt
input, Active Low, than the maskable interrupts. It is
edge-triggered
interrupt
always recognized at the end of an
instruction, regardless of the state of
the interrupt enable control bits. This
input includes a Schmitt Trigger to
allow for RC rise times.
57
58
M7
L7
BUSREQ
BUSACK
Bus Request
Schmitt Trigger
External devices request the eZ80F91
input, Active Low device to release the memory inter-
face bus for their use by driving this
pin Low.
Bus Acknowl- Output, Active
edge
The eZ80F91 device responds to a
Low on BUSREQ making the address,
data, and control signals high imped-
ance, and by driving the BUSACK line
Low. During bus acknowledge cycles
ADDR[23:0], IORQ, and MREQ are
inputs.
Low
59
60
K7
H6
V
V
Power Supply
Ground
Power Supply.
Ground.
DD
SS
PS027004-0613
P R E L I M I N A R Y
Architectural Overview
eZ80F91 ASSP
Product Specification
10
Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
61
M8
RTC_X
Real-Time
Clock Crystal
Input
Input
This pin is the input to the low-power
32kHz crystal oscillator for the Real-
Time Clock. If the Real-Time Clock is
disabled or not used, this input must
IN
be left floating or tied to V to mini-
SS
mize any input current leakage.
62
L8
RTC_X
Real-Time
Clock Crystal
Output
Bidirectional
This pin is the output from the low-
power 32kHz crystal oscillator for the
Real-Time Clock. This pin is an input
when the RTC is configured to oper-
ate from 50/60 Hz input clock signals
and the 32 kHz crystal oscillator is dis-
abled.
OUT
63
J7
RTC_V
Real-Time
Clock Power
Supply
Power supply for the Real-Time Clock
and associated 32kHz oscillator. Iso-
lated from the power supply to the
remainder of the chip. A battery is
connected to this pin to supply con-
stant power to the Real-Time Clock
and 32kHz oscillator. If the Real-Time
Clock is disabled or not used this out-
DD
put must be tied to V
.
DD
64
65
K8
V
Ground
Ground.
SS
M9
HALT_SLP HALT and
Output, Active
A Low on this pin indicates that the
CPU has entered either HALT or
SLEEP Mode because of execution of
either a HALT or SLP instruction.
SLEEP Indica- Low
tor
66
67
68
69
H7
L9
J8
TMS
JTAG Test
Mode Select
Input
Input
JTAG Mode Select Input.
TCK
JTAG Test
Clock
JTAG and ZDI clock input.
Active High trigger event indicator.
TRIGOUT
TDI
JTAG Test Trig- Output
ger Output
K9
JTAG Test
Data In
Bidirectional
JTAG data input pin. Functions as ZDI
data I/O pin when JTAG is disabled.
This pin has an internal pull-up resis-
tor in the pad.
PS027004-0613
P R E L I M I N A R Y
Architectural Overview
eZ80F91 ASSP
Product Specification
11
Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
70
M10
TDO
JTAG Test
Data Out
Output
JTAG data output pin.
71
L10
TRST
JTAG Reset
Schmitt Trigger
JTAG reset input pin.
input, Active Low
72
73
M11
M12
V
Ground
Ground.
SS
PD0
GPIO Port D
Bidirectional
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port D pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port D is multiplexed with one
UART.
TxD0
IR_TxD
PD1
UARTTransmit Output
Data
This pin is used by the UART to trans-
mit asynchronous serial data. This
signal is multiplexed with PD0.
IrDA Transmit Output
Data
This pin is used by the IrDA encoder/
decoder to transmit serial data. This
signal is multiplexed with PD0.
74
L12
GPIO Port D
Bidirectional
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port D pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port D is multiplexed with one
UART.
RxD0
Receive Data Input
This pin is used by the UART to
receive asynchronous serial data.
This signal is multiplexed with PD1.
IR_RxD
IrDA Receive Input
Data
This pin is used by the IrDA encoder/
decoder to receive serial data. This
signal is multiplexed with PD1.
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Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
75
76
77
L11
K10
J9
PD2
GPIO Port D
Bidirectional
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port D pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port D is multiplexed with one
UART.
RTS0
PD3
Request to
Send
Output, Active
Low
Modem control signal from UART.
This signal is multiplexed with PD2.
GPIO Port D
Bidirectional
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port D pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port D is multiplexed with one
UART.
CTS0
PD4
Clear to Send Input, Active Low Modem status signal to the UART.
This signal is multiplexed with PD3.
GPIO Port D
Bidirectional
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port D pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port D is multiplexed with one
UART.
DTR0
Data Terminal Output, Active
Modem control signal to the UART.
This signal is multiplexed with PD4.
Ready
Low
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Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
Bidirectional
78
79
80
K12
K11
H8
PD5
GPIO Port D
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port D pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port D is multiplexed with one
UART.
DSR0
PD6
Data Set
Ready
Input, Active Low Modem status signal to the UART.
This signal is multiplexed with PD5.
GPIO Port D
Bidirectional
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port D pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port D is multiplexed with one
UART.
DCD0
PD7
Data Carrier
Detect
Input, Active Low Modem status signal to the UART.
This signal is multiplexed with PD6.
GPIO Port D
Bidirectional
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port D pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port D is multiplexed with one
UART.
RI0
Ring Indicator Input, Active Low Modem status signal to the UART.
This signal is multiplexed with PD7.
81
82
83
84
85
J11
J12
J10
G7
V
V
Power Supply
Ground
Power Supply.
DD
SS
Ground.
LOOP_FILT PLL Loop Filter Analog
Loop Filter pin for the Analog PLL.
Ground for Analog PLL.
PLL_V
Ground
SS
H12
X
System Clock Output
Oscillator Out-
put
This pin is the output of the onboard
crystal oscillator. When used, a crystal
must be connected between X and
OUT
IN
X
OUT
.
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Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
86
H11
X
System Clock Input
Oscillator Input
This pin is the input to the onboard
crystal oscillator for the primary sys-
tem clock. If an external oscillator is
used, its clock output must be con-
nected to this pin. When a crystal is
used, it must be connected between
IN
X
and X
.
IN
OUT
87
88
89
90
H10
H9
PLL_V
Power Supply
Power Supply
Ground
Power Supply for Analog PLL.
Power Supply.
DD
V
V
DD
SS
G12
G11
Ground.
PC0
GPIO Port C
Bidirectional with This pin is used for GPIO. It is individ-
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port C pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port C is multiplexed with one
UART.
TxD1
PC1
Transmit Data Output
This pin is used by the UART to trans-
mit asynchronous serial data. This
signal is multiplexed with PC0.
91
G10
GPIO Port C
Bidirectional with This pin is used for GPIO. It is individ-
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port C pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port C is multiplexed with one
UART.
RxD1
Receive Data Schmitt Trigger
input
This pin is used by the UART to
receive asynchronous serial data.
This signal is multiplexed with PC1.
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Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
Bidirectional with This pin is used for GPIO. It is individ-
92
93
94
G9
PC2
GPIO Port C
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port C pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port C is multiplexed with one
UART.
RTS1
PC3
Request to
Send
Output, Active
Low
Modem control signal from UART.
This signal is multiplexed with PC2.
F12
GPIO Port C
Bidirectional with This pin is used for GPIO. It is individ-
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port C pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port C is multiplexed with one
UART.
CTS1
PC4
Clear to Send Schmitt Trigger
Modem status signal to the UART.
input, Active Low This signal is multiplexed with PC3.
F11
GPIO Port C
Bidirectional with This pin is used for GPIO. It is individ-
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port C pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port C is multiplexed with one
UART.
DTR1
Data Terminal Output, Active
Modem control signal to the UART.
This signal is multiplexed with PC4.
Ready
Low
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16
Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
Bidirectional with This pin is used for GPIO. It is individ-
95
96
97
F10
PC5
GPIO Port C
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port C pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port C is multiplexed with one
UART.
DSR1
PC6
Data Set
Ready
Schmitt Trigger
input, Active Low This signal is multiplexed with PC5.
Modem status signal to the UART.
G8
GPIO Port C
Bidirectional with This pin is used for GPIO. It is individ-
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port C pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port C is multiplexed with one
UART.
DCD1
PC7
Data Carrier
Detect
Schmitt Trigger
input, Active Low This signal is multiplexed with PC6.
Modem status signal to the UART.
E12
GPIO Port C
Bidirectional with This pin is used for GPIO. It is individ-
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port C pin, when
programmed as output is selected to
be an open-drain or open-source out-
put. Port C is multiplexed with one
UART.
RI1
Ring Indicator Schmitt Trigger
Modem status signal to the UART.
input, Active Low This signal is multiplexed with PC7.
98
99
E11
F9
V
V
Power Supply
Ground
Power Supply.
Ground.
DD
SS
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Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
Bidirectional with This pin is used for GPIO. It is individ-
100
E10
PB0
GPIO Port B
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port B pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
IC0
Input Capture Schmitt Trigger
input
Input Capture A Signal to Timer 1.
This signal is multiplexed with PB0.
EC0
PB1
Event Counter Schmitt Trigger
input
Event Counter Signal to Timer 1. This
signal is multiplexed with PB0.
101
D12
GPIO Port B
Bidirectional with This pin is used for GPIO. It is individ-
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port B pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
IC1
Input Capture Schmitt Trigger
input
Input Capture B Signal to Timer 1.
This signal is multiplexed with PB1.
102
F8
PB2
GPIO Port B
Bidirectional with This pin is used for GPIO. It is individ-
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port B pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
SS
SPI Slave
Select
Schmitt Trigger
input, Active Low select a slave device in SPI Mode.
This signal is multiplexed with PB2.
The slave select input line is used to
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Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
Bidirectional with This pin is used for GPIO. It is individ-
103
D11
PB3
GPIO Port B
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port B pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
SCK
PB4
SPI Serial
Clock
Bidirectional with SPI serial clock. This signal is multi-
Schmitt Trigger
input
plexed with PB3.
104
E9
GPIO Port B
Bidirectional with This pin is used for GPIO. It is individ-
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port B pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
IC2
Input Capture Schmitt Trigger
input
Input Capture A Signal to Timer 3.
This signal is multiplexed with PB4.
105
D10
PB5
GPIO Port B
Bidirectional with This pin is used for GPIO. It is individ-
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port B pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
IC3
Input Capture Schmitt Trigger
input
Input Capture B Signal to Timer 3.
This signal is multiplexed with PB5.
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Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
Bidirectional with This pin is be used for GPIO. It is indi-
106
C12
PB6
GPIO Port B
Schmitt Trigger
input
vidually programmed as input or out-
put and is also used individually as an
interrupt input. Each Port B pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
MISO
PB7
SPI Master-In/ Bidirectional with The MISO line is configured as an
Slave-Out
Schmitt Trigger
input
input when the eZ80F91 device is an
SPI master device and as an output
when eZ80F91 is an SPI slave device.
This signal is multiplexed with PB6.
107
C11
GPIO Port B
Bidirectional with This pin is used for GPIO. It is individ-
Schmitt Trigger
input
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port B pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
MOSI
SPI Master Out Bidirectional with The MOSI line is configured as an out-
Slave In
Schmitt Trigger
input
put when the eZ80F91 device is an
SPI master device and as an input
when the eZ80F91 device is an SPI
slave device. This signal is multi-
plexed with PB7.
108
109
110
B12
A12
A11
V
Ground
Ground.
SS
2
2
SDA
SCL
I C Serial Data Bidirectional
This pin carries the I C data signal.
2
I C Serial
Clock
Bidirectional
This pin is used to receive and trans-
2
mit the I C clock.
111
B11
PHI
System Clock Output
This pin is an output driven by the
internal system clock. It is used by the
system for synchronization with the
eZ80F91 device.
112
113
C10
D9
V
V
Power Supply
Ground
Power Supply.
Ground.
DD
SS
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Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
114
115
116
A10
B10
E8
PA0
GPIO Port A
Bidirectional
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port A pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
PWM0
OC0
PWM
Output 0
Output
Output
This pin is used by Timer 3 for PWM
0. This signal is multiplexed with PA0.
Output Com-
pare 0
This pin is used by Timer 3 for Output
Compare 0. This signal is multiplexed
with PA0.
PA1
GPIO Port A
Bidirectional
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port A pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
PWM1
OC1
PWM
Output 1
Output
Output
This pin is used by Timer 3 for PWM
1. This signal is multiplexed with PA1.
Output Com-
pare 1
This pin is used by Timer 3 for Output
Compare 1. This signal is multiplexed
with PA1.
PA2
GPIO Port A
Bidirectional
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port A pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
PWM2
OC2
PWM
Output 2
Output
Output
This pin is used by Timer 3 for PWM
2. This signal is multiplexed with PA2.
Output Com-
pare 2
This pin is used by Timer 3 for Output
Compare 2. This signal is multiplexed
with PA2.
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21
Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
Bidirectional
117
B9
PA3
GPIO Port A
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port A pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
PWM3
OC3
PWM Output 3 Output
This pin is used by Timer 3 for PWM
3. This signal is multiplexed with PA3.
Output Com-
pare 3
Output
This pin is used by Timer 3 for Output
Compare 3 This signal is multiplexed
with PA3.
118
A9
PA4
GPIO Port A
Bidirectional
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port A pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
PWM0
TOUT0
PA5
PWM Output 0 Output
Inverted
This pin is used by Timer 3 for nega-
tive PWM 0. This signal is multiplexed
with PA4.
Timer Out
Output
This pin is used by Timer 0 timer-out
signal. This signal is multiplexed with
PA4.
119
C9
GPIO Port A
Bidirectional
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port A pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
PWM1
TOUT2
PWM Output 1 Output
Inverted
This pin is used by Timer 3 for nega-
tive PWM 1. This signal is multiplexed
with PA5.
Timer Out
Output
This pin is used by the Timer 2 timer-
out signal. This signal is multiplexed
with PA5.
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22
Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
Bidirectional
120
F7
PA6
GPIO Port A
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port A pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
PWM2
PWM Output 2 Output
Inverted
This pin is used by Timer 3 for nega-
tive PWM 2. This signal is multiplexed
with PA6.
EC1
PA7
Event Counter Input
Event Counter Signal to Timer 2. This
signal is multiplexed with PA6.
121
A8
GPIO Port A
Bidirectional
This pin is used for GPIO. It is individ-
ually programmed as input or output
and is also used individually as an
interrupt input. Each Port A pin, when
programmed as output is selected to
be an open-drain or open-source out-
put.
PWM3
PWM Output 3 Output
Inverted
This pin is used by Timer 3 for nega-
tive PWM 3. This signal is multiplexed
with PA7.
122
123
124
B8
C8
D8
V
V
Power Supply
Ground
Power Supply.
Ground.
DD
SS
CRS
MII Carrier
Sense
Input
This pin is used by the EMAC for the
MII Interface to the PHY (physical
layer). Carrier Sense is an asynchro-
nous signal.
125
126
A7
B7
COL
MII Collision
Detect
Input
This pin is used by the EMAC for the
MII Interface to the PHY. Collision
Detect is an asynchronous signal.
TxD3
MII Transmit
Data
Output
This pin is used by the EMAC for the
MII Interface to the PHY. Transmit
Data is synchronous to the rising-
edge of Tx_CLK.
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23
Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
127
128
129
130
131
C7
D7
A6
B6
C6
TxD2
MII Transmit
Data
Output
Output
Output
Output
Input
This pin is used by the Ethernet MAC
for the MII Interface to the PHY. Trans-
mit Data is synchronous to the rising-
edge of Tx_CLK.
TxD1
MII Transmit
Data
This pin is used by the Ethernet MAC
for the MII Interface to the PHY. Trans-
mit Data is synchronous to the rising-
edge of Tx_CLK.
TxD0
MII Transmit
Data
This pin is used by the Ethernet MAC
for the MII Interface to the PHY. Trans-
mit Data is synchronous to the rising-
edge of Tx_CLK.
Tx_EN
Tx_CLK
MII Transmit
Enable
This pin is used by the Ethernet MAC
for the MII Interface to the PHY. Trans-
mit Enable is synchronous to the ris-
ing-edge of Tx_CLK.
MII Transmit
Clock
This pin is used by the Ethernet MAC
for the MII Interface to the PHY. Trans-
mit Clock is the Nibble or Symbol
Clock provided by the MII PHY inter-
face.
132
E7
Tx_ER
MII Transmit
Error
Output
This pin is used by the Ethernet MAC
for the MII Interface to the PHY. Trans-
mit Error is synchronous to the rising-
edge of Tx_CLK.
133
134
135
A5
B5
D6
V
V
Power Supply
Ground
Power Supply.
Ground.
DD
SS
Rx_ER
MII Receive
Error
Input
Input
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Error is provided by the MII
PHY interface synchronous to the ris-
ing-edge of Rx_CLK.
136
C5
Rx_CLK
MII Receive
Clock
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Clock is the Nibble or Symbol
Clock provided by the MII PHY inter-
face.
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24
Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
137
138
139
140
141
142
143
A4
E6
B4
D5
C4
A3
B3
Rx_DV
RxD0
RxD1
RxD2
RxD3
MDC
MII Receive
Data Valid
Input
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Data Valid is provided by the
MII PHY interface synchronous to the
rising-edge of Rx_CLK.
MII Receive
Data
Input
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Data is provided by the MII
PHY interface synchronous to the ris-
ing-edge of Rx_CLK.
MII Receive
Data
Input
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Data is provided by the MII
PHY interface synchronous to the ris-
ing-edge of Rx_CLK.
MII Receive
Data
Input
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Data is provided by the MII
PHY interface synchronous to the ris-
ing-edge of Rx_CLK.
MII Receive
Data
Input
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Data is provided by the MII
PHY interface synchronous to the ris-
ing-edge of Rx_CLK.
MII Manage-
ment Data
Clock
Output
Bidirectional
This pin is used by the Ethernet MAC
for the MII Management Interface to
the PHY. The Ethernet MAC provides
the MII Management Data Clock to
the MII PHY interface.
MDIO
MII Manage-
ment Data
This pin is used by the Ethernet MAC
for the MII Management Interface to
the PHY. The Ethernet MAC sends
and receives the MII Management
Data to and from the MII PHY inter-
face.
144
A2
WP
Write Protect Schmitt Trigger
The Write Protect input is used by the
input, Active Low Flash Controller to protect the boot
block from write and erase operations.
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eZ80F91 ASSP
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25
System Clock Source Options
The following section describes five system clock source options.
System Clock
The eZ80F91 ASSP device’s internal clock, SCLK, is responsible for clocking all internal
logic. The SCLK source can be an external crystal oscillator, an internal PLL, or an inter-
nal 32kHz RTC oscillator. The SCLK source is selected by PLL Control Register 0.
RESET default is provided by the external crystal oscillator. For more details about
CLK_MUX values in the PLL Control Register 0, see Table 155 on page 270.
PHI
PHI is a device output driven by SCLK that is used for system synchronization to the
eZ80F91 ASSP device. PHI is used as the reference clock for all AC characteristics; for
details, see the AC Characteristics chapter on page 343.
External Crystal Oscillator
An externally-driven oscillator operates in two modes. In one mode, the XIN pin is driven
by a oscillator from DC up to 50 MHz when the XOUT pin is not connected. In the other
mode, the XIN and XOUT pins are driven by a crystal circuit.
Crystals recommended by Zilog are defined to be a 50MHz–3 overtone circuit or 1–
10MHz range fundamental for PLL operation. For details, see the On-Chip Oscillators
chapter on page 332.
Real Time Clock
An internal 32 kHz real-time clock crystal oscillator driven by either the on-chip 32768
Hz crystal oscillator or a 50/60 Hz power-line frequency input. While intended for time-
keeping, the RTC 32 kHz oscillator is selected as an SCLK. RTC_VDD and RTC_VSS pro-
vides an isolated power supply to ensure RTC operation in the event of loss of line power
when a battery is provided. For more details, see the Real-Time Clock chapter on page
155.
PLL Clock
The eZ80F91 MCU’s internal PLL is driven by external crystals or external crystal oscilla-
tors in the range of 1MHz to 10MHz, and generates an SCLK up to 50MHz. For more
details, see the Phase-Locked Loop chapter on page 265.
SCLK Source Selection Example
For additional SCLK source selection examples, refer to the Crystal Oscillator/Resonator
Guidelines for eZ80 and eZ80Acclaim! Devices Technical Note (TN0013), which is avail-
able free for download from the Zilog website.
PS027004-0613
P R E L I M I N A R Y
Architectural Overview
eZ80F91 ASSP
Product Specification
26
Register Map
All on-chip peripheral registers are accessed in the I/O address space. All I/O operations
employ 16-bit addresses. The upper byte of the 24-bit address bus is undefined during all
I/O operations (ADDR[23:16] = XX). All I/O operations using 16-bit addresses within the
0000h–00FFhrange are routed to the on-chip peripherals. External I/O chip selects are
not generated if the address space programmed for the I/O chip selects overlap the
0000h–00FFhaddress range.
Registers at unused addresses within the 0000h–00FFhrange assigned to on-chip periph-
erals are not implemented. Read access to such addresses returns unpredictable values,
and write access produces no effect.
Table 3 presents the register map for the eZ80F91 device.
Table 3. Register Map
Address
(hex)
Reset
(hex) Access
CPU
Page
No
Mnemonic
Name
Product ID
0000
0001
0002
ZDI_ID_L
eZ80 Product ID Low Byte Register
eZ80 Product ID High Byte Register
eZ80 Product ID Revision Register
08
00
XX
R
R
R
255
255
255
ZDI_ID_H
ZDI_ID_REV
Interrupt Priority
0010
0011
0012
0013
0014
0015
INT_P0
INT_P1
INT_P2
INT_P3
INT_P4
INT_P5
Interrupt Priority Register, Byte 0
Interrupt Priority Register, Byte 1
Interrupt Priority Register, Byte 2
Interrupt Priority Register, Byte 3
Interrupt Priority Register, Byte 4
Interrupt Priority Register, Byte 5
00
00
00
00
00
00
R/W
R/W
R/W
R/W
R/W
R/W
61
61
61
61
61
61
Ethernet Media Access Controller
0020
0021
0022
0023
0024
EMAC_TEST
EMAC_CFG1
EMAC_CFG2
EMAC_CFG3
EMAC_CFG4
EMAC Test Register
00
00
37
0F
00
R/W
R/W
R/W
R/W
R/W
302
303
305
306
307
EMAC Configuration Register
EMAC Configuration Register
EMAC Configuration Register
EMAC Configuration Register
PS027004-0613
P R E L I M I N A R Y
Register Map
eZ80F91 ASSP
Product Specification
27
Table 3. Register Map (Continued)
Address
(hex)
Reset
(hex) Access
CPU
Page
No
Mnemonic
Name
0025
0026
0027
0028
0029
002A
002B
EMAC_STAD_0
EMAC_STAD_1
EMAC_STAD_2
EMAC_STAD_3
EMAC_STAD_4
EMAC_STAD_5
EMAC_TPTV_L
EMAC Station Address Byte 0
EMAC Station Address Byte 1
EMAC Station Address Byte 2
EMAC Station Address Byte 3
EMAC Station Address Byte 4
EMAC Station Address Byte 5
00
00
00
00
00
00
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
308
308
308
308
308
308
309
EMAC Transmit Pause Timer Value Low
Byte
002C
EMAC_TPTV_H
EMAC Transmit Pause Timer Value High
Byte
00
R/W
309
002D
002E
002F
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
003A
003B
003C
003D
003E
003F
EMAC_IPGT
EMAC Inter-Packet Gap
15
0C
12
00
06
00
00
00
00
00
00
00
00
00
00
00
00
00
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
309
312
312
313
314
315
316
316
316
316
316
316
316
316
317
318
319
319
320
EMAC_IPGR1
EMAC_IPGR2
EMAC_MAXF_L
EMAC_MAXF_H
EMAC_AFR
EMAC Non-Back-Back IPG
EMAC Non-Back-Back IPG
EMAC Maximum Frame Length Low Byte
EMAC Maximum Frame Length High Byte
EMAC Address Filter Register
EMAC Hash Table Byte 0
EMAC_HTBL_0
EMAC_HTBL_1
EMAC_HTBL_2
EMAC_HTBL_3
EMAC_HTBL_4
EMAC_HTBL_5
EMAC_HTBL_6
EMAC_HTBL_7
EMAC_MIIMGT
EMAC_CTLD_L
EMAC_CTLD_H
EMAC_RGAD
EMAC_FIAD
EMAC Hash Table Byte 1
EMAC Hash Table Byte 2
EMAC Hash Table Byte 3
EMAC Hash Table Byte 4
EMAC Hash Table Byte 5
EMAC Hash Table Byte 6
EMAC Hash Table Byte 7
EMAC MII Management Register
EMAC PHY Configuration Data Low Byte
EMAC PHY Configuration Data High Byte
EMAC PHY Register Address Register
EMAC PHY Unit Select Address Register
PS027004-0613
P R E L I M I N A R Y
Register Map
eZ80F91 ASSP
Product Specification
28
Table 3. Register Map (Continued)
Address
(hex)
Reset
(hex) Access
CPU
Page
No
Mnemonic
Name
0040
0041
0042
EMAC_PTMR
EMAC_RST
EMAC_TLBP_L
EMAC Transmit Polling Timer Register
EMAC Reset Control Register
00
20
00
R/W
R/W
R/W
320
321
322
EMAC Transmit Lower Boundary Pointer
Low Byte
0043
EMAC_TLBP_H
EMAC Transmit Lower Boundary Pointer
High Byte
00
R/W
322
0044
0045
0046
0047
EMAC_BP_L
EMAC_BP_H
EMAC_BP_U
EMAC_RHBP_L
EMAC Boundary Pointer Low Byte
EMAC Boundary Pointer High Byte
EMAC Boundary Pointer Upper Byte
00
C0
FF
00
R/W
R/W
R/W
R/W
323
323
323
324
EMAC Receive High Boundary Pointer
Low Byte
0048
EMAC_RHBP_H
EMAC Receive High Boundary Pointer
High Byte
00
R/W
325
0049
004A
004B
004C
004D
004E
004F
0050
0051
0052
EMAC_RRP_L
EMAC_RRP_H
EMAC_BUFSZ
EMAC_IEN
EMAC Receive Read Pointer Low Byte
EMAC Receive Read Pointer High Byte
EMAC Buffer Size Register
00
00
00
00
00
00
00
00
00
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
325
326
326
327
329
330
331
331
332
333
EMAC Interrupt Enable Register
EMAC Interrupt Status Register
EMAC_ISTAT
EMAC_PRSD_L
EMAC_PRSD_H
EMAC_MIISTAT
EMAC_RWP_L
EMAC_RWP_H
EMAC PHY Read Status Data Low Byte
EMAC PHY Read Status Data High Byte
EMAC MII Status Register
EMAC Receive Write Pointer Low Byte
EMAC Receive Write Pointer High Byte
Ethernet Media Access Controller, continued
0053
0054
0055
EMAC_TRP_L
EMAC_TRP_H
EMAC Transmit Read Pointer Low Byte
EMAC Transmit Read Pointer High Byte
00
00
20
R/W
R/W
R/W
333
334
334
EMAC_BLKSLFT_L EMAC Receive Blocks Left Low Byte Reg-
ister
0056
0057
EMAC_BLKSLFT_H EMAC Receive Blocks Left High Byte
Register
00
R/W
R/W
335
336
EMAC_FDATA_L
EMAC FIFO Data Low Byte
XX
PS027004-0613
P R E L I M I N A R Y
Register Map
eZ80F91 ASSP
Product Specification
29
Table 3. Register Map (Continued)
Address
(hex)
Reset
(hex) Access
CPU
Page
No
Mnemonic
Name
0058
0059
PLL
EMAC_FDATA_H
EMAC_FFLAGS
EMAC FIFO Data High Byte
EMAC FIFO Flags Register
0X
33
R/W
R/W
336
337
005C
005D
005E
005F
PLL_DIV_L
PLL_DIV_H
PLL_CTL0
PLL_CTL1
PLL Divider Low Byte Register
PLL Divider High Byte Register
PLL Control Register 0
00
00
00
00
W
W
272
273
273
275
R/W
R/W
PLL Control Register 1
Timers and PWM
0060
0061
0062
0063
TMR0_CTL
Timer 0 Control Register
00
00
R/W
R/W
R/W
R
132
133
135
136
138
137
139
132
133
135
136
138
137
139
139
140
TMR0_IER
Timer 0 Interrupt Enable Register
Timer 0 Interrupt Identification Register
Timer 0 Data Low Byte Register
Timer 0 Reload Low Byte Register
Timer 0 Data High Byte Register
Timer 0 Reload High Byte Register
Timer 1 Control Register
TMR0_IIR
00
TMR0_DR_L
TMR0_RR_L
TMR0_DR_H
TMR0_RR_H
TMR1_CTL
XX
XX
XX
XX
00
W
0064
R
W
0065
0066
0067
0068
R/W
R/W
R/W
R
TMR1_IER
Timer 1 Interrupt Enable Register
Timer 1 Interrupt Identification Register
Timer 1 Data Low Byte Register
Timer 1 Reload Low Byte Register
Timer 1 Data High Byte Register
Timer 1 Reload High Byte Register
Timer 1 Input Capture Control Register
00
TMR1_IIR
00
TMR1_DR_L
TMR1_RR_L
TMR1_DR_H
TMR1_RR_H
TMR1_CAP_CTL
TMR1_CAPA_L
XX
XX
XX
XX
XX
XX
W
0069
R
W
006A
006B
R/W
R/W
Timer 1 Capture Value A Low Byte Regis-
ter
006C
006D
TMR1_CAPA_H
TMR1_CAPB_L
Timer 1 Capture Value A High Byte Regis-
ter
XX
XX
R/W
R/W
141
141
Timer 1 Capture Value B Low Byte Regis-
ter
PS027004-0613
P R E L I M I N A R Y
Register Map
eZ80F91 ASSP
Product Specification
30
Table 3. Register Map (Continued)
Address
(hex)
Reset
(hex) Access
CPU
Page
No
Mnemonic
Name
006E
TMR1_CAPB_H
Timer 1 Capture Value B High Byte Regis-
ter
XX
R/W
142
006F
0070
0071
0072
TMR2_CTL
TMR2_IER
Timer 2 Control Register
00
00
R/W
R/W
R/W
R
132
133
135
136
138
137
139
132
133
135
136
138
137
139
153
154
156
139
157
140
Timer 2 Interrupt Enable Register
Timer 2 Interrupt Identification Register
Timer 2 Data Low Byte Register
Timer 2 Reload Low Byte Register
Timer 2 Data High Byte Register
Timer 2 Reload High Byte Register
Timer 3 Control Register
TMR2_IIR
00
TMR2_DR_L
TMR2_RR_L
TMR2_DR_H
TMR2_RR_H
TMR3_CTL
TMR3_IER
XX
XX
XX
XX
00
W
0073
R
W
0074
0075
0076
0077
R/W
R/W
R/W
R
Timer 3 Interrupt Enable Register
Timer 3 Interrupt Identification Register
Timer 3 Data Low Byte Register
Timer 3 Reload Low Byte Register
Timer 3 Data High Byte Register
Timer 3 Reload High Byte Register
PWM Control Register 1
00
TMR3_IIR
00
TMR3_DR_L
TMR3_RR_L
TMR3_DR_H
TMR3_RR_H
PWM_CTL1
PWM_CTL2
PWM_CTL3
TMR3_CAP_CTL
PWM0R_L
XX
XX
XX
XX
00
W
0078
R
W
0079
007A
007B
R/W
R/W
R/W
R/W
R/W
R/W
PWM Control Register 2
00
PWM Control Register 3
00
Timer 3 Input Capture Control Register
PWM 0 Rising-Edge Low Byte Register
00
007C
007D
007E
XX
XX
TMR3_CAPA_L
Timer 3 Capture Value A Low Byte Regis-
ter
PWM0R_H
PWM 0 Rising-Edge High Byte Register
XX
XX
R/W
R/W
157
141
TMR3_CAPA_H
Timer 3 Capture Value A High Byte Regis-
ter
PWM1R_L
PWM 1 Rising-Edge Low Byte Register
XX
XX
R/W
R/W
157
141
TMR3_CAPB_L
Timer 3 Capture Value B Low Byte Regis-
ter
PS027004-0613
P R E L I M I N A R Y
Register Map
eZ80F91 ASSP
Product Specification
31
Table 3. Register Map (Continued)
Address
(hex)
Reset
(hex) Access
CPU
Page
No
Mnemonic
Name
007F
0080
0081
0082
0083
0084
0085
0086
0087
0088
PWM1R_H
PWM 1 Rising-Edge High Byte Register
XX
XX
R/W
R/W
157
142
TMR3_CAPB_H
Timer 3 Capture Value B High Byte Regis-
ter
PWM2R_L
PWM 2 Rising-Edge Low Byte Register
XX
00
R/W
R/W
157
132
TMR3_OC_CTL1
Timer 3 Output Compare Control Register
1
PWM2R_H
PWM 2 Rising-Edge High Byte Register
XX
00
R/W
R/W
157
132
TMR3_OC_CTL2
Timer 3 Output Compare Control Register
2
PWM3R_L
PWM 3 Rising-Edge Low Byte Register
XX
XX
R/W
R/W
157
144
TMR3_OC0_L
Timer 3 Output Compare 0 Value Low Byte
Register
PWM3R_H
PWM 3 Rising-Edge High Byte Register
XX
XX
R/W
R/W
157
145
TMR3_OC0_H
Timer 3 Output Compare 0 Value High
Byte Register
PWM0F_L
PWM 0 Falling-Edge Low Byte Register
XX
XX
R/W
R/W
158
144
TMR3_OC1_L
Timer 3 Output Compare 1 Value Low Byte
Register
PWM0F_H
PWM 0 Falling-Edge High Byte Register
XX
XX
R/W
R/W
158
145
TMR3_OC1_H
Timer 3 Output Compare 1 Value High
Byte Register
PWM1F_L
PWM 1 Falling-Edge Low Byte Register
XX
XX
R/W
R/W
158
144
TMR3_OC2_L
Timer 3 Output Compare 2 Value Low Byte
Register
PWM1F_H
PWM 1 Falling-Edge High Byte Register
XX
XX
R/W
R/W
158
145
TMR3_OC2_H
Timer 3 Output Compare 2 Value High
Byte Register
PWM2F_L
PWM 2 Falling-Edge Low Byte Register
XX
XX
R/W
R/W
158
144
TMR3_OC3_L
Timer 3 Output Compare 3 Value Low Byte
Register
PS027004-0613
P R E L I M I N A R Y
Register Map
eZ80F91 ASSP
Product Specification
32
Table 3. Register Map (Continued)
Address
(hex)
Reset
(hex) Access
CPU
Page
No
Mnemonic
Name
0089
PWM2F_H
PWM 2 Falling-Edge High Byte Register
XX
XX
R/W
R/W
158
145
TMR3_OC3_H
Timer 3 Output Compare 3 Value High
Byte Register
008A
008B
PWM3F_L
PWM3F_H
PWM 3 Falling-Edge Low Byte Register
PWM 3 Falling-Edge High Byte Register
XX
XX
R/W
R/W
158
158
Watchdog Timer
0093
0094
WDT_CTL
WDT_RR
Watchdog Timer Control Register
Watchdog Timer Reset Register
08/28
XX
R/W
W
118
120
General-Purpose Input/Output Ports
0096
0097
0098
0099
009A
009B
009C
009D
009E
009F
00A0
00A1
00A2
00A3
00A4
00A5
00A6
00A7
PA_DR
Port A Data Register
XX
FF
00
00
XX
FF
00
00
XX
FF
00
00
XX
FF
00
00
00
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
55
56
56
57
55
56
56
57
55
56
56
57
55
56
56
57
56
56
PA_DDR
PA_ALT1
PA_ALT2
PB_DR
Port A Data Direction Register
Port A Alternate Register 1
Port A Alternate Register 2
Port B Data Register
PB_DDR
PB_ALT1
PB_ALT2
PC_DR
Port B Data Direction Register
Port B Alternate Register 1
Port B Alternate Register 2
Port C Data Register
PC_DDR
PC_ALT1
PC_ALT2
PD_DR
Port C Data Direction Register
Port C Alternate Register 1
Port C Alternate Register 2
Port D Data Register
PD_DDR
PD_ALT1
PD_ALT2
PA_ALT0
PB_ALT0
Port D Data Direction Register
Port D Alternate Register 1
Port D Alternate Register 2
Port A Alternate Register 0
Port B Alternate Register 0
W
Chip Select/Wait State Generator
00A8 CS0_LBR
Chip Select 0 Lower Bound Register
00
R/W
85
PS027004-0613
P R E L I M I N A R Y
Register Map
eZ80F91 ASSP
Product Specification
33
Table 3. Register Map (Continued)
Address
(hex)
Reset
(hex) Access
CPU
Page
No
Mnemonic
CS0_UBR
CS0_CTL
CS1_LBR
CS1_UBR
CS1_CTL
CS2_LBR
CS2_UBR
CS2_CTL
CS3_LBR
CS3_UBR
CS3_CTL
Name
00A9
00AA
00AB
00AC
00AD
00AE
00AF
00B0
00B1
00B2
00B3
Chip Select 0 Upper Bound Register
Chip Select 0 Control Register
FF
E8
00
00
00
00
00
00
00
00
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
86
87
85
86
87
85
86
87
85
86
87
Chip Select 1 Lower Bound Register
Chip Select 1 Upper Bound Register
Chip Select 1 Control Register
Chip Select 2 Lower Bound Register
Chip Select 2 Upper Bound Register
Chip Select 2 Control Register
Chip Select 3 Lower Bound Register
Chip Select 3 Upper Bound Register
Chip Select 3 Control Register
Random Access Memory Control
00B4
00B5
00B6
00B7
RAM_CTL
RAM Control Register
C0
FF
00
00
R/W
R/W
R/W
R/W
94
95
96
96
RAM_ADDR_U
MBIST_GPR
MBIST_EMR
RAM Address Upper Byte Register
General Purpose RAM MBIST Control
Ethernet MAC RAM MBIST Control
Serial Peripheral Interface
00B8
SPI_BRG_L
SPI Baud Rate Generator Low Byte Regis-
ter
02
00
R/W
R/W
209
209
00B9
SPI_BRG_H
SPI Baud Rate Generator High Byte Reg-
ister
00BA
00BB
00BC
SPI_CTL
SPI_SR
SPI Control Register
04
00
R/W
R
210
211
212
212
SPI Status Register
SPI_TSR
SPI_RBR
SPI Transmit Shift Register
SPI Receive Buffer Register
XX
XX
W
R
Infrared Encoder/Decoder
00BF IR_CTL
Infrared Encoder/Decoder Control
00
R/W
201
PS027004-0613
P R E L I M I N A R Y
Register Map
eZ80F91 ASSP
Product Specification
34
Table 3. Register Map (Continued)
Address
(hex)
Reset
(hex) Access
CPU
Page
No
Mnemonic
Name
Universal Asynchronous Receiver/Transmitter 0 (UART0)
00C0
UART0_RBR
UART0_THR
UART0_BRG_L
UART 0 Receive Buffer Register
UART 0 Transmit Holding Register
XX
XX
02
R
W
184
184
182
UART 0 Baud Rate Generator Low Byte
Register
R/W
00C1
00C2
UART0_IER
UART 0 Interrupt Enable Register
00
00
R/W
R/W
185
183
UART0_BRG_H
UART 0 Baud Rate Generator High Byte
Register
UART0_IIR
UART 0 Interrupt Identification Register
UART 0 FIFO Control Register
UART 0 Line Control Register
UART 0 Modem Control Register
UART 0 Line Status Register
01
00
00
00
60
XX
00
R
W
186
187
188
191
192
194
195
UART0_FCTL
UART0_LCTL
UART0_MCTL
UART0_LSR
UART0_MSR
UART0_SPR
00C3
00C4
00C5
00C6
00C7
R/W
R/W
R
UART 0 Modem Status Register
UART 0 Scratch Pad Register
R
R/W
2
I C
2
00C8
00C9
00CA
00CB
I2C_SAR
I2C_XSAR
I2C_DR
I C Slave Address Register
00
00
00
00
R/W
R/W
R/W
R/W
226
227
227
228
2
I C Extended Slave Address Register
2
I C Data Register
2
I2C_CTL
I C Control Register
General-Purpose Input/Output Ports
00CE
00CF
00CC
PC_ALT0
PD_ALT0
I2C_SR
Port C Alternate Register 0
Port D Alternate Register 0
00
00
F8
00
XX
W
W
R
56
56
2
I C Status Register
230
232
233
2
I2C_CCR
I2C_SRR
I C Clock Control Register
W
W
2
00CD
I C Software Reset Register
PS027004-0613
P R E L I M I N A R Y
Register Map
eZ80F91 ASSP
Product Specification
35
Table 3. Register Map (Continued)
Address
(hex)
Reset
(hex) Access
CPU
Page
No
Mnemonic
Name
Universal Asynchronous Receiver/Transmitter 1 (UART1)
00D0
UART1_RBR
UART1_THR
UART1_BRG_L
UART 1 Receive Buffer Register
UART 1 Transmit Holding Register
XX
XX
02
R
W
184
184
182
UART 1 Baud Rate Generator Low Byte
Register
R/W
00D1
UART1_IER
UART 1 Interrupt Enable Register
00
00
R/W
R/W
185
183
UART1_BRG_H
UART 1 Baud Rate Generator High Byte
Register
00D2
00D3
UART1_IIR
UART 1 Interrupt Identification Register
UART 1 FIFO Control Register
UART 1 Line Control Register
01
00
00
R
W
186
187
188
UART1_FCTL
UART1_LCTL
R/W
Universal Asynchronous Receiver/Transmitter 0 (UART0)
00D4
00D5
00D6
00D7
UART1_MCTL
UART1_LSR
UART1_MSR
UART1_SPR
UART 1 Modem Control Register
UART 1 Line Status Register
UART 1 Modem Status Register
UART 1 Scratch Pad Register
00
60
XX
00
R/W
R/W
R/W
R/W
191
192
194
195
Low-Power Control
00DB
00DC
CLK_PPD1
CLK_PPD2
Clock Peripheral Power-Down Register 1
Clock Peripheral Power-DownRegister 2
00
00
R/W
R/W
47
48
Real-Time Clock
00E0
00E1
00E2
00E3
00E4
00E5
00E6
00E7
00E8
RTC_SEC
RTC Seconds Register
RTC Minutes Register
XX
XX
XX
0X
XX
XX
XX
XX
XX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
161
162
163
164
165
166
167
168
169
RTC_MIN
RTC_HRS
RTC_DOW
RTC_DOM
RTC_MON
RTC_YR
RTC Hours Register
RTC Day-of-the-Week Register
RTC Day-of-the-Month Register
RTC Month Register
RTC Year Register
RTC_CEN
RTC_ASEC
RTC Century Register
RTC Alarm Seconds Register
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P R E L I M I N A R Y
Register Map
eZ80F91 ASSP
Product Specification
36
Table 3. Register Map (Continued)
Address
(hex)
Reset
(hex) Access
CPU
Page
No
Mnemonic
RTC_AMIN
RTC_AHRS
RTC_ADOW
RTC_ACTRL
RTC_CTRL
Name
00E9
00EA
00EB
00EC
00ED
RTC Alarm Minutes Register
RTC Alarm Hours Register
RTC Alarm Day-of-the-Week Register
RTC Alarm Control Register
RTC Control Register
XX
XX
0X
00
R/W
R/W
R/W
R/W
R/W
170
171
172
173
174
x0xxxx0
0b/
x0xxxx1
0b
Chip Select Bus Mode Control
00F0
00F1
00F2
00F3
CS0_BMC
CS1_BMC
CS2_BMC
CS3_BMC
Chip Select 0 Bus Mode Control Register
Chip Select 1 Bus Mode Control Register
Chip Select 2 Bus Mode Control Register
Chip Select 3 Bus Mode Control Register
02
02
02
02
R/W
R/W
R/W
R/W
88
88
88
88
Flash Memory Control
00F5
00F6
00F7
00F8
00F9
00FA
00FB
00FC
00FD
00FE
00FF
FLASH_KEY
FLASH_DATA
FLASH_ADDR_U
FLASH_CTL
Flash Key Register
00
XX
00
88
01
FF
00
00
00
00
00
W
102
103
104
105
106
107
108
109
111
112
112
Flash Data Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Flash Address Upper Byte Register
Flash Control Register
FLASH_FDIV
FLASH_PROT
FLASH_IRQ
Flash Frequency Divider Register
Flash Write/Erase Protection Register
Flash Interrupt Control Register
Flash Page Select Register
Flash Row Select Register
Flash Column Select Register
Flash Program Control Register
FLASH_PAGE
FLASH_ROW
FLASH_COL
FLASH_PGCTL
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P R E L I M I N A R Y
Register Map
eZ80F91 ASSP
Product Specification
37
eZ80 CPU Core
The eZ80 CPU is the first 8-bit CPU to support 16MB linear addressing. Each software
module or task under a real-time executive or operating system operates in Z80-compati-
ble (64KB) mode or full 24-bit (16MB) address mode.
The CPU instruction set is a superset of the instruction sets for the Z80 and Z180 CPUs.
Z80 and Z180 programs can be executed on an eZ80 CPU with little or no modification.
Features
The features of eZ80 CPU include:
•
•
•
•
•
•
•
•
Code-compatible with Z80 and Z180 products
24-bit linear address space
Single-cycle instruction fetch
Pipelined fetch, decode, and execute
Dual stack pointers for ADL (24-bit) and Z80 (16-bit) memory modes
24-bit CPU registers and Arithmetic Logic Unit (ALU)
Debug support
Nonmaskable Interrupt (NMI), plus support for 128 maskable vectored interrupts
New Instructions
Two new eZ80 CPU instructions load/unload the I Register with a 16-bit value. These new
instructions are:
•
•
LD I,HL (ED C7)
LD HL,I (ED D7)
For more information about the eZ80 CPU, its instruction set, and eZ80 programming,
refer to the eZ80 CPU User Manual (UM0077), which is available free for download from
the Zilog website.
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P R E L I M I N A R Y
eZ80 CPU Core
eZ80F91 ASSP
Product Specification
38
Reset
The Reset controller within the eZ80F91 device features a consistent reset function for all
types of resets that affects the system. A system reset, referred in this document as RESET,
returns the eZ80F91 to a defined state. All internal registers affected by a RESET return to
their default conditions. RESET configures the GPIO port pins as inputs and clears the
CPU’s Program Counter to 000000h. Program code execution ceases during RESET.
The events that cause a RESET are:
•
•
•
•
•
•
Power-On Reset (POR)
Low-Voltage Brown-Out (VBO)
External RESET pin assertion
Watchdog Timer (WDT) time-out when configured to generate a RESET
Real-Time Clock alarm with the CPU in low-power SLEEP Mode
Execution of a Debug RESET command
During RESET, an internal RESET mode timer holds the system in RESET for 1025 sys-
tem clock (SCLK) cycles to allow sufficient time for the primary crystal oscillator to stabi-
lize. For internal RESET sources, the RESET mode timer begins incrementing on the next
rising edge of SCLK following deactivation of the signal that is initiating the RESET
event. For external RESET pin assertion, the RESET mode timer begins on the next rising
edge of SCLK following assertion of the RESET pin for three consecutive SCLK cycles.
The default clock source for SCLK on RESET is the crystal input (XIN). See the
CLK_MUX values in the PLL Control Register 0 in Table 155 on page 270.
Note:
External Reset Input and Indicator
The eZ80F91 RESET pin functions as both open-drain (active Low) RESET mode indica-
tor and active Low RESET input. When a RESET event occurs, the internal circuitry
begins driving the RESET pin Low. The RESET pin is held Low by the internal circuitry
until the internal RESET mode timer times out. If the external reset signal is released prior
to the end of the 1025 count time-out, program execution begins following the RESET
mode time-out. If the external reset signal is released after the end of the 1025 count time-
out, then program execution begins following release of the RESET input (the RESET pin
is High for four consecutive SCLK cycles).
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P R E L I M I N A R Y
Reset
eZ80F91 ASSP
Product Specification
39
Power-On Reset
A POR occurs every time the supply voltage to the part rises from below the Voltage
Brown-Out threshold (VVBO) to above the POR voltage threshold (VPOR). The internal
bandgap-referenced voltage detector sends a continuous RESET signal to the Reset con-
troller until the supply voltage (VCC) exceeds the POR voltage threshold. After VCC rises
above VPOR, an on-chip analog delay element briefly maintains the RESET signal to the
Reset controller. After this analog delay element times out, the Reset controller holds the
eZ80F91 in RESET until the RESET mode timer expires. POR operation is shown in
Figure 3. The signals in Figure 3 are not drawn to scale but for illustration purposes only.
VCC = 3.3V
V
POR
V
VBO
Program Execution
VCC = 0.0V
System Clock
Oscillator
Startup
Internal RESET
Signal
TANA
RESET mode timer delay
Figure 3. Power-On Reset Operation
Voltage Brown-Out Reset
If the supply voltage (VCC) drops below the VVBO after program execution begins, the
eZ80F91 device resets. The VBO protection circuitry detects the low supply voltage and
initiates a RESET via the Reset controller. The eZ80F91 remains in RESET until the sup-
ply voltage again returns above the POR voltage threshold (VPOR) and the Reset controller
releases the internal RESET signal. The VBO circuitry rejects short negative brown-out
pulses to prevent spurious RESET events.
VBO operation is shown in Figure 4. The signals in the figure are not drawn to scale but
for illustration purposes only.
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P R E L I M I N A R Y
Reset
eZ80F91 ASSP
Product Specification
40
V
= 3.3V
V
= 3.3V
CC
CC
V
POR
V
VBO
Voltage
Brown-out
Program Execution
Program Execution
System Clock
Internal RESET
Signal
RESET mode
timer delay
T
ANA
Figure 4. Voltage Brown-Out Reset Operation
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P R E L I M I N A R Y
Reset
eZ80F91 ASSP
Product Specification
41
Low-Power Modes
The eZ80F91 device provides a range of power-saving features. The highest level of
power reduction is provided by SLEEP Mode with all peripherals disabled, including
VBO. The next level of power reduction is provided by the HALT instruction. The most
basic level of power reduction is provided by the clock peripheral power-down registers.
SLEEP Mode
Execution of the CPU’s SLP instruction puts the eZ80F91 device into SLEEP Mode. In
SLEEP Mode, the operating characteristics are:
•
•
•
•
•
The primary crystal oscillator is disabled.
The system clock is disabled.
The CPU is idle.
The Program Counter (PC) stops incrementing.
The 32 kHz crystal oscillator continues to operate and drives the real-time clock and
WDT (if WDT is configured to operate from the 32 kHz oscillator).
The CPU is brought out of SLEEP Mode by any of the following operations:
•
•
•
A RESET via the external RESET pin driven Low.
A RESET via a real-time clock alarm.
A RESET via a WDT time-out (if running out of the 32 kHz oscillator and configured
to generate a RESET on time-out).
•
•
A RESET via execution of a Debug RESET command.
A RESET via the Low-Voltage Brown-Out (VBO) detection circuit, if enabled.
After exiting SLEEP Mode, the standard RESET delay occurs to allow the primary crystal
oscillator to stabilize. For more information, see Figure 4 on page 40.
HALT Mode
Execution of the CPU’s HALT instruction puts the eZ80F91 device into HALT Mode. In
HALT Mode, the operating characteristics are:
•
The primary crystal oscillator is enabled and continues to operate.
PS027004-0613
P R E L I M I N A R Y
Low-Power Modes
eZ80F91 ASSP
Product Specification
42
•
•
•
The system clock is enabled and continues to operate.
The CPU is idle.
The PC stops incrementing.
The CPU is brought out of HALT Mode by any of the following operations:
•
•
•
•
A nonmaskable interrupt (NMI).
A maskable interrupt.
A RESET via the external RESET pin driven Low.
A Watchdog Timer time-out (if, configured to generate either an NMI or RESET upon
time-out).
•
•
A RESET via execution of a Debug RESET command.
A RESET via the Low-Voltage Brown-Out detection circuit, if enabled.
To minimize current in HALT Mode, the system clock must be gated-off for all unused on-
chip peripherals via the Clock Peripheral Power-Down Registers.
HALT Mode and the EMAC Function
When the CPU is in HALT Mode, the eZ80F91 device’s EMAC block cannot be disabled
as other peripherals can. On receipt of an Ethernet packet, a maskable Receive interrupt is
generated by the EMAC block, just as it would be in a non-halt mode. Accordingly, the
processor wakes up and continues with the user-defined application.
Clock Peripheral Power-Down Registers
To reduce power, the Clock Peripheral Power-Down Registers allow the system clock to
be blocked to unused on-chip peripherals. On RESET, all peripherals are enabled. The
clock to unused peripherals are gated off by setting the appropriate bit in the Clock Periph-
eral Power-Down Registers to 1. When powered down, the peripherals are completely dis-
abled. To reenable, the bit in the Clock Peripheral Power-Down Registers must be cleared
to 0.
Additionally, the VBO_OFF bit of CLK_PPD2 is used to disable the VBO detection cir-
cuit and thereby significantly reduce DC current consumption (see Table 235 on page 339)
when this function is not required.
Many peripherals features separate enable/disable control bits that must be appropriately
set for operation. These peripheral specific enable/disable bits do not provide the same
level of power reduction as the Clock Peripheral Power-Down Registers. When powered
PS027004-0613
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Low-Power Modes
eZ80F91 ASSP
Product Specification
43
down, the individual peripheral control register is not accessible for read or write access;
see Tables 4 and 5.
Table 4. Clock Peripheral Power-Down Register 1 (CLK_PPD1)
Bit
7
6
5
4
3
2
1
0
GPIO_d_ GPIO_C_ GPIO_B_ GPIO_A_ SPI_OFF I2C_OFF UART1_ UART0_
Field
OFF
OFF
OFF
OFF
OFF
OFF
0
0
0
0
0
0
0
0
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00DBh
Address
Note: R/W = read/write.
Bit
Description
System Clock to GPIO Port D
[7]
GPIO_D_OFF 1: Powered down; Port D alternate functions do not operate correctly.
0: System clock to GPIO Port D is powered up.
[6]
System Clock to GPIO Port C
GPIO_C_OFF 1: Powered down; Port C alternate functions do not operate correctly.
0: System clock to GPIO Port C is powered up.
[5]
System Clock to GPIO Port B
GPIO_B_OFF 1: Powered down; Port B alternate functions do not operate correctly.
0: System clock to GPIO Port B is powered up.
[4]
System Clock to GPIO Port A
GPIO_A_OFF 1: Powered down; Port A alternate functions do not operate correctly.
0: System clock to GPIO Port A is powered up.
[3]
SPI_OFF
System Clock to SPI
1: System clock to SPI is powered down.
0: System clock to SPI is powered up.
2
[2]
I2C_OFF
System Clock to I C
2
1: System clock to I C is powered down.
2
0: System clock to I C is powered up.
[1]
System Clock to UART1
UART1_OFF 1: System clock to UART1 is powered down.
0: System clock to UART1 is powered up.
[0]
System Clock to UART0 and IrDA Endec
UART0_OFF 1: System clock to UART0 and IrDA endec is powered down.
0: System clock to UART0 and IrDA endec is powered up.
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Product Specification
44
Table 5. Clock Peripheral Power-Down Register 2 (CLK_PPD2)
Bit
7
6
5
4
3
2
1
0
Field
PHI_OFF VBO_OFF
Reserved
TIMER3_ TIMER2_ TIMER1_ TIMER0_
OFF
OFF
OFF
OFF
Reset
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Address
00DCh
Note: R = read only; R/W = read/write.
Bit
Description
[7]
PHI_OFF
PHI Clock output
1: Disabled (output is high-impedance).
0: PHI Clock output is enabled.
[6]
VBO_OFF
Voltage Brown-Out Detection Circuit
1: Disabled to reduce DC current consumption in situations wherein VBO detection is not
necessary. Power-On Reset functionality is not affected by this setting.
0: Enabled.
[5:4]
Reserved
These bits are reserved and must be programmed to 00.
[3]
System Clock to TIMER3
TIMER3_OFF 1: Powered down.
0: Powered up.
[2]
System Clock to TIMER2
TIMER2_OFF 1: Powered down.
0: Powered up.
[1]
System Clock to TIMER1
TIMER1_OFF 1: Powered down.
0: Powered up.
[0]
System Clock to TIMER0
TIMER0_OFF 1: Powered down.
0: Powered up.
PS027004-0613
P R E L I M I N A R Y
Low-Power Modes
eZ80F91 ASSP
Product Specification
45
General-Purpose Input/Output
The eZ80F91 device features 32 General-Purpose Input/Output (GPIO) pins. The GPIO
pins are assembled as four 8-bit ports: Port A, Port B, Port C, and Port D. All port signals
are configured as either inputs or outputs. In addition, all of the port pins are used as vec-
tored interrupt sources for the CPU.
The eZ80F91 ASSPs GPIO ports are slightly different from its eZ80 predecessors. Specif-
ically, Port A pins source 8 mA and sink 10 mA. In addition, the Port B and C inputs now
feature Schmitt Trigger input buffers.
GPIO Operation
GPIO operation is the same for all four GPIO ports (Ports A, B, C, and D). Each port fea-
tures eight GPIO port pins. The operating mode for each pin is controlled by four bits that
are divided between four 8-bit registers. The GPIO mode control registers are:
•
•
•
•
Port x Data Register (Px_DR)
Port x Data Direction Register (Px_DDR)
Port x Alternate Register 1 (Px_ALT1)
Port x Alternate Register 2 (Px_ALT2)
In the above list, x can be A, B, C or D, representing any of the four GPIO ports. The mode
for each pin is controlled by setting each register bit pertinent to the pin to be configured.
For example, the operating mode for port B pin 7 (PB7) is set by the values contained in
PB_DR[7], PB_DDR[7], PB_ALT1[7], and PB_ALT2[7].
The combination of the GPIO control register bits allows individual configuration of each
port pin for nine modes. In all modes, reading of the Port x Data Register returns the sam-
pled state or level of the signal on the corresponding pin. Table 6 indicates the function of
each port signal based on these four register bits. After a RESET event, all GPIO port pins
are configured as standard digital inputs with the interrupts disabled.
In addition to the four mode control registers, each port has an 8-bit register, which is used
for clearing edge-triggered interrupts. This register is the Port x Alternate Register 0
(Px_ALT0), in which x can be A, B, C or D representing the four GPIO ports. When a
GPIO pin is configured as an edge-triggered interrupt, writing 1 to the corresponding bit
of the Px_ALT0 Register clears the interrupt.
PS027004-0613
P R E L I M I N A R Y
General-Purpose Input/Output
eZ80F91 ASSP
Product Specification
46
Table 6. GPIO Mode Selection
GPIO Px_ALT2 Px_ALT1 Px_DDR Px_DR
Mode
Bits7:0 Bits7:0
Bits7:0
Bits7:0 Port Mode
Output
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
0
Output
1
2
3
4
Input from pin
Input from pin
Open-drain output
Open-drain I/O
Open-source I/O
Open-source output
Reserved
High impedance
High impedance
0
High impedance
High impedance
1
5
6
7
High impedance
High impedance
Interrupt, dual edge-triggered
Alternate function controls port I/O.
Alternate function controls port I/O.
Interrupt, active Low
8
9
High impedance
High impedance
High impedance
High impedance
Interrupt, active High
Interrupt, falling edge-triggered
Interrupt, rising edge-triggered
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P R E L I M I N A R Y
General-Purpose Input/Output
eZ80F91 ASSP
Product Specification
47
Figures 5 and 6 show simplified block diagrams of the GPIO port pin for the various
modes.
GPIO Port Pin
Mode 2
Mode 6
Mode 8
GPIO Output Buffer
Mode 9
Mode 7(Input)
Px_DR*
ENB
Input to chip
D
Q
D
Q
Tristated for
modes 2,6,8,9
and 7(Input)
SysClock
Alternate
Function
Input
Default Value
Mode 7(Input)
Interrupt
Interrupt
Logic
Clear Interrupt
Modes 6,8,9
* Reading from the Px_DR returns
the value stored in this register
Figure 5. GPIO Port Pin Block Diagram for Input and Interrupt Modes
Simplified GPIO Port Block Diagram for Modes 1, 3, 4 and 7 (Output)
VDD
Px_DR*
Mode 4
External
Pull-up
Required for
Mode 3
Data
D
Q
GPIO Output Buffer
ENB
System Clock
GPIO Port
Pin
(open drain)
Q
Mode 3
Mode 1
External Pull-down
Required for
Mode 4
Mode 7 (Output)
(Open source)
Alternate Function Output
* Writing to the Px_DR stores
the value in this register
Figure 6. GPIO Port Pin Block Diagram for Output and Input/Output Mode
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P R E L I M I N A R Y
General-Purpose Input/Output
eZ80F91 ASSP
Product Specification
48
GPIO Mode 1: Output
The port pin is configured as a standard digital output pin. The value written to the Port x
Data Register (Px_DR) is driven on the pin.
GPIO Mode 2: Input
The port pin is configured as a standard digital input pin. The output is high impedance.
The value stored in the Port x Data Register produces no effect. As in all modes, a read
from the Port x Data Register returns the pin’s value. GPIO Mode 2 is the default operat-
ing mode following a RESET.
GPIO Mode 3: Open Drain
The port pin is configured as open-drain Input/Output. The GPIO pins do not feature an
internal pull-up to the supply voltage. To employ the GPIO pin in OPEN-DRAIN Mode,
an external pull-up resistor must connect the pin to the supply voltage. Writing 0 to the
Port x Data Register outputs a Low at the pin. Writing 1 to the Port x Data Register results
in high-impedance output.
GPIO Mode 4: Open Source
The port pin is configured as open-source I/O. The GPIO pins do not feature an internal
pull-down to the supply ground. To employ the GPIO pin in OPEN-SOURCE Mode, an
external pull-down resistor must connect the pin to the supply ground. Writing 1 to the
Port x Data Register outputs a High at the pin. Writing 0 to the Port x Data Register results
in a high-impedance output.
GPIO Mode 5: Reserved
This mode, reserved for Zilog testing purposes, produces a high-impedance output.
GPIO Mode 6: Dual Edge-Triggered
The port pin is configured for dual edge-triggered interrupt mode. Both a rising and a fall-
ing edge on this pin cause an interrupt request to be sent to the CPU. To select this mode
from the default mode (Mode 2), observe the following brief procedure.
1. Set Px_DR = 1
2. Set Px_ALT2 = 1
3. Set Px_ALT1 = 0
4. Set Px_DDR = 0
Writing a 1 to the Port x ALT0 Register bit position corresponding to the interrupt request
clears the interrupt.
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P R E L I M I N A R Y
General-Purpose Input/Output
eZ80F91 ASSP
Product Specification
49
GPIO Mode 7: Alternate Functions
The port pin is configured to pass control over to the alternate (secondary) functions
assigned to the pin. For example, the alternate mode function for PC5 is the DSR1 input
signal to UART1 and the alternate mode function for PB4 is the timer 3 input capture.
When GPIO Mode 7 is enabled, the pin output data and pin high-impedance control is
obtained from the alternate function's data output and high-impedance control, respec-
tively. The value in the Port x Data Register produces no effect on operation. Input signals
are sampled by the system clock before being passed to the alternate input function.
If the alternate function of a pin is an input and alternate function mode for that pin is not
enabled, the input is driven to a default non-asserted value. For example, in alternate mode
function, PC5 drives the DSR1 signal to UART1. As this signal is Low level true, the
DSR1 signal to UART1 is driven to 1 when PC5 is not in alternate mode function.
GPIO Mode 8: Level Sensitive Interrupt
The port pin is configured for level-sensitive interrupt mode. The value in the Port x Data
Register determines if a low or high-level causes an interrupt request. An interrupt request
is generated when the level at the pin is the same as the level stored in the Port x Data Reg-
ister. The port pin value is sampled by the system clock. The input pin must be held at the
selected interrupt level for a minimum of two system clock periods to initiate an interrupt.
The interrupt request remains active as long as this condition is maintained at the external
source. For example, if a port pin is configured as a low-level-sensitive interrupt, the inter-
rupt request will be asserted when the pin has been low for two system clocks and remains
active until the pin goes high.
Configuring a pin for Mode 8 requires a transition through Mode 9 (edge-triggered mode).
To avoid the possibility of an unwanted interrupt while transition through Mode 9, observe
the following brief procedure to select Mode 8 when starting from the default mode (Mode
2):
1. Disable interrupts.
2. Set Px_DR = 0 (low level interrupt) or 1 (high level interrupt).
3. Set Px_ALT2 = 1.
4. Set Px_ALT1 =1 (Mode 9).
5. Set Px_DDR = 0 (Mode 8).
6. Set Px_ALT0 = 1 (to clear possible Mode 9 interrupt).
7. Enable interrupts.
GPIO Mode 9: Edge-Triggered Interrupt
The port pin is configured for single edge-triggered interrupt mode. The value in the Port x
Data Register determines whether a positive or negative edge causes an interrupt request.
Writing 0 to the Port x Data Register bit sets the selected pin to generate an interrupt
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Product Specification
50
request for falling edges. Writing 1 to the Port x Data Register bit sets the selected pin to
generate an interrupt request for rising edges. The interrupt request remains active until 1
is written to the corresponding bit of the Port x Alternate Register 0. To select Mode 9
from the default mode (Mode 2), observe the following brief procedure.
1. Set the Port x Data Register.
2. Set Px_ALT2 = 1.
3. Set Px_ALT1 = 1.
4. Set Px_DDR = 1.
GPIO Interrupts
Each port pin is used as an interrupt source. Interrupts are either level- or edge-triggered.
Level-Triggered Interrupts
When the port is configured for level-triggered interrupts (Mode 8), the corresponding
port pin is open-drain. An interrupt request is generated when the level at the pin is the
same as the level stored in the Port x Data Register. The port pin value is sampled by the
system clock. The input pin must be held at the selected interrupt level for a minimum of
two clock periods to initiate an interrupt. The interrupt request remains active as long as
this condition is maintained at the external source.
For example, if PA3 is programmed for low-level interrupt and the pin is forced Low for
two clock cycles, an interrupt request signal is generated from that port pin and sent to the
CPU. The interrupt request signal remains active until the external device driving PA3
forces the pin high. The CPU must be enabled to respond to interrupts for the interrupt
request signal to be acted upon.
Edge-Triggered Interrupts
When the port is configured for edge-triggered interrupts, the corresponding port pin is
open-drain. If the pin receives the correct edge from an external device, the port pin gener-
ates an interrupt request signal to the CPU.
When configured for dual edge-triggered interrupt mode (GPIO Mode 6), both a rising
and a falling edge on the pin cause an interrupt request to be sent to the CPU. To select
Mode 6 from the default mode (Mode 2), observe the following brief procedure.
1. Set Px_DR = 1.
2. Set Px_ALT2 = 1.
3. Set Px_ALT1 = 0.
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4. Set Px_DDR = 0.
When configured for single edge-triggered interrupt mode (GPIO Mode 9), the value in
the Port x Data Register determines whether a positive or negative edge causes an interrupt
request. 0 in the Port x Data Register bit sets the selected pin to generate an interrupt
request for falling edges. 1 in the Port x Data Register bit sets the selected pin to generate
an interrupt request for rising edges. To select Mode 9 from the default mode (Mode 2),
observe the following brief procedure.
1. Set Px_DR = 1
2. Set Px_ALT2 = 1
3. Set Px_ALT = 1.
4. Set Px_DDR = 1.
Edge-triggered interrupts are cleared by writing 1 to the corresponding bit of the Px_ALT0
Register. For example, if PD4 has been set up to generate an edge-triggered interrupt, the
interrupt is cleared by writing a 1 to Px_ALT0[4].
GPIO Control Registers
Each GPIO port has four registers that controls its operation. The operating mode of each
bit within a port is selected by writing to the corresponding bits of these four registers as
shown in Table 6 on page 46. These four registers are Port Data Register (Px_DR), Port
Data Direction Register (Px_DDR), Port Alternate Register 1 (PX_ALT1), and Port Alter-
nate Register 2 (Px_ALT2). In addition to these four control registers, each port has a Port
Alternate Register 0 (Px_ALT0), which is used for clearing edge-triggered interrupts.
Port x Data Registers
When the port pins are configured for one of the output modes, the data written to the Port
x Data registers (see Table 7) is driven on the corresponding pins. In all modes, reading
from the Port x Data registers always returns the sampled current value of the correspond-
ing pins. When the port pins are configured for edge-triggered interrupts or level-sensitive
interrupts, the value written to the Port x Data Register bit selects the interrupt edge or
interrupt level (for more details about GPIO mode selection, see Table 6 on page 46 ).
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Table 7. Port x Data Registers (Px_DR)
Bit
7
U
6
U
5
U
4
U
3
U
2
U
1
U
0
U
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
PA_DR = 0096h, PB_DR = 009Ah, PC_DR = 009Eh, PD_DR = 00A2h
Note: U = undefined; R/W = read/write.
Port x Data Direction Registers
In conjunction with the other GPIO Control registers, the Port x Data Direction registers
(see Table 8) control the operating modes of the GPIO port pins. For more details about
GPIO mode selection, see Table 6 on page 46.
Table 8. Port x Data Direction Registers (Px_DDR)
Bit
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
PA_DDR = 0097h, PB_DDR = 009Bh, PC_DDR = 009Fh, PD_DDR = 00A3h
Note: R/W = read/write.
Port x Alternate Register 0
The Port x Alternate Register 0 is used to clear edge-triggered interrupts. If an edge-trig-
gered interrupt occurs, writing 1 to the corresponding bit of this register will clear it.
Table 9. Port x Alternate Registers 0 (Px_ALT0)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
R/W
W
W
W
W
W
W
W
W
Address
Note: W = write only.
PA_ALT0 = 00A6h, PB_ALT0 = 00A7h, PC_ALT0 = 00CEh, PD_ALT0 = 00CFh
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Port x Alternate Register 1
In conjunction with the other GPIO Control registers, the Port x Alternate Register 1 (see
Table 10) controls the operating modes of the GPIO port pins. For more details about
GPIO mode selection, see Table 6 on page 46.
Table 10. Port x Alternate Registers 1 (Px_ALT1)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
PA_ALT1 = 0098h, PB_ALT1 = 009Ch, PC_ALT1 = 00A0h, PD_ALT1 = 00A4h
Note: R/W = read/write.
Port x Alternate Register 2
In conjunction with the other GPIO Control registers, the Port x Alternate Register 2 (see
Table 11) controls the operating modes of the GPIO port pins. For more details about
GPIO mode selection, see Table 6 on page 46.
Table 11. Port x Alternate Registers 2 (Px_ALT2)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
PA_ALT2 = 0099h, PB_ALT2 = 009Dh, PC_ALT2 = 00A1h, PD_ALT2 = 00A5h
Note: R/W = read/write.
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Interrupt Controller
The interrupt controller on the eZ80F91 device routes the interrupt request signals from
the internal peripherals, external devices (via the internal port I/O), and the nonmaskable
interrupt (NMI) pin to the CPU.
Maskable Interrupts
On the eZ80F91 device, all maskable interrupts use the CPU’s vectored interrupt function.
The size of the I Register is modified to 16 bits in the eZ80F91 ASSP device differing
from the previous versions of eZ80 CPU, to allow for a 16MB range of interrupt vector
table placement. Additionally, the size of the IVECT Register is increased from 8 bits to 9
bits to provide an interrupt vector table that is expanded and more easily integrated with
other interrupts.
The vectors are 4 bytes (32 bits) apart, even though only 3 bytes (24 bits) are required. A
fourth byte is implemented for both programmability and expansion purposes.
Starting the interrupt vectors at 40hallows for easy implementation of the interrupt con-
troller vectors with the RST vectors. Table 12 lists the interrupt vector sources by priority
for each of the maskable interrupt sources. The maskable interrupt sources are listed in
order of their priority, with vector 40h being the highest-priority interrupt. In ADL Mode,
the full 24-bit interrupt vector is located at starting address {I[15:1], IVECT[8:0]}, where
I[15:0] is the CPU’s Interrupt Page Address Register.
Table 12. Interrupt Vector Sources by Priority
Priority
Vector
040h
044h
048h
04Ch
050h
054h
058h
05Ch
060h
064h
Source
EMAC Rx
EMAC Tx
EMAC SYS
PLL
Priority
24
Vector
0A0h
0A4h
0A8h
0ACh
0B0h
0B4h
0B8h
0BCh
0C0h
0C4h
Source
Port B 0
Port B 1
Port B 2
Port B 3
Port B 4
Port B 5
Port B 6
Port B 7
Port C 0
Port C 1
0
1
2
3
4
5
6
7
8
9
25
26
27
Flash
28
Timer 0
Timer 1
Timer 2
Timer 3
Unused*
29
30
31
32
33
Note: The vector addresses 064h and 068h are left unused to avoid conflict with the nonmaskable interrupt
(NMI) address 066h. The NMI is prioritized higher than all maskable interrupts.
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Table 12. Interrupt Vector Sources by Priority (Continued)
Priority
10
Vector
068h
06Ch
070h
074h
078h
07Ch
080h
084h
088h
08Ch
090h
094h
098h
09Ch
Source
Unused*
RTC
Priority
34
Vector
0C8h
0CCh
0D0h
0D4h
0D8h
0DCh
0E0h
0E4h
0E8h
0ECh
0F0h
0F4h
0F8h
0FCh
Source
Port C 2
Port C 3
Port C 4
Port C 5
Port C 6
Port C 7
Port D 0
Port D 1
Port D 2
Port D 3
Port D 4
Port D 5
Port D 6
Port D 7
11
35
12
UART 0
UART 1
36
13
37
2
14
I C
38
15
SPI
39
16
Port A 0
Port A 1
Port A 2
Port A 3
Port A 4
Port A 5
Port A 6
Port A 7
40
17
41
18
42
19
43
20
44
21
45
22
46
23
47
Note: The vector addresses 064h and 068h are left unused to avoid conflict with the nonmaskable interrupt
(NMI) address 066h. The NMI is prioritized higher than all maskable interrupts.
The user’s program must store the interrupt service routine starting address in the four-
byte interrupt vector locations. For example in ADL Mode, the three-byte address for the
SPI interrupt service routine is stored at {I[15:1], 07Ch}, {I[15:1], 07Dh}, and {I[15:1],
07Eh}. In Z80 Mode, the two-byte address for the SPI interrupt service routine is stored at
{MBASE[7:0], I[7:1], 07Ch} and {MBASE, I[7:1], 07Dh}. The least-significant byte is
stored at the lower address.
When one or more interrupt requests (IRQs) become active, an interrupt request is gener-
ated by the interrupt controller and sent to the CPU. The corresponding 9-bit interrupt vec-
tor for the highest-priority interrupt is placed on the 9-bit interrupt vector bus, IVECT[8:0].
The interrupt vector bus is internal to the eZ80F91 device and is therefore externally not
visible. The response time of the CPU to an interrupt request is a function of the current
instruction being executed as well as the number of wait states being asserted. The interrupt
vector, {I[15:1], IVECT[8:0]} is visible on the address bus (ADDR[23:0]), when the inter-
rupt service routine begins. The response of the CPU to a vectored interrupt on the
eZ80F91 device is explained in Table 13. Interrupt sources are required to be active until
the Interrupt Service Routine (ISR) starts.
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Note: The lower bit of the I Register is replaced with the MSB of the IVECT from the interrupt
controller. As a result, the interrupt vector table is required to be placed onto a 512-byte
boundary. Setting the LSB of the I Register produces no effect on the interrupt vector
address.
Table 13. Vectored Interrupt Operation
Memory
ADL MADL
Mode
Bit
Bit
Operation
Z80 Mode
0
0
Read the LSB of the interrupt vector placed on the internal vectored interrupt
bus, IVECT [8:0], by the interrupting peripheral.
IEF1 ← 0
IEF2 ← 0
• The Starting Program Counter is effective {MBASE, PC[15:0]}.
• Push the 2-byte return address PC[15:0] onto the ({MBASE,SPS}) stack.
• The ADL Mode bit remains cleared to 0.
• The interrupt vector address is located at { MBASE, I[7:1], IVECT[8:0] }.
• PC[23:0] ← ( { MBASE, I[7:1], IVECT[8:0] } ).
• The interrupt service routine must end with RETI.
ADL Mode
1
0
Read the LSB of the interrupt vector placed on the internal vectored interrupt
bus, IVECT [8:0], by the interrupting peripheral.
IEF1 ← 0
IEF2 ← 0
• The Starting Program Counter is PC[23:0].
• Push the 3-byte return address, PC[23:0], onto the SPL stack.
• The ADL Mode bit remains set to 1.
• The interrupt vector address is located at { I[15:1], IVECT[8:0] }.
• PC[23:0] ← ( { I[15:1], IVECT[8:0] } ).
• The interrupt service routine must end with RETI.
Z80 Mode
0
1
Read the LSB of the interrupt vector placed on the internal vectored interrupt
bus, IVECT[8:0], bus by the interrupting peripheral.
• IEF1 ← 0
• IEF2 ← 0
• The Starting Program Counter is effective {MBASE, PC[15:0]}.
• Push the 2-byte return address, PC[15:0], onto the SPL stack.
• Push a 00h byte onto the SPL stack to indicate an interrupt from Z80 Mode
(because ADL = 0).
• Set the ADL Mode bit to 1.
• The interrupt vector address is located at { I[15:1], IVECT[8:0] }.
• PC[23:0] ← ( { I[15:1], IVECT[8:0] } ).
• The interrupt service routine must end with RETI.L
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Table 13. Vectored Interrupt Operation (Continued)
ADL MADL
Memory
Mode
Bit
Bit
Operation
ADL Mode
1
1
Read the LSB of the interrupt vector placed on the internal vectored interrupt
bus, IVECT [8:0], by the interrupting peripheral.
• IEF1 ← 0
• IEF2 ← 0
• The Starting Program Counter is PC[23:0].
• Push the 3-byte return address, PC[23:0], onto the SPL stack.
• Push a 01h byte onto the SPL stack to indicate a restart from ADL Mode
(because ADL = 1).
• The ADL Mode bit remains set to 1.
• The interrupt vector address is located at {I[15:1], IVECT[8:0]}.
• PC[23:0] ← ( { I[15:1], IVECT[8:0] } ).
• The interrupt service routine must end with RETI.L
Interrupt Priority Registers
The eZ80F91 provides two interrupt priority levels for the maskable interrupts. The
default priority (or Level 0) is indicated in Table 14. The default priority of any maskable
interrupt increases to Level 1 (a higher priority than any Level 0 interrupt) by setting the
appropriate bit in the Interrupt Priority registers as shown in Table 14.
Table 14. Interrupt Priority Registers (INT_Px)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
INT_P0 Reset
INT_P1 Reset
INT_P2 Reset
INT_P3 Reset
INT_P4 Reset
INT_P5 Reset
R/W
0
0
0
0
0
0*
0
0*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
INT_P0 = 0010h, INT_P1 = 0011h, INT_P2 = 0012h,
INT_P3 = 0013h, INT_P4 = 0014h, INT_P5 = 0015h
Note: R/W = read/write, *Unused.
Bit
Description
[7]
INT_PX
Pin 7 Interrupt Priority
1: Level One priority.
0: Default priority
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Bit
Description (Continued)
[6]
INT_PX
Pin 6 Interrupt Priority
1: Level One Interrupt Priority
0: Default Interrupt Priority
[5]
INT_PX
Pin 5 Interrupt Priority
1: Level One Interrupt Priority
0: Default Interrupt Priority
[4]
INT_PX
Pin 4 Interrupt Priority
1: Level One Interrupt Priority
0: Default Interrupt Priority
[3]
INT_PX
Pin 3 Interrupt Priority
1: Level One Interrupt Priority
0: Default Interrupt Priority
[2]
INT_PX
Pin 2 Interrupt Priority
1: Level One Interrupt Priority
0: Default Interrupt Priority
[1]
INT_PX
Pin 1 Interrupt Priority
1: Level One Interrupt Priority
0: Default Interrupt Priority
[0]
INT_PX
Pin 0 Interrupt Priority
1: Level One Interrupt Priority
0: Default Interrupt Priority
The Interrupt Vector Priority Control bits are listed in Table 15.
Table 15. Interrupt Vector Priority Control Bits
Priority Control
Bit
Priority Control
Bit
Vector
040h
044h
048h
04Ch
050h
054h
058h
05Ch
060h
064h
Source
EMAC Rx
EMAC Tx
EMAC SYS
PLL
Vector
Source
Port B 0
Port B 1
Port B 2
Port B 3
Port B 4
Port B 5
Port B 6
Port B 7
Port C 0
Port C 1
INT_P0[0]
INT_P3[0]
INT_P3[1]
INT_P3[2]
INT_P3[3]
INT_P3[4]
INT_P3[5]
INT_P3[6]
INT_P3[7]
INT_P4[0]
INT_P4[1]
0A0h
0A4h
0A8h
0ACh
0B0h
0B4h
0B8h
0BCh
0C0h
0C4h
INT_P0[1]
INT_P0[2]
INT_P0[3]
INT_P0[4]
INT_P0[5]
INT_P0[6]
INT_P0[7]
INT_P1[0]
INT_P1[1]
Flash
Timer 0
Timer 1
Timer 2
Timer 3
Unused*
Note: *The vector addresses 064h and 068h are left unused to avoid conflict with the NMI vector address 066h.
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Table 15. Interrupt Vector Priority Control Bits (Continued)
Priority Control
Bit
Priority Control
Bit
Vector
068h
06Ch
070h
074h
078h
07Ch
080h
084h
088h
08Ch
090h
094h
098h
09Ch
Source
Unused*
RTC
Vector
0C8h
0CCh
0D0h
0D4h
0D8h
0DCh
0E0h
0E4h
0E8h
0ECh
0F0h
0F4h
0F8h
0FCh
Source
Port C 2
Port C 3
Port C 4
Port C 5
Port C 6
Port C 7
Port D 0
Port D 1
Port D 2
Port D 3
Port D 4
Port D 5
Port D 6
Port D 7
INT_P1[2]
INT_P1[3]
INT_P1[4]
INT_P1[5]
INT_P1[6]
INT_P1[7]
INT_P2[0]
INT_P2[1]
INT_P2[2]
INT_P2[3]
INT_P2[4]
INT_P2[5]
INT_P2[6]
INT_P2[7]
INT_P4[2]
INT_P4[3]
INT_P4[4]
INT_P4[5]
INT_P4[6]
INT_P4[7]
INT_P5[0]
INT_P5[1]
INT_P5[2]
INT_P5[3]
INT_P5[4]
INT_P5[5]
INT_P5[6]
INT_P5[7]
UART 0
UART 1
2
I C
SPI
Port A 0
Port A 1
Port A 2
Port A 3
Port A 4
Port A 5
Port A 6
Port A 7
Note: *The vector addresses 064h and 068h are left unused to avoid conflict with the NMI vector address 066h.
If more than one maskable interrupt is prioritized to a higher level (Level 1), the higher-
priority interrupts follow the priority order as described in Table 14. For example, Table
16 shows the maskable interrupts 044h(EMAC Tx), 084h(Port A 1), and 06Ch(RTC) as
elevated to priority Level 1. Table 17 shows the new interrupt priority for the top ten
maskable interrupts.
Table 16. Example: Maskable Interrupt Priority
Priority
Register
INT_P0
INT_P1
INT_P2
INT_P3
INT_P4
INT_P5
Setting
02h
Description
Increase 044h (EMAC Tx) to Priority Level 1.
Increase 06Ch (RTC) to Priority Level 1.
Increase 084h (Port A1) to Priority Level 1.
Default priority.
08h
02h
00h
00h
Default priority.
00h
Default priority.
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Table 17. Example: Priority Levels for Maskable Interrupts
Priority
Vector
044h
06Ch
084h
040h
048h
04Ch
050h
054h
058h
05Ch
Source
EMAC Tx
RTC
0
1
2
3
4
5
6
7
8
9
Port A 1
EMAC Rx
EMAC SYS
PLL
Flash
Timer 0
Timer 1
Timer 2
GPIO Port Interrupts
All interrupts are latched. In effect, an interrupt is held even if the interrupt occurs while
another interrupt is being serviced and interrupts are disabled, or if the interrupt is of a
lower priority. However, before the latched ISR completes its task or reenables interrupts,
the ISR must clear the interrupt. For on-chip peripherals, the interrupt is cleared when the
data register is accessed. For GPIO-level interrupts, the interrupt signal must be removed
before the ISR completes its task. For GPIO-edge interrupts (single and dual), the interrupt
is cleared by writing a 1 to the corresponding bit position in the Px_ALT0 Register. See
the Edge-Triggered Interrupts section on page 50.
Note: For eZ80F91 devices with a ZDI or JTAG revision less than 2, care must be taken using a
GPIO data register when it is configured for interrupts. For edge-interrupt modes (modes 6
and 9) as discussed earlier, writing 1 clears the interrupt. However, 1 in the data register
also conveys a particular configuration. For example, when the data register Px_DR is set
first followed by the Px_ALT2, Px_ALT1, and Px_DDR registers, then the configuration
is performed correctly. Writing 1 to the register later to clear interrupts does not change the
configuration. For eZ80F91 devices with a ZDI or JTAG revision 2 or later, the clearing of
interrupts is accomplished through the new Px_ALT0 registers and the above problem
does not exist.
In Mode 9 operation, if the GPIO is already configured for Mode 9 and if the trigger edge
must be changed (from falling to rising or from rising to falling), then the configuration
must be changed to another mode, such as Mode 2, and then changed back to Mode 9. For
example, enter Mode 2 by writing the registers in the sequence PxDR, Px_ALT2,
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Px_ALT1, Px_DDR. Next, change back to Mode 9 by writing the registers in the sequence
PxDR, Px_ALT2, Px_ALT1, Px_DDR.
In Mode 8 operation, if the GPIO is configured for level-sensitive interrupts, a write value
to Px_DR after configuration must be the same write value used when configuring the
GPIO.
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Chip Selects and Wait States
The eZ80F91 generates four chip selects for external devices. Each chip select is pro-
grammed to access either the memory space or the I/O space. The memory chip selects are
individually programmed on a 64 KB boundary. Each I/O chip selects choose a 256 byte
section of I/O space. In addition, each chip select is programmed for up to 7 wait states.
Memory and I/O Chip Selects
Each of the chip selects are enabled either for the memory address space or the I/O address
space, but not both. To select the memory address space for a particular chip select,
CSX_IO (CSx_CTL[4]) must be reset to 0. To select the I/O address space for a particular
chip select, CSX_IO must be set to 1. After RESET, the default is for all chip selects to be
configured for the memory address space. For either the memory address space or the I/O
address space, the individual chip selects must be enabled by setting CSX_EN
(CSx_CTL[3]) to 1.
Memory Chip Select Operation
Operation of each of the memory chip select is controlled by three control registers. To
enable a particular memory chip select, the following conditions must be satisfied:
•
•
•
The chip select is enabled by setting CSx_EN to 1
The chip select is configured for memory by clearing CSX_IO to 0
The address is in the associated chip select range:
CSx_LBR[7:0] ≤ ADDR[23:16] ≤ CSx_UBR[7:0]
•
•
On-chip Flash is not configured for the same address space, because on-chip Flash is
prioritized higher than all memory chip selects
On-chip RAM is not configured for the same address space, because on-chip RAM is
prioritized higher than Flash and all memory chip selects
•
•
No higher priority (lower number) chip select meets the above conditions
A memory access instruction must be executing
If all of the preceding conditions are satisfied to generate a memory chip select, then the
following results occur:
•
The appropriate chip select (CS0, CS1, CS2, or CS3) is asserted (driven Low)
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•
•
MREQ is asserted (driven Low)
Depending on the instruction either RD or WR is asserted (driven Low)
If the upper and lower bounds are set to the same value (CSx_UBR = CSx_LBR), then a
particular chip select is valid for a single 64 KB page.
Memory Chip Select Priority
A lower-numbered chip select is granted priority over a higher-numbered chip select. For
example, if the address space of chip select 0 overlaps the chip select 1 address space, then
chip select 0 is active. If the address range programmed for any chip select signal overlaps
with the address of internal memory, the internal memory is accorded higher priority. If
the particular chip select(s) are configured with an address range that overlaps with an
internal memory address and when the internal memory is accessed, the chip select signal
is not asserted.
Reset States
On RESET, chip select 0 is active for all addresses, because its lower bound register resets
to 00hand its upper bound register resets to FFh. All of the other lower and upper bound
chip select registers reset to 00h.
Memory Chip Select Example
The use of memory chip selects is demonstrated in Figure 7. The associated control regis-
ter values are indicated in Table 18. In this example, all 4 chip selects are enabled and con-
figured for memory addresses. Also, CS1 overlaps with CS0. Because CS0 is prioritized
higher than CS1, CS1 is not active for much of its defined address space.
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Memory
Location
CS3_UBR = FFh
FFFFFFh
CS3 Active
3 MB Address Space
CS3_LBR = D0h
CS2_UBR = CFh
D00000h
CFFFFFh
CS2 Active
3 MB Address Space
CS2_LBR = A0h
CS1_UBR = 9Fh
A00000h
9FFFFFh
CS1 Active
2 MB Address Space
800000h
7FFFFFh
CS0_UBR = 7Fh
CS0 Active
8 MB Address Space
CS0_LBR = CS1_LBR = 00h
000000h
Figure 7. Example: Memory Chip Select
Table 18. Example: Register Values for Figure 7 Memory Chip Select
Chip
Select
CSx_CTL[3] CSx_CTL[4]
CSx_EN
CSx_IO
CSx_LBR CSx_UBR Description
CS0
CS1
CS2
CS3
1
0
00h
00h
A0h
D0h
7Fh
9Fh
CFh
FFh
CS0 is enabled as a Memory chip
select. Valid addresses range from
000000h–7FFFFFh.
1
1
1
0
0
0
CS1 is enabled as a Memory chip
select. Valid addresses range from
800000h–9FFFFFh.
CS2 is enabled as a Memory chip
select. Valid addresses range from
A00000h–CFFFFFh.
CS3 is enabled as a Memory chip
select. Valid addresses range from
D00000h–FFFFFFh.
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Input/Output Chip Select Operation
I/O chip selects will be active only when the CPU is performing I/O instructions. Because
the I/O space is separate from the memory space in the eZ80F91 device, a conflict
between I/O and memory addresses never occurs.
The eZ80F91 supports a 16-bit I/O address. The I/O chip select logic decodes the high
byte of the I/O address, ADDR[15:8]. Because the upper byte of the address bus,
ADDR[23:16], is ignored, the I/O devices are always accessed from memory mode (ADL
or Z80). The MBASE offset value used for setting the Z80 MEMORY Mode page is also
always ignored.
Four I/O chip selects are available with the eZ80F91 device. To generate a particular I/O
chip select, the following conditions must be satisfied:
•
•
•
•
•
The chip select is enabled by setting CSx_EN to 1
The chip select is configured for I/O by setting CSX_IO to 1
An I/O chip select address match occurs; ADDR[15:8] = CSx_LBR[7:0]
No higher-priority (lower-number) chip select meets the above conditions
The I/O address is not within the on-chip peripheral address range 0000h–00FFh. On-
chip peripheral registers assume priority for all addresses in which the following state-
ment is true:
0000h ≤ ADDR[15:0] ≤ 00FFh
•
An I/O instruction must be executing.
If all of the foregoing conditions are met to generate an I/O chip select, then the following
results occur:
•
•
•
The appropriate chip select (CS0, CS1, CS2, or CS3) is asserted (driven Low).
IORQ is asserted (driven Low).
Depending on the instruction, either RD or WR is asserted (driven Low).
Wait States
For each of the chip selects, programmable wait states are asserted to provide external
devices with additional clock cycles to complete their read or write operations. The num-
ber of wait states for a particular chip select is controlled by the 3-bit field CSx_WAIT
(CSx_CTL[7:5]). The wait states are independently programmed to provide 0 to 7 wait
states for each chip select. The wait states idle the CPU for the specified number of system
clock cycles.
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WAIT Input Signal
Similar to the programmable wait states, an external peripheral drives the WAIT input pin
to force the CPU to provide additional clock cycles to complete its read or write operation.
Driving the WAIT pin Low stalls the CPU. The CPU resumes operation on the first rising
edge of the internal system clock following deassertion of the WAIT pin.
If the WAIT pin is to be driven by an external device, the corresponding chip select for
the device must be programmed to provide at least one wait state. Due to input sampling
of the WAIT input pin (see Figure 8), one programmable wait state is required to allow
the external peripheral sufficient time to assert the WAIT pin. It is recommended that the
corresponding chip select for the external device be programmed to provide the maxi-
mum number of wait states (seven).
Caution:
eZ80
CPU
Wait
Pin
D
Q
System Clock
Figure 8. Wait Input Sampling Block Diagram
An example of wait state operation is shown in Figure 9. In this example, the chip select is
configured to provide a single wait state. The external peripheral accessed drives the
WAIT pin Low to request assertion of an additional wait state. If the WAIT pin is asserted
for additional system clock cycles, wait states are added until the WAIT pin is deasserted
(active High).
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TCLK
TWAIT
SCLK
ADDR[23:0]
DATA[7:0]
(output)
CSx
MREQ
RD
INSTRD
Figure 9. Example: Wait State Read Operation
Chip Selects During Bus Request/Bus Acknowledge
Cycles
When the CPU relinquishes the address bus to an external peripheral in response to an
external bus request (BUSREQ), it drives the bus acknowledge pin (BUSACK) Low. The
external peripheral then drives the address bus (and data bus). The CPU continues to gen-
erate chip select signals in response to the address on the bus. External devices cannot
access the internal registers of the eZ80F91.
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Bus Mode Controller
The bus mode controller allows the address and data bus timing and signal formats of the
eZ80F91 to be configured to connect with external devices compatible with eZ80, Z80,
Intel and Motorola microcontrollers. Bus modes for each of the chip selects are configured
independently using the Chip Select Bus Mode Control Registers. The number of CPU
system clock cycles per bus mode state is also independently programmable. For Intel bus
mode, multiplexed address and data are selected in which both the lower byte of the
address and the data byte use the data bus, DATA[7:0]. Each of the bus modes are
explained in the following sections.
eZ80 BUS Mode
Chip selects configured for eZ80 BUS Mode do not modify the bus signals from the CPU.
The timing diagrams for external Memory and I/O read and write operations are shown in
the AC Characteristics section on page 343. The default mode for each chip select is eZ80
Mode.
Z80 BUS Mode
Chip selects configured for Z80 Mode modify the eZ80 bus signals to match the Z80
microprocessor address and data bus interface signal format and timing. During read oper-
ations, the Z80 bus mode employs three states: T1, T2, and T3, as described in Table 19.
Table 19. Z80 BUS Mode Read States
STATE T1 The read cycle begins in State T1. The CPU drives the address onto the address bus and
the associated chip select signal is asserted.
STATE T2 During State T2, the RD signal is asserted. Depending on the instruction, either the MREQ
or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU system
clock cycle prior to the end of State T2, additional wait states (T
WAIT pin is driven High.
) are asserted until the
WAIT
STATE T3 During State T3, no bus signals are altered. The data is latched by the eZ80F91 at the rising
edge of the CPU system clock at the end of State T3.
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During write operations, Z80 bus mode employs 3 states: T1, T2, and T3, as described in
Table 20.
Table 20. Z80 Bus Mode Write States
STATE T1 The write cycle begins in State T1. The CPU drives the address onto the address bus, and
the associated chip select signal is asserted.
STATE T2 During State T2, the WR signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU
system clock cycle prior to the end of State T2, additional wait states (T
until the WAIT pin is driven High.
) are asserted
WAIT
STATE T3 During State T3, no bus signals are altered.
Z80 bus mode read and write timing is shown in Figures 10 and 11. The Z80 bus mode
states are configured for 1 to 15 CPU system clock cycles. In the figures, each Z80 bus
mode state is two CPU system clock cycles in duration. The figures also show the asser-
tion of 1 wait state (TWAIT) by the external peripheral during each Z80 bus mode cycle.
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T
T1
T2
T3
CLK
System Clock
ADDR[23:0]
DATA[7:0]
CSx
RD
WAIT
WR
MREQ
or IORQ
Figure 10. Example: Z80 Bus Mode Read Timing
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T
T1
T2
T3
CLK
System Clock
ADDR[23:0]
DATA[7:0]
CSx
RD
WAIT
WR
MREQ
or IORQ
Figure 11. Example: Z80 Bus Mode Write Timing
Intel Bus Mode
Chip selects configured for Intel bus mode modify the CPU bus signals to duplicate a four-
state memory transfer similar to that found on Intel-style microcontrollers. The bus signals
and eZ80F91 pins are mapped as shown in Figure 12. In Intel bus mode, you select either
multiplexed or nonmultiplexed address and data buses. In nonmultiplexed operation, the
address and data buses are separate. In multiplexed operation, the lower byte of the
address, ADDR[7:0], also appears on the data bus, DATA[7:0], during State T1 of the Intel
bus mode cycle.
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Bus Mode
Controller
eZ80 Bus Mode
Signals (Pins)
Intel Bus
Signal Equvalents
INSTRD
RD
ALE
RD
WR
WR
WAIT
READY
MREQ
MREQ
IORQ
IORQ
ADDR[23:0]
ADDR[23:0]
ADDR[7:0]
Multiplexed
Bus
Controller
DATA[7:0]
DATA[7:0]
Figure 12. Intel Bus Mode Signal and Pin Mapping
Intel Bus Mode: Separate Address and Data Buses
During read operations with separate address and data buses, the Intel bus mode employs
4 states: T1, T2, T3, and T4, as described in Table 21.
Table 21. Intel Bus Mode Read States: Separate Address and Data Buses
STATE T1 The read cycle begins in State T1. The CPU drives the address onto the address bus and
the associated chip select signal is asserted. The CPU drives the ALE signal High at the
beginning of T1. In the middle of T1, the CPU drives ALE Low to facilitate the latching of the
address.
STATE T2 During State T2, the CPU asserts the RD signal. Depending on the instruction, either the
MREQ or IORQ signal is asserted.
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Table 21. Intel Bus Mode Read States: Separate Address and Data Buses (Continued)
STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(T
) are asserted until the READY pin is driven High.
WAIT
STATE T4 The CPU latches the read data at the beginning of State T4. The CPU deasserts the RD sig-
nal and completes the Intel bus mode cycle.
During write operations with separate address and data buses, the Intel bus mode employs
4 states: T1, T2, T3, and T4, as described in Table 22.
Table 22. Intel Bus Mode Write States: Separate Address and Data Buses
STATE T1 The write cycle begins in State T1. The CPU drives the address onto the address bus, the
associated chip select signal is asserted, and the data is driven onto the data bus. The CPU
drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU drives
ALE Low to facilitate the latching of the address.
STATE T2 During State T2, the CPU asserts the WR signal. Depending on the instruction, either the
MREQ or IORQ signal is asserted.
STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(T
) are asserted until the READY pin is driven High.
WAIT
STATE T4 The CPU deasserts the WR signal at the beginning of State T4. The CPU holds the data and
address buses till the end of T4. The bus cycle is completed at the end of T4.
Intel bus mode timing for a read operation is diagrammed in Figure 13; see Figure 14 for
write operation timing. If the READY signal (external WAIT pin) is driven Low prior to
the beginning of State T3, additional wait states (TWAIT) are asserted until the READY
signal is driven High. The Intel bus mode states are configured for 2 to 15 CPU system
clock cycles. In the two figures, each Intel bus mode state is two CPU system clock cycles
in duration. These timing figures also show the assertion of one wait state (TWAIT) by the
selected peripheral.
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T
WAIT
T1
T2
T3
T4
System Clock
ADDR[23:0]
DATA[7:0]
CSx
ALE
RD
READY
WR
MREQ
or IORQ
Figure 13. Example: Intel Bus Mode Read Timing: Separate Address and Data Buses
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T
WAIT
T1
T2
T3
T4
System Clock
ADDR[23:0]
DATA[7:0]
CSx
ALE
WR
READY
RD
MREQ
or IORQ
Figure 14. Example: Intel Bus Mode Write Timing: Separate Address and Data Buses
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Intel Bus Mode: Multiplexed Address and Data Bus
During read operations with multiplexed address and data, the Intel bus mode employs 4
states: T1, T2, T3, and T4, as described in Table 23.
Table 23. Intel Bus Mode Read States: Multiplexed Address and Data Bus
STATE T1 The read cycle begins in State T1. The CPU drives the address onto the DATA bus and the
associated chip select signal is asserted. The CPU drives the ALE signal High at the begin-
ning of T1. In the middle of T1, the CPU drives ALE Low to facilitate the latching of the
address.
STATE T2 During State T2, the CPU removes the address from the DATA bus and asserts the RD sig-
nal. Depending upon the instruction, either the MREQ or IORQ signal is asserted.
STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(T
) are asserted until the READY pin is driven High.
WAIT
STATE T4 The CPU latches the read data at the beginning of State T4. The CPU deasserts the RD sig-
nal and completes the Intel™ bus mode cycle.
During write operations with multiplexed address and data, the Intel™ bus mode employs
4 states: T1, T2, T3, and T4, as described in Table 24.
Table 24. Intel Bus Mode Write States: Multiplexed Address and Data Bus
STATE T1 The write cycle begins in State T1. The CPU drives the address onto the DATA bus and
drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU drives
ALE Low to facilitate the latching of the address.
STATE T2 During State T2, the CPU removes the address from the DATA bus and drives the write data
onto the DATA bus. The WR signal is asserted to indicate a write operation.
STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(T
) are asserted until the READY pin is driven High.
WAIT
STATE T4 The CPU deasserts the write signal at the beginning of T4 identifying the end of the write
operation. The CPU holds the data and address buses through the end of T4. The bus cycle
is completed at the end of T4.
Signal timing for Intel bus mode with multiplexed address and data for a read operation is
diagrammed in Figure 15; see Figure 16 for write timing. In these two figures, each Intel
bus mode state is two CPU system clock cycles in duration. These timing figures also
show the assertion of one wait state (TWAIT) by the selected peripheral.
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T
WAIT
T1
T2
T3
T4
System Clock
ADDR[23:0]
DATA[7:0]
CSx
ALE
RD
READY
WR
MREQ
or IORQ
Figure 15. Example: Intel Bus Mode Read Timing: Multiplexed Address and Data Bus
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T
WAIT
T1
T2
T3
T4
System Clock
ADDR[23:0]
DATA[7:0]
CSx
ALE
WR
READY
RD
MREQ
or IORQ
Figure 16. Example: Intel Bus Mode Write Timing: Multiplexed Address and Data Bus
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Motorola Bus Mode
Chip selects configured for Motorola bus mode modify the CPU bus signals to duplicate
an eight-state memory transfer similar to that on the Motorola-style microcontrollers. The
bus signals (and eZ80F91 I/O pins) are mapped as shown in Figure 17.
Bus Mode
Controller
eZ80 Bus Mode
Signals (Pins)
Motorola Bus
Signal Equvalents
INSTRD
RD
AS
DS
R/W
WR
WAIT
DTACK
MREQ
MREQ
IORQ
IORQ
ADDR[23:0]
ADDR[23:0]
DATA[7:0]
DATA[7:0]
Figure 17. Motorola Bus Mode Signal and Pin Mapping
During write operations, the Motorola bus mode employs 8 states: S0, S1, S2, S3, S4, S5,
S6, and S7, as described in Table 25.
Table 25. Motorola Bus Mode Read States
STATE S0 The read cycle starts in state S0. The CPU drives R/W High to identify a read cycle.
STATE S1 Entering state S1, the CPU drives a valid address on the address bus, ADDR[23:0].
STATE S2 On the rising edge of state S2, the CPU asserts AS and DS.
STATE S3 During state S3, no bus signals are altered.
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Table 25. Motorola Bus Mode Read States (Continued)
STATE S4 During state S4, the CPU waits for a cycle termination signal DTACK (WAIT), a peripheral
signal. If the termination signal is not asserted at least one full CPU clock period prior to the
rising clock edge at the end of S4, the CPU inserts WAIT (T
asserted. Each wait state is a full bus mode cycle.
) states until DTACK is
WAIT
STATE S5 During state S5, no bus signals are altered.
STATE S6 During state S6, data from the external peripheral device is driven onto the data bus.
STATE S7 On the rising edge of the clock entering state S7, the CPU latches data from the addressed
peripheral device and deasserts AS and DS. The peripheral device deasserts DTACK at this
time.
The eight states for a write operation in Motorola bus mode are described in Table 26.
Table 26. Motorola Bus Mode Write States
STATE S0 The write cycle starts in S0. The CPU drives R/W High (if a preceding write cycle leaves R/
W Low).
STATE S1 Entering S1, the CPU drives a valid address on the address bus.
STATE S2 On the rising edge of S2, the CPU asserts AS and drives R/W Low.
STATE S3 During S3, the data bus is driven out of the high-impedance state as the data to be written is
placed on the bus.
STATE S4 At the rising edge of S4, the CPU asserts DS. The CPU waits for a cycle termination signal
DTACK (WAIT). If the termination signal is not asserted at least one full CPU clock period
prior to the rising clock edge at the end of S4, the CPU inserts WAIT (T
DTACK is asserted. Each wait state is a full bus mode cycle.
) states until
WAIT
STATE S5 During S5, no bus signals are altered.
STATE S6 During S6, no bus signals are altered.
STATE S7 On entering S7, the CPU deasserts AS and DS. As the clock rises at the end of S7, the CPU
drives R/W High. The peripheral device deasserts DTACK at this time.
Signal timing for Motorola bus mode for a read operation is diagrammed in Figure 18; see
Figure 19 for write timing. In these two figures, each Motorola bus mode state is two CPU
system clock cycles in duration.
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S3
S6
S7
S0
S1
S2
S4
S5
System Clock
ADDR[23:0]
DATA[7:0]
CSx
AS
DS
R/W
DTACK
MREQ
or IORQ
Figure 18. Example: Motorola Bus Mode Read Timing
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S3
S6
S7
S0
S1
S2
S4
S5
System Clock
ADDR[23:0]
DATA[7:0]
CSx
AS
DS
R/W
DTACK
MREQ
or IORQ
Figure 19. Example: Motorola Bus Mode Write Timing
Switching Between Bus Modes
When switching bus modes between Intel™ to Motorola, Motorola to Intel, eZ80 to
Motorola, or eZ80 to Intel, there is one extra SCLK cycle added to the bus access. An
extra clock cycle is not required for repeated access in any of the bus modes (for example,
Intel to Intel). An extra clock cycle is not required for Intel (or Motorola) to eZ80 BUS
Mode (under normal operation). The extra clock cycle is not shown in the timing exam-
ples. Due to the asynchronous nature of these bus protocols, the extra delay does not
impact peripheral communication.
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Chip Select Registers
This section presents register data for the Chip Select x Lower and Upper Bound registers,
the Chip Select x Control Register and the Chip Select x Bus Mode Control Register.
Chip Select x Lower Bound Register
For memory chip selects, the Chip Select x Lower Bound Register, shown in Table 27,
defines the lower bound of the address range for which the corresponding Memory chip
select (if enabled) is active. For I/O chip selects, the Chip Select x Lower Bound Register
defines the address to which ADDR[15:8] is compared to generate an I/O chip select. All
chip select lower bound registers reset to 00h.
Table 27. Chip Select x Lower Bound Register (CSx_LBR)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
CS0_LBR Reset
CS1_LBR Reset
CS2_LBR Reset
CS3_LBR Reset
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
CS0_LBR = 00A8h, CS1_LBR = 00ABh, CS2_LBR = 00AEh, CS3_LBR = 00B1h
Note: R/W = read/write.
Bit
Description
[7:0]
CSx_LBR
Chip Select x Lower Bound
For Memory Chip Selects (CSx_IO = 0)
00h–FFh: This byte specifies the lower bound of the chip select address range. The
upper byte of the address bus, ADDR[23:16], is compared to the values contained
in these registers for determining whether a Memory chip select signal must be gen-
erated.
For I/O Chip Selects (CSx_IO = 1)
00h–FFh: This byte specifies the chip select address value. ADDR[15:8] is com-
pared to the values contained in these registers for determining whether an I/O chip
select signal must be generated.
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Chip Select x Upper Bound Register
For memory chip selects, the Chip Select x Upper Bound registers, shown in Table 28,
define the upper bound of the address range for which the corresponding Chip Select (if
enabled) are active. For I/O chip selects, this register produces no effect. The reset state for
the Chip Select 0 Upper Bound Register is FFh when the reset state for the other Chip
Select Upper Bound registers is 00h.
Table 28. Chip Select x Upper Bound Register (CSx_UBR)
Bit
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
CS0_UBR Reset
CS1_UBR Reset
CS2_UBR Reset
CS3_UBR Reset
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
CS0_UBR = 00A9h, CS1_UBR = 00ACh, CS2_UBR = 00AFh, CS3_UBR = 00B2h
Note: R/W = read/write.
Bit
Description
[7:0]
CSx_UBR
Chip Select x Upper Bound
For Memory Chip Selects (CSx_IO = 0)
00h–FFh: This byte specifies the upper bound of the chip select address range. The
upper byte of the address bus, ADDR[23:16], is compared to the values contained
in these registers for determining whether a chip select signal must be generated.
For I/O Chip Selects (CSx_IO = 1)
00h–FFh: No effect.
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Chip Select x Control Register
The Chip Select x Control Register, shown in Table 29, enables the chip selects, specifies
the type of chip select, and sets the number of wait states. The reset state for the Chip
Select 0 Control Register is E8hwhen the reset state for the 3 other Chip Select Control
registers is 00h.
Table 29. Chip Select x Control Register (CSx_CTL)
Bit
7
1
6
1
5
1
4
0
3
1
2
0
0
0
0
R
1
0
0
0
0
R
0
0
0
0
0
R
CS0_CTL Reset
CS1_CTL Reset
CS2_CTL Reset
CS3_CTL Reset
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Address
CS0_CTL = 00AAh, CS1_CTL = 00ADh, CS2_CTL = 00B0h, CS3_CTL = 00B3h
Note: R/W = read/write; R = read only.
Bit
Description
[7:5]
CSx_WAIT
Chip Select Wait States
000: 0 wait states are asserted when this chip select is active.
001: 1 wait state is asserted when this chip select is active.
010: 2 wait states are asserted when this chip select is active.
011: 3 wait states are asserted when this chip select is active.
100: 4 wait states are asserted when this chip select is active.
101: 5 wait states are asserted when this chip select is active.
110: 6 wait states are asserted when this chip select is active.
111: 7 wait states are asserted when this chip select is active.
[4]
CSx_IO
Chip Select I/O
0: Chip select is configured as a memory chip select.
1: Chip select is configured as an I/O chip select.
[3]
CSx_EN
Chip Select Enable
0: Chip select is disabled.
1: Chip select is enabled.
[2:0]
Reserved
These bits are reserved and must be programmed to 000.
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Chip Select x Bus Mode Control Register
The Chip Select Bus Mode Register, shown in Table 30, configures the chip select for
eZ80, Z80, Intel™, or Motorola bus modes. Changing the bus mode allows the eZ80F91
device to interface to peripherals based on the Z80, Intel™, or Motorola style asynchro-
nous bus interfaces. When a bus mode other than eZ80 is programmed for a particular chip
select, the CSx_WAIT setting in that Chip Select Control Register is ignored.
Table 30. Chip Select x Bus Mode Control Register (CSx_BMC)
Bit
7
6
5
4
–
0
0
0
0
R
3
2
1
0
Field
BUS_MODE
AD_MUX
BUS_CYCLE
CS0_BMC Reset
CS1_BMC Reset
CS2_BMC Reset
CS3_BMC Reset
R/W
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
CS0_BMC = 00F0h, CS1_BMC = 00F1h, CS2_BMC = 00F2h, CS3_BMC = 00F3h
Note: R/W = read/write; R = read only.
Bit
Description
[7:6]
BUS_MODE
Bus Mode
00: eZ80 BUS Mode.
01: Z80 BUS Mode.
10: Intel™ BUS Mode.
11: Motorola BUS Mode.
[5]
AD_MUX
Address Multiplexing
0: Separate address and data
1: Multiplexed address and data; appears on data bus DATA[7:0]
[4]
Reserved
This bit is reserved and must be programmed to 0.
Notes:
1. Setting the BUS_CYCLE to 1 in Intel bus mode causes the ALE pin to not function properly.
2. Use of the external WAIT input pin in Z80 mode requires that BUS_CYCLE is set to a value greater than 1.
3. BUS_CYCLE produces no effect in eZ80 mode.
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Bit
Description (Continued)
[3:0]
BUS_CYCLE
Bus Cycle
0000: Not valid.
1, 2, 3
0001: Each bus mode state is 1 eZ80 clock cycle in duration.
0010: Each bus mode state is 2 eZ80 clock cycles in duration.
0011: Each bus mode state is 3 eZ80 clock cycles in duration.
0100: Each bus mode state is 4 eZ80 clock cycles in duration.
0101: Each bus mode state is 5 eZ80 clock cycles in duration.
0110: Each bus mode state is 6 eZ80 clock cycles in duration.
0111: Each bus mode state is 7 eZ80 clock cycles in duration.
1000: Each bus mode state is 8 eZ80 clock cycles in duration.
1001: Each bus mode state is 9 eZ80 clock cycles in duration.
1010: Each bus mode state is 10 eZ80 clock cycles in duration.
1011: Each bus mode state is 11 eZ80 clock cycles in duration.
1100: Each bus mode state is 12 eZ80 clock cycles in duration.
1101: Each bus mode state is 13 eZ80 clock cycles in duration.
1110: Each bus mode state is 14 eZ80 clock cycles in duration.
1111: Each bus mode state is 15 eZ80 clock cycles in duration.
Notes:
1. Setting the BUS_CYCLE to 1 in Intel bus mode causes the ALE pin to not function properly.
2. Use of the external WAIT input pin in Z80 mode requires that BUS_CYCLE is set to a value greater than 1.
3. BUS_CYCLE produces no effect in eZ80 mode.
Bus Arbiter
The Bus Arbiter within the eZ80F91 allows external bus masters to gain control of the
CPU memory interface bus. During normal operation, the eZ80F91 device is the bus mas-
ter. External devices request master use of the bus by asserting the BUSREQ pin. The Bus
Arbiter forces the CPU to release the bus after completing the current instruction. When
the CPU releases the bus, the Bus Arbiter asserts the BUSACK pin to notify the external
device that it can master the bus. When an external device assumes control of the memory
interface bus, the bus acknowledge cycle is complete. Table 31 shows the status of the pins
on the eZ80F91 device during bus acknowledge cycles.
During a bus acknowledge cycle, the bus interface pins of the eZ80F91 device are used by
an external bus master to control the memory and I/O chip selects.
Table 31. eZ80F91 Pin Status During Bus Acknowledge Cycles
Signal
Pin Symbol
Direction
Description
ADDR23..ADDR0
Input
Allows external bus master to utilize the chip select logic of the
eZ80F91.
CS0
Output
Normal operation.
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Table 31. eZ80F91 Pin Status During Bus Acknowledge Cycles (Continued)
CS1
Output
Output
Output
Tristate
Input
Normal operation.
Normal operation.
Normal operation.
CS2
CS3
DATA7..0
IORQ
Allows external bus master to communicate with external peripherals.
Allows external bus master to utilize the chip select logic of the
eZ80F91.
MREQ
Input
Allows external bus master to utilize the chip select logic of the
eZ80F91.
RD
Tristate
Tristate
Tristate
Allows external bus master to communicate with external peripherals.
Allows external bus master to communicate with external peripherals.
Allows external bus master to communicate with external peripherals.
WR
INSTRD
Normal bus operation of the eZ80F91 device using CS0 to communicate to an external
peripheral is shown in Figure 20. Figure 21 shows an external bus master communicating
with an external peripheral during bus acknowledge cycles.
WAIT
RD
WR
External
Master
External
Peripheral
DATA
ADDRESS
IORQ
eZ80F91
MREQ
Chip Select
Wait State
Generator
CS0
CS1
CS2
CS3
Figure 20. Memory Interface Bus Operation During CPU Bus Cycles, Normal Operation
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WAIT
RD
WR
External
Master
External
Peripheral
DATA
ADDRESS
IORQ
eZ80F91
MREQ
Chip Select
Wait State
Generator
CS0
CS1
CS2
CS3
Figure 21. Memory Interface Bus Operation During Bus Acknowledge Cycles
During bus acknowledge cycles, the Memory and I/O chip select logic is controlled by the
external address bus and external IORQ and MREQ signals.
The following chip select features are not available during bus acknowledge cycles:
•
The chip select logic does not insert wait states during bus acknowledge cycles regard-
less of the WAIT configuration for the decoded chip select.
•
•
The bus mode controller does not function during bus acknowledge cycles.
Internal registers and memory addresses in the eZ80F91 device are not accessible dur-
ing bus acknowledge cycles.
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Random Access Memory
The eZ80F91 device features 8 KB (8192 bytes) of single-port data Random Access
Memory (RAM) for general-purpose use and 8 KB of RAM for the EMAC. RAM is
enabled or disabled, and it is relocated to the top of any 64 KB page in memory. Data is
passed to and from RAM via the 8-bit data bus. On-chip RAM operates with zero wait
states. EMAC RAM is accessed via the bus arbiter and executes with zero or one wait
states.
General purpose RAM occupies memory addresses in the RAM Address Upper Byte Reg-
ister in the range {RAM_ADDR_U[7:0], E000h}to {RAM_ADDR_U[7:0], FFFFh}.
EMAC RAM occupies memory addresses in the range {RAM_ADDR_U[7:0], C000h}to
{RAM_ADDR_U[7:0], DFFFh}. Following a RESET, RAM is enabled when
RAM_ADDR_U is set to FFh. Figure 22 shows a memory map for on-chip RAM. In this
example, RAM_ADDR_U is set to 7Ah. Figure 22 is not drawn to scale, as RAM occupies
only a very small fraction of the available 16MB address space.0
Memory
Location
FFFFFFh
7AFFFFh
8 KB
General-Purpose
RAM
RAM_ADDR_U
7Ah
7AE000h
7ADFFFh
8 KB
EMAC SRAM
7AC000h
000000h
Figure 22. Example: eZ80F91 On-Chip RAM Memory Addressing
When enabled, on-chip RAM assumes priority over on-chip Flash memory and any mem-
ory chip selects that is also enabled in the same address space. If an address is generated in
a range that is covered by both the RAM address space and a particular memory chip
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select address space, the memory chip select is not activated. On-chip RAM is not accessi-
ble to external devices during bus acknowledge cycles.
RAM Control Registers
This section presents register data for the RAM Control Register, the RAM Address
Upper Byte Register and the MBIST Control Register.
RAM Control Register
Internal general-purpose RAM is disabled by clearing the GPRAM_EN bit. The default on
RESET is for general purpose RAM to be enabled. See Table 32.
Table 32. RAM Control Register (RAM_CTL)
Bit
7
6
ERAM_EN
1
5
4
3
2
1
0
Field
Reset
R/W
GPRAM_EN
Reserved
1
0
0
R
0
0
0
0
R/W
R/W
R
R
R
R
R
Address
00B4h
Note: R/W = read/write; R = read only.
Bit
Description
[7]
General-Purpose RAM Enable
0: On-chip general-purpose RAM is disabled.
1: On-chip general-purpose RAM is enabled.
GPRAM_EN
[6]
ERAM_EN
EMAC RAM
0: On-chip EMAC RAM is disabled.
1: On-chip EMAC RAM is enabled.
[5:0]
Reserved
These bits are reserved and must be programmed to 000000.
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RAM Address Upper Byte Register
The RAM_ADDR_U Register, shown in Table 33, defines the upper byte of the address
for on-chip RAM. If enabled, RAM addresses assume priority over all Chip Selects. The
external Chip Select signals are not asserted if the corresponding RAM address is enabled.
Table 33. RAM Address Upper Byte Register (RAM_ADDR_U)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
RAM_ADDR_U
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
00B5h
Note: R/W = read/write.
Bit
Description
RAM Address Upper Byte
[7:0]
RAM_ADDR_U
00h–FFh: This byte defines the upper byte of the RAM address. When enabled, the
general-purpose RAM address space ranges from {RAM_ADDR_U, E000h} to
{RAM_ADDR_U, FFFFh}. When enabled, the EMAC RAM address space ranges from
{RAM_ADDR_U, C000h} to {RAM_ADDR_U, DFFFh}.
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MBIST Control
There are two Memory Built-In Self-Test (MBIST) controllers for the RAM blocks on the
eZ80F91 MCU; MBIST_GPR is for general-purpose RAM and MBIST_EMR is for
EMAC RAM. Writing a 1 to MBIST_ON starts the MBIST testing. Writing a 0 to
MBIST_ON stops the MBIST testing. On completion of the MBIST testing, MBIST_ON
is automatically reset to 0. If RAM passes MBIST testing, MBIST_PASS is 1. The value
in MBIST_PASS is only valid when MBIST_DONE is High. See Table 34.
Table 34. MBIST Control Register (MBIST_GPR, MBIST_EMR)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
MBIST_ON MBIST_DONE MBIST_PASS
Reset
R/W
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
Address
MBIST_GPR=00B6h, MBIST_EMR=00B7h
Note: R/W = read/write; R = read only.
Bit
Description
[7]
MBIST_ON
Memory Built-In Self Test Enable
0: MBIST Testing of the RAM is disabled.
1: MBIST Testing of the RAM is enabled.
[6]
Memory Built-In Self Test Complete
MBIST_DONE 0: MBIST Testing has not completed.
1: MBIST Testing has completed.
[5]
Memory Built-In Self Test Pass/Fail
MBIST_PASS 0: MBIST Testing has failed.
1: MBIST Testing has passed.
[4:0]
Reserved
These bits are reserved and must be programmed to 00000.
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Flash Memory
The eZ80F91 device features 256 KB (262,144 bytes) of non-volatile Flash memory with
read/write/erase capability. The main Flash memory array is arranged in 128 pages with 8
rows per page and 256 bytes per row. In addition to main Flash memory, there are two sep-
arately addressable rows which comprise a 512-byte information page.
In eight 32 KB blocks, 256KB of main storage is protected. Protecting a 32 KB block pre-
vents write or erase operations. The lower 32 KB block (00000h–07FFFh) is protected
using the external WP pin. This portion of memory is called the boot block because the
CPU always starts executing code from this location at startup. If the application requires
external program memory, then the boot block must at least contain a jump instruction to
move the Program Counter outside of the Flash memory space.
The Flash memory arrangement is shown in Figure 23.
16
8
8
2 KB pages
per block
256-byte rows
per page
32 KB blocks
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
256
single-byte columns
per row
255 254
1
0
Figure 23. eZ80F91 Flash Memory Arrangement
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Flash Memory Overview
The eZ80F91 device includes a Flash memory controller that automatically converts stan-
dard CPU read and write cycles to the specific protocol required for the Flash memory
array. As such, standard memory read and write instructions access the Flash memory
array as if it is internal RAM. The controller also supports I/O access to the Flash memory
array, in effect presenting it as an indirectly addressable bank of I/O registers. These
access methods are also supported via the ZDI and OCI™ interfaces.
In addition, eZ80AcclaimPlus!™ Flash Microcontrollers support a Flash read–while–
write methodology. In other words, the eZ80 CPU continues to read and execute code
from an area of Flash memory when a nonconflicting area of Flash memory is being pro-
grammed.
The Flash memory controller contains a frequency divider, a Flash Register interface, and
a Flash control state machine. A simplified block diagram of the Flash controller is shown
in Figure 24.
Clock Divider
8-bit downcounter
System Clock
17
8
ADDR
DOUT
FDOUT
8
eZ80 Core
Interface
FADDR
FDIN
17
8
Flash
256 KB
+
FCNTL
9
Flash
State
Machine
512 bytes
MAIN_INFO
Flash
Control
Registers
CPUDOUT
8
FLASH_IRQ
Figure 24. Flash Memory Block Diagram
Reading Flash Memory
The main Flash memory array is read using both memory and I/O operations. As an auxil-
iary storage area, the information page is only accessible via I/O operations. In all cases,
wait states are automatically inserted to allow for read access time.
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Memory Read
A memory read operation uses the address bus and data bus of the eZ80F91 device to read
a single data byte from Flash memory. This read operation is similar to reads from RAM.
To perform Flash memory reads, the FLASH_CTRL Register must be configured to
enable memory access to Flash with the appropriate number of wait states. See Table 38
on page 102.
Only the main area of Flash memory is accessible via memory reads. The information
page must be read using I/O access.
I/O Read
A single-byte I/O read operation uses I/O registers for setting the column, page, and row
address to be read. A read of the FLASH_DATA Register returns the contents of Flash
memory at the designated address. Each access to the FLASH_DATA Register causes an
autoincrement of the Flash address stored in the Flash address registers (FLASH_PAGE,
FLASH_ROW, FLASH_COL). To allow for Flash memory access time, the
FLASH_CTRL Register must be configured with the appropriate number of wait states.
See Table 38 on page 102.
Programming Flash Memory
Flash memory is programmed using standard I/O or memory write operations that the
Flash memory controller automatically translates to the detailed timing and protocol
required for Flash memory. The more efficient multibyte (row) programming mode is only
available via I/O writes.
To ensure data integrity and device reliability, two main restrictions exist on programming
of Flash memory:
Notes:
1. The cumulative programming time since the last erase cannot exceed 31ms for any
given row.
2. The same byte cannot be programmed more than once since the previous erase.
Single-Byte I/O Write
A single-byte I/O write operation uses I/O registers for setting the column, page, and row
address to be written. The FLASH_DATA Register stores the data to be written. While the
CPU executes an I/O instruction to load the data into the FLASH_DATA Register, the
Flash controller asserts the internal WAIT signal to stall the CPU until the Flash write
operation is complete. A single-byte write takes between 66 µs and 85 µs to complete.
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Programming an entire row (256 bytes) using single-byte writes therefore takes no more
than 21.8ms. This duration of time does not include the time required by the CPU to trans-
fer data to the registers which is a function of the instructions employed and the system
clock frequency. Each access to the FLASH_DATA Register causes an autoincrement of
the Flash address stored in the Flash Address registers (FLASH_PAGE, FLASH_ROW,
FLASH_COL).
A typical sequence that performs a single-byte I/O write is shown below. Because the
write is self-timed, Step 2 of the sequence is repeated back-to-back without requiring poll-
ing or interrupts.
1. Write the FLASH_PAGE, FLASH_ROW, and FLASH_COL registers with the
address of the byte to be written.
2. Write the data value to the FLASH_DATA Register.
Multibyte I/O Write (Row Programming)
Multibyte I/O write operations use the same I/O registers as single-byte writes. Multibyte
I/O writes allow the programming of full row and are enabled by setting the ROW_PGM
bit of the Flash Program Control Register. For multibyte I/O writes, the CPU sets the
address registers, enables row programming, and then executes an I/O instruction (with
repeat) to load the block of data into the FLASH_DATA Register. For each individual byte
written to the FLASH_DATA Register during the block move, the Flash controller asserts
the internal WAIT signal to stall the CPU until the current byte is programmed. Each
access to the FLASH_DATA Register causes an autoincrement of the Flash address stored
in the Flash Address registers (FLASH_PAGE, FLASH_ROW, FLASH_COL).
During row programming, the Flash controller continuously asserts the Flash memory’s
high voltage signal until all bytes are programmed (column address < 255). As a result, the
row programs more quickly than if the high-voltage signal is toggled for each byte. The
per-byte programming time during row programming is between 41µs and 52µs. As such,
programming 256 bytes of a row in this mode takes not more than 13.4ms, leaving 17.6ms
for CPU instruction overhead to fetch the 256 bytes.
A typical sequence that performs a multibyte I/O write is shown below:
1. Check the FLASH_IRQ Register to ensure that any previous row program is com-
pleted.
2. Write the FLASH_PAGE, FLASH_ROW, and FLASH_COL registers with the
address of the first byte to be written.
3. Set the ROW_PGM bit in the FLASH_PGCTL Register to enable row programming
mode.
4. Write the next data value to the FLASH_DATA Register.
5. If the end of the row has not been reached, return to Step 4.
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During row programming, software must monitor the row time-out error bit either by
enabling this interrupt or via polling. If a row time-out occurs, the Flash controller aborts
the row programming operation, and software must assure that no further writes are per-
formed to the row without it first being erased. It is suggested that row programming is be
used one time per row and not in combination with single-byte writes to the same row
without first erasing it. Otherwise, the burden is on software to ensure that the 31 ms max-
imum cumulative programming time between erases is not exceeded for a row.
Memory Write
A single-byte memory write operation uses the address bus and data bus of the eZ80F91
device for programming a single data byte to Flash memory. While the CPU executes a
Load instruction, the Flash controller asserts the internal WAIT signal to stall the CPU
until the write is complete. A single-byte write takes between 66 µs and 85µs to complete.
Programming an entire row using memory writes therefore takes no more than 21.8ms.
This duration of time does not include time required by the CPU to transfer data to the reg-
isters, which is a function of the instructions employed and the system clock frequency.
The memory write function does not support multibyte row programming. Because mem-
ory writes are self-timed, they are performed back-to-back without requiring polling or
interrupts.
Erasing Flash Memory
Erasing bytes in Flash memory returns them to a value of FFh. Both the mass and page
erase operations are self-timed by the Flash controller, leaving the CPU free to execute
other operations in parallel. The DONE status bit in the Flash Interrupt Control Register
are polled by software or used as an interrupt source to signal completion of an erase oper-
ation. If the CPU attempts to access Flash memory while an erase is in progress, the Flash
controller forces a wait state until the erase operation is completed.
Mass Erase
Performing a mass erase operation on Flash memory erases all bits contained in the main
Flash memory array. The information page remains unaffected unless the FLASH_PAGE
Register bit 7 (INFO_EN) is set. This self-timed operation takes approximately 200ms to
complete.
Page Erase
The smallest erasable unit in Flash memory is a page. The pages to be erased, whether
they are the 128 main Flash memory pages or the information page, are determined by the
setting of the FLASH_PAGE Register. This self-timed operation takes approximately
10 ms to complete.
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Information Page Characteristics
As noted earlier, the information page is not accessible using memory access instructions
and must be accessed via the FLASH_DATA I/O Register. The Flash Page Select Register
contains a bit which selects the information page for I/O access.
There are two ways to erase the information page. You must set the FLASH_PAGE Regis-
ter bit7 (INFO_EN; 0x00FC) and then you execute either a mass erase operation (which
also erases the entire main Flash memory array) or a page erase operation.
Flash Control Registers
The Flash Control Register interface contains all of the registers used in Flash memory.
The definitions in this section describe each register.
Flash Key Register
Writing the two-byte sequence B6h, 49hin immediate succession to this register unlocks
the Flash Divider and Flash Write/Erase Protection registers. If these values are not writ-
ten by consecutive CPU I/O writes (I/O reads and memory read/writes have no effect), the
Flash Divider and Flash Write/Erase Protection registers remain locked. This prevents
accidental overwrites of these critical Flash Control Register settings. Writing a value to
either the Flash Frequency Divider Register or the Flash Write/Erase Protection Register
automatically relocks both of the registers. See Table 35.
Table 35. Flash Key Register (FLASH_KEY)
Bit
7
6
5
4
3
2
1
0
Field
FLASH_KEY
Reset
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Address
Note: W = write only.
00F5h
Bit
Description
Flash Key
[7:0]
FLASH_KEY B6h, 49h: Sequential write operations of the values B6h, 49h to this register will unlock
the Flash Frequency Divider and Flash Write/Erase Protection registers.
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Flash Data Register
The Flash Data Register, shown in Table 36, stores the data values to be programmed into
Flash memory via I/O write operations. An I/O read of the Flash Data Register returns data
from Flash memory. The Flash memory address used for I/O access is determined by the
contents of the page, row, and column registers. Each access to the FLASH_DATA Register
causes an autoincrement of the Flash address stored in the Flash Address registers
(FLASH_PAGE, FLASH_ROW, FLASH_COL).
Table 36. Flash Data Register (FLASH_DATA)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
00F6h
Note: U = undefined; R/W = read/write.
Bit
Description
Flash Data
[7:0]
FLASH_DATA 00h–FFh: Data value to be written to Flash memory during an I/O write operation, or the
data value that is read in Flash memory, indicated by the Flash Address registers
(FLASH_PAGE, FLASH_ROW, FLASH_COL).
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Product Specification
101
Flash Address Upper Byte Register
The FLASH_ADDR_U Register, shown in Table 37, defines the upper 6 bits of the Flash
memory address space. Changing the value of FLASH_ADDR_U allows on-chip 256 KB
Flash memory to be mapped to any location within the 16MB linear address space of the
eZ80F91 device. If on-chip Flash memory is enabled, the Flash address assumes priority
over any external chip selects. The external chip select signals are not asserted if the corre-
sponding Flash address is enabled. Internal Flash memory does not hold priority over
internal SRAM.
Table 37. Flash Address Upper Byte Register (FLASH_ADDR_U)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
FLASH_ADDR_U
Reserved
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Address
00F7h
Note: R/W = read/write; R = read only.
Bit
Description
Flash Address Upper Byte
[7:2]
FLASH_ADDR_U
00h–FCh: These bits define the upper byte of the Flash address. When on-chip
Flash is enabled, the Flash address space begins at address {FLASH_ADDR_U,
00b, 0000h}. On-chip Flash has priority over all external Chip Selects.
[1:0]
Reserved
Enforces alignment on a 256KB boundary. These read-only bits are reserved and
must be programmed to 00.
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Product Specification
102
Flash Control Register
The Flash Control Register, shown in Table 38, enables or disables memory access to
Flash memory. I/O access to the Flash control registers and to Flash memory is still possi-
ble while Flash memory space access is disabled.
The minimum access time of internal Flash memory is 60ns. The Flash Control Register
must be configured to provide the appropriate number of wait states based on the system
clock frequency of the eZ80F91 device. Because the maximum SCLK frequency is
50 MHz (20ns), the default on RESET is for four wait states to be inserted for Flash mem-
ory access (Flash memory access + one eZ80 bus cycle = 60 ns + 20 ns = 80ns;
80 ns ÷ 20 ns = 4 wait states).
Table 38. Flash Control Register (FLASH_CTRL)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
FLASH_WAIT
Reserved FLASH_EN
Reserved
1
0
0
0
1
0
0
0
R/W
R/W
R/W
R
R/W
R
R
R
Address
00F8h
Note: R/W = read/write, R = read only.
Bit
Description
[7:5]
Flash Wait States
FLASH_WAIT 000: 0 wait states are inserted when the Flash is active.
001: 1 wait state is inserted when the Flash is active.
010: 2 wait states are inserted when the Flash is active.
011: 3 wait states are inserted when the Flash is active.
100: 4 wait states are inserted when the Flash is active.
101: 5 wait states are inserted when the Flash is active.
110: 6 wait states are inserted when the Flash is active.
111: 7 wait states are inserted when the Flash is active.
[4]
Reserved
This bit is reserved and must be programmed to 0.
[3]
Flash Enable
FLASH_EN
0: Flash memory access is disabled.
1: Flash memory access is enabled.
[2:0]
Reserved
These bits are reserved and must be programmed to 000.
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Product Specification
103
Flash Frequency Divider Register
The 8-bit frequency divider allows the programming of Flash memory over a range of sys-
tem clock frequencies. Flash is programmed with system clock frequencies ranging from
154kHz to 50MHz. The Flash controller requires an input clock with a period that falls
within the range of 5.1-6.5µs. The period of the Flash controller clock is set in the Flash
Frequency Divider Register. Writes to this register is allowed only after it is unlocked via
the FLASH_KEY Register. The Flash Frequency Divider Register value required versus
the system clock frequency is shown in Table 39. System clock frequencies outside of the
ranges shown are not supported. Register values for the Flash Frequency Divider are
shown in Table 40.
Table 39. Flash Frequency Divider Values
System Clock Frequency
Flash Frequency Divider Value
154–196kHz
308–392kHz
462–588kHz
616kHz–50MHz
1
2
3
CEILING [System Clock Frequency (MHz) x 5.1 (µs)]*
Note: *The CEILING function rounds fractional values up to the next whole number. For example,
CEILING(3.01) is 4.
Table 40. Flash Frequency Divider Register (FLASH_FDIV)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
FLASH_FDIV
0
0
0
0
0
0
0
1
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W
Address
00F9h
Note: *Key sequence required to enable writes; R/W = read/write, R = read only.
Bit
Description
[7:0]
Flash Frequency Divider
FLASH_FDIV 01h–FFh: Divider value for generating the required 5.1-6.5 µ s Flash controller clock
period.
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Product Specification
104
Flash Write/Erase Protection Register
The Flash Write/Erase Protection Register prevents accidental write or erase operations.
The protection is limited to a resolution of eight 32 KB blocks. Setting a bit to 1 protects
that 32KB block of Flash memory from accidental writes or Erases. The default upon
RESET is for all Flash memory blocks to be protected.
The WP pin works in conjunction with FLASH_PROT[0] to protect the lowest block (also
called the boot block) of Flash memory. If either the WP is held asserted or
FLASH_PROT[0] is set, the boot block is protected from write and erase operations.
A protect bit is not available for the information page. The information page is, however,
protected excluded from a mass erase by clearing the FLASH_PAGE Register (0x00FC)
bit7 (INFO_EN).
Note:
Writes to this register is allowed only after it is unlocked via the FLASH_KEY Register.
Any attempted writes to this register while locked will set it to FFh, thereby protecting all
blocks. See Table 41.
Table 41. Flash Write/erase Protection Register (FLASH_PROT)
Bit
7
6
5
4
3
2
1
0
BLK7_
PROT
BLK6_
PROT
BLK5_
PROT
BLK4_
PROT
BLK3_
PROT
BLK2_
PROT
BLK1_
PROT
BLK0_
PROT
Field
Reset
R/W
1
1
1
1
1
1
1
1
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
00FAh
Note: *Key sequence required to unlock; R/W = read/write if unlocked, R = read only if locked.
Bit
Description
[7]
Block 7 Protection
BLK7_PROT 0: Disable Write/Erase Protect on block 38000h to 3FFFFh.
1: Enable Write/Erase Protect on block 38000h to 3FFFFh.
[6]
Block 6 Protection
BLK6_PROT 0: Disable Write/Erase Protect on block 30000h to 37FFFh.
1: Enable Write/Erase Protect on block 30000h to 37FFFh.
[5]
Block 5 Protection
BLK5_PROT 0: Disable Write/Erase Protect on block 28000h to 2FFFFh.
1: Enable Write/Erase Protect on block 28000h to 2FFFFh.
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105
Bit
Description (Continued)
Block 4 Protection
[4]
BLK4_PROT 0: Disable Write/Erase Protect on block 20000h to 27FFFh.
1: Enable Write/Erase Protect on block 20000h to 27FFFh.
[3]
Block 3 Protection
BLK3_PROT 0: Disable Write/Erase Protect on block 18000h to 1FFFFh.
1: Enable Write/Erase Protect on block 18000h to 1FFFFh.
[2]
Block 2 Protection
BLK2_PROT 0: Disable Write/Erase Protect on block 10000h to 17FFFh.
1: Enable Write/Erase Protect on block 10000h to 17FFFh.
[1]
Block 1 Protection
BLK1_PROT 0: Disable Write/Erase Protect on block 08000h to 0FFFFh.
1: Enable Write/Erase Protect on block 08000h to 0FFFFh.
[0]
Block 0 Protection
BLK0_PROT 0: Disable Write/Erase Protect on block 00000h to 07FFFh.
1: Enable Write/Erase Protect on block 00000h to 07FFFh.
Note: The lower 32KB block (00000h to 07FFFh; BLK0) is called the boot block and is protected using the external
WP pin.
Flash Interrupt Control Register
There are two sources of interrupts from the Flash controller. These two sources are:
•
•
Page erase, mass erase, or row program completed successfully
An error condition occurred
Either or both of these two interrupt sources are enabled by setting the appropriate bits in
the Flash Interrupt Control Register.
The Flash Interrupt Control Register contains four status bits to indicate the following
error conditions:
Row Program Time-Out
This bit signals a time-out during row programming. If the current row program operation
does not complete within 4864 Flash controller clocks, the Flash controller terminates the
row program operation by clearing bit 2 of the Flash Program Control Register and sets
the RP_TM0 error bit to 1.
Write Violation
This bit indicates an attempt to write to a protected block of Flash memory (the write was
not performed).
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Product Specification
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Page Erase Violation
This bit indicates an attempt to erase a protected block of Flash memory (the requested
page was not erased).
Mass Erase Violation
This bit indicates an attempt to mass erase when there are one or more protected blocks in
Flash memory (the mass erase was not performed).
If the error condition interrupt is enabled, any of these four error conditions result in an
interrupt request being sent to the eZ80F91device’s interrupt controller. Reading the Flash
Interrupt Control Register clears all error condition flags and the DONE flag. See Table
42.
Table 42. Flash Interrupt Control Register (FLASH_IRQ)
Bit
7
6
5
4
3
2
1
0
Field
DONE_
IEN
ERR_
IEN
DONE Reserved
WR_
VIO
RP_
TMO
PG_
VIO
MASS_
VIO
Reset
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R
R
R
R
R
R
Address
00FBh
Note: R/W = read/write, R = read only. A read resets bits [5] and [3:0].
Bit
Description
[7]
Flash Erase/Row Program Done Interrupt
0: Interrupt is disabled.
DONE_IEN
1: Interrupt is enabled.
[6]
ERR_IEN
Error Condition Interrupt
0: Interrupt is disabled.
1: Interrupt is enabled.
[5]
DONE
Erase/Row Program Done Flag
0: Flag is not set.
1: Flag is set.
[4]
Reserved
This bit is reserved and must be programmed to 0.
[3]
WR_VIO
Write Violation Error Flag
0: Flag is not set.
1: Flag is set.
Note: The lower 32KB block (00000h to 07FFFh) is called the boot block and is protected using the external WP pin.
Attempts to page erase BLK0 or mass erase Flash when WP is asserted result in failure and signal an erase
violation.
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Product Specification
107
Bit
Description (Continued)
[2]
RP_TMO
Row Program Time-Out Error Flag
0: Flag is not set.
1: Flag is set.
[1]
Page Erase Violation Error Flag
PG_VIO
0: The page erase violation error flag is not set.
1: The page erase violation error flag is set.
[0]
Mass Erase Violation Error Flag
MASS_VIO
0: The mass erase violation error flag is not set.
1: The mass erase violation error flag is set.
Note: The lower 32KB block (00000h to 07FFFh) is called the boot block and is protected using the external WP pin.
Attempts to page erase BLK0 or mass erase Flash when WP is asserted result in failure and signal an erase
violation.
Flash Page Select Register
The msb of this register is used to select whether I/O Flash access and page erase opera-
tions are directed to the 512-byte information page or to the main Flash memory array, and
also whether the information page is included in mass erase operations. The lower 7 bits
are used to select one of the main 128 pages for page erase or I/O operations.
To perform a page erase, the software must set the proper page value prior to setting the
page erase bit in the Flash Control Register. In addition, each access to the FLASH_DATA
Register causes an autoincrement of the Flash address stored in the Flash Address registers
(FLASH_PAGE, FLASH_ROW, FLASH_COL). See Table 43.
Table 43. Flash Page Select Register (FLASH_PAGE)
Bit
7
INFO_EN
0
6
5
4
3
FLASH_PAGE
0
2
1
0
Field
Reset
R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
00FCh
Note: R/W = read/write, R = read only.
Bit
Description
Flash I/O Access to Page Erase Operations
[7]
INFO_EN
0: Directed to main Flash memory. Info page is not affected by a mass erase operation.
1: Directed to the information page. Page erase operations only affect the information
page. Info page is included during a mass erase operation
[6:0]
Flash Page Address
FLASH_PAGE 00h–7Fh: Page address of Flash memory to be used during a page erase or I/O access
of main Flash memory. When INFO_EN is set to 1, this field is ignored.
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108
Flash Row Select Register
The Flash Row Select Register, shown in Table 44, is a 3-bit value used to define one of
the 8 rows of Flash on a single page. This register is used for all I/O access to Flash mem-
ory. In addition, each access to the FLASH_DATA Register causes an autoincrement of
the Flash address stored in the Flash Address registers (FLASH_PAGE, FLASH_ROW,
FLASH_COL).
Table 44. Flash Row Select Register (FLASH_ROW)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
Reserved
FLASH_ROW
U
R
U
R
U
R
U
R
U
R
0
0
0
R/W
R/W
R/W
Address
00FDh
Note: U = undefined; R/W = read/write, R = read only.
Bit
Description
Reserved
[7:3]
These bits are reserved and must be programmed to 00h.
[2:0]
Flash Row Address
FLASH_ROW 0h–7h: Row address of Flash memory to be used during an I/O access of Flash memory.
When INFO_EN is 1 in the Flash Page Select Register, values for this field are restricted
to 0h–1h, which selects between the two rows in the information page.
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Flash Column Select Register
The Flash Column Select Register, shown in Table 45, is an 8-bit value used to define one
of the 256 bytes of Flash memory contained in a single row. This register is used for all I/
O access to Flash memory. In addition, each access to the FLASH_DATA Register causes
an autoincrement of the Flash address stored in the Flash Address registers
(FLASH_PAGE, FLASH_ROW, FLASH_COL).
Table 45. Flash Column Select Register (FLASH_COL)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
FLASH_COL
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
00FEh
Note: R/W = read/write, R = read only.
Bit
Description
[7:0]
Flash Column Select
FLASH_COL 00h–FFh: Column address of Flash memory to be used during an I/O access of Flash
memory.
Flash Program Control Register
The Flash Program Control Register, shown in Table 46, is used to perform the functions
of mass erase, page erase, and row program. The mass erase and page erase operations are
self-clearing functions.
A mass erase operation requires approximately 200ms to completely erase the full 256KB
of main Flash and the 512-byte information page if the FLASH_PAGE Register bit7
(INFO_EN; 0x00FC) is set. The 200ms time is not reduced by excluding the 512 byte
information page from erasing.
A page erase operation requires approximately 10ms to erase a 2KB page.
On completion of either a mass erase or page erase, the value of each corresponding bit is
reset to 0.
When Flash is being erased, any read or write access to Flash forces the CPU into a wait
state until the erase operation is complete and the Flash is accessed. Reads and writes to
areas other than Flash memory proceeds as usual while an erase operation is under way.
During row programming, any reads of Flash memory force a WAIT condition until the
row programming operation completes or times out.
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110
Table 46. Flash Program Control Register (FLASH_PGCTL)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
Reserved
ROW_PGM PG_ERASE MASS_ERASE
0
0
0
0
0
0
0
0
R
R
R
R
R
R/W
R/W
R/W
Address
00FFh
Note: R/W = read/write, R = read only.
Bit
Description
Reserved
[7:3]
These bits are reserved and must be programmed to 00h.
[2]
Row Program Enable
ROW_PGM
0: Row program disable or row program completed.
1: Row program enable. This bit automatically resets to 0 when the row address reaches
256 or when the row program operation times out.
[1]
Page Erase Enable
PG_ERASE
0: Page erase disable (page erase completed).
1: Page erase enable. This bit automatically resets to 0 when the page erase operation is
complete.
[0]
Mass Erase Enable
MASS_ERASE 0: Mass erase disable (mass erase completed).
1: Mass erase enable. This bit automatically resets to 0 when the mass erase operation is
complete.
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Product Specification
111
Watchdog Timer
The Watchdog Timer (WDT) helps protect against corrupt or unreliable software, power
faults, and other system-level problems which places the CPU into unsuitable operating
states. The eZ80F91 WDT features:
•
Four programmable time-out ranges (depending on the WDT clock source). The four
ranges are:
–
–
–
–
03.2–5.20ms
51.2–83.9ms
0.50–0.82 sec
2.68–4.00 sec
•
Three selectable WDT clock sources:
–
–
–
Internal RC oscillator
System clock
Real-Time Clock source (on-chip 32 kHz crystal oscillator or 50/60 Hz signal)
•
•
A selectable time-out response: a time-out is configured to generate either a RESET or
a nonmaskable interrupt (NMI)
A WDT time-out RESET indicator flag
Figure 25 shows a block diagram of the Watchdog Timer.
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Watchdog Timer
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Product Specification
112
Control Register/
Reset Register
WDT_CLK
RTC Clock
28-Bit
Upcounter
System Clock
WDT Control Logic
Time-out Compare Logic
(WDT_PERIOD)
WDT
Oscillator
RESET
¤
NMI to eZ80 CPU
Figure 25. Watchdog Timer Block Diagram
Watchdog Timer Operation
This section presents configuration options for the Watchdog Timer.
Enabling and Disabling the Watchdog Timer
The WDT is disabled on a RESET. To enable the WDT, the application program must set
WDT_EN, which is bit 7 of the WDT_CTL Register. After WDT_EN is set, no writes are
allowed to the WDT_CTL Register. When enabled, the WDT cannot be disabled except
by a RESET.
Time-Out Period Selection
There are four choices of time-out periods for the WDT. The WDT time-out period is
defined by the WDT_PERIOD WDT_CTL[1:0] field and WDT_CLK WDT_CTL[3:2]
field of the Watchdog Timer Control Register (WDT_CTL = 0093h). The approximate
time-out period and corresponding clock cycles for three different WDT clock sources are
listed in Table 47.
The WDT time-out period divider is set to one of the four available settings for the
selected frequency of the WDT clock source. Basing the divider settings on the clock
source values provides a time-out range from few seconds to few milliseconds, regardless
of the frequency setting.
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Watchdog Timer
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Product Specification
113
Table 47. WDT Approximate Time-Out Delays for Possible Clock Sources
WDT_CLK[3:2]
00
01
10
11
Internal RC
Oscillator
(~10kHz)
50MHz
System Clock
32.768kHz
RTC Clock
Reserved
Time
Time
Time
Time
WDT_PERIOD[1:0]
Divider
Out
2.68s
0.67s
83.9ms
5.2ms
Divider
Out
4.00s
0.5 s
Divider
Out
Divider
Out
27
17
15
00
01
10
11
2
2
2
3.28 s
0.82 s
51.2 ms
3.2 ms
–
–
–
–
–
25
14
13
2
2
2
–
22
11
9
2
2
62.5 ms
3.9 ms
2
–
18
7
5
2
2
2
–
RESET or NMI Generation
A WDT time-out causes a RESET or sends a NMI signal to the CPU. The default opera-
tion is for the WDT to cause a RESET.
If the NMI_OUT bit in the WDT_CTL Register is set to 0, then on a WDT time-out, the
RST_FLAG bit in the WDT_CTL Register is set to 1. The RST_FLAG bit is polled by the
CPU to determine the source of the RESET event.
If the NMI_OUT bit in the WDT_CTL Register is set to 1, then on time-out, the WDT
asserts an NMI for CPU processing. The NMI_FLAG bit is polled by the CPU to deter-
mine the source of the NMI event.
Watchdog Timer Registers
This section presents the Watchdog Timer Control and Reset registers.
Watchdog Timer Control Register
The Watchdog Timer Control Register, shown in Table 48, is an 8-bit read/write Register
used to enable the Watchdog Timer, set the time-out period, indicate the source of the most
recent RESET or NMI, and select the required operation on WDT time-out.
The default clock source for the WDT is the WDT oscillator (WDT_CLK = 10b). To
power-down the WDT oscillator, another clock source must be selected. The power-up
sequence of the WDT oscillator takes approximately 20 ms.
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114
Table 48. Watchdog Timer Control Register (WDT_CTL)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
WDT_EN NMI_OUT RST_FLAG NMI_FLAG
WDT_CLK
WDT_PERIOD
0
0
0/1
R
0
1
0
0
0
R/W
R/W
R
R/W
R/W
R/W
R/W
Address
0093h
Note: R = Read only; R/W = read/write.
Bit
Description
[7]
WDT_EN
Watchdog Timer Enable
0: WDT is disabled.
1: WDT is enabled. When enabled, the WDT cannot be disabled without a RESET.
[6]
NMI_OUT
Watchdog Timer Nonmaskable Interrupt
0: WDT time-out resets the CPU.
1: WDT time-out generates a NMI to the CPU.
[5]
RST_FLAG
Watchdog Timer Reset Flag
0: RESET caused by external full-chip reset or ZDI reset.
1: RESET caused by WDT time-out. This flag is set by the WDT time-out, only if the
NMI_OUT flag is set to 0. The CPU polls this bit to determine the source of the RESET.
This flag is cleared by a non-WDT generated reset.
[4]
NMI_FLAG
Watchdog Timer Nonmaskable Interrupt Flag
0: NMI caused by external source.
1: NMI caused by WDT time-out. This flag is set by the WDT time-out, only if the
NMI_OUT flag is set to 1. The CPU polls this bit to determine the source of the NMI.
This flag is cleared by a non-WDT NMI.
[3:2]
Watchdog Timer Clock Source
WDT_CLK
00: WDT clock source is system clock.
01: WDT clock source is Real-Time Clock source (32kHz on-chip oscillator or 50/60 Hz
input as set by RTC_CTRL[4]).
10: WDT clock source is internal RC oscillator (10kHz typical).
11: This bit is reserved and must be programmed to 11.
Note: When the WDT is enabled, no writes are allowed to the WDT_CTL Register.
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Product Specification
115
Bit
Description (Continued)
Watchdog Timer Period
[1:0]
WDT_PERIOD
27
00: WDT_CLK = 00: WDT time-out period is 2 clock cycles.
17
WDT_CLK = 01: WDT time-out period is 2 clock cycles.
15
WDT_CLK = 10: WDT time-out period is 2 clock cycles.
WDT_CLK = 11: reserved.
25
01: WDT_CLK = 00: WDT time-out period is 2 clock cycles.
14
WDT_CLK = 01: WDT time-out period is 2 clock cycles.
13
WDT_CLK = 10: WDT time-out period is 2 clock cycles.
WDT_CLK = 11: reserved.
22
10: WDT_CLK = 00: WDT time-out period is 2 clock cycles.
11
WDT_CLK = 01: WDT time-out period is 2 clock cycles.
9
WDT_CLK = 10: WDT time-out period is 2 clock cycles.
WDT_CLK = 11: reserved.
18
11: WDT_CLK = 00: WDT time-out period is 2 clock cycles.
7
WDT_CLK = 01: WDT time-out period is 2 clock cycles.
5
WDT_CLK = 10: WDT time-out period is 2 clock cycles.
WDT_CLK = 11: reserved.
Note: When the WDT is enabled, no writes are allowed to the WDT_CTL Register.
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Product Specification
116
Watchdog Timer Reset Register
The WDT Reset Register, shown in Table 49, is an 8-bit write-only register. The WDT is
reset when an A5hvalue followed by a 5Ahvalue is written to this register. Any amount of
time occurs between the writing of A5hvalue and the 5Ahvalue, so long as the WDT
time-out does not occur prior to completion. Any value other than 5Ahwritten to the WDT
Reset Register after the A5hvalue requires that the sequence of writes (A5h,5Ah) be
restarted for the timer to be reset.
Table 49. Watchdog Timer Reset Register (WDT_RR)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
WDT_RR
U
U
U
U
U
U
U
U
W
W
W
W
W
W
W
W
Address
0094h
Note: U = undefined; W = write only.
Bit
Description
[7:0]
WDT_RR
Watchdog Timer Reset
A5h: The first write value required to reset the WDT prior to a time-out.
5Ah: The second write value required to reset the WDT prior to a time-out. If an A5h, 5Ah
sequence is written to WDT_RR, the WDT timer is reset to its initial count value and
counting resumes.
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Programmable Reload Timers
The eZ80F91 device features four programmable reload timers. The core of each timer is a
16-bit downcounter. In addition, each timer features a selectable clock source, adjustable
prescaling and operates in either SINGLE PASS or CONTINUOUS mode.
In addition to the basic timer functionality, some of the timers support specialty modes
that performs event counting, input capture, output compare, and PWM generation func-
tions. PWM Mode supports four individually-configurable outputs and a power trip func-
tion.
Each of the four timers available on the eZ80F91 device are controlled individually. They
do not share the same counters, reload registers, control registers, or interrupt signals. A
simplified block diagram of a programmable reload timer is shown in Figure 26.
Each timer features its own interrupt which is triggered either by the timer reaching zero
or after a successful comparison occurs. As with the other eZ80F91 interrupts, the priority
is fully programmable.
Input Capture
Registers
CONTROL
ICx
R
E
L
O
A
D
16-Bit
Down Counter
Comparator
OCx
16
16
SCLK
DIV
Output Compare
Registers
M
U
X
RTC CLK
ECx
PWM
OC PWR Trip
PWM
Control
PWM
EOC
IC
IRQ Control
IRQ
Figure 26. Programmable Reload Timer Block Diagram
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Basic Timer Operation
Basic timer operation is controlled by a timer control register and a programmable reload
value. The CPU uses the control register to setup the prescaling, the input clock source,
the end-of-count behavior, and to start the timer. The 16-bit reload value is used to deter-
mine the duration of the timer’s count before either halting or reloading.
After choosing a timer period and writing the appropriate values to the reload registers, the
CPU must set the timer enable bit (TMRx_CTL[TIM_EN]) by allowing the count to
begin. The reload bit (TMRx_CTL[RLD]) must also be asserted so that the timer counts
down from the reload value rather than from 0000h. On the system clock cycle, after the
assertion of the reload bit, the timer loads with the 16-bit reload value and begins counting
down. The reload bit is automatically cleared after the loading operation. The timer is
enabled and reloaded on the same cycle; however, the timer does not require disabling to
reload and reloading is performed at any time. It is also possible to halt the timer by deas-
serting the timer enable bit and resuming the count at a later time from the same point by
reasserting the bit.
Reading the Current Count Value
The CPU reads the current count value when the timer is running. Because the count is a
16-bit value, the hardware latches the value of the upper byte into temporary storage when
the lower byte is read. This value in temporary storage is the value returned when the
upper byte is read. Therefore, the software must read the lower byte first. If it attempts to
read the upper byte first, it does not obtain the current upper byte of the count. Instead, it
obtains the last latched value. This read operation does not affect timer operation.
Setting Timer Duration
There are three factors to consider while determining Programmable Reload Timer dura-
tion: clock frequency, clock divider ratio, and initial count value. Minimum duration of the
timer is achieved by loading 0001h. Maximum duration is achieved by loading 0000h,
because the timer first rolls over to FFFFh and then continues counting down to 0000h
before the end-of-count is signaled. Depending on the TMRx_CTL[CLK_SEL] bits of the
control register, the clock is either the system clock, or an on-chip RC oscillator output or
an input from a pin.
The time-out period of the timer is returned by the following equation:
Clock Divider Ratio x Reload Value
Time-Out Period =
System Clock Frequency
To calculate the time-out period with the above equation while using an initial value of
0000h, enter a reload value of 65536 (FFFFh+ 1).
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Minimum time-out duration is four times longer than the input clock period and is gener-
ated by setting the clock divider ratio to 1:4 and the reload value to 0001h. Maximum
time-out duration is 224 (16,777,216) times longer than the input clock period and is gen-
erated by setting the clock divider ratio to 1:256 and the reload value to 0000h.
SINGLE PASS Mode
In SINGLE PASS Mode when the end-of-count value (0000h) is reached; counting halts,
the timer is disabled, and TMRx_CTL[TIM_EN] bit resets to 0. To reenable the timer, the
CPU must set the TIM_EN bit to 1. An example of a PRT operating in SINGLE PASS
Mode is shown in Figure 27. Timer register information is indicated in Table 50.
System Clock
Clock Enable
TMR3_CTL Write
(Timer Enable)
T3 Count
0
4
3
2
1
0
Interrupt Request
Figure 27. Example: PRT SINGLE PASS Mode Operation
Table 50. Example: PRT SINGLE PASS Mode Parameters
Parameter
Control Register(s)
Value
Timer Enable
TMRx_CTL[TIM_EN]
TMRx_CTL[RLD]
1
Reload
1
Prescaler Divider = 4
SINGLE PASS Mode
End of Count Interrupt Enable
Timer Reload Value
TMRx_CTL[CLK_DIV]
TMRx_CTL[TIM_CONT]
TMRx_IER[IRQ_EOC_EN]
{TMRx_RR_H, TMRx_RR_L}
00b
0
1
0004h
CONTINUOUS Mode
In CONTINUOUS Mode, when the end-of-count value, 0000h, is reached, the timer auto-
matically reloads the 16-bit start value from the Timer Reload registers, TMRx_RR_H and
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TMRx_RR_L. Downcounting continues on the next clock edge and the timer continues to
count until disabled. An example of the timer operating in CONTINUOUS Mode is shown
in Figure 28. Timer register information is indicated in Table 51.
System Clock
Clock Enable
TMR3_CTL Write
(Timer Enable)
T3 Count
X
4
3
2
1
4
3
2
1
Interrupt
Request
Figure 28. Example: PRT CONTINUOUS Mode Operation
Table 51. Example: PRT CONTINUOUS Mode Parameters
Parameter
Timer Enable
Control Register(s)
Value
TMRx_CTL[TIM_EN]
TMRx_CTL[RLD]
1
Reload
1
Prescaler Divider = 4
CONTINUOUS Mode
End of Count Interrupt Enable
Timer Reload Value
TMRx_CTL[CLK_DIV]
TMRx_CTL[TIM_CONT]
TMRx_IER[IRQ_EOC_EN]
{TMRx_RR_H, TMRx_RR_L}
00b
1
1
0004h
Timer Interrupts
The terminal count flag (TMRx_IIR[EOC]) is set to 1 whenever the timer reaches 0000h,
its end-of-count value in SINGLE PASS Mode, or when the timer reloads the start value
in CONTINUOUS Mode. The terminal count flag is only set when the timer reaches
0000h(or reloads) from 0001h. The timer interrupt flag is not set to 1 when the timer is
loaded with the value 0000h, which selects the maximum time-out period.
The CPU is programmed to poll the EOC bit for the time-out event. Alternatively, an inter-
rupt service request signal is sent to the CPU by setting the TMRx_IER[EOC] bit to 1.
And when the end-of-count value (0000h) is reached, the EOC bit is set to 1 and an inter-
rupt service request signal is passed to the CPU. The interrupt service request signal is
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deactivated by a CPU read of the timer interrupt identification register, TMRx_IIR. All
bits in that register are reset by the read.
The response of the CPU to this interrupt service request is a function of the CPU’s inter-
rupt enable flag, IEF1. For more information about this flag, refer to the eZ80 CPU User
Manual (UM0077) available for free download from the Zilog website.
Timer Input Source Selection
Timers 0–3 features programmable input source selection. By default, the input is taken
from the eZ80F91’s system clock. The timers also use the Real-Time Clock source (50,
60, or 32768THz) as their clock sources. The input source for these timers is set using the
timer control register. (TMRx_CTL[CLK_SEL])
Timer Output
The timer count is directed to the GPIO output pins, if required. To enable the Timer Out-
put feature, the GPIO port pin must be configured as an output and for alternate functions.
The GPIO output pin toggles each time the timer reaches its end-of-count value. In CON-
TINUOUS Mode operation, enabling the Timer Output feature results in a Timer Output
signal period which is twice the timer time-out period. Examples of Timer Output opera-
tion are shown in Figure 29 and Table 52. The initial value for the timer output is zero.
Logic to support timer output exists in all timers; but for the eZ80F91 device, only Timer
0 and 2 route the actual timer output to the pins. Because Timer 3 uses the TOUT pins for
PWMxN signals, the timer outputs are not available when using complementary PWM
outputs. See Table 52 for details.
System Clock
Clock Enable
TMR3_CTL Write
(Timer Enable)
T3 Count
0
4
3
2
1
4
3
2
1
Timer Out
(internal)
Timer Out
(at pad)
Figure 29. Example: PRT Timer Output Operation
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Table 52. Example: PRT Timer Out Parameters
Control Register(s)
Parameter
Value
Timer Enable
TMRx_CTL[TIM_EN]
TMRx_CTL[RLD]
1
Reload
1
Prescaler Divider = 4
CONTINUOUS Mode
Timer Reload Value
TMRx_CTL[CLK_DIV]
TMRx_CTL[TIM_CONT]
{TMRx_RR_H, TMRx_RR_L}
00b
1
0003h
Break Point Halting
When the eZ80F91 device is running in DEBUG Mode, encountering a break point causes
all CPU functions to halt. However, the timers keep running. This instance makes debug-
ging timer-related software much more difficult. Therefore, the control register contains a
BRK_STP bit. Setting this bit causes the count value to be held during debug break points.
Specialty Timer Modes
The features described above are common to all timers in the eZ80F91 device. In addition
to these common features, some of the timers have additional functionality.
The following bullets list the special features for each timer:
•
Timer 0
–
No special functions
•
Timer 1
–
–
One event counter (EC0)
Two input captures (IC0 and IC1)
•
•
Timer 2
–
One event counter (EC1)
Timer 3
–
–
–
Two input captures (IC2 and IC3)
Four output compares (OC0, OC1, OC2, and OC3)
Four PWM outputs (PWM0, PWM1, PWM2, and PWM3)
Timer 3 consists of three specialty modes. Each of these modes are enabled using bits in
their respective control registers (TMR3_CAP_CTL, TMR3_OC_CTL1,
TMR3_PWM_CTL1). When PWM Mode is enabled, the OUTPUT COMPARE and
INPUT CAPTURE modes are not available. This instance is due to address space sharing
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requirements. However, INPUT CAPTURE and OUTPUT COMPARE modes run simul-
taneously.
Timers with specialty modes offer multiple ways to generate an interrupt. When the inter-
rupt controller services a timer interrupt, the software must read the Timer Interrupt Iden-
tification Registers (TMRx_IIR) to determine the causes for an interrupt request. This
register is cleared each time it is read, allowing subsequent events to be identified without
interference from prior events.
Event Counter
When a timer is configured to take its input from a port input pin (ECx), it functions as an
event counter. For event counting, the clock prescaler is automatically bypassed and edges
(events) cause the timer to decrement. You must select the rising or the falling edge for
counting. Also, the port pins must be configured as inputs.
Input sampling on the port pins results in the counter being updated on the third rising
edge of the system clock after the edge event occurs at the port pin. Due to sampling, the
frequency of the event input is limited to one-half the system clock frequency under ideal
conditions. In practice, the event frequency must be less than this value due to duty cycle
variation and system clock jitter.
This EVENT COUNT Mode is identical to basic timer operation, except for the clock
source. Therefore, interrupts are managed in the same manner.
RTC Oscillator Input
When the timer clock source is the Real-Time Clock signal, the timer functions just as it
does in EVENT COUNT Mode, except that it samples the internal RTC clock rather than
the ECx pin.
Input Capture
INPUT CAPTURE Mode allows the CPU to determine the timing of specified events on a
set of external pins.
A timer intended for use in INPUT CAPTURE Mode is setup the same way as in BASIC
Mode, with one exception. The CPU must also write the TMRx_CAP_CTL Register to
select the edge on which to capture: rising, falling, or both. When one of these events
occurs on an input capture pin, the current 16 bit timer value is latched into the capture
value register pair (TMRx_CAP_A or TMRx_CAP_B depending on the IC pin exhibiting
the event).
Reading the low byte of the register pair causes the timer to ignore other capture events on
the associated external pin until the high byte is read. This instance prevents a subsequent
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capture event from overwriting the high byte between the two reads and generating an
invalid capture value. The capture value registers are read-only.
A capture flag (ICA or ICB) in the TMRx_IIR register is set whenever a capture event
occurs. Setting the interrupt identification register bit TMRx_IER[IRQ_ICx_EN] enables
the capture event to generate a timer interrupt. The port pins must be configured as alter-
nate functions, see the GPIO Mode 7: Alternate Functions section on page 49.
Output Compare
The output compare function reverses the input capture function. Rather than store a timer
value when an external event occurs, OUTPUT COMPARE Mode waits until the timer
reaches a specified value, then generates an external event. Although the same base timer
is used, up to four separate external pins are driven each with its own compare value.
To use OUTPUT COMPARE Mode, the CPU must first configure the basic timer parame-
ters. Then it must load up to four 16-bit compare values into the four TMR3_OCx Register
pairs. Next, it must load the TMR3_ OC_CTL2 Register to specify the event that occurs
on comparison. You can select the following events: SET, CLEAR, and TOGGLE.
Finally, the CPU must enable OUTPUT COMPARE Mode by asserting
TMR3_OC_CTL1[OC_EN].
The initial value for the OCx pins in OUTPUT COMPARE Mode is 0 by default. It is pos-
sible to initialize this value to 1 or force a value at a later time. Setting the
TMR3_OC_CTL2[OCx_MODE] value to 0 forces the OCx pin to the selected state pro-
vided by the TMR3_OC_CTL1[OCx_INIT] bits. Regardless of any compare events, the
pin stays at the forced value until OCx_MODE is changed. After release, it retains the
forced value until modified by an OUTPUT COMPARE event.
Asserting TMR3_OC_CTL1[MAST_MODE] selects MASTER MODE for all OUTPUT
COMPARE events and sets output 0 as the master. As a result, outputs 1, 2, and 3 are
caused to disregard output-specific configuration and comparison values and instead
mimic the current settings for output 0.
The OCx bits in the TMR3_IIR Register are set whenever the corresponding timer com-
pares occur. TMR3_IER[IRQ_OCx_EN] allows the compare event to generate a timer
interrupt.
Timer Port Pin Allocation
The eZ80F91 device timers interface to the outside world via Ports A and B. These ports
are also used for GPIO as well as other assorted functions. Table 53 lists the timer pins and
their respective functions.
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Table 53. GPIO Mode Selection Using Timer Pins
Timer Function
GPIO Port GPIO Port
PWM_CTL1
PWM_CTL1
Port
Bits
PA0
PA1
PA2
PA3
Mode
MPWM_EN = 0
MPWM_EN = 1
A
7
7
7
7
OC0
OC1
OC2
OC3
PWM0
PWM1
PWM2
PWM3
PWM_CTL1
PAIR_EN = 0
PWM_CTL1
PAIR_EN = 1
PA4
PA5
PA6
PA7
PB0
PB1
PB4
PB5
7
7
7
7
7
7
7
7
TOUT0
TOUT2
EC1
PWM0
PWM1
PWM2
PWM3
B
IC0/EC0
IC1
IC2
IC3
Timer Registers
The CPU monitors and controls the timer using seven 8-bit registers. These registers are
the control register, the interrupt identification register, the interrupt enable register and
the reload register pair (high and low byte). There are also a pair of data registers used to
read the current timer count value.
The variable x can be 0, 1, 2, or 3 to represent each of the 4 available timers.
Basic Timer Register Set
Each timer requires a different set of registers for configuration and control. However, all
timers contain the following seven registers, each of which is necessary for basic opera-
tion:
•
•
•
•
Timer Control Register (TMRx_CTL)
Interrupt Identification Register (TMRx_IIR)
Interrupt Enable Register (TMRx_IER)
Timer Data Registers (TMRx_DR_H and TMRx_DR_L)
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•
Timer Reload Registers (TMRx_RR_H and TMRx_RR_L)
The Timer Data Register is read-only when the Timer Reload Register is write-only. The
address space for these two registers is shared.
Register Set for Capture in Timer 1
In addition to the basic register set, Timer 1 uses the following five registers for its INPUT
CAPTURE Mode:
•
•
Capture Control Register (TMR1_CAP_CTL)
Capture Value Registers (TMR1_CAP_B_H, TMR1_CAP_B_L, TMR1_CAP_A_H,
TMR1_CAP_A_L)
Register Set for Capture/Compare/PWM in Timer 3
In addition to the basic register set, Timer 3 uses 19 registers for INPUT CAPTURE,
OUTPUT COMPARE, and PWM modes. PWM and capture/compare functions cannot be
used simultaneously so, their register address space is shared. INPUT CAPTURE and
OUTPUT COMPARE are used concurrently and their address space is not shared.
The INPUT CAPTURE Mode registers are equivalent to those used in Timer 1 above
(substitute TMR3 for TMR1).
OUTPUT COMPARE Mode uses the following nine registers:
•
•
Output Compare Control Registers
–
–
TMR3_OC_CTL1
TMR3_OC_CTL2
Compare Value Registers
–
–
–
–
–
–
–
–
TMR3_OC3_H
TMR3_OC3_L
TMR3_OC2_H
TMR3_OC2_L
TMR3_OC1_H
TMR3_OC1_L
TMR3_OC0_H
TMR3_OC0_L
Multiple PWM Mode uses the following 19 registers:
PWM Control Registers
TMR3_PWM_CTL1
•
–
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127
–
–
TMR3_PWM_CTL2
TMR3_PWM_CTL3
•
•
PWM Rising Edge Values
–
–
–
–
–
–
–
–
TMR3_PWM3R_H
TMR3_PWM3R_L
TMR3_PWM2R_H
TMR3_PWM2R_L
TMR3_PWM1R_H
TMRx_PWM1R_L
TMR3_PWM0R_H
TMR3_PWM0R_L
PWM Falling Edge Values
–
–
–
–
–
–
–
–
TMR3_PWM3F_H
TMRx_PWM3F_L
TMR3_PWM2F_H
TMR3_PWM2F_L
TMR3_PWM1F_H
TMR3_PWM1F_L
TMR3_PWM0F_H
TMR3_PWM0F_L
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Timer Control Register
The Timer x Control Register, shown in Table 54, is used to control timer operations
including enabling the timer, selecting the clock source, selecting the clock divider, select-
ing between CONTINUOUS and SINGLE PASS modes, and enabling the auto-reload
feature.
Table 54. Timer Control Register (TMRx_CTL)
Bit
7
BRK_STOP
0
6
5
4
3
2
TIM_CONT
0
1
0
TIM_EN
0
Field
Reset
R/W
CLK_SEL
CLK_DIV
RLD
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
TMR0_CTL = 0060h, TMR1_CTL = 0065h, TMR2_CTL = 006Fh, TMR3_CTL = 0074h
Note: R = read only; R/W = read/write.
Bit
Description
[7]
BRK_STOP
Break Point Operation
0: The timer continues to operate during debug break points.
1: The timer stops operation and holds count value during debug break points.
[6:5]
CLK_SEL
Clock Source Select
00: Timer source is the system clock divided by the prescaler.
01: Timer source is the Real Time Clock Input.
10: Timer source is the Event Count (ECx) input; falling edge. For Timer 1 this is EC0. For
Timer 2, this is EC1.
11: Timer source is the Event Count (ECx) input; rising edge. For Timer 1 this is EC0. For
Timer 2, this is EC1.
[4:3]
CLK_DIV
Clock Divider
00: System clock divider = 4.
01: System clock divider = 16.
10: System clock divider = 64.
11: System clock divider = 256.
[2]
TIM_CONT
Timer Count Mode
0: The timer operates in SINGLE PASS Mode. TIM_EN (bit 0) is reset to 0 and counting
stops when the end-of-count value is reached.
1: The timer operates in CONTINUOUS Mode. The timer reload value is written to the
counter when the end-of-count value is reached.
[1]
RLD
Timer Reload
0: Reload function is not forced.
1: Force reload. When 1 is written to this bit, the values in the reload registers are loaded
into the downcounter.
[0]
TIM_EN
Programmable Reload Timer Enable
0: The programmable reload timer is disabled.
1: The programmable reload timer is enabled.
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Timer Interrupt Enable Register
The Timer x Interrupt Enable Register, shown in Table 55, is used to control timer inter-
rupt operations. Only bits related to functions present in a given timer are active.
Table 55. Timer Interrupt Enable (TMRx_IER)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
IRQ_OCx_EN
IRQ_
IRQ_
IRQ_
ICB_EN ICA_EN EOC_EN
Reset
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
TMR0_IER = 0061h, TMR1_IER = 0066h, TMR2_IER = 0070h, TMR3_IER = 0075h
Note: R = read only; R/W = read/write.
Bit
Description
[7]
Reserved
This bit is unused and must be programmed to 0.
[6]
Interrupt Request Output Compare 3 Enable
IRQ_OC3_EN 0: Interrupt requests for OC3 are disabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
1: Interrupt requests for OC3 are enabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
[5]
Interrupt Request Output Compare 2 Enable
IRQ_OC2_EN 0: Interrupt requests for OC2 are disabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
1: Interrupt requests for OC2 are enabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
[4]
Interrupt Request Output Compare 1 Enable
IRQ_OC1_EN 0: Interrupt requests for OC1 are disabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
1: Interrupt requests for OC1 are enabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
[3]
Interrupt Request Output Compare 0 Enable
IRQ_OC0_EN 0: Interrupt requests for OC0 are disabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
1: Interrupt requests for OC0 are enabled (valid only in OUTPUT COMPARE Mode). OC
operations occur in Timer 3.
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Bit
Description (Continued)
[2]
Interrupt Request Input Capture x Enable
IRQ_ICB_EN 0: Interrupt requests for ICx are disabled (valid only in INPUT CAPTURE Mode).
Timer 1: the capture pin is IC1.
Timer 3: the capture pin is IC3.
1: Interrupt requests for ICx are enabled (valid only in INPUT CAPTURE Mode).
For Timer 1: the capture pin is IC1.
For Timer 3: the capture pin is IC3.
[1]
Interrupt Request Input Capture/PWM Enable
IRQ_ICA_EN 0: Interrupt requests for ICA or PWM power trip are disabled (valid only in INPUT CAP-
TURE and PWM modes). For Timer 1: the capture pin is IC0. For Timer 3: the capture
pin is IC2.
1: Interrupt requests for ICA or PWM power trip are enabled (valid only in INPUT CAP-
TURE and PWM modes). For Timer 1: the capture pin is IC0. For Timer 3: the capture
pin is IC2.
[0]
Interrupt Request End Of Count Enable
IRQ_EOC_EN 0: Interrupt on end-of-count is disabled.
1: Interrupt on end-of-count is enabled.
Timer Interrupt Identification Register
The TImer x Interrupt Identification Register, shown in Table 56, is used to flag timer
events so that the CPU determines the cause of a timer interrupt. This register is cleared by
a CPU read.
Table 56. Timer Interrupt Identification Register (TMRx_IIR)
Bit
7
6
5
4
3
2
1
0
Field
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only;
TMR0_IIR = 0062h, TMR1_IIR = 0067h, TMR2_IIR = 0071h, TMR3_IIR = 0076h
Bit
Description
Reserved
[7]
This bit is unused and must be programmed to 0.
[6]
OC3
Output Compare 3
0: OC3 does not occur.
1: Output compare, OC3, occurs.
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Bit
Description (Continued)
[5]
OC2
Output Compare 2
0: Output compare, OC2, does not occur.
1: Output compare, OC2, occurs.
[4]
OC1
Output Compare 1
0: Output compare, OC1, does not occur.
1: Output compare, OC1, occurs.
[3]
OC0
Output Compare 0
0: Output compare, OC0, does not occur.
1: Output compare, OC0, occurs.
[2]
ICB
Input Capture B
0: Input capture, ICB, does not occur. For Timer 1, the capture pin is IC1. For Timer 3, the
capture pin is IC3.
1: Input capture, ICB, occurs. For Timer 1, the capture pin is IC1. For Timer 3, the capture
pin is IC3.
[1]
ICA
Input Capture A
0: Input capture, ICA, or PWM power trip does not occur. For Timer 1, the capture pin is
IC0. For Timer 3, the capture pin is IC2.
1: Input capture, ICA, or PWM power trip occurs. For Timer 1, the capture pin is IC0. For
Timer 3, the capture pin is IC2.
[0]
EOC
End Of Count
0: End-of-count does not occur.
1: End-of-count occurs.
Timer Data Low Byte Register
The Timer x Data Low Byte Register returns the low byte of the current count value of the
selected timer. The Timer Data Low Byte Register, shown in Table 57, is read when the
timer is in operation. Reading the current count value does not affect timer operation. To
read the 16-bit data of the current count value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]},
first read the Timer Data Low Byte Register, followed by the Timer Data High Byte Reg-
ister. The Timer Data High Byte Register value is latched into temporary storage when a
read of the Timer Data Low Byte Register occurs.
This register shares its address with the corresponding timer reload register.
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Table 57. Timer Data Low Byte Register (TMRx_DR_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
TMRx_DR_L
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Address
TMR0_DR_L = 0063h, TMR1_DR_L = 0068h,
TMR2_DR_L = 0072h, TMR3_DR_L = 0077h
Note: R = read only.
Bit
Description
Timer Data Low Byte
[7:0]
TMRx_DR_L 00h–FFh: These bits represent the low byte of the 2-byte timer data value,
{TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. Bit 7 is bit 7 of the 16-bit timer data value. Bit 0 is
bit 0 (lsb) of the 16-bit timer data value.
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Timer Data High Byte Register
The Timer x Data High Byte Register, shown in Table 58, returns the high byte of the
count value of the selected timer as it existed at the time that the low byte was read. The
Timer Data High Byte Register is read when the timer is in operation. Reading the current
count value does not affect timer operation. To read the 16-bit data of the current count
value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}, first read the Timer Data Low Byte Reg-
ister followed by the Timer Data High Byte Register. The Timer Data High Byte Register
value is latched into temporary storage when a read of the Timer Data Low Byte Register
occurs.
This register shares its address with the corresponding timer reload register.
Table 58. Timer Data High Byte Register (TMRx_DR_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
TMRx_DR_H
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Address
TMR0_DR_H = 0064h, TMR1_DR_H = 0069h,
TMR2_DR_H = 0073h, TMR3_DR_H = 0078h
Note: R = read only.
Bit
Description
Timer Data Low Byte
00h–FFh: These bits represent the high byte of the 2-byte timer data value,
[7:0]
TMR_DR_H
{TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. Bit 7 is bit 15 (msb) of the 16-bit timer data value.
Bit 0 is bit 8 of the 16-bit timer data value.
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Timer Reload Low Byte Register
The Timer x Reload Low Byte Register, shown in Table 59, stores the least-significant
byte (LSB) of the 2-byte timer reload value. In CONTINUOUS Mode, the timer reload
value is reloaded into the timer on end-of-count. When the reload bit (TMRx_CTL[RLD])
is set to 1 forcing the reload function, the timer reload value is written to the timer on the
next rising edge of the clock.
This register shares its address with the corresponding timer data register.
Table 59. Timer Reload Low Byte Register (TMRx_RR_L)
Bit
7
6
5
4
3
2
1
0
Field
TMR_RR_L
Reset
R/W
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Address
TMR0_RR_L = 0063h, TMR1_RR_L = 0068h,
TMR2_RR_L = 0072h, TMR3_RR_L = 0077h
Note: W = write only.
Bit
Description
Timer Reload Low Byte
00h–FFh: These bits represent the low byte of the 2-byte timer reload value,
[7:0]
TMR_RR_L
{TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. Bit 7 is bit 7 of the 16-bit timer reload value. Bit 0
is bit 0 (lsb) of the 16-bit timer reload value.
Timer Reload High Byte Register
The Timer x Reload High Byte Register, shown in Table 60, stores the most-significant
byte (MSB) of the 2-byte timer reload value. In CONTINUOUS Mode, the timer reload
value is reloaded into the timer upon end-of-count. When the reload bit
(TMRx_CTL[RLD]) is set to 1, it forces the reload function, the timer reload value is writ-
ten to the timer on the next rising edge of the clock.
This register shares its address with the corresponding timer data register.
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Table 60. Timer Reload High Byte Register (TMRx_RR_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
TMR_RR_H
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Address
TMR0_RR_H = 0064h, TMR1_RR_H = 0069h,
TMR2_RR_H = 0073h, TMR3_RR_H = 0078h
Note: W = write only.
Bit
Description
Timer Reload High Byte
00h–FFh: These bits represent the high byte of the 2-byte timer reload value,
[7:0]
TMR_RR_H
{TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. Bit 7 is bit 15 (msb) of the 16-bit timer reload
value. Bit 0 is bit 8 of the 16-bit timer reload value.
Timer Input Capture Control Register
The Timer x Input Capture Control Register, shown in Table 61, is used to select the edge
or edges to be captured. For Timer 1, CAP_EDGE_B is used for IC1 and CAP_EDGE_A
is for IC0. For Timer 3, CAP_EDGE_B is for IC3, and CAP_EDGE_A is for IC2.
Table 61. Timer Input Capture Control Register (TMR1_CAP_CTL, TMR3_CAP_CTL)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
Reserved
CAP_EDGE_B
CAP_EDGE_A
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
TMR1_CAP_CTL = 006Ah, TMR3_CAP_CTL = 007Bh
Note: R = read only; R/W = read/write.
Bit
Description
[7:4]
Reserved
These bits are reserved and must be programmed to 0000.
[3:2]
Capture Edge Enable B
CAP_EDGE_B 00: Disable capture on ICB.
01: Enable capture only on the falling edge of ICB.
10: Enable capture only on the rising edge of ICB.
11: Enable capture on both edges of ICB.
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Bit
Description (Continued)
Capture Edge Enable A
[1:0]
CAP_EDGE_A 00: Disable capture on ICA.
01: Enable capture only on the falling edge of ICA
10: Enable capture only on the rising edge of ICA.
11: Enable capture on both edges of ICA.
Timer Input Capture Value A Low Byte Register
The Timer x Input Capture Value A Low Byte Register, shown in Table 62, stores the low
byte of the capture value for external input A. For Timer 1, the external input is IC0. For
Timer 3, it is IC2.
Table 62. Timer Input Capture Value Low Byte Register A (TMR1_CAPA_L, TMR3_CAPA_L)
Bit
7
6
5
4
3
2
1
0
Field
TMRx_CAPA_L
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
TMR1_CAPA_L = 006Bh, TMR3_CAPA_L = 007Ch
Bit
Description
[7:0]
Timer Input Capture A Low Byte
TMRx_CAPA_L 00h–FFh: These bits represent the low byte of the 2-byte capture value,
{TMRx_CAPA_H[7:0], TMRx_CAPA_L[7:0]}. Bit 7 is bit 7 of the 16-bit data value. Bit 0
is bit 0 (lsb) of the 16-bit timer data value.
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Timer Input Capture Value A High Byte Register
The Timer x Input Capture Value A High Byte Register, shown in Table 63, stores the high
byte of the capture value for external input A. For Timer 1, the external input is IC0. For
Timer 3, it is IC2.
Table 63. Timer Input Capture Value High Byte Register A (TMR1_CAPA_H, TMR3_CAPA_H)
Bit
7
6
5
4
3
2
1
0
Field
TMRx_CAPA_H
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
TMR1_CAPA_H = 006Ch, TMR3_CAPA_H = 007Dh
Bit
Description
[7:0]
Timer Input Capture A High Byte
TMRx_CAPA_H 00h–FFh: These bits represent the high byte of the 2-byte capture value,
{TMRx_CAPA_H[7:0], TMRx_CAPA_L[7:0]}. Bit 7 is bit 15 (msb) of the 16-bit data
value. Bit 0 is bit 8 of the 16-bit timer data value.
Timer Input Capture Value B Low Byte Register
The Timer x Input Capture Value B Low Byte Register, shown in Table 64, stores the low
byte of the capture value for external input B. For Timer 1, the external input is IC1. For
Timer 3, it is IC3.
Table 64. Timer Input Capture Value Low Byte Register B (TMR1_CAPB_L, TMR3_CAPB_L)
Bit
7
6
5
4
3
2
1
0
Field
TMRx_CAPB_L
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
TMR1_CAPB_L = 006Dh, TMR3_CAPB_L = 007Eh
Bit
Description
[7:0]
Timer Input Capture B Low Byte
TMRx_CAPB_L 00h–FFh: These bits represent the low byte of the 2-byte capture value,
{TMRx_CAPB_H[7:0], TMRx_CAPB_L[7:0]}. Bit 7 is bit 7 of the 16-bit data value. Bit 0
is bit 0 (lsb) of the 16-bit timer data value.
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Timer Input Capture Value B High Byte Register
The Timer x Input Capture Value B High Byte Register, shown in Table 65, stores the high
byte of the capture value for external input B. For Timer 1, the external input is IC0. For
Timer 3, it is IC3.
Table 65. Timer Input Capture Value High Byte Register B (TMR1_CAPB_H, TMR3_CAPB_H)
Bit
7
6
5
4
3
2
1
0
Field
TMRx_CAPB_H
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
TMR1_CAPB_H = 006Eh, TMR3_CAPB_H = 007Fh
Bit
Description
[7:0]
Timer Input Capture B High Byte
TMRx_CAPB_H 00h–FFh: These bits represent the high byte of the 2-byte capture value,
{TMRx_CAPB_H[7:0], TMRx_CAPB_L[7:0]}. Bit 7 is bit 15 (msb) of the 16-bit data
value. Bit 0 is bit 8 of the 16-bit timer data value.
Timer Output Compare Control Register 1
The Timer3 Output Compare Control Register 1, shown in Table 66, is used to select the
Master Mode and to provide initial values for the OC pins.
Table 66. Timer Output Compare Control Register 1 (TMR3_OC_CTL1)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
Reserved
OCx_INIT
MAST_MODE OC_EN
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
0080h
Note: R = read only; R/W = read/write.
Bit
Description
Reserved
[7:6]
These bits are unused and must be programmed to 00.
[5]
OC3_INIT
Output Compare 3 Initialize
0: OC pin cleared when initialized.
1: OC pin set when initialized.
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Bit
Description (Continued)
[4]
OC2_INIT
Output Compare 2 Initialize
0: OC pin cleared when initialized.
1: OC pin set when initialized.
[3]
OC1_INIT
Output Compare 1 Initialize
0: OC pin cleared when initialized.
1: OC pin set when initialized.
[2]
OC0_INIT
Output Compare 0 Initialize
0: OC pin cleared when initialized.
1: OC pin set when initialized.
[1]
Master Mode Select
MAST_MODE 0: OC pins are independent.
1: OC pins all mimic OC0.
[0]
OC_EN
Output Compare Mode Enable
0: OUTPUT COMPARE Mode is disabled.
1: OUTPUT COMPARE Mode is enabled.
Timer Output Compare Control Register 2
The Timer3 Output Compare Control Register 2, shown in Table 67, is used to select the
event that occurs on the output compare pins when a timer compare happens.
Table 67. Timer Output Compare Control Register 2 (TMR3_OC_CTL2)
Bit
7
6
5
4
3
2
1
0
Field
OC3_MODE
OC2_MODE
OC1_MODE
OC0_MODE
Reset
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
0081h
Note: R/W = read/write.
Bit
Description
Output Compare 3 Mode
[7:6]
OC3_MODE
00: Initialize OC pin to value specified in TMR3_OC_CTL1[OC3_INT].
01: OC pin is cleared upon timer compare.
10: OC pin is set upon timer compare.
11: OC pin toggles upon timer compare.
[5:4]
OC2_MODE
Output Compare 2 Mode
00: Initialize OC pin to value specified in TMR3_OC_CTL1[OC2_INT].
01: OC pin is cleared upon timer compare.
10: OC pin is set upon timer compare.
11: OC pin toggles upon timer compare.
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Bit
Description (Continued)
Output Compare 1 Mode
[3:2]
OC1_MODE
00: Initialize OC pin to value specified in TMR3_OC_CTL1[OC1_INT].
01: OC pin is cleared upon timer compare.
10: OC pin is set upon timer compare.
11: OC pin toggles upon timer compare.
[1:0]
OC0_MODE
Output Compare 0 Mode
00: Initialize OC pin to value specified in TMR3_OC_CTL1[OC0_INT].
01: OC pin is cleared upon timer compare.
10: OC pin is set upon timer compare.
11: OC pin toggles upon timer compare.
Timer Output Compare Value Low Byte Register
The Timer3 Output Compare x Value Low Byte Register, shown in Table 68, stores the
low byte of the compare value for OC0–OC3.
Table 68. Compare Value Low Byte Register (TMR3_OCx_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
TMR3_OC0_L = 0082h, TMR3_OC1_L = 0084h,
TMR3_OC2_L = 0086h, TMR3_OC3_L = 0088h
Note: R/W = read/write.
Bit
Description
Timer 3 Output Compare Low Byte
[7:0]
TMR3_OCx_L 00h–FFh: These bits represent the low byte of the 2-byte compare value,
{TMR3_OCx_H[7:0], TMR3_OCx_L[7:0]}. Bit 7 is bit 7 of the 16-bit data value. Bit 0 is bit
0 (lsb) of the 16-bit timer compare value.
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Timer Output Compare Value High Byte Register
The Timer3 Output Compare x Value High Byte Register, shown in Table 69, stores the
high byte of the compare value for OC0–OC3.
Table 69. Compare Value High Byte Register (TMR3_OCx_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
TMR3_OCx_H
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
TMR3_OC0_H = 0083h, TMR3_OC1_H = 0085h, TMR3_OC2_H = 0087h,
TMR3_OC3_H = 0089h
Note: R/W = read/write.
Bit
Description
[7:0]
TMR3_OCx_H
Timer 3 Output Compare High Byte
00h–FFh: These bits represent the high byte of the 2-byte compare value,
{TMR3_OCx_H[7:0], TMR3_OCx_L[7:0]}. Bit 7 is bit 15 (msb) of the 16-bit data value.
Bit 0 is bit 8
of the 16-bit timer compare value.
Multi-PWM Mode
The special Multi-PWM Mode uses the Timer 3 16-bit counter as the primary timekeeper
to control up to 4 PWM generators. The 16-bit reload value for Timer 3 sets a common
period for each of the PWM signals. However, the duty cycle and phase for each generator
are independent that is, the High and Low periods for each PWM generator are set inde-
pendently. In addition, each of the 4 PWM generators are enabled independently. The 8
PWM signals (4 PWM output signals and their inverse signals) are output via Port A. A
functional block diagram of the Multi-PWM is shown in Figure 30.
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16
PA0
PA4
PWM0 Output
PWM0 Output
PWM0
Generator
16
Timer 3
16-Bit Binary
Downcounter
PA1
PA5
PWM1 Output
PWM1 Output
PWM1
Generator
16
Timer 3
Clock Input
Count Value
16
PA2
PA6
PWM2 Output
PWM2 Output
PWM2
Generator
16
PA3
PA7
PWM3 Output
PWM3 Output
PWM3
Generator
Figure 30. Multi-PWM Simplified Block Diagram
Setting TMR3_PWM_CTL1[MPWM_EN] to 1 enables Multi-PWM Mode. The
TMR3_PWM_CTL1 Register bits enable the 4 individual PWM generators by adjusting
settings according to the list provided in Table 70.
Table 70. Enabling PWM Generators
Enable PWM generator 0 by setting TMR3_PWM_CTL1[PWM0_EN] to 1.
Enable PWM generator 1 by setting TMR3_PWM_CTL1[PWM1_EN] to 1.
Enable PWM generator 2 by setting TMR3_PWM_CTL1[PWM2_EN] to 1.
Enable PWM generator 3 by setting TMR3_PWM_CTL1[PWM3_EN] to 1.
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The inverted PWM outputs PWM0, PWM1, PWM2, and PWM3 are globally enabled by
setting TMR3_PWM_CTL1[PAIR_EN] to 1. The individual PWM generators must be
enabled for the associated inverted PWM signals to be output.
For each of the 4 PWM generators, there is a 16-bit rising edge value
{TMR3_PWMxR_H[PWMxR_H], TMR3_PWMxR_L[PWMxR_L]} and a 16-bit falling
edge value {TMR3_PWMxF_H[PWMxF_H], TMR3_PWMxF_L[PWMxF_L]} for a total
of 16 registers. The rising-edge byte pairs define the timer count at which the PWMx
output transitions from Low to High. Conversely, the falling-edge byte pairs define the
timer count at which the PWMx output transitions from High to Low. On reset, all enabled
PWM outputs begin Low and all PWMx outputs begin High. When the PWMx output is
Low, the logic is looking for a match between the timer count and the rising edge value,
and vice versa. Therefore, in a case in which the rising edge value is the same as the falling
edge value, the PWM output frequency is one-half the rate at which the counter passes
through its entire count cycle (from reload value down to 0000h).
Figures 31 and 32demonstrate a simple Multi-PWM output and an expanded view of the
timing, respectively. Associated control values are listed in Table 71.
T3 Count
PWM0
C
B A 9 8 7 6 5 4 3 2 1 C B A 9 8 7 6 5 4 3 2 1 C B A 9 8 7 6 5 4 3 2 1 C B A
0
PWM0
PWM1
PWM1
Figure 31. Multi-PWM Operation
System Clock
Clock Enable
T3 Count
A
9
8
7
6
5
4
Figure 32. Multi-PWM Operation: Expanded View of Timing
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Table 71. Example: Multi-PWM Addressing
Parameter
Control Register(s)
Value
Timer Reload Value
PWM0 rising edge
PWM0 falling edge
PWM1 rising edge
PWM1 falling edge
PWM enable
{TMR3_RR_H, TMR3_RR_L}
000Ch
{TMR3_PWM0R_H, TMR3_PWM0R_L}
{TMR3_PWM0F_H, TMR3_PWM0F_L}
{TMR3_PWM1R_H, TMR3_PWM1R_L}
{TMR3_PWM1F_H, TMR3_PWM1F_L}
TMR3_PWM_CTL1[PAIR_EN]
0008h
0004h
0006h
0007h
1
PWM0 enable
TMR3_PWM_CTL1[PWM0_EN]
TMR3_PWM_CTL1[PWM1_EN]
TMR3_PWM_CTL1[MPWM_EN]
TMR3_CTL[CLK_DIV]
1
PWM1 enable
1
Multi-PWM enable
Prescaler Divider = 4
PWM nonoverlapping delay = 0
1
00b
0000b
TMR3_PWM_CTL2[PWM_DLY]
PWM Master Mode
In PWM Master Mode, the pair of output signals generated from the PWM0 generator
(PWM0 and PWM0) are directed to all four sets of PWM output pairs. Setting
TMR3_PWM_CTL1[MM_EN] to 1 enables PWM Master Mode. Assuming the outputs
are all enabled and no AND/OR gating is used, all four PWM output pairs transition
simultaneously under the direction of PWM0 and PWM0. In PWM Master Mode, the out-
puts still be gated individually using the AND/OR gating functions described in the next
section. Multi-PWM Mode and the individual PWM outputs must be enabled along with
PWM Master Mode. It is possible to enable or disable any combination of the 4 PWM out-
puts while running in PWM Master Mode.
Modification of Edge Transition Values
Special circuitry is included for the update of the PWM edge transition values. Normal use
requires that these values be updated while the PWM generator is running.
Note: Under certain circumstances, electric motors driven by the PWM logic encounters rough
operation. In other words, cycles could be skipped if the PWM waveform edge is not care-
fully modified.
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Without special consideration, if a PWM generator looks for a particular count to make a
state transition and if the edge transition value changes to a value that already occurred in
the current counter count-down cycle, then the transition is missed. The PWM generator
holds the current output state until the counter reloads and cycles through to the appropri-
ate edge transition value again. In effect, an entire cycle of the PWM waveform is skipped
with the signal held at a DC value. The change in PWM waveform duty cycle from cycle
to cycle must be limited to some fraction of a period to avoid rough running. To avoid
unintentional roughness due to timing of the load operation for the register values in ques-
tion, the PWM edge transition values are double-buffered and exhibit the following behav-
ior:
•
•
When the PWM generators are disabled, PWM edge transition values written by the
CPU are immediately loaded into the PWM edge transition registers.
When the PWM generators are enabled, a PWM edge transition value is loaded into a
buffer register and transferred to its destination register only during a specific transition
event. A rising edge transition value is only loaded upon a falling edge transition event,
and a falling edge transition value is only loaded upon a rising edge transition event.
AND/OR Gating of the PWM Outputs
When in Multi-PWM Mode, it is possible for you to turn off PWM propagation to the pins
without disabling the PWM generator. This feature is global and applies to all enabled
PWM generators. The function is implemented by applying digital logic (AND or OR
functions) to combine the corresponding bits in the port output register with the PWM and
PWM outputs.
The AND or OR functions are enabled on all PWM outputs by setting
TMR3_PWM_CTL2[AO_EN] to either a 01b (AND) or 10b (OR). Any other value dis-
ables this feature. Likewise, the AND or OR functions are enabled on all PWM outputs by
setting TMR3_PWM_CTL2[AON_EN] to either a 01b (AND) or 10b (OR). Any other
value disables this feature. A functional block diagram for the AND/OR gating feature for
PWM0 and PWM0 is shown in Figure 33. The functionality for the other three PWM pairs
are identical.
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00
01
10
11
PA0
PWM0 Output
PWM0 Signal
PADR0
2
TMR3_PWM_CTL2[5:4]
00
01
10
PWM0 Output
PWM0 Signal
PADR4
PA4
11
2
TMR3_PWM_CTL2[7:6]
Figure 33. PWM AND/OR Gating Functional Diagram
If you enable the OR function on all PWM outputs and PADR0 is set to 1, then the PWM0
output on PA0 is forced High. Similarly, if you select the AND function on all PWM
outputs and PADR0 is set to a 0, then the PWM0 output on PA0 is forced Low.
PWM Nonoverlapping Output Pair Delays
A delay is added between the falling edge of the PWM (PWM) outputs and the rising edge
of the PWM (PWM) outputs. This delay is set to assure that even with load and output
drive variations there will be no overlap between the falling edge of a PWM (PWM) out-
put and the rising edge of its paired output. The selected delay is global to all four PWM
pairs. The delay duration is software-selectable using the 4-bit field,
TMR3_PWM_CTL2[PWM_DLY]. The duration is programmable in units of the system
clock (SCLK), from 0 SCLK periods to 15 SCLK periods. The
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TMR3_PWM_CTL2[PWM_DLY] bits are mapped directly to a counter, such that a
setting of 0000b represents a delay of 0 system clock periods and a setting of 1111b rep-
resents a delay of 15 system clock periods. The PWM delay feature is shown in Figure 34
with associated addressing listed in Table 72.
Note: The PWM nonoverlapping delay time must always be defined to be less than the delay
between the rising and falling edges (and the delay between the falling and rising edges) of
all Multi-PWM outputs. In other words, a rising (falling) edge cannot be delayed beyond
the time at which it is subsequently scheduled to fall (rise).
System Clock
Clock Enable
A
9
8
7
6
5
4
3
2
1
C
TMR3_Count
PWM0
PWM0
3 x SCLK
3 x SCLK
Figure 34. PWM Nonoverlapping Output Delay
Table 72. PWM Nonoverlapping Output Addressing
Control Register(s)
Parameter
Value
00b
Timer clock is SCLK ÷ 4
Timer reload value
TMR3_CTL[CLK_DIV]
{TMR3_RR_H, TMR3_RR_L}
{TMR3_PWM0R_H, TMR3_PWM0R_L}
{TMR3_PWM0F_H, TMR3_PWM0F_L}
TMR3_CTL[CLK_DIV]
000Ch
0008h
0004h
00b
PWM0 rising edge
PWM0 falling edge
Prescaler divider = 4
PWM nonoverlapping delay = 3
PWM enable
TMR3_PWM_CTL2[PWM_DLY]
TMR3_PWM_CTL1[PAIR_EN]
0011b
1
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Table 72. PWM Nonoverlapping Output Addressing (Continued)
Parameter
Control Register(s)
Value
PWM0 enable
Multi-PWM enable
TMR3_PWM_CTL1[PWM0_EN]
TMR3_PWM_CTL1[MPWN_EN]
1
1
Multi-PWM Power-Trip Mode
When enabled, the Multi-PWM power-trip feature forces the enabled PWM outputs to a
predetermined state when an interrupt is generated from an external source via IC0, IC1,
IC2, or IC3. One or multiple external interrupt sources are enabled at any given time. If
multiple sources are enabled, any of the selected external sources trigger an interrupt.
Configuring the PWM_CTL3 Register enables or disables interrupt sources. See Table 75
on page 152.
The possible interrupt sources for a Multi-PWM power-trip are:
•
•
•
•
IC0: digital input
IC1: digital input
IC2: digital input
IC3: digital input
When the power-trip is detected, TMR3_PWM_CTL3[PTD] is set to 1 to indicate detec-
tion of the power-trip. A value of 0 signifies that no power-trip is detected.
The PWMs are released only after a power-trip when TMR3_PWM_CTL3[PTD] is writ-
ten back to 0 by software. As a result, you are allowed to check the conditions of the motor
being controlled before releasing the PWMs. The explicit release also prevents noise
glitches after a power-trip from causing an accidental exit or reentry of the PWM power-
trip state.
The programmable power-trip states of the PWMs are globally grouped for the PWM out-
puts and the inverting PWM outputs. Upon detection of a power-trip, the PWM outputs
are forced to either a High state, a Low state, or high-impedance. The settings for the
power-trip states are made with power-trip control bits TMR3_PWM_CTL3[PT_LVL],
TMR3_PWM_CTL3[PT_LVL_N], and TMR3_PWM_CTL3[PT_TRI].
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Multi-PWM Control Registers
This section describes the following PWM control registers:
Pulse-Width Modulation Control Register 1 – see page 149
Pulse-Width Modulation Control Register 2 – see page 150
Pulse-Width Modulation Control Register 3 – see page 152
Pulse-Width Modulation Rising Edge Low Byte Register – see page 153
Pulse-Width Modulation Rising Edge High Byte Register – see page 153
Pulse-Width Modulation Falling Edge Low Byte Register – see page 154
Pulse-Width Modulation Falling Edge High Byte Register – see page 154
Pulse-Width Modulation Control Register 1
The PWM Control Register 1 (see Table 73) controls the enabling of PWM functions.
Table 73. PWM Control Register 1 (PWM_CTL1)
Bit
7
6
5
MM_EN
0
4
3
2
1
0
MPWM_EN
0
Field
Reset
R/W
PAIR_EN PT_EN
PWMx_EN
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
0079h
Note: R/W = read/write.
Bit
Description
PWM Output Pair Enable
[7]
PAIR_EN
0: Global disable of the PWM outputs (PWM outputs enabled only).
1: Global enable of the PWM and PWM output pairs.
[6]
PT_EN
PWM Power Trip Enable
0: Disable power-trip feature.
1: Enable power-trip feature.
[5]
MM_EN
PWM Master Mode Enable
0: Disable Master Mode.
1: Enable Master Mode.
[4:1]
PWM Generator x Enable
PWMx_EN 0: Disable PWM generator 3, 2, 1, 0.
1: Enable PWM generator 3, 2, 1, 0.
Note: x indicates bits in the range [3:0].
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Bit
Description (Continued)
Multi-PWM Mode Enable
[0]
MPWM_EN 0: Disable Multi-PWM Mode.
1: Enable Multi-PWM Mode.
Note: x indicates bits in the range [3:0].
Pulse-Width Modulation Control Register 2
The PWM Control Register 2, shown in Table 74, controls pulse-width modulation AND/
OR and edge delay functions.
Table 74. PWM Control Register 2 (PWM_CTL2)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
AON_EN
AO_EN
PWM_DLY
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
007Ah
Note: R/W = read/write.
Bit
Description
AND/OR Enable, Logic Low
[7:6]
AON_EN
00: Disable AND/OR features on PWM.
01: Enable AND logic on PWM.
10: Enable OR logic on PWM.
11: Disable AND/OR features on PWM.
[5:4]
AND/OR Enable
AO_EN
00: Disable AND/OR features on PWM.
01: Enable AND logic on PWM.
10: Enable OR logic on PWM.
11: Disable AND/OR features on PWM.
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Bit
Description (Continued)
PWM Delay
[3:0]
PWM_DLY
0000: No delay between falling edge of PWM (PWM) and rising edge of PWM (PWM)
0001: Delay of 1 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
0010: Delay of 2 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
0011: Delay of 3 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
0100: Delay of 4 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
0101: Delay of 5 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
0110: Delay of 6 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
0111: Delay of 7 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
1000: Delay of 8 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
1001: Delay of 9 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
1010: Delay of 10 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
1011: Delay of 11 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
1100: Delay of 12 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
1101: Delay of 13 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
1110: Delay of 14 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
1111: Delay of 15 SCLK periods between falling edge of PWM (PWM) and rising edge of
PWM (PWM)
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Pulse-Width Modulation Control Register 3
The PWM Control Register 3 (see Table 75) is used to configure the PWM power trip
functionality.
Table 75. PWM Control Register 3 (PWM_CTL3)
Bit
7
6
5
4
3
PT_TRI
0
2
1
0
PTD
0
Field
Reset
R/W
PT_ICx_EN
PT_LVL PT_LVL_N
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Address
007Bh
Note: x indicates bits in the range [3:0]; R/W = read/write; R = read only.
Bit
Description
[7]
PT_IC3_EN
IC3 Power Trip Enable
0: Power trip disabled on IC3.
1: Power trip enabled on IC3.
[6]
PT_IC2_EN
IC2 Power Trip Enable
0: Power trip disabled on IC2.
1: Power trip enabled on IC2.
[5]
PT_IC1_EN
IC1 Power Trip Enable
0: Power trip disabled on IC1.
1: Power trip enabled on IC1.
[4]
PT_IC0_EN
IC0 Power Trip Enable
0: Power trip disabled on IC0.
1: Power trip enabled on IC0.
[3]
PWM Trip Level
PT_TRI
0: All PWM trip levels are open-drain
1: All PWM trip levels are defined by PT_LVL and PT_LVL_N
[2]
PT_LVL
PWMx Level Output
0: After power trip, PWMx outputs are set to one.
1: After power trip, PWMx outputs are set to zero.
[1]
PT_LVL_N
PWMx Level Output, Logic Low
0: After power trip, PWMx outputs are set to one.
1: After power trip, PWMx outputs are set to zero.
[0]
PTD
Power Trip Event
0: Power trip has been cleared.
1: This bit is set after power trip event.
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Pulse-Width Modulation Rising Edge Low Byte Register
A parallel 16-bit write of {TMR3_PWMxR_H[7–0], TMR3_PWMxR_L[7–0]} occurs
when software initiates a write to TMR3_PWMxR_L. See Table 76.
Table 76. PWMx Rising-Edge Low Byte Register (TMR3_PWMxR_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
PWMxR_L
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
TMR3_PWM0R_L = 007Ch, TMR3_PWM1R_L = 007Eh,
TMR3_PWM2R_L = 0080h, TMR3_PWM3R_L = 0082h
Note: R/W = read/write; x indicates bits in the range [7:0].
Bit
Description
[7:0]
PWMxR_L
PWM Rising Edge Low Byte
00h–FFh: These bits represent the low byte of the 16-bit value to set the rising edge
COMPARE value for PWMx, {TMR3_PWMxR_H[7:0], TMR3_PWMxR_L[7:0]}. Bit 7 is bit
7 of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the 16-bit timer data value.
Pulse-Width Modulation Rising Edge High Byte Register
Writing to TMR3_PWMxR_H stores the value in a temporary holding register. A parallel
16-bit write of {TMR3_PWMxR_H[7–0], TMR3_PWMxR_L[7–0]} occurs when soft-
ware initiates a write to TMR3_PWMxR_L. See Table 77.
Table 77. PWMx Rising-Edge High Byte Register (TMR3_PWMxR_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
PWMxR_H
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
TMR3_PWM0R_H = 007Dh, TMR3_PWM1R_H = 007Fh,
TMR3_PWM2R_H = 0081h, TMR3_PWM3R_H = 0083h
Note: R/W = read/write; x indicates bits in the range [7:0].
Bit
Description
[7:0]
PWMxR_H
PWM Rising Edge High Byte
00h–FFh: These bits represent the high byte of the 16-bit value to set the rising edge
COMPARE value for PWMx, {TMR3_PWMxR_H[7:0], TMR3_PWMxR_L[7:0]}. Bit 7 is bit
15 (msb) of the 16-bit timer data value. Bit 0 is bit 8 of the 16-bit timer data value.
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Pulse-Width Modulation Falling Edge Low Byte Register
A parallel 16-bit write of {TMR3_PWMxF_H[7–0], TMR3_PWMxF_L[7–0]} occurs
when software initiates a write to TMR3_PWMxF_L. See Table 78.
Table 78. PWMx Falling-Edge Low Byte Register (TMR3_PWMxF_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
PWMxF_L
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
TMR3_PWM0F_L = 0084h, TMR3_PWM1F_L = 0086h,
TMR3_PWM2F_L = 0088h, TMR3_PWM3F_L = 008Ah
Note: R/W = read/write; x indicates bits in the range [7:0].
Bit
Description
[7:0]
PWMxF_L
PWM Falling Edge Low Byte
00h–FFh: These bits represent the low byte of the 16-bit value to set the falling edge
COMPARE value for PWMx, {TMR3_PWMxF_H[7:0], TMR3_PWMxF_L[7:0]}. Bit 7 is bit
7 of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the 16-bit timer data value.
Pulse-Width Modulation Falling Edge High Byte Register
Writing to TMR3_PWMxF_H stores the value in a temporary holding register. A parallel
16-bit write of {TMR3_PWMxF_H[7–0], TMR3_PWMxF_L[7–0]} occurs when soft-
ware initiates a write to TMR3_PWMxF_L. See Table 79.
Table 79. PWMx Falling-Edge High Byte Register (TMR3_PWMxF_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
PWMxF_H
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
TMR3_PWM0F_H = 0085h, TMR3_PWM1F_H = 0087h,
TMR3_PWM2F_H = 0089h, TMR3_PWM3F_H = 008Bh
Note: R/W = read/write; x indicates bits in the range [7:0].
Bit
Description
[7:0]
PWMxF_H
PWM Falling Edge High Byte
00h–FFh: These bits represent the high byte of the 16-bit value to set the falling edge
COMPARE value for PWMx, {TMR3_PWMxF_H[7:0], TMR3_PWMxF_L[7:0]}. Bit 7 is bit
15 (msb) of the 16-bit timer data value. Bit 0 is bit 8 of the 16-bit timer data value.
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Real-Time Clock
The Real-Time Clock (RTC) maintains time by keeping count of seconds, minutes, hours, day-
of-the-week, day-of-the-month, year, and century. The current time is kept in 24-hour format.
The format for all count and alarm registers is selectable between binary and binary-coded
decimal (BCD) operations. The calendar operation maintains the correct day-of-the-month
and automatically compensates for leap year. A simplified block diagram of the RTC and the
associated on-chip, low-power 32 kHz oscillator is shown in Figure 35, which also shows con-
nections to an external battery supply and a 32kHz crystal network.
If you are not using the Real Time Clock, the following RTC signal pins must be con-
nected as shown in Figure 35 to avoid a 10µA leakage within the RTC circuit block.
RTC_XIN (pin 61) must remain floating or connected to ground.
Note:
RTC_VDD
Battery
VDD
IRQ
Real-Time Clock
ADDR[15:0]
DATA[7:0]
RTC Clock
R1
RTC_XOUT
C
System Clock
Low-Power
32 KHz Oscillator
VDD
32 KHz
Crystal
Enable
CLK_SEL
(RTC_CTRL[4])
RTC_XIN
C
Figure 35. Real-Time Clock and 32kHz Oscillator Block Diagram
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Real-Time Clock Alarm
The clock is programmed to generate an alarm condition when the current count matches
the alarm set-point registers. Alarm registers are available for seconds, minutes, hours, and
day-of-the-week. Each alarm is independently enabled. To generate an alarm condition,
the current time must match all enabled alarm values. For example, if the day-of-the-week
and hour alarms are both enabled, the alarm only occurs at a specified hour on a specified
day. The alarm triggers an interrupt if the interrupt enable bit, INT_EN, is set to 1. The
alarm flag, ALARM, and corresponding interrupts to the CPU are cleared by reading the
RTC_CTRL Register.
Alarm value registers and alarm control registers are written at any time. Alarm conditions
are generated when the count value matches the alarm value. The comparison of alarm and
count values occurs whenever the RTC count increments (one time every second). The
RTC is also forced to perform a comparison at any time by writing a 0 to the
RTC_UNLOCK bit (the RTC_UNLOCK bit is not required to be changed to a 1 first).
Real-Time Clock Oscillator and Source Selection
The RTC count is driven by either the on-chip 32kHz RTC oscillator or an external 50/
60 Hz CMOS-level clock signal (typically derived from the AC power line frequency).
The on-chip oscillator requires an external 32 kHz crystal connected to RTC_XIN and
RTC_XOUT as shown in Figure 35. If an external 50/60 Hz clock signal is used, connect it
to RTC_XOUT.
The clock source and power-line frequencies are selected in the RTC_CTRL Register.
Writing to the RTC_CTRL Register resets the clock divider.
Real-Time Clock Battery Backup
The power supply pin (RTC_VDD) for the RTC and associated low-power 32kHz oscilla-
tor is isolated from the other power supply pins on the eZ80F91 device. To ensure that the
RTC continues to keep time in the event of loss of line power to the application, a battery
is used to supply power to the RTC and the oscillator via the RTC_VDD pin. All VSS
(ground) pins must be connected together on the printed circuit assembly.
Real-Time Clock Recommended Operation
Following a initial system reset from a power-down condition of VDD and VDD_RTC, the
counter values of the RTC are undefined and all alarms are disabled. The following proce-
dure is recommended to initialize the Real-Time Clock:
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•
Write to RTC_CTRL to set RTC_UNLOCK and disable the RTC counter; this action
also clears the clock divider
•
•
•
Write values to the RTC count registers to set the current time
Write values to the RTC alarm registers to set the appropriate alarm conditions
Write to RTC_CTRL to clear RTC_UNLOCK; clearing the RTC_UNLOCK bit resets
and enables the clock divider
Real-Time Clock Registers
The RTC registers are accessed via the address and data buses using I/O instructions. The
RTC_UNLOCK control bit controls access to the RTC count registers. When unlocked
(RTC_UNLOCK = 1), the RTC count is disabled and the count registers are read/write.
When locked (RTC_UNLOCK = 0), the RTC count is enabled and the count registers are
read-only. The default at RESET is for the RTC to be locked.
Real-Time Clock Seconds Register
This register contains the current seconds count. The value in the RTC_SEC Register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values in this
register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). Access to this reg-
ister is read-only if the RTC is locked, and read/write if the RTC is unlocked. See Table 80.
Table 80. Real-Time Clock Seconds Register (RTC_SEC)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
TEN_SEC
SEC
U
U
U
U
U
U
U
U
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
00E0h
Note: U = Unchanged by RESET; R/W* = read only if RTC locked, read/write if RTC unlocked.
Binary-Coded Decimal Operation (BCD_EN = 1)
Bit
Description
[7:4]
TEN_SEC
Seconds: Tens
0–5: The tens digit of the current seconds count.
[3:0]
SEC
Seconds: Ones
0–9: The ones digit of the current seconds count.
Binary Operation (BCD_EN = 0)
[7:0]
SEC
Seconds
00h–3Bh: The current seconds count.
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Product Specification
158
Real-Time Clock Minutes Register
This register contains the current minutes count. The value in the RTC_MIN Register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values in
this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). Access to
this register is read-only if the RTC is locked, and read/write if the RTC is unlocked. See
Table 81.
Table 81. Real-Time Clock Minutes Register (RTC_MIN)
Bit
7
6
5
4
3
2
1
0
Field
TEN_MIN
MIN
Reset
R/W
U
U
U
U
U
U
U
U
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
00E1h
Note: U = unchanged by RESET; R/W* = read only if RTC locked, read/write if RTC unlocked.
Binary-Coded Decimal Operation (BCD_EN = 1)
Bit
Description
[7:4]
TEN_MIN
Minutes: Tens
0–5: The tens digit of the current minutes count.
[3:0]
MIN
Minutes: Ones
0–9: The ones digit of the current minutes count.
Binary Operation (BCD_EN = 0)
Bit
Description
[7:0]
MIN
Minutes
00h–3Bh: The current minutes count.
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Product Specification
159
Real-Time Clock Hours Register
This register contains the current hours count. The value in the RTC_HRS Register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values in
this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). Access to
this register is read-only if the RTC is locked, and read/write if the RTC is unlocked. See
Table 82.
Table 82. Real-Time Clock Hours Register (RTC_HRS)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
TEN_HRS
HRS
U
U
U
U
U
U
U
U
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
00E2h
Note: U = unchanged by RESET; R/W* = read only if RTC locked, read/write if RTC unlocked.
Binary-Coded Decimal Operation (BCD_EN = 1)
Bit
Description
[7:4]
TEN_HRS
Hours: Tens
0–2: The tens digit of the current hours count.
[3:0]
HRS
Hours: Ones
0–9: The ones digit of the current hours count.
Binary Operation (BCD_EN = 0)
Bit
Description
[7:0]
HRS
Hours
00h–17h: The current hours count.
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160
Real-Time Clock Day-of-the-Week Register
This register contains the current day-of-the-week count. The RTC_DOW Register begins
counting at 01h. The value in the RTC_DOW Register is unchanged by a RESET. The
current setting of BCD_EN determines whether the value in this register is binary
(BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). Access to this register is read-
only if the RTC is locked and read/write if the RTC is unlocked. See Table 83.
Table 83. Real-Time Clock Day-of-the-Week Register (RTC_DOW)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
Reserved
DOW
0
0
0
0
U
U
U
U
R
R
R
R
R/W*
R/W*
R/W*
R/W*
Address
00E3h
Note: U = unchanged by RESET; R = read only; R/W* = read only if RTC locked, read/write if RTC unlocked.
Binary-Coded Decimal Operation (BCD_EN = 1)
Bit
Description
[7:4]
Reserved
These bits are reserved and must be programmed to 0000.
[3:0]
DOW
Day Of The Week
1–7: The current day-of-the-week count.
Binary Operation (BCD_EN = 0)
Bit
Description
[7:4]
Reserved
These bits are reserved and must be programmed to 0000.
[3:0]
DOW
Day Of The Week
01h–07h: The current day-of-the-week count.
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161
Real-Time Clock Day-of-the-Month Register
This register contains the current day-of-the-month count. The RTC_DOM Register
begins counting at 01h. The value in the RTC_DOM Register is unchanged by a RESET.
The current setting of BCD_EN determines whether the values in this register are binary
(BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). Access to this register is read-
only if the RTC is locked, and read/write if the RTC is unlocked. See Table 84.
Table 84. Real-Time Clock Day-of-the-Month Register (RTC_DOM)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
TENS_DOM
DOM
U
U
U
U
U
U
U
U
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
00E4h
Note: U = unchanged by RESET; R/W* = read only if RTC locked, read/write if RTC unlocked.
Binary-Coded Decimal Operation (BCD_EN = 1)
Bit
Description
[7:4]
TENS_DOM
Day Of The Month: Tens
0–3: The tens digit of the current day-of-the-month count.
[3:0]
DOM
Day Of The Month: Ones
0–9: The ones digit of the current day-of-the-month count.
Binary Operation (BCD_EN = 0)
Bit
Description
[7:0]
DOM
Day Of The Month
01h–1Fh: The current day-of-the-month count.
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Real-Time Clock
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Product Specification
162
Real-Time Clock Month Register
This register contains the current month count. The RTC_MON Register begins counting
at 01h. The value in the RTC_MON Register is unchanged by a RESET. The current set-
ting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0)
or binary-coded decimal (BCD_EN = 1). Access to this register is read-only if the RTC is
locked, and read/write if the RTC is unlocked. See Table 85.
Table 85. Real-Time Clock Month Register (RTC_MON)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
TENS_MON
MON
U
U
U
U
U
U
U
U
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
00E5h
Note: U = unchanged by RESET; R/W* = read only if RTC locked, read/write if RTC unlocked.
Binary-Coded Decimal Operation (BCD_EN = 1)
Bit
Description
[7:4]
TENS_MON
Month: Tens
0–1: The tens digit of the current month count.
[3:0]
MON
Month: Ones
0–9: The ones digit of the current month count.
Binary Operation (BCD_EN = 0)
Bit
Description
[7:0]
MON
Month
01h–0Ch: The current month count.
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Real-Time Clock
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Product Specification
163
Real-Time Clock Year Register
This register contains the current year count. The value in the RTC_YR Register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values in
this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). Access to
this register is read-only if the RTC is locked, and read/write if the RTC is unlocked. See
Table 86.
Table 86. Real-Time Clock Year Register (RTC_YR)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
TENS_YR
YR
U
U
U
U
U
U
U
U
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
00E6h
Note: U = unchanged by RESET; R/W* = read only if RTC locked, read/write if RTC unlocked.
Binary-Coded Decimal Operation (BCD_EN = 1)
Bit
Description
[7:4]
TENS_YR
Year: Tens
0–9: The tens digit of the current year count.
[3:0]
YR
Year: Ones
0–9: The ones digit of the current year count.
Binary Operation (BCD_EN = 0)
Bit
Description
[7:0]
YR
Year
00h–63h: The current year count.
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Real-Time Clock
eZ80F91 ASSP
Product Specification
164
Real-Time Clock Century Register
This register contains the current century count. The value in the RTC_CEN Register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values in
this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). Access to
this register is read-only if the RTC is locked, and read/write if the RTC is unlocked. See
Table 87.
Table 87. Real-Time Clock Century Register (RTC_CEN)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
TENS_CEN
CEN
U
U
U
U
U
U
U
U
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
00E7h
Note: U = unchanged by RESET; R/W* = read only if RTC locked, read/write if RTC unlocked.
Binary-Coded Decimal Operation (BCD_EN = 1)
Bit
Description
[7:4]
TENS_CEN
Century: Tens
0–9: The tens digit of the current century count.
[3:0]
CEN
Century: Ones
0–9: The ones digit of the current century count.
Binary Operation (BCD_EN = 0)
Bit
Description
[7:0]
CEN
Century
00h–63h: The current century count.
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Real-Time Clock
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Product Specification
165
Real-Time Clock Alarm Seconds Register
This register contains the alarm seconds value. The value in the RTC_ASEC Register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values in
this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). See Table
88.
Table 88. Real-Time Clock Alarm Seconds Register (RTC_ASEC)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
ATEN_SEC
ASEC
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
00E8h
Note: U = unchanged by RESET; R/W = read/write.
Binary-Coded Decimal Operation (BCD_EN = 1)
Bit
Description
[7:4]
ATEN_SEC
Alarm Seconds: Ten
0–5: The tens digit of the alarm seconds value.
[3:0]
ASEC
Alarm Seconds: Ones
0–9: The ones digit of the alarm seconds value.
Binary Operation (BCD_EN = 0)
Bit
Description
[7:0]
ASEC
Alarm Seconds
00h–3Bh: The alarm seconds value.
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Product Specification
166
Real-Time Clock Alarm Minutes Register
This register contains the alarm minutes value. The value in the RTC_AMIN Register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values in
this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). See Table
89.
Table 89. Real-Time Clock Alarm Minutes Register (RTC_AMIN)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
ATEN_MIN
AMIN
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
00E9h
Note: U = unchanged by RESET; R/W = read/write.
Binary-Coded Decimal Operation (BCD_EN = 1)
Bit
Description
[7:4]
ATEN_MIN
Alarm Minutes: Ten
0–5: The tens digit of the alarm minutes value.
[3:0]
AMIN
Alarm Minutes: Ones
0–9: The ones digit of the alarm minutes value.
Binary Operation (BCD_EN = 0)
Bit
Description
[7:0]
AMIN
Alarm Minutes
00h–3Bh: The alarm minutes value.
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Real-Time Clock
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Product Specification
167
Real-Time Clock Alarm Hours Register
This register contains the alarm hours value. The value in the RTC_AHRS Register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values in
this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). See Table
90.
Table 90. Real-Time Clock Alarm Hours Register (RTC_AHRS)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
ATEN_HRS
AHRS
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
00EAh
Note: U = unchanged by RESET; R/W = read/write.
Binary-Coded Decimal Operation (BCD_EN = 1)
Bit
Description
[7:4]
ATEN_HRS
Alarm Hours: Ten
0–2: The tens digit of the alarm hours value.
[3:0]
AHRS
Alarm Hours: Ones
0–9: The ones digit of the alarm hours value.
Binary Operation (BCD_EN = 0)
Bit
Description
[7:0]
AHRS
Alarm Hours
00h–17h: The alarm hours value.
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Real-Time Clock
eZ80F91 ASSP
Product Specification
168
Real-Time Clock Alarm Day-of-the-Week Register
This register contains the alarm day-of-the-week value. The value in the RTC_ADOW
Register is unchanged by a RESET. The current setting of BCD_EN determines whether
the value in this register is binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1).
See Table 91.
Table 91. Real-Time Clock Alarm Day-of-the-Week Register (RTC_ADOW)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
Reserved
ADOW
0
0
0
0
U
U
U
U
R
R
R
R
R/W*
R/W*
R/W*
R/W*
Address
00EBh
Note: U = unchanged by RESET; R = read only; R/W* = read only if RTC locked, read/write if RTC unlocked.
Binary-Coded Decimal Operation (BCD_EN = 1)
Bit
Description
[7:4]
Reserved
These bits are reserved and must be programmed to 0000.
[3:0]
ADOW
Alarm Day Of The Week
1–7: The alarm day-of-the-week value.
Binary Operation (BCD_EN = 0)
Bit
Description
[7:4]
Reserved
These bits are reserved and must be programmed to 0000.
[3:0]
ADOW
Alarm Day Of The Week
01h–07h: The alarm day-of-the-week value.
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Real-Time Clock
eZ80F91 ASSP
Product Specification
169
Real-Time Clock Alarm Control Register
This register contains control bits for the Real-Time Clock. The RTC_ACTRL Register is
cleared by a RESET. See Table 92.
Table 92. Real-Time Clock Alarm Control Register (RTC_ACTRL)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
ADOW_EN AHRS_EN AMIN_EN ASEC_EN
Reset
R/W
0
0
0
0
0
0
0
0
R
R
R
R
R/W
R/W
R/W
R/W
Address
00ECh
Note: R = read only; R/W = read/write.
Bit
Description
Reserved
[7:4]
These bits are reserved and must be programmed to 0000.
[3]
ADOW_EN
Day Of The Week Alarm Enable
0: The day-of-the-week alarm is disabled.
1: The day-of-the-week alarm is enabled.
[2]
AHRS_EN
Hours Alarm Enable
0: The hours alarm is disabled.
1: The hours alarm is enabled.
[1]
AMIN_EN
Minutes Alarm Enable
0: The minutes alarm is disabled.
1: The minutes alarm is enabled.
[0]
ASEC_EN
Seconds Alarm Enable
0: The seconds alarm is disabled.
1: The seconds alarm is enabled.
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170
Real-Time Clock Control Register
This register contains control and status bits for the Real-Time Clock. Some bits in the
RTC_CTRL Register are cleared by a RESET. The ALARM bit flag and associated inter-
rupt (if INT_EN is enabled) are cleared by reading this register. The ALARM bit flag is
updated by clearing (locking) the RTC_UNLOCK bit or by an increment of the RTC
count. Writing to the RTC_CTRL Register also resets the RTC count prescaler allowing
the RTC to be synchronized to another time source.
SLP_WAKE indicates if an RTC alarm condition initiated the CPU recovery from SLEEP
Mode. This bit is checked after RESET to determine if a sleep-mode recovery is caused by
the RTC. SLP_WAKE is cleared by a read of the RTC_CTRL Register.
Setting the BCD_EN bit causes the RTC to use binary-coded decimal
all registers including the alarm set points.
(BCD) counting in
The CLK_SEL and FREQ_SEL bits select the RTC clock source. If the 32kHz crystal
option is selected, the oscillator is enabled and the internal prescaler is set to divide by
32768. If the power-line frequency option is selected, the prescale value is set by the
FREQ_SEL bit, and the 32 kHz oscillator is disabled. See Table 93.
Table 93. Real-Time Clock Control Register (RTC_CTRL)
Bit
7
6
5
4
3
2
1
0
FREQ_
SEL
SLP_
WAKE UNLOCK
RTC_
Field
ALARM INT_EN BCD_EN CLK_SEL
DAY_SAV
Reset
R/W
U
R
0
U
U
U
U
0/1
R
0
R/W
R/W
R/W
R/W
R/W
R/W
Address
00EDh
Note: U = Unchanged by RESET; R = read only; R/W = read/write.
Bit
Description
[7]
ALARM
Alarm Interrupt
0: Alarm interrupt is inactive.
1: Alarm interrupt is active.
[6]
INT_EN
Alarm Interrupt Enable
0: Interrupt on alarm condition is disabled.
1: Interrupt on alarm condition is enabled.
[5]
BCD_EN
RTC Count/Alarm Value Registers Enable
0: RTC count and alarm value registers are binary.
1: RTC count and alarm value registers are BCD.
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171
Bit
Description (Continued)
RTC Clock Source Select
[4]
CLK_SEL
0: RTC clock source is crystal oscillator output (32768Hz). On-chip 32768Hz oscillator is
enabled.
1: RTC clock source is power-line frequency input. On-chip 32768Hz oscillator is dis-
abled.
[3]
FREQ_SEL
Power Line Frequency Select
0: Power-line frequency is 60Hz.
1: Power-line frequency is 50Hz.
[2]
DAY_SAV
Daylight Savings Time Select
0: Suggested value for Daylight Savings Time not selected.
1: Suggested value for Daylight Savings Time selected. This register bit has been allo-
cated as a storage location only for software applications that use DST. No action is
performed in the eZ80F91 when setting or clearing this bit.
[1]
SLP_WAKE
Sleep Mode Recovery Reset
0: RTC alarm did not generate a sleep-mode recovery reset.
1: RTC alarm generated a sleep-mode recovery reset.
[0]
RTC Counter/Register Lock
RTC_UNLOCK 0: RTC count registers are locked to prevent write access. RTC counter is enabled.
1: RTC count registers are unlocked to allow write access. RTC counter is disabled.
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Universal Asynchronous Receiver/
Transmitter
The UART module implements all of the logic required to support the asynchronous com-
munications protocol. The module also implements two separate 16-byte-deep FIFOs for
both transmission and reception. A block diagram of the UART is shown in Figure 36.
System Clock
Receive
RxD0/RxD1
Buffer
I/O Address
Transmit
Buffer
Data
TxD0/TxD1
Interrupt Signal
CTS0/CTS1
RTS0/RTS1
DSR0/DSR1
DTR0/DTR1
DCD0/DCD1
RI0/RI1
Modem
Control
Logic
Figure 36. UART Block Diagram
The UART module provides the following asynchronous communications protocol-
related features and functions:
•
•
•
•
•
•
5-, 6-, 7-, 8- or 9-bit data transmission
Even/odd, space/mark, address/data, or no parity bit generation and detection
Start and stop bit generation and detection (supports up to two stop bits)
Line break detection and generation
Receiver overrun and framing errors detection
Logic and associated I/O to provide modem handshake capability
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UART Functional Description
The UART Baud Rate Generator (BRG) creates the clock for the serial transmit and
receive functions. The UART module supports all of the various options in the asynchro-
nous transmission and reception protocol including:
•
•
•
•
•
5- to 9-bit transmit/receive
Start bit generation and detection
Parity generation and detection
Stop bit generation and detection
Break generation and detection
The UART contains 16-byte-deep FIFOs in each direction. The FIFOs are enabled or dis-
abled by the application. The receive FIFO features trigger-level detection logic, which
enables the CPU to block-transfer data bytes from the receive FIFO.
UART Functions
The UART function implements:
•
•
•
The transmitter and associated control logic
The receiver and associated control logic
The modem interface and associated logic
UART Transmitter
The transmitter block controls the data transmitted on the TxD output. It implements the
FIFO, access via the UARTx_THR Register, the transmit shift register, the parity genera-
tor, and control logic for the transmitter to control parameters for the asynchronous com-
munications protocol.
The UARTx_THR is a write-only register. The CPU writes the data byte to be transmitted
into this register. In FIFO Mode, up to 16 data bytes are written via the UARTx_THR Reg-
ister. The data byte from the FIFO is transferred to the transmit shift register at the appro-
priate time and transmitted via TxD output. After SYNC_RESET, the UARTx_THR
Register is empty. Therefore, the Transmit Holding Register Empty (THRE) bit (bit 5 of
the UARTx_LSR Register) is 1. An interrupt is sent to the CPU if interrupts are enabled.
The CPU resets this interrupt by loading data into the UARTx_THR Register, which clears
the transmitter interrupt.
The transmit shift register places the byte to be transmitted on the TxD signal serially. The
least-significant bit of the byte to be transmitted is shifted out first and the most-significant
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174
bit is shifted out last. The control logic within the block adds the asynchronous communi-
cations protocol bits to the data byte being transmitted. The transmitter block obtains the
parameters for the protocol from the bits programmed via the UARTx_LCTL Register.
When enabled, an interrupt is generated after the final protocol bit is transmitted which the
CPU resets by loading data into the UARTx_THR Register. The TxD output is set to 1 if
the transmitter is idle (that is, the transmitter does not contain any data to be transmitted).
The transmitter operates with the BRG clock. The data bits are placed on the TxD output
one time every 16 BRG clock cycles. The transmitter block also implements a parity gen-
erator that attaches the parity bit to the byte, if programmed. For 9-bit data, the host CPU
programs the parity bit generator so that it marks the byte as either address (mark parity)
or data (space parity).
UART Receiver
The receiver block controls the data reception from the RxD signal. The receiver block
implements a receiver shift register, receiver line error condition monitoring logic and
receiver data ready logic. It also implements the parity checker.
The UARTx_RBR is a read-only register of the module. The CPU reads received data
from this register. The condition of the UARTx_RBR Register is monitored by the DR bit
(bit 0 of the UARTx_LSR Register). The DR bit is 1 when a data byte is received and
transferred to the UARTx_RBR Register from the receiver shift register. The DR bit is
reset only when the CPU reads all of the received data bytes. If the number of bits received
is less than eight, the unused most-significant bits of the data byte read are 0.
For 9-bit data, the receiver checks incoming bytes for space parity. A line status interrupt
is generated when an address byte is received, because address bytes maintain high parity
bits. The CPU clears the interrupt by determining if the address matches its own, then con-
figures the receiver to either accept the subsequent data bytes if the address matches, or
ignore the data if the address does not match.
The receiver uses the clock from the BRG for receiving the data. This clock must operate
at 16 times the appropriate baud rate. The receiver synchronizes the shift clock on the fall-
ing edge of the RxD input start bit. It then receives a complete byte according to the set
parameters. The receiver also implements logic to detect framing errors, parity errors,
overrun errors, and break signals.
UART Modem Control
The modem control logic provides two outputs and four inputs for handshaking with the
modem. Any change in the modem status inputs, except RI, is detected and an interrupt is
generated. For RI, an interrupt is generated only when the trailing edge of the RI is
detected. The module also provides LOOP Mode for self-diagnostics.
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UART Interrupts
There are six different sources of interrupts from the UART. The six sources of interrupts
are:
•
•
•
Transmitter (two different interrupts)
Receiver (three different interrupts)
Modem status
UART Transmitter Interrupt
A Transmitter Hold Register Empty interrupt is generated if there is no data available in
the hold register. By the same token, a transmission complete interrupt is generated after
the data in the shift register is sent. Both interrupts are disabled using individual interrupt
enable bits, or cleared by writing data into the UARTx_THR Register.
UART Receiver Interrupts
A receiver interrupt is generated by three possible events. The first event, a receiver data
ready interrupt event, indicates that one or more data bytes are received and are ready to
be read. Next, this interrupt is generated if the number of bytes in the receiver FIFO is
greater than or equal to the trigger level. If the FIFO is not enabled, the interrupt is gener-
ated if the receive buffer contains a data byte. This interrupt is cleared by reading the
UARTx_RBR.
The second interrupt source is the receiver time-out. A receiver time-out interrupt is gen-
erated when there are fewer data bytes in the receiver FIFO than the trigger level and there
are no reads and writes to or from the receiver FIFO for four consecutive byte times.
When the receiver time-out interrupt is generated, it is cleared only after emptying the
entire receive FIFO.
The first two interrupt sources from the receiver (data ready and time-out) share an inter-
rupt enable bit. The third source of a receiver interrupt is a line status error, indicating an
error in byte reception. This error results from:
•
Incorrect received parity
For 9-bit data, incorrect parity indicates detection of an address byte.
Note:
•
•
Incorrect framing (that is, the stop bit) is not detected by receiver at the end of the byte.
Receiver overrun condition
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•
A break condition being detected on the receive data input
An interrupt due to one of the above conditions is cleared when the UARTx_LSR Register
is read. In case of FIFO Mode, a line status interrupt is generated only after the received
byte with an error reaches the top of the FIFO and is ready to be read.
A line status interrupt is activated (provided this interrupt is enabled) as long as the read
pointer of the receiver FIFO points to the location of the FIFO that contains a byte with the
error. The interrupt is immediately cleared when the UARTx_LSR Register is read. The
ERR bit of the UARTx_LSR Register is active as long as an erroneous byte is present in
the receiver FIFO.
UART Modem Status Interrupt
The modem status interrupt is generated if there is any change in state of the modem status
inputs to the UART. This interrupt is cleared when the CPU reads the UARTx_MSR Reg-
ister.
UART Recommended Usage
The following standard sequence of events occurs in the UART block of the eZ80F91
device. A description of each follows.
•
•
•
Module Reset
Control Transfers to Configure UART Operation
Data Transfers
Module Reset
Upon reset, all internal registers are set to their default values. All command status regis-
ters are programmed with their default values, and the FIFOs are flushed.
Control Transfers to Configure UART Operation
Based on the requirements of the application, the data transfer baud rate is determined and
the BRG is configured to generate a 16X clock frequency. Interrupts are disabled and the
communication control parameters are programmed in the UARTx_LCTL Register. The
FIFO configuration is determined and the receive trigger levels are set in the
UARTx_FCTL Register. The status registers, UARTx_LSR and UARTx_MSR, are read to
ensure that none of the interrupt sources are active. The interrupts are enabled (except for
the transmit interrupt) and the application is ready to use the module for transmission/
reception.
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Data Transfers
This section describes the transmit, receive and poll mode types of UART data transfers.
Transmit
To transmit data, the application enables the transmit interrupt. An interrupt is immedi-
ately expected in response. The application reads the UARTx_IIR Register and determines
whether the interrupt occurs due to either an empty UARTx_THR Register or a completed
transmission. When the application makes this determination, it writes the transmit data
bytes to the UARTx_THR Register. The number of bytes that the application writes
depends on whether or not the FIFO is enabled. If the FIFO is enabled, the application
writes 16 bytes at a time. If not, the application writes one byte at a time. As a result of the
first write, the interrupt is deactivated. The CPU then waits for the next interrupt. When
the interrupt is raised by the UART module, the CPU repeats the same process until it
exhausts all of the data for transmission.
To control and check the modem status, the application sets up the modem by writing to
the UARTx_MCTL Register and reading the UARTx_MCTL Register before starting the
process described above.
In RS-485 MULTIDROP Mode, the first byte of the message is the station address and the
rest of the message contains the data for that station. You must set the Even Parity Select
(EPS bit 4) and Parity Enable (PEN bit 3) in the UARTx_LCTL before sending the station
address. We recommend that in your UART initialization routine set up the
UARTx_LCTL Register for your data transfer format and set the Parity Enable (PEN bit
3) bit. Follow the steps below each time you want to send a new message:
1. Since the UART automatically clears the Even Parity Select (EPS bit 4) bit in the
UARTx_LCTL after a byte is sent, before starting a new message you have to wait for
the transmitter to go idle. The Transmit Empty (TEMT bit 6) of the UARTx_LSR will
be set. If you set the EPS bit of the UARTx_LCTL before the last byte of the previous
message is transmitted, the EPS bit will be cleared and the new station address will be
sent as data instead of being used as an address.
2. Set the Even Parity Select (EPS bit 4) bit in the UARTx_LCTL Register being careful
not to alter the other bits in the register sets the address mark. Write station address to
the UARTx_THR. The UART will automatically clear the EPS bit after the station
address byte is transmitted.
3. Send the rest of the message. Write data to the UART Transmit Holding Register
UARTx_THR whenever the Transmit Holding Register Empty (THRE bit 5) in the
UARTx_LSR is set.
In MULTIDROP Mode, during receiving start address marks, you will see a receive line
interrupt (INSTS bits[3:1]) in the IIR Register. Read the LSR and check for receive errors
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only and ignore any parity errors. The parity is only used for address marks in this MUL-
TIDROP Mode.
Receive
The receiver is always enabled, and it continually checks for the start bit on the RxD input
signal. When an interrupt is raised by the UART module, the application reads the
UARTx_IIR Register and determines the cause for the interrupt. If the cause is a line sta-
tus interrupt, the application reads the UARTx_LSR Register, reads the data byte and then
discards the byte or take other appropriate action. If the interrupt is caused by a receive-
data-ready condition, the application alternately reads the UARTx_LSR and
UARTx_RBR registers and removes all of the received data bytes. It reads the
UARTx_LSR Register before reading the UARTx_RBR Register to determine that there is
no error in the received data.
To control and check modem status, the application sets up the modem by writing to the
UARTx_MCTL Register and reading the UARTx_MSR Register before starting the pro-
cess described above.
Poll Mode Transfers
When interrupts are disabled, all data transfers are referred to as poll mode transfers. In
poll mode transfers, the application must continually poll the UARTx_LSR Register to
transmit or receive data without enabling the interrupts. The same holds true for the
UARTx_MSR Register. If the interrupts are not enabled, the data in the UARTx_IIR Reg-
ister cannot be used to determine the cause of interrupt.
Baud Rate Generator
The Baud Rate Generator consists of a 16-bit downcounter, two registers, and associated
decoding logic. The initial value of the Baud Rate Generator is defined by the two BRG
Divisor Latch registers, {UARTx_BRG_H, UARTx_BRG_L}. At the rising edge of each
system clock, the BRG decrements until it reaches the value 0001h. On the next system
clock rising edge, the BRG reloads the initial value from {UARTx_BRG_H,
UARTx_BRG_L) and outputs a pulse to indicate the end-of-count.
Calculate the UART data rate with the following equation:
System Clock Frequency
UART Data Rate (bits/s)
=
16 x UART Baud Rate Generator Divisor
Upon RESET, the 16-bit BRG divisor value resets to the smallest allowable value of
0002h. Therefore, the minimum BRG clock divisor ratio is 2. A software write to either
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the Low- or High-byte registers for the BRG Divisor Latch causes both the low and high
bytes to load into the BRG counter, and causes the count to restart.
The divisor registers are accessed only if bit 7 of the UART Line Control Register
(UARTx_LCTL) is set to 1. After reset, this bit is reset to 0.
Recommended Use of the Baud Rate Generator
The following is the normal sequence of operations that must occur after the eZ80F91 is
powered on to configure the BRG:
1. Assert and deassert RESET.
2. Set UARTx_LCTL[7] to 1 to enable access of the BRG divisor registers.
3. Program the UARTx_BRG_L and UARTx_BRG_H registers.
4. Clear UARTx_LCTL[7] to 0 to disable access of the BRG divisor registers.
BRG Control Registers
This section presents register data for the UART Baud Rate Generator.
UART Baud Rate Generator High and Low Byte Registers
The registers hold the low and high bytes of the 16-bit divisor count loaded by the CPU for
UART baud rate generation. The 16-bit clock divisor value is returned by
{UARTx_BRG_H, UARTx_BRG_L}, where x is either 0 or 1 to identify the two available
UART devices. Upon RESET, the 16-bit BRG divisor value resets to 0002h. The initial
16-bit divisor value must be between 0002hand FFFFh, because the values 0000hand
0001hare invalid and proper operation is not guaranteed at these two values. As a result,
the minimum BRG clock divisor ratio is 2.
A write to either the Low- or High-byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter. The count is then restarted.
Bit 7 of the associated UART Line Control Register (UARTx_LCTL) must be set to 1 to
access this register. See Tables 94 and 95. For more information, see the UART Line Con-
trol Register section on page 186.
Note: The UARTx_BRG_L registers share the same address space with the UARTx_RBR and
UARTx_THR registers. The UARTx_BRG_H registers share the same address space with
the UARTx_IER registers. Bit 7 of the associated UART Line Control Register
(UARTx_LCTL) must be set to 1 to enable access to the BRG registers.
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Table 94. UART Baud Rate Generator Low Byte Registers (UARTx_BRG_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
UART_BRG_L
0
0
0
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
UART0_BRG_L = 00C0h, UART1_BRG_L = 00D0h
Note: x indicates UART[1:0]; R = read only; R/W = read/write.
Bit
Description
[7:0]
UART_BRG_L
UART Baud Rate Generator Low Byte
00h–FFh: These bits represent the low byte of the 16-bit BRG divider value. The com-
plete BRG divisor value is returned by {UART_BRG_H, UART_BRG_L}.
Table 95. UART Baud Rate Generator High Byte Registers (UARTx_BRG_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
UART_BRG_H
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
UART0_BRG_H = 00C1h, UART1_BRG_H = 00D1h
Note: x indicates UART[1:0]; R = read only; R/W = read/write.
Bit
Description
[7:0]
UART_BRG_H
UART Baud Rate Generator High Byte
00h–FFh: These bits represent the high byte of the 16-bit BRG divider value. The com-
plete BRG divisor value is returned by {UART_BRG_H, UART_BRG_L}.
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UART Registers
After a system reset, all UART registers are set to their default values. Any writes to
unused registers or register bits are ignored and reads return a value of 0. For compatibility
with future revisions, unused bits within a register must always be written with a value of
0. Read/write attributes, reset conditions, and bit descriptions of all of the UART registers
are provided in this section.
UART Transmit Holding Register
If less than eight bits are programmed for transmission, the lower bits of the byte written
to this register are selected for transmission. The Transmit FIFO is mapped at this address.
You can write up to 16 bytes for transmission at one time to this address if the FIFO is
enabled by the application. If the FIFO is disabled, this buffer is only one byte deep.
These registers share the same address space as the UARTx_RBR and UARTx_BRG_L
registers. See Table 96.
Table 96. UART Transmit Holding Registers (UARTx_THR)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
TxD
U
U
U
U
U
U
U
U
W
W
W
W
W
W
W
W
Address
UART0_THR = 00C0h, UART1_THR = 00D0h
Note: x indicates UART[1:0]; U = undefined; W = write only.
Bit
Description
[7:0]
TxD
Transmit Data
00h–FFh: Transmit data byte.
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UART Receive Buffer Register
The bits in this register reflect the data received. If less than eight bits are programmed for
reception, the lower bits of the byte reflect the bits received, whereas upper unused bits are
0. The Receive FIFO is mapped at this address. If the FIFO is disabled, this buffer is only
one byte deep.
These registers share the same address space as the UARTx_THR and UARTx_BRG_L
registers. See Table 97.
Table 97. UART Receive Buffer Registers (UARTx_RBR)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
RxD
U
R
U
R
U
R
U
R
U
R
U
R
U
R
U
R
Address
UART0_RBR = 00C0h, UART1_RBR = 00D0h
Note: x indicates UART[1:0]; U = undefined; R = read only.
Bit
Description
[7:0]
RxD
Receive Data
00h–FFh: Receive data byte.
UART Interrupt Enable Register
The UARTx_IER Register, shown in Table 98, is used to enable and disable the UART
interrupts. The UARTx_IER registers share the same I/O addresses as the
UARTx_BRG_H registers.
Table 98. UART Interrupt Enable Registers (UARTx_IER)
Bit
7
6
Reserved
0
5
4
TCIE
0
3
2
1
TIE
0
0
RIE
0
Field
Reset
R/W
MIIE
0
LSIE
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
UART0_IER = 00C1h, UART1_IER = 00D1h
Note: x indicates UART[1:0]; R/W = read/write.
Bit
Description
[7:5]
Reserved
These bits are reserved and must be programmed to 000.
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Bit
Description (Continued)
[4]
TCIE
Transmission Complete Interrupt
0: Transmission complete interrupt is disabled
1: Transmission complete interrupt is generated when both the transmit hold register and
the transmit shift register are empty
[3]
MIIE
Modem Interrupt Input Enable
0: Modem interrupt on edge detect of status inputs is disabled.
1: Modem interrupt on edge detect of status inputs is enabled.
[2]
LSIE
Line Status Interrupt Input Enable
0: Line status interrupt is disabled.
1: Line status interrupt is enabled for receive data errors: incorrect parity bit received,
framing error, overrun error, or break detection.
[1]
TIE
Transmit Interrupt Input Enable
0: Transmit interrupt is disabled.
1: Transmit interrupt is enabled. Interrupt is generated when the transmit FIFO/buffer is
empty indicating no more bytes available for transmission.
[0]
RIE
Receive Interrupt Input Enable
0: Receive interrupt is disabled.
1: Receive interrupt and receiver time-out interrupt are enabled. Interrupt is generated if
the FIFO/buffer contains data ready to be read or if the receiver times out.
UART Interrupt Identification Register
The read-only UARTx_IIR Register allows you to check whether the FIFO is enabled and
the status of interrupts. These registers share the same I/O addresses as the UARTx_FCTL
registers. See Tables 99 and 100.
Table 99. UART Interrupt Identification Registers (UARTx_IIR)
Bit
7
FSTS
0
6
5
4
3
2
INSTS
0
1
0
Field
Reset
R/W
Reserved
INTBIT
0
0
0
0
0
1
R
R
R
R
R
R
R
R
Address
UART0_IIR = 00C2h, UART1_IIR = 00D2h
Note: x indicates UART[1:0]; R = read only.
Bit
Description
[7]
FSTS
FIFO Enable
0: FIFO is disabled.
1: FIFO is enabled.
[6:4]
Reserved
These bits are reserved and must be programmed to 000.
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Bit
Description (Continued)
Interrupt Status
[3:1]
INSTS
000–110: The code indicated in these three bits is valid only if INTBIT is 1. If two internal
interrupt sources are active and their respective enable bits are High, only the higher pri-
ority interrupt is seen by the application. The lower-priority interrupt code is indicated only
after the higher-priority interrupt is serviced. Table 100 lists the interrupt status codes.
[0]
INTBIT
UART Interrupt Source Bit
0: There is an active interrupt source within the UART.
1: There is not an active interrupt source within the UART.
Table 100. UART Interrupt Status Codes
INSTS
Value
Priority
Highest
Second
Third
Interrupt Type
011
Receiver Line Status
Receive Data Ready or Trigger Level
Character Time-out
010
110
101
001
000
Fourth
Fifth
Transmission Complete
Transmit Buffer Empty
Modem Status
Lowest
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UART FIFO Control Register
This register is used to monitor trigger levels, clear FIFO pointers, and enable or disable
the FIFO. The UARTx_FCTL registers share the same I/O addresses as the UARTx_IIR
registers. See Table 101.
Table 101. UART FIFO Control Registers (UARTx_FCTL)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
TRIG
Reserved
CLRTxF CLRRxF FIFOEN
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Address
UART0_FCTL = 00C2h, UART1_FCTL = 00D2h
Note: x indicates UART[1:0]; W = write only.
Bit
Description
[7:6]
TRIG
Receive FIFO Trigger Level
00: Receive FIFO trigger level set to 1. Receive data interrupt is generated when there is
1 byte in the FIFO. Valid only if FIFO is enabled.
01: Receive FIFO trigger level set to 4. Receive data interrupt is generated when there
are 4 bytes in the FIFO. Valid only if FIFO is enabled.
10: Receive FIFO trigger level set to 8. Receive data interrupt is generated when there
are 8 bytes in the FIFO. Valid only if FIFO is enabled.
11: Receive FIFO trigger level set to 14. Receive data interrupt is generated when there
are 14 bytes in the FIFO. Valid only if FIFO is enabled.
[5:3]
Reserved
These bits are reserved and must be programmed to 000b.
[2]
CLRTxF
Clear Transmit FIFO Logic
0: Transmit Disable. This register bit works differently than the standard 16550 UART.
This bit must be set to transmit data. When it is reset the transmit FIFO logic is reset
along with the associated transmit logic to keep them in sync. This bit is now persis-
tent; it does not self clear and it must remain at 1 to transmit data.
1: Transmit Enable.
[1]
CLRRxF
Clear Receive FIFO Logic
0: Receive Disable. This register bit works differently than the standard 16550 UART.
This bit must be set to receive data. When it is reset the receive FIFO logic is reset
along with the associated receive logic to keep them in sync and avoid the previous
version’s lookup problem. This bit is now persistent–it does not self clear and it must
remain at 1 to receive data.
1: Receive Enable.
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Bit
Description (Continued)
[0]
FIFOEN
FIFO Enable
0: FIFOs are not used.
1: Receive and transmit FIFOs are used–You must clear the FIFO logic using bits 1 and
2. First enable the FIFOs by setting bit 0 to 1 then enable the receiver and transmitter
by setting bits 1 and 2.
UART Line Control Register
This register is used to control the communication control parameters. See Tables 102 and
103.
Table 102. UART Line Control Registers (UARTx_LCTL)
Bit
7
DLAB
0
6
SB
0
5
4
3
2
1
CHAR
0
0
Field
Reset
R/W
FPE
0
EPS
0
PEN
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
UART0_LCTL = 00C3h, UART1_LCTL = 00D3h
Note: x indicates UART[1:0]; R/W = read/write.
Bit
Description
[7]
DLAB
Divisor Latch Access Bit
0: Access to the UART registers at I/O addresses C0h, C1h, D0h and D1h is enabled.
1: Access to the Baud Rate Generator registers at I/O addresses C0h, C1h, D0h and D1h
is enabled.
[6]
SB
Send Break
0: Do not send a break signal.
1: UART sends continuous zeroes on the transmit output from the next bit boundary. The
transmit data in the transmit shift register is ignored. After forcing this bit High, the TxD
output is 0 only after the bit boundary is reached. Just before forcing TxD to 0, the
transmit FIFO is cleared. Any new data written to the transmit FIFO during a break
must be written only after the THRE bit of UARTx_LSR Register goes High. This new
data is transmitted after the UART recovers from the break. After the break is removed,
the UART recovers from the break for the next BRG edge.
[5]
FPE
Force Parity Error
0: Do not force a parity error.
1: Force a parity error. When this bit and the parity enable bit (pen) are both 1, an incor-
rect parity bit is transmitted with the data byte.
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Bit
Description (Continued)
Even Parity Select
[4]
EPS
0: Use odd parity for transmit and receive. The total number of 1 bits in the transmit data
plus parity bit is odd. Used as SPACE bit in MULTIDROP Mode. See Table 104 for par-
ity select definitions. Note: Receive Parity is set to SPACE in MULTIDROP Mode.
1: Use even parity for transmit and receive. The total number of 1 bits in the transmit data
plus parity bit is even. Used as MARK bit in MULTIDROP Mode. See Table 104 for par-
ity select definitions.
[3]
PEN
Parity Enable
0: Parity bit transmit and receive is disabled.
1: Parity bit transmit and receive is enabled. For transmit, a parity bit is generated and
transmitted with every data character. For receive, the parity is checked for every
incoming data character. In MULTIDROP Mode, receive parity is checked for space
parity.
[2:0]
CHAR
UART Character Parameter Selection
000–111: See Table 103 for a description of these values.
Table 103. UART Character Parameter Definition
Character
Length (Tx/Rx
Data Bits)
Stop Bits (Tx
Stop Bits)
CHAR[2:0]
000
5
6
7
8
5
6
7
8
1
1
1
1
2
2
2
2
001
010
011
100
101
110
111
Table 104. Parity Select Definition for Multidrop Communications
MULTIDROP Mode
Even Parity Select
Parity Type
odd
0
0
1
1
0
1
even
0
space
mark
1*
Note: *In MULTIDROP Mode, EPS resets to 0 after the first character is sent.
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UART Modem Control Register
This register is used to control and check the modem status. See Table 105.
Table 105. UART Modem Control Registers (UARTx_MCTL)
Bit
7
6
5
MDM
0
4
LOOP
0
3
OUT2
0
2
OUT1
0
1
0
Field
Reset
R/W
Reserved POLARITY
RTS
0
DTR
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
UART0_MCTL = 00C4h, UART1_MCTL = 00D4h
Note: x indicates UART[1:0]; R = read only; R/W = read/write.
Bit
Description
[7]
Reserved
This bit is reserved and must be programmed to 0.
[6]
TxD and RxD Polarity
POLARITY
0: TxD and RxD signals; normal polarity.
1: Invert polarity of TxD and RxD signals.
[5]
MDM
Multidrop Mode Enable
0: MULTIDROP Mode disabled.
1: MULTIDROP Mode enabled. See Table 104 for parity select definitions.
[4]
LOOP
Loopback Mode Enable
0: LOOPBACK Mode is not enabled.
1: LOOPBACK Mode is enabled. The UART operates in internal LOOPBACK Mode. The
transmit data output port is disconnected from the internal transmit data output and set
to 1. The receive data input port is disconnected and internal receive data is connected
to internal transmit data. The modem status input ports are disconnected and the four
bits of the modem control register are connected as modem status inputs. The two
modem control output ports (OUT1&2) are set to their inactive state
[3]
OUT2
Loopback Output 2
0–1: No function in normal operation. In LOOPBACK Mode, this bit is connected to the
DCD bit in the UART Status Register.
[2]
OUT1
Loopback Output 1
0–1: No function in normal operation. In LOOPBACK Mode, this bit is connected to the RI
bit in the UART Status Register.
[1]
RTS
Request to Send
0–1: In normal operation, the RTS output port is the inverse of this bit. In LOOPBACK
Mode, this bit is connected to the CTS bit in the UART Status Register.
[0]
DTR
Data Terminal Ready
0–1: In normal operation, the DTR output port is the inverse of this bit. In LOOPBACK
Mode, this bit is connected to the DSR bit in the UART Status Register.
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UART Line Status Register
This register is used to show the status of UART interrupts and registers. See Table 106.
Table 106. UART Line Status Registers (UARTx_LSR)
Bit
7
ERR
0
6
TEMT
1
5
THRE
1
4
BI
0
3
FE
0
2
PE
0
1
OE
0
0
DR
0
Field
Reset
R/W
R
R
R
R
R
R
R
R
Address
UART0_LSR = 00C5h, UART1_LSR = 00D5h
Note: x indicates UART[1:0]; R = read only.
Bit
Description
[7]
ERR
Error Detection
0: Always 0 when operating in with the FIFO disabled. With the FIFO enabled, this bit is
reset when the UARTx_LSR Register is read and there are no more bytes with error
status in the FIFO.
1: Error detected in the FIFO. There is at least 1 parity, framing or break indication error in
the FIFO.
[6]
TEMT
Transmit Empty
0: Transmit holding register/FIFO is not empty or transmit shift register is not empty or
transmitter is not idle.
1: Transmit holding register/FIFO and transmit shift register are empty; and the transmit-
ter is idle. This bit cannot be set to 1 during the break condition. This bit only becomes
1 after the BREAK command is removed.
[5]
THRE
Transmit Holding Register Empty
0: Transmit holding register/FIFO is not empty.
1: Transmit holding register/FIFO. This bit cannot be set to 1 during the break condition.
This bit only becomes 1 after the BREAK command is removed.
[4]
BI
Break Indicator
0: Receiver does not detect a break condition. This bit is reset to 0 when the UARTx_LSR
Register is read.
1: Receiver detects a break condition on the receive input line. This bit is 1 if the duration
of break condition on the receive data is longer than one character transmission time,
the time depends on the programming of the UARTx_LSR Register. In case of FIFO
only one null character is loaded into the receiver FIFO with the framing error. The
framing error is revealed to the eZ80 whenever that particular data is read from the
receiver FIFO.
[3]
FE
Framing Error Detect
0: No framing error detected for character at the top of the FIFO. This bit is reset to 0
when the UARTx_LSR Register is read.
1: Framing error detected for the character at the top of the FIFO. This bit is set to 1 when
the stop bit following the data/parity bit is logic 0.
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Bit
Description (Continued)
Parity Error
[2]
PE
0: The received character at the top of the FIFO does not contain a parity error. In MULTI-
DROP Mode, this indicates that the received character is a data byte. This bit is reset
to 0 when the UARTx_LSR Register is read.
1: The received character at the top of the FIFO contains a parity error. In MULTIDROP
Mode, this indicates that the received character is an address byte.
[1]
OE
Overrun Error Detect
0: The received character at the top of the FIFO does not contain an overrun error. This
bit is reset to 0 when the UARTx_LSR Register is read.
1: Overrun error is detected. If the FIFO is not enabled, this indicates that the data in the
receive buffer register was not read before the next character was transferred into the
receiver buffer register. If the FIFO is enabled, this indicates the FIFO was already full
when an additional character was received by the receiver shift register. The character
in the receiver shift register is not put into the receiver FIFO.
[0]
DR
Data Ready
0: This bit is reset to 0 when the UARTx_RBR Register is read or all bytes are read from
the receiver FIFO.
1: If the FIFO is not enabled, this bit is set to 1 when a complete incoming character is
transferred into the receiver buffer register from the receiver shift register. If the FIFO is
enabled, this bit is set to 1 when a character is received and transferred to the receiver
FIFO.
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UART Modem Status Register
This register is used to show the status of the UART signals. See Table 107.
Table 107. UART Modem Status Registers (UARTx_MSR)
Bit
7
DCD
U
6
RI
U
5
DSR
U
4
CTS
U
3
DDCD
U
2
TERI
U
1
DDSR
U
0
DCTS
U
Field
Reset
R/W
R
R
R
R
R
R
R
R
Address
UART0_MSR = 00C6h, UART1_MSR = 00D6h
Note: x indicates UART[1:0]; U = undefined; R = read only.
Bit
Description
[7]
DCD
Data Carrier Detect
0–1: In NORMAL Mode, this bit reflects the inverted state of the DCDx input pin. In
LOOPBACK Mode, this bit reflects the value of the UARTx_MCTL[3] = out2.
[6]
RI
Ring Indicator
0–1: In NORMAL Mode, this bit reflects the inverted state of the RIx input pin. In LOOP-
BACK Mode, this bit reflects the value of the UARTx_MCTL[2] = out1.
[5]
DSR
Data Set Ready
0–1: In NORMAL Mode, this bit reflects the inverted state of the DSRx input pin. In
LOOPBACK Mode, this bit reflects the value of the UARTx_MCTL[0] = DTR.
[4]
CTS
Clear To Send
0–1: In NORMAL Mode, this bit reflects the inverted state of the CTSx input pin. In LOOP-
BACK Mode, this bit reflects the value of the UARTx_MCTL[1] = RTS.
[3]
DDCD
Delta Status Change of DCD
0–1: This bit is set to 1 whenever the DCDx pin changes state. This bit is reset to 0 when
the UARTx_MSR Register is read.
[2]
TERI
Trailing Edge Change on RI
0–1: This bit is set to 1 whenever a falling edge is detected on the RIx pin. This bit is reset
to 0 when the UARTx_MSR Register is read.
[1]
DDSR
Delta Status Change of DSR
0–1: This bit is set to 1 whenever the DSRx pin changes state. This bit is reset to 0 when
the UARTx_MSR Register is read.
[0]
DCTS
Delta Status Change of CTS
0–1: This bit is set to 1 whenever the CTSx pin changes state. This bit is reset to 0 when
the UARTx_MSR Register is read.
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UART Scratch Pad Register
The UARTx_SPR Register is used by the system as a general-purpose read/write register.
See Table 108.
Table 108. UART Scratch Pad Registers (UARTx_SPR)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
SPR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
UART0_SPR = 00C7h, UART1_SPR = 00D7h
Note: x indicates UART[1:0]; R/W = read/write.
Bit
Description
Scratch Pad
[7:0]
SPR
00h–FFh: UART scratch pad register is available for use as a general-purpose read/write
register. In MULTIDROP 9-BIT Mode, this register is used to store the address value.
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Infrared Encoder/Decoder
The eZ80F91 device contains a UART to an infrared encoder/decoder (endec). The endec
is integrated with the on-chip UART0 to allow easy communication between the CPU and
IrDA Physical Layer Specification Version 1.4-compatible infrared transceivers, as shown
in Figure 37. Infrared communication provides secure, reliable, high-speed, low-cost,
point-to-point communication between PCs, PDAs, mobile telephones, printers and other
infrared-enabled devices.
eZ80F91
System
Clock
Infrared
Transceiver
RxD
TxD
IR_RxD
IR_TxD
RxD
TxD
Infrared
Encoder/Decoder
UART0
Baud Rate
Clock
Interrupt
I/O
Data
I/O
Address
Data
Signal Address
¤
To eZ80 CPU
Figure 37. Infrared System Block Diagram
Functional Description
When the endec is enabled, the transmit data from the on-chip UART is encoded as digital
signals in accordance with the IrDA standard and output to the infrared transceiver. Like-
wise, data received from the infrared transceiver is decoded by the endec and passed to the
UART. Communication is half-duplex, meaning that simultaneous data transmission and
reception is not allowed.
The baud rate is set by the UART Baud Rate Generator (BRG), which supports IrDA stan-
dard baud rates from 9600bps to 115.2kbps. Higher baud rates are possible, but do not
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meet IrDA specifications. The UART must be enabled to use the endec. For more informa-
tion about the UART and its BRG, see the Universal Asynchronous Receiver/Transmitter
chapter on page 172.
Transmit
The data to be transmitted via the IR transceiver is the data sent to UART0. The UART
transmit signal, TxD, and Baud Rate Clock are used by the endec to generate the modula-
tion signal, IR_TxD, that drives the infrared transceiver. Each UART bit is 16 clocks wide.
If the data to be transmitted is a logic 1 (High), the IR_TxD signal remains Low (0) for the
full 16-clock period. If the data to be transmitted is a logic 0, a 3-clock High (1) pulse is
output following a 7-clock Low (0) period. Following the 3-clock High pulse, a 6-clock
Low pulse completes the full 16-clock data period. Data transmission is shown in
Figure 38. During data transmission, the IR receive function must be disabled by clearing
the IR_RxEN bit in the IR_CTL reg to 0 to prevent transmitter-to-receiver crosstalk.
16-clock
period
Baud Rate
Clock
UART_TxD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
3-clock
pulse
IR_TxD
7-clock
delay
Figure 38. Infrared Data Transmission
Receive
Data received from the IR transceiver via the IR_RxD signal is decoded by the endec and
passed to the UART. The IR_RxEN bit in the IR_CTL Register must be set to enable the
receiver decoder. The IrDA serial infrared (SIR) data format uses half duplex communica-
tion. Therefore, the UART must not be allowed to transmit while the receiver decoder is
enabled. The UART Baud Rate Clock is used by the endec to generate the demodulated
signal, RxD, that drives the UART. Each UART bit is 16 clocks wide. If the data to be
received is a logic 1 (High), the IR_RxD signal remains High (1) for the full 16-clock
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period. If the data to be received is a logic 0, a delayed Low (0) pulse is output on RxD.
Data transmission is shown in Figure 39.
16-clock
period
Baud Rate
Clock
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_RxD
UART_RxD
16-clock
period
16-clock
period
16-clock
period
16-clock
period
8-clock
delay
Figure 39. Infrared Data Reception
The IrDA endec is designed to ignore pulses on IR_RxD which do not comply with IrDA
pulse width specifications. Input pulses wider than five baud clocks (that is, 5/16 of a bit
period) are always ignored, as this would be a violation of the maximum pulse width spec-
ified for any standard baud rate up to 115.2kbps. The check for minimum pulse widths is
optional, since using a slow system clock frequency limits the ability to accurately mea-
sure narrow pulse widths near the IrDA specification minimum of 1.41 us for the 2.4–
115.2kbps rate range.
To enable checks of minimum input pulse width on IR_RxD, a non-zero value must be
programmed into the MIN_PULSE field of IR_CTL (bits [7:4]). This field forms the
most-significant four bits of the 6-bit down-counter used to determine if an input pulse
will be ignored because it is too narrow. The lower two counter bits are hard-coded to load
with 0x3h, resulting in a total down-count equal to ((MIN_PULSE* 4) + 3). To be
accepted, input pulses must have a width greater than or equal to the down-count value
times the system clock period.
The following equation is used to determine an appropriate setting for MIN_PULSE:
MIN_PULSE = INT( ((F *W ) – 3) ÷ 4 )
sys
min
In this equation, Fsys is the frequency of the system clock, and Wmin is the minimum width
of recognized input pulses.
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If this equation results in a value less than one, MIN_PULSE must be set to 0x0h, which
enables edge detection and ensures that valid pulses wider than Wmin are accepted. The
field's maximum setting of 0xFhsupports a Wmin of 1.25 us when Fsys is 50MHz.
Jitter
Due to the inherent sampling of the received IR_RxD signal by the Bit Rate Clock, some
jitter is expected on the first bit in any sequence of data. However, all subsequent bits in
the received data stream are a fixed 16 clock periods wide.
Infrared Encoder/Decoder Signal Pins
The endec signal pins, IR_TxD and IR_RxD, are multiplexed with General Purpose Input/
Output (GPIO) pins. These GPIO pins must be configured for alternate function operation
for the endec to operate.
The remaining six UART0 pins, CTS0, DCD0, DSR0, DTR0, RTS and RI0, are not
required for use with the endec. The UART0 modem status interrupt must be disabled to
prevent unwanted interrupts from these pins. The GPIO pins corresponding to these six
unused UART0 pins are used for inputs, outputs, or interrupt sources. Recommended
GPIO Port D control register settings are provided in Table 109. See the General-Purpose
Input/Output chapter on page 45 for additional information about setting the GPIO port
modes.
Table 109. GPIO Mode Selection when using the IrDA Encoder/Decoder
GPIO Port
D Bits
PD0
Allowable GPIO Port Mode
Allowable Port Mode Functions
Alternate Function
7
7
PD1
Alternate Function
PD2–PD7
Any other than GPIO Mode 7
(1, 2, 3, 4, 5, 6, 8, or 9)
Output, Input, Open-Drain, Open-
Source, Level-sensitive Interrupt Input,
or Edge-Triggered Interrupt Input
Loopback Testing
Both internal and external loopback testing is accomplished with the endec on the eZ80F91
device. Internal loopback testing is enabled by setting the LOOP_BACK bit to 1. During
internal loopback, the IR_TxD output signal is inverted and connected on-chip to the
IR_RxD input. External loopback testing of the off-chip IrDA transceiver is accomplished
by transmitting data from the UART while the receiver is enabled (IR_RxEN set to 1).
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Infrared Encoder/Decoder Register
After a RESET, the Infrared Encoder/Decoder Register, shown in Table 110, is set to its
default value. Any writes to unused register bits are ignored and reads return a value of 0.
Table 110. Infrared Encoder/Decoder Control Registers (IR_CTL)
Bit
7
6
5
4
3
2
1
0
MIN_PULSE
Reserved LOOP_BACK IR_RxEN IR_EN
Field
Reset
R/W
0
0
0
0
0
R
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00BFh
Address
Note: R = read only; R/W = read/write.
Bit
Description
Minimum Receive Pulse
[7:4]
MIN_PULSE
0000: Minimum receive pulse width control. When this field is equal to 0x0, the IrDA
decoder uses edge detection to accept arbitrarily narrow (that is, short) input
pulses.
1h–Fh: When not equal to 0x0, this field forms the most-significant four bits of the 6-bit
down-counter used to determine if an input pulse will be ignored because it is too
narrow. The lower two counter bits are hard-coded to load with 0x3, resulting in a
total down-count equal to ((IR_CTL[4:0]MIN_PULSE * 4) + 3). To be accepted,
input pulses must have a width greater than or equal to the down-count value
times the system clock period.
[3]
Reserved
This bit is reserved and must be programmed to 0.
[2]
Internal LOOPBACK Mode
LOOP_BACK 0: Internal LOOPBACK Mode is disabled.
1: Internal LOOPBACK Mode is enabled.
IR_TxD output is inverted and connected to IR_RxD input for internal loop back test-
ing.
[1]
IR_RxEN
Endec Receive Data
0: IR_RxD data is ignored.
1: IR_RxD data is passed to UART0 RxD.
[0]
IR_EN
Endec Enable
0: Endec is disabled.
1: Endec is enabled.
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Serial Peripheral Interface
The Serial Peripheral Interface (SPI) is a synchronous interface allowing several SPI-type
devices to be interconnected. The SPI is a full-duplex, synchronous, character-oriented
communication channel that employs a four-wire interface. The SPI block consists of a
transmitter, receiver, baud rate generator, and control unit. During an SPI transfer, data is
sent and received simultaneously by both the master and the slave SPI devices.
In a serial peripheral interface, separate signals are required for data and clock. The SPI is
configured either as a master or as a slave. The connection of two SPI devices (one master
and one slave) and the direction of data transfer is demonstrated in Figures 40 and 41.
MASTER
SS
MISO
Bit 0
Bit 7
DATAOUT
CLKOUT
MOSI
SCK
DATAIN
8-Bit Shift Register
Baud Rate
Generator
Figure 40. SPI Master Device
SLAVE
SS
ENABLE
MOSI
SCK
Bit 0
Bit 7
MISO
DATAOUT
DATAIN
CLKIN
8-Bit Shift Register
Figure 41. SPI Slave Device
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SPI Signals
The four basic SPI signals are:
•
•
•
•
MISO (Master In, Slave Out)
MOSI (Master Out, Slave In)
SCK (SPI Serial Clock)
SS (Slave Select)
These SPI signals are discussed in the following paragraphs. Each signal is described in
both MASTER and SLAVE modes.
Master In, Slave Out
The Master In, Slave Out (MISO) pin is configured as an input in a master device and as
an output in a slave device. It is one of the two lines that transfer serial data, with the most-
significant bit sent first. The MISO pin of a slave device is placed in a high-impedance
state if the slave is not selected. When the SPI is not enabled, this signal is in a high-
impedance state.
Master Out, Slave In
The Master Out, Slave In (MOSI) pin is configured as an output in a master device and as
an input in a slave device. It is one of the two lines that transfer serial data, with the most-
significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance
state.
Slave Select
The active Low Slave Select (SS) input signal is used to select the SPI as a slave device. It
must be Low prior to all data communication and must stay Low for the duration of the
data transfer.
The SS input signal must be High for the SPI to operate as a master device. If the SS signal
goes Low in Master Mode, a Mode Fault error flag (MODF) is set in the SPI_SR Register.
For more information, see the SPI Status Register section on page 206.
When the clock phase (CPHA) is set to 0, the shift clock is the logic OR of SS with SCK.
In this clock phase mode, SS must go High between successive characters in an SPI mes-
sage. When CPHA is set to 1, SS remains Low for several SPI characters. In cases in
which there is only one SPI slave, its SS line could be tied Low as long as CPHA is set to
1. For more information about CPHA, see the SPI Control Register section on page 205.
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Serial Clock
The Serial Clock (SCK) is used to synchronize data movement both in and out of the
device via its MOSI and MISO pins. The master and slave are each capable of exchanging
a byte of data during a sequence of eight clock cycles. Because SCK is generated by the
master, the SCK pin becomes an input on a slave device. The SPI contains an internal
divide-by-two clock divider. In MASTER Mode, the SPI serial clock is one-half the fre-
quency of the clock signal created by the SPI Baud Rate Generator.
As demonstrated in Figure 42 and Table 111, four possible timing relations are chosen by
using the clock polarity (CPOL) and clock phase CPHA control bits in the SPI Control
Register. See the SPI Control Register section on page 205. Both the master and slave
must operate with the identical timing, CPOL, and CPHA. The master device always
places data on the MOSI line a half-cycle before the clock edge (SCK signal), for the slave
device to latch the data.
Number of Cycles on the SCK Signal
1
2
3
4
5
6
7
8
SCK (CPOL bit = 0)
SCK (CPOL bit = 1)
Sample Input
(CPHA bit = 0) Data Out
MSB
6
5
4
3
2
1
LSB
Sample Input
(CPHA bit = 1) Data Out
MSB
6
5
4
3
2
1
LSB
ENABLE (To Slave)
Figure 42. SPI Timing
Table 111. SPI Clock Phase and Clock Polarity Operation
SCK
Transmit
Edge
SCK
Receive
Edge
SCK
Idle
State
SS High
Between
Characters?
CPHA
CPOL
0
0
0
1
Falling
Rising
Rising
Falling
Low
Yes
Yes
High
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Table 111. SPI Clock Phase and Clock Polarity Operation (Continued)
SCK
Transmit
Edge
SCK
Receive
Edge
SCK
Idle
State
SS High
Between
Characters?
CPHA
CPOL
1
1
0
1
Rising
Falling
Falling
Rising
Low
No
No
High
SPI Functional Description
When a master transmits to a slave device via the MOSI signal, the slave device responds
by sending data to the master via the master’s MISO signal. The result is a full-duplex
transmission, with both data out and data in synchronized with the same clock signal. The
byte transmitted is replaced by the byte received, eliminating the need for separate trans-
mit-empty and receive-full status bits. A single status bit, SPIF, is used to signify that the
I/O operation is complete. See the SPI Status Register section on page 206.
The SPI is double-buffered during reads, but not during writes. If a write is performed dur-
ing data transfer, the transfer occurs uninterrupted, and the write is unsuccessful. This con-
dition causes the write collision (WCOL) status bit in the SPI_SR Register to be set. After
a data byte is shifted, the SPI flag of the SPI_SR Register is set to 1.
In SPI MASTER Mode, the SCK pin functions as an output. It idles High or Low depend-
ing on the CPOL bit in the SPI_CTL Register until data is written to the shift register. Data
transfer is initiated by writing to the transmit shift register, SPI_TSR. Eight clocks are then
generated to shift the eight bits of transmit data out via the MOSI pin while shifting in
eight bits of data via the MISO pin. After transfer, the SCK signal becomes idle.
In SPI SLAVE Mode, the start logic receives a logic Low from the SS pin and a clock
input at the SCK pin; as a result, the slave is synchronized to the master. Data from the
master is received serially from the slave MOSI signal and is loaded into the 8-bit shift
register. After the 8-bit shift register is loaded, its data is parallel-transferred to the read
buffer. During a write cycle, data is written into the shift register. Next, the slave waits for
the SPI master to initiate a data transfer, supply a clock signal, and shift the data out on the
slave's MISO signal.
If the CPHA bit in the SPI_CTL Register is 0, a transfer begins when the SS pin signal
goes Low. The transfer ends when SS goes High after eight clock cycles on SCK. When
the CPHA bit is set to 1, a transfer begins the first time SCK becomes active while SS is
Low. The transfer ends when the SPI flag is set to 1.
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SPI Flags
This section describes the SPI Mode Fault and Write Collision flags.
Mode Fault
The Mode Fault flag (MODF) indicates that there is a multimaster conflict in the system
control. The MODF bit is normally cleared to 0 and is only set to 1 when the master
device’s SS pin is pulled Low. When a mode fault is detected, the following sequence
occurs:
1. The MODF flag (SPI_SR[4]) is set to 1.
2. The SPI device is disabled by clearing the SPI_EN bit (SPI_CTL[5]) to 0.
3. The MASTER_EN bit (SPI_CTL[4]) is cleared to 0, forcing the device into SLAVE
Mode.
4. If the SPI interrupt is enabled by setting IRQ_EN (SPI_CTL[7]) High, an SPI inter-
rupt is generated.
Clearing the Mode Fault flag is performed by reading the SPI Status Register. The other
SPI control bits (SPI_EN and MASTER_EN) must be restored to their original states by
user software after the Mode Fault Flag is cleared to 0.
Write Collision
The write collision flag, WCOL (SPI_SR[5]), is set to 1 when an attempt is made to write
to the SPI Transmit Shift Register (SPI_TSR) while data transfer occurs. Clearing the
WCOL bit is performed by reading SPI_SR with the WCOL bit set to 1.
SPI Baud Rate Generator
The SPI Baud Rate Generator (BRG) creates a lower frequency clock from the high-fre-
quency system clock. The BRG output is used as the clock source by the SPI.
Baud Rate Generator Functional Description
The SPI BRG consists of a 16-bit downcounter, two 8-bit registers, and associated decod-
ing logic. The BRG’s initial value is defined by the two BRG Divisor Latch registers
{SPI_BRG_H, SPI_BRG_L}. At the rising edge of each system clock, the BRG decre-
ments until it reaches the value 0001h. On the next system clock rising edge, the BRG
reloads the initial value from {SPI_BRG_H, SPI_BRG_L) and outputs a pulse to indicate
the end of the count.
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The SPI Data Rate is calculated using the following equation:
System Clock Frequency
SPI Data Rate (bits/s)
=
2 x SPI Baud Rate Generator Divisor
Upon RESET, the 16-bit BRG divisor value resets to 0002h. When the SPI is operating as
a Master, the BRG divisor value must be set to a value of 0003hor greater. When the SPI
is operating as a Slave, the BRG divisor value must be set to a value of 0004hor greater.
A software write to either the Low- or High-byte registers for the BRG Divisor Latch
causes both the low and high bytes to load into the BRG counter, and causes the count to
restart.
Data Transfer Procedure with SPI Configured as a Master
The following list describes the procedure for transferring data from a master SPI device
to a slave SPI device.
1. Load the SPI BRG Registers, SPI_BRG_H and SPI_BRG_L. The external device
must deassert the SS pin if currently asserted.
2. Load the SPI Control Register, SPI_CTL.
3. Assert the ENABLE pin of the slave device using a GPIO pin.
4. Load the SPI Transmit Shift Register, SPI_TSR.
5. When the SPI data transfer is complete, deassert the ENABLE pin of the slave device.
Data Transfer Procedure with SPI Configured as a Slave
The following list describes the procedure for transferring data from a slave SPI device to
a master SPI device.
1. Load the SPI BRG Registers, SPI_BRG_H and SPI_BRG_L.
2. Load the SPI Transmit Shift Register, SPI_TSR. This load cannot occur while the SPI
slave is currently receiving data.
3. Wait for the external SPI Master device to initiate the data transfer by asserting SS.
SPI Registers
There are six registers in the Serial Peripheral Interface that provide control, status, and
data storage functions. The SPI registers are described in the following paragraphs.
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SPI Baud Rate Generator Low Byte and High Byte Registers
These registers hold the low and high bytes of the 16-bit divisor count loaded by the CPU
for baud rate generation. The 16-bit clock divisor value is returned by {SPI_BRG_H,
SPI_BRG_L}. Upon RESET, the 16-bit BRG divisor value resets to 0002h. When config-
ured as a Master, the 16-bit divisor value must be between 0003hand FFFFh, inclusive.
When configured as a Slave, the 16-bit divisor value must be between 0004hand FFFFh,
inclusive.
A write to either the Low- or High-byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter and a restart of the count. See Tables 112 and
113.
Table 112. SPI Baud Rate Generator Low Byte Register (SPI_BRG_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
SPI_BRG_L
0
0
0
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
00B8h
Note: R/W = read/write.
Bit
Description
BRG Low Byte
[7:0]
SPI_BRG_L
00h–FFh: These bits represent the low byte of the 16-bit BRG divider value. The com-
plete BRG divisor value is returned by {SPI_BRG_H, SPI_BRG_L}.
Table 113. SPI Baud Rate Generator High Byte Register (SPI_BRG_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
SPI_BRG_H
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
00B9h
Note: R/W = read/write.
Bit
Description
BRG High Byte
[7:0]
SPI_BRG_H
00h–FFh: These bits represent the high byte of the 16-bit BRG divider value. The com-
plete BRG divisor value is returned by {SPI_BRG_H, SPI_BRG_L}.
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SPI Control Register
This register is used to control and setup the serial peripheral interface. The SPI must be
disabled prior to making any changes to CPHA or CPOL. See Table 114.
Table 114. SPI Control Register (SPI_CTL)
Bit
7
6
5
4
3
2
1
0
Field
IRQ_EN Reserved SPI_EN MASTER_ CPOL
EN
CPHA
Reserved
Reset
R/W
0
0
0
0
0
1
0
0
R/W
R
R/W
R/W
R/W
R/W
R
R
Address
00BAh
Note: R = read only; R/W = read/write.
Bit
Description
[7]
IRQ_EN
SPI Interrupt Request Enable
0: SPI system interrupt is disabled.
1: SPI system interrupt is enabled.
[6]
Reserved
This bit is reserved and must be programmed to 0.
[5]
SPI_EN
Serial Peripheral Interface Enable
0: SPI is disabled.
1: SPI is enabled.
[4]
SPI Mode Enable
MASTER_EN 0: When enabled, the SPI operates as a slave.
1: When enabled, the SPI operates as a master.
[3]
CPOL
Clock Polarity
0: Master SCK pin idles in a Low (0) state.
1: Master SCK pin idles in a High (1) state.
[2]
CPHA
Clock Phase
0: SS must go High after transfer of every byte of data.
1: SS remains Low to transfer any number of data bytes.
[1:0]
Reserved
These bits are reserved and must be programmed to 00.
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SPI Status Register
The read-only SPI Status Register returns the status of data transmitted using the serial
peripheral interface. Reading the SPI_SR Register clears Bits 7, 6, and 4 to a logic 0. See
Table 115.
Table 115. SPI Status Register (SPI_SR)
Bit
7
SPIF
0
6
5
4
3
2
1
0
Field
Reset
R/W
WCOL Reserved MODF
Reserved
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Address
00BBh
Note: R = read only.
Bit
Description
SPI Flag
0: SPI data transfer is not finished.
[7]
SPIF
1: SPI data transfer is finished. If enabled, an interrupt is generated. This bit flag is
cleared to 0 by a read of the SPI_SR Register.
[6]
WCOL
SPI Write Collision
0: An SPI write collision is not detected.
1: An SPI write collision is detected. This bit Flag is cleared to 0 by a read of the SPI_SR
registers.
[5]
Reserved
This bit is reserved and must be programmed to 0.
[4]
MODF
SPI Mode Fault
0: A mode fault (multimaster conflict) is not detected.
1: A mode fault (multimaster conflict) is detected. This bit Flag is cleared to 0 by a read of
the SPI_SR Register.
[3:0]
Reserved
These bits are reserved and must be programmed to 0000.
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SPI Transmit Shift Register
The SPI Transmit Shift Register (SPI_TSR) is used by the SPI master to transmit data over
an SPI serial bus to a slave device. A write to the SPI_TSR Register places data directly
into the shift register for transmission. A write to this register within an SPI device config-
ured as a master initiates transmission of the byte of the data loaded into the register. At
the completion of transmitting a byte of data, the SPI Flag (SPI_SR[7]) is set to 1 in both
the master and slave devices.
The write-only SPI Transmit Shift Register shares the same address space as the read-only
SPI Receive Buffer Register. See Table 116.
Table 116. SPI Transmit Shift Register (SPI_TSR)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
Tx_DATA
U
U
U
U
U
U
U
U
W
W
W
W
W
W
W
W
Address
00BCh
Note: U = undefined; W = write only.
Bit
Description
[7:0]
Tx_DATA
SPI Transmit Data
00h–FFh: SPI transmit data.
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SPI Receive Buffer Register
The SPI Receive Buffer Register (SPI_RBR), shown in Table 117, is used by the SPI slave
to receive data from the serial bus. The SPIF bit must be cleared prior to a second transfer
of data from the shift register; otherwise, an overrun condition exists. In the event of an
overrun, the byte that causes the overrun is lost.
The read-only SPI Receive Buffer Register shares the same address space as the write-
only SPI Transmit Shift Register.
Table 117. SPI Receive Buffer Register (SPI_RBR)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
Rx_DATA
U
R
U
R
U
R
U
R
U
R
U
R
U
R
U
R
Address
00BCh
Note: U = undefined; R = read only.
Bit
Description
00h–FFh: SPI received data.
[7:0]
Rx_DATA
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2
I C Serial I/O Interface
The Inter-Integrated Circuit (I2C) serial I/O bus is a two-wire communication interface
that operates in the following four modes:
•
•
•
•
MASTER TRANSMIT
MASTER RECEIVE
SLAVE TRANSMIT
SLAVE RECEIVE
The I2C interface consists of a Serial Clock (SCL) and Serial Data (SDA). Both SCL and
SDA are bidirectional lines connected to a positive supply voltage via an external pull-up
resistor. When the bus is free, both lines are High. The output stages of devices connected
to the bus must be configured as open-drain outputs. Data on the I2C bus are transferred at
a rate of up to 100kbps in STANDARD Mode, or up to 400 kbps in FAST Mode. One
clock pulse is generated for each data bit transferred.
Clocking Overview
If another device on the I2C bus drives the clock line when the I2C is in MASTER Mode,
the I2C synchronizes its clock to the I2C bus clock. The High period of the clock is deter-
mined by the device that generates the shortest High clock period. The Low period of the
clock is determined by the device that generates the longest Low clock period.
The Low period of the clock is stretched by a slave to slow down the bus master. The Low
period is also stretched for handshaking purposes. This result is accomplished after each
bit transfer or each byte transfer. The I2C stretches the clock after each byte transfer until
the IFLG bit in the I2C_CTL Register is cleared to 0.
Bus Arbitration Overview
In MASTER Mode, the I2C checks that each transmitted logic 1 appears on the I2C bus as
a logic 1. If another device on the bus overrules and pulls the SDA signal Low, arbitration
is lost. If arbitration is lost during the transmission of a data byte or a Not Acknowledge
(NACK) bit, the I2C returns to an idle state. If arbitration is lost during the transmission of
an address, the I2C switches to SLAVE Mode so that it recognizes its own slave address or
the general call address.
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Data Validity
The data on the SDA line must be stable during the High period of the clock. The High or
Low state of the data line changes only when the clock signal on the SCL line is Low, as
shown in Figure 43.
SDA Signal
SCL Signal
Data Line
Stable
Change of
Data Allowed
Data Valid
2
Figure 43. I C Clock and Data Relationship
Start and Stop Conditions
Within the I2C bus protocol, unique situations arise which are defined as start and stop
conditions. Figure 44 shows a High-to-Low transition on the SDA line while SCL is High,
indicating a start condition. A Low-to-High transition on the SDA line while SCL is High
defines a stop condition.
Start and stop conditions are always generated by the master. The bus is considered to be
busy after a start condition. The bus is considered to be free for a defined time after a stop
condition.
SDA Signal
SCL Signal
S
P
START Condition
STOP Condition
2
Figure 44. Start and Stop Conditions In I C Protocol
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Transferring Data
2
This section describes data byte format and how data is transferred via the I C Serial I/O interface.
Byte Format
Every character transferred on the SDA line must be a single 8-bit byte. The number of
bytes that is transmitted per transfer is unrestricted. Each byte must be followed by an
Acknowledge (ACK). Data is transferred with the most-significant bit (msb) first.
Figure 45 shows a receiver that holds the SCL line Low to force the transmitter into a wait
state. Data transfer then continues when the receiver is ready for another byte of data and
releases SCL.
SDA Signal
SCL Signal
MSB
1
Acknowledge from
Receiver
Acknowledge from
Receiver
2
8
9
1
9
S
P
ACK
START Condition
STOP Condition
Clock Line Held Low By Receiver
2
Figure 45. I C Frame Structure
Acknowledge
Data transfer with an ACK function is obligatory. The ACK-related clock pulse is gener-
ated by the master. The transmitter releases the SDA line (High) during the ACK clock
pulse. The receiver must pull down the SDA line during the ACK clock pulse so that it
remains stable (Low) during the High period of this clock pulse. See Figure 46.
Data Output
by Transmitter
MSB
Data Output
by Receiver
1
1
S
SCL Signal
from Master
2
8
9
START Condition
Clock Pulse for Acknowledge
2
Figure 46. I C Acknowledge
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A receiver that is addressed is obliged to generate an ACK after each byte is received.
When a slave receiver does not acknowledge the slave address (for example, unable to
receive because it is performing some real-time function), the data line must be left High
by the slave. The master then generates a stop condition to abort the transfer.
If a slave receiver acknowledges the slave address, but cannot receive any more data
bytes, the master must abort the transfer. The abort is indicated by the slave generating the
Not Acknowledge (NACK) on the first byte to follow. The slave leaves the data line High
and the master generates the stop condition.
If a master receiver is involved in a transfer, it must signal the end of the data stream to the
slave transmitter by not generating an ACK on the final byte that is clocked out of the
slave. The slave transmitter must release the data line to allow the master to generate a
stop or a repeated start condition.
Clock Synchronization
All masters generate their own clocks on the SCL line to transfer messages on the I2C bus.
Data is only valid during the High period of each clock.
Clock synchronization is performed using the wired AND connection of the I2C interfaces
to the SCL line, meaning that a High-to-Low transition on the SCL line causes the relevant
devices to start counting from their Low period. When a device clock goes Low, it holds
the SCL line in that state until the clock High state is reached. See Figure 47. The Low-to-
High transition of this clock, however, cannot change the state of the SCL line if another
clock is still within its Low period. The SCL line is held Low by the device with the lon-
gest Low period. Devices with shorter Low periods enter a High wait state during this
time.
When all devices count off the Low period, the clock line is released and goes High. There
is no difference between the device clocks and the state of the SCL line; all of the devices
start counting the High periods. The first device to complete its High period again pulls
the SCL line Low. In this way, a synchronized SCL clock is generated with its Low period
determined by the device with the longest clock Low period, and its High period deter-
mined by the device with the shortest clock High period.
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Wait
State
Start Counting
High Period
CLK1 Signal
Counter
Reset
CLK2 Signal
SCL Signal
2
Figure 47. Clock Synchronization In I C Protocol
Arbitration
Any master initiates a transfer if the bus is free. As a result, multiple masters each gener-
ates a start condition if the bus is free within a minimum period. If multiple masters gener-
ate a start condition, a start is defined for the bus. However, arbitration defines which
MASTER controls the bus. Arbitration takes place on the SDA line. As mentioned, start
conditions are initiated only while the SCL line is held High. If during this period, a mas-
ter (M1) initiates a High-to-Low transition – that is, a start condition – while a second
master (M2) transmits a Low signal on the line, then the first master, M1, cannot take con-
trol of the bus. As a result, the data output stage for M1 is disabled.
Arbitration continues for many bits. Its first stage is comparison of the address bits. If the
masters are each trying to address the same device, arbitration continues with a compari-
son of the data. Because address and data information about the I2C bus is used for arbitra-
tion, no information is lost during this process. A master that loses the arbitration
generates clock pulses until the end of the byte in which it loses the arbitration.
If a master also incorporates a slave function and it loses arbitration during the addressing
stage, it is possible that the winning master is trying to address it. The losing master must
switch over immediately to its slave receiver mode. Figure 47 shows the arbitration proce-
dure for two masters. Of course, more masters can be involved, depending on how many
masters are connected to the bus. The moment there is a difference between the internal
data level of the master generating DATA 1 and the actual level on the SDA line, its data
output is switched off, which means that a High output level is then connected to the bus.
As a result, the data transfer initiated by the winning master is not affected. Because con-
trol of the I2C bus is decided solely on the address and data sent by competing masters,
there is no central master, nor any order of priority on the bus.
Special attention must be paid if, during a serial transfer, the arbitration procedure is still
in progress at the moment when a repeated start condition or a stop condition is transmit-
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ted to the I2C bus. If it is possible for such a situation to occur, the masters involved must
send this repeated start condition or stop condition at the same position in the format
frame. In other words, arbitration is not allowed between:
•
•
•
A repeated start condition and a data bit
A stop condition and a data bit
A repeated start condition and a stop condition
Clock Synchronization for Handshake
The clock-synchronizing mechanism functions as a handshake, enabling receivers to cope
with fast data transfers, on either a byte or a bit level. The byte level allows a device to
receive a byte of data at a fast rate, but allows the device more time to store the received
byte or to prepare another byte for transmission. Slaves hold the SCL line Low after recep-
tion and acknowledge the byte, forcing the master into a wait state until the slave is ready
for the next byte transfer in a handshake procedure.
Operating Modes
This section describes the Master Transmit, Master Receive, Slave Transmit and Slave
Receive modes of operation.
Master Transmit
In MASTER TRANSMIT Mode, the I2C transmits a number of bytes to a slave receiver.
Enter MASTER TRANSMIT Mode by setting the STA bit in the I2C_CTL Register to 1.
The I2C then tests the I2C bus and transmits a start condition when the bus is free. When a
start condition is transmitted, the IFLG bit is 1 and the status code in the I2C_SR Register
is 08h. Before this interrupt is serviced, the I2C_DR Register must be loaded with either a
7-bit slave address or the first part of a 10-bit slave address, with the lsb cleared to 0 to
specify TRANSMIT Mode. The IFLG bit must now be cleared to 0 to prompt the transfer
to continue.
After the 7-bit slave address (or the first part of a 10-bit address) plus the write bit are
transmitted, the IFLG is set again. A number of status codes are possible in the I2C_SR
Register. See Table 118.
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2
Table 118. I C Master Transmit Status Codes
2
2
Code
I C State
ASSP Response
Next I C Action
18h
Addr+W transmitted
ACK received
For a 7-bit address: write byte Transmit data byte, receive ACK
to DATA, clear IFLG
1
Or set STA, clear IFLG
Or set STP, clear IFLG
Transmit repeated start
Transmit stop
Or set STA & STP, clear IFLG Transmit stop, then start
For a 10-bit address: write
extended address byte to data,
clear IFLG
Transmit extended address byte
20h
38h
Addr+W transmitted,
ACK not received
Same as code 18h
Same as code 18h
Arbitration lost
Clear IFLG
Return to idle
Or set STA, clear IFLG
Transmit start when bus is free
Receive data byte, transmit NACK
Receive data byte, transmit ACK
2
68h
78h
Arbitration lost +W
received; ACK trans-
mitted
Clear IFLG, AAK = 0
Or clear IFLG, AAK = 1
Same as code 68h
Arbitration lost, Gen-
eral call address
received, ACK trans-
mitted
Same as code 68h
B0h
Arbitration lost, SLA+R Write byte to DATA, clear IFLG, Transmit last byte, receive ACK
received; ACK
transmitted
clear AAK = 0
3
Or write byte to DATA, clear
IFLG, set AAK = 1
Transmit data byte, receive ACK
Notes:
1. W is defined as the write bit; that is, the lsb is cleared to 0.
2. AAK is an I2C control bit that identifies which ACK signal to transmit.
3. R is defined as the read bit; that is, the lsb is set to 1.
If 10-bit addressing is used, the status code is 18hor 20hafter the first part of a 10-bit
address, plus the write bit, are successfully transmitted.
After this interrupt is serviced and the second part of the 10-bit address is transmitted, the
I2C_SR Register contains one of the codes listed in Table 119.
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2
Table 119. I C 10-Bit Master Transmit Status Codes
2
2
Code
I C State
ASSP Response
Next I C Action
38h
Arbitration lost
Clear IFLG
Return to idle
Or set STA, clear IFLG
Clear IFLG, clear AAK = 0
Transmit start when bus free
Receive data byte, transmit NACK
Receive data byte, transmit ACK
2
68h
B0h
Arbitration lost,
SLA+W received,
ACK transmitted
Or clear IFLG, set AAK = 1
1
Arbitration lost,
SLA+R received,
ACK transmitted
Write byte to DATA, clear IFLG, Transmit last byte, receive ACK
clear AAK = 0
3
Or write byte to DATA,
Transmit data byte, receive ACK
clear IFLG, set AAK = 1
D0h
Second address byte Write byte to data, clear IFLG Transmit data byte, receive ACK
+ W transmitted,
ACK received
Or set STA, clear IFLG
Or set STP, clear IFLG
Transmit repeated start
Transmit stop
Or set STA & STP, clear IFLG Transmit stop, then start
D8h
Second address byte Same as code D0h
+ W transmitted,
Same as code D0h
ACK not received
Notes:
1. W is defined as the write bit; that is, the lsb is cleared to 0.
2. AAK is an I2C control bit that identifies which ACK signal to transmit.
3. R is defined as the read bit; that is, the lsb is set to 1.
If a repeated start condition is transmitted, the status code is 10hinstead of 08h.
After each data byte is transmitted, the IFLG is set to 1 and one of the status codes listed in
Table 120 is loaded into the I2C_SR Register.
2
Table 120. I C Master Transmit Status Codes For Data Bytes
2
2
Code
I C State
ASSP Response
Next I C Action
28h
Data byte transmitted, Write byte to data, clear IFLG Transmit data byte, receive ACK
ACK received
Or set STA, clear IFLG
Or set STP, clear IFLG
Transmit repeated start
Transmit stop
Or set STA and STP, clear IFLG Transmit start then stop
30h
38h
Data byte transmitted, Same as code 28h
ACK not received
Same as code 28h
Arbitration lost
Clear IFLG
Return to idle
Or set STA, clear IFLG
Transmit start when bus free
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When all bytes are transmitted, the ASSP must write a 1 to the STP bit in the I2C_CTL
Register. The I2C then transmits a stop condition, clears the STP bit and returns to an idle
state.
Master Receive
In MASTER RECEIVE Mode, the I2C receives a number of bytes from a slave transmit-
ter.
After the start condition is transmitted, the IFLG bit is 1 and the status code 08his loaded
into the I2C_SR Register. The I2C_DR Register must be loaded with the slave address (or
the first part of a 10-bit slave address), with the lsb set to 1 to signify a read. The IFLG bit
must be cleared to 0 as a prompt for the transfer to continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the read bit are
transmitted, the IFLG bit is set and one of the status codes listed in Table 121 is loaded
into the I2C_SR Register.
2
Table 121. I C Master Receive Status Codes
2
2
Code
I C State
ASSP Response
Next I C Action
40h
Addr + R transmitted, For a 7-bit address,
Receive data byte, transmit NACK
1
ACK received
clear IFLG, AAK = 0
Or clear IFLG, AAK = 1
Receive data byte, transmit ACK
Transmit extended address byte
For a 10-bit address write
extended address byte to data,
clear IFLG
48h
Addr + R transmitted, For a 7-bit address: Set STA,
Transmit repeated start
Transmit stop
2
ACK not received
clear IFLG
Or set STP, clear IFLG
Or set STA and STP, clear IFLG Transmit stop, then start
For a 10-bit address: write
extended address byte to data,
clear IFLG
Transmit extended address byte
38h
68h
Arbitration lost
Clear IFLG
Return to idle
Or set STA, clear IFLG
Clear IFLG, clear AAK = 0
Or clear IFLG, set AAK = 1
Transmit start when bus is free
Receive data byte, transmit NACK
Receive data byte, transmit ACK
Arbitration lost,
SLA+W received,
ACK transmitted
3
Notes:
1. AAK is an I2C control bit that identifies which ACK signal to transmit.
2. R is defined as the read bit; that is, the lsb is set to 1.
3. W is defined as the write bit; that is, the lsb is cleared to 0.
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2
Table 121. I C Master Receive Status Codes
2
2
Code
I C State
ASSP Response
Next I C Action
78h
Arbitration lost, gen-
eral call addr received,
ACK transmitted
Same as code 68h
Same as code 68h
B0h
Arbitration lost, SLA+R Write byte to DATA, clear IFLG, Transmit last byte, receive ACK
received, ACK trans-
mitted
clear AAK = 0
Or write byte to DATA, clear
IFLG, set AAK = 1
Transmit data byte, receive ACK
Notes:
1. AAK is an I2C control bit that identifies which ACK signal to transmit.
2. R is defined as the read bit; that is, the lsb is set to 1.
3. W is defined as the write bit; that is, the lsb is cleared to 0.
If 10-bit addressing is being used, the slave is first addressed using the full 10-bit address,
plus the write bit. The master then issues a restart followed by the first part of the 10-bit
address again, this time with the read bit. The status code then becomes 40hor 48h. It is
the responsibility of the slave to remember that it had been selected prior to the restart.
If a repeated start condition is received, the status code is 10hinstead of 08h.
After each data byte is received, the IFLG is set to 1 and one of the status codes listed in
Table 122 is loaded into the I2C_SR Register.
2
Table 122. I C Master Receive Status Codes For Data Bytes
2
2
Code
I C State
ASSP Response
Next I C Action
50h
Data byte received,
ACK transmitted
Read data, clear IFLG, clear
AAK = 0*
Receive data byte, transmit NACK
Or read data, clear IFLG, set
AAK = 1
Receive data byte, transmit ACK
58h
Data byte received,
NACK transmitted
Read data, set STA, clear IFLG Transmit repeated start
Or read data, set STP, clear
IFLG
Transmit stop
Or read data, set STA and STP, Transmit stop, then start
clear IFLG
38h
Arbitration lost in
NACK bit
Same as master transmit
Same as master transmit
Note: *AAK is an I2C control bit that identifies which ACK signal to transmit.
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When all bytes are received, a NACK must be sent, then the ASSP must write 1 to the STP
bit in the I2C_CTL Register. The I2C then transmits a stop condition, clears the STP bit
and returns to an idle state.
Slave Transmit
In SLAVE TRANSMIT Mode, a number of bytes are transmitted to a master receiver.
The I2C enters SLAVE TRANSMIT Mode when it receives its own slave address and a
read bit after a start condition. The I2C then transmits an ACK bit (if the AAK bit is set to
1); it then sets the IFLG bit in the I2C_CTL Register. As a result, the I2C_SR Register con-
tains the status code A8h.
When I2C contains a 10-bit slave address (signified by the address range F0h–F7hin the
Note:
I2C_SAR Register), it transmits an ACK when the first address byte is received after a
restart. An interrupt is generated and IFLG is set to 1; however, the status does not change.
No second address byte is sent by the master. It is up to the slave to remember it had been
selected prior to the restart.
I2C goes from MASTER Mode to SLAVE TRANSMIT Mode when arbitration is lost
during the transmission of an address, and the slave address and read bit are received. This
action is represented by the status code B0hin the I2C_SR Register.
The data byte to be transmitted is loaded into the I2C_DR Register and the IFLG bit is
cleared to 0. After the I2C transmits the byte and receives an ACK, the IFLG bit is set to 1
and the I2C_SR Register contains B8h. When the final byte to be transmitted is loaded into
the I2C_DR Register, the AAK bit is cleared when the IFLG is cleared to 0. After the final
byte is transmitted, the IFLG is set and the I2C_SR Register contains C8hand the I2C
returns to an idle state. The AAK bit must be set to 1 before reentering SLAVE Mode.
If no ACK is received after transmitting a byte, the IFLG is set and the I2C_SR Register
contains C0h. The I2C then returns to an idle state.
If a stop condition is detected after an ACK bit, the I2C returns to an idle state.
Slave Receive
In SLAVE RECEIVE Mode, a number of data bytes are received from a master transmit-
ter. The I2C enters SLAVE RECEIVE Mode when it receives its own slave address and a
write bit (lsb = 0) after a start condition. The I2C transmits an ACK bit and sets the IFLG
bit in the I2C_CTL Register and the I2C_SR Register contains the status code 60h. The
I2C also enters SLAVE RECEIVE Mode when it receives the general call address 00h(if
the GCE bit in the I2C_SAR Register is set). The status code is then 70h.
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Note: When the I2C contains a 10-bit slave address (signified by F0h–F7hin the I2C_SAR Reg-
ister), it transmits an acknowledge after the first address byte is received but no interrupt is
generated. IFLG is not set and the status does not change. The I2C generates an interrupt
only after the second address byte is received. The I2C sets the IFLG bit and loads the sta-
tus code as described above.
I2C goes from MASTER Mode to SLAVE RECEIVE Mode when arbitration is lost dur-
ing the transmission of an address, and the slave address and write bit (or the general call
address if the CGE bit in the I2C_SAR Register is set to 1) are received. The status code in
the I2C_SR Register is 68hif the slave address is received or 78hif the general call
address is received. The IFLG bit must be cleared to 0 to allow data transfer to continue.
If the AAK bit in the I2C_CTL Register is set to 1 then an ACK bit (Low level on SDA) is
transmitted and the IFLG bit is set after each byte is received. The I2C_SR Register con-
tains the two status codes 80hor 90hif SLAVE RECEIVE Mode is entered with the gen-
eral call address. The received data byte are read from the I2C_DR Register and the IFLG
bit must be cleared to allow the transfer to continue. If a stop condition or a repeated start
condition is detected after the acknowledge bit, the IFLG bit is set and the I2C_SR Regis-
ter contains status code A0h.
If the AAK bit is cleared to 0 during a transfer, the I2C transmits a NACK bit (High level
on SDA) after the next byte is received, and sets the IFLG bit to 1. The I2C_SR Register
contains the two status codes 88hor 98hif SLAVE RECEIVE Mode is entered with the
general call address. The I2C returns to an idle state when the IFLG bit is cleared to 0.
2
I C Registers
The section that follows describes each of the eZ80F91 ASSP’s Inter-Integrated Circuit
(I2C) registers.
Addressing
The CPU interface provides access to seven 8-bit registers: four read/write registers, one
read-only register and two write-only registers, as indicated in Table 123.
2
Table 123. I C Register Descriptions
Register
I2C_SAR
I2C_XSAR
I2C_DR
Description
Slave address register.
Extended slave address register.
Data byte register.
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Table 123. I C Register Descriptions
Register
I2C_CTL
I2C_SR
Description
Control register.
Status register (read only).
Clock Control register (write only).
Software reset register (write only).
I2C_CCR
I2C_SRR
Resetting the I2C Registers
This section describes the hardware and software reset operations of the I2C Serial I/O
interface.
Hardware Reset
When the I2C is reset by a hardware reset of the eZ80F91 device, the I2C_SAR,
I2C_XSAR, I2C_DR, and I2C_CTL registers are cleared to 00h; while the I2C_SR Regis-
ter is set to F8h.
Software Reset
Perform a software reset by writing any value to the I2C Software Reset Register
(I2C_SRR). A software reset clears the STP, STA, and IFLG bits of the I2C_CTL Register
to 0 and sets the I2C back to an idle state.
I2C Slave Address Register
The I2C_SAR Register provides the 7-bit address of the I2C when in SLAVE Mode and
allows 10-bit addressing in conjunction with the I2C_XSAR Register. I2C_SAR[7:1] =
SLA[6:0] is the 7-bit address of the I2C when in 7-bit SLAVE Mode. When the I2C
receives this address after a start condition, it enters SLAVE Mode. I2C_SAR[7] corre-
sponds to the first bit received from the I2C bus.
When the register receives an address starting with F7hto F0h(I2C_SAR[7:3] = 11110b),
the I2C recognizes that a 10-bit slave addressing mode is being selected. The I2C sends an
ACK after receiving the I2C_SAR byte (the device does not generate an interrupt at this
point). After the next byte of the address (I2C_XSAR) is received, the I2C generates an
interrupt and enters SLAVE Mode.Then I2C_SAR[2:1] are used as the upper 2 bits for the
10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}. See Table 124.
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2
Table 124. I C Slave Address Register (I2C_SAR)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
SLA
0
GCE
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
00C8h
Note: R/W = read/write.
Bit
Description
Slave Address
[7:1]
2
SLA
00h–7Fh: 7-bit slave address or upper 2 bits of address (I C_SAR[2:1]) when operating
in 10-bit mode.
0
GCE
General Call Address Enable
2
0: I C not enabled to recognize the General Call Address.
2
1: I C enabled to recognize the General Call Address.
I2C Extended Slave Address Register
The I2C_XSAR Register is used in conjunction with the I2C_SAR Register to provide 10-
bit addressing of the I2C when in SLAVE Mode. The I2C_SAR value forms the lower 8
bits of the 10-bit slave address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}.
When the register receives an address starting with F7hto F0h(I2C_SAR[7:3] = 11110b),
the I2C recognizes that a 10-bit slave addressing mode is being selected. The I2C sends an
ACK after receiving the I2C_XSAR byte (the device does not generate an interrupt at this
point). After the next byte of the address (I2C_XSAR) is received, the I2C generates an
interrupt and enters SLAVE Mode.Then I2C_SAR[2:1] are used as the upper 2 bits for the
10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}. See Table 125.
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2
Table 125. I C Extended Slave Address Register (I2C_XSAR)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
SLAX
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
00C9h
Note: R/W = read/write.
Bit
Description
Extended Slave Address
[7:0]
SLAX
00h–FFh: Least-significant 8 bits of the 10-bit extended slave address
I2C Data Register
This register contains the data byte/slave address to be transmitted or the data byte just
received. In TRANSMIT Mode, the most-significant bit of the byte is transmitted first. In
RECEIVE Mode, the first bit received is placed in the most-significant bit of the register.
After each byte is transmitted, the I2C_DR Register contains the byte that is present on the
bus in case a lost arbitration event occurs. See Table 126.
2
Table 126. I C Data Register (I2C_DR)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
DATA
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
00CAh
Note: R/W = read/write.
Bit
Description
2
[7:0]
I C Data
2
DATA
00h–FFh: I C data byte
I2C Control Register
The I2C_CTL Register is a control register that is used to control the interrupts and the
master slave relationships on the I2C bus. When the Interrupt Enable bit (IEN) is set to 1,
the interrupt line goes High when the IFLG is set to 1. When IEN is cleared to 0, the inter-
rupt line always remains Low.
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When the Bus Enable bit (ENAB) is set to 0, the I2C bus inputs SCLx and SDAx are
ignored and the I2C module does not respond to any address on the bus. When ENAB is
set to 1, the I2C responds to calls to its slave address and to the general call address if the
GCE bit (I2C_SAR[0]) is set to 1.
When the Master Mode Start bit (STA) is set to 1, the I2C enters MASTER Mode and
sends a start condition on the bus when the bus is free. If the STA bit is set to 1 when the
I2C module is already in MASTER Mode and one or more bytes are transmitted, then a
repeated start condition is sent. If the STA bit is set to 1 when the I2C block is being
accessed in SLAVE Mode, the I2C completes the data transfer in SLAVE Mode and then
enters MASTER Mode when the bus is released. The STA bit is automatically cleared
after a start condition is set. Writing 0 to the STA bit produces no effect.
If the Master Mode Stop bit (STP) is set to 1 in MASTER Mode, a stop condition is trans-
mitted on the I2C bus. If the STP bit is set to 1 in SLAVE Mode, the I2C module operates
as if a stop condition is received, but no stop condition is transmitted. If both STA and STP
bits are set, the I2C block first transmits the stop condition (if in MASTER Mode), then
transmits the start condition. The STP bit is cleared to 0 automatically. Writing a 0 to this
bit produces no effect.
The I2C Interrupt Flag (IFLG) is set to 1 automatically when any of 30 of the possible 31
I2C states is entered. The only state that does not set the IFLG bit is state F8h. If IFLG is
set to 1 and the IEN bit is also set, an interrupt is generated. When IFLG is set by the I2C,
the Low period of the I2C bus clock line is stretched and the data transfer is suspended.
When a 0 is written to IFLG, the interrupt is cleared and the I2C clock line is released.
When the I2C Acknowledge bit (AAK) is set to 1, an acknowledge is sent during the
acknowledge clock pulse on the I2C bus if:
•
•
•
Either the whole of a 7-bit slave address or the first or second byte of a 10-bit slave ad-
dress is received
The general call address is received and the General Call Enable bit in I2C_SAR is set
to 1
A data byte is received while in MASTER or SLAVE modes
When AAK is cleared to 0, a NACK is sent when a data byte is received in MASTER or
SLAVE Mode. If AAK is cleared to 0 in SLAVE TRANSMIT Mode, the byte in the
I2C_DR Register is assumed to be the final byte. After this byte is transmitted, the I2C
block enters the C8hstate, then returns to an idle state. The I2C module does not respond
to its slave address unless AAK is set to 1. See Table 127.
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2
Table 127. I C Control Register (I2C_CTL)
Bit
7
IEN
0
6
ENAB
0
5
4
3
2
1
0
Field
Reset
R/W
STA
0
STP
0
IFLG
0
AAK
0
Reserved
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Address
00CBh
Note: R/W = read/write; R = read only.
Bit
Description
[7]
IEN
Interrupt Enable
2
0: I C interrupt is disabled.
2
1: I C interrupt is enabled.
2
[6]
ENAB
I C Bus Enable
2
0: The I C bus (SCL/SDA) is disabled and all inputs are ignored.
1: The I C bus (SCL/SDA) is enabled.
2
[5]
STA
Start Condition
0: MASTER Mode start condition is sent.
1: MASTER Mode start-transmit start condition on the bus.
[4]
STP
Stop Condition
0: MASTER Mode stop condition is sent.
1: MASTER Mode stop-transmit stop condition on the bus.
[3]
IFLG
Interrupt Flag
2
0: I C interrupt flag is not set.
2
1: I C interrupt flag is set.
[2]
AAK
Acknowledge
0: Not Acknowledge.
1: Acknowledge.
[1:0]
Reserved
These bits are reserved and must be programmed to 00.
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I2C Status Register
The I2C_SR Register is a read-only register that contains a 5-bit status code in the five
most-significant bits; the three least-significant bits are always 0. The read-only I2C_SR
registers share the same I/O addresses as the write-only I2C_CCR registers. See Table
128.
2
Table 128. I C Status Registers (I2C_SR)
Bit
7
6
5
STAT
1
4
3
2
1
0
Field
Reserved
Reset
1
1
1
1
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
00CCh
Bit
Description
2
[7:3]
I C Status
2
STAT
00000–11111: 5-bit I C status code.
These bits are reserved and must be programmed to 000.
[2:0]
There are 29 possible status codes, each of which is defined in Table 129. When the
I2C_SR Register contains the status code F8h, no relevant status information is available,
no interrupt is generated, and the IFLG bit in the I2C_CTL Register is not set. All other
status codes correspond to a defined state of the I2C.
When each of these states is entered, the corresponding status code appears in this register
and the IFLG bit in the I2C_CTL Register is set to 1. When the IFLG bit is cleared, the sta-
tus code returns to F8h.
2
Table 129. I C Status Codes
Code
00h
08h
10h
18h
20h
28h
30h
38h
Status
Bus error.
Start condition transmitted.
Repeated start condition transmitted.
Address and write bit transmitted, ACK received.
Address and write bit transmitted, ACK not received.
Data byte transmitted in MASTER Mode, ACK received.
Data byte transmitted in MASTER Mode, ACK not received.
Arbitration lost in address or data byte.
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2
Table 129. I C Status Codes (Continued)
Code
40h
48h
50h
58h
60h
68h
70h
78h
80h
88h
90h
98h
A0h
A8h
B0h
B8h
C0h
C8h
D0h
D8h
F8h
Status
Address and read bit transmitted, ACK received.
Address and read bit transmitted, ACK not received.
Data byte received in MASTER Mode, ACK transmitted.
Data byte received in MASTER Mode, NACK transmitted.
Slave address and write bit received, ACK transmitted.
Arbitration lost in address as master, slave address and write bit received, ACK transmitted.
General Call address received, ACK transmitted.
Arbitration lost in address as master, General Call address received, ACK transmitted.
Data byte received after slave address received, ACK transmitted.
Data byte received after slave address received, NACK transmitted.
Data byte received after General Call received, ACK transmitted.
Data byte received after General Call received, NACK transmitted.
Stop or repeated start condition received in SLAVE Mode.
Slave address and read bit received, ACK transmitted.
Arbitration lost in address as master, slave address and read bit received, ACK transmitted.
Data byte transmitted in SLAVE Mode, ACK received.
Data byte transmitted in SLAVE Mode, ACK not received.
Last byte transmitted in SLAVE Mode, ACK received.
Second Address byte and write bit transmitted, ACK received.
Second Address byte and write bit transmitted, ACK not received.
No relevant status information, IFLG = 0.
If an illegal condition occurs on the I2C bus, the bus error state is entered (status code
00h). To recover from this state, the STP bit in the I2C_CTL Register must be set and the
IFLG bit cleared. The I2C then returns to an idle state. No stop condition is transmitted on
the I2C bus.
Note: The STP and STA bits are set to 1 at the same time to recover from the bus error. The I2C
then sends a start condition.
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I2C Clock Control Register
The I2C_CCR Register is a write-only register. The seven LSBs control the frequency at
which the I2C bus is sampled and the frequency of the I2C clock line (SCL) when the I2C
is in MASTER Mode. The write-only I2C_CCR registers share the same I/O addresses as
the read-only I2C_SR registers. See Table 130.
2
Table 130. I C Clock Control Registers (I2C_CCR)
Bit
7
6
5
4
3
2
1
N
0
0
Field
Reset
R/W
Reserved
M
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Address
00CCh
Note: W = read only.
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6:3]
M
Scalar Value
2
0000–1111: I C clock divider scalar value; see the equations that follow.
[2:0]
N
Exponential Value
000–111: I C clock divider exponent; see the equations that follow.
2
The I2C clocks are derived from the system clock of the eZ80F91 device. The frequency
of this system clock is fSCK. The I2C bus is sampled by the I2C block at the frequency
fSAMP supplied by the following equation:
f
SCLK
f
=
SAMP
N
2
In MASTER Mode, the I2C clock output frequency on SCL (fSCL) is supplied by the fol-
lowing equation:
f
SCLK
f
=
SCL
N
10 • (M + 1)(2)
The use of two separately-programmable dividers allows the MASTER Mode output fre-
quency to be set independently of the frequency at which the I2C bus is sampled. This fea-
ture is particularly useful in multimaster systems because the frequency at which the I2C
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bus is sampled must be at least 10 times the frequency of the fastest master on the bus to
ensure that start and stop conditions are always detected. By using two programmable
clock divider stages, a high sampling frequency is ensured while allowing the MASTER
Mode output to be set to a lower frequency.
Bus Clock Speed
The I2C bus is defined for bus clock speeds up to 100 kbps (400kbps in FAST Mode).
To ensure correct detection of start and stop conditions on the bus, the I2C must sample the
I2C bus at least ten times faster than the bus clock speed of the fastest master on the bus.
The sampling frequency must therefore be at least 1MHz (4MHz in FAST Mode) to guar-
antee correct operation with other bus masters.
The I2C sampling frequency is determined by the frequency of the eZ80F91 system clock
and the value in the I2C_CCR bits 2 to 0. The bus clock speed generated by the I2C in
MASTER Mode is determined by the frequency of the input clock and the values in
I2C_CCR[2:0] and I2C_CCR[6:3].
I2C Software Reset Register
The I2C_SRR Register is a write-only register. Writing any value to this register performs
a software reset of the I2C module. See Table 131.
2
Table 131. I C Software Reset Register (I2C_SRR)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
SRR
U
U
U
U
U
U
U
U
W
W
W
W
W
W
W
W
Address
00CDh
Note: U = undefined; W = write only.
Bit
Description
[7:0]
SRR
Software Reset
2
00h–FFh: Writing any value to this register performs a software reset of the I C module.
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Zilog Debug Interface
The Zilog Debug Interface (ZDI) provides a built-in debugging interface to the CPU. ZDI
provides basic in-circuit emulation features including:
•
•
•
•
•
•
•
•
•
Examining and modifying internal registers
Examining and modifying memory
Starting and stopping the user program
Setting program and data break points
Single-stepping the user program
Executing user-supplied instructions
Debugging the final product with the inclusion of one small connector
Downloading code into SRAM
C source-level debugging using Zilog Developer Studio II (ZDS II)
The above features are built into the silicon. Control is provided via a two-wire interface
that is connected to the ZPAKII emulator. Figure 48 shows a typical setup using a a target
board, ZPAKII, and the host PC running Zilog Developer Studio II. For more information
about ZPAKII and ZDS II, refer to www.zilog.com.
Target Board
C
O
N
N
E
C
T
O
R
ZiLOG
Developer
Studio
ZPAK
Emulator
eZ80
Product
Figure 48. Typical ZDI Debug Setup
ZDI allows reading and writing of most internal registers without disturbing the state of
the machine. Reads and writes to memory occurs as fast as the ZDI downloads and
uploads data, with a maximum supported ZDI clock frequency of 0.4 times the eZ80F91
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system clock frequency. Also, regardless of the ZDI clock frequency, the duration of the
low-phase of the ZDI clock (that is, ZCL = 0) must be at least 1.25 times the system clock
period.
For the description on how to enable the ZDI interface on the exit of RESET, see the OCI
Activation section on page 257.
Table 132. Recommend ZDI Clock versus System Clock Frequency
System Clock
Frequency
ZDI Clock
Frequency
3–10MHz
8–16MHz
12–24MHz
20–50MHz
1MHz
2MHz
4 MHz
8 MHz
ZDI-Supported Protocol
ZDI supports a bidirectional serial protocol. The protocol defines any device that sends
data as the transmitter and any receiving device as the receiver. The device controlling the
transfer is the master and the device being controlled is the slave. The master always initi-
ates the data transfers and provides the clock for both receive and transmit operations. The
ZDI block on the eZ80F91 device is considered a slave in all data transfers.
Figure 49 shows the schematic for building a connector on a target board. This connector
allows you to connect directly to the ZPAK emulator using a six-pin header.
TVDD
(Target VDD
)
10 Kohm
10 Kohm
2
4
6
1
3
5
TCK (ZCL)
TDI (ZDA)
eZ80F91
6-Pin Target Connector
Figure 49. Schematic For Building a Target Board ZPAK Connector
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ZDI Clock and Data Conventions
The two pins used for communication with the ZDI block are the ZDI clock pin (ZCL) and
the ZDI data pin (ZDA). On eZ80F91, the ZCL pin is shared with the TCK pin while the
ZDA pin is shared with the TDI pin. The ZCL and ZDA pin functions are only available
when the On-Chip Instrumentation is disabled and the ZDI is therefore enabled. For gen-
eral data communication, the data value on the ZDA pin changes only when ZCL is Low
(0). The only exception is the ZDI start bit, which is indicated by a High-to-Low transition
(falling edge) on the ZDA pin while ZCL is High.
Data is shifted into and out of ZDI, with the most-significant bit (bit 7) of each byte being
first in time, and the least-significant bit (bit 0) last in time. All information is passed
between the master and the slave in 8-bit (single-byte) units. Each byte is transferred with
nine clock cycles; eight to shift the data, and the ninth for internal operations.
ZDI Start Condition
All ZDI commands are preceded by the ZDI start signal, which is a High-to-Low transi-
tion of ZDA when ZCL is High. The ZDI slave on the eZ80F91 device continually moni-
tors the ZDA and ZCL lines for the start signal and does not respond to any command until
this condition is met. The master pulls ZDA Low, with ZCL High, to indicate the begin-
ning of a data transfer with the ZDI block. Figure 50 and Figure 51 shows a valid ZDI start
signal prior to writing and reading data, respectively. A Low-to-High transition of ZDA
while the ZCL is High produces no effect.
Data is shifted in during a write to the ZDI block on the rising edge of ZCL, as shown in
Figure 50. Data is shifted out during a read from the ZDI block on the falling edge of ZCL
as shown in Figure 51. When an operation is completed, the master stops during the ninth
cycle and holds the ZCL signal High.
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ZDI Data In
(Write)
ZDI Data In
(Write)
ZCL
ZDA
Start Signal
Figure 50. ZDI Write Timing
ZDI Data Out
(Read)
ZDI Data Out
(Read)
ZCL
ZDA
Start Signal
Figure 51. ZDI Read Timing
ZDI Single-Bit Byte Separator
Following each 8-bit ZDI data transfer, a single-bit byte separator is used. To initiate a
new ZDI command, the single-bit byte separator must be High (logic 1) to allow for a new
ZDI start command to be sent. For all other cases, the single-bit byte separator is either
Low (logic 0) or High (logic 1). When ZDI is configured to allow the CPU to accept exter-
nal bus requests, the single-bit byte separator must be Low (logic 0) during all ZDI com-
mands. This Low value indicates that ZDI is still operating and is not ready to relinquish
the bus. The CPU does not accept the external bus requests until the single-bit byte separa-
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tor is a High (logic 1). For more information about accepting bus requests in ZDI DEBUG
Mode, see the Bus Requests During ZDI Debug Mode section on page 238.
ZDI Register Addressing
Following a start signal the ZDI master must output the ZDI register address. All data
transfers with the ZDI block use special ZDI registers. The ZDI control registers that
reside in the ZDI register address space must not be confused with the eZ80F91 device
peripheral registers that reside in the I/O address space.
Many locations in the ZDI control register address space are shared by two registers – one
for read-only access and one for write-only access. For example, a read from ZDI register
address 00hreturns the eZ80 Product ID Low Byte, while a write to this same location,
00h, stores the low byte of one of the address match values used for generating break
points.
The format for a ZDI address is seven bits of address, followed by one bit for read or write
control, and completed by a single-bit byte separator. The ZDI executes a read or write
operation depending on the state of the R/W bit (0 = write, 1 = read). If no new start com-
mand is issued at completion of the read or write operation, the operation is repeated. This
allows repeated read or write operations without having to resend the ZDI command. A
start signal must follow to initiate a new ZDI command. Figure 52 shows the timing for
address writes to ZDI registers.
Single-Bit
Byte Separator
or new ZDI
START Signal
ZDI Address Byte
ZCL
ZDA
S
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
lsb
R/W 0/1
msb
START
Signal
0 = WRITE
1 = READ
Figure 52. ZDI Address Write Timing
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ZDI Write Operations
This section describes the two write operations of the Zilog Debug Interface.
ZDI Single-Byte Write
For single-byte write operations, the address and write control bit are first written to the
ZDI block. Following the single-bit byte separator, the data is shifted into the ZDI block
on the next 8 rising edges of ZCL. The master terminates activity after 8 clock cycles.
Figure 53 shows the timing for ZDI single-byte write operations.
ZDI Data Byte
ZCL
ZDA
7
8
9
1
2
3
4
5
6
7
8
9
A0
Write
0/1
D7
D6
D5
D4
D3
D2
D1
D0
1
msb
of DATA
lsb
of DATA
lsb of
Single-Bit
End of Data
or New ZDI
START Signal
ZDI Address Byte Separator
Figure 53. ZDI Single-Byte Data Write Timing
ZDI Block Write
The block write operation is initiated in the same manner as the single-byte write opera-
tion, but instead of terminating the write operation after the first data byte is transferred,
the ZDI master continues to transmit additional bytes of data to the ZDI slave on the
eZ80F91 device. After the receipt of each byte of data the ZDI register address increments
by 1. If the ZDI register address reaches the end of the write-only ZDI register address
space (30h), the address stops incrementing. Figure 54 shows the timing for ZDI block
write operations.
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ZDI Data Bytes
ZCL
ZDA
7
8
9
1
2
7
8
9
1
2
A0
Write
0/1
D7
D6
D1
D0
0/1
D7
D6
msb
of DATA
Byte 1
lsb
of DATA
Byte 1
msb
of DATA
Byte 2
lsb of
Single-Bit
Single-Bit
Byte Separator
ZDI Address Byte Separator
Figure 54. ZDI Block Data Write Timing
ZDI Read Operations
This section describes the two read operations of the Zilog Debug Interface.
ZDI Single-Byte Read
Single-byte read operations are initiated in the same manner as single-byte write opera-
tions, with the exception that the R/W bit of the ZDI register address is set to 1. Upon
receipt of a slave address with the R/W bit set to 1, the eZ80F91 device’s ZDI block loads
the selected data into the shifter at the beginning of the first cycle following the single-bit
data separator. The most-significant bit (msb) is shifted out first. Figure 55 shows the tim-
ing for ZDI single-byte read operations.
ZDI Data Byte
ZCL
ZDA
7
8
9
1
2
3
4
5
6
7
8
9
A0
Read
0/1
D7
D6
D5
D4
D3
D2
D1
D0
1
msb
of DATA
lsb
of DATA
lsb of
Single-Bit
End of Data
or New ZDI
START Signal
ZDI Address Byte Separator
Figure 55. ZDI Single-Byte Data Read Timing
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Note: In ZDI single-byte read operations, after each read operation, the Program Counter (PC)
address is incremented by two bytes. For example, if the current PC address is 0x00, then
a read operation at 0x00increments the PC to 0x02. To read the next byte, the PC must be
decremented by one.
ZDI Block Read
A block read operation is initiated in the same manner as a single-byte read; however, the
ZDI master continues to clock in the next byte from the ZDI slave as the ZDI slave contin-
ues to output data. The ZDI register address counter increments with each read. If the ZDI
register address reaches the end of the read-only ZDI register address space (20h), the
address stops incrementing. Figure 56 shows the ZDI’s block read timing.
ZDI Data Bytes
ZCL
ZDA
7
8
9
1
2
7
8
9
1
2
A0
Read
0/1
D7
D6
D1
D0
0/1
D7
D6
msb
of DATA
Byte 1
lsb
of DATA
Byte 1
msb
of DATA
Byte 2
lsb of
Single-Bit
Single-Bit
Byte Separator
ZDI Address Byte Separator
Figure 56. ZDI Block Data Read Timing
Operation of the eZ80F91 Device During ZDI Break Points
If the ZDI forces the CPU to break, only the CPU suspends operation. The system clock
continues to operate and drive other peripherals. Those peripherals that operate autono-
mously from the CPU continues to operate, if so enabled. For example, the Watchdog
Timer and Programmable Reload Timers continue to count during a ZDI break point.
When using the ZDI interface, any write or read operations of peripheral registers in the I/
O address space produces the same effect as read or write operations using the CPU. As
many register read/write operations exhibit secondary effects, such as clearing flags or
causing operations to commence, the effects of the read/write operations during a ZDI
break must be taken into consideration.
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Bus Requests During ZDI Debug Mode
The ZDI block on the eZ80F91 device allows an external device to take control of the
address and data bus while the eZ80F91 device is in DEBUG Mode. ZDI_BUSACK_EN
causes ZDI to allow or prevent acknowledgement of bus requests by external peripherals.
The bus acknowledge occurs only at the end of the current ZDI operation (indicated by a
High during the single-bit byte separator). The default reset condition is for bus acknowl-
edgement to be disabled. To allow bus acknowledgement, the ZDI_BUSACK_EN must be
written.
When an external bus request (BUSREQ pin asserted) is detected, ZDI waits until comple-
tion of the current operation before responding. ZDI acknowledges the bus request by
asserting the bus acknowledge (BUSACK) signal. If the ZDI block is not currently shift-
ing data, it acknowledges the bus request immediately. ZDI uses the single-bit byte separa-
tor of each data word to determine if it is at the end of a ZDI operation. If the bit is a logic
0, ZDI does not assert BUSACK to allow additional data read or write operations. If the
bit is a logic 1, indicating completion of the ZDI commands, BUSACK is asserted.
Potential Hazards of Enabling Bus Requests During DEBUG
Mode
There are some potential hazards that you must be aware of when enabling external bus
requests during ZDI DEBUG Mode. First, when the address and data bus are being used
by an external source, ZDI must only access ZDI registers and internal CPU registers to
prevent possible bus contention. The bus acknowledge status is reported in the
ZDI_BUS_STAT Register. The BUSACK output pin also indicates the bus acknowledge
state.
A second hazard is that when a bus acknowledge is granted, the ZDI is subject to any wait
states that are assigned to the device currently being accessed by the external peripheral.
To prevent data errors, ZDI must avoid data transmission while another device is control-
ling the bus.
Finally, exiting ZDI DEBUG Mode while an external peripheral controls the address and
data buses, as indicated by BUSACK assertion produces unpredictable results.
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ZDI Write-Only Registers
Table 133 lists all ZDI registers that can be written to. Many of the ZDI write-only
addresses are shared with ZDI read-only registers.
Table 133. ZDI Write-Only Registers
Reset
Value
ZDI Address ZDI Register Name ZDI Register Function
00h
01h
02h
04h
05h
06h
08h
09h
0Ah
0Ch
0Dh
0Eh
10h
11h
13h
14h
15h
16h
17h
21h
22h
23h
24h
25h
30h
ZDI_ADDR0_L
ZDI_ADDR0_H
ZDI_ADDR0_U
ZDI_ADDR1_L
ZDI_ADDR1_H
ZDI_ADDR1_U
ZDI_ADDR2_L
ZDI_ADDR2_H
ZDI_ADDR2_U
ZDI_ADDR3_L
ZDI_ADDR3_H
ZDI_ADDR3_U
ZDI_BRK_CTL
Address Match 0 Low Byte
Address Match 0 High Byte
Address Match 0 Upper Byte
Address Match 1 Low Byte
Address Match 1 High Byte
Address Match 1 Upper Byte
Address Match 2 Low Byte
Address Match 2 High Byte
Address Match 2 Upper Byte
Address Match 3 Low Byte
Address Match 3 High Byte
Address Match 4 Upper Byte
Break Control Register
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00h
ZDI_MASTER_CTL Master Control Register
00h
ZDI_WR_DATA_L
ZDI_WR_DATA_H
ZDI_WR_DATA_U
ZDI_RW_CTL
ZDI_BUS_CTL
ZDI_IS4
Write Data Low Byte
Write Data High Byte
Write Data Upper Byte
Read/Write Control Register
Bus Control Register
Instruction Store 4
XXh
XXh
XXh
00h
00h
XXh
XXh
XXh
XXh
XXh
XXh
ZDI_IS3
Instruction Store 3
ZDI_IS2
Instruction Store 2
ZDI_IS1
Instruction Store 1
ZDI_IS0
Instruction Store 0
ZDI_WR_MEM
Write Memory Register
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ZDI Read-Only Registers
Table 134 lists the ZDI registers that can be read from. Many of these ZDI read-only
addresses are shared with ZDI write-only registers.
Table 134. ZDI Read-Only Registers
Reset
Value
ZDI Address
00h
ZDI Register Name
ZDI_ID_L
ZDI Register Function
eZ80 Product ID Low Byte Register
eZ80 Product ID High Byte Register
eZ80 Product ID Revision Register
Status Register
08h
01h
ZDI_ID_H
00h
02h
ZDI_ID_REV
ZDI_STAT
XXh
00h
03h
10h
ZDI_RD_L
Read Memory Address Low Byte Register
Read Memory Address High Byte Register
Read Memory Address Upper Byte Register
Bus Status Register
XXh
XXh
XXh
00h
11h
ZDI_RD_H
12h
ZDI_RD_U
17h
ZDI_BUS_STAT
ZDI_RD_MEM
20h
Read Memory Data Value
XXh
ZDI Register Definitions
This section describes the following registers:
ZDI Address Match Registers – see page 241
ZDI Break Control Register – see page 242
ZDI Master Control Register – see page 244
ZDI Write Data Registers – see page 245
ZDI Read/Write Control Register – see page 245
ZDI Bus Control Register – see page 248
Instruction Store 4:0 Registers – see page 248
ZDI Write Memory Register – see page 249
eZ80 Product ID Low and High Byte Registers – see page 250
eZ80 Product ID Revision Register – see page 251
ZDI Status Register – see page 252
ZDI Read Register Low, High, and Upper – see page 253
ZDI Bus Status Register – see page 254
ZDI Read Memory Register – see page 254
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ZDI Address Match Registers
The four sets of address match registers are used for setting the addresses for generating
break points. When the accompanying BRK_ADDRX bit is set in the ZDI Break Control
Register to enable the particular address match, the current eZ80F91 address is compared
with the 3-byte address set, {ZDI_ADDRx_U, ZDI_ADDRx_H, and ZDI_ADDR_x_L}.
If the CPU is operating in ADL Mode, the address is supplied by ADDR[23:0]. If the CPU
is operating in Z80 Mode, the address is supplied by {MBASE[7:0], ADDR[15:0]}. If a
match is found, ZDI issues a break to the eZ80F91 device placing the CPU in ZDI Mode
pending further instructions from the ZDI interface block. If the address is not the first op-
code fetch, the ZDI break is executed at the end of the instruction in which it is executed.
There are four sets of address match registers. They are used in conjunction with each
other to break on branching instructions. See Table 135.
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Table 135. ZDI Address Match Registers
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
ZDI_ADDRx_L, ZDI_ADDRx_H or ZDI_ADDRx_U
U
U
U
U
U
U
U
U
W
W
W
W
W
W
W
W
Address
See Table 136
Note: U = undefined; W = write only.
Bit
Description
ZDI Address Match
[7:0]
ZDI_ADDRx_L, 00h–FFh: The four sets of ZDI address match registers are used for setting the
ZDI_ADDRx_H, addresses for generating break points. The 24 bit addresses are supplied by
or
{ZDI_ADDRx_U, ZDI_ADDRx_H, ZDI_ADDRx_L, in which x is 0, 1, 2, or 3.
ZDI_ADDRx_U
Address Information for ZDI Address Match Registers in the ZDI Register Write-Only
Address Space.
Table 136. ZDI Address Match Register Addressing
Register
Address
00h
ZDI_ADDR0_L
ZDI_ADDR0_H
ZDI_ADDR0_U
ZDI_ADDR1_L
ZDI_ADDR1_H
ZDI_ADDR1_U
ZDI_ADDR2_L
ZDI_ADDR2_H
ZDI_ADDR2_U
ZDI_ADDR3_L
ZDI_ADDR3_H
ZDI_ADDR3_U
01h
02h
04h
05h
06h
08h
09h
0Ah
0Ch
0Dh
0Eh
ZDI Break Control Register
The ZDI Break Control Register, shown in Table 137, is used to enable break points. ZDI
asserts a break when the CPU instruction address, ADDR[23:0], matches the value in the
ZDI Address Match 3 registers, {ZDI_ADDR3_U, ZDI_ADDR3_H, ZDI_ADDR3_L}.
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BREAKs occurs only on an instruction boundary. If the instruction address is not the
beginning of an instruction (that is, for multibyte instructions), then the break occurs at the
end of the current instruction. The brk_next bit is set to 1. The BRK_NEXT bit must be
reset to 0 to release the break.
Table 137. ZDI Break Control Register (ZDI_BRK_CTL)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
BRK_NEXT
BRK_ADDRx
IGN_LOW_y
SINGLE_STEP
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Address
10h in the ZDI write-only register address space
Note: x indicates bits in the range [3:0]; y indicates bits in the range [1:0]; W = write only.
Bit
Description
ZDI Break
[7]
BRK_NEXT
0: The ZDI break on the next CPU instruction is disabled. Clearing this bit releases the
CPU from its current break condition.
1: The ZDI break on the next CPU instruction is enabled. The CPU uses multibyte Op
Codes and multibyte operands. Break points only occur on the first Op Code in a
multibyte Op Code instruction. If the ZCL pin is High and the ZDA pin is Low at the
end of RESET, this bit is set to 1 and a break occurs on the first instruction following
the RESET. This bit is set automatically during ZDI break on address match. A
break is also forced by writing a 1 to this bit.
[6]
ZDI Break Enable 3
0: The ZDI break, upon matching break address 3, is disabled.
1: The ZDI break, upon matching break address 3, is enabled.
BRK_ADDR3
[5]
ZDI Break Enable 2
0: The ZDI break, upon matching break address 2, is disabled.
1: The ZDI break, upon matching break address 2, is enabled.
BRK_ADDR2
[4]
ZDI Break Enable 1
0: The ZDI break, upon matching break address 1, is disabled.
1: The ZDI break, upon matching break address 1, is enabled.
BRK_ADDR1
[3]
ZDI Break Enable 0
0: The ZDI break, upon matching break address 0, is disabled.
1: The ZDI break, upon matching break address 0, is enabled.
BRK_ADDR0
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Bit
Description (Continued)
Ignore Low Byte Enable 1
[2]
IGN_LOW_1
0: The Ignore the Low Byte function of the ZDI Address Match 1 registers is disabled.
If BRK_ADDR1 is set to 1, ZDI initiates a break when the entire 24-bit address,
ADDR[23:0], matches the 3-byte value {ZDI_ADDR1_U, ZDI_ADDR1_H,
ZDI_ADDR1_L}.
1: The Ignore the Low Byte function of the ZDI Address Match 1 registers is enabled. If
BRK_ADDR1 is set to 1, ZDI initiates a break when only the upper 2 bytes of the 24-
bit address, ADDR[23:8], match the 2-byte value {ZDI_ADDR1_U, ZDI_ADDR1_H}.
As a result, a break occurs anywhere within a 256-byte page.
[1]
Ignore Low Byte Enable 0
IGN_LOW_0
0: The Ignore the Low Byte function of the ZDI Address Match 1 registers is disabled.
If BRK_ADDR0 is set to 1, ZDI initiates a break when the entire 24-bit address,
ADDR[23:0], matches the 3-byte value {ZDI_ADDR0_U, ZDI_ADDR0_H,
ZDI_ADDR0_L}.
1: The Ignore the Low Byte function of the ZDI Address Match 1 registers is enabled. If
the BRK_ADDR1 is set to 0, ZDI initiates a break when only the upper 2 bytes of the
24-bit address, ADDR[23:8], match the two-bytes value {ZDI_ADDR0_U,
ZDI_ADDR0_H}. As a result, a break occurs anywhere within a 256-byte page.
[0]
Single Step Mode Enable
SINGLE_STEP
0: ZDI SINGLE STEP Mode is disabled.
1: ZDI SINGLE STEP Mode is enabled. ZDI asserts a break following execution of
each instruction.
ZDI Master Control Register
The ZDI Master Control Register, Table 138, provides control of the eZ80F91 device. It is
capable of forcing a RESET and waking up the eZ80F91 from the low-power modes
(HALT or SLEEP).
Table 138. ZDI Master Control Register (ZDI_MASTER_CTL)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
ZDI_RESET
Reserved
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Address
11h in the ZDI write-only register address space
Note: W = write only.
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Bit
Description
[7]
ZDI System Reset
0: No action.
ZDI_RESET
1: Initiate a RESET of the eZ80F91 MCU. This bit is automatically cleared at the end of
the RESET event.
[6:0]
Reserved
These bits are reserved and must be programmed to 0000000.
ZDI Write Data Registers
These three registers are used in the ZDI write-only register address space to store the data
that is written when a write instruction is sent to the ZDI Read/Write Control Register
(ZDI_RW_CTL). The ZDI Read/Write Control Register is located at ZDI address 16h
immediately following the ZDI Write Data registers. As a result, the ZDI Master is
allowed to write the data to {ZDI_WR_U, ZDI_WR_H, ZDI_WR_L} and the write com-
mand in one data transfer operation. See Table 139.
Table 139. ZDI Write Data Registers (ZDI_WR_U, ZDI_WR_H, ZDI_WR_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
ZDI_WR_L, ZDI_WR_H or ZDI_WR_L
U
U
U
U
U
U
U
U
W
W
W
W
W
W
W
W
Address
ZDI_WR_U = 13h, ZDI_WR_H = 14h and ZDI_WR_L = 15h
in the ZDI Register write-only address space
Note: U = undefined; W = write.
Bit
Description
ZDI Write Data
[7:0]
ZDI_WR_L,
ZDI_WR_H,
or
00h–FFh: These registers contain the data that is written during execution of a write oper-
ation defined by the ZDI_RW_CTL Register. The 24-bit data value is stored as
{ZDI_WR_U, ZDI_WR_H, ZDI_WR_L}. If less than 24 bits of data are required to com-
plete the required operation, the data is taken from the least-significant byte(s).
ZDI_WR_L
ZDI Read/Write Control Register
The ZDI Read/Write Control Register is used in the ZDI write-only register address to
read data from, write data to, and manipulate the CPU’s registers or memory locations.
When this register is written, the eZ80F91 device immediately performs the operation cor-
responding to the data value written as described in Table 140. When a read operation is
executed via this register, the requested data values are placed in the ZDI Read Data regis-
ters {ZDI_RD_U, ZDI_RD_H, ZDI_RD_L}. When a write operation is executed via this
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register, the write data is taken from the ZDI Write Data registers {ZDI_WR_U,
ZDI_WR_H, ZDI_WR_L}.
In Table 140, ZDI_RW_CTL = 16hin the ZDI Register write-only address space. For
information about the CPU registers, refer to the eZ80 CPU User Manual (UM0077),
which is available free for download from the Zilog website.
Table 140. ZDI Read/Write Control Register Functions (ZDI_RW_CTL)
Hex
Value
Hex
Value
Command
Command
00
01
02
03
04
05
Read {MBASE, A, F}
ZDI_RD_U ← MBASE
ZDI_RD_H ← F
80
Write AF
MBASE ← ZDI_WR_U
F ← ZDI_WR_H
A ← ZDI_WR_L
ZDI_RD_L ← A
Read BC
81
82
83
84
85
Write BC
ZDI_RD_U ← BCU
ZDI_RD_H ← B
ZDI_RD_L ← C
BCU ← ZDI_WR_U
B ← ZDI_WR_H
C ← ZDI_WR_L
Read DE
Write DE
ZDI_RD_U ← DEU
ZDI_RD_H ← D
ZDI_RD_L ← E
DEU ← ZDI_WR_U
D ← ZDI_WR_H
E ← ZDI_WR_L
Read HL
Write HL
ZDI_RD_U ← HLU
ZDI_RD_H ← H
ZDI_RD_L ← L
HLU ← ZDI_WR_U
H ← ZDI_WR_H
L ← ZDI_WR_L
Read IX
Write IX
ZDI_RD_U ← IXU
ZDI_RD_H ← IXH
ZDI_RD_L ← IXL
IXU ← ZDI_WR_U
IXH ← ZDI_WR_H
IXL ← ZDI_WR_L
Read IY
Write IY
ZDI_RD_U ← IYU
ZDI_RD_H ← IYH
ZDI_RD_L ← IYL
IYU ← ZDI_WR_U
IYH ← ZDI_WR_H
IYL ← ZDI_WR_L
06
07
Read SP
In ADL Mode, SP = SPL.
In Z80 Mode, SP = SPS.
86
87
Write SP
In ADL Mode, SP = SPL.
In Z80 Mode, SP = SPS.
Read PC
Write PC
ZDI_RD_U ← PC[23:16]
ZDI_RD_H ← PC[15:8]
ZDI_RD_L ← PC[7:0]
PC[23:16] ← ZDI_WR_U
PC[15:8] ← ZDI_WR_H
PC[7:0] ← ZDI_WR_L
08
Set ADL
ADL ← 1
88
Reserved.
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Table 140. ZDI Read/Write Control Register Functions (ZDI_RW_CTL)
Hex
Value
Hex
Value
Command
Command
09
Reset ADL
ADL ← 0
89
Reserved.
0A
Exchange CPU register sets 8A
AF ← AF’
Reserved.
BC ← BC’
DE ← DE’
HL ← HL’
0B
Read memory from current PC 8B
value, increment PC
Write memory from current PC
value, increment PC.
The CPU’s alternate register set (A’, F’, B’, C’, D’, E’, HL’) cannot be read directly. The
ZDI programmer must execute the exchange instruction (EXX) to gain access to the alter-
nate CPU register set.
Note:
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ZDI Bus Control Register
The ZDI Bus Control Register controls bus requests during DEBUG Mode. It enables or
disables bus acknowledge in ZDI DEBUG Mode and allows ZDI to force assertion of the
BUSACK signal. This register must only be written during ZDI DEBUG Mode (that is,
following a break). See Table 141.
Table 141. ZDI Bus Control Register (ZDI_BUS_CTL)
Bit
7
6
5
4
3
2
1
0
Field
ZDI_BUSAK_EN ZDI_BUSAK
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Address
Note: W = write only.
17h in the ZDI Register write-only address space
Bit
Description
ZDI Bus Acknowledge Enable
[7]
ZDI_BUSAK_EN 0: Bus requests by external peripherals using the BUSREQ pin are ignored. The bus
acknowledge signal, BUSACK, is not asserted in response to any bus requests.
1: Bus requests by external peripherals using the BUSREQ pin are accepted. A bus
acknowledge occurs at the end of the current ZDI operation. The bus acknowledge
is indicated by asserting the BUSACK pin in response to a bus request.
[6]
ZDI Bus Acknowledge Assert
0: Deassert the bus acknowledge pin (BUSACK) to return control of the address and
data buses back to ZDI.
ZDI_BUSAK
1: Assert the bus acknowledge pin (BUSACK) to pass control of the address and data
buses to an external peripheral.
[5:0]
Reserved
These bits are reserved and must be programmed to 000000.
Instruction Store 4:0 Registers
The ZDI Instruction Store registers are located in the ZDI Register write-only address
space. They are written with instruction data for direct execution by the CPU. When the
ZDI_IS0 Register is written, the eZ80F91 device exits the ZDI break state and executes a
single instruction. The op codes and operands for the instruction come from these Instruc-
tion Store registers. The Instruction Store Register 0 is the first byte fetched, followed by
Instruction Store registers 1, 2, 3, and 4, as necessary. Only the bytes the CPU requires to
execute the instruction must be stored in these registers. Some CPU instructions, when
combined with the MEMORY Mode suffixes (.SIS, .SIL, .LIS, or .LIL), require 6 bytes to
operate. These 6-byte instructions cannot be executed directly using the ZDI Instruction
Store registers. See Table 142.
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Table 142. Instruction Store 4:0 Registers (ZDI_IS4, ZDI_IS3, ZDI_IS2, ZDI_IS1, ZDI_IS0)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
ZDI_IS4, ZDI_IS3, ZDI_IS2, ZDI_IS1 or ZDI_IS0
U
U
U
U
U
U
U
U
W
W
W
W
W
W
W
W
Address
ZDI_IS4 = 21h, ZDI_IS3 = 22h, ZDI_IS2 = 23h, ZDI_IS1 = 24h, and ZDI_IS0 = 25h
in the ZDI Register Write-Only Address Space
Note: U = undefined; W = write.
Bit
Description
[7:0]
Instruction Store
ZDI_IS4,
ZDI_IS3,
ZDI_IS2,
ZDI_IS1
or
00h–FFh: These registers contain the Op Codes and operands for immediate execution
by the CPU following a write to ZDI_IS0. The ZDI_IS0 Register contains the first Op Code
of the instruction. The remaining ZDI_ISx registers contain any additional Op Codes or
operand dates required for execution of the required instruction.
ZDI_IS0
Note: The Instruction Store 0 Register is located at a higher ZDI address than the other Instruc-
tion Store registers. This feature allows the use of the ZDI auto-address increment function
to load and execute a multibyte instruction with a single data stream from the ZDI master.
Execution of the instruction commences with writing the final byte to ZDI_IS0.
ZDI Write Memory Register
A write to the ZDI Write Memory Register, shown in Table 143, causes the eZ80F91
device to write the 8-bit data to the memory location specified by the current address in the
Program Counter. In Z80 MEMORY Mode, this address is {MBASE, PC[15:0]}. In ADL
MEMORY Mode, this address is PC[23:0]. The Program Counter, PC, increments after
each data write. However, the ZDI register address does not increment automatically when
this register is accessed. As a result, the ZDI master is allowed to write any number of data
bytes by writing to this address one time followed by any number of data bytes.
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Table 143. ZDI Write Memory Register (ZDI_WR_MEM)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
ZDI_WR_MEM
U
U
U
U
U
U
U
U
W
W
W
W
W
W
W
W
Address
ZDI_WR_MEM = 30h in the ZDI Register write-only address space
Note: U = undefined; W = write.
Bit
Description
[7:0]
ZDI Write Memory
ZDI_WR_MEM 00h–FFh: The 8-bit data that is transferred to the ZDI slave following a write to this
address is written to the address indicated by the current Program Counter. The Program
Counter is incremented following each 8 bits of data. In Z80 MEMORY Mode, ({MBASE,
PC[15:0]}) ← 8 bits of transferred data. In ADL MEMORY Mode, (PC[23:0]) ← 8-bits of
transferred data.
eZ80 Product ID Low and High Byte Registers
The eZ80 Product ID Low and High Byte registers combine to provide a means for an
external device to determine the particular eZ80 product being addressed. See Tables 144
and 145.
Table 144. eZ80 Product ID Low Byte Register (ZDI_ID_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
ZDI_ID_L
0
0
0
0
1
0
0
0
R
R
R
R
R
R
R
R
Address
ZDI_ID_L = 00h in the ZDI Register read-only address space;
ZDI_ID_L = 0000h in the I/O Register address space
Note: R = read only.
Bit
Description
[7:0]
ZDI_ID_L
eZ80 Product Identification Low Byte
08h: {ZDI_ID_H, ZDI_ID_L} = {00h, 08h} indicates the eZ80F91 device.
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Table 145. eZ80 Product ID High Byte Register (ZDI_ID_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
ZDI_ID_H
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Address
ZDI_ID_H = 01h in the ZDI Register read-only address space;
ZDI_ID_H = 0001h in the I/O Register address space
Note: R = read only.
Bit
Description
[7:0]
ZDI_ID_H
eZ80 Product Identification High Byte
00h: {ZDI_ID_H, ZDI_ID_L} = {00h, 08h} indicates the eZ80F91 device.
eZ80 Product ID Revision Register
The eZ80 Product ID Revision Register identifies the current revision of the eZ80F91
product. See Table 146.
Table 146. eZ80 Product ID Revision Register (ZDI_ID_REV)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
ZDI_ID_REV
U
R
U
R
U
R
U
R
U
R
U
R
U
R
U
R
Address
ZDI_ID_REV = 02h in the ZDI Register read-only address space;
ZDI_ID_REV = 0002h in the I/O Register address space
Note: U = undefined; R = read only.
Bit
Description
[7:0]
eZ80 Product Identification Revision
ZDI_ID_REV 00h–FFh: Identifies the current revision of the eZ80F91 device.
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ZDI Status Register
The ZDI Status Register, shown in Table 147, provides current information about the
eZ80F91 device and the CPU.
Table 147. ZDI Status Register (ZDI_STAT)
Bit
7
6
5
4
ADL
0
3
MADL
0
2
IEF1
0
1
0
Field
ZDI_ACTIVE Reserved HALT_SLP
Reserved
Reset
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
ZDI_STAT = 03h in the ZDI Register read-only address space
Bit
Description
ZDI Mode
[7]
ZDI_ACTIVE 0: The CPU is not functioning in ZDI Mode.
1: The CPU is currently functioning in ZDI Mode.
[6]
Reserved
This bit is reserved and must be programmed to 0.
[5]
HALT_SLP
HALT/SLEEP Modes
0: The CPU is not currently in HALT or SLEEP Mode.
1: The CPU is currently in HALT or SLEEP Mode.
[4]
ADL
Z80 MEMORY Mode
0: The CPU is operating in Z80 MEMORY Mode (ADL bit = 0).
1: The CPU is operating in ADL MEMORY Mode (ADL bit = 1).
[3]
MADL
MIXED MEMORY Mode
0: The CPU’s MIXED-MEMORY Mode (MADL) bit is reset to 0.
1: The CPU’s MIXED-MEMORY Mode (MADL) bit is set to 1.
[2]
IEF1
Interrupt Enable Flag 1
0: The CPU’s Interrupt Enable Flag 1 is reset to 0. Maskable interrupts are disabled.
1: The CPU’s Interrupt Enable Flag 1 is set to 1. Maskable interrupts are enabled.
[1:0]
Reserved
These bits are reserved and must be programmed to 00.
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ZDI Read Register Low, High, and Upper
The read-only ZDI Register address space offers Low, High, and Upper functions, which
contain the value read by a read operation from the ZDI Read/Write Control Register
(ZDI_RW_CTL). This data is valid only while in ZDI BREAK Mode and only if the
instruction is read by a request from the ZDI Read/Write Control Register. See Table 148.
Table 148. ZDI Read Register Low, High, and Upper (ZDI_RD_L, ZDI_RD_H, ZDI_RD_U)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
ZDI_RD_L, ZDI_RD_H, ZDI_RD_U
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Address
ZDI_RD_L = 10h, ZDI_RD_H = 11h, ZDI_RD_U = 12h
in the ZDI Register read-only address space
Note: R = read only.
Bit
Description
ZDI Read Low, High, Upper Byte
[7:0]
ZDI_RD_L,
ZDI_RD_H,
or
00h–FFh: Values read from the memory location as requested by the ZDI Read Control
Register during a ZDI read operation. The 24-bit value is supplied by {ZDI_RD_U,
ZDI_RD_H, ZDI_RD_L}.
ZDI_RD_U
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ZDI Bus Status Register
The ZDI Bus Status Register monitors BUSACKs during DEBUG Mode. See Table 149.
Table 149. ZDI Bus Control Register (ZDI_BUS_STAT)
Bit
7
6
5
4
3
2
1
0
Field
ZDI_BUSACK_EN ZDI_BUS_STAT
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
ZDI_BUS_STAT = 17h in the ZDI Register read-only address space
Bit
Description
Bus Acknowledge
[7]
ZDI_BUSACK_EN 0: Bus requests by external peripherals using the BUSREQ pin are ignored. The
bus acknowledge signal, BUSACK, is not asserted.
1: Bus requests by external peripherals using the BUSREQ pin are accepted. A bus
acknowledge occurs at the end of the current ZDI operation. The bus acknowl-
edge is indicated by asserting the BUSACK pin.
[6]
Bus Status
ZDI_BUS_STAT
0: Address and data buses are not relinquished to an external peripheral. Bus
acknowledge is deasserted (BUSACK pin is High).
1: Address and data buses are relinquished to an external peripheral. Bus acknowl-
edge is asserted (BUSACK pin is Low).
[5:0]
Reserved
These bits are reserved and must be programmed to 000000.
ZDI Read Memory Register
When a read is executed from the ZDI Read Memory Register, the eZ80F91 device
fetches the data from the memory address currently pointed to by the Program Counter,
PC; the Program Counter is then incremented. In Z80 MEMORY Mode, the memory
address is {MBASE, PC[15:0]}. In ADL MEMORY Mode, the memory address is
PC[23:0]. For more information about Z80 and ADL MEMORY modes, refer to the eZ80
CPU User Manual (UM0077), which is available free for download from the Zilog web-
site.
The Program Counter, PC, increments after each data read. However, the ZDI register
address does not increment automatically when this register is accessed. As a result, the
ZDI master reads any number of data bytes out of memory via the ZDI Read Memory
Register. See Table 150.
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Table 150. ZDI Read Memory Register (ZDI_RD_MEM)
Bit
7
6
5
4
3
2
1
0
Field
ZDI_RD_MEM
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
ZDI_RD_MEM = 20h in the ZDI Register read-only address space
Bit
Description
00h–FFh: 8-bit data read from the memory address indicated by the CPU’s Program
[7:0]
ZDI_RD_MEM Counter. In Z80 MEMORY Mode, 8-bit data is transferred out from address {MBASE,
PC[15:0]}. In ADL MEMORY Mode, 8-bit data is transferred out from address PC[23:0].
Note: The delay between issuing a memory read request and the return of the corresponding data
amount to multiple ZDI clock cycles. This delay is a function of the wait state configura-
tion of the memory space being accessed as well as the relative frequencies of the ZDI
clock and the system clock. If the ZDI master begins clocking the read data out of the
eZ80F91 soon after issuing the memory read request, invalid data will be returned. Since
no data-valid handshake mechanism exists in the ZDI protocol, the ZDI master must
account for expected memory read delay in some way.
A technique exists to mask this delay in almost all situations. It always reads at least two
consecutive bytes, starting one address lower than the address of interest. In this situation,
the eZ80F91 internally prefetches the data from the second address while the ZDI master
is sending the second read request. This allows enough time for the second ZDI memory
read to return valid data. The first data byte returned to the ZDI master must be discarded
since it is invalid. Memory reads of more than two consecutive bytes will also return cor-
rect data for all but the first address.
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On-Chip Instrumentation
On-Chip Instrumentation1 (OCI™) for the eZ80 CPU core enables powerful debugging
features. The OCI provides run control, memory and register visibility, complex break
points, and trace history features.
The OCI employs all of the functions of the Zilog Debug Interface (ZDI) as described in
the ZDI section. It also adds the following debug features:
•
Control via a 4-pin Joint Test Action Group (JTAG) port that conforms to IEEE Stan-
dard 1149.1 (Test Access Port and Boundary Scan Architecture)
•
•
Complex break point trigger functions
Break point enhancements, such as the ability to:
–
–
–
–
Define two break point addresses that form a range
Break on masked data values
Start or stop trace
Assert a trigger output signal
•
•
Trace history buffer
Software break point instruction
There are four sections to the OCI:
•
•
•
•
JTAG interface
ZDI debug control
Trace buffer memory
Complex triggers
This document contains information about how to activate the OCI for JTAG boundary
scan register operations. For additional information regarding OCI features, or to order
OCI debug tools, contact:
First Silicon Solutions, Inc.
www.fs2.com
1. On-Chip Instrumentation and OCI are trademarks of First Silicon Solutions, Inc.
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OCI Activation
OCI features clock initialization circuitry so that external debug hardware is detected dur-
ing power-up. The external debugger must drive the OCI clock pin (TCK) Low at least
two system clock cycles prior to the end of the RESET to activate the OCI block. If TCK
is High at the end of the RESET, the OCI block shuts down so that it does not draw power
in normal product operation. When the OCI is shut down, ZDI is enabled directly and is
accessed via the clock (TCK) and data (TDI) pins. For more information about ZDI, see
the Zilog Debug Interface chapter on page 230.
OCI Interface
There are six dedicated pins on the eZ80F91 for the OCI interface. Four pins – TCK,
TMS, TDI, and TDO – are required for IEEE Standard 1149.1-compliant JTAG ports. A
fifth pin, TRSTn, is optional for IEEE 1149.1 and utilized by the eZ80F91 device. The
TRIGOUT pin provides additional testability features. These six OCI pins are described in
Table 151.
Table 151. OCI Pins
Symbol
Name
Type
Description
TCK
Clock
Input
Asynchronous to the primary eZ80F91 system clock.
The TCK period must be at least twice the system
clock period. During RESET, this pin is sampled to
select either OCI or ZDI DEBUG modes. If Low dur-
ing RESET, the OCI is enabled. If High during
RESET, the OCI is powered down and ZDI DEBUG
Mode is enabled. When ZDI DEBUG Mode is active,
this pin is the ZDI clock. On-chip pull-up ensures a
default value of 1 (High).
TRSTn
TMS
TAP Reset
Input
Input
Active Low asynchronous reset for the Test Access
Port State Register. On-chip pull-up ensures a default
value of 1 (High).
Test Mode Select
This serial test mode input controls JTAG mode
selection. On-chip pull-up ensures a default value of
1 (High). The TMS signal is sampled on the rising
edge of the TCK signal.
TDI
Data In
Input
(OCI enabled)
Serial test data input. This pin is input-only when the
OCI is enabled. The input data is sampled on the ris-
ing edge of the TCK signal.
I/O
When the OCI is disabled, this pin functions as the
(OCI disabled) ZDA (ZDI Data) I/O pin. NORMAL Mode, following
RESET, configures TDI as an input.
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Table 151. OCI Pins (Continued)
Type Description
Symbol
Name
TDO
Data Out
Output
The output data changes on the falling edge of the
TCK signal.
TRIGOUT Trigger Output
Output
Generates an active High trigger pulse when valid
OCI trigger events occur. Output is open-drain when
no data is being driven out.
JTAG Boundary Scan
This section describes coverage, implementation, and usage of the eZ80F91 boundary
scan register based on the JTAG standard. A working knowledge of the IEEE 1149.1 spec-
ification, particularly Clause 11, is required.
Pin Coverage
All pins are included in the boundary scan chain, except the following:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
TCK
TMS
TDI
TDO
TRSTN
VDD
VSS
PLL_VDD
PLL_VSS
RTC_VDD
XIN
XOUT
RTC_XIN
RTC_XOUT
LOOP_FILT
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Boundary Scan Cell Functionality
The boundary scan cells implemented are analogous to cell BC_1, defined in the Standard
VHDL Package STD_1149_1_2001.
All boundary scan cells are of the type control-and-observe; they provide both controlla-
bility and observability for the pins to which they are connected. For open-drain outputs
and bidirectional pins, this type includes controllability and observability of output
enables.
Chain Sequence and Length
When enabled to shift data, the boundary scan shift register is connected to TDI at the
input line for TRIGOUT and to TDO at PD0. The shift register is arranged so that data is
shifted via the pins starting to the left of the OCI interface pins and proceeding clockwise
around the chip. If a pin features multiple scannable bits (example: bidirectional pins or
open-drain output pins), the data is shifted first into the input signal, then the output, then
the output enable (OEN).
The boundary scan register is 213 bits wide. Table 152 shows the ordering of bits in the
shift register, numbering them in clockwise order.
Table 152. Pin to Boundary Scan Cell Mapping
Pin
Direction Scan Cell No
Pin
Direction Scan Cell No
TRIGOUT
TRIGOUT
TRIGOUT
HALT_SLP
BUSACK
BUSREQ
NMI
Input
Output
OEN
0
1
MII_TxD2
MII_TxD3
MII_COL
MII_CRS
PA7
Output
Output
Input
107
108
109
110
111
112
113
114
115
116
117
2
Output
Output
Input
3
Input
4
Input
5
PA7
Output
OEN
Input
6
PA7
RESET
Input
7
PA6
Input
RESET_OUT
WAIT
Output
Input
8
PA6
Output
OEN
9
PA6
INSTRD
Notes:
Output
10
PA5
Input
1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are
associated with the least-significant bit that they control.
2. Direction on the data bus is controlled by a single output enable. It is associated in this table with D[0].
3. MREQ, IORQ, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.
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Table 152. Pin to Boundary Scan Cell Mapping (Continued)
Pin
WR
WR
RD
Direction Scan Cell No
Pin
Direction Scan Cell No
Output
OEN
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PA5
PA5
PA4
PA4
PA4
PA3
PA3
PA3
PA2
PA2
PA2
PA1
PA1
PA1
PA0
PA0
PA0
PHI
PHI
SCL
SCL
SDA
SDA
PB7
PB7
PB7
Output
OEN
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
Output
Input
Input
MREQ
MREQ
IORQ
IORQ
D7
Output
OEN
Output
Input
Input
Output
Input
Output
OEN
D7
Output
Input
Input
D6
Output
OEN
D6
Output
Input
D5
Input
D5
Output
Input
Output
OEN
D4
D4
Output
Input
Input
D3
Output
OEN
D3
Output
Input
D2
Output
OEN
D2
Output
Input
D1
Input
D1
Output
Input
Output
Input
D0
D0
Output
OEN
Output
Input
D0
CS3
CS2
Notes:
Output
Output
Output
OEN
1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are
associated with the least-significant bit that they control.
2. Direction on the data bus is controlled by a single output enable. It is associated in this table with D[0].
3. MREQ, IORQ, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.
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Table 152. Pin to Boundary Scan Cell Mapping (Continued)
Pin
Direction Scan Cell No
Pin
Direction Scan Cell No
CS1
CS0
A23
A23
A22
A22
A21
A21
A20
A20
A19
A19
A18
A18
A17
A17
A16
A16
A16
A15
A15
A14
A14
A13
A13
A12
Notes:
Output
Output
Input
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
PB6
PB6
PB6
PB5
PB5
PB5
PB4
PB4
PB4
PB3
PB3
PB3
PB2
PB2
PB2
PB1
PB1
PB1
PB0
PB0
PB0
PC7
PC7
PC7
PC6
PC6
Input
Output
OEN
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
Output
Input
Input
Output
OEN
Output
Input
Input
Output
Input
Output
OEN
Output
Input
Input
Output
OEN
Output
Input
Input
Output
Input
Output
OEN
Output
Input
Input
Output
OEN
Output
OEN
Input
Input
Output
OEN
Output
Input
Input
Output
Input
Output
OEN
Output
Input
Input
Output
1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are
associated with the least-significant bit that they control.
2. Direction on the data bus is controlled by a single output enable. It is associated in this table with D[0].
3. MREQ, IORQ, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.
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Table 152. Pin to Boundary Scan Cell Mapping (Continued)
Pin
A12
A11
A11
A10
A10
A9
Direction Scan Cell No
Pin
Direction Scan Cell No
Output
Input
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PC6
PC5
PC5
PC5
PC4
PC4
PC4
PC3
PC3
PC3
PC2
PC2
PC2
PC1
PC1
PC1
PC0
PC0
PC0
PD7
PD7
PD7
PD6
PD6
PD6
PD5
OEN
Input
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
Output
Input
Output
OEN
Output
Input
Input
Output
OEN
A9
Output
Input
A8
Input
A8
Output
OEN
Output
OEN
A8
A7
Input
Input
A7
Output
Input
Output
OEN
A6
A6
Output
Input
Input
A5
Output
OEN
A5
Output
Input
A4
Input
A4
Output
Input
Output
OEN
A3
A3
Output
Input
Input
A2
Output
OEN
A2
Output
Input
A1
Input
A1
Output
Input
Output
OEN
A0
A0
Output
Input
Notes:
1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are
associated with the least-significant bit that they control.
2. Direction on the data bus is controlled by a single output enable. It is associated in this table with D[0].
3. MREQ, IORQ, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.
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Table 152. Pin to Boundary Scan Cell Mapping (Continued)
Pin
Direction Scan Cell No
Pin
Direction Scan Cell No
A0
OEN
Input
89
90
PD5
PD5
PD4
PD4
PD4
PD3
PD3
PD3
PD2
PD2
PD2
PD1
PD1
PD1
PD0
PD0
PD0
Output
OEN
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
WP
MII_MDIO
MII_MDIO
MII_MDIO
MII_MDC
MII_RxD3
MII_RxD2
MII_RxD1
MII_RxD0
MII_Rx_DV
MII_Rx_CLK
MII_Rx_ER
MII_Tx_ER
MII_Tx_CLK
MII_Tx_EN
MII_TxD0
MII_TxD1
Notes:
Input
91
Input
Output
OEN
92
Output
OEN
93
Output
Input
94
Input
95
Output
OEN
Input
96
Input
97
Input
Input
98
Output
OEN
Input
99
Input
100
101
102
103
104
105
106
Input
Input
Output
OEN
Output
Input
Input
Output
Output
Output
Output
OEN
1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are
associated with the least-significant bit that they control.
2. Direction on the data bus is controlled by a single output enable. It is associated in this table with D[0].
3. MREQ, IORQ, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.
Usage
Boundary scan functionality is utilized by issuing the appropriate Test Access Port (TAP)
instruction and shifting data accordingly. Both of these steps are accomplished using the
JTAG interface. To activate the TAP (see the OCI Activation section on page 257), the
TCK pin must be driven Low at least two CPU system clock cycles prior to the deassertion
of the RESET pin. Otherwise the OCI-JTAG features are disabled.
Per the IEEE 1149.1 specification, the boundary scan cells capture system I/O on the ris-
ing edge of TCK during the CAPTURE_DR state. This captured data is shifted on the ris-
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ing edge of TCK while in the SHIFT_DR state. Pins and logic receive shifted data only
when enabled, and only on the falling edge of TCK during the UPDATE_DR state, after
shifting is completed.
For more information about eZ80F91 boundary scan support, refer to the Zilog application
note titled Using BSDL Files with eZ80 and eZ80Acclaim! Devices (AN0114).
Boundary Scan Instructions
The eZ80F91 device’s boundary scan architecture supports the following instructions:
•
•
•
•
•
BYPASS (required)
SAMPLE (required)
EXTEST (required)
PRELOAD (required)
IDCODE (optional)
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Phase-Locked Loop
The Phase-Locked-Loop (PLL) is a programmable frequency multiplier that satisfies the
equation SCLK (Hz) = N * FOSC (Hz). Figure 57 shows the PLL block diagram.
System Clock
(F
< SCLK < F
* N)
OSC
OSC
PLL_CTL1[0] = PLL Enable
SCLK-MUX
RTC_CLK
(1MHz < F
< 10MHz)
OSC
x2
Charge
Pump
Off-Chip
Loop Filter
Oscillator
PFD
VCO
x1
RPLL
CPLL1
PLL_CTL0[7:6]
Lock
Detect
CPLL2
PLL_INT
Div N
PLL_CTL0[3:2]
{PLL_DIV_H, PLL_DIV_L}
Figure 57. Phase-Locked Loop Block Diagram
PLL includes seven main blocks as listed below:
•
•
•
•
•
•
•
Phase Frequency Detector
Charge Pump
Voltage-Controlled Oscillator
Loop Filter
Divider
MUX/CLK Sync
Lock Detect
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Phase Frequency Detector
The Phase Frequency Detector (PFD) is a digital block. The two inputs are the reference
clock (XTAL oscillator; see the On-Chip Oscillators chapter on page 332) and the PLL
divider output. The two outputs drive the internal charge pump and represent the error (or
difference) between the falling edges of the PFD inputs.
Charge Pump
The Charge Pump is an analog block that is driven by two digital inputs from the PFD that
control its programmable current sources. The internal current source contains four pro-
grammable values: 1.5 mA, 1 mA, 500 µA, and 100 µA. These values are selected by
PLL_CTRL1[7:6]. The selected current drive is sinked/sourced onto the loop-filter node
according to the error (or difference) between the falling edges of the PFD inputs. Ideally,
when the PLL is locked, there are no errors (error = 0) and no current is sourced/sinked
onto the loop-filter node.
Voltage-Controlled Oscillator
The Voltage-Controlled Oscillator (VCO) is an analog block that exhibits an output fre-
quency proportional to its input voltage. The VCO input is driven from the charge pump
and filtered via the off-chip loop filter.
Loop Filter
The Loop Filter comprises off-chip passive components (usually 1 resistor and 2 capaci-
tors) that filter/integrate charge from the internal charge pump. The filtered node also
drives the VCO input, which creates a proportional frequency output. When PLL is not
used, the Loop Filter pin must not be connected.
Divider
The Divider is a digital, programmable downcounter. The divider input is driven by the
VCO. The divider output drives the PFD. The function of the Divider is to divide the fre-
quency of its input signal by a programmable factor N and supply the result in its output.
MUX/CLK Sync
The MUX/CLK Sync is a digital, software-controllable multiplexer that selects between
PLL or the XTAL oscillator as the system clock (SCLK). A PLL source is selected only
after the PLL is locked (via the lock detect block) to allow glitch-free clock switching.
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Lock Detect
The Lock Detect digital block analyzes the PFD output for a locked condition. The PLL
block of the eZ80F91 device is considered locked when the error (or difference) between
the reference clock and divided-down VCO is less than the minimum timing lock criteria
for the number of consecutive reference clock cycles. The lock criteria is selected in the
PLL Control Register, PLL_CTL0[LDS_CTL]. When the locked condition is met, this
block outputs a logic High signal (lock) that interrupts the CPU.
PLL Normal Operation
By default (after system reset) the PLL is disabled and SCLK = XTAL oscillator. Ensuring
proper loop filter, supply voltages and external oscillator are correctly configured, the PLL
is enabled. The SCLK/Timer cannot choose the PLL as its source until the PLL is locked,
as determined by the lock detect block. By forcing the PLL to be locked prior to enabling
the PLL as a SCLK/Timer source, it is assured to be stable and accurate.
Figure 58 shows the programming flow for normal PLL operation.
POR/System
Reset
Execute instructions with
SCLK = XTAL Oscillator
Program:
{PLL Divider}
PLL_DIV_L then PLL_DIV_H
{Charge Pump & Lock criteria}
PLL_CTL0
Enable:
{Interrupts & PLL}
PLL_CTL1
Upon Lock Interrupt:
Set SCLK MUX to PLL (PLL_CTL0)
Disable Lock Interrupt Mask
(PLL_CTL1)
Execute Application Code
Figure 58. Normal PLL Programming Flow
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Power Requirement to the Phase-Locked Loop Function
Regardless of whether or not you chooses to use the PLL module block as a clock source
for the eZ80F91 ASSP device, the PLL_VDD (pin 87) must be connected to a VDD supply
and the PLL_VSS (pin 84) must be connected to a VSS supply for proper operation of the
eZ80F91 using any system clock source.
PLL Registers
This section describes the PLL control registers.
PLL Divider Control High and Low Byte Registers
This register is designed such that the 11 bit divider value is loaded into the divider mod-
ule whenever the PLL_DIV_H Register is written. Therefore, the procedure must be to
load the PLL_DIV_L Register, followed by the PLL_DIV_H Register, for the divider to
receive the appropriate value.
The divider is designed such that any divider value less than two is ignored; a value of two
is used in its place.
The least-significant byte of PLL divider N is set via the corresponding bits in the
PLL_DIV_L Register. See Tables 153 and 154.
Note: The PLL Divider Register is written only when the PLL is disabled. A read-back of the
PLL Divider registers returns 0.
Table 153. PLL Divider Low Byte Registers (PLL_DIV_L)
Bit
7
6
5
4
3
2
1
0
Field
PLL_DIV_L
Reset
0
0
0
0
0
0
1
0
R/W
W
W
W
W
W
W
W
W
Address
Note: W = write only.
005Ch
Bit
Description
PLL Divider Low Byte
[7:0]
PLL_DIV_L
00h–FFh: These bits represent the low byte of the 11 bit PLL divider value. The complete
PLL divider value is returned by {PLL_DIV_H, PLL_DIV_L}.
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Table 154. PLL Divider High Byte Registers (PLL_DIV_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
Reserved
PLL_DIV_H
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Address
005Dh
Note: R = read only; R/W = read/write.
Bit
Description
Reserved
[7:3]
These bits are reserved and must be programmed to 00h.
[2:0]
PLL_DIV_H
PLL Divider High Byte
0h–7h: These bits represent the high byte of the 11 bit PLL divider value. The complete
PLL divider value is returned by {PLL_DIV_H, PLL_DIV_L}.
PLL Control Register 0
The charge pump program, lock detect sensitivity, and system clock source selections are
set using this register. A brief description of each of these PLL Control Register 0 attri-
butes is listed below, and further described in Table 155.
Charge Pump Program (CHRP_CTL)
Selects one of four values of charge pump current.
Lock Detect Sensitivity (LDS_CTL)
Determines the lock criteria for the PLL.
System Clock Source (CLK_MUX)
Selects the system clock source from a choice of the external crystal oscillator (XTAL),
PLL, or Real-Time Clock crystal oscillator.
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Table 155. PLL Control Register 0 (PLL_CTL0)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
CHRP_CTL1
Reserved
LDS_CTL1
CLK_MUX
0
0
0
0
0
0
0
0
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Address
005Eh
Note: R = read only; R/W = read/write.
Bit
Description
[7:6]
Charge Pump
CHRP_CTL1 00: Charge pump current = 100µA.
01: Charge pump current = 500µA.
10: Charge pump current = 1.0mA.
11: Charge pump current = 1.5mA.
[5:4]
Reserved
These bits are reserved and must be programmed to 00.
[3:2]
LDS_CTL1
Lock Control
00: Lock criteria: 8 consecutive cycles of 20ns.
01: Lock criteria: 16 consecutive cycles of 20ns.
10: Lock criteria: 8 consecutive cycles of 400ns.
11: Lock criteria: 16 consecutive cycles of 400ns.
[1:0]
CLK_MUX
Clock Source
00: System clock source is the external crystal oscillator.
01: System clock source is the PLL .
2
10: System clock source is the Real-Time Clock crystal oscillator.
11: Reserved (previous select is preserved).
Notes:
1. Bits are programmed only when the PLL is disabled. The PLL is disabled when PLL_CTL1 bit 0 is equal to 0.
2. PLL cannot be selected when disabled or out of lock.
PLL Control Register 1
The PLL is enabled using this register. PLL lock-detect status, the PLL interrupt signals
and the PLL interrupt enables are accessed via this register. A brief description of each of
these PLL Control Register 1 attributes is listed below, and further described in Table 156.
Lock Status (LCK_STATUS)
The current lock bit out of the PLL is synchronized and read via this bit.
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Interrupt Lock (INT_LOCK)
This signal feeds the interrupt line out of the CLKGEN module and indicates that a rising
edge on the lock signal out of the PLL has been observed.
Interrupt Unlock (INT_UNLOCK)
This signal feeds the interrupt line out of the clkgen module and indicates that a falling
edge on the lock signal out of the PLL has been observed.
Interrupt Lock Enable (INT_LOCK_EN)
This signal enables the interrupt lock bit.
Interrupt Unlock Enable (INT_UNLOCK_EN)
This signal enables the interrupt unlock bit.
PLL Enable (PLL_ENABLE)
Enables/disables the PLL.
Table 156. PLL Control Register 1 (PLL_CTL1)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
0
0
0
0
0
0
0
0
R
R
R
R/W
R/W
R/W
R/W
R/W
Address
005Fh
Note: R = read only; R/W = read/write.
Bit
Description
Reserved
[7:6]
These bits are reserved and must be programmed to 00.
[5]
PLL Lock Status
0: PLL is currently out of lock.
1: PLL is currently locked.
LCK_STATUS
[4]
INT_LOCK
Lock Mode Interrupt
0: Lock signal from PLL has not risen since last time register was read.
1: Interrupt generated when PLL enters LOCK Mode. Held until register is read.
[3]
Unlock Mode Interrupt
0: Lock signal from PLL has not fallen since last time register was read
1: Interrupt generated when PLL goes out of lock. Held until register is read.
INT_UNLOCK
Note: *PLL cannot be disabled if the CLK_MUX bit of PLL_CTL0[1:0] is set to 01, because the PLL is selected as the
clock source.
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Bit
Description (Continued)
PLL Lock Interrupt Enable
[2]
INT_LOCK_EN
0: Interrupt generation for PLL locked condition (Bit 4) is disabled.
1: Interrupt generation for PLL locked condition is enabled.
[1]
PLL Unlock Interrupt Enable
INT_UNLOCK_EN 0: Interrupt generation for PLL unlocked condition (Bit 3) is disabled.
1: Interrupt generation for PLL unlocked condition is enabled.
[0]
PLL Enable
0: PLL is disabled.*
1: PLL is enabled.
PLL_ENABLE
Note: *PLL cannot be disabled if the CLK_MUX bit of PLL_CTL0[1:0] is set to 01, because the PLL is selected as the
clock source.
PLL Characteristics
The operating and testing characteristics for the PLL are described in Table 157.
Table 157. PLL Characteristics
Symbol
Parameter
Test Condition
3.0 < V < 3.6
0.6 < PD_OUT < V – 0.6
PLL_CTL0[7:6] = 11
Min
Typ
Max Units
I
I
I
I
I
I
I
High level output current for
CP_OUT pin (programmed
value ±42%)
–0.86 –1.50 –2.13 mA
OHCP_OUT
OLCP_OUT
OHCP_OUT
OLCP_OUT
OHCP_OUT
OLCP_OUT
OHCP_OUT
DD
DD
Low level output current for
CP_OUT pin (programmed
value ±42%)
3.0 < V <3.6
0.86 1.50 2.13
mA
DD
0.6 < PD_OUT < V – 0.6
PLL_CTL0[7:6] = 11
DD
High level output current for
CP_OUT pin (programmed
value ±42%)
3.0 < V <3.6
–0.42 –1.0 –1.42 mA
DD
0.6 < PD_OUT < V – 0.6
PLL_CTL0[7:6] = 10
DD
Low level output current for
CP_OUT pin (programmed
value ±42%)
3.0 < V <3.6
0.42
1.0
1.42
mA
µA
µA
µA
DD
0.6 < PD_OUT <V – 0.6
PLL_CTL0[7:6] = 10
DD
High level output current for
CP_OUT pin (programmed
value ±42%)
3.0 < V <3.6
–210 –500 –710
DD
0.6 < PD_OUT <V – 0.6
PLL_CTL0[7:6] = 01
DD
Low level output current for
CP_OUT pin (programmed
value ±42%)
3.0 < V <3.6
210
500
710
DD
0.6 < PD_OUT <V – 0.6
PLL_CTL0[7:6] = 01
DD
High level output current for
CP_OUT pin (programmed
value ±42%)
3.0 < V <3.6
–42 –100 –142
DD
0.6 < PD_OUT <V – 0.6
PLL_CTL0[7:6] = 00
DD
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Table 157. PLL Characteristics (Continued)
Test Condition
Symbol
Parameter
Min
Typ
Max Units
I
Low level output current for
CP_OUT pin (programmed
value ±42%)
3.0 < V <3.6
0.6 < PD_OUT <V – 0.6
PLL_CTL0[7:6] = 00
42
100
142
µA
OLCP_OUT
DD
DD
Match
I
–I
3.0 < V <3.6
–15
+15
%
OHCP_OUT OLCP_OUT
DD
current match
0.6 < CP_OUT <V – 0.6
DD
PLL_CTL0[7:6] = XX
I
Tristate leakage on CP_OUT CP_OUT tristated
output pin
–1
1
µA
LCP_OUT
F
F
Crystal oscillator frequency
VCO frequency
PLL_CTL0[5:4] = 01
1 M
10 M
Hz
OSC
VCO
Recommended operating
conditions
50
MHz
G
VCO Gain
Recommended operating
conditions
36
45
120 MHz/
V
VCO
D1
SCLK Duty Cycle from PLL or Recommended operating
XTAL Oscillator Source
50
55
%
ps
s
conditions
T1A
Lock2
PLL Clock Jitter
F
= 50MHz. XTALOSC
350
500
VCO
= 10 MHz
F = 50MHz. XTALOSC =
VCO
PLL Lock-Time
3.579 MHz
C
C
= 220 pF, R = 499¾,
= 0.056 µF
pll1
pll2
pll
I
I
I
I
(XTL)
(XTL)
(XTL)
(XTL)
High-level Output Current for
XTAL2 pin
V
= V –0.4 V
–0.3
0.6
mA
mA
mA
mA
V
OH1
OL1
OH2
OL2
oH
DD
PLL_CTL0[5:4] = 01
V = 0.4 V
oL
PLL_CTL0[5:4] = 01
V = V –0.4 V
oH
PLL_CTL0[5:4] = 11
V = 0.4 V
oL
PLL_CTL0[5:4] = 11
F = 3.579 MHz
OSC
Low-level Output Current for
XTAL2 pin
High-level Output Current for
XTAL2 pin
DD
Low-level Output Current for
XTAL2 pin
V
Peak-to-peak voltage under
PP3M
(XTL)
oscillator conditions for XTAL2 Cx1 = 10 pF
pin
Cx2 = 10 pF
V
Peak-to-peak voltage under
F
OSC
= 10 MHz
V
PP10M
(XTL)
oscillator conditions for XTAL2 Cx1 = 10 pF
pin
Cx2 = 10 pF
PS027004-0613
P R E L I M I N A R Y
Phase-Locked Loop
eZ80F91 ASSP
Product Specification
274
Table 157. PLL Characteristics (Continued)
Test Condition
Symbol
Parameter
Min
Typ
Max Units
Cxtal1
(package
Capacitance measured from T = 25ºC
XTAL1 pin to GND
pF
type)
C
Capacitance measured from T = 25ºC
XTAL2 pin to GND
pF
pF
xtal2
(package
type)
C
Capacitance measured from T = 25ºC
loop filter pin to GND
loop
(package
type)
Not all conditions are tested in production test. The values in Table 157 are for design and
characterization only.
Note:
PS027004-0613
P R E L I M I N A R Y
Phase-Locked Loop
eZ80F91 ASSP
Product Specification
275
eZ80 CPU Instruction Set
Tables 158 through 167 indicate the CPU instructions available for use with the eZ80F91
ASSP device. The instructions are grouped by class. For more information, refer to the
eZ80 CPU User Manual (UM0077), which is available free for download from the Zilog
website.
Table 158. Arithmetic Instructions
Mnemonic
ADC
ADD
CP
Instruction
Add with Carry
Add without Carry
Compare with Accumulator
Decimal Adjust Accumulator
Decrement
DAA
DEC
INC
Increment
MLT
Multiply
NEG
SBC
SUB
Negate Accumulator
Subtract with Carry
Subtract without Carry
Table 159. Bit Manipulation Instructions
Mnemonic
BIT
Instruction
Bit Test
RES
Reset Bit
Set Bit
SET
Table 160. Block Transfer and Compare Instructions
Mnemonic
Instruction
CPD (CPDR)
CPI (CPIR)
LDD (LDDR)
LDI (LDIR)
Compare and Decrement (with Repeat)
Compare and Increment (with Repeat)
Load and Decrement (with Repeat)
Load and Increment (with Repeat)
PS027004-0613
P R E L I M I N A R Y
eZ80 CPU Instruction Set
eZ80F91 ASSP
Product Specification
276
Table 161. Exchange Instructions
Mnemonic
EX
Instruction
Exchange registers
EXX
Exchange CPU multibyte register banks
Table 162. Input/Output Instructions
Mnemonic
IN
Instruction
Input from I/O
IN0
Input from I/O on Page 0
IND (INDR)
INDRX
Input from I/O and Decrement (with Repeat)
Input from I/O and Decrement Memory Address with Stationary I/O Address
Input from I/O and Decrement (with Repeat)
Input from I/O and Decrement (with Repeat)
Input from I/O and Increment (with Repeat)
Input from I/O and Increment Memory Address with Stationary I/O Address
Input from I/O and Increment (with Repeat)
Input from I/O and Increment (with Repeat)
Output to I/O and Decrement (with Repeat)
Output to I/O and Decrement Memory Address with Stationary I/O Address
Output to I/O and Increment (with Repeat)
Output to I/O and Increment Memory Address with Stationary I/O Address
Output to I/O
IND2 (IND2R)
INDM (INDMR)
INI (INIR)
INIRX
INI2 (INI2R)
INIM (INIMR)
OTDM (OTDMR)
OTDRX
OTIM (OTIMR)
OTIRX
OUT
OUT0
Output to I/0 on Page 0
OUTD (OTDR)
OUTD2 (OTD2R)
OUTI (OTIR)
OUTI2 (OTI2R)
TSTIO
Output to I/O and Decrement (with Repeat)
Output to I/O and Decrement (with Repeat)
Output to I/O and Increment (with Repeat)
Output to I/O and Increment (with Repeat)
Test I/O
PS027004-0613
P R E L I M I N A R Y
eZ80 CPU Instruction Set
eZ80F91 ASSP
Product Specification
277
Table 163. Load Instructions
Mnemonic
LD
Instruction
Load
LEA
Load Effective Address
PEA
Push Effective Address
POP
Pop
PUSH
Push
Table 164. Logic Instructions
Mnemonic
AND
Instruction
Logic AND
CPL
Complement Accumulator
Logic OR
OR
TST
Test Accumulator
Logic Exclusive OR
XOR
Table 165. Processor Control Instructions
Mnemonic
CCF
DI
Instruction
Complement Carry Flag
Disable Interrupts
Enable Interrupts
Halt
EI
HALT
IM
Interrupt Mode
NOP
RSMIX
SCF
No Operation
Reset Mixed-Memory Mode Flag
Set Carry Flag
SLP
Sleep
STMIX
Set Mixed-Memory Mode Flag
PS027004-0613
P R E L I M I N A R Y
eZ80 CPU Instruction Set
eZ80F91 ASSP
Product Specification
278
Table 166. Program Control Instructions
Mnemonic
CALL
CALL cc
DJNZ
JP
Instruction
Call Subroutine
Conditional Call Subroutine
Decrement and Jump if Nonzero
Jump
JP cc
JR
Conditional Jump
Jump Relative
JR cc
RET
Conditional Jump Relative
Return
RET cc
RETI
Conditional Return
Return from Interrupt
Return from nonmaskable interrupt
Restart
RETN
RST
Table 167. Rotate and Shift Instructions
Mnemonic
RL
Instruction
Rotate Left
RLA
Rotate Left–Accumulator
Rotate Left Circular
Rotate Left Circular–Accumulator
Rotate Left Decimal
Rotate Right
RLC
RLCA
RLD
RR
RRA
RRC
RRCA
RRD
SLA
Rotate Right–Accumulator
Rotate Right Circular
Rotate Right Circular–Accumulator
Rotate Right Decimal
Shift Left Arithmetic
Shift Right Arithmetic
Shift Right Logic
SRA
SRL
PS027004-0613
P R E L I M I N A R Y
eZ80 CPU Instruction Set
eZ80F91 ASSP
Product Specification
279
Op Code Map
Tables 168 through 174 list the hex values for each of the eZ80 instructions.
Table 168. Op Code Map: First Op Code
Legend
Upper
Lower Op Code Nibble
4
Op Code
Nibble
AND
A,H
Mnemonic
A
Second Operand
First Operand
Lower Nibble (Hex)
0
NOP
0
1
LD
2
LD
3
INC
4
INC
B
5
DEC
B
6
LD
B,n
7
8
EX
9
ADD
A
LD
B
DEC
C
INC
C
D
DEC
C
E
LD
C,n
F
RRC
A
RLCA
BC, (BC),A BC
Mmn
AF,AF’ HL,BC A,(BC) BC
DJNZ
d
LD
LD
INC
INC
D
DEC
D
LD
D,n
RLA
DAA
SCF
LD
JR
d
ADD
LD
DEC
INC
E
DEC
E
LD
E,n
RRA
CPL
CCF
LD
1
2
3
DE, (DE),A DE
Mmn
LD
HL, (Mmn), HL
Mmn
LD
SP, (Mmn), SP
Mmn
LD
B,C
LD
D,C
LD
HL,DE A,(DE) DE
JR
NZ,d
LD
INC
INC
H
DEC
H
LD
H,n
JR
Z,d
ADD
HL,HL HL,
(Mmn)
LD
DEC
HL
INC
L
DEC
L
LD
L,n
HL
LD
JR
NC,d
INC
INC
(HL)
DEC
(HL) (HL),n
LD
JR
ADD
LD
A,
(Mmn)
LD
C,D
LD
E,D
LD
L,D
LD
DEC
SP
INC
A
DEC
A
LD
A,n
CF,d HL,SP
A
LD
B,D
.SIL
suffix
LD
.SIS
suffix
LD
D,B
LD
LD
B,E
LD
D,E
LD
LD
B,H
LD
D,H
LD
LD LD
LD
C,B
LD
E,B
LD
.LIS
suffix
LD
E,C
LD
LD
C,E
.LIL
suffix
LD
LD
C,H
LD
E,H
LD
LD
LD
4
5
6
7
8
9
A
B
B,L B,(HL) B,A
LD LD LD
D,L D,(HL) D,A
LD LD LD
H,L H,(HL) H,A
C,L C,(HL) C,A
LD LD LD
E,L E,(HL) E,A
LD
L,L
LD
LD
L,(HL) L,A
LD LD
LD
H,B
LD
H,C
LD
H,D
LD
H,E
LD
H,H
LD
L,B
LD
L,C
LD
L,E
LD
L,H
LD
LD
HALT
LD
(HL),B (HL),C (HL),D (HL),E (HL),H (HL),L
(HL),A A,B
A,C
ADC
A,C
SBC
A,C
XOR
A,C
CP
A,D
ADC
A,D
SBC
A,D
XOR
A,D
CP
A,E
ADC
A,E
SBC
A,E
XOR
A,E
CP
A,H
ADC
A,H
SBC
A,H
XOR XOR
A,H
CP
A,L A,(HL) A,A
ADC ADC ADC
A,L A,(HL) A,A
SBC SBC SBC
A,L A,(HL) A,A
XOR XOR
A,L A,(HL) A,A
CP CP CP
A,L A,(HL) A,A
ADD
A,B
SUB
A,B
AND
A,B
OR
A,B
RET
NZ
ADD
A,C
SUB
A,C
AND
A,C
OR
A,C
POP
BC
ADD
A,D
SUB
A,D
AND
A,D
OR
A,D
JP
NZ,
Mmn
JP
ADD
A,E
SUB
A,E
AND
A,E
OR
A,E
JP
Mmn
ADD
A,H
SUB
A,H
AND
A,H
OR
ADD
ADD
ADD
ADC
A,B
SBC
A,B
XOR
A,B
CP
A,L A,(HL) A,A
SUB SUB SUB
A,L A,(HL) A,A
AND AND AND
A,L A,(HL) A,A
OR OR OR
A,L A,(HL) A,A
A,H
A,B
RET
Z
A,C
RET
A,D
JP
A,E
See
A,H
CALL PUSH ADD
NZ,
Mmn
RST
00h
CALL CALL ADC RST
C
D
E
F
BC
A,n
Z, Table Z,
Mmn
A,n
08h
Mmn 169 Mmn
RET
NC
POP
DE
OUT CALL PUSH SUB
(n),A
RST
10h
RET
CF
EXX
JP
CF,
Mmn
JP
IN
A,(n)
CALL
See
SBC RST
NC,
Mmn
JP
NC,
Mmn
DE
A,n
CF, Table A,n
Mmn 170
18h
RET
PO
POP
HL
EX
CALL PUSH AND
RST
20h
RET
PE
JP
(HL)
EX
CALL
See
XOR RST
PO, (SP),H PO,
HL
A,n
PE, DE,HL PE, Table A,n
Mmn
JP
M,
Mmn
28h
Mmn
JP
P,
L
DI
Mmn
CALL PUSH
Mmn 171
RET
P
POP
AF
OR
A,n
RST
30h
RET
M
LD
SP,HL
EI
CALL
M,
See
Table
172
CP
A,n
RST
38h
P,
AF
Mmn
Mmn
Mmn
Note: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.
PS027004-0613
P R E L I M I N A R Y
eZ80 CPU Instruction Set
eZ80F91 ASSP
Product Specification
280
Table 169. Op Code Map: Second Op Code after 0CBh
Legend
Upper
Lower Nibble of 2nd Op Code
Nibble
of Second
Op Code
4
RES
4,H
Mnemonic
A
First Operand
Second Operand
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RLC RLC RLC RLC RLC RLC RLC RLC RRC RRC RRC RRC RRC RRC RRC RRC
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
B
RL
B
C
RL
C
D
RL
D
E
RL
E
H
RL
H
L
RL
L
(HL)
RL
(HL)
SLA
(HL)
A
RL
A
B
RR
B
C
RR
C
D
RR
D
E
RR
E
H
RR
H
L
RR
L
(HL)
RR
(HL)
A
RR
A
SLA
B
SLA
C
SLA
D
SLA
E
SLA
H
SLA
L
SLA
A
SRA SRA SRA SRA SRA SRA SRA SRA
B
C
D
E
H
L
SRL
L
(HL)
SRL
(HL)
BIT
A
SRL
A
SRL
B
SRL
C
SRL
D
SRL
E
SRL
H
BIT
0,B
BIT
2,B
BIT
4,B
BIT
6,B
BIT
0,C
BIT
2,C
BIT
4,C
BIT
6,C
BIT
0,D
BIT
2,D
BIT
4,D
BIT
6,D
BIT
0,E
BIT
2,E
BIT
4,E
BIT
6,E
BIT
0,H
BIT
2,H
BIT
4,H
BIT
6,H
BIT
BIT
BIT
BIT
1,B
BIT
3,B
BIT
5,B
BIT
7,B
BIT
1,C
BIT
3,C
BIT
5,C
BIT
7,C
BIT
1,D
BIT
3,D
BIT
5,D
BIT
7,D
BIT
1,E
BIT
3,E
BIT
5,E
BIT
7,E
BIT
1,H
BIT
3,H
BIT
5,H
BIT
7,H
BIT
BIT
0,L 0,(HL) 0,A
BIT BIT BIT
2,L 2,(HL) 2,A
BIT BIT BIT
4,L 4,(HL) 4,A
BIT BIT BIT
6,L 6,(HL) 6,A
1,L 1,(HL) 1,A
BIT BIT BIT
3,L 3,(HL) 3,A
BIT BIT BIT
5,L 5,(HL) 5,A
BIT BIT BIT
7,L 7,(HL) 7,A
RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES
0,B 0,C 0,D 0,E 0,H 0,L 0,(HL) 0,A 1,B 1,C 1,D 1,E 1,H 1,L 1,(HL) 1,A
RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES
2,B 2,C 2,D 2,E 2,H 2,L 2,(HL) 2,A 3,B 3,C 3,D 3,E 3,H 3,L 3,(HL) 3,A
RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES
4,B 4,C 4,D 4,E 4,H 4,L 4,(HL) 4,A 5,B 5,C 5,D 5,E 5,H 5,L 5,(HL) 5,A
RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES
6,B
SET
0,B
6,C
SET
0,C
6,D
SET
0,D
6,E
SET
0,E
6,H
SET
0,H
6,L 6,(HL) 6,A
SET SET SET
0,L 0,(HL) 0,A
SET SET SET
2,L 2,(HL) 2,A
SET SET SET
4,L 4,(HL) 4,A
SET SET SET
6,L 6,(HL) 6,A
7,B
SET
1,B
7,C
SET
1,C
7,D
SET
1,D
7,E
SET
1,E
7,H
SET
1,H
7,L 7,(HL) 7,A
SET SET SET
1,L 1,(HL) 1,A
SET SET SET
3,L 3,(HL) 3,A
SET SET SET
5,L 5,(HL) 5,A
SET SET SET
SET
2,B
SET
2,C
SET
2,D
SET
2,E
SET
2,H
SET
3,B
SET
3,C
SET
3,D
SET
3,E
SET
3,H
SET
4,B
SET
4,C
SET
4,D
SET
4,E
SET
4,H
SET
5,B
SET
5,C
SET
5,D
SET
5,E
SET
5,H
SET
6,B
SET
6,C
SET
6,D
SET
6,E
SET
6,H
SET
7,B
SET
7,C
SET
7,D
SET
7,E
SET
7,H
7,L 7,(HL) 7,A
Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.
PS027004-0613
P R E L I M I N A R Y
eZ80 CPU Instruction Set
eZ80F91 ASSP
Product Specification
281
Table 170. Op Code Map: Second Op Code After 0DDh
Legend
Lower Nibble of 2nd Op Code
Upper
9
LD
SP,IX
Nibble
of Second
Op Code
Mnemonic
F
Second Operand
First Operand
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
LD
8
9
ADD
A
B
C
D
E
F
LD
0
BC,
IX,BC
(IX+d),
(IX+d)
LD
BC
LD
ADD
1
2
DE,
(IX+d)
LD
HL,
(IX+d)
IX,DE
(IX+d),
DE
LD
LD
IX,
Mmn
LD
(Mmn)
INC
IX
INC
IXH
DEC
IXH IXH,n
LD
ADD
IX,IX
LD
IX,
(Mmn)
DEC
IX
INC
IXL
DEC
IXL
LD
IXL,n (IX+d),
HL
,
IX
LD IY,
INC
DEC LD (IX LD IX,
ADD
LD
LD
3
(IX+d)
(IX+d) (IX+d) +d),n (IX+d)
IX,SP
(IX+d), (IX+d),
IY
IX
LD
B,IXH B,IXL (IX+d)
LD LD LD D,
D,IXH D,IXL (IX+d)
LD LD LD H,
LD
LD B,
LD
LD
LD C,
4
5
C,IXH C,IXL (IX+d)
LD LD LD E,
E,IXH E,IXL (IX+d)
LD LD LD L,
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
6
IXH,B IXH,C IXH,D IXH,E IXH,IX IXH,IX (IX+d) IXH,A IXL,B IXL,C IXL,D IXL,E IXL,IX IXL,IX (IX+d) IXL,A
H
L
H
L
LD
LD
LD
LD
LD
LD
LD
(IX+d),
A
LD
LD
LD A,
7 (IX+d), (IX+d), (IX+d), (IX+d), (IX+d), (IX+d),
A,IXH A,IXL (IX+d)
B
C
D
E
H
L
ADD ADD ADD
ADC ADC ADC
8
9
A,IXH A,IXL
A,
A,IXH A,IXL
A,
(IX+d)
SUB
A,
(IX+d)
SBC
A,
SUB
SUB
SBC
SBC
A,IXH A,IXL
A,IXH A,IXL
(IX+d)
(IX+d)
AND AND AND
XOR XOR XOR
A
A,IXH A,IXL
A,
A,IXH A,IXL
A,
(IX+d)
OR OR A,
A,IXH A,IXL (IX+d)
(IX+d)
CP A,
A,IXH A,IXL (IX+d)
OR
CP
CP
B
C
D
Table
173
POP
IX
EX
(SP),I
X
PUSH
IX
JP
(IX)
E
F
LD
SP,IX
Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.
PS027004-0613
P R E L I M I N A R Y
eZ80 CPU Instruction Set
eZ80F91 ASSP
Product Specification
282
Table 171. Op Code Map: Second Op Code After 0EDh
Legend
Lower Nibble of 2nd Op Code
Upper
2
Nibble
of Second
Op Code
SBC
HL,BC
Mnemonic
4
First Operand
Second Operand
Lower Nibble (Hex)
0
1
2
3
LEA
4
TST
5
6
7
LD
8
9
A
B
C
TST
D
E
F
LD
IN0 OUT0 LEA
IN0 OUT0
0
1
2
3
B,(n) (n),B BC,
IX+d IY+d
IN0 OUT0 LEA
D,(n) (n),D DE,
IX+d IY+d
IN0 OUT0 LEA
BC,
A,B
BC,
(HL)
LD
DE,
(HL)
LD
C,(n) (n),C
A,C
(HL),
BC
LD(HL
),
DE
LD
(HL),
HL
LEA
DE,
TST
A,D
IN0 OUT0
E,(n) (n),E
TST
A,E
LEA
HL
TST
A,H
IN0 OUT0
L,(n) (n),L
TST
A,L
H,(n) (n),H
HL
HL,
(HL)
,IX+d ,IY+d
LD IY, LEA
LEA
IY
TST
A,(HL)
LD IX, IN0 OUT0
(HL) A,(n) (n),A
TST
A,A
LD
LD
(HL)
IX
(HL),I (HL),
,IX+d ,IY+d
LD
B,(BC (BC), HL,BC (Mmn)
Y
IX
LD
R,A
IN
OUT SBC
NEG RETN IM 0
LD
I,A
IN
OUT ADC
LD
MLT RETI
BC
C,(C) (C),C HL,BC BC,
(Mmn)
4
5
6
7
)
B
,
BC
LD
IN
OUT SBC
LEA
LEA
IY,
IM 1
LD
A,I
IN
OUT ADC
LD
MLT
DE
IM 2
LD
LD
A,R
D,(BC (BC), HL,DE (Mmn) IX,
E,(C) (C),E HL,DE DE,
(Mmn)
)
D
,
IY+d IX+d
DE
LD
IBN
OUT SBC
TST
PEA PEA RRD
IX+d IY+d
IN
OUT ADC
LD
MLT
HL
LD
RLD
H,(C) (BC), HL,HL (Mmn) A,n
L,(C) (C),L HL,HL HL,
(Mmn)
MB,A A,MB
H
,
HL
SBC
LD TSTIO
SLP
IN
OUT ADC
LD
MLT STMI RSMI
SP
HL,SP (Mmn)
n
A,(C) (C),A HL,SP SP,
(Mmn)
X
X
,
SP
INIM OTIM INI2
INDM OTDM IND2
8
9
INIMR OTIM INI2R
R
INDM OTDM IND2
R
R
R
LDI
CPI
INI
OUTI OUTI2
LDD CPD
IND OUTD OUTD
A
B
C
D
E
F
2
LDIR CPIR INIR OTIR OTI2R
LDDR CPDR INDR OTDR OTD2
R
INIRX OTIR
X
LD
I,HL
LD
INDR OTDR
X
X
HL,I
Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.
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Table 172. Op Code Map: Second Op Code After 0FDh
Legend
Lower Nibble of 2nd Op Code
Upper
9
Nibble
of Second
Op Code
LD
SP,IY
Mnemonic
F
First Operand
Second Operand
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
LD
BC,
(IY+d)
LD
DE,
(IY+d)
LD
8
9
ADD
IY,BC
A
B
C
D
E
F
LD (IY
+d),B
C
LD (IY
+d),D
E
0
ADD
IY,DE
1
LD
LD
INC
IY
INC
IYH
DEC
LD
ADD
IY,IY
LD
IY,
(Mmn)
DEC
IY
INC
IYL
DEC
IYL
LD LD (IY
IYL,n +d),H
L
2
IY,Mm (Mmn)
n
IYH IYH,n HL,
(IY+d)
,IY
LD IX,
(IY+d)
INC
DEC LD (IY LD IY,
ADD
IY,SP
LD (IY LD (IY
+d),IX +d),IY
LD C,
3
4
5
(IY+d) (IY+d) +d),n (IY+d)
LD LD LD B,
B,IYH B,IYL (IY+d)
LD LD LD D,
D,IYH D,IYL (IY+d)
LD LD LD H,
LD
LD
C,IYH C,IYL (IY+d)
LD LD LD E,
E,IYH E,IYL (IY+d)
LD LD LD L,
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
6
7
8
IYH,B IYH,C IYH,D IYH,E IYH,IY IYH,IY (IY+d) IYH,A IYL,B IYL,C IYL,D IYL,E IYL,IY IYL,IY (IY+d) IYL,A
H
L
H
L
LD (IY LD (IY LD (IY LD (IY LD (IY LD (IY
+d),B +d),C +d),D +d),E +d),H +d),L
LD (IY
+d),A
LD
LD
LD A,
A,IYH A,IYL (IY+d)
ADC ADC ADC
ADD ADD ADD
A,IYH A,IYL
A,
A,IYH A,IYL
A,
(IY+d)
(IY+d)
SUB SUB SUB
SBC SBC SBC
9
A,IYH A,IYL
A,
A,IYH A,IYL
A,
(IY+d)
(IY+d)
AND AND AND
XOR XOR XOR
A
A,IYH A,IYL
A,
A,IYH A,IYL
A,
(IY+d)
(IY+d)
OR
OR OR A,
CP
CP CP A,
B
C
D
A,IYH A,IYL (IY+d)
A,IYH A,IYL (IY+d)
Table
174
POP
IY
EX
(SP),I
Y
PUSH
IY
JP
(IY)
E
F
LD
SP,IY
Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.
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Table 173. Op Code Map: Fourth Byte After 0DDh, 0CBh, and dd
Legend
Lower Nibble of 4th Byte
Upper
Nibble
of Fourth
Byte
6
BIT
0,(IX+d)
Mnemonic
4
First Operand
Second Operand
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RLC
(IX+d)
RL
RRC
(IX+d)
RR
0
1
2
3
4
5
6
7
(IX+d)
(IX+d)
SRA
(IX+d)
SRL
(IX+d)
BIT 1,
(IX+d)
BIT 3,
(IX+d)
BIT 5,
(IX+d)
BIT 7,
(IX+d)
RES
1,
SLA
(IX+d)
BIT 0,
(IX+d)
BIT 2,
(IX+d)
BIT 4,
(IX+d)
BIT 6,
(IX+d)
RES
0,
8
9
(IX+d)
RES
2,
(IX+d)
RES
3,
(IX+d)
RES
4,
(IX+d)
RES
6,
(IX+d)
SET
0,
(IX+d)
SET
2,
(IX+d)
SET
4,
(IX+d)
SET
6,
(IX+d)
RES
5,
(IX+d)
RES
7,
(IX+d)
SET
1,
(IX+d)
SET
3,
(IX+d)
SET
5,
(IX+d)
SET
7,
A
B
C
D
E
F
(IX+d)
(IX+d)
Notes: d = 8-bit two’s-complement displacement
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Table 174. Op Code Map: Fourth Byte After 0FDh, 0CBh, and dd
Legend
Lower Nibble of 4th Byte
Upper
Nibble
of Fourth
Byte
6
BIT
0,(IY+d)
Mnemonic
4
1
First Operand
Second Operand
Lower Nibble (Hex)
0
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
RLC
(IY+d)
RL
RRC
(IY+d)
RR
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
(IY+d)
SLA
(IY+d)
(IY+d)
SRA
(IY+d)
SRL
(IY+d)
BIT 1,
(IY+d)
BIT 3,
(IY+d)
BIT 5,
(IY+d)
BIT 7,
(IY+d)
RES 1,
(IY+d)
RES 3,
(IY+d)
RES 5,
(IY+d)
RES 7,
(IY+d)
SET 1,
(IY+d)
SET 3,
(IY+d)
SET 5,
(IY+d)
SET 7,
(IY+d)
BIT 0,
(IY+d)
BIT 2,
(IY+d)
BIT 4,
(IY+d)
BIT 6,
(IY+d)
RES 0,
(IY+d)
RES 2,
(IY+d)
RES 4,
(IY+d)
RES 6,
(IY+d)
SET 0,
(IY+d)
SET 2,
(IY+d)
SET 4,
(IY+d)
SET 6,
(IY+d)
Notes: d = 8-bit two’s-complement displacement
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Ethernet Media Access Controller
The Ethernet Media Access Controller (EMAC) is a full-function 10/100 Mbps media
access control module with a Media-Independent Interface (MII). When communicating
with an external PHY device, the eZ80F91 ASSP uses the MII to gain access to the Ether-
net network.
Figure 59 shows the EMAC block diagram.
MDIO
TxDMA
MDC
TxD
TxCLK
TxFIFO
TxER
TxEN
COL
CRS
MII Interface
RxD
RxCLK
RxDV
RxD
RxD/CTRL
RxER
RxFIFO
Accept
CTRL
RxDMA
Reject
Figure 59. EMAC Block Diagram
For additional information about the Ethernet protocol and using it with the eZ80F91
ASSP, refer to the IEEE 802.3 specification, 1998 edition, Section 22. The eZ80F91 ASSP
supports the IEEE 802.3 protocol with the following exception:
Note:
The eZ80F91 ASSP does not support the Giga Media Independent Interface (GMII)
referred to in the following sections of the IEEE 802.3 1998 version: section 22.1.5, sec-
tion 22.2.4, section 22.2.4.1.2, section 22.2.4.1.5, and section 22.2.4.1.6.
The EMAC is used for many different applications, including network interface, ethernet
switching, and test equipment designs. The EMAC includes the following blocks:
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•
•
•
•
•
Central clock and reset module (not shown in the block diagram)
Host memory interface and transmit/receiver arbiter
FIFO buffer and DMA control blocks for transmit and receive
802.3x media access control block
MII interface management
The media access control block implements 802.3x flow control functions for both trans-
mit and receive.
The MII management module provides a two-wire control/status path to the MII PHY.
read and write communication to and from registers within the PHY is accomplished via
the host interface.
MII PHY is a Physical Layer transceiver device; PHY does not refer to the eZ80F91 sys-
tem clock output pin, PHI.
Note:
The MII management module provides a two-wire control/status path to the MII. Read
and write communication to and from registers within the PHY is accomplished via the
host interface.
EMAC Functional Description
The EMAC block implements memory, arbiter, and transmit and receive direct memory
access functions, and offers four communication modes: HALF-DUPLEX, FULL-
DUPLEX, NIBBLE, and ENDEC. In HALF-DUPLEX and FULL-DUPLEX modes,
throughput occurs at both 10 Mbps and 100 Mbps speeds. Throughput in ENDEC and
NIBBLE modes occurs at 10 Mbps. A brief description of these four modes are as fol-
lows:
10/100 Mbps HALF-DUPLEX Mode
In this mode, data are transferred only in one direction at a time; that is, one can either
transmit or receive, but both cannot occur simultaneously.
10/100 Mbps FULL-DUPLEX Mode
In this mode, data are transmitted and received at the same time.
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10 Mbps ENDEC Mode
This mode affects the MII interface between the PHY and the MAC. In ENDEC Mode, the
RxCLK and TxCLK clocks are bit clocks instead of the normal nibble clock. In NIBBLE
Mode, 4 bits are transferred on each clock. In ENDEC Mode, 1 bit is transferred per clock.
For more information about throughput, see the EMAC and the System Clock section on
page 295.
Memory
EMAC memory is the shared Ethernet memory location of the Transmit and Receive buf-
fers. This memory is broken into two parts: the Tx buffer and the Rx buffer. The Transmit
Lower Boundary Pointer Register, EmacTLBP, is the register that holds the starting
address of the Tx buffer. The Boundary Pointer Register, EmacBP, points to the start of the
Rx buffer (end of Tx buffer + 1). The Receive High Boundary Pointer Register, Emac-
RHBP, points to the end of the Rx buffer + 1. The Tx and Receive buffers are divided into
packet buffers of either 256, 128, 64, or 32 bytes. These buffer sizes are selected by
EmacBufSize Register bits 7 and 6.
The EmacBlksLeft Register contains the number of Receive packet buffers remaining in
the Rx buffer. This buffer is used for software flow control. If the Block_Level is nonzero
(bits 5:0 of the EmacBufSize Register), hardware flow control is enabled. If in FULL-
DUPLEX Mode, the EMAC transmits a pause control frame when the EmacBlksLeft Reg-
ister is less than the Block_Level. In HALF-DUPLEX Mode, the EMAC continually
transmits a nibble pattern of hexadecimal 5’s to jam the channel.
Four pointers are defined for reading and writing the Tx and Rx buffers. The Transmit
Write Pointer, TWP, is a software pointer that points to the next available packet buffer.
The TWP is reset to the value stored in EmacTLBP. The Transmit Read Pointer, TRP, is a
hardware pointer in the Transmit Direct Memory Access Register, TxDMA, that contains
the address of the next packet to be transmitted. It is automatically reset to the EmacTLBP.
The Receive Write Pointer, RWP, is a hardware pointer in the Receive Direct Memory
Access Register, RxDMA, which contains the storage address of the incoming packet. The
RWP pointer is automatically initialized to the Boundary Pointer registers. The Receive
Read Pointer, RRP, is a software pointer to the address location in which the next packet
must be read from. The RRP pointer must be initialized to the Boundary Pointer registers.
For the hardware flow control to function properly, the software must update the hardware
RRP (EmacRrp) pointer whenever the software version is updated. The RxDMA uses
RWP and the RRP to determine how many packet buffers remain in the Rx buffer.
Arbiter
The arbiter controls access to EMAC memory. It prioritizes the requests for memory
access between the CPU, the TxDMA, and the RxDMA. The TxDMA offers two levels of
priority: a high priority when the TxFIFO is less than half full and a Low priority when the
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TxFIFO is more than half full. Similarly, the RxDMA offers two levels of priority: a high
priority when the RxFIFO is more than half full and a Low priority when the RxFIFO is
less than half full.
The arbiter determines resolution between the CPU, the RxDMA, and the TxDMA
requests to access EMAC memory. Post writing for CPU writes results in zero wait state
write access timing when the CPU assumes the highest priority. CPU reads require a mini-
mum of 1 wait state and takes more when the CPU does not hold the highest priority. The
CPU read wait state is not a user-controllable operation, because it is controlled by the
arbiter. The RxDMA and TxDMA requests are not allowed to occur back-to-back. There-
fore, the maximum throughput rate for the two Direct Memory Access (DMA) ports is 25
MBps each (one byte every 2 clocks) when the system clock is running at 50MHz. The
rate is reduced to 20 MBps for a 40MHz system clock. The arbiter uses the internal WAIT
signal to add wait states to CPU access when required. See Table 175.
Table 175. Arbiter Priority
Priority
Level
Device Serviced Flags
0
1
2
3
4
RxDMA High
TxDMA High
RxFIFO > half full (FAF)
TxFIFO < half full (FAE)
®
eZ80 CPU
RxDMA Low
TxDMA Low
RxFIFO < half full (FAE)
TxFIFO > half full (FAF)
TxDMA
The TxDMA module moves the next packet to be transmitted from EMAC memory into
the TxFIFO. Whenever the polling timer expires, the TxDMA reads the High status byte
from the Tx descriptor table pointed to by the Transmit Read Pointer, TRP. Polling contin-
ues until the High status read reaches bit 7, when the Emac_Owns ownership semaphore,
bit 15 of the descriptor table (see Table 179 ) is set to 1. The TxDMA then initializes the
packet length counter with the size of the packet from descriptor table bytes 3 and 4. The
TxDMA moves the data into the TxFIFO until the packet length counter downcounts to
zero. The TxDMA then waits for Transmission Complete signal to be asserted to indicate
that the packet is sent and that the Transmit status from the EMAC is valid. The TxDMA
updates the descriptor table status and resets the ownership semaphore, bit 15. Finally, the
Tx_DONE_STAT bit of the EMAC Interrupt Status Register is set to 1, the address field,
DMA_Address, is updated from the descriptor table next pointer, NP (see Figure 62 ). The
high byte of the status is read to determine if the next packet is ready to be transmitted.
While the TxDMA is filling the TxFIFO, it monitors two signals from the Transmit FIFO
State Machine (TxFifoSM) to detect error conditions and to determine if the packet is to
be retransmitted (TxDMA_Retry asserted) or the packet is aborted (TxDMA_Abort
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asserted). If the packet is aborted, the TxDMA updates the descriptor status and moves to
the next packet. If the packet is to be retried, the DMA_Address is reset to the start of the
packet, the packet length counter is reloaded from the descriptor table, bytes 3 and 4, and
the packet is moved into the TxFIFO again. When an abort or retry event occurs, the
TxDMA asserts the appropriate signal to reset the TxFIFO read and write pointers which
clears out any data that is in the FIFO. The TxFifoSM negates the TxDMA_Abort or
TxDMA_Retry signal(s) or both when the TxFCWP signal is High. This handshaking
maintains synchronization between the TxDMA and the TxFifoSM.
RxDMA
The RxDMA reads the data from the RxFIFO and stores it in the EMAC memory Receive
buffer. When the end of the packet is detected, the RxDMA reads the next two bytes from
the RxFIFO and writes them into the Rx descriptor status LSB and MSB. The packet-
length counter is stored into the descriptor table’s Packet Length field, and the descriptor
table’s next pointer is written into the Rx descriptor table. Additionally, the
Rx_DONE_STAT bit in the EMAC Interrupt Status Register is set to 1.
Signal Termination
When the EMAC interface is not used, the MII signals must be terminated as indicated in
Table 176. Terminated pins are either left unconnected (float) or tied to ground.
MDIO is controlled by the MDC output signal. When the EMAC is not being used, these
two pins are not driven. The RX_DV, RX_ER, and RXD[3:0] inputs are controlled by the
rising edge of the RX_CLK input signal. When RX_CLK is tied to Ground, these pins do
not affect the EMAC. The TX_EN, TX_ER, and TXD[3:0] outputs are controlled by the
rising edge of the TX_CLK input signal. When TX_CLK is tied to Ground, these pins do
not affect the EMAC. The CRS and COL input pins have no relationship to the clock, and
therefore must be placed into nonactive states and tied to Ground.
Table 176. MII Signal Termination When EMAC is Not Used
Termination
Signal
MDIO
Pin Type
Bidirectional
Output pin
Input pin
Input pin
Input pin
Input pin
Input pins
Input pin
Direction
Float
MDC
Float
RX_DV
CRS
Float
Ground
Ground
Float
RX_CLK
RX_ER
RXD[3:0]
COL
Float
Ground
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Table 176. MII Signal Termination When EMAC is Not Used
Termination
Direction
Signal
Pin Type
Input pin
TX_CLK
TX_EN
TXD[3:0]
TX_ER
Ground
Float
Output pin
Output pins
Output pin
Float
Float
EMAC Interrupts
Eight different sources of interrupts from the EMAC are described in Table 177.
Table 177. EMAC Interrupts
Interrupt
Description
EMAC System Interrupts
Transmit State Machine Error Bit 7 (TxFSMERR_STAT) of the EMAC Interrupt Status Register
(EMAC_ISTAT). A Transmit State Machine Error must not occur. How-
ever, if this bit is set, the entire transmitter module must be reset.
MIIMGT Done
Bit 6 (MGTDONE_STAT) of the Interrupt Status Register
(EMAC_ISTAT). This bit is set when communicating to the PHY over
the MII during a read or write operation.
Receive Overrun
Bit 2 (Rx_OVR_STAT) of the Interrupt Status Register
(EMAC_ISTAT). If this bit is set, all incoming packets are ignored until
this bit is cleared by software.
EMAC Transmitter Interrupts
Transmit Control Frame
Transmit Control Frame = Bit 1 (Tx_CF_STAT) of the Interrupt Status
Register (EMAC_ISTAT). Denotes when control frame transmission is
complete.
Transmit Done
Bit 0 (Tx_DONE_STAT) of the Interrupt Status Register
(EMAC_ISTAT). Denotes when packet transmission is complete.
EMAC Receiver Interrupts
Receive Packet
Bit 5 (Rx_CF_STAT) of the Interrupt Status Register (EMAC_ISTAT).
Denotes when packet reception is complete.
Receive Pause Packet
Receive Done
Bit 4 (Rx_PCF_STAT) of the Interrupt Status Register (EMAC_ISTAT).
Denotes when pause packet reception is complete.
Bit 3 (Rx_DONE_STAT) of the Interrupt Status Register
(EMAC_ISTAT). Denotes when packet reception is complete.
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EMAC Shared Memory Organization
Internal Ethernet SRAM shares memory with the CPU. This memory is divided into the
Transmit buffer and the Receive buffer by defining three registers, as listed below.
Transmit Lower Boundary Pointer (TLBP). This register points to the start of the Trans-
mit buffer in the internal Ethernet shared memory space.
Boundary Pointer (BP). This register points to the start of the Receive buffer.
Receive High Boundary Pointer (RHBP). This register points to the end of the Receive
buffer + 1.
Figure 60 shows the internal Ethernet shared memory.
Upper Memory Address
RHBP
Rx Buffer
BP
Tx Buffer
TLBP
Lower Memory Address
Figure 60. Internal Ethernet Shared Memory
The Transmit and Receive buffers are subdivided into packet buffers of 32, 64, 128, or 256
bytes in size. The packet buffer size is set in bits 7 and 6 of the EmacBufSize Register. An
Ethernet packet accommodate multiple packet buffers. First, however, a brief listing of the
contents of a typical Ethernet packet is in order. See Table 178.
Table 178. Ethernet Packet Contents
Byte Range
Bytes 0–5
Contents
MAC destination address.
MAC source address.
Length/Type field.
MAC Client Data.
Bytes 6–11
Bytes 12–13
Bytes 14–n
Bytes (n+1)–(n+4)
Frame Check Sequence.
At the start of each packet is a descriptor table that describes the packet. Each actual
Ethernet packet follows the descriptor table as shown in Figure 61.
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Offset
Ethernet
Packet
0007h
0000h
Descriptor
Table
TWP
Figure 61. Descriptor Table
Note: For an official description of an Ethernet packet, refer to the IEEE 802.3 specification,
Figure 3-1.
The descriptor table contains three entries: the next pointer (NP), the packet size
(Pkt_Size) and the packet status (Stat), as shown in Figure 62.
Offset
Stat
0005h
Pkt_Size
0003h
NP
TWP
0000h
Figure 62. Descriptor Table Entries
NP is a 24-bit pointer to the start of the next packet. Pkt_Size contains the number of bytes
of data in the Ethernet packet, including the four CRC bytes, but does not contain the
seven descriptor table bytes. Stat contains the status of the packet. Stat differs for Transmit
and Receive packets. See Table 179 and 180.
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Table 179. Transmit Descriptor Status
Bit
15
14
13
12
11
10
Name
Description
TxOwner
TxAbort
TxBPA
0 = Host (eZ80) owns, 1 = EMAC owns.
1 = Packet aborted (not transmitted).
1 = Back pressure applied.
TxHuge
TxLOOR
TxLCError
1 = Packet size is very large (Pkt_Size > EmacMaxf).
1 = Type/Length field is out of range (larger than 1518 bytes).
1 = Type/Length field is not a Type field and it does not match the actual
data byte length of the Ethernet packet. The data byte length is the
number of bytes of data in the Ethernet packet between the Type/
Length field and the FCS.
9
TxCrcError
1 = The packet contains an invalid FCS (CRC). This flag is set when
CRCEN = 0 and the last 4 bytes of the packet are not the valid FCS.
8
7
TxPktDeferred
TxXsDfr
1 = Packet is deferred.
1 = Packet is excessively deferred. (> 6071 nibble times in 100BaseT
or 24,287 bit times in 10BaseT).
6
5
TxFifoUnderRun
TxLateCol
1 = TxFIFO experiences underrun. Check the TxAbort bit to see if the
packet is aborted or retried.
1 = A late collision occurs. Collision is detected at a byte count >
EmacCfg2[5:0]. Collisions detected before the byte count reaches
EmacCfg2[5:0] are early collisions and retried.
4
TxMaxCol
1 = The maximum number of collisions occurs. #Collisions >
EmacCfg3[3:0]. These packets are aborted.
[3:0] TxNumberOfCollisions
This field contains the number of collisions that occur while transmitting
the packet.
Table 180. Receive Descriptor Status
Bit
15
14
13
12
Name
Description
RxOK
1 = Packet received intact.
1 = An odd number of nibbles is received.
1 = The CRC (FCS) is in error.
RxAlignError
RxCrcError
RxLongEvent
1 = A Long or Dropped Event occurs. A Long Event is when a packet
over 50,000 bit times occurs. A Dropped Packet occurs if the minimum
interpacket gap is not met, the preamble is not pure, and the
EmacCfg3[PUREP] bit is set, or if a preamble over 11 bytes in length is
detected and the EmacCfg3[LONGP] bit is set to 1.
11
RxPCF
1 = The packet is a pause control frame.
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Table 180. Receive Descriptor Status (Continued)
Bit
10
9
Name
Description
RxCF
1 = The packet is a control frame.
1 = The packet contains a multicast address.
1 = The packet contains a broadcast address.
1 = The packet is a VLAN packet.
RxMcPkt
RxBcPkt
RxVLAN
RxUOpCode
8
7
6
1 = An unsupported op code is indicated in the op code field of the
Ethernet packet.
5
4
RxLOOR
1 = The Type/Length field is out of range (larger than 1518 bytes).
RxLCError
1 = Type/Length field is not a Type field and it does not match the actual
data byte length of the Ethernet packet. The data byte length is the
number of bytes of data in the Ethernet packet between the Type/
Length field and the FCS.
3
2
RxCodeV
RxCEvent
1 = A code violation is detected. The PHY asserts Rx error (RxER).
1 = A carrier event is previously seen. This event is defined as Rx error
RxER = 1, receive data valid (RxDV) = 0 and receive data (RxD) = Eh.
1
0
RxDvEvent
RxOVR
1 = A receive data (RxDV) event is previously seen. Indicates that the
last Receive event is not long enough to be a valid packet.
1 = A Receive overrun occurs in this packet. An overrun occurs when
all of the EMAC Receive buffers are in use and the Receive FIFO is full.
The hardware ignores all incoming packets until the EmacIStat Register
[Rx_Ovr] bit is cleared by the software. There is no indication as to how
many packets are ignored.
EMAC and the System Clock
Effective Ethernet throughput in any given system is dependent upon factors such as sys-
tem clock speed, network protocol overhead, application complexity, and network traffic
conditions at any given moment. The following information provides a general guideline
about the effects of system clock speed on Ethernet operation.
The eZ80F91 ASSP's EMAC block performs a synchronous function that is designed to
operate over a wide range of system clock frequencies. To understand its maximum data
transfer capabilities at certain system operating frequencies, you must first understand the
internal data bus bandwidth that is required under ideal conditions.
For 10BaseT Ethernet connectivity, the data rate is 10 Mbps, which equates to 1.25 Mbps.
If the eZ80F91 ASSP is operating in FULL-DUPLEX Mode over 10BaseT, the data rate
for RX data and TX data is 1.25Mbps. Because raw data transfers at this rate consume a
certain amount of CPU bandwidth, the CPU must support traffic from both directions as
well as operate at a minimum clock frequency of (1.25 + 1.25) * 2 = 5MHz while transfer-
ring Ethernet packets to and from the physical layer.
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Similarly, for 100BaseT Ethernet, the data rate is 100 Mbps, which equates to 12.5 Mbps.
If the eZ80F91 ASSP is operating in FULL-DUPLEX Mode over 100BaseT, the data rate
for RX data and TX data is 12.5Mbps. Because raw data transfers at this rate consume a
certain amount of CPU bandwidth, the CPU must support traffic from both directions as
well as operate at a minimum clock frequency of (12.5 + 12.5) x 2 = 50 MHz while trans-
ferring Ethernet packets to and from the physical layer. Consequently, 50 MHz is the min-
imum system clock speed that the eZ80 CPU requires to sustain EMAC data transfers
while not including any software overhead or additional eZ80 tasks.
The FIFO functionality of the EMAC operates at any frequency as long as the user appli-
cation avoids overrun and underrun errors via higher-level flow control. Actual applica-
tion requirements will dictate Ethernet modes of operation (FULL-DUPLEX, HALF-
DUPLEX, etc.). Because each user and application is different, it becomes your responsi-
bility to control the data flow with these parameters. Under ideal conditions, the system
clock will operate somewhere between 5 MHz and 50 MHz to handle the EMAC data
rates.
EMAC Operation in HALT Modes
When the CPU is in HALT Mode, the eZ80F91 device’s EMAC block cannot be disabled
as other peripherals. Upon receipt of an Ethernet packet, a maskable Receive interrupt is
generated by the EMAC block, just as it would be in a non-halt mode. Accordingly, the
processor wakes up and continues with the user-defined application.
EMAC Registers
After a system reset, all EMAC registers are set to their default values. Any writes to
unused registers or register bits are ignored and reads return a value of 0. For compatibility
with future revisions, unused bits within a register must always be written with a value of
0. Read/write attributes, reset conditions, and bit descriptions of all of the EMAC registers
are provided in this section.
EMAC Test Register
The EMAC Test Register, shown in Table 181, allows test functionality of the EMAC
block. Available test modes are defined for bits [6:0].
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Table 181. EMAC Test Register (EMAC_TEST)
Bit
7
6
5
4
3
2
1
0
Field
Reserved TEST_FIFO TxRx_SEL SSTC SIMR FRC_OVR_ FRC_UND_ LPBK
ERR
ERR
Reset
R/W
0
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
0020h
Note: R/W = read/write, R = read only.
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6]
FIFO Test Mode Enable
TEST_FIFO
0: FIFO TEST Mode disabled; normal operation.
1: FIFO TEST Mode enabled.
[5]
Transmit/Receive FIFO Select
TxRx_SEL
0: Select the Receive FIFO when FIFO TEST Mode is enabled.
1: Select the Transmit FIFO when FIFO TEST Mode is enabled.
[4]
Short Cut Slot Timer Counter Operation
SSTC
0: Normal operation.
1: Short Cut Slot Timer Counter. Slot time is shortened to speed up simulation.
[3]
SIMR
Reset Simulator Operation
0: Normal operation.
1: Simulation Reset.
[2]
Force Overrun Error Operation
0: Normal operation.
FRC_OVR_
ERR
1: Force Overrun error in Receive FIFO.
[1]
Force Underrun Error Operation
0: Normal operation.
FRC_UND_
ERR
1: Force Underrun error in Transmit FIFO.
[0]
Loopback Operation
LPBK
0: Normal operation.
1: EMAC Transmit interface is looped back into EMAC Receive interface.
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EMAC Configuration Register 1
The EMAC Configuration Register 1, shown in Table 182, allows control of the padding,
autodetection, cyclic redundancy checking (CRC) control, full-duplex, field length check-
ing, maximum packet ignores, and proprietary header options.
Table 182. EMAC Configuration Register 1 (EMAC_CFG1)
Bit
7
6
5
4
CRCEN
0
3
FULLD
0
2
FLCHK
0
1
0
Field
Reset
R/W
PADEN ADPADN VLPAD
HUGEN DCRCC
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
0021h
Note: R/W = read/write.
Bit
Description
Pad Enable
0: No padding. Assume all frames presented to EMAC have proper length.
[7]
PADEN
1: EMAC pads all short frames by adding zeroes to the end of the data field. This bit is
used in conjunction with ADPADN and VLPAD.
[6]
Frame Detection Enable
ADPADN
0: Disable autodetection.
1: Enable frame detection by comparing the two bytes following the source address with
0x8100 (VLAN Protocol ID) and pad accordingly. This bit is ignored if PADEN is
cleared to 0.
[5]
Short Frame Pad
VLPAD
0: Do not pad all short frames.
1: EMAC pads all short frames to 64 bytes and append a valid CRC. This bit is ignored if
PADEN is cleared to 0.
[4]
CRCEN
Cyclic Redundancy Check Append Enable
0: Do not append CRC.
1: Append CRC to every frame regardless of padding options.
[3]
Duplex Mode Enable
FULLD
0: HALF-DUPLEX Mode. CSMA/CD is enabled.
1: Enable FULL-DUPLEX Mode. CSMA/CD is disabled.
[2]
Frame Length Check
FLCHK
0: Ignore the length field within Transmit/Receive frames.
1: Both Transmit and Receive frame lengths are compared to the length/type field. If the
length/type field represents a length then the frame length check is performed.
[1]
Frame Size Enable
HUGEN
0: Limit the Receive frame size to the number of bytes specified in the MAXF[15:0] field.
1: Allow unlimited-sized frames to be received. Ignore the MAXF[15:0] field.
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Bit
Description (Continued)
[0]
Header Check
DCRCC
0: No proprietary header. Normal operation.
1: Four bytes of proprietary header, ignored by CRC, exists on the front of IEEE 802.3
frames.
Table 183 shows the results of different settings for bits [7:4] of EMAC Configuration
Register 1.
Table 183. CRC/PAD Features of EMAC Configuration Register
ADPADN VLPADN PADEN CRCEN Result
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
No pad or CRC appended.
CRC appended.
Pad to 60 bytes if necessary; append CRC (min. size = 64).
Pad to 60 bytes if necessary; append CRC (min. size = 64).
No pad or CRC appended.
CRC appended.
Pad to 64 bytes if necessary, append CRC (min. size = 68).
Pad to 64 bytes if necessary, append CRC (min. size = 68).
No pad or CRC appended.
CRC appended.
If VLAN not detected, pad to 60, add CRC.
If VLAN detected, pad to 64, add CRC.
1
0
1
1
If VLAN not detected, pad to 60, add CRC.
If VLAN detected, pad to 64, add CRC.
1
1
1
1
1
1
0
0
1
0
1
0
No pad or CRC appended.
CRC appended.
If VLAN not detected, pad to 60, add CRC.
If VLAN detected, pad to 64, add CRC.
1
1
1
1
If VLAN not detected, pad to 60, add CRC.
If VLAN detected, pad to 64, add CRC.
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EMAC Configuration Register 2
The EMAC Configuration Register 2, shown in Table 184, controls the behavior of the
back pressure and late collision data from the Descriptor table.
Table 184. EMAC Configuration Register 2 (EMAC_CFG2)
Bit
7
BPNB
0
6
NOBO
0
5
4
3
2
1
0
Field
Reset
R/W
LCOL
1
1
0
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
0022h
Note: R/W = read/write.
Bit
Description
[7]
Back-Off Pressure
BPNB
0: Use normal back-off algorithm prior to transmitting packet. No back pressure applied.
1: After incidentally causing a collision during back pressure, the EMAC immediately (that
is, no back-off) retransmits the packet without back-off, which reduces the chance of
further collisions and ensures that the Transmit packets are sent.
[6]
Exponential Back-Off Enable
NOBO
0: Enable exponential back-off.
1: The EMAC immediately retransmits following a collision rather than use the binary
exponential backfill algorithm, as specified in the IEEE 802.3 specification.
[5:0]
Late Collision
LCOL
00h–3Fh: Sets the number of bytes after a Start Frame Delimiter (SFD) for which a late
collision occurs. By default, all late collisions are aborted.
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EMAC Configuration Register 3
The EMAC Configuration Register 3, shown in Table 185, controls preamble length and
value, excessive deferment, and the number of retransmission tries.
Table 185. EMAC Configuration Register 3 (EMAC_CFG3)
Bit
7
6
5
XSDFR
0
4
BITMD
0
3
2
1
0
Field
Reset
R/W
LONGP PUREP
RETRY
0
0
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
0023h
Note: R/W = read/write.
Bit
Description
[7]
Preamble Length*
LONGP
0: The EMAC allows any preamble length per the IEEE 802.3 specification.
1: The EMAC only allows Receive packets that contain preamble fields less than 12 bytes
in length.
[6]
Preamble Error Check
PUREP
0: No preamble error checking is performed.
1: The EMAC verifies the content of the preamble to ensure that it contains a value of 55h
and that it is error-free. Packets containing an errored preamble are discarded.
[5]
Excessive Deferral Limit
XSDFR
0: The EMAC aborts when the excessive deferral limit is reached.
1: The EMAC defers to the carrier indefinitely per the IEEE 802.3 specification.
[4]
Endec Mode Enable
BITMD
0: Disable 10Mbps ENDEC Mode.
1: Enable 10Mbps ENDEC Mode.
[3:0]
Retransmission Attempts
RETRY
0h–Fh: A programmable field specifying the number of retransmission attempts following
a collision before aborting the packet due to excessive collisions.
Note: *IEEE 802.3 specifies a minimum of 56 bits of preamble. A maximum number of bits is not defined. For details,
see the IEEE 802.3 Specification, Section 7.2.3.2.
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EMAC Configuration Register 4
The EMAC Configuration Register 4, shown in Table 186, controls pause control frame
behavior, back pressure, and receive frame acceptance.
Table 186. EMAC Configuration Register 4 (EMAC_CFG4)
Bit
7
6
TPCF
0
5
THDF
0
4
PARF
0
3
RxFC
0
2
TxFC
0
1
TPAUSE
0
0
RxEN
0
Field
Reset
R/W
Reserved
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
0024h
Note: R = read only; R/W = read/write.
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6]
TPCF
Transmit Pause Control Frame
0: Do not transmit a pause control frame.
1: Transmit pause control frame (FULL-DUPLEX Mode). TPCF continually sends pause
control frames until negated.
[5]
THDF
Transmit Half-Duplex Frame
0: Disable back pressure.
1: EMAC asserts back pressure on the link. Back pressure causes the preamble to be
transmitted, raising the carrier sense (HALF-DUPLEX Mode).
[4]
PARF
Frame Receive
0: Only accept frames that meet preset criteria (that is, address, CRC, length, etc.).
1: All frames are received regardless of address, CRC, length, etc.
[3]
RxFC
Receive Pause Control Frames
0: EMAC ignores received pause control frames.
1: EMAC acts upon pause control frames received.
[2]
TxFC
Transmit Pause Control Frames
0: Pause control frames are not allowed to be transmitted.
1: Pause control frames are allowed to be transmitted.
[1]
TPAUSE
Pause Condition
0: Do not force a pause condition.
1: Force a pause condition while this bit is asserted.
[0]
RxEN
Pause Control Frames
0: EMAC receiver disabled.
1: EMAC receiver enabled.
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EMAC Station Address Register
The EMAC Station Address Register, shown in Table 187, is used for two functions. In the
address recognition logic for Receive frames, EMAC_STAD_0–EMAC_STAD_5 are
matched against the sixth byte Destination Address (DA) field of the Receive frame.
EMAC_STAD_0 is matched against the first byte of the Receive frame, and
EMAC_STAD_5 is matched against the sixth byte of the Receive frame. Bit 0 of
EMAC_STAD_0 (STAD[40]) is matched against the first bit (Unicast/Multicast bit) of the
first byte of the Receive frame. This bit ordering is used to logically map the PE-MACMII
station address as illustrated below.
EMAC_STAD0[7:0] contains STAD[47:40]
....
....
EMAC_STAD5[7:0] contains STAD[7:0]
The second function of the EMAC Station Address registers is to provide the Source
Address (SA) field of Transmit Pause frames when these frames are transmitted by the
EMAC. EMAC_STAD_0 provides the first byte of the 6 byte SA field and
EMAC_STAD_5 provides the final byte of the SA field in order of transmission. The LSB
is the first byte sent out. The EMAC Station Address Register is detailed in Table 187.
Table 187. EMAC Station Address Register (EMAC_STAD_x)
Bit
7
6
5
4
3
2
1
0
Field
EMAC_STAD_x
EMAC_STAD_0 Reset
EMAC_STAD_1 Reset
EMAC_STAD_2 Reset
EMAC_STAD_3 Reset
EMAC_STAD_4 Reset
EMAC_STAD_5 Reset
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
EMAC_STAD_0 = 0025h, EMAC_STAD_1 = 0026h,
EMAC_STAD_2 = 0027h, EMAC_STAD_3 = 0028h,
EMAC_STAD_4 = 0029h, EMAC_STAD_5 = 002Ah
Note: R/W = read/write; x = reset bits in the range [5:0].
Bit
Description
[7:0]
EMAC_STAD_x
00h–FFh: This 48-bit station address comprises {EMAC_STAD_5,
EMAC_STAD_4, EMAC_STAD_3, EMAC_STAD_2, EMAC_STAD_1,
EMAC_STAD_0}.
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EMAC Transmit Pause Timer Value High and Low Byte
Registers
The low and high bytes of the EMAC Transmit Pause Timer Value Register are inserted
into outgoing pause control frames. See Table 188 and 189.
Table 188. EMAC Transmit Pause Timer Value Low Byte Register (EMAC_TPTV_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
EMAC_TPTV_L
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
002Bh
Note: R/W = read/write.
Bit
Description
Transmit Pause Timer Value Low Byte
[7:0]
EMAC_TPTV_L 00h–FFh: The 16-bit value, {EMAC_TPTV_H, EMAC_TPTV_L}, is inserted into outgo-
ing pause control frames as the pause timer value upon asserting TPCF.
Table 189. EMAC Transmit Pause Timer Value High Byte Register (EMAC_TPTV_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
EMAC_TPTV_H
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
002Ch
Note: R/W = read/write.
Bit
Description
Transmit Pause Timer Value High Byte
[7:0]
EMAC_TPTV_H 00h–FFh: The 16-bit value, {EMAC_TPTV_H, EMAC_TPTV_L}, is inserted into outgo-
ing pause control frames as the pause timer value upon asserting TPCF.
EMAC Interpacket Gap
Interpacket Gap (IPG) is measured between the last nibble of the frame check sequence
(FCS) and the first nibble of the preamble of the next packet. Three registers are available
to fine tune the IPG, the EMAC_IPGT, EMAC_IPGR1, and the EMAC_IPGR2. The first
register, EMAC_IPGT, determines the back-to-back Transmit IPG. The other two registers
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determine the non-back-to-back IPG in two parts. Table 190 shows the values for the
EMAC_IPGT and the corresponding IPGs for both FULL-DUPLEX and HALF-
DUPLEX modes.
Table 190. EMAC_IPGT Back-to-Back Settings for Full- and Half-Duplex Modes
MII, RMII/SMII, PMD
(100 Mbps)
MII, RMII/SMII
(10 Mbps)
ENDEC Mode
(10 Mbps)
Clock Period = 40ns
IPGT[6:0]
Clock Period = 400ns
IPGT[6:0]
Clock Period = 100ns
IPGT[6:0]
Half
Duplex
Full
Duplex
Interpacket
Half
Duplex
Full
Duplex
Interpacket
Half
Duplex
Full
Duplex
Interpacket
Gap
Gap
1.2µs
4.4µs
6.0µs
7.5µs
9.6µs
14.0µs
Gap
1.9µs
2.7µs
3.5µs
6.7µs
9.6µs
13.0µs
0Dh
0Bh
0Ch
10h
15h
20h
0.12µs
0.44µs
0.60µs
0.76µs
0.96µs
1.40µs
00h
08h
0Ch
10h
15h
20h
10h
18h
20h
40h
5Dh
20h
*12h
12h
5Ah
Note: *The IEEE 802.3, 802.3(u) minimum values are shaded.
The equations for back-to-back Transmit IPG are determined by the following equations:
FULL-DUPLEX Mode (3 clocks + IPGT clocks) * clock period = IPG
HALF-DUPLEX Mode (6 clocks + IPGT clocks) * clock period = IPG
Table 191 lists the IPGR2 settings for the non-back-to-back packets.
Table 191. EMAC_IPGT Non-Back-to-Back Settings for Full- /Half-Duplex Modes
MII, RMII/SMII, PMD
(100 Mbps)
MII, RMII/SMII
(10 Mbps)
ENDEC Mode
(10 Mbps)
Clock Period = 40ns
Clock Period = 400ns
Clock Period = 100ns
IPGR2[6:0]
Interpacket
IPGR2[6:0]
Interpacket
IPGR2[6:0]
Interpacket
Gap
Gap
2.4 µs
8.8 µ s
9.6 µs
15.2 µs
Gap
00h
10h
*12h
20h
0.24 µs
0.88 µ s
0.96 µ s
1.52 µ s
00h
10h
12h
20h
00h
10h
20h
40h
0.6 µ s
2.2 µ s
3.8 µ s
7.0µ s
Note: *The IEEE 802.3, 802.3(u) minimum values are shaded.
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Table 191. EMAC_IPGT Non-Back-to-Back Settings for Full- /Half-Duplex Modes (Continued)
MII, RMII/SMII, PMD
(100 Mbps)
MII, RMII/SMII
(10 Mbps)
ENDEC Mode
(10 Mbps)
40h
7Fh
2.80 µ s
5.32 µ s
40h
7Fh
28.0 µ s
53.2 µ s
5Ah
7Fh
9.6 µ s
13.3 µs
Note: *The IEEE 802.3, 802.3(u) minimum values are shaded.
A non-back-to-back Transmit IPG is determined by the following formula:
(6 clocks + IPGR2 clocks) * clock period = IPG
The difference in values between Table 190 and 191 is due to the asynchronous nature of
the Carrier Sense (CRS). The CRS must undergo a 2-clock synchronization before the
internal Tx state machine detects it. This synchronization equates to a 6-clock intrinsic
delay between packets instead of the 3-clock intrinsic delay in the back-to-back packet
mode. More information covering this topic is found in the IEEE 802.3/4.2.3.2.1 Carrier
Deference section.
EMAC Interpacket Gap Register
The EMAC Interpacket Gap (IPG) Register, shown in Table 192, is a programmable field
representing the IPG between back-to-back packets. It is the IPG parameter used in
FULL-DUPLEX and HALF-DUPLEX modes between back-to-back packets. Set this
field to the appropriate number of IPG bytes. The default setting of 15hrepresents the
minimum IPG of 0.96 µs (at 100 Mbps) or 9.6µs (at 10 Mbps).
Table 192. EMAC Interpacket Gap Register (EMAC_IPGT)
Bit
7
6
5
4
3
IPGT
0
2
1
0
Field
Reset
R/W
Reserved
0
0
0
1
1
0
1
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
002Dh
Note: R = read only; R/W = read/write
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6:0]
Interpacket Gap Bytes
IPGT
00h–7Fh: The number of bytes of IPG.
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EMAC Non-Back-To-Back IPG Register, Part 1
Part 1 of the EMAC non-back-to-back IPG Register, shown in Table 193, is a programma-
ble field representing the optional carrier sense window referenced in IEEE 802.3/
4.2.3.2.1 Carrier Deference. If a carrier is detected during the timing of IPGR1, the EMAC
defers to the carrier. If, however, the carrier becomes active after IPGR1, the EMAC con-
tinues timing for IPGR2 and transmits, knowingly causing a collision. This collision acts
to ensure fair access to the medium. Its range of values is 00hto IPGR2. The default set-
ting of 0Chrepresents the Carrier Sense Window Referencing depicted tin IEEE 802.3,
Section 4.2.3.2.1.
Table 193. EMAC Non-Back-To-Back IPG Register, Part 1 (EMAC_IPGR1)
Bit
7
Reserved
0
6
5
4
3
IPGR 1
1
2
1
0
Field
Reset
R/W
0
0
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
002Eh
Note: R/W = read/write
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6:0]
Interpacket Gap Register 1
IPGR 1
00h–7Fh: A programmable field representing the optional carrier sense window refer-
enced in IEEE 802.3/4.2.3.2.1 Carrier Deference.
EMAC Non-Back-To-Back IPG Register, Part 2
Part 2 of the EMAC non-back-to-back IPG Register, shown in Table 194, is a programma-
ble field representing the non-back-to-back IPG. Its default is 12h, which represents the
minimum IPG of 0.96µs at 100Mbps or 9.6µs at 10Mbps.
Table 194. EMAC Non-Back-To-Back IPG Register, Part 2 (EMAC_IPGR2)
Bit
7
6
5
4
3
IPGR 2
0
2
1
0
Field
Reset
R/W
Reserved
0
0
0
1
0
1
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
002Fh
Note: R = read only; R/W = read/write.
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Product Specification
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Bit
Description
[7]
Reserved
This bit is reserved and must be programmed to 0.
[6:0]
IPGR2
Interpacket Gap Register 2
00h–7Fh: This bit range is a programmable field representing the non-back-to-back inter-
packet gap.
EMAC Maximum Frame Length High and Low Byte Registers
The 16-bit field resets to 0600h, which represents a maximum Receive frame of 1536
bytes. An untagged maximum size Ethernet frame (packet) is 1518 bytes. A tagged frame
adds four bytes for a total of 1522 bytes. If a shorter maximum length restriction is more
appropriate, program this field. See Table 195 and 196.
Note: The default value of 1536 bytes is large enough to cover the largest Ethernet packet, which
contains 14 bytes of Ethernet header, 1500 bytes of MAC client data, plus 4 bytes of CRC
for a total of 1518 maximum bytes. This value is also large enough to cover VLAN frames
with prepended headers up to 18 bytes.
VLAN frames have a proprietary header prepended to the Ethernet packet. Setting the
DCRCC bit in EMAC_CFG1 will exclude the first 4 bytes – the proprietary header – from
the CRC calculation. For VLAN packets, the maximum frame length is 1522, four more
than for normal Ethernet packets, due to the four-byte prepended header. Normal packets
feature a twelve-byte header before the MAC client data. For more information about this
topic, refer to Figure 3-1 of the IEEE 802.3 specification.
Note: If a proprietary header is allowed, this field must be adjusted accordingly. For example, if
12 byte headers are prepended to frames, MAXF must be set to 1524 bytes to allow the
maximum VLAN tagged frame plus the 12 byte header. The default value of 1536 is large
enough to cover the largest Ethernet packet: 14 bytes of Ethernet header, 1500 bytes of
MAC client data, plus 4 bytes of CRC for a total of 1518 bytes maximum. It is also large
enough to cover VLAN packets with prepended headers up to 18 bytes. The following for-
mulas illustrate:
Ethernet Packet
Use the following equation to calculate the maximum frame size of an Ethernet packet:
Maximum frame size = normal Ethernet packet – 14 (Ethernet header) + 1500 (MAC
client data) + 4 (CRC) = 1518 bytes
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VLAN Packet
Use the following equation to calculate the maximum frame size of a VLAN packet:
Maximum frame size = VLAN with 4 byte header – 4 (VLAN header) + 14 (Ethernet
header) + 1500 MAC client data) + 4 (CRC) = 1522 bytes.
The low and high bytes of the EMAC Maximum Frame Length Register are shown in
Tables 195 and 196, respectively.
Table 195. EMAC Maximum Frame Length Low Byte Register (EMAC_MAXF_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
EMAC_MAXF_L
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
0030h
Note: R/W = read/write.
Bit
Description
Maximum Frame Length, Low Byte
[7:0]
EMAC_MAXF_L 00h–FFh: These bits represent the low byte of the 2-byte MAXF value
{EMAC_MAXF_H, EMAC_MAXF_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is bit 0 (lsb)
of the 16-bit value.
Table 196. EMAC Maximum Frame Length High Byte Register (EMAC_MAXF_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
EMAC_MAXF_H
0
0
0
0
0
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
0031h
Note: R/W = read/write.
Bit
Description
Maximum Frame Length, High Byte
[7:0]
EMAC_MAXF_H 00h–FFh: These bits represent the high byte of the 2-byte MAXF value
{EMAC_MAXF_H, EMAC_MAXF_L}. Bit 7 is bit 15 (msb) of the 16-bit value. Bit 0 is bit
8 of the 16-bit value.
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EMAC Address Filter Register
The EMAC Address Filter Register, shown in Table 197, functions as a filter to control
PROMISCUOUS Mode, plus multicast and broadcast messaging.
Table 197. EMAC Address Filter Register (EMAC_AFR)
Bit
7
6
5
4
3
PROM
0
2
MC
0
1
QMC
0
0
BC
0
Field
Reset
R/W
Reserved
0
0
0
0
R
R
R
R
R/W
R/W
R/W
R/W
Address
0032h
Note: R = read only; R/W = read/write.
Bit
Description
Reserved
[7:4]
These bits are reserved and must be programmed to 0h.
[3]
Promiscuous Mode Enable
PROM
0: Disable Promiscuous Mode.
1: Enable Promiscuous Mode. Receive all incoming packets regardless of station
address. Disables station address filtering.
[2]
Multicast Accept
MC
0: Do not accept multicast messages of any type.
1: Accept any multicast message. A multicast packet is determined by the first bit in the des-
tination address. If the first LSB is a 1, it is a group address and is globally or locally
administered depending on the 2nd bit. For more information, see IEEE 802.3/3.2.3.
[1]
Qualified Multicast Accept
QMC
0: Do not accept QMC messages.
1: Accept only qualified multicast (QMC) messages as determined by the hash table.
[0]
Broadcast Accept
BC
0: Do not accept broadcast messages.
1: Accept broadcast messages. Broadcast messages have the destination address set to
FFFFFFFFFFFFh.
EMAC Hash Table Register
The EMAC Hash Table Register, shown in Table 198, represents the 8x8 hash table
matrix. This table is used as an option to select between different multicast addresses. If a
multicast address is received, the first 6 bits of the CRC are decoded and added to a table
that points to a single bit within the hash table matrix. If the selected bit = 1, the multicast
packet is accepted. If the bit = 0, the multicast packet is rejected.
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Table 198. EMAC Hash Table Register (EMAC_HTBL_x)
Bit
7
6
5
4
3
2
1
0
Field
EMAC_HTBL_x
EMAC_HTBL_0 Reset
EMAC_HTBL_1 Reset
EMAC_HTBL_2 Reset
EMAC_HTBL_3 Reset
EMAC_HTBL_4 Reset
EMAC_HTBL_5 Reset
EMAC_HTBL_6 Reset
EMAC_HTBL_7 Reset
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
EMAC_HTBL_0 = 0033h, EMAC_HTBL_1 = 0034h,
EMAC_HTBL_2 = 0035h, EMAC_HTBL_3 = 0036h,
EMAC_HTBL_4 = 0037h, EMAC_HTBL_5 = 0038h,
EMAC_HTBL_6 = 0039h, EMAC_HTBL_7 = 003Ah
Note: R/W = read/write; x indicates reset bits in the range [7:0].
Bit
Description
[7:0]
EMAC_HTBL_x
00h–FFh: This field is the hash table. The 64 bit hash table is
{EMAC_HTBL_7, EMAC_HTBL_6, EMAC_HTBL_5, EMAC_HTBL_4,
EMAC_HTBL_3, EMAC_HTBL_2, EMAC_HTBL_1, EMAC_HTBL_0}.
EMAC MII Management Register
The EMAC MII Management Register, shown in Table 199, is used to control the external
PHY attached to the MII.
Table 199. EMAC MII Management Register (EMAC_MIIMGT)
Bit
7
LCTLD
0
6
RSTAT
0
5
SCINC
0
4
SCAN
0
3
SPRE
0
2
1
CLKS
0
0
Field
Reset
R/W
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
003Bh
Note: R/W = read/write.
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Bit
Description
[7]
Configuration Data
LCTLD
0: No operation.
1: A rising edge causes the CTLD control data to be transmitted to external PHY if MII is
not busy. This bit is self-clearing.
[6]
Read Status
RSTAT
0: No operation.
1: A rising edge causes status to be read from external PHY via PRSD[15:0] bus if MII is
not busy. This bit is self-clearing.
[5]
Scan Address Increments
SCINC
0: Normal operation.
1: Scan PHY address increments upon SCAN cycle. The SCAN bit must also be set for
the PHY address to increment after each scan. The scanning starts at the
EMAC_FIAD and increments up to 1Fh. It then returns to the EMAC_FIAD address.
[4]
Scan Mode Read
SCAN
0: Normal operation.
1: Perform continuous read cycles via MII management. While in SCAN Mode, the
EMAC_ISTAT[MGTDONE] bit is set when the current PHY read has completed. At this
time, the EMAC_PRSD Register holds the read data and the EMAC_MIISTAT[4:0]
holds the address of the PHY for which the EMAC_PRSD data pertains.
[3]
Suppress Preamble
SPRE
0: Normal preamble.
1: Suppress the MDO preamble. MDO is management data output, an internal signal
driven from the MDIO pin.
[2:0]
Serial Clock Divisor
CLKS
Programmable divisor that produces MDC from SCLK. MDC is the management data
clock pin, which clocks MDIO data to and from the PHY. its frequency is SCLK divided by
the MDC clock divider.
000: MDC = SCLK ÷ 4.
001: MDC = SCLK ÷ 4.
010: MDC = SCLK ÷ 6.
011: MDC = SCLK ÷ 8.
100: MDC = SCLK ÷ 10.
101: MDC = SCLK ÷ 14.
110: MDC = SCLK ÷ 20.
111: MDC = SCLK ÷ 28.
EMAC PHY Configuration Data Register, Low and High Byte
The low and high bytes of the EMAC PHY Configuration Data Register, shown in
Tables 200 and 201, represent the configuration data written to the external PHY. The
EMAC_CTLD_H and EMAC_CTLD_L registers form a 16-bit register. These registers
are loaded with data to be sent via the MDIO pin to the PHY. The PHY is selected by set-
ting the EMAC_FIAD. The register inside the PHY is selected by setting EMAC_RGAD.
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Table 200. EMAC PHY Configuration Data Low Byte Register (EMAC_CTLD_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
EMAC_CTLD_L
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
003Ch
Note: R/W = read/write.
Bit
Description
Configuration Data Low Byte
[7:0]
EMAC_CTLD_L 00h–FFh: These bits represent the low byte of the two-byte PHY configuration data
value, {EMAC_CTLD_H, EMAC_CTLD_L}. Bit 7 is bit 7 of the 16-bit value; bit 0 is bit 0
(lsb) of the 16-bit value.
Table 201. EMAC PHY Configuration Data High Byte Register (EMAC_CTLD_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
EMAC_CTLD_H
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
003Dh
Note: R/W = read/write.
Bit
Description
Configuration Data High Byte
[7:0]
EMAC_CTLD_H 00h–FFh: These bits represent the high byte of the two-byte PHY configuration data
value, {EMAC_CTLD_H, EMAC_CTLD_L}. Bit 7 is bit 15 (msb) of the 16-bit value; bit
0 is bit 8 of the 16-bit value.
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EMAC PHY Address Register
The EMAC PHY Address Register, shown in Table 202, allows access to the external
PHY registers.
Table 202. EMAC PHY Address Register (EMAC_RGAD)
Bit
7
6
5
4
3
2
RGAD
0
1
0
Field
Reset
R/W
Reserved
0
0
0
0
0
0
0
R
R
R
R/W
R/W
R/W
R/W
R/W
Address
003Eh
Note: R = read only; R/W = read/write.
Bit
Description
Reserved
[7:5]
These bits are reserved and must be programmed to 000.
[4:0]
Address Select
RGAD
00h–1Fh: Programmable 5-bit value which selects addresses within the selected external
PHY.
EMAC PHY Unit Select Address Register
The EMAC PHY Unit Select Address Register allows the selection of multiple connected
external PHY devices. See Table 203.
Table 203. EMAC PHY Unit Select Address Register (EMAC_FIAD)
Bit
7
6
5
4
3
2
FIAD
0
1
0
Field
Reset
R/W
Reserved
0
0
0
0
0
0
0
R
R
R
R/W
R/W
R/W
R/W
R/W
Address
003Fh
Note: R = read only; R/W = read/write.
Bit
Description
Reserved
[7:5]
These bits are reserved and must be programmed to 000.
[4:0]
PHY Select
FIAD
00h–1Fh: Programmable 5-bit value that selects an external PHY.
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EMAC Transmit Polling Timer Register
This register sets the Transmit Polling Period in increments of TPTMR = SYSCLK ÷ 256.
Whenever this register is written, the status of the Transmit Buffer Descriptor is checked
to determine if the EMAC owns the Transmit buffer. It then rechecks this status every
TPTMR (calculated by TPTMR x EMAC_PTMR[7:0]). The Transmit Polling Timer is
disabled if this register is set to 00h(which also disables the transmitting of packets). If a
transmission is in progress when EMAC_PTMR is set to 00h, the transmission will com-
plete. See Table 204.
Table 204. EMAC Transmit Polling Timer Register (EMAC_PTMR)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
EMAC_PTMR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
0040h
Note: R/W = read/write.
Bit
Description
[7:0]
Transmit Polling Timer
EMAC_PTMR 00h–FFh: The transmit polling period.
EMAC Reset Control Register
The bit values in the EMAC Reset Control Register, shown in Table 205, are not self-
clearing bits. You are responsible for controlling their state.
Table 205. EMAC Reset Control Register (EMAC_RST)
Bit
7
6
5
SRST
1
4
HRTFN
0
3
2
1
0
Field
Reset
R/W
Reserved
HRRFN HRTMC HRRMC HRMGT
0
0
0
0
0
0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Address
0041h
Note: R = read only; R/W = read/write.
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Bit
Description
[7:6]
Reserved
These bits are reserved and must be programmed to 00.
[5]
SRST
Software Reset
0: Normal operation.
1: Software Reset Active: resets Receive, Transmit, EMAC Control and EMAC MII_MGT
functions.
[4]
HRTFN
Reset Transmit
0: Normal operation.
1: Reset Transmit function.
[3]
HRRFN
Reset Receive
0: Normal operation.
1: Reset Receive function.
[2]
HRTMC
EMAC Transmit
0: Normal operation.
1: Reset EMAC Transmit Control function.
[1]
EMAC Receive
HRRMC
0: Normal operation.
1: Reset EMAC Receive Control function.
[0]
EMAC Management
HRMGT
0: Normal operation.
1: Reset EMAC Management function.
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EMAC Transmit Lower Boundary Pointer High and Low Byte
Registers
The EMAC Transmit Lower Boundary Pointer is set to the start of the Transmit buffer in
EMAC shared memory. See Tables 206 and 207.
Table 206. EMAC Transmit Lower Boundary Pointer Low Byte Register (EMAC_TLBP_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
EMAC_TLBP_L
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R
R
R
Address
0042h
Note: R/W = read/write.
Bit
Description
Transmit Lower Boundary Pointer Low Byte
[7:0]
EMAC_TLBP_L 00h–FFh: These bits represent the low byte of the two-byte Transmit Lower Boundary
Pointer value, {EMAC_TLBP_H, EMAC_TLBP_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0
is bit 0 (lsb) of the 16-bit value.
Table 207. EMAC Transmit Lower Boundary Pointer High Byte Register (EMAC_TLBP_H) *
Bit
7
6
5
4
3
2
1
0
Field
EMAC_TLBP_H
Reset
1
1
0
0
0
0
0
0
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
Address
0043h
Note: R/W = read/write.
Bit
Description
Transmit Lower Boundary Pointer High Byte
[7:0]
EMAC_TLBP_H 00h–FFh: These bits represent the high byte of the two-byte Transmit Lower Boundary
Pointer value, {EMAC_TLBP_H, EMAC_TLBP_L}. Bit 7 is bit 15 (msb) of the 16-bit
value. Bits 7:5 default to 000 on reset; bit 0 is bit 8 of the 16-bit value.
Note: *Bits 7:5 are not used by the EMAC; these bits return 000.
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EMAC Boundary Pointer High and Low Byte Registers
The Boundary Pointer is set to the start of the Receive buffer (end of Transmit buffer +1)
in EMAC shared memory. This pointer is 24 bits and determined by {RAM_ADDR_U,
EMAC_BP_H, EMAC_BP_L}. The upper 3 bits of the EMAC_BP_H Register are hard-
wired inside the eZ80F91 device to locate the base of EMAC shared memory. The last 5
bits of the EMAC_BP_L Register value are hard-wired to keep the addressing aligned to a
32-byte boundary. See Table 208 and 209.
Table 208. EMAC Boundary Pointer Low Byte Register (EMAC_BP_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
EMAC_BP_L
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R
R
R
Address
0044h
Note: R = read only, R/W = read/write.
Bit
Description
Boundary Pointer Low Byte
[7:0]
EMAC_BP_L 00h–FFh: These bits represent the low byte of the 3-byte EMAC Boundary Pointer value,
{EMAC_BP_U, EMAC_BP_H, EMAC_BP_L}. Bit 7 is bit 7 of the 24 bit value. Bit 0 is bit 0
of the 24 bit value.
Table 209. EMAC Boundary Pointer High Byte Register (EMAC_BP_H)
Bit
15:13
12:8
Field
Reset
R/W
EMAC_BP_H
1
1
0
0
0
0
0
0
R
R
R
R/W
R/W
R/W
R/W
R/W
Address
0045h
Note: R = read only, R/W = read/write.
Bit
Description
Boundary Pointer High Byte
[7:0]
EMAC_BP_H 00h–FFh: These bits represent the high byte of the 3-byte EMAC Boundary Pointer
value, {EMAC_BP_U, EMAC_BP_H, EMAC_BP_L}. Bit 7 is bit 15 of the 24 bit value. Bit
0 is bit 8 of the 24 bit value.
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EMAC Boundary Pointer Register, Upper Byte
The EMAC Boundary Pointer Register, shown in Table 210, maps directly to the
RAM_ADDR_U Register within the eZ80F91 device. This register value is read-only.
Table 210. EMAC Boundary Pointer Register, Upper Byte (EMAC_BP_U)
Bit
7
6
5
4
3
2
1
0
Field
EMAC_BP_U
Reset
1
1
1
1
1
1
1
1
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
0046h
Bit
Description
Boundary Pointer Upper Byte
[7:0]
EMAC_BP_U 00h–FFh: These bits represent the upper byte of the 3-byte EMAC Boundary Pointer
value, {EMAC_BP_U, EMAC_BP_H, EMAC_BP_L}. Bit 7 is bit 23 of the 24 bit value. Bit
0 is bit 16 of the 24 bit value.
EMAC Receive High Boundary Pointer High and Low Byte
Registers
The Receive High Boundary Pointer Registers, shown in Table 211 and 212, must be set to
the end of the Receive buffer +1 in EMAC shared memory. This RHBP uses the same
RAM_ADDR_U as the EMAC_BP_U pointer above.
Table 211. EMAC Receive High Boundary Pointer Low Byte Register (EMAC_RHBP_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
EMAC_RHBP_L
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R
R
R
Address
0047h
Note: R = read only, R/W = read/write
Bit
Description
Receive High Boundary Pointer Low Byte
[7:0]
EMAC_RHBP_L 00h–E0h: These bits represent the low byte of the two-byte EMAC Receive High
Boundary Pointer value, {EMAC_RHBP_H, EMAC_RHBP_L}. Bit 7 is bit 7 of the 16-bit
value. Bit 0 is bit 0 (lsb) of the 16-bit value.
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Table 212. EMAC Receive High Boundary Pointer High Byte Register (EMAC_RHBP_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
EMAC_RHBP_H
1
1
0
0
0
0
0
0
R
R
R
R/W
R/W
R/W
R/W
R/W
Address
0048h
Note: R = read only, R/W = read/write.
Bit
Description
Receive High Boundary Pointer High Byte
[7:0]
EMAC_RHBP_H 00h–FFh: These bits represent the high byte of the two-byte EMAC Receive High
Boundary Pointer value, {EMAC_RHBP_H, EMAC_RHBP_L}. Bit 7 is bit 15 (msb) of
the 16-bit value. Bit 0 is bit 8 of the 16-bit value.
Note: *Bits 7:5 are not used by the EMAC; these bits return 000 upon reset.
EMAC Receive Read Pointer High and Low Byte Registers
The Receive Read Pointer Registers, shown in Tables 213 and 214, must be initialized to
the EMAC_BP value (i.e., the start of the Receive buffer). This register points to the
address location in which the next Receive packet is read from. The EMAC_BP[12:5] is
loaded into this register whenever the EMAC_RST [(HRRFN) is set to 1. The RxDMA
block uses Emac_Rrp[12:5] to compare to EmacRwp[12:5] for determining how many
buffers remain. The result equates to the EmacBlksLeft Register.
Table 213. EMAC Receive Read Pointer Low Byte Register (EMAC_RRP_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
EMAC_RRP_L
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R
R
R
Address
0049h
Note: R = read only, R/W = read/write.
Bit
Description
Receive Read Pointer Low Byte
[7:0]
EMAC_RRP_L
00h–FFh: These bits represent the low byte of the two-byte EMAC Receive Read
Pointer value, {EMAC_RRP_H, EMAC_RRP_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0
is bit 0 (lsb) of the 16-bit value.
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Table 214. EMAC Receive Read Pointer High Byte Register (EMAC_RRP_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
EMAC_RRP_H
0
0
0
0
0
0
0
0
R
R
R
R/W
R/W
R/W
R/W
R/W
Address
004Ah
Note: R = read only, R/W = read/write
Bit
Description
Receive Read Pointer High Byte
[7:0]
EMAC_RRP_H
00h–FFh: These bits represent the high byte of the 2-byte EMAC Receive Read
Pointer value, {EMAC_RRP_H, EMAC_RRP_L}. Bit 7 is bit 15 (msb) of the 16-bit
value. Bits 7:5 default to 000 on reset; bit 0 is bit 8 of the 16-bit value.
EMAC Buffer Size Register
The lower six bits of this register set the level at which the EMAC either transmits a pause
control frame or jams the Ethernet bus, depending on the mode selected. When each of
these bits contain a zero, this feature is disabled.
In FULL-DUPLEX Mode, a Pause Control Frame is transmitted as a One-shot operation.
The software must free up a number of Rx buffers so that the number of buffers remaining,
EmacBlksLeft, is greater than TCPF_LEV.
In HALF-DUPLEX Mode, the EMAC jams the Ethernet by sending a continuous stream
of hexadecimal 5s (5fh). When the software frees up the Rx buffers and the number of
buffers remaining, EmacBlksLeft, is greater than TCPF_LEV, the EMAC stops jamming.
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Table 215. EMAC Buffer Size Register (EMAC_BUFSZ)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
BUFSZ
TPCF_LEV
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
004Bh
Note: R/W = read/write.
Bit
Description
[7:6]
Buffer Size Control
BUFSZ
00: Set EMAC Rx/Tx buffer size to 256 bytes.
01: Set EMAC Rx/Tx buffer size to 128 bytes.
10: Set EMAC Rx/Tx buffer size to 64 bytes.
11: Set EMAC Rx/Tx buffer size to 32 bytes.
[5:0]
Transmit Pause Control Frame Level
TPCF_LEV
00h–3Fh: 00h disables the hardware-generated transmit pause control frame.
EMAC Interrupt Enable Register
Enabling the Receive Overrun interrupt allows software to detect an overrun condition as
soon as it occurs. If this interrupt is not set, then an overrun cannot be detected until the
software processes the Receive packet with the overrun and checks the Receive status in
the Rx descriptor table. Because the receiver is disabled by an overrun error until the
Rx_OVR bit is cleared in the EMAC_ISTAT Register, this packet is the final packet in the
Receive buffer. To reenable the receiver before all of the Receive packets are processed
and the Receive buffer is empty, software enables this interrupt to detect the overrun con-
dition early. As it processes the Receive packets, it reenables the receiver when the num-
ber of free buffers is greater than the number of minimum buffers. See Table 216.
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Table 216. EMAC Interrupt Enable Register (EMAC_IEN)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
TxFSMERR MGTDONE Rx_CF Rx_PCF Rx_DONE Rx_OVR Tx_CF Tx_DONE
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
004Ch
Note: R/W = read/write.
Bit
Description
Transmit State Machine Error Interrupt Enable
[7]
TxFSMERR
0: Disable Transmit State Machine Error Interrupt (system interrupt).
1: Enable Transmit State Machine Error Interrupt (system interrupt).
[6]
MGTDONE
Management Done Enable
0: Disable MII Management Done Interrupt (system Interrupt).
1: Enable MII Management Done Interrupt (system Interrupt).
[5]
Rx_CF
Receive Control Frame Interrupt Enable
0: Disable Receive Control Frame Interrupt (Receive interrupt).
1: Enable Receive Control Frame Interrupt (Receive interrupt).
[4]
Rx_PCF
Receive Pause Control Frame Interrupt Enable
0: Disable Receive Pause Control Frame interrupt (Receive interrupt).
1: Enable Receive Pause Control Frame interrupt (Receive interrupt).
[3]
Rx_DONE
Receive Done Interrupt Enable
0: Disable Receive Done interrupt (Receive interrupt).
1: Enable Receive Done interrupt (Receive interrupt).
[2]
Rx_OVR
Receive Overrun Interrupt Enable
0: Disable Receive Overrun interrupt (System interrupt).
1: Enable Receive Overrun interrupt (System interrupt).
[1]
Tx_CF
Transmit Control Frame Interrupt Enable
0: Disable Transmit Control Frame Interrupt (Transmit interrupt).
1: Enable Transmit Control Frame Interrupt (Transmit interrupt).
[0]
Tx_DONE
Transmit Done Interrupt Enable
0: Disable Transmit Done Interrupt (Transmit interrupt).
1: Enable Transmit Done interrupt (Transmit interrupt).
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EMAC Interrupt Status Register
When a Receive overrun occurs, all incoming packets are ignored until the Rx_OVR_STAT
status bit is cleared by software. Consequently, software controls when the receiver is reen-
abled after an overrun. Enable the Rx_OVR interrupt to detect overrun conditions when they
occur. Clear this condition when the Rx buffers are freed to avoid additional overrun errors.
See Table 217.
Note: Status bits are not self-clearing. Each status bit is cleared by writing a 1 into the selected
bit.
Table 217. EMAC Interrupt Status Register (EMAC_ISTAT)
Bit
7
6
5
4
3
2
1
0
Field
TxFSMERR MGTDONE_ Rx_CF_ Rx_PCF_ Rx_DONE_ Rx_OVR_
Tx_CF_ Tx_DONE_
_STAT
STAT
STAT
STAT
STAT
STAT
STAT
STAT
Reset
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
004Dh
Note: R/W = read/write.
Bit
Description
0: Normal operation: no Transmit state machine errors.
[7]
TxFSMERR_STAT
1: An internal error occurs in the EMAC Transmit path. The Transmit path must be
reset to reset this error condition.
[6]
0: The MII Management interrupt does not occur.
MGTDONE_STAT
1: The MII Management interrupt has completed a read (RSTAT or SCAN) or a write
(LDCTLD) access to the PHY.
5
0: Receive Control Frame interrupt does not occur.
Rx_CF_STAT
1: Receive Control Frame interrupt (Receive Interrupt) occurs.
4
0: Disable Receive Pause Control Frame interrupt (Receive Interrupt) does not occur.
1: Receive Pause Control Frame interrupt (Receive Interrupt) occurs.
Rx_PCF_STAT
3
0: Disable Receive Done interrupt (Receive Interrupt) does not occur.
1: Receive Done interrupt (Receive Interrupt) occurs.
Rx_DONE_STAT
2
0: Receive Overrun interrupt (System Interrupt) does not occur.
1: Receive Overrun interrupt (System Interrupt) occurs.
Rx_OVR_STAT
1
0: Transmit Control Frame Interrupt (Transmit Interrupt) does not occur.
1: Transmit Control Frame Interrupt (Transmit Interrupt) occurs.
Tx_CF_STAT
0
0: Transmit Done interrupt (Transmit Interrupt) does not occur.
1: Transmit Done interrupt (Transmit Interrupt) occurs.
Tx_DONE_STAT
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EMAC PHY Read Status Data High and Low Byte Registers
The PHY MII Management Data Registers, shown in Table 218 and 219, store data that is
read from the PHY.
Table 218. EMAC PHY Read Status Data Low Byte Register (EMAC_PRSD_L)
Bit
7
6
5
4
3
2
1
0
Field
EMAC_PRSD_L
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
004Eh
Bit
Description
[7:0]
PHY Read Status Data Low Byte
EMAC_PRSD_L 00h–FFh: These bits represent the low byte of the two-byte EMAC PHY Read Status
Data value, {EMAC_PRSD_H, EMAC_PRSD_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0
is bit 0 (lsb) of the 16-bit value.
Table 219. EMAC PHY Read Status Data High Byte Register (EMAC_PRSD_H)
Bit
7
6
5
4
3
2
1
0
Field
EMAC_PRSD_H
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
004Fh
Bit
Description
[7:0]
PHY Read Status Data High Byte
EMAC_PRSD_H 00h–FFh: These bits represent the high byte of the 2-byte EMAC PHY Read Status
Data value, {EMAC_PRSD_H, EMAC_PRSD_L}. Bit 7 is bit 15 (msb) of the 16-bit
value. Bit 0 is bit 8 of the 16-bit value.
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EMAC MII Status Register
The EMAC MII Status Register, shown in Table 220, is used to determine the current state
of the external PHY device.
Table 220. EMAC MII Status Register (EMAC_MIISTAT)
Bit
7
BUSY
0
6
MIILF
0
5
4
3
2
1
0
Field
Reset
R/W
NVALID
RDADR
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Address
0050h
Note: R = read only.
Bit
Description
[7]
MII Management Operation In Progress
BUSY
0: Not Busy.
1: This status bit goes busy whenever the LCTLD (PHY write) or the RSTAT (PHY read)
is set in the EMAC_MIIMGT Register. It is negated when the write or read operation to
the PHY has completed. In SCAN Mode, the BUSY will be asserted until the SCAN is
disabled. Use the EmacIStat[MGTDONE] interrupt status bit to determine when the
data is valid.
[6]
MII Link Status
MIILF
0: PHY Link OK.
1: Local copy of PHY Link fail bit.
[5]
Read Status Data Valid
NVALID
0: Emac_PRSD is valid.
1: MII Scan result is not valid Emac_PRSD is invalid
[4:0]
Read Address
RDADR
00h–1Fh: Denotes PHY addressed in current scan cycle.
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EMAC Receive Write Pointer Low Byte Register
The read-only Receive Write Pointer Registers, shown in Tables 221 and 222, report the
current RxDMA Receive Write pointer. This pointer gets initialized to EmacTLBP when-
ever Emac_RST bits SRST or HRRTN are set. Because the size of the packet is limited to
a minimum of 32 bytes, the last five bits are always zero.
Table 221. EMAC Receive Write Pointer Low Byte Register (EMAC_RWP_L)
Bit
7
6
5
4
3
2
1
0
Field
EMAC_RWP_L
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
0051h
Bit
Description
[7:0]
EMAC_RWP_L
Receive Write Pointer Low Byte
00h–E0h: These bits represent the low byte of the two-byte EMAC RxDMA Receive
Write Pointer value, {EMAC_RWP_H, EMAC_RWP_L}. Bit 7 is bit 7 of the 16-bit value.
Bit 0 is bit 0 (lsb) of the 16-bit value.
EMAC Receive Write Pointer High Byte Register
Because of the size of the EMAC’s 8KB SRAM space, the upper three bits of the EMAC
Receive Write Pointer Register are always zero; see Table 222.
Table 222. EMAC Receive Write Pointer High Byte Register (EMAC_RWP_H)
Bit
7
6
5
4
3
2
1
0
Field
EMAC_RWP_H
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
0052h
Bit
Description
[7:0]
Receive Write Pointer High Byte
EMAC_RWP_H 00h–1Fh: These bits represent the high byte of the two-byte EMAC RxDMA Receive
Write Pointer value, {EMAC_RWP_H, EMAC_RWP_L}. Bit 7 is bit 15 (msb) of the 16-
bit value. Bit 0 is bit 8 of the 16-bit value.
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EMAC Transmit Read Pointer Low Byte Register
The low byte of the Transmit Read Pointer Register, shown in Table 223, reports the cur-
rent TxDMA Transmit Read pointer.This pointer is initialized to EmacTLBP whenever
Emac_RST bits SRST or HRRTN are set. Because the size of the packet is limited to a
minimum of 32 bytes, the last five bits are always zero.
Table 223. EMAC Transmit Read Pointer Low Byte Register (EMAC_TRP_L)
Bit
7
6
5
4
3
2
1
0
Field
EMAC_TRP_L
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
0053h
Bit
Description
[7:0]
EMAC_TRP_L
Transmit Read Pointer Low Byte
00h–E0h: These bits represent the low byte of the two-byte EMAC TxDMA Transmit
Read Pointer value, {EMAC_TRP_H, EMAC_TRP_L}. Bit 7 is bit 7 of the 16-bit value.
Bit 0 is bit 0 (lsb) of the 16-bit value.
EMAC Transmit Read Pointer High Byte Register
Because of the size of the EMAC’s 8KB SRAM, the upper three bits of the EMAC Trans-
mit Read Pointer Register, shown in Table 224, are always zero.
Table 224. EMAC Transmit Read Pointer High Byte Register (EMAC_TRP_H)
Bit
7
6
5
4
3
2
1
0
Field
EMAC_TRP_H
Reset
0
0
0
0
0
0
0
0
R/W
RO
RO
RO
RO
RO
RO
RO
RO
Address
0054h
Note: R/W = read/write.
Bit
Description
Transmit Read Pointer High Byte
[7:0]
EMAC_TRP_H
00h–1Fh: These bits represent the high byte of the two-byte EMAC TxDMA Transmit
Read Pointer value, {EMAC_TRP_H, EMAC_TRP_L}. Bit 7 is bit 15 (msb) of the 16-bit
value. Bit 0 is bit 8 of the 16-bit value.
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EMAC Receive Blocks Left High and Low Byte Registers
This register reports the number of buffers left in Receive EMAC shared memory. The
hardware uses this information along with the block-level set in the EMAC_BUFSZ Reg-
ister to determine when to transmit a pause control frame. Software uses this information
to determine when it must request that a pause control frame be transmitted (by setting bit
6 of the EMAC_CFG4 Register). For the BlksLeft logic to operate properly, the Receive
buffer must contain at least one more packet buffer than the number of packet buffers
required for the largest packet. That is, one packet cannot fill the entire Receive buffer.
Otherwise, BlksLeft will be in error. See Tables 225 and 226.
Table 225. EMAC Receive Blocks Left Low Byte Register (EMAC_BLKSLFT_L)
Bit
7
6
5
4
3
2
1
0
Field
EMAC_BLKSLFT_L
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
0055h
Bit
Description
[7:0]
Receive Blocks Left Low Byte
EMAC_BLKSLFT_L 00h–FFh: These bits represent the low byte of the two-byte EMAC Receive Blocks
Left value, {EMAC_BLKSLFT_H, EMAC_BLKSLFT_L}. Bit 7 is bit 7 of the 16-bit
value. Bit 0 is bit 0 (lsb) of the 16-bit value.
Table 226. EMAC Receive Blocks Left High Byte Register (EMAC_BLKSLFT_H)
Bit
7
6
5
4
3
2
1
0
Field
EMAC_BLKSLFT_H
Reset
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
0056h
Bit
Description
[7:0]
Receive Blocks Left High Byte
EMAC_BLKSLFT_H 00h–FFh: These bits represent the high byte of the two-byte EMAC Receive Blocks
Left value, {EMAC_BLKSLFT_H, EMAC_BLKSLFT_L}. Bit 7 is bit 15 (msb) of the
16-bit value. Bit 0 is bit 8 of the 16-bit value.
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EMAC FIFO Data High and Low Byte Registers
The read/write FIFO Test Access Data Registers, shown in Tables 227 and 228, allow the
writing and reading of the FIFO selected by the EMAC_TEST TxRx_SEL bit when the
EMAC_TEST Register TEST_FIFO bit is set.
Table 227. EMAC FIFO Data Low Byte Register (EMAC_FDATA_L)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
EMAC_FDATA_L
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
0057h
Note: U = undefined; R/W = read/write.
Bit
Description
[7:0]
FIFO Data Low Byte
EMAC_FDATA_L 00h–FFh: These bits represent the low byte of the 10 bit EMAC FIFO data value,
{EMAC_FDATA_H[1:0], EMAC_FDATA_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is bit 0
(lsb) of the 10 bit value.
Table 228. EMAC FIFO Data High Byte Register (EMAC_FDATA_H)
Bit
7
6
5
4
3
2
1
0
Field
Reset
R/W
Reserved
EMAC_FDATA_H
0
0
0
0
0
0
U
U
R
R
R
R
R
R
R/W
R/W
Address
0058h
Note: U = undefined; R = read only; R/W = read/write.
Bit
Description
Reserved
[7:2]
These bits are reserved and must be programmed to 00h.
[1:0]
FIFO Data High Byte
EMAC_FDATA_H 0h–3h: These bits represent the upper two bits of the 10 bit EMAC FIFO data value,
{EMAC_FDATA_H[1:0], EMAC_FDATA_L}. Bit 1 is bit 9 (msb) of the 16-bit value. Bit 0
is bit 8 of the 10 bit value.
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EMAC FIFO Flags Register
The FIFO Flags value is set in the EMAC hardware to half full, or 16 bytes. See Table 229.
Table 229. EMAC FIFO Flags Register (EMAC_FFLAGS)
Bit
7
TFF
0
6
5
TFAE
1
4
TFE
1
3
RFF
0
2
RFAF
0
1
RFAE
1
0
RFE
1
Field
Reset
0
R/W
R
R
R
R
R
R
R
R
Address
Note: R = read only.
0059h
Bit
Description
[7]
Transmit FIFO Full
TFF
0: Transmit FIFO not full.
1: Transmit FIFO full.
[6]
Reserved
This bit is reserved and must be programmed to 0.
[5]
TFAE
Transmit FIFO Almost Empty
0: Transmit FIFO not almost empty.
1: Transmit FIFO almost empty.
[4]
TFE
Transmit FIFO Empty
0: Transmit FIFO not empty.
1: Transmit FIFO empty.
[3]
Receive FIFO Full
RFF
0: Receive FIFO not full.
1: Receive FIFO full.
[2]
RFAF
Receive FIFO Almost Full
0: Receive FIFO not almost full.
1: Receive FIFO almost full.
[1]
RFAE
Receive FIFO Almost Empty
0: Receive FIFO not almost empty.
1: Receive FIFO almost empty.
[0]
Receive FIFO Empty
RFE
0: Receive FIFO not empty.
1: Receive FIFO empty.
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On-Chip Oscillators
The eZ80F91 features two on-chip oscillators for use with an external crystal. The primary
oscillator generates the system clock for the internal CPU and the majority of the on-chip
peripherals. Alternatively, the XIN input pin also accepts a CMOS-level clock input signal.
If an external clock generator is used, the XOUT pin must be left unconnected. The second-
ary oscillator drives a 32 kHz crystal to generate the time-base for the Real-Time Clock.
Primary Crystal Oscillator Operation
Figure 63 shows a recommended configuration for connection with an external 50MHz,
3rd-overtone, parallel-resonant crystal. Recommended crystal specifications are provided
in Tables 230 and 231. Printed circuit board layout must add not more than 4 pF of stray
capacitance to either the XIN or XOUT pins. If oscillation does not occur, try removing C1
for testing and decreasing the value of C2 by the estimated stray capacitance to decrease
loading.
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333
On-Chip Oscillator
XIN
XOUT
50 MHz Crystal
(Third Overtone)
R = 100 Kꢁ
C1= 5 pF
(this value is not critical)
C2= 10-15 pF
L = 3.3 ꢀH ( 10%)
C3 = .01-0.1 ꢀF
Figure 63. Recommended Crystal Oscillator Configuration: 50MHz Operation
Table 230. Recommended Crystal Oscillator Specifications: 1MHz Operation
Frequency-
Parameter
Frequency
Resonance
Mode
Dependent Value
Units
Comments
1
MHz
Parallel
Fundamental
750
Series Resistance (R )
Ohms
pF
Maximum
Maximum
S
Load Capacitance (C )
13
L
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eZ80F91 ASSP
Product Specification
334
Table 230. Recommended Crystal Oscillator Specifications: 1MHz Operation (Continued)
Frequency-
Parameter
Dependent Value
Units
Comments
Maximum
Maximum
Shunt Capacitance (C )
7
1
pF
0
Drive Level
mW
Table 231. Recommended Crystal Oscillator Specifications: 10 MHz Operation
Frequency-
Parameter
Frequency
Resonance
Mode
Dependent Value
Units
Comments
10
MHz
Parallel
Fundamental
Series Resistance (R )
35
30
7
Ohms
pF
Maximum
Maximum
Maximum
Maximum
S
Load Capacitance (C )
L
Shunt Capacitance (C )
pF
0
Drive Level
1
mW
32kHz Real-Time Clock Crystal Oscillator Operation
Figure 64 shows a recommended configuration for connecting the Real-Time Clock oscil-
lator with an external 32kHz, fundamental mode, parallel-resonant crystal. The recom-
mended crystal specifications are provided in Table 232. A printed circuit board layout
must not add more than 4 pF of stray capacitance to either the RTC_XIN or RTC_XOUT
pins. If oscillation does not occur, reduce the values of capacitors C1 and C2 to decrease
loading.
An on-chip MOS resistor sets the crystal drive current limit. This configuration does not
require an external bias resistor across the crystal. An on-chip MOS resistor provides the
biasing.
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335
On-Chip Oscillator
RTC_XIN
RTC_XOUT
32 kHz Crystal
(Fundamental Mode)
C1 = 10 pF
C2 = 10 pF
Figure 64. Recommended Crystal Oscillator Configuration: 32kHz Operation
Table 232. Recommended Crystal Oscillator Specifications: 32kHz Operation
Parameter
Frequency
Resonance
Mode
Value
Units
Comments
32
kHz
32768Hz
Parallel
Fundamental
Series Resistance (R )
50
12.5
3
kΩ
pF
pF
µW
Maximum
Maximum
Maximum
Maximum
S
Load Capacitance (C )
L
Shunt Capacitance (C )
0
Drive Level
1
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Electrical Characteristics
This chapter presents the following sections, which offer characterization details about the
eZ80F91 ASSP device.
Absolute Maximum Ratings – see page 336
DC Characteristics – see page 338
POR and VBO Electrical Characteristics – see page 339
Flash Memory Characteristics – see page 339
Current Consumption Under Various Operating Conditions – see page 340
AC Characteristics – see page 343
External Memory Read Timing – see page 344
External Memory Write Timing – see page 345
External I/O Read Timing – see page 346
External I/O Write Timing – see page 347
Wait State Timing for Read Operations – see page 349
Wait State Timing for Write Operations – see page 350
General-Purpose Input/Output Port Input Sample Timing – see page 351
General-Purpose Input/Output Port Output Timing – see page 351
External Bus Acknowledge Timing – see page 352
Absolute Maximum Ratings
Stresses greater than those listed in Table 233 causes permanent damage to the device. These
ratings are stress ratings only. Operation of the device at any condition outside those indi-
cated in the operational sections of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods affects device reliability. For improved
reliability, unused inputs must be tied to one of the supply voltages (V or V ).
DD
SS
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Table 233. Absolute Maximum Ratings
Minimum Maximum Units
Parameter
Notes
Ambient temperature under bias (ºC)
Storage temperature (ºC)
–40
–65
+105
+150
+5.5
+3.6
830
230
230
+15
+8
ºC
C
1
Voltage on any pin with respect to V
–0.3
–0.3
V
2
SS
Voltage on V pin with respect to V
V
DD
SS
Total power dissipation
mW
mA
mA
µA
mA
Maximum current out of V
SS
Maximum current into V
DD
Maximum current on input and/or inactive output pin
–15
–8
Maximum output current from active output pin
(except PORT A pins)
Maximum PORT A output SOURCE current from active out-
put pin
+8
mA
mA
Maximum PORT A output SINK current from active output
pin
+10
Flash memory writes to Same Single Address
Flash Memory Data Retention
–
2
–
–
–
3
4
100
Years
Cycles
Flash Memory Write/Erase Endurance
10,000
Notes:
1. Operating temperature is specified in DC Characteristics.
2. This voltage applies to all pins except X and X
3. Before next erase operation.
4. Write cycles.
.
IN
OUT
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DC Characteristics
Table 234 lists the DC characteristics of the eZ80F91 device.
Table 234. DC Characteristics
T = 0ºC to 70ºC
T = –40ºC to 105ºC
A
A
1
1
Symbol Parameter
Min.
Typ.
Max.
Min.
3.0
Typ.
Max. Units Conditions
V
V
Supply Voltage
3.0
3.3
3.6
3.3
3.6
V
V
DD
IL
Low Level Input
Voltage
–0.3
0.3 x
–0.3
0.3 x
V
V
DD
DD
V
V
V
V
I
High Level Input
Voltage
0.7x
5.5
0.7 x
5.5
0.4
V
V
IH
V
V
DD
DD
Low Level Output
Voltage
0.4
V
= 3.0V;
DD
= 1mA
OL
OH
RTC
I
OL
High Level Output
Voltage
2.4
2.0
2.4
2.0
V
V
= 3.0 V;
DD
I
= –1 mA
OH
RTC Supply
Voltage
3.6
3.6
V
Input Leakage
Current
–10
+10
–10
+10
µA
V
V
V
= 3.6V;
DD
IL
= V or
IN
DD
2
SS
I
I
Open-drain
Leakage Current
–10
+10
–10
+10
µA
V
= 3.6V
DD
TL
a
Active Current
26
52
40
80
mA @ 10MHz
mA @ 20MHz
mA @ 50MHz
mA @ 10MHz
mA @ 20MHz
mA @ 50MHz
CC
CC
CC
137
15
190
20
I
HALT Mode
Current
h
27
40
75
100
95
I
I
SLEEP Mode
Current
2.5
2.5
20
10
2.5
µA VBO_OFF=1
(VBO disabled)
s
RTC Supply
Current
2.5
10
µA Supply current
RTC
3
into V
RTC
Notes:
1. Values in Typical column are for V
= 3.3 V and TA = 25ºC.
DD
2. This condition excludes all pins with on-chip pull-ups when driven Low.
3. In the Real Time Clock Control (RTC_CTRL) Register, CLK_SEL and RTC_UNLOCK must be cleared to 0; V
= 0V.
DD
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POR and VBO Electrical Characteristics
Table 235 lists the Power-On Reset and Voltage Brown-Out characteristics of the eZ80F91
ASSP device.
Table 235. POR and VBO Electrical Characteristics
T = –40ºC to 105ºC
A
Symbol
Parameter
Min.
2.45
2.55
30
Typ.
2.65
2.75
100
Max. Units Conditions
V
V
V
VBO Voltage Threshold
POR Voltage Threshold
POR/VBO Hysteresis
2.90
2.95
120
100
V
V
V
V
= V
= V
VBO
POR
HYST
CC
CC
VBO
POR
mV
µs
µs
µA
T
POR/VBO analog RESET duration
VBO pulse reject period
POR/VBO DC current consumption
40
ANA
T
10
40
VBO_MIN
POR_VBO
I
50
IS
POR/VBO DC Sleep Mode current
consumption
120
150
µA VBO_OFF=0
(VBO enabled)
POR_VBO
VCC
V
ramp rate requirements to guar-
0.1
100
V/ms
RAMP
CC
antee proper RESET occurs
Flash Memory Characteristics
Table 236 lists the Flash memory characteristics of the eZ80F91 device. For Flash pro-
gramming and erase timing information, see Flash Memory.
Table 236. Flash Memory Electrical Characteristics and Timing
V
= 3.0 V to 3.6 V;
DD
T = –40ºC to 105ºC
A
Symbol
Min.
Typ.
Max.
Unit
Flash Byte Read Cycle Time
78
–
–
ns
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Current Consumption Under Various Operating Conditions
Figure 65 shows the typical current consumption of the eZ80F91 ASSP device versus
VDD while operating at 25ºC, with zero wait states, and with either a 10MHz, 20MHz, or
50MHz system clock.
eZ80F91 Active IDD vs CLK Freq. @ VDD (25°C)
180.00
160.00
140.00
120.00
100.00
80.00
60.00
40.00
20.00
0.00
10Mhz
20Mhz
50Mhz
Frequency (M Hz)
VDD=2.9V
VDD=3.3V
VDD=3.7V
Figure 65. I vs. System Clock Frequency During ACTIVE Mode
CC
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Figure 66 shows the typical current consumption of the eZ80F91 ASSP device versus sys-
tem clock frequency while operating in HALT Mode.
eZ80F91 HALT Mode IDD vs CLK Freq @ VDD (25°C)
100.00
90.00
80.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.00
10Mhz
20Mhz
50Mhz
Fre que ncy (M Hz)
V DD=2.9V
V DD=3.3V
V DD=3.7V
Figure 66. I vs. System Clock Frequency During HALT Mode
CC
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Figure 67 shows the typical current consumption of the eZ80F91 ASSP device versus
VDD while operating in SLEEP Mode (units in microamps, 10–6A); all peripherals off, and
VBO disabled.
e Z80F91 S LEEP M ode IDD vs V DD (25°C)
2.65
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.9
3.3
3.7
V D D (V )
IC C S (V BO dis abled)
Figure 67. I vs. V During SLEEP Mode
CC
DD
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AC Characteristics
This section provides information about the AC characteristics and timing of the eZ80F91
device. All AC timing information assumes a standard load of 50 pF on all outputs. See
Table 237.
Table 237. AC Characteristics
T = 0ºC to 70ºC
T = –40ºC to 105ºC
A
A
Symbol Parameter
Min.
Max.
Min.
Max.
Units Conditions
T
T
T
T
T
System Clock
Cycle Time
20
1000
20
1000
ns
ns
ns
ns
ns
pF
V
= 3.0–3.6 V
XIN
DD
System Clock
High Time
8
8
8
8
V
= 3.0–3.6 V;
= 20ns
XINH
XINL
XINR
XINF
DD
T
CLK
System Clock
Low Time
V
= 3.0–3.6 V;
= 20ns
DD
T
CLK
System Clock
Rise Time
3
3
3
3
V
= 3.0–3.6 V;
= 20ns
DD
T
CLK
System Clock
Fall Time
V
= 3.0–3.6 V;
= 20 ns
DD
T
CLK
C
Input capaci-
tance
10 typical
10 typical
IN
Table 238 lists simulated inductance, capacitance, and resistance results for the 144-pin
LQFP (vendor-supplied) package at 100MHz operating frequency.
Table 238. Typical 144-LQFP Package Electrical Characteristics
Lead
Inductance (nH)
6.430
Capacitance (pF)
1.100
Resistance (MΩ)
Longest
Shortest
62.9
52.6
4.230
1.070
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External Memory Read Timing
Figure 68 and Table 239 show the timing for external memory reads.
TCLK
PHI
T1
T2
ADDR[23:0]
T3
T4
DATA[7:0]
(input)
T5
T6
CSx
T7
T9
T8
MREQ
RD
T10
Figure 68. External Memory Read Timing
Table 239. External Memory Read Timing
Delay (ns)
Parameter Abbreviation
Min.
Max.
8.5
–
T
T
T
T
T
T
T
T
T
T
PHI Clock Rise to ADDR Valid Delay
PHI Clock Rise to ADDR Hold Time
–
1
1.0
0.5
0.5
2.6
0.0
2.6
1.0
2.7
1.0
2
DATA Valid to PHI Clock Rise Setup Time
PHI Clock Rise to DATA Hold Time
–
3
–
4
PHI Clock Rise to CSx Assertion Delay
PHI Clock Rise to CSx Deassertion Delay
PHI Clock Rise to MREQ Assertion Delay
PHI Clock Rise to MREQ Deassertion Delay
PHI Clock Rise to RD Assertion Delay
PHI Clock Rise to RD Deassertion Delay
8.0
6.0
7.0
6.3
7.0
6.3
5
6
7
8
9
10
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External Memory Write Timing
Figure 69 and Table 240 show the timing for external memory writes.
TCLK
PHI
T2
T4
T1
ADDR[23:0]
T3
DATA[7:0]
(output)
T5
T6
CSx
T7
T8
MREQ
WR
T9
T10
Figure 69. External Memory Write Timing
Table 240. External Memory Write Timing
Delay (ns)
Parameter Abbreviation
Min.
–
Max.
8.5
–
T
T
T
T
T
T
T
PHI Clock Rise to ADDR Valid Delay
PHI Clock Rise to ADDR Hold Time
PHI Clock Fall to DATA Valid
1
2
3
4
5
6
7
1
–
2.5
–
PHI Clock Rise to DATA Hold Time
PHI Clock Rise to CSx Assertion Delay
PHI Clock Rise to CSx Deassertion Delay
PHI Clock Rise to MREQ Assertion Delay
1.0
2.3
0.0
2.3
10.8
6.0
7.0
Note: *At the conclusion of a write cycle, deassertion of WR always occurs before any change to
ADDR, DATA, CSx, or MREQ.
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Table 240. External Memory Write Timing (Continued)
Delay (ns)
Min.
Parameter Abbreviation
Max.
6.5
1.0
5.0
–
T
T
T
PHI Clock Rise to MREQ Deassertion Delay
PHI Clock Fall to WR Assertion Delay
PHI Clock Rise to WR Deassertion Delay*
WR Deassertion to ADDR Hold Time
WR Deassertion to DATA Hold Time
WR Deassertion to CSx Hold Time
2.3
–
8
9
0.0
0.4
0.5
1.2
0.5
10
–
–
WR Deassertion to MREQ Hold Time
–
Note: *At the conclusion of a write cycle, deassertion of WR always occurs before any change to
ADDR, DATA, CSx, or MREQ.
External I/O Read Timing
Figure 70 and Table 241 show the timing for external I/O reads. PHI clock rise/fall to sig-
nal transition timing is independent of the particular bus mode employed (eZ80, Z80,
Intel, or Motorola).
TCLK
PHI
T1
T2
ADDR[23:0]
T3
T4
DATA[7:0]
(input)
T5
T6
CSx
T7
T9
T8
IORQ
RD
T10
Figure 70. External I/O Read Timing
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Table 241. External I/O Read Timing
Delay (ns)
Parameter Abbreviation
Min.
Max.
7.3
–
T
T
T
T
T
T
T
T
T
T
PHI Clock Rise to ADDR Valid Delay
PHI Clock Rise to ADDR Hold Time
–
1
1.0
0.5
0.0
2.0
0.0
2.6
1.0
2.7
0.5
2
DATA Valid to PHI Clock Rise Setup Time
PHI Clock Rise to DATA Hold Time
–
3
–
4
PHI Clock Rise to CSx Assertion Delay
PHI Clock Rise to CSx Deassertion Delay
PHI Clock Rise to IORQ Assertion Delay
PHI Clock Rise to IORQ Deassertion Delay
PHI Clock Rise to RD Assertion Delay
PHI Clock Rise to RD Deassertion Delay
8.5
6.0
7.0
6.3
7.0
6.3
5
6
7
8
9
10
External I/O Write Timing
Figure 71 and Table 242 show the timing for external I/O writes. PHI clock rise/fall to sig-
nal transition timing is independent of the particular bus mode employed (eZ80, Z80,
Intel, or Motorola).
TCLK
PHI
T2
T4
T1
ADDR[23:0]
T3
DATA[7:0]
(output)
T5
T6
CSx
T7
T8
IORQ
WR
T9
T10
Figure 71. External I/O Write Timing
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Table 242. External I/O Write Timing
Delay (ns)
Parameter Abbreviation
Min.
Max.
7.3
–
T
T
T
T
T
T
T
T
T
T
PHI Clock Rise to ADDR Valid Delay
PHI Clock Rise to ADDR Hold Time
PHI Clock Fall to DATA Valid
–
1
1.0
–
2
2.5
–
3
PHI Clock Rise to DATA Hold Time
PHI Clock Rise to CSx Assertion Delay
PHI Clock Rise to CSx Deassertion Delay
PHI Clock Rise to IORQ Assertion Delay
PHI Clock Rise to IORQ Deassertion Delay
PHI Clock Fall to WR Assertion Delay
PHI Clock Rise to WR Deassertion Delay*
WR Deassertion to ADDR Hold Time
WR Deassertion to DATA Hold Time
WR Deassertion to CSx Hold Time
WR Deassertion to IORQ Hold Time
1.0
2.3
1.0
2.4
1.0
–
4
10.8
6.0
7.0
6.3
1.0
5.0
–
5
6
7
8
9
0.0
0.4
0.5
1.2
0.5
10
–
–
–
Note: *At the conclusion of a write cycle, deassertion of WR always occurs before any change to
ADDR, DATA, CSx, or IORQ.
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Wait State Timing for Read Operations
Figure 72 shows the extension of the memory access signals using a single wait state for a
read operation. This wait state is generated by setting CS_WAIT to 001 in the Chip Select
Control Register.
TCLK
TWAIT
SCLK
ADDR[23:0]
DATA[7:0]
(output)
CSx
MREQ
RD
INSTRD
Figure 72. Wait State Timing for Read Operations
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Wait State Timing for Write Operations
Figure 73 shows the extension of the memory access signals using a single wait state for a
write operation. This wait state is generated by setting CS_WAIT to 001 in the Chip Select
Control Register.
TCLK
TWAIT
PHI
ADDR[23:0]
DATA[7:0]
(output)
CSx
MREQ
WR
Figure 73. Wait State Timing for Write Operations
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General-Purpose Input/Output Port Input Sample Timing
Figure 74 shows timing of the GPIO input sampling. The input value on a GPIO port pin is
sampled on the rising edge of the system clock. The port value is then available to the
CPU on the second rising clock edge following the change of the port value.
TCLK
PHI
Port Value
Changes to 0
GPIO Pin
Input Value
GPIO Input
Data Latch
0 Latched
Into GPIO
Data Register
GPIO Data Register
Value 0 Read
by eZ80
GPIO Data
READ on Data Bus
Figure 74. Port Input Sample Timing
General-Purpose Input/Output Port Output Timing
Figure 75 and Table 243 show timing information for the GPIO port output pins.
TCLK
PHI
Port Output
T1
T2
Figure 75. GPIO Port Output Timing
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Table 243. GPIO Port Output Timing
Delay (ns)
Parameter Abbreviation
Min.
Max.
T
T
PHI Clock Rise to Port Output Valid Delay
PHI Clock Rise to Port Output Hold Time
–
5
–
1
2
1.0
External Bus Acknowledge Timing
Table 244 lists information about the bus acknowledge timing.
Table 244. Bus Acknowledge Timing
Delay (ns)
Parameter Abbreviation
Min.
2.8
1.5
Max.
7.1
T
T
PHI Clock Rise to BUSACK Assertion Delay
PHI Clock Rise to BUSACK Deassertion Delay
1
2
6.5
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353
Packaging
Zilog’s eZ80F91 ASSP product is based on the eZ80 CPU, and is available in the 64-pin
Low-Profile Quad Flat Package (LQFP).
Current diagrams for this package are published in Zilog’s Packaging Product Specifica-
tion (PS0072), which is available free for download from the Zilog website.
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eZ80F91 ASSP
Product Specification
354
Ordering Information
Table 245 provides a part name, a product specification index code, and a brief description
of each part. Order the eZ80F91 ASSP device from Zilog using the part numbers in this
table. For more information about ordering, please consult your local Zilog sales office.
The Zilog website (www.zilog.com) lists all regional offices and provides additional
eZ80F91 ASSP product information.
Table 245. Ordering Information
Part
PSI
Description
eZ80F91
eZ80F91AZA50SG
eZ80F91AZA50EG
eZ80F91NAA50SG
eZ80F91NAA50EG
144-LQFP, 256KB Flash memory, 8KB SRAM, 50MHz, Standard
Temperature
144-LQFP, 256KB Flash memory, 8 KB SRAM, 50MHz, Extended
Temperature
144-BGA, 256KB Flash memory, 8 KB SRAM, 50MHz, Standard
Temperature
144-BGA, 256KB Flash memory, 8 KB SRAM, 50MHz, Extended
Temperature
eZ80F910300KITG
eZ80F910300ZCOG
eZ80F910200KITG
eZ80F916005MODG
eZ80F917050SBCG
eZ80AcclaimPlus! Development Kit
eZ80F91 Development Kit
eZ80AcclaimPlus! Modular Development Kit
eZ80F91 Mini Enet Module
Zdots Single Board Computer
ZUSBSC00100ZACG USB Smart Cable
ZENETSC0100ZACG Ethernet Smart Cable
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eZ80F91 ASSP
Product Specification
355
Part Number Description
Zilog part numbers consists of number of components as described below:
eZ80 F91 AZ A50
S
C
Environmental Flow
C = Plastic Standard
G = Lead-Free
Temperature Range
S = Standard, 0 °C to 70 °C
E = Extended, –40 °C to +105 °C
Speed
A = eZ80AcclaimPlus!
50 = Speed
Package
AZ = 144-pin LQFP (also called VQFP)
NA = 144-pin BGA
Product Number
Zilog eZ80 CPU
Example. Part number eZ80F91AZA50SC is an eZ80AcclaimPlus! product in a 144-pin
LQFP package operating with a 50MHz external clock frequency over a 0ºC to +70ºC
temperature range and built using the Plastic Standard environmental flow.
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Z16FMC Series Motor Control MCUs
Product Specification
356
Index
80, 83, 84, 157, 238, 248, 254
24-bit 26
Numerics
100-pin LQFP package 4
Addressing, I2C 220
16-bit clock divisor value 179, 204
16-bit divisor count 179, 204
32 KHz Real-Time Clock Crystal Oscillator Opera-
tion 334
ALARM 170
bit flag 170
alarm condition 156, 157, 170
alarm flag 156
AND/OR Gating of the PWM Outputs 144, 145
Arbiter, EMAC 288
A
Arbitration, I2C 213
AAK 215, 216, 217, 218, 219, 220, 224, 225
Absolute Maximum Ratings 336
AC Characteristics 343
ACK 211, 215, 216, 217, 218, 221, 226, 227
asynchronous communications protocol 172, 173
bits 174
asynchronous serial data 11, 14
Acknowledge 211
I2C 211
ADDR0 6
B
Basic Timer Operation 118
Basic Timer Register Set 125
Baud Rate Generator 178
ADDR1 6
ADDR10 6
ADDR11 6
ADDR12 7
ADDR13 7
ADDR14 7
ADDR15 7
ADDR16 7
ADDR17 7
ADDR18 7
ADDR19 7
ADDR2 6
ADDR20 7
ADDR21 7
ADDR22 7
ADDR23 7
ADDR3 6
Functional Description 202
BCD—see binary-coded decimal operation 155
binary operation 155, 157, 158, 159, 162, 163, 164,
165, 166, 167, 168
binary-coded decimal operation 155, 157, 160, 161,
162, 163, 164, 165, 166, 167, 168, 170
bit generation 172, 173
block diagram 2
boot block 24, 94, 104, 106
boundary scan architecture 256
Boundary Scan Cell Functionality 259
Boundary Scan Instructions 264
break detection 172, 183
Break Point Halting 122
break point trigger functions 256
BRG Control Registers 179
bus acknowledge cycle 6, 8, 9, 67, 87, 88, 89, 91
bus acknowledge pin 67, 248
Bus Arbiter 87
ADDR4 6
ADDR5 6
ADDR6 6
ADDR7 6
ADDR8 6
ADDR9 6
Bus Arbitration Overview 209
Bus Clock Speed, I2C 229
address bus 6, 7, 55, 65, 67, 68, 69, 72, 73, 76, 79,
PS027004-0613
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
357
Bus Mode Controller 68
bus mode state 68, 69, 73
bus modes 68, 82, 86
Switching Between 82
Bus Requests During ZDI Debug Mode 238
bus timing 68
Control Transfers, UART 176
CPHA—see clock phase 199, 200, 205
CPOL—see clock polarity 200, 205
CRC 293, 294, 298, 299, 310
CRS 22, 306
CS0 7, 62, 63, 64, 65
CS1 7, 62, 63, 64, 65
CS2 7, 62, 64, 65
BUSACK 9, 67, 238, 248, 254, 352
pin 87, 248, 254
BUSREQ 9, 67, 254
CS3 7, 62, 64, 65
pin 87, 238, 248, 254
CTS 188, 191
CTS0 12, 196
Byte Format, I2C 211
CTS1 15
Customer Support 370
C
C source-level debugging 230
capture flag 124
carrier sense 302, 306
D
data bus 8, 67, 68, 71, 72, 73, 76, 80, 86, 157, 238,
window 307
248, 254
window referencing 307
MII 22
Chain Sequence and Length, JTAG Boundary Scan
259
data carrier detect 13, 16, 191
data set ready 13, 16, 191
data terminal ready 12, 15, 188
Data Transfer Procedure with SPI configured as a
Slave 203
charge pump 265, 269
PLL 266
Data Transfer Procedure with SPI Configured as the
Master 203
data transfer, SPI 206
Data Transfers, UART 177
Data Validity, I2C 210
DATA0 8
Chip Select Registers 83
Chip Select x Bus Mode Control Register 86
Chip Select x Lower Bound Register 83
chip select/wait state generator block 6
Chip Selects During Bus Request/Bus Acknowl-
edge Cycles 67
DATA1 8
clear to send 12, 15, 191
CLK_MUX 269
DATA2 8
DATA3 8
clock divisor value, 16-bit 179, 204
clock initialization circuitry 257
Clock Peripheral Power-Down Registers 42
clock phase 199
DATA4 8
DATA5 8
DATA6 8
DATA7 8
bit 201
clock polarity bit 201
DC Characteristics 337
DCD 188, 191
Clock Synchronization for Handshake 214
Clock Synchronization, I2C 212
Clocking Overview 209
COL 22
DCD0 13, 196
DCD1 16
DCTS 191
DDCD 191
complex triggers 256
DDSR 191
CONTINUOUS Mode 117, 119, 121, 122, 128, 134
Divider, PLL 266
PS027004-0613
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
358
divisor count 204
16-bit 179
EMAC Non-Back-To-Back IPG Register—Part 2
307
DSR 188, 191
DSR0 13, 196
DSR1 16
EMAC PHY Address Register 314
EMAC PHY Configuration Data Register—Low
Byte 312
DTACK 80
DTR 188, 191
DTR0 12, 196
DTR1 15
EMAC PHY Read Status Data Register—Low and
High Bytes 325
EMAC PHY Unit Select Address Register 314
EMAC RAM 90, 91, 92, 93
EMAC Receive Blocks Left Register—Low and
High Bytes 329
E
EMAC Receive High Boundary Pointer Register—
Low and High Bytes 319
EC0 17, 122, 125, 128
EMAC Receive Read Pointer Register—Low and
High Bytes 320
EMAC Receive Write Pointer Register—High Byte
327
EC1 22, 122, 125, 128
Edge-Triggered Interrupts 50, 51
EI, Op Code Map 279
EMAC 286
EMAC Receive Write Pointer Register—Low Byte
327
EMAC receiver interrupts 291
EMAC Registers 296
EMAC Reset Control Register 315
EMAC Shared Memory Organization 292
EMAC Station Address Register 303
EMAC system interrupts 291
EMAC Test Register 296
EMAC Transmit Lower Boundary Pointer Regis-
ter—Low and High Bytes 317
EMAC Transmit Pause Timer Value Register—
Low and High Bytes 304
EMAC Address Filter Register 310
EMAC Boundary Pointer Register—Low and High
Bytes 318
EMAC Boundary Pointer Register—Upper Byte
319
EMAC Buffer Size Register 321
EMAC Configuration Register 1 298
EMAC Configuration Register 2 300
EMAC Configuration Register 3 301
EMAC Configuration Register 4 302
EMAC FIFO Data Register—Low and High Bytes
330
EMAC FIFO Flags Register 331
EMAC Functional Description 287
EMAC Hash Table Register 310
EMAC Interpacket Gap 304
EMAC Interpacket Gap Register 306
EMAC Interrupt Enable Register 322
EMAC Interrupt Status Register 324
EMAC Interrupts 291
EMAC Transmit Polling Timer Register 315
EMAC Transmit Read Pointer Register—High
Byte 328
EMAC Transmit Read Pointer Register—Low Byte
328
EMAC transmitter interrupts 291
EMACMII module 286
Enabling and Disabling the WDT 112
endec 193, 194, 196, 197
IrDA 43
signal pins 196
ENDEC Mode 301, 305
Erasing Flash Memory 98
EMAC Maximum Frame Length Register—Low
and High Bytes 308
EMAC memory 288, 289
EMAC MII Management Register 311
EMAC MII Status Register 326
EMAC Non-Back-To-Back IPG Register—Part 1
307
Ethernet Media Access Controller 286
PS027004-0613
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
359
event count input 128
Flash Page Select Register 107
EVENT COUNT Mode 123
event counter 121, 122, 123
External Bus Acknowledge Timing 352
external bus master 87, 88
Flash Program Control Register 109
Flash Row Select Register 108
Flash Write/Erase Protection Register 104
frame check sequence 304
external bus request 67, 233, 238
External I/O Read Timing 346
External I/O Write Timing 347
External Memory Read Timing 344
External Memory Write Timing 345
external pull-down resistor 48
framing error 172, 174, 183, 189
frequency divider 95, 103
full-duplex transmission 201
Functional Description, Infrared Encoder/Decoder
193
Functional Description, Serial Peripheral Interface
201
External Reset Input and Indicator 38
eZ80 BUS Mode 68, 86
eZ80 CPU 8, 66, 67, 72, 80, 193, 241, 256
eZ80 Product ID Low and High Byte Registers 250
eZ80 Product ID Revision Register 251
eZ80AcclaimPlus! Flash Microcontrollers 1, 95
eZ80F91 ASSP Block Diagram 3
eZ80F91 ASSP device 2, 4, 6, 8, 9, 19, 26, 54, 55,
65, 111
G
General Purpose I/O Port Input Sample Timing 351
General Purpose I/O Port Output Timing 351
General-Purpose Input/Output 45
GND 2
GPIO Control Registers 51
GPIO Interrupts 50
eZ80F92 MCU 251
GPIO modes 48, 49
GPIO Operation 45
GPIO Overview 45
F
falling edge 143, 144, 146, 151
FAST Mode 209, 229
GPIO port pins 38, 45, 52, 351
FCS 294, 295, 304
Features 1
eZ80 CPU core 37
FIFO Mode 173, 176
Flash address registers 96, 97, 100, 107
Flash Address Upper Byte Register 101
Flash Column Select Register 109
Flash Control Register 102
Flash Control Registers 99
Flash controller 95, 96, 97, 98, 103, 105
clock 103
H
HALT 10, 252
HALT instruction 41
HALT Mode 1, 41, 42, 244, 252
HALT_SLP 10, 252, 259
HALT, Op-Code Map 279
handshake 172, 174, 214
hash table 310
Flash Data Register 100
Flash Frequency Divider Register 103
Flash Interrupt Control Register 105
Flash Key Register 99
I
I/O Chip Select Operation 65
I/O chip selects, external 26
I/O Read 96
Flash Memory 94
I/O space 6, 8, 62, 65
I2C acknowledge bit 224
I2C bus 209, 212, 213, 214
array 95, 107
Overview 95
PS027004-0613
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
360
clock 209
Interrupt Controller 54
protocol 210
interrupt enable 9
I2C Clock Control Register 228
I2C control bit 215, 216, 217
I2C Control Register 223
I2C Data Register 223
bit 156, 175, 223
flag 121, 252
interrupt input 11, 12, 13, 14, 15, 16, 196
interrupt priority 58, 59
levels 57
Registers 57
interrupt request 50, 55, 106, 123, 129, 130
signals 54
I2C Extended Slave Address Register 222
I2C Registers 220
I2C Software Reset Register 229
I2C Status Register 226
IC0 17, 122, 125, 130, 131, 135, 136, 137, 138, 148,
152
interrupt service routine 55, 56, 57
SPI 55
IC1 17, 122, 125, 130, 131, 135, 137, 148, 152
IC2 18, 122, 125, 130, 131, 135, 136, 137, 148, 152
IC3 18, 122, 125, 130, 131, 135, 137, 138, 148, 152
IEEE 1149.1 specification 258, 263
IEEE 802.3 310
interrupt sources 148
interrupt vector 54, 55
address 56, 57
bus 55
locations 55
frames 299
table 56
specification 300, 301
interrupt, higher-priority 59, 184
interrupt, highest-priority 54, 55
interrupts, edge-selectable 51
interrupts, level-sensitive 51
IORQ 8, 9, 65, 68, 69, 72, 73, 76
IORQ assertion delay 347, 348
IORQ deassertion delay 347, 348
IORQ hold time 348
IR_RXD 194, 196, 197
IR_TxD modulation signal 11, 194, 196
IrDA encoder/decoder (endec) 11, 43, 196
IrDA receive data 11
IrDA specifications 194
IrDA standard 193
IEEE 802.3, 802.3(u) minimum values 305
IEEE 802.3/4.2.3.2.1 Carrier Deference 306, 307
IEEE Standard 1149.1 256, 257
IEF1 56, 121, 252
IEF2 56
IFLG bit 209, 214, 217, 219, 220, 221, 224, 227
IM 0, Op Code Map 282
IM 1, Op Code Map 282
IM 2, Op Code Map 282
Information Page Characteristics 99
Infrared Encoder/Decoder 193
Register 197
Signal Pins 196
Input Capture 123
baud rates 193
INPUT CAPTURE Mode 122, 123, 126, 130
INSTRD 9
Instruction Store 4
IrDA transceiver 196
IrDA transmit data 11
IrDA—see Infrared Data Association 193
IRQ 55
0 Registers 248
Intel Bus Mode 71
irq_en 202, 205
Intel Bus Mode (Separate Address and Data Buses)
72
ISR 55
IVECT 54, 55, 56, 57
internal pull-up 48
internal RC oscillator 111, 114
internal system clock 66
interpacket gap 294, 304, 305, 306, 307
J
Jitter, Infrared Encoder/Decoder 196
PS027004-0613
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
361
JTAG Boundary Scan 258
JTAG interface 256, 263
JTAG mode selection 257
JTAG test mode 10
Master-Out, Slave-In 199
MAXF—see maximum frame length
maximum frame length 298, 308
MBIST 93
MBIST Control 93
MDC 24, 312
L
MDIO 24
Memory and I/O Chip Selects 62
Memory Built-In Self-Test controllers 93
Memory Chip Select Example 63
Memory Chip Select Operation 62
Memory Chip Select Priority 63
Memory Read 96
memory request 8
memory space 62, 65
Memory Write 98
Memory, EMAC 288
least-significant byte 55
level-sensitive interrupt modes 49
level-sensitive interrupts 51, 196
Level-Triggered Interrupts 50
line break detection 172
line status error 175
line status interrupt 174, 176, 178, 183
lock detect 265, 267
sensitivity 269
Lock Detect, PLL 267
MII 286, 291, 305, 311, 323, 324, 325, 326
MISO—see SPI Master In Slave Out 19, 199, 201
mode fault 206
loop filter 265, 267, 274
Loop Filter, PLL 13, 266
LOOP Mode 174
LOOP_FILT 258
Loopback Testing, Infrared Encoder/Decoder 196
low-byte vector 54
error flag 199
flag 202
SPI Flag 202
modem status 175, 176, 177, 184, 188, 191
interrupt 196
signal 12, 13, 15, 16
MODF 199, 202, 206
LSB 56, 57, 134, 228, 290, 303, 310
lsb 132, 134, 136, 137, 140, 153, 154, 214, 215,
216, 217, 219, 309, 313, 317, 319, 320, 325, 327,
328
Module Reset, UART 176
MOSI—see SPI Master Out Slave In 19, 199, 200,
201
Motorola Bus Mode 79
mpwm_en 142, 150
MREQ 8, 9, 63, 68, 69, 72, 73, 76
assertion delay 344, 345
deassertion delay 344
hold time 346
MSB 56, 134, 290
M
maskable interrupt 42, 54, 57, 59
Maskable Interrupts 54
mass erase operation 98, 99, 104, 106, 107, 109
MASTER Mode 200, 209, 219, 220, 224, 225, 226,
227, 228, 229
start bit 224
stop bit 224
msb 107, 133, 135, 137, 138, 141, 153, 154, 211,
236, 309, 317, 325, 327, 328, 329
Multibyte I/O Write (Row Programming) 97
multicast address 295, 310
multicast packet 310
SPI 201
Master Receive 217
MASTER RECEIVE Mode 209
Master Transmit 214
MASTER TRANSMIT Mode 209
master_en bit 202
multimaster conflict 202, 206
Multi-PWM Control Registers 149
Master-In, Slave-Out 199
PS027004-0613
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
362
MULTI-PWM Mode 141
overrun error 172, 174, 183, 190
MULTI-PWM POWER-TRIP Mode 148
MUX/CLK sync 265
MUX/CLK Sync, PLL 266
P
PA7 146
Packaging 353
page erase 98
N
NACK 212, 215, 216, 217, 218, 219, 224, 227
new instructions, eZ80 CPU core 37
NMI 9, 37, 42, 54, 111, 113, 114
NMI_flag bit 113
operation 98, 107, 109
PAIR_EN 149, 150
parity error 174, 186, 190
Part Number Description 355
nmi_out bit 113
PB0 17
nonmaskable interrupt 9, 37, 42, 54, 111, 113, 278
nonoverlapping delay, PWM 144, 147
Not Acknowledge 212
PB1 17
PB2 17
PB3 18
PB4 18
PB5 18
O
PB6 19
PB7 19
PC0 14, 20
PC1 14, 20
PC2 15, 20
PC3 15, 21
PC4 15, 21
PC5 16, 21
PC6 16, 22
PC7 16, 22
PD0 11, 196
PD1 11, 196
PD2 12, 196
PD3 12
PD4 12
PD5 13
OC0 20, 122, 125, 129, 131, 139, 140, 141
OC1 20, 122, 125, 129, 131
OC2 20, 122, 125, 129, 131
OC3 21, 122, 125, 129, 130, 140, 141
OCI Activation 257
OCI clock pin 257
OCI Interface 257
On-Chip Instrumentation 256
on-chip pull-up 337
on-chip RAM 62, 90, 91
Op Code Map 279
open source I/O 46
open source output 46
open-drain I/O 46, 48
open-drain mode 48
open-drain output 46, 209
open-source mode 48
PD6 13
PD7 13, 196
phase frequency detector 265
Phase Frequency Detector, PLL 266
Phase-Locked Loop 265
PHI 19, 260
open-source output 11, 12, 13, 14, 15, 16, 17, 18, 19
Operating Modes, I2C 214
Operation of the eZ80F91 Device during ZDI Break
Points 237
PHI clock output 44
PHY 22, 24, 27, 28, 291, 295, 312, 314, 324, 325
PHY, MII 287, 311
Pin Characteristics 6
Pin Coverage, JTAG Boundary Scan 258
Ordering Information 353
Output Compare 124
OUTPUT COMPARE Mode 123, 124, 126, 129,
139
overrun condition, receiver 175
PS027004-0613
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
363
Pin Description 4
PLL 265
Pulse-Width Modulation Control Register 3 152
Pulse-Width Modulation Falling Edge—High Byte
154
Characteristics 272
Control Register 0 269
Control Register 1 270
Pulse-Width Modulation Falling Edge—Low Byte
154
Divider Control Register—Low and High
Bytes 268
Pulse-Width Modulation Rising Edge—High Byte
153
loop filter 13
Normal Operation 267
Pulse-Width Modulation Rising Edge—Low Byte
153
Registers 268
PLL_VDD 268
PUSH, Op Code Map 279, 281, 283
PWM delay feature 147
PLL_VSS 268
Poll Mode Transfers 178
PWM edge transition values 144, 145
PWM generator 141, 142, 143, 144, 145, 149
PWM generators 142
PWM MASTER Mode 144
PWM Mode 117, 122, 126, 130
PWM Mode, MULTI- 141, 142, 145, 150
PWM Mode, MULTI- 144
PWM nonoverlapping delay 144
time 147
PWM Nonoverlapping Output Pair Delays 146
PWM output pairs 144
PWM outputs 145, 146, 148
PWM Outputs, AND/OR Gating 144, 145
PWM outputs, inverted 143
PWM pairs 145
POP, Op Code Map 279, 281, 283
POR Voltage Threshold 339
POR voltage threshold 39
POR/VBO analog RESET duration 339
POR/VBO DC current consumption 339
POR/VBO Hysteresis 339
Port A 20, 21, 43, 45, 55, 59, 60, 141
Port x Alternate Register 1 52
Port x Alternate Register 2 53
Port x Data Direction Registers 52
Port x Data Registers 51
Potential Hazards of Enabling Bus Requests During
DEBUG Mode 238
power connections 2
Power Requirement to the Phase-Locked Loop
Function 268
PWM power-trip state 148
PWM signals 141
PWM trip levels 152
Power-On Reset 38, 39, 339
power-trip 149
PWM waveform 145
PWM0 146
POWER-TRIP Mode, MULTI-PWM 148
POWER-TRIP, MULTI-PWM 148
Primary Crystal Oscillator Operation 332
Program Counter 254
PWM1 20, 21, 122, 125, 143, 145
PWM1 falling edge end-of-count 144, 147
PWM1 rising edge end-of-count 144, 147
PWM1FH 144
program counter 38, 41, 42, 56, 94, 249, 250
program counter, starting 57
Programmable Reload Timers 117
Programming Flash Memory 96
PROMISCUOUS Mode 310
PT_EN 149
PWM1RH 153, 154
PWM1RL 153, 154
PWM2 20, 22, 122, 125, 143
PWM2 falling edge end-of-count 144
PWM2 rising edge end-of-count 144
PWM2RH 144
pull-up resistor, external 48, 209
Pulse-Width Modulation Control Register 1 149
Pulse-Width Modulation Control Register 2 150
PWM3 21, 22, 122, 143
pwm3_en 149
PWMCNTRL1 142
PS027004-0613
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
364
PWMCNTRL2 144
PWMCNTRL3 148
Recommended Usage of the Baud Rate Generator
179
Register Set for Capture in Timer 1 126
Register Set for Capture/Compare/PWM in Timer 3
126
Q
request to send 12, 15, 188
RESET 9, 38, 39, 41, 42, 48, 62, 90, 91, 102, 104,
111, 112, 113, 157, 160, 161, 162, 163, 164, 165,
166, 167, 168, 169, 170, 178, 179, 197, 203, 204,
243, 244, 257, 259, 339
reset controller 38, 39
RESET event 38, 45
RESET Mode timer 38, 39
RESET Or NMI Generation 113
Reset States 63
QMC 310
qualified multicast messages 310
R
RAM 90
Address Upper Byte Register 92
Control Register 91
Random Access Memory 90
RD 8, 63, 65, 68, 72, 73, 76
RESET_OUT 259
assertion delay 344, 347
deassertion delay 344, 347
Resetting the I2C Registers 221
RI 174, 188, 191
Reading Flash Memory 95
Reading the Current Count Value 118
Real-Time Clock 155
real-time clock 38, 41, 156, 157, 169
Real-Time Clock Alarm41, 156
Control Register 169
RI0 13, 196
RI1 16, 49
ring indicator 13, 16, 191
rising edge 143, 144, 146, 151
rst_flag bit 113
RTC Oscillator Input 123
RTC supply voltage 338
RTC_VDD 10
RTC_XIN 10
RTC_XOUT 10
RTS 188, 191, 196
RTS0 12
RTS1 15
RX_CLK 24
Rx_CLK 23
Rx_DV 24
Rx_ER 23
RxD0 11, 24
RxD1 14, 24
RxD2 24
Day-of-the-Week Register 168
Hours Register 167
Minutes Register 166
Seconds Register 165
Real-Time Clock Battery Backup 156
Real-Time Clock Century Register 164
Real-Time Clock Control Register 170
Real-Time Clock Day-of-the-Month Register 161
Real-Time Clock Day-of-the-Week Register 160
Real-Time Clock Hours Register 159
Real-Time Clock Minutes Register 158
Real-Time Clock Month Register 162
Real-Time Clock Oscillator and Source Selection
156
Real-Time Clock Recommended Operation 156
Real-Time Clock Registers 157
Real-Time Clock Seconds Register 157
real-time clock signal 123
RxD3 24
RxDMA 290
real-time clock source 111, 114, 121
Real-Time Clock Year Register 163
Receive, Infrared Encoder/Decoder 194
S
Schmitt Trigger input 9, 11, 14, 15, 17, 18, 24
PS027004-0613
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
365
buffers 45
SPI data rate 203
SCK 18, 199, 200
SPI Flags 202
idle state 200
pin 201, 205
receive edge 200
signal 201
SPI interrupt service routine 55
SPI master device 19, 203
SPI MASTER Mode 201
SPI Mode 17
transmit edge 200
SCL 19, 209, 210, 211, 228
line 212, 214
SPI Receive Buffer Register 208
SPI Registers 203
SPI serial bus 207
SCLK 38, 146, 265, 266, 267, 312
periods 151
SPI serial clock 18
SPI Signals 199
SDA 19, 209, 210, 211, 220
line 213
SPI slave device 19
SPI SLAVE Mode 201
see system reset 8
SPI Status Register 202, 206
SPI Transmit Shift Register 202, 203, 207
SPIF status bit—see serial peripheral interface flag
207
serial bus, SPI 207, 208
serial clock 209
I2C 19
SPI 18, 199, 200
SPIF—see serial peripheral interface flag 201, 206
SRA 278
serial data 199, 209
I2C 19
Op Code Map 280, 284
Serial Peripheral Interface 1
serial peripheral interface 43, 55, 59, 198, 199, 201
flag 207, 208
SRAM 1, 101, 230, 327, 354
internal Ethernet 292
SS—see Slave Select 17, 199, 200, 201, 203, 205
STA 224
Functional Description 201
Setting Timer Duration 118
SINGLE PASS Mode 117, 119, 120, 128
Single-Byte I/O Write 96
SLA 216, 217, 222, 278
Op Code Map 280, 284, 285
SLAVE Mode 209, 219, 221, 222, 224, 227
SPI 201
STANDARD Mode 209
Standard VHDL Package STD_1149_1_2001 259
Start and Stop Conditions 210
start condition 212, 226
starting program counter 56, 57
stop condition 220, 224, 225
supply voltage 2, 39, 48, 209, 267, 336, 337
Switching Between Bus Modes 82
system clock 38, 41, 42, 43, 44, 49, 50, 111, 114,
121, 123, 128, 146, 178, 202, 228, 229, 237, 257,
266, 289, 351
Slave Receive 219
SLAVE RECEIVE Mode 209
Slave Select 199
Slave Transmit 219
SLAVE TRANSMIT Mode 209, 219, 224
SLEEP Mode 1, 41, 170, 244, 252
sleep-mode recovery 170
reset 171
cycle 73, 76, 118
cycle time 343
cycles 9, 65, 68, 69, 73, 76, 80, 112, 257
divider 128
software break point instruction 256
Specialty Timer Modes 122
SPI Baud Rate Generator 202
Registers—Low Byte and High Byte 204
SPI Control Register 205
fall time 343
frequency 97, 98, 102, 103, 118, 178, 203, 231
high-frequency 202
internal 66
high time 343
PS027004-0613
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
366
jitter 123
low time 343
oscillator input 14
oscillator output 13
period 257
Timer Output Compare Control Register 1 138
Timer Output Compare Control Register 2 139
Timer Output Compare Value Register—High Byte
141
Timer Output Compare Value Register—Low Byte
140
periods 147
rise time 343
Timer Port Pin Allocation 124
Timer Registers 125
Timer Reload Register—High Byte 134
Timer Reload Register—Low Byte 134
TMS 257, 258
rising edge 178, 202
system clock source 269, 270
system reset 38, 156, 158, 159, 181, 267, 296
TOUT0 21, 125
T
TOUT1 21, 125
trace buffer memory 256
trace history buffer 256
Transferring Data 211
transmit shift register 173, 183, 186, 189
SPI 201, 202, 203, 207
Transmit, Infrared Encoder/Decoder 194
trigger-level detection logic 173
TRIGOUT 257, 259
tristate 148
TRSTN 257, 258
Tx_CLK 23
Tx_EN 23
Tx_ER 23
TxD0 11, 23
TxD1 14, 23
TxD2 23
TxD3 22
TxDMA 289
T2 clock 147
T2 end-of-count 147
T23CLKCN 147
TAP 263
TAP reset 257
TCK 232, 257, 258, 263
TDI 257, 258, 259
TDO 257, 258, 259
TERI 191
test access port 256
instruction 263
state register 257
test mode select 257
Time-Out Period Selection 112
Timer Control Register 128
Timer Data Register—High Byte 133
Timer Data Register—Low Byte 131
Timer Input Capture Control Register 135
Timer Input Capture Value A Register—High Byte
137
Timer Input Capture Value A Register—Low Byte
136
Timer Input Capture Value B Register—High Byte
138
U
UART Baud Rate Generator Register—Low and
High Bytes 179
UART FIFO Control Register 185
UART Functional Description 173
UART Functions 173
Timer Input Capture Value B Register—Low Byte
137
Timer Input Source Selection 121
Timer Interrupt Enable Register 129
Timer Interrupt Identification Register 130
Timer Interrupts 120
UART Interrupt Enable Register 182
UART Interrupt Identification Register 183
UART Interrupts 175
UART Line Control Register 186
UART Line Status Register 189
Timer Output 121
PS027004-0613
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
367
UART Modem Control 174
Watchdog Timer 1, 41, 111, 112, 237
Control Register 113
Operation 112
Register 188
UART Modem Status Interrupt 176
UART Modem Status Register 191
UART Receive Buffer Register 182
UART Receiver 174
Registers 113
Reset Register 116
time-out 38, 41, 42
UART Receiver Interrupts 175
UART Recommended Usage 176
UART Registers 181
UART Scratch Pad Register 192
UART Transmit Holding Register 181
UART Transmitter 173
UART Transmitter Interrupt 175
Universal Asynchronous Receiver/Transmitter 172
Usage, JTAG Boundary Scan 263
WCOL—see write collision 201, 202, 206
WDT 38, 41, 111, 112, 113
clock source 111, 112, 114
oscillator 113
time-out 111, 113, 114, 116
time-out period 112, 115
WP 24
WP pin 94, 104, 105, 106
WR 8, 63, 65, 69, 73, 76
WR assertion delay 346, 348
write collision 201, 202
SPI 206
V
VBO 38, 39, 339
pulse reject period 339
Voltage Threshold 339
VCC 2, 39, 339
X
XIN input pin 332
ramp rate 339
XOUT output pin 332
VCO 266, 273
VLAN tagged frame 308
Voltage Brown-Out 339
Reset 39
Z
Z80 BUS Mode 68
voltage signal, high 97
voltage, input 266
ZCL 232, 235, 243
ZDA 232, 243, 257
voltage, peak-to-peak 273
voltage, supply 2, 48, 209, 267, 336, 337
voltage-controlled oscillator 265
PLL 266
ZDI 230, 231, 256
Address Match Registers 241
Block Read 237
Block Write 235
Break Control Register 242
Bus Control Register 248
Bus Status Register 254
Clock and Data Conventions 232
clock pin 232
W
wait 1, 9, 80
wait condition 109
WAIT Input Signal 66
data pin 232
wait pin, external 68, 69
debug control 256
wait state 69, 76, 349, 350
Wait State Timing for Read Operations 349
Wait State Timing for Write Operations 350
wait states 55, 65, 73, 76, 85, 238
Master Control Register 244
Read Memory Register 254
Read Operations 236
Read Register Low, High, and Upper 253
PS027004-0613
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
368
Read/Write Control Register 245
Read-Only Registers 240
Register Addressing 234
Register Definitions 240
Single-Bit Byte Separator 233
Single-Byte Read 236
Write Memory Register 249
Write Only Registers 239
Write Operations 235
ZDI_BUS_STAT 238, 240, 254
ZDI_BUSACK_EN 238, 254
ZDI_BUSACK_En 254
Single-Byte Write 235
Start Condition 232
ZDI-Supported Protocol 231
ZDS II 230
Status Register 252
Write Data Registers 245
Zilog Debug Interface 230, 256
Zilog Developer Studio II 230
PS027004-0613
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
369
PS027004-0613
P R E L I M I N A R Y
Index
eZ80F91 ASSP
Product Specification
370
Customer Support
To share comments, get your technical questions answered, or report issues you may be
experiencing with our products, please visit Zilog’s Technical Support page at
http://support.zilog.com.
To learn more about this product, find additional documentation, or to discover other fac-
ets about Zilog product offerings, please visit the Zilog Knowledge Base or consider par-
ticipating in the Zilog Forum.
This publication is subject to replacement by a later edition. To determine whether a later
edition exists, please visit the Zilog website at http://www.zilog.com.
PS027004-0613
P R E L I M I N A R Y
Customer Support
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