Z16FMC32AG20SG [ZILOG]
IC 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP64, LEAD FREE, LQFP-64, Microcontroller;
| 型号： | Z16FMC32AG20SG |
| 厂家： | 
ZILOG, INC. |
| 描述： | IC 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP64, LEAD FREE, LQFP-64, Microcontroller 时钟 微控制器 外围集成电路 |
| 文件： | 总353页 (文件大小：1534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Motor Control MCUs
Z16FMC Series
Product Specification
PS028706-1013
P R E L I M I N A R Y
®
Copyright ©2013 Zilog Inc. All rights reserved.
www.zilog.com
Z16FMC Series Motor Control MCUs
Product Specification
ii
DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
Warning:
LIFE SUPPORT POLICY
ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti-
cal component is any component in a life support device or system whose failure to perform can be reason-
ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2013 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
Z8, Z8 Encore!, ZNEO and Z16FMC are trademarks or registered trademarks of Zilog, Inc. All other prod-
uct or service names are the property of their respective owners.
PS028706-1013
P R E L I M I N A R Y
Disclaimer
Z16FMC Series Motor Control MCUs
Product Specification
iii
Revision History
Each instance in the following revision history table reflects a change to this document
from its previous version. For more details, refer to the corresponding pages provided in
the table.
Revision
Date Level
Description
Page
Aug.
2013
06
05
04
Added the Peripheral Address Map and the Flash Frequency Register sec- 17, 259
tion.
Jun
2013
Updated the Analog Functions Block Diagram.
215
Jan
2013
Corrected the following issues per CR #13234:
• Corrected Figure 2, pin 47 from “FAULTY” to “FAULT1”
7, 8, 60,
84, 101,
• Corrected Table 1, V
to 1µF
description to change 10µF capacitance figure 103, 103,
104, 105
REF
• Modified language in Interrupt Request 0 Register section, 2nd para-
graph
• Modified language in Table 50, INCAP bit
• Modified language in Table 59, INDEN bit
• Modified language in PWM Fault Mask Register section, 2nd paragraph.
• Corrected RESET value, bits 4 and 3, Table 62
• Correct order of bits in Table 63
• Correct order of bits in Table 64
Jun
2011
03
02
Corrected V
value in Comparator Electrical Characteristics table.
313
COFF
Dec
2010
Minor corrections to the Zilog Part Numbers table and to the Part Number 323, 324
Suffix Designations map.
Nov 01
Original issue.
N/A
2010
PS028706-1013
P R E L I M I N A R Y
Revision History
Z16FMC Series Motor Control MCUs
Product Specification
iv
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiv
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
ZNEO CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Flash Z16FMC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Motor Control Peripherals Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
10-Bit Analog-to-Digital Converter with Programmable Gain Amplifier . . . . . . 3
Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Infrared Encoder/Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Inter-Integrated Circuit Master/Slave Controller . . . . . . . . . . . . . . . . . . . . . . . . . 4
Enhanced Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pulse Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Standard Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signal and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Internal Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Internal RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input/Output Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PS028706-0813
P R E L I M I N A R Y
Table of Contents
Z16FMC Series Motor Control MCUs
Product Specification
v
Input/Output Memory Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ZNEO CPU Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Peripheral Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reset and Stop-Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
External Reset Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
User Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Fault Detect Logic Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Stop-Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Stop-Mode Recovery Using WDT time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Stop-Mode Recovery Using a GPIO Port Pin Transition . . . . . . . . . . . . . . . . . . 38
Reset Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Peripheral-Level Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Power Control Option Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
GPIO Port Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Port A–H Input Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Port A–H Output Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Port A–H Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port A–H High Drive Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port A–H Alternate Function High and Low Registers . . . . . . . . . . . . . . . . . . . 48
Port A–H Output Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port A–H Pull-Up Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PS028706-0813
P R E L I M I N A R Y
Table of Contents
Z16FMC Series Motor Control MCUs
Product Specification
vi
Port A–H Stop-Mode Recovery Source Enable Registers . . . . . . . . . . . . . . . . . 51
Port A IRQ MUX1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Port A IRQ MUX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Port A IRQ Edge Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Port C IRQ MUX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
System Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
System Exception Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Last IRQ Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Reading Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Timer 0–2 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Timer X Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . 82
Timer 0–2 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . 83
Timer 0–2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Multi-Channel PWM Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
PWM Option Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
PWM Reload Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PWM Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PWM Period and Count Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PWM Duty Cycle Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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Table of Contents
Z16FMC Series Motor Control MCUs
Product Specification
vii
Independent and Complementary PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . 93
Manual Off-state Control of PWM Output Channels . . . . . . . . . . . . . . . . . . . . 93
Deadband Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Minimum PWM Pulse Width Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Synchronization of PWM and ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Synchronized Current-Sense Sample and Hold . . . . . . . . . . . . . . . . . . . . . . . . . 94
PWM Timer and Fault Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Fault Detection and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
PWM Operation in CPU HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
PWM Operation in CPU STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Observing the State of PWM Output Channels . . . . . . . . . . . . . . . . . . . . . . . . . 96
PWM Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
PWM Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
PWM 0–2 Duty Cycle High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . 98
PWM Control 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
PWM Control 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
PWM Deadband Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
PWM Minimum Pulse Width Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
PWM Fault Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
PWM Fault Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
PWM Fault Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
PWM Input Sample Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PWM Output Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Current-Sense Sample and Hold Control Registers . . . . . . . . . . . . . . . . . . . . . 107
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Watchdog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Watchdog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Watchdog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Watchdog Timer Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Watchdog Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . 112
LIN-UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Data Format for Standard UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Transmitting Data Using Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . 116
Receiving Data Using Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . 118
Clear To Send Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
LIN-UART Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
MULTIPROCESSOR (9-Bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
LIN Protocol Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
LIN-UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
LIN-UART DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
LIN-UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Noise Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
LIN-UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
LIN-UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
LIN-UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
LIN-UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
LIN-UART Mode Select and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 136
LIN-UART Control 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
LIN-UART Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
LIN-UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
LIN-UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . 145
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . . . . . . . 152
Enhanced Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
ESPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Master-In/Slave-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Master-Out/Slave-In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
ESPI Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Comparison with Basic SPI Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
ESPI Clock Phase and Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
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Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SPI Protocol Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
ESPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
ESPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
ESPI Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
ESPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
ESPI Transmit Data Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
ESPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
ESPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
ESPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
ESPI State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
ESPI Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . 178
I2C Master/Slave Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
I2C Master/Slave Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Comparison with MASTER ONLY Mode I2C Controller . . . . . . . . . . . . . . . . 182
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
SDA and SCL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
I2C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Software Control of I2C Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Master Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Slave Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
DMA Control of I2C Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
I2C Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
I2C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
I2C Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
I2C Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . 208
I2C State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
I2C Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
I2C Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Analog Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
ADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
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ADC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
ADC0 Timer0 Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
ADC Convert on Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Reference Buffer, RBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Internal Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
ADC0 Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
ADC0 Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
ADC0 Data Low Bit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Sample Settling Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Sample Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
ADC Clock Prescale Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
ADC0 Max Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
ADC Timer0 Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Comparator and Operational Amplifier Overview . . . . . . . . . . . . . . . . . . . . . . . . . 224
Comparator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Operational Amplifier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Comparator Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Comparator and Operational Amplifier Control Register . . . . . . . . . . . . . . . . 226
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
DMA Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
DMA Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
DMA Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
DMA Control Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
DMA Watermark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
DMA Peripheral Interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Buffer Closure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
DMA Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
LINKED LIST Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
DMA Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
DMA Request Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
DMA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
DMA X Transfer Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
DMA Destination Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
DMA Source Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
DMA List Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
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Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Timing Using the Flash Frequency Register . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Flash Read Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Flash Write/Erase Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Flash Controller Behavior Using the On-Chip Debugger . . . . . . . . . . . . . . . . 255
Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Flash Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Flash Frequency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Option Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Program Memory Address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Program Memory Address 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Program Memory Address 0002h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Program Memory Address 0003h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
IPO Trim Registers (Information Area Address 0021h and 0022h) . . . . . . . . 264
ADC Reference Voltage Trim (Information Area Address 0023h) . . . . . . . . . 265
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
On-Chip Debug Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Auto-Baud Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Line Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
9-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Start Bit Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
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Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Initialization During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Debug Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Error Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
DEBUG HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Reading and Writing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Reading Memory CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Instruction Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Memory Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
DBG pin used as a GPIO pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Baud Rate Reload Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Line Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Debug Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Hardware Breakpoint Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Trace Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Trace Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Oscillator Operation with an External RC Network . . . . . . . . . . . . . . . . . . . . . . . . 295
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
System Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Clock Selection Following System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Clock Failure Detection and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
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Oscillator Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Oscillator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Oscillator Divide Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . 310
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
General Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . . . . 315
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
SPI MASTER Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
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List of Figures
Figure 1. Z16FMC Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Z16FMC in the 64-Pin Low-Profile Quad Flat Package (LQFP) . . . . . . . . . 7
Figure 3. Physical Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. Endianness of Words and Quads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. Alignment of Word and Quad Operations on 16-Bit Memories . . . . . . . . . 16
Figure 6. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 7. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 8. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 9. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 10. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 11. PWM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 12. Edge-Aligned PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 13. Center-Aligned PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 14. LIN-UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 15. LIN-UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . 115
Figure 16. LIN-UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . 115
Figure 17. LIN-UART Driver Enable Signal Timing (shown with 1 Stop Bit
and Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 18. LIN-UART Asynchronous MULTIPROCESSOR Mode Data Format . . 121
Figure 19. LIN-UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . 128
Figure 20. Noise Filter System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 21. Noise Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 22. Infrared Data Communication System Block Diagram . . . . . . . . . . . . . . 149
Figure 23. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 24. Infrared Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 25. ESPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 26. ESPI Timing when PHASE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 27. ESPI Timing when PHASE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 28. SPI Mode (SSMD = 000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 29. I2S Mode (SSMD = 010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 30. ESPI Configured as an SPI Master in a Single Master, Single Slave
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
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Figure 31. ESPI Configured as an SPI Master in a Single Master, Multiple Slave
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 32. ESPI Configured as an SPI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 33. I2C Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 34. Data Transfer Format: Master Write Transaction with a 7-Bit Address . . 188
Figure 35. Data Transfer Format: Master Write Transaction with 10-Bit Address . . 189
Figure 36. Data Transfer Format: Master Read Transaction with 7-Bit Address . . . . 191
Figure 37. Data Transfer Format: Master Read Transaction with 10-Bit Address . . . 192
Figure 38. Data Transfer Format: Slave Receive Transaction with 7-Bit Address . . . 196
Figure 39. Data Transfer Format: Slave Receive Transaction with 10-Bit Address . . 197
Figure 40. Data Transfer Format: Slave Transmit Transaction with 7-Bit Address . . 198
Figure 41. Data Transfer Format: Slave Transmit Transaction with 10-Bit Address . 199
Figure 42. Analog Functions Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 43. ADC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 44. ADC Convert Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 45. DMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 46. DMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 47. Direct DMA Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 48. Linked List Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 49. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 50. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 51. Interfacing the Serial Pin with an RS-232 Interface, #1 of 2 . . . . . . . . . . . 268
Figure 52. Interfacing the Serial Pin with an RS-232 Interface, #2 of 2 . . . . . . . . . . . 268
Figure 53. OCD Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Figure 54. Output Driver when Drive High and Open Drain Enabled . . . . . . . . . . . . 271
Figure 55. 9-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 56. Start Bit Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 57. Initialization During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 58. Recommended 20MHz Crystal Oscillator Configuration . . . . . . . . . . . . . 295
Figure 59. Connecting the On-Chip Oscillator to an External RC Network . . . . . . . . 296
Figure 60. Typical RC Oscillator Frequency as a Function of External Capacitance 297
Figure 61. Typical Idd Versus System Clock Frequency . . . . . . . . . . . . . . . . . . . . . . 307
Figure 62. Typical HALT Mode Idd Versus System Clock Frequency . . . . . . . . . . . 308
Figure 63. Stop Mode Current Versus Vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 64. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Figure 65. SPI MASTER Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
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Figure 66. SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 67. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Figure 68. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Figure 69. UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
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List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Characteristics of the Z16FMC Series MCU . . . . . . . . . . . . . . . . . . . . 11
Reserved Memory Map Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ZNEO CPU Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reset and Stop-Mode Recovery Characteristics and Latency . . . . . . . . . . . 33
System Reset Sources and Resulting Reset Action . . . . . . . . . . . . . . . . . . . 34
Stop-Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . . 38
Reset Status and Control Register (RSTSCR) . . . . . . . . . . . . . . . . . . . . . . . 39
Table 10. Reset Status Register Values Following Reset . . . . . . . . . . . . . . . . . . . . . . 39
Table 11. GPIO Port Availability by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 12. Port Alternate Function Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 13. Port A–H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 14. Port A–H Output Data Registers (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 15. Port A–H Data Direction Registers (PxDD) . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 16. Port A–H High Drive Enable Registers (PxHDE) . . . . . . . . . . . . . . . . . . . . 47
Table 17. Port A–H Alternate Function High Registers (PxAFH) . . . . . . . . . . . . . . . 48
Table 18. Port A–H Alternate Function Low Registers (PxAFL) . . . . . . . . . . . . . . . . 48
Table 19. Alternate Function Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 20. Port A–H Output Control Registers (PxOC) . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 21. Port A–H Pull-Up Enable Registers (PxPUE) . . . . . . . . . . . . . . . . . . . . . . . 50
Table 22. Port A–H Stop-Mode Recovery Source Enable Registers (PxSMRE) . . . . 51
Table 23. Port A IRQ MUX1 Register (PAIMUX1) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 24. Port A IRQ MUX Register (PAIMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 25. Port A IRQ Edge Register (PAIEDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 26. Port C IRQ MUX Register (PCIMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 27. Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 28. Interrupt Vector placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 29. System Exception Register High (SYSEXCPH) . . . . . . . . . . . . . . . . . . . . . 59
Table 30. System Exception Register Low (SYSEXCPL) . . . . . . . . . . . . . . . . . . . . . 59
Table 31. Last IRQ Register (LASTIRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 32. Interrupt Request 0 Register (IRQ0) and Interrupt Request 0 Set Register
(IRQ0SET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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List of Tables
Z16FMC Series Motor Control MCUs
Product Specification
xviii
Table 33. Interrupt Request 1 Register (IRQ1) and Interrupt Request 1 Set Register
(IRQ1SET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 34. Interrupt Request 2 Register (IRQ2) and Interrupt Request 2 Set Register
(IRQ2SET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 35. IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 36. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . . 65
Table 37. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 38. IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 39. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . . 66
Table 40. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 41. IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 42. IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . . . . 67
Table 43. IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 44. Timer 0–2 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 45. Timer 0–2 Low Byte Register (TXL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 46. Timer 0–2 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . . . . . 82
Table 47. Timer 0–2 Reload Low Byte Register (TxRL) . . . . . . . . . . . . . . . . . . . . . . 82
Table 48. Timer 0–2 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . . . . 83
Table 49. Timer 0–2 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . . . . 83
Table 50. Timer 0–2 Control 0 Register (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 51. Timer 0–2 Control 1 Register (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 52. PWM High Byte Register (PWMH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 53. PWM Low Byte Register (PWML) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 54. PWM Reload High Byte Register (PWMRH) . . . . . . . . . . . . . . . . . . . . . . . 97
Table 55. PWM Reload Low Byte Register (PWMRL) . . . . . . . . . . . . . . . . . . . . . . . 98
Table 56. PWM 0–2 H/L Duty Cycle High Byte Register
(PWMHxDH, PWMLxDH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 57. PWM 0–2 H/L Duty Cycle Low Byte Register
(PWMHxDL, PWMLxDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 58. PWM Control 0 Register (PWMCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 59. PWM Control 1 Register (PWMCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 60. PWM Deadband Register (PWMDB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 61. PWM Minimum Pulse Width Filter (PWMMPF) . . . . . . . . . . . . . . . . . . . 103
Table 62. PWM Fault Mask Register (PWMFM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 63. PWM Fault Status Register (PWMFSTAT) . . . . . . . . . . . . . . . . . . . . . . . 104
Table 64. PWM Fault Control Register (PWMFCTL) . . . . . . . . . . . . . . . . . . . . . . . 105
Table 65. PWM Input Sample Register (PWMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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P R E L I M I N A R Y
List of Tables
Z16FMC Series Motor Control MCUs
Product Specification
xix
Table 66. PWM Output Control Register (PWMOUT) . . . . . . . . . . . . . . . . . . . . . . . 107
Table 67. Current-Sense Sample and Hold Control Register (CSSHR0
and CSSHR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 68. Watchdog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . . . . . 110
Table 69. Watchdog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . . . . 112
Table 70. Watchdog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . . 112
Table 71. LIN-UART Transmit Data Register (UxTXD) . . . . . . . . . . . . . . . . . . . . . 133
Table 72. LIN-UART Receive Data Register (UxRXD) . . . . . . . . . . . . . . . . . . . . . . 133
Table 73. LIN-UART Status 0 Register, Standard UART Mode (UxSTAT0) . . . . . 134
Table 74. LIN-UART Status 0 Register, LIN Mode (UxSTAT0) . . . . . . . . . . . . . . . 135
Table 75. LIN-UART Mode Select and Status Register (UxMDSTAT) . . . . . . . . . . 137
Table 76. MULTIPROCESSOR Mode Status Field (MSEL = 000b) . . . . . . . . . . . . 138
Table 77. Digital Noise Filter Mode Status Field (MSEL = 001B) . . . . . . . . . . . . . . 138
Table 78. LIN Mode Status Field (MSEL = 010b) . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 79. Hardware Revision Mode Status Field (MSEL = 111B) . . . . . . . . . . . . . . 139
Table 80. LIN-UART Control 0 Register (UxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 81. Multiprocessor Control Register (UxCTL1 with MSEL = 000b) . . . . . . . 141
Table 82. Noise Filter Control Register (UxCTL1 with MSEL = 001b) . . . . . . . . . . 142
Table 83. LIN Control Register (UxCTL1 with MSEL = 010b) . . . . . . . . . . . . . . . . 143
Table 84. LIN-UART Address Compare Register (UxADDR) . . . . . . . . . . . . . . . . . 144
Table 85. LIN-UART Baud Rate High Byte Register (UxBRH) . . . . . . . . . . . . . . . 145
Table 86. LIN-UART Baud Rate Low Byte Register (UxBRL) . . . . . . . . . . . . . . . . 145
Table 87. LIN-UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 88. ESPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 89. ESPI Clock Phase and Clock Polarity Operation . . . . . . . . . . . . . . . . . . . 158
Table 90. ESPI Tx DMA Descriptor Command Field . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 91. ESPI Tx DMA Descriptor Status field . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 92. ESPI Rx DMA Descriptor Status field . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 93. ESPI Data Register (ESPIDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 94. ESPI Transmit Data Command Register (ESPITDCR) . . . . . . . . . . . . . . . 171
Table 95. ESPI Control Register (ESPICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 96. ESPI Mode Register (ESPIMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 97. ESPI Status Register (ESPISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 98. ESPI State Register (ESPISTATE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 99. ESPISTATE Values and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 100. ESPI Baud Rate High Byte Register (ESPIBRH) . . . . . . . . . . . . . . . . . . . 178
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P R E L I M I N A R Y
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Z16FMC Series Motor Control MCUs
Product Specification
xx
Table 101. ESPI Baud Rate Low Byte Register (ESPIBRL) . . . . . . . . . . . . . . . . . . . . 179
Table 102. I2C Master/Slave Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 103. I2C Data Register (I2CDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 104. I2C Interrupt Status Register (I2CISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 105. I2C Control Register (I2CCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 106. I2C Baud Rate High Byte Register (I2CBRH) . . . . . . . . . . . . . . . . . . . . . 208
Table 107. I2C Baud Rate Low Byte Register (I2CBRL) . . . . . . . . . . . . . . . . . . . . . . 208
Table 108. I2C State Register (I2CSTATE), Description when DIAG = 0 . . . . . . . . . 209
Table 109. I2C State Register (I2CSTATE), Description when DIAG = 1 . . . . . . . . . 210
Table 110. I2CSTATE_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 111. I2CSTATE_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 112. I2C Mode Register (I2CMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 113. I2C Slave Address Register (I2CSLVAD) . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 114. ADC0 Control Register 0 (ADC0CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 115. ADC0 Data High Byte Register (ADC0D_H) . . . . . . . . . . . . . . . . . . . . . . 220
Table 116. ADC0 Data Low Bit Register (ADC0D_L) . . . . . . . . . . . . . . . . . . . . . . . 221
Table 117. Sample and Settling Time (ADCSST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 118. Sample Time (ADCST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 119. ADC Clock Prescale Register (ADCCP) . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 120. ADC0 Max Register (ADC0MAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 121. ADC Timer0 Capture Register, High Byte (ADCTCAP_H) . . . . . . . . . . 224
Table 122. ADC Timer0 Capture Register, Low Byte (ADCTCAP_L) . . . . . . . . . . . 224
Table 123. Comparator and Op Amp Control Register (CMPOPC) . . . . . . . . . . . . . . 226
Table 124. Linked List Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 125. DMA Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 126. DMA Bandwidth Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 127. DMA Request Select Register (DMAxREQSEL) . . . . . . . . . . . . . . . . . . . 242
Table 128. DMA Control Register A (DMAxCTL)) . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 129. DMA X Transfer Length High Register (DMAxTXLNH) . . . . . . . . . . . . 246
Table 130. DMA X Transfer Length Low Register (DMAxTXLNL) . . . . . . . . . . . . . 246
Table 131. DMA Destination Address Register Upper (DMAxDARU) . . . . . . . . . . . 247
Table 132. DMA Destination Address Register High (DMAxDARH) . . . . . . . . . . . . 247
Table 133. DMA Destination Address Register Low (DMAxDARL) . . . . . . . . . . . . 247
Table 134. DMA X Source Address Register Upper (DMAxSARU) . . . . . . . . . . . . . 248
Table 135. DMA X Source Address Register High (DMAxSARH) . . . . . . . . . . . . . . 248
Table 136. DMA X Source Address Register Low (DMAxSARL) . . . . . . . . . . . . . . 248
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List of Tables
Z16FMC Series Motor Control MCUs
Product Specification
xxi
Table 137. DMA X List Address Register Upper (DMAxLARU) . . . . . . . . . . . . . . . 249
Table 138. DMA X List Address Register High (DMAxLARH) . . . . . . . . . . . . . . . . 249
Table 139. DMA X List Address Register Low (DMAxLARL) . . . . . . . . . . . . . . . . . 249
Table 140. Flash Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 141. Flash Memory Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 142. Information Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 143. Flash Command Register (FCMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 144. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 145. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 146. Flash Sector Protect Register (FSECT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 147. Flash Page Select Register (FPAGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 148. Flash Frequency Register (FFREQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 149. Option Bit At Program Memory Address 0000h . . . . . . . . . . . . . . . . . . . . 261
Table 150. Options Bit at Program Memory Address 0001h . . . . . . . . . . . . . . . . . . . 262
Table 151. Options Bit at Program Memory Address 0002h . . . . . . . . . . . . . . . . . . . 263
Table 152. Options Bit at Program Memory Address 0003h . . . . . . . . . . . . . . . . . . . 263
Table 153. IPO Trim 1 (IPOTRIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 154. IPO Trim 2 (IPOTRIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 155. ADC Reference Voltage Trim (ADCTRIM) . . . . . . . . . . . . . . . . . . . . . . . 265
Table 156. OCD Baud Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Table 157. On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 158. Receive Data Register (DBGRXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 159. Transmit Data Register (DBGTXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Table 160. Baud Rate Reload Register (DBGBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Table 161. Line Control Register (DBGLCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Table 162. Status Register (DBGSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 163. Debug Control Register (DBGCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Table 164. OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 165. OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Table 166. Hardware Breakpoint Register (HWBPn) . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 167. Trace Control Register (TRACECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 168. Trace Address (TRACEADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 169. Recommended Crystal Oscillator Specifications (20 MHz Operation) . . . 295
Table 170. Oscillator Configuration and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Table 171. Oscillator Control Register (OSCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 172. Oscillator Divide Register (OSCDIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
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List of Tables
Z16FMC Series Motor Control MCUs
Product Specification
xxii
Table 173. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 174. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Table 175. POR and VBO Electrical Characteristics and Timing . . . . . . . . . . . . . . . . 310
Table 176. Reset and Stop-Mode Recovery Pin Timing . . . . . . . . . . . . . . . . . . . . . . . 310
Table 177. Flash Memory Electrical Characteristics and Timing . . . . . . . . . . . . . . . . 311
Table 178. Watchdog Timer Electrical Characteristics and Timing . . . . . . . . . . . . . . 311
Table 179. ADC Electrical Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . 312
Table 180. Comparator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Table 181. Operational Amplifier Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 313
Table 182. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Table 183. GPIO Port Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Table 184. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Table 185. SPI MASTER Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Table 186. SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Table 187. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Table 188. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Table 189. UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Table 190. Z16FMC Series Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Table 191. Zilog Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
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List of Tables
Z16FMC Series Motor Control MCUs
Product Specification
1
Introduction
Zilog’s Z16FMC Series of products is optimized for motor control applications. The
Z16FMC is a 16-bit microcontroller with a ZNEO CPU and is the most powerful member
of Zilog’s Motor Control Family of MCUs.
Features
The Z16FMC Series of products includes the following features:
•
•
•
•
•
•
•
•
20MHz ZNEO CPU
128KB internal Flash memory with 16-bit access and In-Circuit Programming (ICP)
4KB internal RAM with 16-bit access
12-channel, 10-bit Analog-to-Digital Converter (ADC)
Operational Amplifier
Analog Comparator
4-channel Direct Memory Access (DMA) Controller
Two full-duplex 9-bit Universal Asynchronous Receiver/Transmitters (UARTs) with
support for Local Interconnect Network (LIN) and Infrared Data Association (IrDA)
•
•
•
•
Internal Precision Oscillator (IPO)
Inter-Integrated Circuit (I2C) master/slave controller
Enhanced Serial Peripheral Interface (ESPI)
12-bit Pulse Width Modulation (PWM) module with three complementary pairs or six
independent PWM outputs with deadband generation and fault trip input
•
•
•
•
•
•
•
•
•
Three standard 16-bit timers with Capture, Compare and PWM capability
Watchdog Timer (WDT) with internal RC oscillator
46 General-Purpose Input/Output (GPIO) pins
24 interrupts with programmable priority
On-Chip Debugger (OCD)
Voltage Brown-Out (VBO) protection
Power-On Reset (POR)
2.7V to 3.6V operating voltage with 5 V-tolerant inputs
0°C to +70°C standard temperature and –40°C to +105°C extended temperature oper-
ating ranges
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P R E L I M I N A R Y
Introduction
Z16FMC Series Motor Control MCUs
Product Specification
2
Block Diagram
Figure 1 displays the architecture of the Z16FMC Series.
Oscillators
(XTAL, IPO)
On-Chip
Debugger
POR/VBO
ZNEO
CPU
and Reset
Interrupt
Controller
WDT with
Controller
RC Oscillator
System
Clock
Memory Buses
Timers
(3)
UARTs
(2)
2
Flash
Controller
RAM
Controller
I C
ESPI
Analog
DMA
PWM
IrDA
Flash
Memory
RAM
GPIO
Figure 1. Z16FMC Series Block Diagram
ZNEO CPU Features
Zilog’s Z16FMC Series is powered by the ZNEO CPU, which meets the continuing
demand for faster and more code-efficient microcontrollers. The ZNEO CPU features:
•
•
•
8-bit, 16-bit and 32-bit ALU operations
24-bit stack with overflow protection
Direct register-to-register architecture allows each memory address to function as an
accumulator to improve execution time and decreases the required program memory
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P R E L I M I N A R Y
Block Diagram
Z16FMC Series Motor Control MCUs
Product Specification
3
•
•
New instructions improve execution efficiency for code developed using higher-level
programming languages, including the C language
Pipelined instructions: Fetch, Decode and Execute
For more information about the ZNEO CPU, refer to the ZNEO CPU Core User Manual
(UM0188), available free for download from the Zilog website.
Flash Z16FMC Controller
The Z16FMC products contain up to 128KB of internal Flash memory. The Flash control-
ler programs and erases Flash memory. The ZNEO CPU simultaneously accesses 16 bits
of internal Flash memory to improve the processor throughput. A sector protection
scheme allows flexible protection of user code.
Random Access Memory
An internal RAM of 4KB provides storage space for data, variables and stack operations.
Like Flash memory, the ZNEO CPU simultaneously accesses 16 bits of internal RAM to
improve processor performance.
Motor Control Peripherals Overview
Zilog’s Z16FMC Series motor control peripherals are briefly described in this section.
10-Bit Analog-to-Digital Converter with Programmable Gain
Amplifier
The ADC converts an analog input signal to a 10-bit binary number. The ADC accepts
inputs from 12 different analog input sources.
Analog Comparator
It features an on-chip analog comparator with external input pins.
Operational Amplifier
It features a two-input, one-output operational amplifier.
General-Purpose Input/Output
The Z16FMC Series MCU features 46 GPIO pins. Each pin is individually programmable.
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Motor Control Peripherals Overview
Z16FMC Series Motor Control MCUs
Product Specification
4
Universal Asynchronous Receiver/Transmitter
The Z16FMC MCU contains two fully-featured UARTs with LIN protocol support. UART
communication is full-duplex and capable of handling asynchronous data transfers. These
UARTs support 8-bit and 9-bit data modes, selectable parity and an efficient bus trans-
ceiver driver enable signal for controlling a multi-transceiver bus, such as RS-485.
Infrared Encoder/Decoders
Z16FMC Series products contain two fully-functional, high-performance UARTs to Infra-
red Encoder/Decoders (Endecs). The infrared endec is integrated with an on-chip UART
to allow easy communication between the Z16FMC device and IrDA physical layer speci-
fication Version 1.3-compliant infrared transceivers. Infrared communication provides
secure, reliable, low-cost and point-to-point communication between PCs, PDAs, cell
phones, printers and other infrared enabled devices.
Inter-Integrated Circuit Master/Slave Controller
The I2C controller makes the Z16FMC Series MCU compatible with the I2C protocol. It
consists of two bidirectional bus lines, a serial data (SDA) line and a serial clock (SCL)
line. The I2C operates as a Master and/or Slave and supports multi-master bus arbitration.
Enhanced Serial Peripheral Interface
The ESPI allows the data exchange between the Z16FMC MCU and other peripheral
devices such as electrically erasable programmable read-only memory (EEPROMs),
ADCs and integrated service digital network (ISDN) devices. The SPI is a full-duplex,
synchronous, character-oriented channel which supports a four-wire interface.
DMA Controller
The Z16FMC Series MCU features a 4-channel DMA for efficient transfer of data
between peripherals and/or memories.
Pulse Width Modulator
The Z16FMC Series MCU features a flexible PWM module with three complementary
pairs or six independent PWM outputs supporting deadband operation and fault protection
trip input. These features provide multiphase control capability for a variety of motor
types and ensure safe operation of the motor by providing immediate shutdown of the
PWM pins during Fault condition.
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Motor Control Peripherals Overview
Z16FMC Series Motor Control MCUs
Product Specification
5
Standard Timers
Three 16-bit reloadable timers are used for timing/counting events and PWM signal gener-
ation. These timers provide a 16-bit programmable reload counter and operate in ONE-
SHOT, CONTINUOUS, GATED, CAPTURE, COMPARE, CAPTURE and COMPARE
and PWM modes. The PWM function provides two complementary output signals with
programmable dead-time insertion.
Interrupt Controller
The Z16FMC Series products support three levels of programmable interrupt priority. The
interrupt sources include internal peripherals, GPIO pins and system fault detection.
Crystal Oscillator
The on-chip crystal oscillator features programmable gain to support crystals and ceramic
resonators from 32kHz to 20MHz. The oscillator is also used with external RC networks
or clock drivers.
Reset Controller
The Z16FMC Series MCU is reset using the RESET pin, POR, WDT, Stop-Mode Recov-
ery, or VBO warning signal. The bidirectional RESET pin also provides a system RESET
output indicator.
On-Chip Debugger
The Z16FMC Series MCU features an integrated OCD. The OCD provides a rich-set of
debugging capabilities, such as reading and writing memory, programming the Flash, set-
ting breakpoints and executing code. A single-pin interface provides communication to
the OCD.
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Motor Control Peripherals Overview
Z16FMC Series Motor Control MCUs
Product Specification
6
Signal and Pin Descriptions
The Z16FMC Series MCU products are available in a 64 pin LQFP package. This chapter
describes the signals and pin configuration for the LQFP package style. For more informa-
tion about the physical package specification, see the Packaging chapter on page 318.
Pin Configuration
Figure 2 displays the configuration of the LQFP package. For a description of each signal,
see Table 1 on page 8.
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Signal and Pin Descriptions
Z16FMC Series Motor Control MCUs
Product Specification
7
40
48
PA0/T0IN/T0OUT 49
33
32 PA7/SDA
PD6/CTS1
PC3/SCK
PD2/PWMH2
PC2/SS
PD7/PWML2
RESET
V
V
SS
DD
PE5
PE6
PE7
PE4
PE3
25
V
56
SS
V
PE2
PE1
PE0
DD
PG3
V
DD
PC7/T2OUT/PWML0
PC6/T2IN/T2OUT/PWMH0
DBG
V
SS
PD1/PWML1
PD0/PWMH1
X
PC1/T1OUT/COMPOUT
OUT
X
64
17 PC0/T1IN/T1OUT/CINN
16
IN
1
8
Figure 2. Z16FMC in the 64-Pin Low-Profile Quad Flat Package (LQFP)
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Pin Configuration
Z16FMC Series Motor Control MCUs
Product Specification
8
Signal Descriptions
Table 1 describes the Z16FMC Series MCU signals. To determine the signals available for
the LQFP package, see the Pin Configuration chapter on page 6. Most of the signals
described in Table 1 are multiplexed with GPIO pins. These signals are available as alter-
nate functions on the GPIO pins. For more details about GPIO alternate functions, see the
General-Purpose Input/Output chapter on page 42.
Table 1. Signal Descriptions
Signal Mnemonic
I/O
Description
General-Purpose Input/Output Ports A–H
PA[7:0]
PB[7:0]
PC[7:0]
PD[7:0]
PE[7:0]
PF[7]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port A[7:0]. These pins are used for GPIO.
Port B[7:0]. These pins are used for GPIO.
Port C[7:0]. These pins are used for GPIO.
Port D[7:0]. These pins are used for GPIO.
Port E[7:0]. These pins are used for GPIO.
Port F[7]. This pin is used for GPIO.
PG[3]
Port G[3]. This pin is used for GPIO.
PH[3:0]
Port H[3:0]. These pins are used for GPIO.
Inter-Integrated Circuit Controller
2
SCL
I/O
Serial clock. An input or an output clock for the I C. When the
GPIO pin is configured for alternate function to enable the SCL
function, this pin is open-drain.
2
SDA
I/O
Serial data. This open-drain pin transfers data between the I C
and a slave. When the GPIO pin is configured for alternate func-
tion to enable the SDA function, this pin is open-drain.
Enhanced Serial Peripheral Interface Controller
I/O
Slave select. This signal is an output or an input. If the Z16FMC
MCU is the SPI master, this pin is configured as the slave select
output. If the Z16FMC Series MCU is the SPI slave, this pin is an
input slave select.
SS
SCK
I/O
SPI serial clock. The SPI master supplies this pin. If the Z16FMC
device is the SPI master, this pin is an output. If the Z16FMC
device is the SPI slave, this pin is an input.
MOSI
MISO
I/O
I/O
Master-Out/Slave-In. This signal is the data output from the SPI
master device and the data input to the SPI slave device.
Master-In/Slave-Out. This pin is the data input to the SPI master
device and the data output from the SPI slave device.
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Signal Descriptions
Z16FMC Series Motor Control MCUs
Product Specification
9
Table 1. Signal Descriptions (Continued)
Signal Mnemonic
I/O
Description
UART Controllers
TXD0
O
I
Transmit data. These signals transmit outputs from the UARTs.
RXD0
Receive data. These signals receives inputs for the UARTs and
IrDAs.
CTS0
DE0
I
Clear to Send. These signals are control inputs for the UARTs.
O
Driver enable (DE). This signal allows automatic control of external
RS-485 driver. This signal is approximately the inverse of the
Transmit Empty (TXE) bit in the UART Status 0 Register. The DE
signal is used to ensure an external RS-485 driver is enabled
when data is transmitted by the UARTs.
General-Purpose Timers
T0OUT/T0OUT
T1OUT/T1OUT
T2OUT/T2OUT
O
I
General-purpose timer outputs. These signals are output pins from
the timers.
T0IN/T0IN1/T0IN2
/T1IN/T2IN
General-purpose timer inputs. These signals are used as the cap-
ture, gating and counter inputs.
Pulse-Width Modulator for Motor Control
PWMH0/PWMH1/
PWMH2
O
O
I
PWM High output.
PWML0/PWML1/
PWML2
PWM Low output.
FAULT0/FAULT1
PWM Fault condition input. FAULT0 and FAULT1 are active Low.
Analog
ANA[11:0]
VREF
I
I
Analog input. These signals are inputs to the ADC.
ADC reference voltage input or internal reference output.
Caution: The V
pin must be capacitively coupled to analog
REF
ground, if the internal voltage reference is selected as the ADC ref-
erence voltage. A 1µF capacitor is recommended.
CINP
I
I
Comparator positive input.
Comparator negative input.
Comparator output
CINN
COMPOUT
OPINP
OPINN
OPOUT
O
I
Operational amplifier positive input
Operational amplifier negative input
Operational amplifier output
I
O
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Signal Descriptions
Z16FMC Series Motor Control MCUs
Product Specification
10
Table 1. Signal Descriptions (Continued)
Signal Mnemonic
Oscillators
I/O
Description
X
I
External crystal input. The input pin to the crystal oscillator.
IN
A crystal is connected between it and the X
pin to form the
OUT
oscillator. In addition, this pin is used with external RC networks or
external clock drivers to provide the system clock to the system.
X
O
External crystal output. This pin is the output of crystal oscillator. A
OUT
crystal is connected between it and the X pin to form the oscilla-
IN
tor. This pin must be left unconnected when not using a crystal.
On-Chip Debugger
DBG
I/O
Debug. This pin is the control and data input and output to and
from the OCD.
Caution: For operation of the OCD, all power pins (V and
DD
AV ) must be supplied with power and all ground pins (V and
DD
SS
AV ) must be grounded. This pin is open-drain and must have an
SS
external pull-up resistor to ensure proper operation.
Reset
RESET
I/O
RESET. Bidirectional RESET signals generates a Reset when
asserted (driven Low) and drives a Low output when the Z16FMC
MCU is in Reset.
Power Supply
V
I
I
I
I
Power supply
Analog power supply
Ground
DD
AV
DD
SS
V
SS
AV
Analog ground
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Signal Descriptions
Z16FMC Series Motor Control MCUs
Product Specification
11
Pin Characteristics
Table 2 lists information about the characteristics of each pin available on Z16FMC Series
products. Data is sorted alphabetically by pin symbol mnemonic.
Table 2. Pin Characteristics of the Z16FMC Series MCU
Internal
Tri–State Pull-Up or
Schmitt
Trigger
Input
Symbol
Reset
Active
Open Drain
Output
Mnemonic Direction Direction Low/High Output
Pull-Down
AV
AV
N/A
N/A
I/O
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Yes
Yes
No
No
N/A
N/A
Yes
DD
SS
N/A
No
No
DBG
I
I
Pull-up
Yes
Yes
PA[7:0]
I/O
Pull-up,
Yes,
Programmable
Programmable
PB[7:0]
PC[7:0]
PD[7:0]
PE[7:0]
PF[7:0]
PG[7:0]
PH[3:0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Pull-up,
Programmable
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes,
Programmable
Pull-up,
Programmable
Yes,
Programmable
Pull-up,
Programmable
Yes,
Programmable
Pull-up,
Programmable
Yes,
Programmable
Pull-up,
Programmable
Yes,
Programmable
Pull-up,
Programmable
Yes,
Programmable
Pull-up,
Yes,
Programmable
Programmable
RESET
VREF
I/O
I/O
N/A
N/A
I
I
Low
N/A
N/A
N/A
N/A
N/A
N/A
Yes
N/A
N/A
N/A
N/A
Pull-up
N/A
No
Yes
No
No
No
No
No
Yes
No
I
V
V
X
X
N/A
N/A
I
N/A
N/A
N/A
No
DD
SS
No
No
IN
O
O
No
OUT
Note: X represents integers 0, 1,... to indicate multiple pins with symbol mnemonics which differ only by
an integer.
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Pin Characteristics
Z16FMC Series Motor Control MCUs
Product Specification
12
Address Space
The ZNEO CPU offers a unique architecture with a single, unified 24-bit address space. It
supports up to three memory areas:
•
•
•
Internal nonvolatile memory (Flash, EEPROM, EPROM, or ROM).
Internal RAM.
Internal I/O memory (internal peripherals).
The ZNEO CPU supports three different data widths:
•
•
•
Byte (8-bit)
Word (16-bit)
Quad (32-bit)
The ZNEO CPU accesses memories of differing bus width:
•
•
8-bit-wide memories
16-bit-wide memories
Memory Map
A memory map of the ZNEO, including the location of internal nonvolatile memory, inter-
nal RAM and internal I/O memory, is illustrated in Figure 3.
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Address Space
Z16FMC Series Motor Control MCUs
Product Specification
13
FF_FFFFh – Top of I/O Memory
Internal I/O Memory
Reserved
FF_E000h – Bottom of I/O Memory
FF_DFFFh
FF_C000h
FF_BFFFh – Top of Internal RAM
XX_XXXXH – Bottom of Internal RAM
(device specific)
Internal RAM
Reserved
XX_XXXXH – Top of Internal Nonvolatile Memory
(device specific)
Internal Nonvolatile
Memory
00_0000h – Bottom of Internal Nonvolatile Memory
Figure 3. Physical Memory Map
To determine the amount of internal RAM and internal nonvolatile memory available for
the specific device, see the Ordering Information section on page 322.
Internal Nonvolatile Memory
Internal nonvolatile memory contains executable program code, constants and data. For
each product within the ZNEO family, a memory block beginning at address 00_0000his
reserved for user option bits and system vectors (for example, RESET, Trap, Interrupts
and System Exceptions, etc.). Table 3 provides an example of a reserved memory map for
a ZNEO product with 24 interrupt vectors.
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Internal Nonvolatile Memory
Z16FMC Series Motor Control MCUs
Product Specification
14
Table 3. Reserved Memory Map Example
Memory Address (Hex)
00_0000–00_0003
00_0004–00_0007
00_0008–00_000B
00_000C–00_000F
00_0010–00_006F
Description
Option bits
RESET vector
System exception vector
Privileged trap vector
Interrupt vectors
Internal RAM
Internal RAM is mainly employed for data and stacks. However, internal RAM also con-
tains program code for execution. Most ZNEO devices contain some internal RAM. The
top (highest address) of internal RAM is always located at address FF_BFFFh. The bottom
(lowest address) of internal RAM is a function of the amount of internal RAM available.
To determine the amount of internal RAM available, see the Ordering Information section
on page 322.
Input/Output Memory
The ZNEO supports 8KB (8,192 bytes) of I/O memory space located at addresses
FF_E000hthrough FF_FFFFh. The I/O memory addresses are reserved for control of the
ZNEO, the on-chip peripherals and the I/O ports. Refer to the device-specific product
specification for descriptions of the peripheral and I/O control registers. Attempts to read
or execute from unavailable I/O memory addresses returns FFh. Attempts to write to
unavailable I/O memory addresses produce no effect.
Input/Output Memory Precautions
Some control registers within the I/O memory provide read-only or write-only access.
When accessing these read-only or write-only registers, ensure that the instructions do not
attempt to read from a write-only register, or conversely write to a read-only register.
ZNEO CPU Control Registers
Some control registers are reserved in 8KB of I/O memory for the ZNEO control. These
registers are listed in Table 4. For detailed information about the operation of the ZNEO
control registers, refer to the ZNEO CPU Core User Manual (UM0188), available free for
download from the Zilog website.
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Internal RAM
Z16FMC Series Motor Control MCUs
Product Specification
15
Table 4. ZNEO CPU Control Registers
Address (Hex)
FF_E004-FF_E007
FF_E00C-FF_E00F
FF_E010
Register Description
Program counter overflow
Stack pointer overflow
Flags
Register Mnemonic
PCOV
SPOV
FLAGS
FF_E012
CPU control
CPUCTL
Endianness
The ZNEO CPU accesses data in big endian order, i.e., the address of a multi-byte word or
quad points to the most significant byte. Figure 4 displays the Endianness of the CPU.
LSB
00_0081h
00_0080h
Address
of Word
MSB
00_0083h
LSB
00_0082h
00_0081h
00_0080h
Address
of Quad
MSB
Figure 4. Endianness of Words and Quads
Bus Widths
The ZNEO CPU accesses 8-bit or 16-bit memories. The data buses of the internal nonvol-
atile memory and internal RAM are 16-bit wide. The internal peripherals are a mix of 8-bit
and 16-bit peripherals.
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Endianness
Z16FMC Series Motor Control MCUs
Product Specification
16
If a Word or Quad operation occurs on a 16-bit wide memory, the number of memory
accesses depends on the alignment of the address. If the address is aligned on an even
boundary, a Word operation takes one memory access and a Quad operation takes two
memory accesses. If the address is on an odd boundary (unaligned), a Word operation
takes two memory accesses and a Quad operation takes three memory accesses. Figure 5
displays the alignment Word and Quad operations on 16-bit memories.
000082h
000080h
000083h
LSB
000080h
LSB 000081h
MSB 000081h
MSB
Aligned Word Access
Unaligned Word Access
000084h
LSB
000085h
000083h
000082h
000080h MSB
LSB 000083h
000082h
000080h
000081h
MSB 000081h
Aligned Quad Access
Unaligned Quad Access
Figure 5. Alignment of Word and Quad Operations on 16-Bit Memories
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Bus Widths
Z16FMC Series Motor Control MCUs
Product Specification
17
Peripheral Address Map
Table 5 provides the address map for the peripheral space of the Z16FMC Series of prod-
ucts. Not all devices and package styles in the Z16FMC Series support all peripherals or
all GPIO ports. Registers for unimplemented peripherals are considered reserved.
Table 5. Register File Address Map
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
CPU Base Address = FF_E000
FF_E004–FF_E007 Program Counter
Overflow
PCOV
SPOV
00FFFFFF
00000000
See the
ZNEO CPU
Core User
Manual
FF_E00C–FF_E00F Stack Pointer
Overflow
FF_E010
FF_E012
Flags
FLAGS
XX
00
CPU Control
CPUCTL
Trace Address = FF_E014
FF_E013
Trace Control
TRACECTL
00
292
293
FF_E014–FF_E017 Trace Address
TRACEADDR
XXXXXXXX
Interrupt Controller Base Address = FF_E020
FF_E020
System Exception
Status High
SYSEXCPH
0000
0000
58
58
FF_E021
System Exception
Status Low
SYSEXCPL
FF_E022
FF_E023
Reserved
–
XX
02
–
–
Last IRQ Register
LASTIRQ
–
60
–
FF_E024–FF_E02F Reserved
FF_E030
FF_E031
Interrupt Request 0
IRQ0
00
xx
60
60
Interrupt Request 0
Set
IRQ0SET
FF_E032
FF_E033
FF_E034
FF_E035
IRQ0 Enable High Bit IRQ0ENH
IRQ0 Enable Low Bit IRQ0ENL
00
00
00
XX
64
64
62
62
Interrupt Request 1
IRQ1
Interrupt Request
1Set
IRQ1SET
FF_E036
IRQ1 Enable High Bit IRQ1ENH
00
66
Note: XX = undefined.
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Z16FMC Series Motor Control MCUs
Product Specification
18
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
Interrupt Controller Base Address = FF_E020 (cont’d.)
FF_E037
FF_E038
FF_E039
IRQ1 Enable Low Bit IRQ1ENL
00
00
xx
66
63
63
Interrupt Request 2
IRQ2
Interrupt Request 2
Set
IRQ2SET
FF_E03A
FF_E03B
IRQ2 Enable High Bit IRQ2ENH
IRQ2 Enable Low Bit IRQ2ENL
00
00
XX
67
67
–
FF_E03C–FF_E03F Reserved
–
Watchdog Timer Base Address = FF_E040
FF_E040–FF_E041 Reserved
–
–
–
FF_E042
Watchdog Timer
Reload
WDTH
04
112
High Byte
FF_E043
Watchdog Timer
Reload
Low Byte
WDTL
–
00
–
112
–
FF_E044–FF_E04F Reserved
Reset Base Address = FF_E050
FF_E050
Reset Status and
Control Register
RSTSCR
–
XX
XX
39
–
FF_E051–FF_E06F Reserved
Flash Controller Base Address = FF_E060
FF_E060
Flash Command
Register
FCMD
XX
256
FF_E060
FF_E061
Flash Status Register FSTAT
00
00
256
257
Flash Control
Register
FCTL
FF_E062
FF_E063
Flash Sector Protect FSECT
Register
00
258
Reserved
–
XX
–
FF_E064–FF_E065 Flash Page Select
Register
FPAGE
0000
258
FF_E066–FF_E067h Flash Frequency
Register
FFREQ
0000
259
Note: XX = undefined.
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Z16FMC Series Motor Control MCUs
Product Specification
19
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
On Chip Debugger = FF_E080
FF_E080
Debug Receive Data DBGRXD
XX
283
On Chip Debugger = FF_E080 (cont’d.)
FF_E081
Debug Transmit Data DBGTXD
XX
284
284
285
286
288
FF_E082–FF_E083 Debug Baud Rate
DBGBR
XXXX
XX
FF_E084
FF_E085
FF_E086
Debug Line Control
Debug Status
DBGLCR
DBGSTAT
DBGCTL
XX
Debug Control
XX
Hardware Breakpoints = FF_E090
FF_E090–FF_E093 Hardware Breakpoint HWBP0
0
00000000
00000000
00000000
00000000
291
291
291
291
FF_E094–FF_E097 Hardware Breakpoint HWBP1
1
FF_E098–FF_E09B Hardware Breakpoint HWBP2
2
FF_E09C–FF_E09F Hardware Breakpoint HWBP3
3
Oscillator Control Base Address = FF_E0A0
FF_E0A0
FF_E0A1
Oscillator Control
Oscillator Divide
OSCCTL
OSCDIV
A0
00
302
303
GPIO Base Address = FF_E100
GPIO Port A Base Address = FF_E100
FF_E100
FF_E101
FF_E102
FF_E103
Port A Input Data
PAIN
XX
00
00
00
46
46
47
47
Port A Output Data
PAOUT
Port A Data Direction PADD
Port A High Drive
Enable
PAHDE
PAAFH
PAAFL
FF_E104
FF_E105
Port A Alternate
Function High
00
00
48
48
Port A Alternate
Function Low
FF_E106
Port A Output Control PAOC
Port A Pull-Up Enable PAPUE
00
00
49
50
FF_E107
Note: XX = undefined.
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Z16FMC Series Motor Control MCUs
Product Specification
20
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
GPIO Port A Base Address = FF_E100 (cont’d.)
FF_E108
Port A Stop-Mode
Recovery
PASMRE
00
51
Enable
FF_E109–FF_E10B Port A Reserved
–
–
–
FF_E10C
FF_E10D
FF_E10E
FF_E10F
Port A IRQ MUX1
Port A Reserved
Port A IRQ MUX
Port A Irq Edge
PAIMUX1
–
00
–
52
–
PAIMUX
PAIEDGE
00
00
52
53
GPIO Port B Base Address = FF_E110
FF_E110
FF_E111
FF_E112
FF_E113
Port B Input Data
PBIN
XX
00
00
00
46
46
47
47
Port B Output Data
PBOUT
Port B Data Direction PBDD
Port B High Drive
Enable
PBHDE
FF_E114
FF_E115
Reserved
–
–
–
Port B Alternate
Function Low
PBAFL
00
48
FF_E116
FF_E117
FF_E118
Port B Output Control PBOC
Port B Pull-Up Enable PBPUE
00
00
00
49
50
51
Port B Stop-Mode
Recovery
PBSMRE
Enable
FF_E119–FF_E11F
Port B Reserved
–
–
–
GPIO Port C Base Address = FF_E120
FF_E120
FF_E121
FF_E122
FF_E123
Port C Input Data
PCIN
XX
00
00
00
46
46
47
47
Port C Output Data
PCOUT
Port C Data Direction PCDD
Port C High Drive
Enable
PCHDE
PCAFH
PCAFL
FF_E124
Port C Alternate
Function High
00
00
48
49
FF_E125
Port C Alternate
Function Low
Note: XX = undefined.
PS028706-0813
P R E L I M I N A R Y
Peripheral Address Map
Z16FMC Series Motor Control MCUs
Product Specification
21
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
GPIO Port C Base Address = FF_E120 (cont’d.)
FF_E126
FF_E127
FF_E128
Port C Output Control PCOC
Port C Pull-Up Enable PCPUE
00
00
00
49
50
51
Port C Stop-Mode
Recovery
PCSMRE
Enable
FF_E129–FF_E12D Port C Reserved
–
–
–
53
–
FF_E12E
FF_E12F
Port C IRQ MUX
Port C Reserved
PCIMUX
–
00
–
GPIO Port D Base Address = FF_E130
FF_E130
FF_E131
FF_E132
FF_E133
Port D Input Data
PDIN
XX
00
00
00
46
46
47
47
Port D Output Data
PDOUT
Port D Data Direction PDDD
Port D High Drive
Enable
PDHDE
PDAFH
PDAFL
FF_E134
FF_E135
Port D Alternate
Function High
00
00
48
49
Port D Alternate
Function Low
FF_E136
FF_E137
FF_E138
Port D Output Control PDOC
Port D Pull-Up Enable PDPUE
00
00
00
49
50
51
Port D Stop-Mode
Recovery
PDSMRE
Enable
FF_E139–FF_E13F Port D Reserved
–
–
–
GPIO Port E Base Address = FF_E140
FF_E140
FF_E141
FF_E142
FF_E143
Port E Input Data
PEIN
XX
00
00
00
46
46
47
47
Port E Output Data
PEOUT
Port E Data Direction PEDD
Port E High Drive
Enable
PEHDE
FF_E144
Reserved
Reserved
–
–
–
–
–
FF_E145
–
FF_E146
Port E Output Control PEOC
00
49
Note: XX = undefined.
PS028706-0813
P R E L I M I N A R Y
Peripheral Address Map
Z16FMC Series Motor Control MCUs
Product Specification
22
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
GPIO Port E Base Address = FF_E140 (cont’d.)
FF_E147
FF_E148
Port E Pull-Up Enable PEPUE
00
00
50
51
Port E Stop-Mode
Recovery Enable
PESMRE
FF_E149–FF_E14F Port E Reserved
–
–
–
GPIO Port F Base Address = FF_E150
FF_E150
FF_E151
FF_E152
FF_E153
Port F Input Data
PFIN
XX
00
00
00
46
46
47
47
Port F Output Data
PFOUT
Port F Data Direction PFDD
Port F High Drive
Enable
PFHDE
FF_E154
FF_E155
Reserved
–
–
–
Port F Alternate
Function Low
PFAFL
00
49
FF_E156
FF_E157
FF_E158
Port F Output Control PFOC
Port F Pull-Up Enable PFPUE
00
00
00
49
50
51
Port F Stop-Mode
Recovery
PFSMRE
Enable
FF_E159–FF_E15F Port F Reserved
–
–
–
GPIO Port G Base Address = FF_E160
FF_E160
FF_E161
FF_E162
FF_E163
Port G Input Data
Port G Output Data
PGIN
XX
00
00
00
46
46
47
47
PGOUT
Port G Data Direction PGDD
Port G High Drive
Enable
PGHDE
FF_E164
FF_E165
Reserved
–
–
–
Port G Alternate
Function Low
PGAFL
00
49
FF_E166
FF_E167
FF_E168
Port G Output Control PGOC
Port G Pull-Up Enable PGPUE
00
00
00
49
50
51
Port G Stop-Mode
Recovery Enable
PGSMRE
FF_E169–FF_E16F Port G Reserved
Note: XX = undefined.
–
–
–
PS028706-0813
P R E L I M I N A R Y
Peripheral Address Map
Z16FMC Series Motor Control MCUs
Product Specification
23
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
GPIO Port H Base Address = FF_E170
FF_E170
FF_E171
FF_E172
FF_E173
Port H Input Data
PHIN
XX
00
00
00
46
46
47
47
Port H Output Data
PHOUT
Port H Data Direction PHDD
Port H High Drive
Enable
PHHDE
PHAFH
PHAFL
FF_E174
FF_E175
Port H Alternate
Function High
00
00
48
49
Port H Alternate
Function Low
FF_E176
FF_E177
FF_E178
Port H Output Control PHOC
Port H Pull-Up Enable PHPUE
00
00
00
49
50
51
Port H Stop-Mode
Recovery
PHSMRE
Enable
FF_E179–FF_E17F Port H Reserved
Serial Channels Base Address = FF_E200
LIN-UART 0 Base Address = FF_E200
–
–
–
FF_E200
LIN-UART 0 Transmit U0TXD
Data
XX
XX
133
133
LIN-UART 0 Receive U0RXD
Data
FF_E201
FF_E202
FF_E203
FF_E204
LIN-UART 0 Status 0 U0STAT0
LIN-UART 0 Control 0 U0CTL0
LIN-UART 0 Control 1 U0CTL1
0000011Xb
134
139
142
141
00
00
00
LIN-UART 0 Mode
Select and Status
U0MDSTAT
FF_E205
FF_E206
FF_E207
LIN-UART 0 Address U0ADDR
Compare Register
00
FF
FF
XX
144
145
145
–
LIN-UART 0 Baud
Rate High Byte
U0BRH
U0BRL
–
LIN-UART 0 Baud
Rate Low Byte
FF_E208–FF_E20F Reserved
Note: XX = undefined.
PS028706-0813
P R E L I M I N A R Y
Peripheral Address Map
Z16FMC Series Motor Control MCUs
Product Specification
24
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
LIN-UART 1 Base Address = FF_E210
FF_E210
LIN-UART 1 Transmit U1TXD
Data
XX
XX
133
133
LIN-UART 1 Receive U1RXD
Data
FF_E211
FF_E212
FF_E213
FF_E214
LIN-UART 1 Status 0 U1STAT0
LIN-UART 1 Control 0 U1CTL0
LIN-UART 1 Control 1 U1CTL1
0000011Xb
134
139
142
141
00
00
00
LIN-UART 1 Mode
Select and Status
U1MDSTAT
FF_E215
FF_E216
FF_E217
LIN-UART 1 Address U1ADDR
Compare Register
00
FF
FF
XX
144
145
145
–
LIN-UART 1 Baud
Rate High Byte
U1BRH
U1BRL
–
LIN-UART 1 Baud
Rate Low Byte
FF_E218–FF_E23F Reserved
2
I C Base Address = FF_E240
2
FF_E240
FF_E241
FF_E242
FF_E243
I C Data
I2CDATA
I2CISTAT
I2CCTL
00
80
00
FF
205
205
206
208
2
I C Interrupt Status
2
I C Control
2
I C Baud Rate High I2CBRH
Byte
2
FF_E244
I C Baud Rate Low
Byte
I2CBRL
FF
208
2
FF_E245
FF_E246
FF_E247
I C State
I2CSTATE
I2CMODE
I2CSLVAD
–
C0
00
00
XX
209
212
214
–
2
I C Mode
2
I C Slave Address
FF_E248–FF_E25F Reserved
Enhanced Serial Peripheral Interface Base Address = FF_E260
FF_E260
ESPI Data
Reserved
ESPIDATA
–
XX
XX
00
170
FF_E261
FF_E262
ESPI Control
ESPI Mode
ESPICTL
ESPIMODE
171
173
FF_E263
00
Note: XX = undefined.
PS028706-0813
P R E L I M I N A R Y
Peripheral Address Map
Z16FMC Series Motor Control MCUs
Product Specification
25
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
Enhanced Serial Peripheral Interface Base Address = FF_E260 (cont’d.)
FF_E264
FF_E265
FF_E266
ESPI Status
ESPI State
ESPISTAT
01
00
FF
175
176
178
ESPISTATE
ESPI Baud Rate High ESPIBRH
Byte
FF_E267
ESPI Baud Rate Low ESPIBRL
Byte
FF
179
Timers, Base Address = FFF_E300
Timer 0 (General-Purpose Timer) Base Address = FF_E300
FF_E300
FF_E301
FF_E302
Timer 0 High Byte
Timer 0 Low Byte
T0H
T0L
00
01
FF
81
81
82
Timer 0 Reload High T0RH
Byte
FF_E303
FF_E304
FF_E305
Timer 0 Reload Low T0RL
Byte
FF
00
00
82
83
83
Timer 0 PWM High
Byte
T0PWMH
Timer 0 PWM Low
Byte
T0PWML
FF_E306
FF_E307
Timer 0 Control 0
Timer 0 Control 1
T0CTL0
T0CTL1
00
00
84
85
Timer 1 (General-Purpose Timer) Base Address = FF_E310
FF_E310
FF_E311
FF_E312
Timer 1 High Byte
Timer 1 Low Byte
T1H
T1L
00
01
FF
81
81
82
Timer 1 Reload High T1RH
Byte
FF_E313
FF_E314
FF_E315
Timer 1 Reload Low T1RL
Byte
FF
00
00
82
83
83
Timer 1 PWM High
Byte
T1PWMH
Timer 1 PWM Low
Byte
T1PWML
FF_E316
Timer 1 Control 0
Timer 1 Control 1
T1CTL0
T1CTL1
00
00
84
85
FF_E317
Note: XX = undefined.
PS028706-0813
P R E L I M I N A R Y
Peripheral Address Map
Z16FMC Series Motor Control MCUs
Product Specification
26
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
Timer 2 (General-Purpose Timer) Base Address = FF_E320
FF_E320
FF_E321
FF_E322
Timer 2 High Byte
Timer 2 Low Byte
T2H
T2L
00
01
FF
81
81
82
Timer 2 Reload High T2RH
Byte
FF_E323
FF_E324
FF_E325
Timer 2 Reload Low T2RL
Byte
FF
00
00
82
83
83
Timer 2 PWM High
Byte
T2PWMH
Timer 2 PWM Low
Byte
T2PWML
FF_E326
FF_E327
Timer 2 Control 0
Timer 2 Control 1
T2CTL0
T2CTL1
00
00
84
85
Pulse Width Modulator (PWM) Base Address = FF_E380
FF_E380
FF_E381
FF_E382
FF_E383
PWM Control 0
PWM Control 1
PWM Deadband
PWMCTL0
PWMCTL1
PWMDB
00
00
00
00
100
101
102
103
PWM Minimum Pulse PWMMPF
Width Filter
FF_E384
FF_E385
FF_E386
PWM Fault Mask
PWM Fault Status
PWMFM
PWMFSTAT
PWMIN
00
00
00
103
104
106
PWM Input Sample
Register
FF_E387
FF_E388
FF_E389
FF_E38A
PWM Output Control PWMOUT
00
00
–
107
105
–
PWM Fault Control
Reserved
PWMFCTL
–
Current-Sense
Sample and Hold
Control 0
CSSHR0
00
108
FF_E38B
Current-Sense
Sample and Hold
Control 1
CSSHR1
00
108
FF_E38C–FF_E38B Reserved
–
–
–
FF_E38C
PWM High Byte
PWM Low Byte
PWMH
PWML
XX
XX
96
97
FF_E38D
Note: XX = undefined.
PS028706-0813
P R E L I M I N A R Y
Peripheral Address Map
Z16FMC Series Motor Control MCUs
Product Specification
27
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
Pulse Width Modulator (PWM) Base Address = FF_E380 (cont’d.)
FF_E38E
FF_E38F
FF_E390
PWM Reload High
Byte
PWMRH
PWMRL
FF
FF
00
97
98
99
PWM Reload Low
Byte
PWM 0 High Side
Duty Cycle
PWMH0DH
High Byte
FF_E391
PWM 0 High Side
Duty Cycle
Low Byte
PWMH0DL
PWML0DH
PWML0DL
PWMH1DH
PWMH1DL
PWML1DH
PWML1DL
PWMH2DH
PWMH2DL
PWML2DH
00
00
00
00
00
00
00
00
00
00
99
99
99
99
99
99
99
99
99
99
FF_E392
PWM 0 Low Side
Duty Cycle
High Byte
FF_E393
PWM 0 Low Side
Duty Cycle
Low Byte
FF_E394
PWM 1 High Side
Duty Cycle
High Byte
FF_E395
PWM 1 High Side
Duty Cycle
Low Byte
FF_E396
PWM 1 Low Side
Duty Cycle
High Byte
FF_E397
PWM 1 Low Side
Duty Cycle
Low Byte
FF_E398
PWM 2 High Side
Duty Cycle
High Byte
FF_E399
PWM 2 High Side
Duty Cycle
Low Byte
FF_E39A
Note: XX = undefined.
PWM 2 Low Side
Duty Cycle
High Byte
PS028706-0813
P R E L I M I N A R Y
Peripheral Address Map
Z16FMC Series Motor Control MCUs
Product Specification
28
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
Pulse Width Modulator (PWM) Base Address = FF_E380 (cont’d.)
FF_E39B
PWM 2 Low Side
Duty Cycle
Low Byte
PWML2DL
–
00
99
FF_E39C–FF_E3BF Reserved for PWM
DMA Block Base Address = FF_E400
DMA Request Selection Control
–
–
FF_E400
FF_E401
FF_E402
FF_E403
FF_E404-F
DMA0 Request Select DMA0REQSEL
DMA1 Request Select DMA1REQSEL
DMA2 Request Select DMA2REQSEL
DMA3 Request Select DMA3REQSEL
00
00
00
00
–
242
242
242
242
–
Reserved
–
DMA Channel 0 Base Address = FF_E410
FF_E410
FF_E411
FF_E412
DMA0 Control0
DMA0 Control1
DMA0CTL0
DMA0CTL1
DMA0TXLNH
00
00
00
245
245
246
DMA0 Transfer
Length High
FF_E413
DMA0 Transfer
Length Low
DMA0TXLNL
00
246
FF_E414
FF_E415
Reserved
–
–
–
DMA0 Destination
Address Upper
DMA0DARU
00
247
FF_E416
FF_E417
DMA0 Destination
Address High
DMA0DARH
DMA0DARL
00
00
247
247
DMA0 Destination
Address Low
FF_E418
FF_E419
Reserved
–
–
–
DMA0 Source
Address Upper
DMA0SARU
00
248
FF_E41A
FF_E41B
DMA0 Source
Address High
DMA0SARH
DMA0SARL
–
00
00
–
248
248
–
DMA0 Source
Address Low
FF_E41C
Reserved
Note: XX = undefined.
PS028706-0813
P R E L I M I N A R Y
Peripheral Address Map
Z16FMC Series Motor Control MCUs
Product Specification
29
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
DMA Channel 0 Base Address = FF_E410 (cont’d.)
FF_E41D
FF_E41E
FF_E41F
DMA0 List Address
Upper
DMA0LARU
DMA0LARH
DMA0LARL
00
00
00
249
249
249
DMA0 List Address
High
DMA0 List Address
Low
DMA Channel 1 Base Address = FF_E420
FF_E420
FF_E421
FF_E422
DMA1 Control0
DMA1 Control1
DMA1CTL0
DMA1CTL1
DMA1TXLNH
00
00
00
245
245
246
DMA1 Transfer
Length High
FF_E423
DMA1 Transfer
Length Low
DMA1TXLNL
00
246
FF_E424
FF_E425
Reserved
–
–
–
DMA1 Destination
Address Upper
DMA1DARU
00
247
FF_E426
FF_E427
DMA1 Destination
Address High
DMA1DARH
DMA1DARL
00
00
247
247
DMA1 Destination
Address Low
FF_E428
FF_E429
Reserved
–
–
–
DMA1 Source
Address Upper
DMA1SARU
00
248
FF_E42A
FF_E42B
DMA1 Source
Address High
DMA1SARH
DMA1SARL
00
00
248
248
DMA1 Source
Address Low
FF_E42C
FF_E42D
Reserved
–
–
–
DMA1 List Address
Upper
DMA1LARU
00
249
FF_E42E
DMA1 List Address
High
DMA1LARH
DMA1LARL
00
00
249
249
FF_E42F
DMA1 List Address
Low
Note: XX = undefined.
PS028706-0813
P R E L I M I N A R Y
Peripheral Address Map
Z16FMC Series Motor Control MCUs
Product Specification
30
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
DMA Channel 2 Base Address = FF_E430
FF_E430
FF_E431
FF_E432
DMA2 Control0
DMA2 Control1
DMA2CTL0
DMA2CTL1
DMA2TXLNH
00
00
00
245
245
246
DMA2 Transfer
Length High
FF_E433
DMA2 Transfer
Length Low
DMA2TXLNL
00
246
FF_E434
FF_E435
Reserved
–
–
–
DMA2 Destination
Address Upper
DMA2DARU
00
247
FF_E436
FF_E437
DMA2 Destination
Address High
DMA2DARH
DMA2DARL
00
00
247
247
DMA2 Destination
Address Low
FF_E438
FF_E439
Reserved
–
–
–
DMA2 Source
Address Upper
DMA2SARU
00
248
FF_E43A
FF_E43B
DMA2 Source
Address High
DMA2SARH
DMA2SARL
00
00
248
248
DMA2 Source
Address Low
FF_E43C
FF_E43D
Reserved
–
DMA2 List Address
Upper
DMA2LARU
DMA2LARH
DMA2LARL
00
00
00
249
FF_E43E
FF_E43F
DMA2 List Address
High
249
249
DMA2 List Address
Low
DMA Channel 3 Base Address = FF_E440
FF_E440
FF_E441
FF_E442
DMA3 Control0
DMA3 Control1
DMA3CTL0
DMA3CTL1
DMA3TXLNH
00
00
00
245
245
246
DMA3 Transfer
Length High
FF_E443
DMA3 Transfer
Length Low
DMA3TXLNL
00
246
Note: XX = undefined.
PS028706-0813
P R E L I M I N A R Y
Peripheral Address Map
Z16FMC Series Motor Control MCUs
Product Specification
31
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
DMA Channel 3 Base Address = FF_E440 (cont’d.)
FF_E444
FF_E445
Reserved
–
–
–
DMA3 Destination
Address Upper
DMA3DARU
00
247
FF_E446
FF_E447
DMA3 Destination
Address High
DMA3DARH
DMA3DARL
00
00
247
247
DMA3 Destination
Address Low
FF_E448
FF_E449
Reserved
–
–
–
DMA3 Source
Address Upper
DMA3SARU
00
248
FF_E44A
FF_E44B
DMA3 Source
Address High
DMA3SARH
DMA3SARL
00
00
248
248
DMA3 Source
Address Low
FF_E44C
FF_E44D
Reserved
–
–
–
DMA3 List Address
Upper
DMA3LARU
00
249
FF_E44E
FF_E44F
DMA3 List Address
High
DMA3LARH
DMA3LARL
00
00
249
249
DMA3 List Address
Low
Analog Block Base Address = FF_E500
ADC Base Address = FF_E500
FF_E500
ADC0 Control
Register
ADC0CTL
–
00
219
FF_E501
FF_E502
Reserved
–
–
ADC0 Data High Byte ADC0D_H
Register
XX
220
FF_E503
ADC0 Data Low Bit
Register
ADC0D_L
ADCSST
ADCST
XX
0F
3F
221
221
222
FF_E504
ADC Sample and
Settling Time Register
FF_E505
ADC Sample Hold
Time
Note: XX = undefined.
PS028706-0813
P R E L I M I N A R Y
Peripheral Address Map
Z16FMC Series Motor Control MCUs
Product Specification
32
Table 5. Register File Address Map (Continued)
Address (Hex)
Register Description Mnemonic
Reset (Hex)
Page
ADC Base Address = FF_E500 (cont’d.)
FF_E506
FF_E507
ADC Clock Prescale ADCCP
Register
00
222
ADC0 MAX Register ADC0MAX
00
–
223
–
FF_E508–FF_E50F Reserved
–
FF_E510
Comparator and Op- CMPOPC
Amp Control
00
226
FF_E511
FF_E512
Reserved
–
–
–
ADC Sample Timer
Capture High
ADCTCAPH
XX
224
FF_E513
ADC Sample Timer
Capture Low
ADCTCAPL
XX
224
Option Trim Registers Base Address = FF_FF00
FF_FF00–FF_FF24 Reserved for internal –
Zilog use
–
–
FF_FF25
FF_FF26
FF_FF27
IPO Trim 1
IPO Trim 2
IPOTRIM1
IPOTRIM2
ADCTRIM
XX
XX
XX
264
264
265
ADC Reference
Voltage Trim
Note: XX = undefined.
PS028706-0813
P R E L I M I N A R Y
Peripheral Address Map
Z16FMC Series Motor Control MCUs
Product Specification
33
Reset and Stop-Mode Recovery
The reset controller within the Z16FMC Series controls the RESET and Stop-Mode
Recovery operations. In a typical operation, the following events cause a Reset to occur:
•
•
•
•
•
•
Power-On Reset
Voltage Brown-Out
WDT time-out (when configured through the WDT_RES option bit to initiate a Reset)
External RESET pin assertion
OCD initiated Reset (OCDCTL[0] set to 1)
Fault detect logic
When the Z16FMC Series MCU is in STOP Mode, a Stop-Mode Recovery is initiated by
either of the following:
•
•
WDT time-out
GPIO port input pin transition on an enabled Stop-Mode Recovery source
Reset Types
The Z16FMC Series MCU provides two different types of Reset operation (System Reset
and Stop-Mode Recovery). The type of Reset is a function of both the current operating
mode of the Z16FMC device and the source of the Reset. Table 6 lists the types of Reset
and their operating characteristics.
Table 6. Reset and Stop-Mode Recovery Characteristics and Latency
Reset Characteristics and Latency
Peripheral
Control Registers
Reset Type
CPU
Reset Latency (Delay)
System Reset
Reset (as applicable)
Reset
A minimum of 66 internal precision
oscillator cycles.
Stop-Mode Recov- Unaffected, except RST- Reset
A minimum of 66 internal precision
oscillator cycles.
ery
SRC and OSCCTL regis-
ters
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System Reset
During a System Reset, the Z16FMC device is held in Reset for 66 cycles of the IPO. At
the beginning of Reset, all GPIO pins are configured as inputs. All GPIO programmable
pull-ups are disabled.
At the start of a System Reset, the motor control PWM outputs are forced to high-imped-
ance momentarily. When the option bits that control the off-state have been properly eval-
uated, the PWM outputs are forced to the programmed off-state.
During Reset, the ZNEO CPU and on-chip peripherals are nonactive; however, the IPO
and WDT oscillator continue to run. During the first 50 clock cycles, the internal option
bit registers are initialized, after which the system clock for the core and peripherals
begins operating. The ZNEO CPU and on-chip peripherals remain nonactive through the
next 16 cycles of the system clock, after which the internal reset signal is deasserted.
On Reset, control registers within the register file that have a defined reset value are
loaded with their reset values. Other control registers (including the Flags) and general-
purpose RAM are undefined following Reset. The CPU fetches the Reset vector at pro-
gram memory address 0004hand loads that value into the program counter. Program exe-
cution begins at the Reset vector address.
Table 7 lists the System Reset sources as a function of the operating mode. The following
text provides more detailed information about the individual Reset sources.
Note: A POR/VBO event always maintains priority over all other possible reset sources to
ensure that a full System Reset occurs.
Table 7. System Reset Sources and Resulting Reset Action
Operating Mode
System Reset Source
Action
NORMAL or HALT modes
POR/VBO
System Reset
WDT time-out when configured for System Reset
Reset
RESET pin assertion
Write RSTSCR[0] to 1
Fault detect logic reset
POR/VBO
System Reset
System Reset
System Reset
System Reset
System Reset
System Reset
STOP Mode
RESET pin assertion
Fault detect logic reset
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System Reset
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Power-On Reset
Each device in the Z16FMC Series contains an internal POR circuit. The POR circuit
monitors the supply voltage and holds the device in the Reset state until the supply voltage
reaches a safe operating level. After the supply voltage exceeds the POR voltage threshold
(VPOR) and has stabilized, the POR counter is enabled and counts 50 cycles of the IPO. At
this point, the system clock is enabled and the POR counter counts a total of 16 system
clock pulses. The device is held in the Reset state until the second POR counter sequence
has timed out. After the Z16FMC MCU exits the POR state, the CPU fetches the Reset
vector. Following POR, the POR status bit in the Reset Status and Control Register (see
page 39) is set to 1.
Figure 6 displays Power-on reset operation. For POR threshold voltage (VPOR), see
Table 63 on page 306.
VCC = 3.3 V
VPOR
VVBO
Program
Execution
VCC = 0.0 V
System Clock
Internal Precision
Oscillator
Oscillator
Start-up
Internal RESET
Signal
Option Bit
Counter Delay
System Clock
Counter Delay
Not to Scale
Figure 6. Power-On Reset Operation
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System Reset
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Voltage Brown-Out Reset
The Z16FMC MCU provides Low Voltage Brown-Out (VBO) protection. The VBO cir-
cuit senses the supply voltage when it drops to an unsafe level (below the VBO threshold
voltage) and forces the device into the Reset state. While the supply voltage remains
below the POR voltage threshold (VPOR), the VBO holds the device in the Reset state.
When the supply voltage exceeds the VPOR and is stabilized, the device progresses
through a full System Reset sequence, as described in the Power-On Reset section on page
35. Following Power-On Reset, the POR status bit in the Reset Source Register is set to 1.
Figure 7 displays Voltage Brown-Out operation. For VBO and POR threshold voltages
(VVBO and VPOR), see the Stop Mode Current Versus Vdd section on page 309.
The VBO circuit is either enabled or disabled during STOP Mode. Operation during STOP
Mode is controlled by the VBO_AO option bit. For information about configuring
VBO_AO, see the Option Bit chapter on page 260.
VCC = 3.3 V
VCC = 3.3 V
VPOR
VVBO
Program
Execution
Voltage
Brown-Out
Program
Execution
System Clock
Internal Precision
Oscillator
Internal RESET
Signal
Option Bit
System Clock
Counter Delay Counter Delay
Figure 7. Voltage Brown-Out Reset Operation
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System Reset
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Watchdog Timer Reset
If the device is in NORMAL Mode or HALT Mode, the WDT initiates a System Reset at
time-out if the WDT_RES option bit is set to 1. This setting is the default (unprogrammed)
setting of the WDT_RES option bit. The WDT status bit in the Reset Status and Control
Register (see page 39) is set to signify that the reset was initiated by the WDT.
External Pin Reset
The input-only RESET pin has a schmitt-triggered input, an internal pull-up, an analog fil-
ter and a digital filter to reject noise. After the RESET pin is asserted for at least four sys-
tem clock cycles, the device progresses through the System Reset sequence. While the
RESET input pin is asserted Low, the Z16FMC device continues to be held in the Reset
state. If the RESET pin is held Low beyond the System Reset time-out, the device exits the
Reset state 16 system clock cycles following RESET pin deassertion. If the RESET pin is
released before the System Reset time-out, the RESET pin is driven Low by the chip until
the completion of the time-out as described in the next section. In STOP Mode, the digital
filter is bypassed as the system clock is disabled.
Following a System Reset initiated by the external RESET pin, the EXT status bit in the
the Reset Status and Control Register (see page 39) is set to 1.
External Reset Indicator
During System Reset, the RESET pin functions as an open drain (active Low) RESET
mode indicator in addition to the input functionality. This reset output feature allows a
Z16FMC device to Reset other components to which it is connected, even if the Reset is
caused by internal sources such as POR, VBO, or WDT events and as an indication of
when the reset sequence completes.
After an internal reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in Table 6 on page 33 has elapsed.
User Reset
A System Reset is initiated by setting RSTSCR[0]. If the Write was caused by the OCD,
the OCD is not Reset.
Fault Detect Logic Reset
Fault detect circuitry exists to detect illegal state changes which is caused by transient
power or electrostatic discharge events. When such a fault is detected, a system reset is
forced. Following the system reset, the FLTD bit in the the Reset Status and Control Reg-
ister (see page 39) is set.
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Stop-Mode Recovery
STOP Mode is entered by execution of a STOP instruction by the CPU. For detailed infor-
mation about STOP Mode, see the Low-Power Modes chapter on page 40. During Stop-
Mode Recovery, the device is held in Reset for 66 cycles of the internal precision oscilla-
tor.
Stop-Mode Recovery only affects the contents of the Reset Status and Control Register
(see page 39) and the Oscillator Control Register (see page 301). Stop-Mode Recovery
does not affect any other values in the register file, including the stack pointer, register
pointer, flags, peripheral control registers and general-purpose RAM.
The ZNEO CPU fetches the Reset vector at program memory addresses 0004h–0007h
and loads that value into the program counter. Program execution begins at the Reset vec-
tor address. Following Stop-Mode Recovery, the stop bit in the Reset Status and Control
Register (see page 39) is set to 1. Table 8 lists the Stop-Mode Recovery sources and result-
ing actions. The following text provides more detailed information about each of the Stop-
Mode Recovery sources.
Table 8. Stop-Mode Recovery Sources and Resulting Action
Operating Mode
Stop-Mode Recovery Source
Action
STOP Mode
WDT time-out when configured for
Reset
Stop-Mode Recovery
WDT time-out when configured for
System Exception
Stop-Mode Recovery followed by WDT
System Exception
Data transition on any GPIO Port pin Stop-Mode Recovery
enabled as a Stop-Mode Recovery
source
Stop-Mode Recovery Using WDT time-out
If the WDT times out during STOP Mode, the device undergoes a Stop-Mode Recovery
sequence. In the Reset Status and Control Register (see page 39), the WDT and stop bits
are set to 1. If the WDT is configured to generate a System Exception on time-out, the
ZNEO CPU services the WDT System Exception following the normal Stop-Mode
Recovery sequence.
Stop-Mode Recovery Using a GPIO Port Pin Transition
Each of the GPIO port pins is configured as a Stop-Mode Recovery input source. If any
GPIO pin enabled as a Stop-Mode Recovery source, a change in the input pin value (from
High to Low or from Low to High) initiates Stop-Mode Recovery. The GPIO Stop-Mode
Recovery signals are filtered to reject pulses less than 10 ns (typical) in duration. In the
Reset Status and Control Register (see page 39), the stop bit is set to 1.
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Short pulses on the port pin initiate Stop-Mode Recovery without initiating in-
terrupts (if enabled for the pin).
Caution:
Reset Status and Control Register
The Reset Status and Control Register (RSTSCR), shown in Table 9, records the cause of
the most recent RESET or Stop-Mode Recovery. All status bits are updated on each
RESET or Stop-Mode Recovery event. Table 10 indicates the possible states of the Reset
status bits following a RESET or Stop-Mode Recovery event.
Table 9. Reset Status and Control Register (RSTSCR)
Bit
7
6
5
WDT
4
3
2
1
0
Field
RESET
R/W
POR
STOP
EXT
FLT
USR
Reserved USER_RST
See Table 10
R
R
R
R
R
R
R
W
ADDR
FF_E050h
The USER_RST bit in this register allows a software-controlled RESET of the part pin. It is a write-only bit
that causes a System Reset, with the result identified by the USR bit after being executed.
0 = No action.
1 = Causes System Reset.
Table 10. Reset Status Register Values Following Reset
Reset or Stop-Mode Recovery Event
Power-on reset.
POR STOP WDT EXT
FLT
0
USR
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
Reset using RESET pin assertion.
Reset using WDT time-out.
0
0
Reset from Fault detect logic.
1
Stop-Mode Recovery using GPIO pin transition.
Stop-Mode Recovery using WDT time-out.
0
0
Reset using software control; write a 1 to bit 0 of this
register.
0
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Reset Status and Control Register
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Low-Power Modes
Z16FMC Series products contain advanced integrated power-saving features. Power man-
agement functions are divided into three categories to include CPU operating modes,
peripheral power control and programmable option bits. The highest level of power reduc-
tion is provided through a combination of all functions.
STOP Mode
Execution of the CPU’s STOP instruction places the device into STOP Mode. In STOP
Mode, the operating characteristics are:
•
•
•
•
•
IPO is stopped; XIN and XOUT pins are driven to VSS
System clock is stopped
The CPU is stopped
Program counter (PC) stops incrementing
If enabled for operation during STOP Mode, the WDT and its internal RC oscillator
continue to operate
•
•
If enabled for operation in STOP Mode through the associated option bit, the VBO pro-
tection circuit continues to operate
All other on-chip peripherals are nonactive
To minimize current in STOP Mode, all GPIO pins that are configured as digital inputs
must be driven to one of the supply rails (VDD or VSS), the VBO protection must be dis-
abled and WDT must be disabled. The device is brought out of STOP Mode using Stop-
Mode Recovery. For detailed information about Stop-Mode Recovery, see the Reset and
Stop-Mode Recovery chapter on page 33.
To prevent excess current consumption when using an external clock source in
STOP Mode, the external clock must be disabled.
Caution:
HALT Mode
Execution of the CPU’s HALT instruction places the device into HALT Mode, which dem-
onstrates the following operating characteristics:
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•
•
•
•
•
•
The System Clock is enabled and continues to operate
The CPU is stopped
The PC stops incrementing
The WDT’s internal RC oscillator continues to operate
If enabled, the WDT continues to operate
All other on-chip peripherals continue to operate
Any of the following operations can cause the CPU to exit HALT Mode:
•
•
•
•
•
•
An Interrupt or System Exception
A WDT time-out (System Exception or Reset)
A Power-On reset
A VBO reset
An external RESET pin assertion
An instantaneous Halt-Mode Recovery
To minimize current in HALT Mode, all GPIO pins which are configured as inputs must
be driven to one of the supply rails (VDD or VSS).
Peripheral-Level Power Control
On-chip peripherals in the Z16FMC Series automatically enter a low-power mode after
Reset and whenever the peripheral is disabled. To minimize power consumption, unused
peripherals must be disabled. See the individual peripheral chapters for specific register
settings to enable or disable the peripheral.
Power Control Option Bit
User programmable option bits are available in some versions of the Z16FMC devices that
enable very low power STOP Mode operation. These options include disabling the VBO
protection circuits and disabling the WDT oscillator. For detailed description of the user
options that affect power management, see the Option Bit chapter on page 260.
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General-Purpose Input/Output
The Z16FMC products contain general-purpose input/output (GPIO) pins arranged as
Ports A–H. Each port contains control and data registers. The GPIO control registers are
used to determine data direction, open-drain, output drive current and alternate pin func-
tions. Each port pin is individually programmable.
GPIO Port Availability
Table 11 lists the available GPIO port pins.
Table 11. GPIO Port Availability by Device
Device
Pin Count
Port A Port B Port C Port D Port E Port F Port G Port H
[7:0] [7:0] [7:0] [7:0] [7:0] [1] [1] [3:0]
Z16FMC
64-pin
Architecture
Figure 8 displays a simplified block diagram of a GPIO port pin. This figure does not,
however, display the ability to accommodate alternate functions or variable port current
drive strength.
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VDD
Pull-up Enable
Port Input
Data Register
Schmitt Trigger
Q
D
System
Clock
VDD
Port Output Control
Port Output
Data Register
Data
Bus
D
Q
Port
Pin
System
Clock
Port Data Direction
GND
Figure 8. GPIO Port Pin Block Diagram
GPIO Alternate Functions
Many GPIO port pins are used for GPIO and to provide access to the on-chip peripheral
functions such as timers and serial communication devices. The Port A–H Alternate Func-
tion registers configure these pins for either GPIO or alternate function operation. When a
pin is configured for alternate function, control of the port pin direction (I/O) is passed
from the Port A–H data direction registers to the alternate function assigned to this pin.
Table 12 lists the alternate functions associated with each port pin.
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Table 12. Port Alternate Function Mapping
Port
Pin
Alternate Function 1
T0IN/T0OUT
T0OUT
DE0
Alternate Function 2
Alternate Function 3
Port A
PA0
T0INPB
PA1
PA2
FAULT1
FAULT0
PA3
CTS0
PA4
RXD0
PA5
TXD0
PA6
SCL
PA7
SDA
Port B
Port C
Port D
PB0/T0IN0
PB1/T0IN1
PB2/T0IN2
PB3
ANA0
ANA1
ANA2
ANA3/OPOUT
ANA4
PB4
PB5
ANA5
PB6
ANA6/OPINP/CINN
ANA7/OPINN
T1IN/T1OUT
T1OUT
SS
PB7
PC0
CINN
PC1
COMPOUT
PC2
PC3
SCK
PC4
MOSI
PC5
MISO
PC6
T2IN/T2OUT
T2OUT
PWMH1
PWML1
PWMH2
DE1
PWMH0
PWML0
PC7
PD0
PD1
PD2
PD3
PD4
RXD1
PD5
TXD1
PD6
CTS1
PD7
PWML2
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Table 12. Port Alternate Function Mapping (Continued)
Port
Pin
Alternate Function 1
Alternate Function 2
Alternate Function 3
Port E
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PF7
PG3
PH0
PH1
PH2
PH3
Port F
Port G
Port H
ANA8
ANA9
ANA10
ANA11/CPINP
GPIO Interrupts
Many of the GPIO port pins are used as interrupt sources. Some port pins are configured
to generate an interrupt request on either the rising edge or falling edge of the pin input
signal. Other port pin interrupts generate an interrupt when any edge occurs (both rising
and falling). For more information about interrupts using the GPIO pins, see the Interrupt
Controller chapter on page 54.
GPIO Control Register Definitions
The section that follows describes the functions of the GPIO control registers.
Port A–H Input Data Register
Reading from the Port A–H Input Data registers, shown in Table 13, returns the sampled
values from the corresponding port pins. The Port A–H Input Data registers are read-only.
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Table 13. Port A–H Input Data Registers (PxIN)
Bit
7
PIN7
X
6
PIN6
X
5
PIN5
X
4
PIN4
X
3
PIN3
X
2
PIN2
X
1
PIN1
X
0
PIN0
X
Field
RESET
R/W
R
R
R
R
R
R
R
R
ADDR
FF_E100, FF_E110, FF_E120, FF_E130, FF_E140,
FF_E150, FF_E160, FF_E170, FF_E180, FF_E190
Bit
Description
[7:0]
PINx
Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
Note: x indicates register bits in the range 7 through 0.
Port A–H Output Data Registers
The Port A–H Output Data registers, shown in Table 14, write output data to the pins.
Table 14. Port A–H Output Data Registers (PxOUT)
Bit
7
POUT7
0
6
POUT6
0
5
POUT5
0
4
POUT4
0
3
POUT3
0
2
POUT2
0
1
POUT1
0
0
POUT0
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E101, FF_E111, FF_E121, FF_E131, FF_E141,
FF_E151, FF_E161, FF_E171, FF_E181, FF_E191
Bit
Description
[7:0]
POUTx
Port Output Data
These bits contain the data to be driven out from the port pins. The values are only driven if
the corresponding pin is configured as an output and the pin is not configured for alternate
function operation.
0 = Drive a logical 0 (Low).
1 = Drive a logical 1 (High). High value is not driven if the drain has been disabled by setting
the corresponding port output control register bit to 1.
Note: x indicates register bits in the range 7 through 0.
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Port A–H Data Direction Registers
The Port A–H Data Direction registers, shown in Table 15, configure the specified port
pins as either inputs or outputs.
Table 15. Port A–H Data Direction Registers (PxDD)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DD7
1
DD6
1
DD5
1
DD4
1
DD3
1
DD2
1
DD1
1
DD0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E102, FF_E112, FF_E122, FF_E132, FF_E142,
FF_E152, FF_E162, FF_E172, FF_E182, FF_E192
Bit
Description
[7:0]
DDx
Data Direction
These bits control the direction of the associated port pin. Port alternate function operation
overrides the Data Direction Register setting.
0 = Output. Data in the Port A–H Output Data Register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–H Input Data Register.
The output driver is high impedance.
Note: x indicates register bits in the range 7 through 0.
Port A–H High Drive Enable Registers
Writing a 1 to the bits in the Port A–H High Drive Enable registers, shown in Table 16, con-
figures the specified port pins for high current output drive operation. The Port A–H High
Drive Enable registers affect the pins directly. As a result, alternate functions are also
affected.
Table 16. Port A–H High Drive Enable Registers (PxHDE)
Bit
7
PHDE7
0
6
PHDE6
0
5
PHDE5
0
4
PHDE4
0
3
PHDE3
0
2
PHDE2
0
1
PHDE1
0
0
PHDE0
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E103, FF_E113, FF_E123, FF_E133, FF_E143,
FF_E153, FF_E163, FF_E173, FF_E183, FF_E193
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Z16FMC Series Motor Control MCUs
Product Specification
48
Bit
Description
[7:0]
PHDEx
Port High Drive Enable
0 = The port pin is configured for standard output current drive.
1 = The port pin is configured for high output current drive.
Note: x indicates register bits in the range 7 through 0.
Port A–H Alternate Function High and Low Registers
The Port A–H Alternate Function High and Low registers, shown in Tables 17 and 18,
select the alternate functions for the selected pins. To determine the alternate function
associated with each port pin, see the GPIO Alternate Functions section on page 43. When
changing alternate functions, Zilog recommends using word data mode instructions to per-
form simultaneous writes to the Port Alternate Function High and Low registers.
Do not enable alternate functions for GPIO port pins which do not also offer an
associated alternate function. Failure to follow this guideline will result in unde-
fined operation.
Caution:
Table 17. Port A–H Alternate Function High Registers (PxAFH)
Bit
7
AFH[7]
6
AFH[6]
0
5
AFH[5]
0
4
AFH[4]
0
3
AFH[3]
0
2
AFH[2]
0
1
AFH[1]
0
0
AFH[0]
0
Field
RESET
R/W
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E104, FF_E124, FF_E134, FF_E174
Table 18. Port A–H Alternate Function Low Registers (PxAFL)
Bit
7
AFL[7]
0
6
AFL[6]
0
5
AFL[5]
0
4
AFL[4]
0
3
AFL[3]
0
2
AFL[2]
0
1
AFL[1]
0
0
AFL[0]
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E105, FF_E115, FF_E125, FF_E135, FF_E155, FF_E165, FF_E175, FF_E195
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49
Table 19. Alternate Function Enabling
AFH[x]
AFL[x] Priority
0
0
1
1
0
1
0
1
No Alternate Function enabled.
Alternate Function 1 enabled.
Alternate Function 2 enabled.
Alternate Function 3 enabled.
Note: x indicates register bits in the range 0 through 7.
Port A–H Output Control Registers
Writing a 1 to the bits in the Port A–H Output Control registers, shown in Table 20, con-
figures the specified port pins for open-drain operation. These registers affect the pins
directly and, as a result, alternate functions are also affected. Enabling the I2C controller
automatically configures the SCL and SDA pins as open-drain; independent of the setting
in the output control registers that have the SCL and SDA alternate functions.
Table 20. Port A–H Output Control Registers (PxOC)
Bit
7
POC7
0
6
POC6
0
5
POC5
0
4
POC4
0
3
POC3
0
2
POC2
0
1
POC1
0
0
POC0
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E106, FF_E116, FF_E126, FF_E136, FF_E146,
FF_E156, FF_E166, FF_E176, FF_E186, FF_E196
Bit
Description
[7:0]
POCx
Port Output Control
These bits function independently of the alternate function bits and disable the drains if set to
1.
0 = The drains are enabled for any output mode.
1 = The drain of the associated pin is disabled (open-drain mode).
Note: x indicates register bits in the range 7 through 0.
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Z16FMC Series Motor Control MCUs
Product Specification
50
Port A–H Pull-Up Enable Registers
Writing a 1 to the bits in the Port A–H Pull-Up Enable registers, shown in Table 21,
enables a weak internal resistive pull-up on the specified port pins. These registers affect
the pins directly and, as a result, alternate functions are also affected.
Table 21. Port A–H Pull-Up Enable Registers (PxPUE)
Bit
7
PUE7
0
6
PUE6
0
5
PUE5
0
4
PUE4
0
3
PUE3
0
2
PUE2
0
1
PUE1
0
0
PUE0
0
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E107, FF_E117, FF_E127, FF_E137, FF_E147,
FF_E157, FF_E167, FF_E177, FF_E187, FF_E197
Bit
Description
[7:0]
PUEx
Port Pull-Up Enable
These bits function independently of the alternate function bit and enable the weak pull-up if
set to 1.
0 = The weak pull-up on the port pin is disabled.
1 = The weak pull-up on the port pin is enabled.
Note: x indicates register bits in the range 7 through 0.
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Z16FMC Series Motor Control MCUs
Product Specification
51
Port A–H Stop-Mode Recovery Source Enable Registers
Writing a 1 to the bits in the Port A–H Stop-Mode Recovery Source Enable registers,
shown in Table 22, configures the specified port pins as a Stop-Mode Recovery source.
During STOP Mode, any logic transition on a port pin enabled as a Stop-Mode Recovery
source initiates Stop-Mode Recovery.
Table 22. Port A–H Stop-Mode Recovery Source Enable Registers (PxSMRE)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMRE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E108, FF_E118, FF_E128, FF_E138, FF_E148,
FF_E158, FF_E168, FF_E178, FF_E188, FF_E198
Bit
Description
[7:0]
PSMREx
Port Stop-Mode Recovery Source Enable
0 = The port pin is not configured as a Stop-Mode Recovery source. Transitions on this pin dur-
ing STOP Mode do not initiate Stop-Mode Recovery.
1 = The port pin is configured as a Stop-Mode Recovery source. Any logic transition on this pin
during STOP Mode initiates Stop-Mode Recovery.
Note: x indicates register bits in the range 7 through 0.
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Z16FMC Series Motor Control MCUs
Product Specification
52
Port A IRQ MUX1 Register
The Port IRQ MUX1 Register, shown in Table 23, selects either Port A/D pins or the com-
parator/DBG channel as interrupt sources.
Table 23. Port A IRQ MUX1 Register (PAIMUX1)
Bit
7
CPIMUX
0
6
5
4
3
2
1
0
DBGIMUX
0
Field
RESET
R/W
Reserved
FF_E10C
0
0
0
0
0
0
R/W
R/W
R
R
R
R
R
R/W
ADDR
Bit
Description
[7]
CPIMUX
Comparator Interrupt MUX
0 = Select Port A7/D7 based upon the Port A IRQ Edge Register as the interrupt source.
1 = Select the comparator as the interrupt source.
[6:1]
Reserved
These bits are reserved and must be programmed to 000000.
[0]
Debug Interrupt MUX
DBGIMUX 0 = Select Port A0/D0 based on the Port A IRQ Edge Register as the interrupt source.
1 = Select the DBG as the interrupt source.
Port A IRQ MUX Register
The Port IRQ MUX Register, shown in Table 24, selects either Port A or Port D pins as
interrupt sources.
Table 24. Port A IRQ MUX Register (PAIMUX)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
PAIMUX7 PAIMUX6 PAIMUX5 PAIMUX4 PAIMUX3 PAIMUX2 PAIMUX1 PAIMUX0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E10E
Bit
Description
[7:0]
PAIMUXx
Port A/D Interrupt Source
0 = Select Port Ax as the interrupt source.
1 = Select Port Dx as the interrupt source.
Note: x indicates register bits in the range 7 through 0.
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Z16FMC Series Motor Control MCUs
Product Specification
53
Port A IRQ Edge Register
The Port IRQ Edge Register, shown in Table 25, selects either positive or negative edge as
the port pin interrupt sources.
Table 25. Port A IRQ Edge Register (PAIEDGE)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
PAIEDGE7 PAIEDGE6 PAIEDGE5 PAIEDGE4 PAIEDGE3 PAIEDGE2 PAIEDGE1 PAIEDGE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E10F
Bit
Description
[7:0]
PAIEDGEx
Port A/D Interrupt Edge
0 = Select Port A/D pin negedge as the interrupt source.
1 = Select Port A/D pins posedge as the interrupt source.
Note: x indicates register bits in the range 7 through 0.
Port C IRQ MUX Register
The Port C IRQ MUX Register, shown in Table 26, selects either Port C pins or the DMA
channels as interrupt sources.
Table 26. Port C IRQ MUX Register (PCIMUX)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
PCIMUX3 PCIMUX2 PCIMUX1 PCIMUX0
RESET
R/W
0
0
0
0
0
0
0
0
R
R
R
R
R/W
R/W
R/W
R/W
Address
FF_E12E
Bit
Description
Reserved
[7:4]
These bits are reserved and must be programmed to 0000.
[3:0]
PCIMUXx
Port C Interrupt MUX
0 = Select DMA Chan[3:0] as the interrupt source.
1 = Select port C pins as the interrupt source.
Note: x indicates register bits in the range 3 through 0.
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Z16FMC Series Motor Control MCUs
Product Specification
54
Interrupt Controller
The Z16FMC Series interrupt controller prioritizes interrupt requests from on-chip periph-
erals and the GPIO port pins. The features of the interrupt controller includes:
•
Flexible GPIO interrupts:
–
–
Eight selectable rising and falling edge GPIO interrupts
Four dual-edge interrupts
•
•
Three levels of individually programmable interrupt priority
Software Interrupt Requests (IRQ) assertion
The IRQs allow peripheral devices to suspend CPU operation in an orderly manner and
force the CPU to start an ISR. Usually this service routine is involved with exchange of
data, status information, or control information between the CPU and the interrupting
peripheral. When the service routine is completed, the CPU returns to the operation from
which it was interrupted.
System exceptions are nonmaskable requests which allow critical system functions to sus-
pend CPU operation in an orderly manner and force the CPU to start a service routine.
Usually this service routine tries to determine how critical the exception is. When the ser-
vice routine is complete, the CPU returns to the operation from which it was interrupted.
Z16FMC MCUs support both vectored and polled interrupt handling. For polled inter-
rupts, the interrupt control has no effect on operation. For more information about inter-
rupt servicing by this device’s ZNEO CPU core, refer to the ZNEO CPU User Manual
(UM0188), available free for download from the Zilog website.
Interrupt Vector Listing
Table 27 lists all of the available interrupts in order of priority.
Table 27. Interrupt Vectors in Order of Priority
Program Memory Programmable
Priority
Vector Address
Priority?
Interrupt Source
Reset (not an interrupt)
System Exceptions
Reserved
Highest
0004h
No
0008h
No
000Ch
No
0010h
Yes
Timer 2
0014h
Yes
Timer 1
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Z16FMC Series Motor Control MCUs
Product Specification
55
Table 27. Interrupt Vectors in Order of Priority (Continued)
Program Memory Programmable
Priority
Vector Address
Priority?
Interrupt Source
Lowest
0018h
Yes
Timer 0
001Ch
Yes
UART 0 receiver
UART 0 transmitter
0020h
Yes
2
0024h
Yes
I C
0028h
Yes
SPI
002Ch
Yes
ADC0
0030h
Yes
Port A7 or Port D7, rising or falling input edge or
Comparator output rising and falling edge (source
selected in PortA IRQ MUX registers)
0034h
0038h
003Ch
0040h
0044h
0048h
004Ch
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Port A6 or Port D6, rising or falling input edge
Port A5 or Port D5, rising or falling input edge
Port A4 or Port D4, rising or falling input edge
Port A3 or Port D3, rising or falling input edge
Port A2 or Port D2, rising or falling input edge
Port A1 or Port D1, rising or falling input edge
Port A0 or Port D0, rising or falling input edge or OCD
Interrupt (source selected in PortA IRQ MUX regis-
ters)
0050h
0054h
0058h
005Ch
0060h
0064h
0068h
006Ch
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PWM Timer
UART 1 Receiver
UART 1 Transmitter
PWM Fault
Port C3, both input edges/DMA 3
Port C2, both input edges/DMA 2
Port C1, both input edges/DMA 1
Port C0, both input edges/DMA 0
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Interrupt Vector Listing
Z16FMC Series Motor Control MCUs
Product Specification
56
The most significant byte (MSB) of the four-byte interrupt vector is not used. The vector
is stored in the three least significant bytes (LSB) of the vector, as shown in Table 28.
Table 28. Interrupt Vector placement
Vector
Byte
Data
0
1
2
3
Reserved
IRQ Vector[23:16]
IRQ Vector[15:8]
IRQ Vector[7:0]
Architecture
Figure 9 displays a block diagram of the interrupt controller.
High
Port Interrupts
Priority
Vector
Priority
Mux
IRQ Request
Medium
Priority
Internal Interrupts
Low
Priority
Figure 9. Interrupt Controller Block Diagram
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Architecture
Z16FMC Series Motor Control MCUs
Product Specification
57
Operation
This section discusses the operational aspects of the Z16FMC Series interrupts, and pres-
ents tabled bit descriptions for the interrupt request, enable, and exception registers.
Master Interrupt Enable
The master interrupt enable bit in the Flag Register globally enables or disables interrupts.
This bit has been moved to the Flag Register (bit 0). Thus, any time the register is loaded,
it changes the state of the IRQE bit. For the IRET instruction the bit is set based on what
has been pushed on the stack.
Interrupts are globally enabled by any of the following actions:
•
•
Execution of an Enable Interrupt (EI) instruction
Writing a 1 to the IRQE bit in the Flag Register
Interrupts are globally disabled by any of the following actions:
•
•
•
•
•
•
Execution of a Disable Interrupt (DI) instruction
CPU acknowledgement of an interrupt service request from the interrupt controller
Writing a 0 to the IRQE bit in the Flag Register
Reset
Execution of a TRAP instruction
All System Exceptions
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all the
interrupts are enabled with identical interrupt priority (for example, all interrupts enabled
as Level 2 interrupts), the interrupt priority is assigned from highest to lowest as specified
in Table 27 on page 54. Level 3 interrupts always have higher priority than Level 2 inter-
rupts, which in turn, always have higher priority than Level 1 interrupts. Within each inter-
rupt priority levels (Level 1, Level 2, or Level 3), priority is assigned as specified in
Table 27. Reset and System Exceptions have the highest priority.
System Exceptions
System Exceptions are generated for stack overflow, illegal instructions, divide-by-zero,
and divide overflow, etc. The System Exceptions are not affected by the IRQE and share a
single vector.
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Each exception has a bit in the system exception status register. When a system exception
occurs it pushes the program counter and the flags on the stack, fetches the system excep-
tion vector from 000008h(similar to a IRQ) and the bit associated with that exception is
set in the status register. Additional exceptions from the same source are blocked until the
status bit of the particular exception is cleared by writing a 1 to that status bit. Other types
of exceptions occur while servicing an exception. When this happens the processor again
vectors to the system exception vector and sets the associated exception status bit. The ser-
vice routine would then have to respond to the new exception.
Upon illegal instruction, the program counter and flags are pushed onto the stack only
once. If the associated exception bit is not reset, the program counter and flags are not
pushed a second time.
Note:
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period (sin-
gle pulse). When the interrupt request is acknowledged by the CPU, the corresponding bit
in the Interrupt Request Register is cleared until the next interrupt occurs. Writing a 1 to
the corresponding bit in the Interrupt Request Register clears the interrupt request.
Program code generates interrupts directly. Writing a 1 to the appropriate bit in the Inter-
rupt Request Set Register triggers an interrupt (assuming that interrupts are enabled).
When the interrupt request is acknowledged by the CPU, the bit in the Interrupt Request
Register is automatically cleared to 0.
System Exception Status Registers
When a System Exception occurs, the System Exception Status registers are read to deter-
mine which system exception occurred. These registers can be read individually or as a
16-bit quantity.
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Product Specification
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Table 29. System Exception Register High (SYSEXCPH)
Bit
7
6
5
DIV0
0
4
3
ILL
2
1
Reserved
0
0
Field
RESET
R/W
SPOVF
0
PCOVF
0
DIVOVF
0
0
0
0
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
ADDR
FF_E020h
Bit
Description
[7]
Stack Pointer Overflow
SPOVF If this bit is 1, a stack pointer overflow exception occurred. Writing a 1 to this bit clears it to 0.
[6] Program Counter Overflow
PCOVF If this bit is 1, a program counter overflow exception occurred. Writing a 1 to this bit clears it to
0.
[5]
DIV0
Divide by Zero
If this bit is 1, a divide operation was executed where the denominator was zero. Writing a 1 to
this bit clear it to 0.
[4]
Divide Over Flow
DIVOVF If this bit is 1, a divide overflow occurred. A divide overflow happens when the result is greater
than FFFFFFFFh. Writing a 1 to this bit clears it to 0.
[3]
ILL
Illegal Instruction
If this bit is 1, an illegal instruction occurred. Writing a 1 to this bit clears it to 0.
[2:0]
Reserved
These bits are reserved and must be programmed to 000.
Table 30. System Exception Register Low (SYSEXCPL)
Bit
7
6
5
Reserved
0
4
3
2
1
0
WDT
0
Field
RESET
R/W
WDTOSC PRIOSC
0
0
0
0
0
0
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
ADDR
FF_E021h
Bit
Description
Reserved
[7:3]
These bits are reserved and must be programmed to 00000.
[2]
WDTOSC
WDT Oscillator Fail
If this bit is 1, a WDT oscillator fail exception occurred. Writing a 1 to this bit clears it to 0.
[1]
PRIOSC
Primary Oscillator Fail
If this bit is 1, a primary oscillator fail exception occurred. Writing a 1 to this bit clears it to 0.
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Product Specification
60
Bit
Description (Continued)
Watchdog Timer Interrupt
[0]
WDT
If this bit is 1, a WDT exception occurred. Writing a 1 to this bit clears it to 0.
Last IRQ Register
When an interrupt occurs, the 5th bit value of the interrupt vector is stored in the Last IRQ
Register. This register allows the software to determine which interrupt source was last
serviced. It is used by RTOS which have a single interrupt entry point. To implement this
the software must set all interrupt vectors to the entry point address. The entry point ser-
vice routine then reads this register to determine which source caused the interrupt or
exception and respond accordingly.
Table 31. Last IRQ Register (LASTIRQ)
Bit
7
6
5
4
IRQADR
0
3
2
1
0
Field
RESET
R/W
Always 0
Always 00
0
0
0
0
1
0
0
R
R/W
R/W
R/W
R/W
R/W
R
R
ADDR
FF_E023h
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) Register, shown in Table 32, stores the interrupt requests
for both vectored and polled interrupts. When a request is presented to the interrupt con-
troller, the corresponding bit in the IRQ0 Register becomes 1. If interrupts are globally
enabled (vectored interrupts), the interrupt controller passes an interrupt request to the
CPU. If interrupts are globally disabled (polled interrupts), the CPU reads the Interrupt
Request 0 Register to determine if any interrupt requests are pending.
Writing a 1 to the bits in this register clears the interrupt. Clearing the individual flag bits
of the IRQ0 Register requires writing a 1 by a means other than using a logical OR; other-
wise, unexpected results can occur.
Example. If bit 5 must be cleared, then either of the following instructions will clear IRQ0
bit 5:
IRQ0 &= ~0xDF;
or
IRQ0 = 0x20;
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The bits in this register are set by writing a 1 to the Interrupt Request 0 Set Register
(IRQ0SET) at address FF_E031h.
Table 32. Interrupt Request 0 Register (IRQ0) and Interrupt Request 0 Set Register (IRQ0SET)
Bit
7
T2I
6
T1I
5
T0I
4
3
2
I2CI
0
1
SPII
0
0
ADCI
0
Field
RESET
R/W
U0RXI
0
U0TXI
0
0
0
0
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
ADDR
Field
RESET
R/W
FF_E030h
T2I
0
T1I
0
T0I
0
U0RXI
U0TXI
I2CI
0
SPII
0
ADCI
0
0
0
W
W
W
W
W
W
W
W
ADDR
FF_E031h
Note: IRQ0SET at address FF_E031h is write only and used to set the interrupts identified.
Bit
Description
[7]
T2I
Timer 2 Interrupt Request
0 = No interrupt request is pending for timer 2.
1 = An interrupt request from timer 2 is awaiting service. Writing a 1 to this bit resets it to 0.
[6]
T1I
Timer 1 Interrupt Request
0 = No interrupt request is pending for timer 1.
1 = An interrupt request from timer 1 is awaiting service. Writing a 1 to this bit resets it to 0.
[5]
T0I
Timer 0 Interrupt Request
0 = No interrupt request is pending for timer 0.
1 = An interrupt request from timer 0 is awaiting service. Writing a 1 to this bit resets it to 0.
[4]
U0RXI
UART 0 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 0 receiver.
1 = An interrupt request from the UART 0 receiver is awaiting service. Writing a 1 to this bit
resets it to 0.
[3]
U0TXI
UART 0 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 0 transmitter.
1 = An interrupt request from the UART 0 transmitter is awaiting service. Writing a 1 to this bit
resets it to 0.
2
[2]
I C Interrupt Request
2
I2CI
0 = No interrupt request is pending for the I C.
2
1 = An interrupt request from the I C is awaiting service. Writing a 1 to this bit resets it to 0.
[1]
SPII
SPI Interrupt Request
0 = No interrupt request is pending for the SPI.
1 = An interrupt request from the SPI is awaiting service. Writing a 1 to this bit resets it to 0.
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Z16FMC Series Motor Control MCUs
Product Specification
62
Bit
Description (Continued)
[0]
ADCI
ADC Interrupt Request
0 = No interrupt request is pending for ADC.
1 = An interrupt request from ADC is awaiting service. Writing a 1 to this bit resets it to 0.
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) Register, shown in Table 33, stores interrupt requests for
both vectored and polled interrupts. When a request is presented to the interrupt controller,
the corresponding bit in the IRQ1 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the CPU. If
interrupts are globally disabled (polled interrupts), the CPU reads the Interrupt Request 1
Register to determine, if any interrupt requests are pending. Writing a 1 to the bits in this
register clears the interrupt. The bits of this register are set by writing a 1 to the Interrupt
Request 1 Set Register (IRQ1SET) at address FF_E035h.
Table 33. Interrupt Request 1 Register (IRQ1) and Interrupt Request 1 Set Register (IRQ1SET)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
PAD7I
0
PAD6I
0
PAD5I
0
PAD4I
0
PAD3I
0
PAD2I
0
PAD1I
0
PAD0I
0
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
ADDR
FF_E034h
Field
PAD7I
PAD6I
PAD5I
PAD4I
PAD3I
PAD2I
PAD1I
PAD0I
RESET
R/W
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
ADDR
FF_E035h
Note: IRQ1SET at address FF_E035h is write only and used to set the interrupts identified.
Bit
Description
[7:0]
PADxI
Port A/D Pin x Interrupt Request
PAD7I and PAD0I have interrupt sources other than Port A and Port D as selected by the Port
A IRQ MUX registers. PAD7I is configured to provide the comparator interrupt. PAD0I is config-
ured to provide the OCD interrupt.
0 = No interrupt request is pending for GPIO port A/D pin x.
1 = An interrupt request from GPIO port A/D pin x is awaiting service. Writing a 1 to these bits
resets them to 0.
Note: x indicates register bits in the range 7 to 0.
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Z16FMC Series Motor Control MCUs
Product Specification
63
Note: These bits are set any time the selected port is toggled. The setting of these bits is not
affected by the associated interrupt enable bits.
Interrupt Request 2 Register
The Interrupt Request 2 Register (IRQ2), shown in Table 34, stores interrupt requests for
both vectored and polled interrupts. When a request is presented to the interrupt controller,
the corresponding bit in the IRQ2 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the CPU. If
interrupts are globally disabled (polled interrupts), the CPU reads the Interrupt Request 1
Register to determine, if any interrupt requests are pending. Writing a 1 to the bits in this
register clears the interrupt. The bits in this register are set by writing a 1 to the Interrupt
Request 2 Set Register (IRQ2SET) at address FF_E039h.
Table 34. Interrupt Request 2 Register (IRQ2) and Interrupt Request 2 Set Register (IRQ2SET)
Bit
7
6
5
4
3
2
1
0
Field
PWMTI
U1RXI
U1TXI
PWMFI
PC3I/
PC2I/
PC1I/
PC0I/
DMA3I
DMA2I
DMA1I
DMA0I
RESET
R/W
0
0
0
0
0
0
0
0
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
ADDR
FF_E038h
Field
PWMTI
U1RXI
U1TXI
PWMFI
PC3I/
PC2I/
PC1I/
PC0I/
DMA3I
DMA2I
DMA1I
DMA0I
RESET
R/W
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
ADDR
FF_E039h
Note: IRQ2SET at address FF_E039h is write only and used to set the interrupts identified.
Bit
Description
[7]
PWM Timer Interrupt Request
PWMTI 0 = No interrupt request is pending for the PWM timer.
1 = An interrupt request from the PWM timer is awaiting service. Writing a 1 to this bit resets it
to 0.
Note: x indicates register bits in the range 3 to 0.
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Z16FMC Series Motor Control MCUs
Product Specification
64
Bit
Description (Continued)
[6]
U1RXI
UART 1 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 1 receiver.
1 = An interrupt request from the UART 1 receiver is awaiting service. Writing a 1 to this bit
resets it to 0.
[5]
U1TXI
UART 1 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 1 transmitter.
1 = An interrupt request from the UART 1 transmitter is awaiting service. Writing a 1 to this bit
resets it to 0.
[4]
PWM Fault Interrupt Request
PWMFI 0 = No interrupt request is pending for the PWM fault.
1 = An interrupt request from the PWM fault is awaiting service. Writing a 1 to this bit resets it
to 0.
[3:0]
PCxI/
DMAxI
Port C Pin x or DMA x Interrupt Request
0 = No interrupt request is pending for GPIO port C pin x or DMA x.
1 = An interrupt request from GPIO port C pin x or DMAx is awaiting service. Writing a 1 to this
bit resets it to 0.
Note: x indicates register bits in the range 3 to 0.
IRQ0 Enable High and Low Bit Registers
The IRQ0 Enable High and Low Bit registers, shown in Tables 36 and 37, form a priority-
encoded enabling for interrupts in the Interrupt Request 0 Register. Priority is generated
by setting bits in each register. Table 35 describes the priority control for IRQ0.
Table 35. IRQ0 Enable and Priority Encoding
IRQ0ENH[x]
IRQ0ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Nominal
High
Note: x indicates the register bits from 0 through 7.
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Table 36. IRQ0 Enable High Bit Register (IRQ0ENH)
Bit
7
T2ENH
0
6
T1ENH
0
5
T0ENH
0
4
3
2
1
0
Field
RESET
R/W
U0RENH U0TENH I2CENH
SPIENH ADCENH
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E032H
Bit
Description
[7]
T2ENH
Timer 2 Interrupt Request Enable High Bit
Timer 0 Interrupt Request Enable High Bit
Timer 0 Interrupt Request Enable High Bit
[6]
T1ENH
[5]
T0ENH
[4]
U0RENH
UART 0 Receive Interrupt Request Enable High Bit
UART 0 Transmit Interrupt Request Enable High Bit
[3]
U0TENH
2
[2]
I C Interrupt Request Enable High Bit
I2CENH
[1]
SPIENH
SPI Interrupt Request Enable High Bit
ADC Interrupt Request Enable High Bit
[0]
ADCENH
Table 37. IRQ0 Enable Low Bit Register (IRQ0ENL)
Bit
7
T2ENL
0
6
T1ENL
0
5
T0ENL
0
4
3
2
I2CENL
0
1
0
Field
RESET
R/W
U0RENL U0TENL
SPIENL ADCENL
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E033h
Bit
Description
[7]
Timer 2 Interrupt Request Enable Low Bit
T2ENL
[6]
Timer 0 Interrupt Request Enable Low Bit
T1ENL
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Bit
Description (Continued)
[5]
Timer 0 Interrupt Request Enable Low Bit
T0ENL
[4]
UART 0 Receive Interrupt Request Enable Low Bit
U0RENL
[3]
UART 0 Transmit Interrupt Request Enable Low Bit
U0TENL
2
[2]
I C Interrupt Request Enable Low Bit
I2CENL
[1]
SPIENL
SPI Interrupt Request Enable Low Bit
ADC Interrupt Request Enable Low Bit
[0]
ADCENL
IRQ1 Enable High and Low Bit Registers
The IRQ1 Enable High and Low Bit registers, shown in Tables 39 and 40, form a priority-
encoded enabling for interrupts in the Interrupt Request 1 Register. Priority is generated
by setting bits in each register. Table 38 describes the priority control for IRQ1.
Table 38. IRQ1 Enable and Priority Encoding
IRQ1ENH[x]
IRQ1ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Nominal
High
Note: x indicates register bits in the range 7 to 0.
Table 39. IRQ1 Enable High Bit Register (IRQ1ENH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E036h
Note: PADxENH = Port A/D Bit[x] Interrupt Request Enable High Bit
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Table 40. IRQ1 Enable Low Bit Register (IRQ1ENL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E037h
Note: PAxENL = Port A/D Bit[x] Interrupt Request Enable Low Bit.
IRQ2 Enable High and Low Bit Registers
The IRQ2 Enable High and Low Bit registers, shown in Tables 42 and 43, form a priority-
encoded enabling for interrupts in the Interrupt Request 2 Register. Priority is generated
by setting bits in each register. Table 41 describes the priority control for IRQ2.
Table 41. IRQ2 Enable and Priority Encoding
IRQ2ENH[x]
IRQ2ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Nominal
High
Note: x indicates the register bits from 0 through 7.
Table 42. IRQ2 Enable High Bit Register (IRQ2ENH)
Bit
7
6
5
4
3
2
1
0
Field
PWMTENH U1RENH
U1TENH PWMFENH
C3ENH/
C2ENH/
C1ENH/
C0ENH/
DMA3ENH DMA2ENH DMA1ENH DMA0ENH
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E03Ah
Bit
Description
[7]
PWM Timer Interrupt Request Enable High Bit
PWMTENH
[6]
UART 1 Receive Interrupt Request Enable High Bit
U1RENH
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Bit
Description (Continued)
[5]
U1TENH
UART 1 Transmit Interrupt Request Enable High Bit
PWM Fault Interrupt Request Enable High Bit
Port Cx or DMAx Interrupt Request Enable High Bit
[4]
PWMFENH
[3:0]
CxENH/
DMAxENH
Table 43. IRQ2 Enable Low Bit Register (IRQ2ENL)
Bit
7
6
5
4
3
2
1
0
Field
PWMTENL
U1RENL
U1TENL
PWMFENL
C3ENL/
C2ENL/
C1ENL/
C0ENL/
DMA3ENL DMA2ENL DMA1ENL DMA0ENL
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E03Bh
Bit
Description
[7]
PWM Timer Interrupt Request Enable Low Bit
PWMTENL
[6]
U1RENL
UART 1 Receive Interrupt Request Enable Low Bit
UART 1 Transmit Interrupt Request Enable Low Bit
PWM Fault Interrupt Request Enable Low Bit
[5]
U1TENL
[4]
PWMFENL
[3:0]
Port Cx or DMAx Interrupt Request Enable Low Bit.
CxENL/
DMAxENL
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Timers
Z16FMC Series MCUs contain three 16-bit reloadable timers used for timing, event
counting, or generation of pulse width modulated (PWM) signals.
Features
The timers include the following features:
•
•
•
•
•
•
•
16-bit reload counter
Programmable prescaler with values ranging from 1 to 128
PWM output generation (single or differential)
Capture and compare capability
External input pin for event counting, clock gating, or capture signal
Complementary timer output pins
Timer interrupt
Architecture
Capture and compare capability measures the velocity from a tachometer wheel or reads
sensor outputs for rotor position for brushless DC motor commutation.
Figure 10 displays the architecture of the timer.
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Timer Block
Timer
Control
Data
Bus
Block
Control
16-Bit
Reload Register
Interrupt,
PWM,
Timer
Interrupt
and
Timer Output
Control
TOUT
TOUT
System
Clock
16-Bit Counter
with Prescaler
Timer
Input
Gate
Input
16-Bit
PWM/Compare
Capture
Input
Figure 10. Timer Block Diagram
Operation
The general-purpose timer is a 16-bit up-counter. In normal operation, the timer is initial-
ized to 0001h. When the timer is enabled, it counts up to the value contained in the reload
High and Low Byte registers, then resets to 0001h. The counter either halts or continues
depending on the mode.
Minimum time-out delay (1 system clock) is set by loading the value 0001hinto the
Timer Reload High and Low Byte registers and setting the prescale value to 1.
Maximum time-out delay (216 * 27 system clocks) is set by loading the value 0000hinto
the Timer Reload High and Low Byte registers and setting the prescale value to 128.
When the timer reaches FFFFh, the timer rolls over to 0000h.
If the reload register is set to a value less than the current counter value, the counter con-
tinues counting until it reaches FFFFh, then resets to 0000h. Next, the timer continues to
count until it reaches the reload value and it resets to 0001h.
Note: When T0IN0, T0IN1 and T0IN2 functions are enabled on the PB0, PB1 and PB2 pins,
each Timer0 input will have the same effect as the single Timer0 input pin, T0IN. For
example, if the Timer 0 is in CAPTURE Mode, any transitions on any of the PB0, PB1 and
PB2 pins will cause a capture.
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Timer Operating Modes
The timers are configured to operate in the following modes:
ONE-SHOT Mode
In ONE-SHOT Mode, the timer counts up to the 16-bit reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. When the timer
reaches the reload value, it generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to 0001h. The timer is automatically disabled and stops
counting.
If the timer output alternate function is enabled, the timer output pin changes state for one
system clock cycle (from Low to High, then back to Low if TPOL = 0) at timer reload. If
the timer output is required to make a permanent state change on ONE-SHOT time-out,
first set the TPOL bit in the Timer Control 1 Register to the start value before beginning
ONE-SHOT Mode. Next, after starting the timer, set TPOL to the opposite value.
Observe the following steps to configure a timer for ONE-SHOT Mode and initiate the
count.
1. Write to the timer control registers to:
–
–
–
–
Disable the timer
Configure the timer for ONE-SHOT Mode
Set the prescale value
Set the initial output level (High or Low) using the TPOL bit for the timer output
alternate function
–
Set the INTERRUPT Mode
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the timer reload High and Low Byte registers to set the reload value.
4. Enable the timer interrupt, if required and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. When using the timer output function, configure the associated GPIO port pin for the
timer output alternate function.
6. Write to the Timer Control 1 Register to enable the timer and initiate counting.
The timer period is calculated by the following equation (start value = 1):
(Reload Value – Start Value + 1) x Prescale
One-Shot Mode Time-Out Period(s)
=
System Clock Frequency (Hz)
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TRIGGERED ONE-SHOT Mode
In TRIGGERED ONE-SHOT Mode, the timer operates as follows:
1. The timer is nonactive until a trigger is received. The timer trigger is taken from the
timer input pin. The TPOL bit in the Timer Control 1 Register selects whether the trig-
ger occurs on the rising edge or the falling edge of the timer input signal.
2. Following the trigger event, the timer counts system clocks up to the 16-bit reload
value stored in the timer reload High and Low Byte registers.
3. After reaching the reload value, the timer outputs a pulse on the timer output pin,
generates an interrupt and resets the count value in the Timer High and Low Byte
registers to 0001h. The duration of the output pulse is a single system clock. The
TPOL bit also sets the polarity of the output pulse.
4. The timer now idles until the next trigger event. Trigger events, which occur while the
timer is responding to a previous trigger is ignored.
Observe the following steps to configure timer 0 in TRIGGERED ONE-SHOT Mode and
initiate operation:
1. Write to the timer control registers to:
–
–
–
–
Disable the timer
Configure the timer for TRIGGERED ONE-SHOT Mode
Set the prescale value
Set the initial output level (High or Low) via the TPOL bit for the timer output
alternate function
–
Set the INTERRUPT Mode
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the timer reload High and Low Byte registers to set the reload value.
4. Enable the timer interrupt, if required and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. When using the timer output function, configure the associated GPIO port pin for the
timer output alternate function.
6. Write to the Timer Control 1 Register to enable the timer. Counting does not start until
the appropriate input transition occurs.
The timer period is calculated by the following equation (Start Value = 1):
(Reload Value – Start Value +1) x Prescale
Triggered One-Shot Mode Time-Out Period(s)
=
System Clock Frequency (Hz)
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CONTINUOUS Mode
In CONTINUOUS Mode, the timer counts up to the 16-bit reload value stored in the timer
reload High and Low Byte registers. After reaching the reload value, the timer generates
an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001h
and counting resumes. If the timer output alternate function is enabled, the timer output
pin changes state (from Low to High or High to Low) after timer reload.
Observe the following steps to configure a timer for CONTINUOUS Mode and initiate
count:
1. Write to the timer control registers to:
–
–
–
–
Disable the timer
Configure the timer for CONTINUOUS Mode
Set the prescale value
Set the initial output level (High or Low) through TPOL for the timer output alter-
nate function
2. Write to the Timer High and Low Byte registers to set the starting count value (usually
0001h). This only affects the first pass in CONTINUOUS Mode. After the first timer
reload in CONTINUOUS Mode, counting always begins at the reset value of 0001h.
3. Write to the timer reload High and Low Byte registers to set the reload period.
4. Enable the timer interrupt, if required and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. When using the timer output function, configure the associated GPIO port pin for the
timer output alternate function.
6. Write to the Timer Control 1 Register to enable the timer and initiate counting.
The timer period is calculated by the following equation:
Reload Value x Prescale
Continuous Mode Time-Out Period(s) =
System Clock Frequency (Hz)
If an initial starting value other than 0001his loaded into the Timer High and Low Byte
registers, use the ONE-SHOT Mode equation to determine the first time-out period.
COUNTER and COMPARATOR COUNTER Modes
In COUNTER Mode, the timer counts input transitions from a GPIO port pin. The timer
input is taken from the associated GPIO port pin. The TPOL bit in the Timer Control 1
Register selects whether the count occurs on the rising edge or the falling edge of the timer
input signal. In COUNTER Mode, the prescaler is disabled.
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The input frequency of the timer input signal must not exceed one-fourth the sys-
tem clock frequency.
Caution:
In COMPARATOR COUNTER Mode, the timer counts output transitions from an analog
comparator output. The timer takes its input from the output of the comparator. The TPOL
bit in the Timer Control 1 Register selects whether the count occurs on the rising edge or
the falling edge of the comparator output signal. The prescaler is disabled in the COM-
PARATOR COUNTER Mode.
The frequency of the comparator output signal must not exceed one-fourth the
system clock frequency.
Caution:
After reaching the reload value stored in the timer reload High and Low Byte registers, the
timer generates an interrupt. The count value in the Timer High and Low Byte registers is
reset to 0001hand counting resumes.
If the timer output alternate function is enabled, the timer output pin changes state (from
Low to High or High to Low) at timer reload.
Observe the following steps to configure a timer for COUNTER and COMPARATOR
COUNTER modes and initiate the count:
1. Write to the timer control registers to:
–
–
–
Disable the timer
Configure the timer for COUNTER or COMPARATOR COUNTER Mode
Select either the rising edge or falling edge of the timer input or comparator output
signal for the count. This selection also sets the initial logic level (High or Low)
for the timer output alternate function. However, the timer output function does
not require enabling.
2. Write to the timer reload High and Low Byte registers to set the starting count value.
This affects only the first pass in the COUNTER modes. After the first timer reload,
counting always begins at the reset value of 0001h.
3. Write to the timer reload High and Low Byte registers to set the reload value.
4. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the associated GPIO port pin for the timer input alternate function
(COUNTER Mode).
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6. When using the timer output function, configure the associated GPIO port pin for the
timer output alternate function.
7. Write to the Timer Control 1 Register to enable the timer.
PWM SINGLE and DUAL OUTPUT Modes
In PWM SINGLE OUTPUT Mode, the timer outputs a PWM output signal through a
GPIO Port pin. In PWM DUAL OUTPUT Mode, the timer outputs a PWM output signal
and also its complement through two GPIO port pins. The timer first counts up to the 16-
bit PWM match value stored in the timer PWM High and Low Byte registers. When the
timer count value matches the PWM value, the timer output toggles. The timer continues
counting until it reaches the reload value stored in the timer reload High and Low Byte
registers. When it reaches the reload value, the timer generates an interrupt. The count
value in the Timer High and Low Byte registers is reset to 0001hand counting resumes.
The timer output signal begins with value = TPOL, then transits to TPOL when the timer
value matches the PWM value. The timer output signal returns to TPOL after the timer
reaches the reload value and is reset to 0001h.
In PWM DUAL OUTPUT Mode, the timer also generates a second PWM output signal,
timer output complement (TOUT). A programmable deadband is configured (PWMD
field) to delay (0 to 128 system clock cycles) the Low to a High (inactive to active) output
transitions on these two pins. This configuration ensures a time gap between the deasser-
tion of one PWM output to the assertion of its complement.
Observe the following steps to configure a timer for PWM SINGLE or DUAL OUTPUT
Mode and initiate the PWM operation:
1. Write to the timer control registers to:
–
–
–
–
Disable the timer.
Configure the timer for the selected PWM Mode.
Set the prescale value.
Set the initial logic level (High or Low) and PWM High or Low transition for the
timer output alternate function with the TPOL bit.
–
Set the deadband delay (DUAL OUTPUT Mode) with the PWMD field.
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001h). The starting count value only affects the first pass in PWM Mode.
After the first timer reset in PWM Mode, counting always begins at the reset value of
0001h.
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the timer reload High and Low Byte registers to set the reload value (PWM
period). The reload value must be greater than the PWM value.
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5. Enable the timer interrupt, if required and set the timer interrupt priority by writing to
the relevant interrupt registers.
6. Configure the associated GPIO port pin(s) for the timer output alternate function.
7. Write to the Timer Control 1 Register to enable the timer and initiate counting.
The PWM period is determined by the following equation:
Reload Value x Prescale
PWM Period(s) =
System Clock Frequency (Hz)
If an initial starting value other than 0001his loaded into the Timer High and Low Byte
registers, use the ONE-SHOT Mode equation to determine the first PWM time-out period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is deter-
mined by:
Reload Value – PWM Value
PWM Output High Time Ration (%)
=
x 100
Reload Value
If TPOL is set to 1, the ratio of the PWM output High time to the total period is deter-
mined by:
PWM Value
PWM Output High Time Ration (%)
=
x 100
Reload Value
CAPTURE Modes
There are three CAPTURE modes which provide slightly different methods for recording
the time or time interval between timer input events. These modes are CAPTURE Mode,
CAPTURE RESTART Mode and CAPTURE COMPARE Mode. In all the three modes,
when the appropriate timer input transition (capture event) occurs, the timer counter value
is captured and stored in the PWM high and low Byte registers. The TPOL bit in the Timer
Control 1 Register determines if the Capture occurs on a rising edge or a falling edge of
the timer input signal. The TICONFIG bit determines whether interrupts are generated on
capture events, reload events, or both. The INCAP bit in Timer Control 0 Register clears
to indicate an interrupt caused by a reload event and sets to indicate the timer interrupt is
caused by an input capture event.
If the timer output alternate function is enabled, the timer output pin changes state (from
Low to High or High to Low) at timer reload. The initial value is determined by the TPOL
bit.
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CAPTURE Mode
When the timer is enabled in CAPTURE Mode, it counts continuously and resets to
0000h from FFFFh. When the capture event occurs, the timer counter value is captured
and stored in the PWM High and Low Byte registers, an interrupt is generated and the
timer continues counting. The timer continues counting up to the 16-bit reload value
stored in the timer reload High and Low Byte registers. On reaching the reload value, the
timer generates an interrupt and continues counting.
CAPTURE RESTART Mode
When the timer is enabled in CAPTURE RESTART Mode, it counts continuously until the
capture event occurs or the timer count reaches the 16-bit Compare value stored in the
timer reload High and Low Byte registers. If the Capture event occurs first, the timer
counter value is captured and stored in the PWM High and Low Byte registers, an inter-
rupt is generated and the count value in the Timer High and Low Byte registers is reset to
0001hand counting resumes. If no Capture event occurs, on reaching the reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001hand counting resumes.
CAPTURE/COMPARE Mode
The CAPTURE/COMPARE Mode is identical to CAPTURE RESTART Mode except that
counting does not start until the first appropriate external Timer Reload High and Low
Byte input transition occurs. Every subsequent appropriate transition (after the first) of the
Timer Reload High and Low Byte input signal captures the current count value. When the
Capture event occurs, an interrupt is generated, the count value in the Timer Reload High
and Low byte High and Low Byte registers is reset to 0001hand counting resumes. If no
Capture event occurs, on reaching the Compare value, the timer generates an interrupt, the
count value in the Timer High and Low Byte registers is reset to 0001hand counting
resumes.
Observe the following steps to configure a timer for one of the CAPTURE modes and ini-
tiate the count:
1. Write to the timer control registers to:
–
–
–
–
–
Disable the timer
Configure the timer for the selected CAPTURE Mode
Set the prescale value
Set the Capture edge (rising or falling) for the timer input
Configure the timer interrupt to be generated at the input capture event, the reload
event or both by setting TICONFIG field
2. Write to the timer reload High and Low Byte registers to set the starting count value
(typically 0001h).
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3. Write to the timer reload High and Low Byte registers to set the reload value.
4. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the associated GPIO port pin for the timer input alternate function.
6. Write to the Timer Control 1 Register to enable the timer. In CAPTURE and
CAPTURE RESTART modes, the timer begins counting. In CAPTURE COMPARE
Mode the timer does not start counting until the first appropriate input transition
occurs.
In CAPTURE modes, the elapsed time from timer start to Capture event is calculated
using the following equation (start value = 1):
(Capture Value – Start Value + 1) x Prescale
Capture Elapsed Time(s)
=
System Clock Frequency (Hz)
COMPARE Mode
In COMPARE Mode, the timer counts up to the 16-bit Compare value stored in the timer
reload High and Low Byte registers. After reaching the compare value, the timer generates
an interrupt and counting continues (the timer value is not reset to 0001h). If the timer
output alternate function is enabled, the timer output pin changes state (from Low to High
or High to Low).
If the timer reaches FFFFh, the timer rolls over to 0000hand continues counting.
Observe the following steps to configure timer for COMPARE Mode and initiate the
count:
1. Write to the timer control registers to:
–
–
–
–
Disable the timer
Configure the timer for COMPARE Mode
Set the prescale value
Set the initial logic level (High or Low) for the timer output alternate function, if
required
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the timer reload High and Low Byte registers to set the Compare value.
4. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. When using the timer output function, configure the associated GPIO port pin for the
timer output alternate function.
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6. Write to the Timer Control 1 Register to enable the timer and initiate counting.
The compare time is calculated by the following equation (Start Value = 1):
(Compare Value – Start Value + 1) x Prescale
Compare Mode Time(s)
=
System Clock Frequency (Hz)
GATED Mode
In GATED Mode, the timer counts only when the timer input signal is in its active state as
determined by the TPOL bit in the Timer Control 1 Register. When the timer input signal
is active, counting begins. A timer interrupt is generated when the timer input signal tran-
sits from active to inactive state or a timer reload occurs. To determine if a timer input sig-
nal deassertion generated the interrupt, read the associated GPIO input value and compare
to the value stored in the TPOL bit.
The timer counts up to the 16-bit reload value stored in the timer reload High and Low
Byte registers. On reaching the reload value, the timer generates an interrupt, the count
value in the Timer High and Low Byte registers is reset to 0001hand counting continues
as long as the timer input signal is active. If the timer output alternate function is enabled,
the timer output pin changes state (from Low to High or from High to Low) at timer
reload.
Observe the following steps to configure a timer for GATED Mode and initiate the count:
1. Write to the timer control registers to:
–
–
–
–
Disable the timer
Configure the timer for GATED Mode
Set the prescale value
Select the active state of the timer input through the TPOL bit
2. Write to the Timer High and Low Byte registers to set the initial count value. This
affects only the first pass in GATED Mode. After the first timer Reset in GATED
Mode, counting always begins at the reset value of 0001h.
3. Write to the timer reload High and Low Byte registers to set the reload value.
4. Enable the timer interrupt and set the timer interrupt priority by writing to the relevant
interrupt registers.
5. Configure the timer interrupt to be generated only at the input deassertion event, the
reload event, or both by setting TICONFIG field of the Timer Control 0 Register.
6. Configure the associated GPIO port pin for the timer input alternate function.
7. Write to the Timer Control 1 Register to enable the timer.
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8. The timer counts when the timer input is equal to the TPOL bit.
Reading Timer Count Values
The current count value in the timer is read while counting (enabled). This has no effect on
timer operation. Normally, the count must be read with one 16-bit operation. However,
8-bit reads are performed using with the following method. When the timer is enabled and
the Timer High Byte Register is read, the contents of the Timer Low Byte Register are
placed in a holding register. A subsequent read from the Timer Low Byte Register returns
the value in the holding register. This operation allows accurate reads of the full 16-bit
timer count value when enabled. When the timer is not enabled, a read from the Timer
Low Byte Register returns the actual value in the counter.
The Timers can be cascaded by using the Cascade bit in the Timer control registers. When
this bit is set for a Timer, the input source is redefined. When the Cascade bit is set for
Timer0, the input for Timer0 is the output of the Analog Comparator. When the Cascade
bit is set for Timer1 and Timer2, the output of Timer0 and Timer1 become the input for
Timer1 and Timer2, respectively. Any Timer Mode can be used. Timer0 can be cascaded
to Timer1 only by setting the Cascade bit for Timer1. Timer1 cascaded to Timer2 only by
setting the Cascade bit for Timer2. Or all three cascaded, Timer0 to Timer1 or Timer2 for
really long counts by setting the Cascade bit for Timer1 and Timer2.
Timer Control Register Definitions
This section presents the timer high-/low-byte, reload, PWM, and control registers.
Timer 0–2 High and Low Byte Registers
The Timer 0–2 High and Low Byte registers (TxH and TxL), shown in Tables 44 and 45,
contain the current 16-bit timer count value. When the timer is enabled, a read from TxH
stores the value in TxL to a temporary holding register. A read from TxL always returns
this temporary register when the timer is enabled. When the timer is disabled, reads from
the TxL reads the register directly.
Writing to the Timer High and Low Byte registers while the timer is enabled is not recom-
mended. There are no temporary holding registers available for Write operations, so
simultaneous 16-bit writes are not possible. When either of the Timer High or Low Byte
registers are written during counting, the 8-bit written value is placed in the counter (High
or Low Byte) at the next clock edge. The counter continues counting from the new value.
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Table 44. Timer 0–2 High Byte Register (TxH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
TH
00h
R/W
ADDR
FF_E300h, FF_E310h, FF_E320h
Bit
Description
[7:0]
TH
Timer High Byte
TH is one of two bytes {TH[7:0], TL[7:0]} which contain the current 16-bit timer count value.
Table 45. Timer 0–2 Low Byte Register (TXL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
TL
01h
R/W
ADDR
FF_E301h, FF_E311h, FF_E321h
Bit
Description
[7:0]
TL
Timer Low Byte
TL is one of two bytes {TH[7:0], TL[7:0]} which contain the current 16-bit timer count value.
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Timer X Reload High and Low Byte Registers
The timer 0–2 Reload High and Low Byte registers (TxRH and TxRL), shown in
Tables 46 and 47, store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the
Timer Reload High Byte Register are stored in a temporary holding register. When a write
to the timer reload low byte register occurs, the temporary holding register value is written
to the Timer High Byte Register. This operation allows simultaneous updates of the 16-bit
timer reload value.
Table 46. Timer 0–2 Reload High Byte Register (TxRH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
TRH
FFh
R/W
ADDR
FF_E302h, FF_E312h, FF_E322h
Bit
Description
7:0
TRH
Timer Reload Register High
TRH is one of two bytes which form the 16-bit reload value, {TRH[7:0], TRL[7:0]}. This value
sets the maximum count value which initiates a timer reload to 0001h.
Table 47. Timer 0–2 Reload Low Byte Register (TxRL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
TRL
FF
R/W
ADDR
FF_E303h, FF_E313h, FF_E323h
Bit
Description
7:0
TRL
Timer Reload Register Low
TRL is one of two bytes which form the 16-bit reload value, {TRH[7:0], TRL[7:0]}. This value
sets the maximum count value which initiates a timer reload to 0001h.
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Timer 0–2 PWM High and Low Byte Registers
The timer 0–2 PWM High and Low Byte registers (TxPWMH and TxPWML), shown in
Tables 48 and 49, define PWM operations. These registers also store the timer counter val-
ues for the CAPTURE modes.
Table 48. Timer 0–2 PWM High Byte Register (TxPWMH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
PWMH
00h
R/W
ADDR
FF_E304h, FF_E314h, FF_E324h
Bit
Description
7:0
PWMH
Pulse-Width Modulator High Byte
PWMH is one of two bytes, {PWMH[7:0], PWML[7:0]}, which form a 16-bit value that is com-
pared to the current 16-bit timer count. When a match occurs, the PWM output changes state.
The PWM output value is set by the TPOL bit in the Timer Control 1 Register (TxCTL1).
The TxPWMH and TxPWML registers also store the 16-bit captured timer value when operat-
ing in CAPTURE or CAPTURE/COMPARE modes.
Table 49. Timer 0–2 PWM Low Byte Register (TxPWML)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
PWML
00h
R/W
ADDR
FF_E305h, FF_E315h, FF_E315h
Bit
Description
7:0
PWML
Pulse-Width Modulator Low Byte
PWHL is one of two bytes, {PWMH[7:0], PWML[7:0]}, which form a 16-bit value that is com-
pared to the current 16-bit timer count. When a match occurs, the PWM output changes state.
The PWM output value is set by the TPOL bit in the Timer Control 1 Register (TxCTL1).
The TxPWMH and TxPWML registers also store the 16-bit captured timer value when operat-
ing in CAPTURE or CAPTURE/COMPARE modes.
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Timer 0–2 Control Registers
Timer 0–2 Control 0 Register
The Timer 0–2 Control 0 (TxCTL0) Register, together with the Timer 0–2 Control 1
(TxCTL1) Register, determines timer configuration and operation.
Table 50. Timer 0–2 Control 0 Register (TxCTL0)
Bit
7
TMODE[3]
0
6
5
4
CASCADE
0
3
2
1
0
Field
RESET
R/W
TICONFIG
PWMD
000
INCAP
00
0
R/W
R/W
R/W
R/W
R
ADDR
FF_E306h, FF_E316h, FF_E326h
Bit
Description
[7]
Timer Mode High Bit
TMODE[3] This bit, along with the TMODE[2:0] field in T0CTL1 Register, determines the operating
mode of the timer; it is the most significant bit of the timer mode selection value. For more
details, see the T0CTL1 Register description.
[6:5]
Timer Interrupt Configuration
TICONFIG This field configures timer interrupt definitions. These bits affect all modes. The effect per
mode is explained below.
ONE SHOT, CONTINUOUS, COUNTER, PWM, COMPARE, DUAL PWM, TRIGGERED
ONE-SHOT, COMPARATOR COUNTER
0x = Timer interrupt occurs on reload.
10 = Timer interrupts are disabled.
11 = Timer Interrupt occurs on reload.
GATED
0x = Timer interrupt occurs on reload.
10 = Timer interrupt occurs on inactive gate edge.
11 = Timer interrupt occurs on reload.
CAPTURE, CAPTURE/COMPARE, CAPTURE RESTART
0x = Timer interrupt occurs on reload and capture.
10 = Timer interrupt occurs on capture only.
11 = Timer interrupt occurs on reload only.
[4]
Timer Cascade
CASCADE This field allows the timers to be cascaded for larger counts. Only Counter Mode must be
used with this feature.
0 = The timer is not cascaded.
1 = Timer is cascaded. If timer 0 CASCADE bit is set, ANALOG COMPARATOR output is
used as input. If timer 1 CASCADE bit is set, the Timer 0 output is used as the input. If
timer 2 CASCADE bit is set, the timer 1 output is used as input.
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Bit
Description (Continued)
PWM Delay Value
[3:1]
PWMD
This field is a programmable delay to control the number of additional system clock cycles
following a PWM or reload compare before the timer output or the timer output complement
is switched to the active state. This field ensures a time gap between deassertion of one
PWM output to the assertion of its complement.
000 = No delay.
001 = 2 cycles delay.
010 = 4 cycles delay.
011 = 8 cycles delay.
100 = 16 cycles delay.
101 = 32 cycles delay.
110 = 64 cycles delay.
111 = 128 cycles delay.
[0]
INCAP
Input Capture Event
0 = The most recent timer interrupt is not a result of a timer input capture event.
1 = The most recent timer interrupt is a result of a timer input capture event.
Timer 0–2 Control 1 Register
The Timer 0–2 control 1 (TxCTL1) register enables/disables the timer, sets the prescaler
value and determines the timer operating mode.
Table 51. Timer 0–2 Control 1 Register (TxCTL1)
BITS
7
6
TPOL
0
5
4
3
2
1
0
FIELD
RESET
R/W
TEN
0
PRES
000
TMODE
000
R/W
R/W
R/W
R/W
ADDR
FF_E307h, FF_E317h, FF_E327h
Bit
Description
[7]
TEN
Timer Enable
0 = Timer is disabled.
1 = Timer is enabled.
Note: This TEN bit is cleared automatically when the timer stops.
[6]
TPOL
Timer Input/Output Polarity
This bit is a function of the current operating mode of the timer. It determines the polarity of the
input and/or output signal. When the timer is disabled, the timer output signal is set to the value
of this bit.
ONE-SHOT Mode. If the timer is enabled, the timer output signal pulses (changes state) for
one system clock cycle after timer reload.
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Bit
Description (Continued)
[6]
TPOL
CONTINUOUS Mode. If the timer is enabled, the timer output signal is complemented after
timer reload.
(cont’d.) COUNTER Mode. If the timer is enabled, the timer output signal is complemented after timer
reload.
0 = Count occurs on the rising edge of the timer input signal.
1 = Count occurs on the falling edge of the timer input signal.
PWM SINGLE OUTPUT Mode. When enabled, the timer output is forced to TPOL after PWM
count match and forced back to TPOL after reload.
CAPTURE Mode. If the timer is enabled, the timer output signal is complemented after timer
reload.
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
COMPARE Mode. The timer output signal is complemented after timer reload.
GATED Mode. The timer output signal is complemented after timer reload.
0 = Timer counts when the timer input signal is High and interrupts are generated on the falling
edge of the timer input.
1 = Timer counts when the timer input signal is Low and interrupts are generated on the rising
edge of the timer input.
CAPTURE/COMPARE Mode. If the timer is enabled, the timer output signal is complemented
after timer reload.
0 = Counting starts on the first rising edge of the timer Input signal.
The current count is captured on subsequent rising edges of the timer
input signal.
1 = Counting starts on the first falling edge of the timer input signal.
The current count is captured on subsequent falling edges of the timer
input signal.
PWM DUAL OUTPUT Mode. If enabled, the timer output is set=TPOL after PWM match and
set = TPOL after reload. If enabled the timer output complement takes on the opposite value of
the timer output. The PWMD field in the T0CTL1 Register determines an optional added delay
on the assertion (Low to High) transition of both timer output and the timer output complement
for deadband generation.
CAPTURE RESTART Mode. If the timer is enabled, the timer output signal is complemented
after timer reload.
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
ANALOG COMPARATOR COUNTER Mode. If the timer is enabled, the timer output sig-
nal is complemented after timer reload.
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
TRIGGERED ONE-SHOT Mode. If the timer is enabled, the timer output signal is comple-
mented after timer reload.
0 = The timer triggers on a Low to High transition on the input.
1 = The timer triggers on a High to Low transition on the input.
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Bit
Description (Continued)
[5–3]
PRES
Prescaler
The timer input clock is divided by 2
PRES
, where PRES is set from 0 to 7. The prescaler is reset
each time the timer is disabled. This ensures proper clock division each time the timer is
restarted.
000 = Divide by 1.
001 = Divide by 2.
010 = Divide by 4.
011 = Divide by 8.
100 = Divide by 16.
101 = Divide by 32.
110 = Divide by 64.
111 = Divide by 128.
[2:0]
Timer Mode
TMODE This field, along with the TMODE[3] bit in T0CTL0 Register, determines the operating mode of
the timer. TMODE[3:0] selects from the following modes:
0000 = ONE-SHOT Mode.
0001 = CONTINUOUS Mode.
0010 = COUNTER Mode.
0011 = PWM SINGLE OUTPUT Mode.
0100 = CAPTURE Mode.
0101 = COMPARE Mode.
0110 = GATED Mode.
0111 = CAPTURE/COMPARE Mode.
1000 = PWM DUAL OUTPUT Mode.
1001 = CAPTURE RESTART Mode.
1010 = COMPARATOR COUNTER Mode.
1011 = TRIGGERED ONE-SHOT Mode.
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Multi-Channel PWM Timer
Z16FMC Series MCUs include a Multi-Channel PWM optimized for motor control appli-
cations. The PWM includes the following features:
•
•
•
•
•
•
Six independent PWM outputs or three complementary PWM output pairs.
Programmable deadband insertion for complementary output pairs.
Edge-aligned or center-aligned PWM signal generation.
PWM off-state is an option bit programmable.
PWM outputs driven to off-state on System Reset.
Asynchronous disabling of PWM outputs on system fault. Outputs are forced to off-
state.
•
•
•
•
•
•
•
Fault inputs generate pulse-by-pulse or hard shutdown.
12-bit reload counter with 1, 2, 4, or 8 programmable clock prescaler.
High current source and sink on all PWM outputs.
PWM pairs used as general purpose inputs when outputs are disabled.
ADC synchronized with PWM period.
Synchronization for current-sense sample and hold.
Narrow pulse suppression with programmable threshold.
Architecture
The PWM unit consists of a master timer to generate the modulator time base and six inde-
pendent compare registers to set the PWM for each output. The six outputs are designed to
provide control signals for inverter drive circuits. The outputs are grouped into pairs con-
sisting of a high-side driver and a low-side driver output. The output pairs are programma-
ble to operate independently or as complementary signals.
In complementary output mode, a programmable dead-time is inserted to ensure nonover-
lapping signal transitions. The master count and compare values feed into modulator logic
which generates the proper transitions in the output states. Output polarity and fault/off-
state control logic allows programming of the default off-states which forces the outputs to
a safe state in the event a fault in the motor drive is detected. Figure 11 displays the archi-
tecture of the PWM modulator.
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ISense S/H
12-bit Counter with
Prescaler
IRQ
Control Logic
ADC Trig
Fault inputs
PWM Deadband
PWMH0D
PWML0D
Data Bus
PWM
State
Logic
Fault
Polarity
Logic
PWMH0
PWML0
System Clock
PWMH1D
PWML1D
PWM
State
Logic
Fault
Polarity
Logic
PWMH1
PWML1
PWMH2D
PWML2D
PWM
State
Logic
Fault
Polarity
Logic
PWMH2
PWML2
Figure 11. PWM Block Diagram
Operation
This section discusses the operational aspects of Z16FMC Series pulse-width modulation,
and presents tabled bit descriptions for the PWM high-/low-byte, reload, duty cycle, and
control registers.
PWM Option Bit
To protect the configuration of critical PWM parameters, settings to enable output chan-
nels and the default off-state are maintained as user option bits. These values are set when
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the user program code is written to the part and the software cannot change these values
(see the Option Bit chapter on page 260).
PWM Output Polarity and Off-State
The default off-state and polarity of the PWM outputs are controlled by the option bits
PWMHI and PWMLO. The PWMHI option controls the off-state and polarity for PWM
high-side outputs PWMH0, PWMH1 and PWMH2. The PWMLO option controls the off-
state and polarity for low-side outputs PWML0, PWML1 and PWML2.
The off-state is the value programmed in the option bit. For example, programming
PWMHI to 1 makes the off-state of PWMH0, PWMH1 and PWMH2 a High logic value
and the active state a Low logic value. Conversely, programming PWMHI to 0 causes the
off-state to be a Low logic value. PWMLO is programmed in a similar manner.
PWM Enable
The MCEN option bit enables output pairs PWM0, PWM1 and PWM2. If the Motor Con-
trol option is not enabled, the PWM outputs remain in a high-impedance state after reset
and is used as alternate functions like general purpose input. If the Motor Control option is
enabled, following a Power-On Reset (POR) the PWM pins enter a high impedance state.
As the internal reset proceeds, the PWM outputs are forced to the off-state as determined
by the PWMHI and PWMLO off-state option bits.
PWM Reload Event
To prevent erroneous PWM pulse-widths and periods, registers that control the timing of
the output are buffered. Buffering causes all the PWM compare values to update. In other
words, the registers controlling the duty cycle and clock source prescaler only take effect
on a PWM reload event. A PWM reload event is configured to occur at the end of each
PWM period or only every 2, 4, or 8 PWM periods by setting the RELFREQ bits in the
PWM Control 1 Register (PWMCTL1). Software indicates that all new values are ready
by setting the READY bit in the PWM Control 0 Register (PWMCTL0) to 1. When the
READY bit is set to 1, the buffered values take effect at the next reload event.
PWM Prescaler
The prescaler decreases the PWM clock signal by factors of 1, 2, 4, or 8 with respect to the
system clock. The PRES[1:0] bit field in the PWM Control 1 Register (PWMCTL1) con-
trols prescaler operation. This 2-bit PRES field is buffered so that the prescale value only
changes on a PWM Reload event.
PWM Period and Count Resolution
The PWM counter operates in two modes to allow edge-aligned and center-aligned out-
puts. Figures 12 and 13 illustrate edge and center-aligned PWM outputs. The mode in
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which the PWM operates determine the period of the PWM outputs (PERIOD). The pro-
grammed duty-cycle (PWMDC) and the programmed deadband time (PWMDB) deter-
mine the active time of a PWM output. The following sections describe the PWM TIMER
modes and the registers controlling the duty-cycle and deadband time.
PWMxH
No Dead Band
PWMLx
PERIOD
PWMHx
Dead Band Insertion
PWMLx
PWMDB
PWMDB
PWMDC
Figure 12. Edge-Aligned PWM Output
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PWMHx
No Dead Band
PWMLx
PERIOD
PWMHx
Dead Band Insertion
PWMLx
PWMDB
PWMDB
Figure 13. Center-Aligned PWM Output
EDGE-ALIGNED Mode
In EDGE-ALIGNED PWM Mode, a 12-bit up counter creates the PWM period with a
minimum resolution equal to the PWM clock source period. The counter counts up to the
reload value, resets to 000h, then resumes counting.
Prescaler Reload Value
------------------------------------------------------------
Edge-Aligned PWM Mode Period =
fPWMclk
CENTER-ALIGNED Mode
In CENTER-ALIGNED PWM Mode, a 12-bit up/down counter creates the PWM period
with a minimum resolution equal to twice the PWM clock source period. The counter
counts up to the reload value, then counts down to 0.
2 Prescaler Reload Value
---------------------------------------------------------------------
Center-Aligned PWM Mode Period =
fPWMclk
PWM Duty Cycle Registers
The PWM duty cycle registers (PWMH0D, PWML0D, PWMH1D, PWML1D,
PWMH2D, PWML2D) contain a 16-bit signed value where bit 15 is the sign bit. The duty
cycle value is compared to the current 12-bit unsigned PWM count value. If the PWM
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duty cycle value is set less than or equal to 0, the PWM output is deasserted for full PWM
period. If the PWM duty cycle value is set to a value greater than the PWM reload value,
the PWM output is asserted for full PWM period.
Independent and Complementary PWM Outputs
The six PWM outputs are configured to operate independently or as three complementary
pairs. Operation as six independent PWM channels are enabled by setting the INDEN bit
in the PWM Control 1 Register (PWMCTL1). In INDEPENDENT Mode, each PWM out-
put uses its own PWM duty cycle value.
When PWM outputs are configured to operate as three complementary pairs, the PWM
duty cycle values PWMH0D, PWMH1D and PWMH2D control the modulator output. In
COMPLEMENTARY OUTPUT Mode, deadband time is also inserted.
The POLx bits in the PWM Control 1 Register (PWMCTL1) select the relative polarity of
the high- and low-side signals. As illustrated in Figures 12 and 13 , when the POLx bits
are cleared to 0, the PWM high-side output will start in the on-state and transits to the off-
state when the PWM timer count reaches the programmed duty cycle. The low-side PWM
value starts in the off-state and transits to the on-state as the PWM timer count reaches the
value in the associated duty cycle register. Alternately, setting the POLx causes the high-
side output to start in the off-state and the low-side output to start in the on-state.
Manual Off-state Control of PWM Output Channels
Each PWM output is controlled directly by the modulator logic or set to the off-state. To
manually set the PWM output to the off-state, set the OUTCTL bit and the associated
OUTx bits in the PWM Output Control Register (PWMOUT). Off-state control operates
individually by channel. For example, suppressing a single output of pair allows the com-
plementary channel to continue operating. Similarly, if the outputs are operating indepen-
dently disabling one output channel has no effect on the other PWM outputs.
Deadband Insertion
When the PWM outputs are configured to operate as complementary pairs, an 8-bit dead-
band value is defined in the PWM Deadband Register (PWMDB). Inserting deadband
time causes the modulator to separate the deassertion of one PWM signal from the asser-
tion of its complement. This action is essential for many motor control applications to pre-
vent simultaneous turn-on of the high-side and low-side drive transistors. The deadband
counter directly counts system clock cycles and is unaffected by PWM prescaler settings.
The width of this deadband is the number of system clock cycles specified in the PWM
Deadband Register (PWMDB). The minimum deadband duration is zero system clocks
and the maximum time is 255 system clocks. Both PWM outputs of a complementary pair
is deasserted during the deadband period. Generation of deadband time does not alter the
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PWM period but the deadband time is subtracted from the active time of the PWM out-
puts. Figures 12 and 13 display the effect of deadband insertion on the PWM output.
Minimum PWM Pulse Width Filter
The PWM modulator is capable of producing pulses as narrow as a single system clock
cycle in width. The response time of external drive circuit is slower than the period of a
system clock. Therefore, a filter is implemented to enforce a minimum width pulse on the
PWM output pins. All output pulses, either High or Low, must be at least the minimum
number of PWM clock cycles (for details, see the PWM Prescaler section on page 90) in
width as specified in the PWM Minimum Pulse Width Filter (PWMMPF) register. If the
expected pulse width is less than the threshold, the associated PWM output does not
change state until the duty cycle value has changed sufficiently to allow pulse generation
of an acceptable width. The minimum pulse width filter also accounts for the duty cycle
variation caused by the deadband insertion. The PWM output pulse is filtered even if the
programmed duty cycle is greater than the threshold but the decrease in pulse width
because of deadband insertion causes the pulse to be too narrow. The pulse width filter
value is calculated as:
roundupPWMMPF = TminPulseOut TsystemClock PWMprescaler
where TminPulseOut is the shortest allowed pulse width on the PWM outputs (in seconds).
Synchronization of PWM and ADC
The ADC on Z16FMC Series MCUs is synchronized with the PWM period. Enabling the
PWM ADC trigger causes the PWM to generate an ADC conversion signal at the end of
each PWM period. Additionally, in CENTER-ALIGNED Mode, the PWM generates a
trigger at the center of the period. Setting the ADCTRIG bit in the PWM Control 0 Regis-
ter (PWMCTL0) enables the ADC synchronization.
Synchronized Current-Sense Sample and Hold
The PWM controls the current-sense input sample and hold amplifier. The signal control-
ling the sample/hold is configured to always sample or automatically hold when any or all
the PWM High or Low outputs are in the on state. The current-sense sample and hold is
controlled by the Current-Sense Sample and Hold Control Register (CSSHR0 and
CSSHR1).
PWM Timer and Fault Interrupts
The PWM generates interrupts to the CPU during any of the following events:
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PWM Reload. The interrupt is generated at the end of a PWM period when a PWM regis-
ter reload occurs.
PWM Fault. A fault condition is indicated by asserting any FAULT pins or by the asser-
tion of the comparator.
Fault Detection and Protection
Z16FMC Series MCUs contain hardware and software fault controls that allow rapid deas-
sertion of all enabled PWM output signals. A logic Low on an external fault pin (FAULT0
or FAULT1) or the assertion of the over current comparator forces the PWM outputs to the
predefined off-state.
Similar deassertion of the PWM outputs is accomplished in software by writing to the
PWMOFF bit in the PWM Control 0 Register. The PWM counter continues to operate
while the outputs are deasserted (inactive) due to one of these fault conditions.
The fault inputs are individually enabled through the PWM Fault Control Register. If a
fault condition is detected and the source is enabled, the fault interrupt is generated. The
PWM Fault Status Register (PWMFSTAT) is read to determine which fault source caused
the interrupt.
When a fault is detected and the PWM outputs are disabled, modulator control of the
PWM outputs are reenabled either by the software or by the fault input signal deasserting.
Selection of the reenable method is made using the PWM Fault Control Register (PWM-
FCTL). Configuration of the fault modes and reenable methods allow pulse-by-pulse lim-
iting and hard shutdown. When configured in AUTOMATIC RESTART Mode, the PWM
outputs are reengaged at beginning of the next PWM cycle (master timer value is equal to
0) if all fault signals are deasserted. In a software-controlled restart, all fault inputs must
be deasserted and the fault flags must be cleared.
The fault input pin is Schmitt-triggered. The input signal from the pin as well as the com-
parators pass though an analog filter to reject high-frequency noise.
The logic path from the fault sources to the PWM output is asynchronous ensuring that the
fault inputs forces the PWM outputs to their off-state even if the system clock is stopped.
PWM Operation in CPU HALT Mode
When the CPU is operating in HALT Mode, the PWM continues to operate if it is enabled.
To minimize current in HALT Mode, the PWM must be disabled by clearing the PWMEN
bit to 0.
PWM Operation in CPU STOP Mode
When the CPU is operating in STOP Mode, the PWM is disabled as the system clock
ceases to operate in STOP Mode. The PWM output remains in the same state as they were
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96
prior to entering the STOP Mode. In normal operation, the PWM outputs must be disabled
by software prior to the CPU entering the STOP Mode. A fault condition detected in
STOP Mode forces the PWM outputs to the predefined off-state.
Observing the State of PWM Output Channels
The logic value of the PWM outputs is sampled by reading the PWMIN Register. If a
PWM channel pair is disabled (option bit is not set), the associated PWM outputs are
forced to high impedance and are used as general purpose inputs.
PWM Control Register Definitions
The following sections describe the various PWM control registers.
PWM High and Low Byte Registers
The PWM High and Low Byte registers (PWMH and PWML), shown in Tables 52 and
53, contain the current 12-bit PWM count value. Reads from PWMH stores the value in
PWML to a temporary holding register. A read from PWML always returns this temporary
register value. It is not recommended to write to the PWM High and Low Byte registers
when the PWM is enabled. There are no temporary holding registers for Write operations,
so simultaneous 12-bit writes are not possible. When either the PWM High and Low Byte
registers are written during counting, the 8-bit written value is placed in the counter (High
or Low Byte) at the next clock edge. The counter continues counting from the new value.
Table 52. PWM High Byte Register (PWMH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
Reserved
0h
PWMH
0h
R/W
R/W
ADDR
FF_E38Ch
Bit
Description
Reserved
[7:4]
These bits are reserved and must be programmed to 0000.
[3:0]
PWMH
PWM High Byte
PWMH is one of two bytes, {PWMH[3:0], PWML[7:0]}, which contain the current 12-bit PWM
count value.
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Table 53. PWM Low Byte Register (PWML)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
PWML
01h
R/W
ADDR
FF_E38Dh
Bit
Description
Reserved
[7:4]
These bits are reserved and must be programmed to 0000.
[3:0]
PWML
PWM Low Byte
PWML is one of two bytes, {PWMH[3:0], PWML[7:0]}, which contain the current 12-bit PWM
count value.
PWM Reload High and Low Byte Registers
The PWM Reload High and Low Byte registers (PWMRH and PWMRL), shown in
Tables 54 and 55, store a 12-bit reload value, {PWMRH[3:0], PWMRL[7:0]}. The PWM
reload value is held in buffer registers. The PWM reload value written to the buffer regis-
ters are not used by the PWM generator until the next PWM reload event occurs. Reads
from these registers always return the values from the buffer registers.
Prescaler Reload Value
------------------------------------------------------------
fPWMclk
Edge-Aligned PWM Mode Period =
Center-Aligned PWM Mode Period =
2 Prescaler Reload Value
---------------------------------------------------------------------
fPWMclk
Table 54. PWM Reload High Byte Register (PWMRH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
Reserved
0h
PWMRH
Fh
R/W
R/W
ADDR
FF_E38Eh
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Product Specification
98
Bit
Description
Reserved
[7:4]
These bits are reserved and must be programmed to 0000.
[3:0]
Reload Register High Byte
PWMRH PWMRH is one of two bytes, {PWMRH[3:0], PWMRL[7:0]}, which form the 12-bit reload value,
{PWMRH[3:0], PWMRL[7:0]}. This value sets the PWM period
Table 55. PWM Reload Low Byte Register (PWMRL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
PWMRL
FF
R/W
ADDR
FF_E38Fh
Bit
Description
Reserved
[7:4]
These bits are reserved and must be programmed to 0000.
[3:0]
Reload Register Low Byte
PWMRL PWMRL is one of two bytes, {PWMRH[3:0], PWMRL[7:0]}, which form the 12-bit reload value,
{PWMRH[3:0], PWMRL[7:0]}. This value sets the PWM period.
PWM 0–2 Duty Cycle High and Low Byte Registers
The PWM 0–2 H/L (High Side/Low Side) Duty Cycle High and Low Byte registers
(PWMxDH and PWMxDL), shown in Tables 56 and 57, set the duty cycle of the PWM
signal. This 14-bit signed value is compared to the PWM count value to determine the
PWM output. Reads from these registers always return the values from the temporary
holding registers. The PWM generator does not use the PWM duty cycle value until the
next PWM reload event occurs.
PWM Duty Cycle Value
----------------------------------------------------------
PWM Duty Cycle = 100
PWM Reload Value
Writing a negative value (DUTYH[7] = 1) forces the PWM to be OFF for the full PWM
period. Writing a positive value greater than the 12-bit PWM reload value forces the PWM
to be ON for the full PWM period.
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Product Specification
99
Table 56. PWM 0–2 H/L Duty Cycle High Byte Register (PWMHxDH, PWMLxDH)
Bit
7
SIGN
X
6
5
4
3
2
1
0
Field
RESET
R/W
Reserved
XX
DUTYH
X_XXXX
R/W
R/W
R/W
ADDR
FF_E390h, FF_E392h, FF_E394h, FF_E396h, FF_E398h, FF_E39Ah
Bit
Description
[7]
SIGN
Duty Cycle Sign
0 = Duty cycle is a positive two’s complement number.
1 = Duty cycle is a negative two’s complement number; output is forced to the off-state.
[6:5]
Reserved
These bits are reserved and must be programmed to 00.
[4:0]
PWM Duty Cycle High Byte
DUTYH The two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value (bits 5 and 6 of the High
byte are always 0). The value is compared to the current 12-bit PWM count.
Table 57. PWM 0–2 H/L Duty Cycle Low Byte Register (PWMHxDL, PWMLxDL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DUTYL
XXH
R/W
ADDR
FF_E391h, FF_E393h, FF_E395h, FF_E397h, FF_E399h, FF_E39Bh
Bit
Description
[7:0]
DUTYL
PWM Duty Cycle Low Byte
The two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value (bits 5 and 6 of the High
byte are always 0). The value is compared to the current 12-bit PWM count.
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Product Specification
100
PWM Control 0 Register
The PWM Control 0 Register (PWMCTL0) controls PWM operation.
Table 58. PWM Control 0 Register (PWMCTL0)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
PWMOFF OUTCTL
ALIGN Reserved ADCTRIG Reserved READY PWMEN
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E380h
Bit
Description
[7]
PWMOFF
Place PWM Outputs in an OFF State
0 = Disable modulator control of the PWM pins. Outputs are in a predefined OFF state. This
action is not dependent on the Reload event.
1 = Reenable modulator control of PWM pins at next PWM Reload event.
[6]
OUTCTL
PWM Output Control
0 = PWM outputs are controlled by the pulse-width modulator.
1 = PWM outputs selectively disabled (set to off-state) according to values in the OUTx bits
of the PWMOUT Register.
[5]
ALIGN
PWM Edge Alignment
0 = PWM outputs are edge aligned.
1 = PWM outputs are center aligned.
[4]
Reserved.
This bit is reserved and must be programmed to 0.
[3]
ADCTRIG
ADC Trigger Enable
0 = No ADC trigger pulses.
1 = ADC trigger enabled.
[2]
Reserved.
This bit is reserved and must be programmed to 0.
[1]
READY
Values Ready for Next Reload Event
0 = PWM values (prescale, period and duty cycle) are not ready. Do not use values in hold-
ing registers at next PWM reload event.
1 = PWM values (prescale, period and duty cycle) are ready. Transfer all values from tempo-
rary holding registers to working registers at next PWM reload event.
[0]
PWMEN
PWM Enable
0 = PWM is disabled and enabled PWM output pins are forced to default off-state. PWM
master counter is stopped.
1 = PWM is enabled and PWM output pins are enabled as outputs.
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101
PWM Control 1 Register
The PWM Control 1 Register (PWMCTL1), shown in Table 59, controls portions of
PWM operation.
Table 59. PWM Control 1 Register (PWMCTL1)
Bit
7
6
5
INDEN
0
4
POL45
0
3
POL23
0
2
POL10
0
1
0
Field
RESET
R/W
RLFREQ[1:0]
PRES[1:0]
00
00
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E381h
Bit
Description
Reload Event Frequency
[7:6]
RLFREQ[1:0] This bit field is buffered. Changes to the reload event frequency takes effect at the end of
the current PWM period. Reads always return the bit values from the temporary holding
register.
00 = PWM reload event occurs at the end of every PWM period.
01 = PWM reload event occurs once every two PWM periods.
10 = PWM reload event occurs once every four PWM periods.
11 = PWM reload event occurs once every eight PWM periods.
[5]
INDEN
Independent PWM Mode Enable
The PWM timer should be turned off (PWMCTL0 bit7) prior to modifying any PWM regis-
ters.
0 = PWM outputs operate as three complementary pairs.
1 = PWM outputs operate as six independent channels.
[4]
POL45
PWM2 Polarity
0 = Noninverted polarity for channel pair PWM2.
1 = Invert output polarity for channel pair PWM2.
[3]
POL23
PWM1 Polarity
0 = Noninverted polarity for channel pair PWM1.
1 = Invert output polarity for channel pair PWM1.
[2]
POL10
PWM0 Polarity
0 = Noninverted polarity for channel pair PWM0.
1 = Invert output polarity for channel pair PWM0.
[1:0]
PRES
PWM Prescaler
The prescaler divides down the PWM input clock (either the system clock or the PWMIN
external input). This field is buffered. Changes to this field take effect at the next PWM
reload event. Reads always return the values from the temporary holding register.
00 = Divide by 1.
01 = Divide by 2.
10 = Divide by 4.
11 = Divide by 8.
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Product Specification
102
PWM Deadband Register
The PWM Deadband Register (PWMDB), shown in Table 60, stores the 8-bit PWM dead-
band value. The deadband value determines the number of PWM input cycles to use for
the deadband time for complementary PWM output pairs. When counting PWM input
cycles, the PWM input signal is used directly (no prescaler). The minimum deadband
value is 1. Maximum deadband time is programmed by setting a value of 00h. This regis-
ter is written only once following a System Reset event. All other writes are ignored.
Table 60. PWM Deadband Register (PWMDB)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
PWMDB[7:0]
01h
R/W
ADDR
FF_E382h
Bit
Description
[7:0]
PWM Deadband
PWMDB[7:0] Sets the PWM deadband period for which both PWM outputs of a complementary PWM
output pair are deasserted.
PWM Minimum Pulse Width Filter
The value in the PWMMPF Register, shown in Table 61, determines the minimum width
pulse, either High or Low, generated by the PWM module. The minimum pulse width
period is calculated as:
PWMDB + PWMMPF
TsystemClock PwmPrescale
---------------------------------------------------------------------
=
TminPulseOut
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Table 61. PWM Minimum Pulse Width Filter (PWMMPF)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
PWMMPF[7:0]
00h
R/W
ADDR
FF_E383h
Bit
Description
[7:0]
Minimum Pulse Filter
PWMMPF Sets the minimum allowed output pulse width in PWM clock cycles.
PWM Fault Mask Register
The PWM Fault Mask Register, shown in Table 62, enables individual fault sources.
When an input is asserted, PWM behavior is determined by the PWM Fault Control Reg-
ister (PWMFCTL). Bits 0, 1, 2, and 5 in this register can only be set once; all subsequent
writes will be ignored. The PWM Fault Mask (PWMF) Comparator0 output generates a
PWM fault and the associated fault system exception.
Table 62. PWM Fault Mask Register (PWMFM)
Bit
7
6
5
DBGMSK
0
4
3
2
1
0
Field
RESET
R/W
Reserved
Reserved
F1MASK C0MASK FMASK
00
R
00
R
0
0
0
R/W1*
R/W1*
R/W1*
R/W1*
ADDR
FF_E384h
Note: *This register can only be written to once (W1 only).
Bit
Description
Reserved
[7:6]
These bits are reserved and must be programmed to 00.
[5]
DBGMSK
Debug Entry Fault Mask
0 = Entering CPU DEBUG Mode generates a PWM Fault.
1 = Entering CPU DEBUG Mode does not generate a PWM Fault.
[4:3]
Reserved
These bits are reserved and must be programmed to 00.
[2]
F1MASK
Fault 1 Fault Mask
0 = Fault 1 generates a PWM Fault.
1 = Fault 1 does not generate a PWM Fault.
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Product Specification
104
Bit
Description (Continued)
[1]
C0MASK
Comparator Fault Mask
0 = Comparator generates a PWM Fault.
1 = Comparator does not generate a PWM Fault.
[0]
F0MASK
Fault Pin Mask
0 = Fault 0 pin generates a PWM Fault.
1 = Fault 0 pin does not generate a PWM Fault.
PWM Fault Status Register
The PWM fault status (PWMFSTAT) register provides status of fault inputs and timer
reload. The fault flags indicate the fault source, which is active. If a fault source is masked,
the flag in this register is not set when the source is asserted. The reload flag is set when
the timer compare values are updated. Clear flags by writing a 1 to the flag bits. Fault flag
bits are cleared only if the associated fault source has deasserted.
Table 63. PWM Fault Status Register (PWMFSTAT)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
RLDFlag Reserved DBGFLAG
Reserved
C0FLAG F1FLAG
FFLAG
U
U
0
U
00
R
U
U
R/W1C
R
R/W1C
R/W1C
R/W1C
R/W1C
ADDR
FF_E385h
Bit
Description
Reload Flag
[7]
RLDFLAG This bit is set and latched when a PWM timer reload occurs. Writing a 1 to this bit clears the
flag.
[6]
[5]
Reserved
This bit is reserved and must be programmed to 0.
Debug Flag
DBGFLAG This bit is set and latched when DEBUG Mode is entered. Writing a 1 to this bit clears the
flag.
[4:3]
Reserved
These bits are reserved and must be programmed to 00.
[2]
C0FLAG
Comparator 0 Flag
This bit is set and latched when comparator is asserted. Writing a 1 to this bit clears the flag.
[1]
F1FLAG
FAULT1 Flag
This bit is set and latched when FAULT1 is asserted. Writing a 1 to this bit clears the flag.
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105
Bit
Description (Continued)
Fault Flag
[0]
FFLAG
This bit is set and latched when the fault0 input is asserted. Writing a 1 to this bit clears the
flag.
Note: For this register, W1C means you must write one to clear the flag.
PWM Fault Control Register
The PWM Fault Control Register (PWMFCTL), shown in Table 64, determines how the
PWM recovers from a fault condition. Settings in this register select either an automatic or
a software-controlled PWM restart.
Table 64. PWM Fault Control Register (PWMFCTL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
Reserved DBGRST CMP1INT CMP1RST CMP0INT CMP0RST Fault0INT Fault0RST
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E388h
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6]
Debug Restart
DBGRST
0 = Automatic recovery. PWM resumes control of outputs when all fault sources have deas-
stered and a new PWM period begins.
1 = Software-controlled recovery. PWM resumes control of outputs only after all fault
sources have deasserted, all fault flags have been cleared, and a PWM reload has
occurred.
[5]
Comparator 1 Interrupt
CMP1INT
0 = Interrupt on comparator assertion disabled.
1 = Interrupt on comparator assertion enabled.
[4]
Comparator 1 Restart
CMP1RST 0 = Automatic recovery. PWM resumes control of outputs when all fault sources have been
deasstered.
1 = Software-controlled recovery. PWM resumes control of outputs only after all fault
sources have been deasserted, all fault flags have been cleared, and a PWM reload has
occurred.
[3]
Comparator 0 Interrupt
CMP0INT
0 = Interrupt on comparator 0 assertion disabled.
1 = Interrupt on comparator 0 assertion enabled.
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Product Specification
106
Bit
Description (Continued)
Comparator 1 Restart
[2]
CMP0RST 0 = Automatic recovery. PWM resumes control of outputs when all fault sources have been
deasserted.
1 = Software-controlled recovery. PWM resumes control of outputs only after all fault
sources have been deasserted, all fault flags have been cleared, and a PWM reload has
occurred.
[1]
Fault 0 Interrupt
Fault0INT
0 = Interrupt on Fault0 pin assertion disabled.
1 = Interrupt on Fault0 pin assertion enabled.
[0]
Fault 0 Restart
Fault0RST 0 = Automatic recovery. PWM resumes control of outputs when all fault sources are deass-
tered.
1 = Software-controlled recovery. PWM resumes control of outputs only after all fault
sources have been, deasserted, all fault flags have been cleared, and a PWM reload
has occurred.
PWM Input Sample Register
PWM pin value is sampled by reading this register.
Table 65. PWM Input Sample Register (PWMIN)
Bit
7
6
FAULT
0
5
4
IN2H
0
3
2
IN1H
0
1
0
IN0H
0
Field
RESET
R/W
Reserved
IN2L
0
IN1L
0
IN0L
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E386h
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6]
FAULT
Sample Fault0 Pin
0 = A Low-level signal was read on the fault pin.
1 = A High-level signal was read on the fault pin.
[5:0]
Sample PWM Pins
IN2L/IN2H/ 0 = A Low-level signal was read on the pins.
IN1L/IN1H/ 1 = A High-level signal was read on the pins.
IN0L/IN0H
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Z16FMC Series Motor Control MCUs
Product Specification
107
PWM Output Control Register
The PWM Output Control Register (PWMOUT) enables modulator control of the six
PWM output signals. Output control is enabled by the OUTCTL bit in the PWMCTL0
Register. The PWM continues to operate but has no effect on the disabled PWM pins. If a
fault condition is detected, all PWM outputs are forced to their selected off state.
Table 66. PWM Output Control Register (PWMOUT)
Bit
7
6
5
OUT2L
0
4
OUT2H
0
3
OUT1L
0
2
OUT1H
0
1
OUT0L
0
0
OUT0H
0
Field
RESET
R/W
Reserved
0
0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E387h
Bit
Description
Reserved
[7:6]
These bits are reserved and must be programmed to 00.
[5, 3, 1] PWM Output 2 Low
OUT2L/ 0 = PWM 2L/1L/0L output configuration; the PWM 2L/1L/0L output signal is enabled and con-
OUT1L/
OUT0L
trolled by the PWM.
1 = PWM 2L/1L/0L output signal is in a low-side off state.
[4, 2, 0] PWM Output 2 High
OUT2H/ 0 = PWM 2H/1H/0H output configuration; the PWM 2H/1H/0H output signal is enabled and
OUT1H/
controlled by the PWM.
OUT0H 1 = PWM 2H/1H/0H output signal is in a high-side off state.
Current-Sense Sample and Hold Control Registers
The Current-Sense Sample/Hold Control Register defines the behavior of the dedicated
current sense sample and hold inputs to the ADC from the operational amplifier. These
input hold the current input value whenever all high-side outputs or all low-side outputs
are in the on-state. The register bits control which PWM outputs must be asserted to acti-
vate the internal hold signal. Disabling the HEN, LEN, NHEN and NLEN bits allows soft-
ware control of the input sample/hold by writing the SHPOL bit.
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Table 67. Current-Sense Sample and Hold Control Register (CSSHR0 and CSSHR1)
Bit
7
SHPOL
0
6
5
NHEN
0
4
3
NLEN
0
2
1
0
Field
RESET
R/W
HEN
0
LEN
0
SHPWM2 SHPWM1 SHPWM0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E38Ah and FF_E38Bh
Bit
Description
[7]
SHPOL
Sample Hold Polarity
0 = Hold when terms are active.
1 = Hold when terms are not active.
[6]
HEN
High Side Active Enable
0 = Ignore Product of PWMH0, PWMH1, PWMH2 in sample/hold equation.
1 = Hold when PWMH0, PWMH1, PWMH2 are all active.
[5]
NHEN
High Side Inactive Enable
0 = Ignore product of PWMH0, PWMH1, PWMH2 in sample/hold equation.
1 = Hold when are all active.
[4]
LEN
Low Side Active Enable
0 = Ignore product of PWML0, PWML1, PWML2 in sample/hold equation.
1 = Hold when PWML0, PWML1, PWML2 are all active.
[3]
NLEN
Low Side Inactive Enable
0 = Ignore product of PWML0, PWML1, PWML2 in sample/hold equation.
1 = Hold when PWML0, PWML1, PWML2 are all active.
[2]
SHPWM2
PWM Channel2 Sample/Hold Enable
0 = Channel 2 terms are not used in sample/hold equation.
1 = Channel 2 terms are used in sample/hold equation.
[1]
SHPWM1
PWM Channel1 Sample/Hold Equation
0 = Channel 1 terms are not used in sample/hold equation.
1 = Channel 1 terms are used in sample/hold equation.
[0]
SHPWM0
PWM Channel0 Sample/Hold Equation
0 = Channel 0 terms are not used in sample/hold equation.
1 = Channel 0 terms are used in sample/hold equation.
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Product Specification
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Watchdog Timer
The Watchdog Timer (WDT) helps protect against corrupt or unreliable software, power
faults and other system-level problems which place the Z16FMC device into unsuitable
operating states.
The WDT includes the following features:
•
•
•
On-chip RC oscillator
A selectable time-out response: short reset or system exception
16-bit programmable time-out value
Operation
The WDT is a retriggerable one-shot timer that resets or interrupts the Z16FMC device
when the WDT reaches its terminal count. The WDT uses its own dedicated on-chip RC
oscillator as its clock source. The WDT features only two modes of operation: on and off.
After it is enabled, the WDT always counts and must be refreshed to prevent a time-out.
An enable is performed by executing the WDT instruction or by setting the WDT_AO
option bit. The WDT_AO bit enables the WDT to operate all the time, even if a WDT
instruction has not been executed.
To minimize power consumption, the RC oscillator is disabled. The RC oscillator is dis-
abled by clearing the WDTEN bit in the Oscillator Control Register (see page 301). If the
RC oscillator is disabled, the WDT will not operate.
The WDT is a 16-bit reloadable downcounter that uses two 8-bit registers in the CPU reg-
ister space to set the reload value. The nominal WDT time-out period is calculated by the
following equation.
WDT Reload Value
-----------------------------------------------
WDT Time-out Period (ms) =
10
In this equation, the WDT reload value is the decimal value of the 16-bit value furnished
by {WDTH[7:0], WDTL[7:0]}, and the typical Watchdog Timer RC oscillator frequency
is 10kHz. Table 68 provides information about approximate time-out delays for the mini-
mum, default and maximum WDT reload values.
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Table 68. Watchdog Timer Approximate Time-Out Delays
Approximate Time-Out Delay
(with 10kHz Typical WDT Oscillator Frequency)
WDT Reload Value WDT Reload Value
(Hex)
0400
FFFF
(Decimal)
Typical
Description
1024
102.4ms
6.55 s
Reset value time-out delay
Maximum time-out delay
65,536
Watchdog Timer Refresh
When enabled first, the WDT is loaded with the value in the Watchdog Timer Reload reg-
isters. The WDT next counts down to 0000hunless a WDT instruction is executed by the
CPU. Execution of the WDT instruction causes the downcounter to be reloaded with the
WDT reload value stored in the Watchdog Timer Reload registers. Counting resumes fol-
lowing the reload operation.
When the Z16FMC device is operating in DEBUG Mode (through the OCD), the WDT is
continuously refreshed to prevent spurious WDT time-outs.
Watchdog Timer Time-Out Response
The WDT times out when the counter reaches 0000h. A time-out of the WDT generates
either a system exception or a short reset. The WDT_RES option bit determines the time-
out response of the WDT. For information about programming of the WDT_RES option
bit, see the Option Bit chapter on page 260.
WDT System Exception in Normal Operation
If configured to generate a system exception when a time-out occurs, the WDT issues an
exception request to the interrupt controller. The CPU responds to the request by fetching
the System Exception vector and executing code from the vector address. After time-out
and system exception generation, the WDT is reloaded automatically and continues count-
ing.
WDT System Exception in STOP Mode
If configured to generate a system exception when a time-out occurs and the Z16FMC
device is in STOP Mode, the WDT automatically initiates a Stop-Mode Recovery and
generates a system exception request. Both the WDT status bit and the stop bit in the Reset
Status and Control Register (see page 39) are set to 1 following WDT time-out in STOP
Mode. For detailed information, see the Reset and Stop-Mode Recovery chapter on page
33.
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Following completion of the Stop-Mode Recovery, the CPU responds to the system excep-
tion request by fetching the System Exception vector and executing code from the vector
address.
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the WDT forces the device into
the Reset state. The WDT status bit in the Reset Status and Control Register (see page 39)
is set to 1. For more information about Reset and the WDT status bit, see the the Reset and
Stop-Mode Recovery chapter on page 33. Following a Reset sequence, the WDT Counter
is initialized with its reset value.
WDT Reset in STOP Mode
If enabled in STOP Mode and configured to generate a Reset when a time-out occurs and
the device is in STOP Mode, the WDT initiates a Stop-Mode Recovery. Both the WDT
status bit and the stop bit in the Reset Status and Control Register (see page 39) are set to 1
following WDT time-out in STOP Mode. For detailed information, see the Reset and
Stop-Mode Recovery chapter on page 33.
Watchdog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watchdog Timer Reload High (WDTH) register
address unlocks the two Watchdog Timer Reload registers (WDTH and WDTL) to allow
changes to the time-out period. These Write operations to the WDTH Register address
produce no effect on the bits in the WDTH Register. The locking mechanism prevents spu-
rious writes to the reload registers.
The following sequence is required to unlock the Watchdog Timer Reload registers
(WDTH and WDTL) for write access:
1. Write 55hto the Watchdog Timer Reload High register (WDTH).
2. Write AAhto the Watchdog Timer reload high register (WDTH).
3. Write the appropriate value to the Watchdog Timer reload high register (WDTH).
4. Write the appropriate value to the Watchdog Timer reload low register (WDTL).
All steps of the WDT reload unlock sequence must be written in the order just listed. The
value in the Watchdog Timer Reload registers is loaded into the counter every time a WDT
instruction is executed.
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Watchdog Timer Register Definitions
Watchdog Timer Reload High and Low Byte Registers
The Watchdog Timer Reload High and Low Byte registers (WDTH, WDTL), shown in
Tables 69 and 70, form the 16-bit reload value that is loaded into the WDT when a WDT
instruction executes. The 16-bit reload value is {WDTH[7:0], WDTL[7:0]}. Writing to
these registers following the unlock sequence sets the appropriate reload value. Reading
from these registers returns the current WDT count value.
The 16-bit WDT reload value must not be set to a value less than 0004h.
Caution:
Table 69. Watchdog Timer Reload High Byte Register (WDTH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
WDTH
0
0
0
0
0
1
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
ADDR
FF_E042h
Note: *Read returns the current WDT count value; write sets the appropriate reload value.
Bit
Description
[15:8]
WDTH
WDT Reload High Byte
Most significant byte (MSB); bits[15:8] of the 16-bit WDT reload value.
Table 70. Watchdog Timer Reload Low Byte Register (WDTL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
WDTL
0
0
0
0
0
0
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
ADDR
FF_E043h
Note: *Read returns the current WDT count value; write sets the appropriate reload value.
Bit
Description
[7:0]
WDTL
WDT Reload Low Byte
Least significant byte (LSB); bits[7:0] of the 16-bit WDT reload value.
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Product Specification
113
LIN-UART
The Local Interconnect Network Universal Asynchronous Receiver/Transmitters (LIN-
UART) are full-duplex communication channels capable of handling asynchronous data
transfers in standard UART applications as well as providing LIN protocol support.
Features of the LIN-UARTs include:
•
•
•
•
8-bit asynchronous data transfer
Selectable even and odd-parity generation and checking
Option of one or two stop bits
Selectable MULTIPROCESSOR (9-Bit) Mode with three configurable interrupt
schemes
•
•
•
Separate transmit and receive interrupts or DMA requests
Framing, parity, overrun and break detection
16-bit Baud Rate Generator (BRG), which functions as a general-purpose timer with
interrupt
•
•
Driver enable output for external bus transceivers
LIN protocol support for both MASTER and SLAVE modes:
–
–
–
Break generation and detection
Selectable slave autobaud
Check Tx vs. Rx data when sending
•
Configurable digital noise filter on receive data line
Architecture
The LIN-UART consists of three primary functional blocks: transmitter, receiver and
BRG. The LIN-UART’s transmitter and receiver function independently but use the same
baud rate and data format. The basic UART operation is enhanced by the noise filter and
IrDA blocks. Figure 14 displays the LIN-UART architecture.
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Parity Checker
Receive Shifter
Rx IRQ
RxDmaReq
Receiver Control
with Address Compare
RxD
Receive Data
Register
Control Registers
System Bus
Transmit Data
Register
Status Registers
Baud Rate
Generator
Transmit Shift
Register
TxD
Transmitter Control
Tx IRQ
TxDmaReq
Parity Generator
CTS
DE
Figure 14. LIN-UART Block Diagram
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Operation
This section discusses the operational aspects of the Z16FMC Series LIN-UART feature,
and presents tabled bit descriptions for the LIN-UART transmit, receive, status, mode
select, multiprocessor control, noise filter, status, baud rate, and control registers.
Data Format for Standard UART Modes
The LIN-UART always transmits and receives data in an 8-bit data format with the first bit
being least-significant bit. An even- or odd-parity bit or multiprocessor address/data bit is
optionally added to the data stream. Each character begins with an active Low start bit and
ends with either 1 or 2 active High stop bits. Figures 15 and 16 display the asynchronous
data format employed by the LIN-UART without parity and with parity, respectively.
Data Field
Stop Bit(s)
Idle State
of Line
lsb
msb
Bit7
1
0
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
1
2
Figure 15. LIN-UART Asynchronous Data Format without Parity
Data Field
Stop Bit(s)
Idle State
of Line
lsb
msb
1
0
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7 Parity
1
2
Figure 16. LIN-UART Asynchronous Data Format with Parity
Transmitting Data using the Polled Method
Observe the following steps to transmit data using the polled operating method:
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1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate
baud rate.
2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. If MULTIPROCESSOR Mode is required, write to the LIN-UART Control 1 Register
to enable MULTIPROCESSOR (9-Bit) Mode functions. Set the MULTIPROCESSOR
Mode select (MPEN) to enable MULTIPROCESSOR Mode.
4. Write to the LIN-UART Control 0 Register to:
a. Set the transmit enable bit (TEN) to enable the LIN-UART for data transmission.
b. If parity is required and MULTIPROCESSOR Mode is not enabled, set the parity
enable bit (PEN) and select either even- or odd parity (PSEL).
c. Set or clear the CTSE bit to enable or disable control from the remote receiver
using the CTS pin.
5. Check the TDRE bit in the LIN-UART Status 0 Register to determine if the Transmit
Data Register is empty (indicated by a 1). If this register is empty, continue to Step 6.
If the Transmit Data Register is full (indicated by a 0), continue to monitor the TDRE
bit until the Transmit Data Register becomes available to receive new data.
6. If in MULTIPROCESSOR Mode, write the LIN-UART Control 1 Register to select
the outgoing address bit. Set the multiprocessor bit transmitter (MPBT) if sending an
address byte; clear it if sending a data byte.
7. Write the data byte to the LIN-UART Transmit Data Register. The transmitter
automatically transfers the data to the Transmit Shift Register and transmits the data.
8. If MULTIPROCESSOR Mode is required and MULTIPROCESSOR Mode is
enabled, make any changes to the multiprocessor bit transmitter (MPBT) value.
9. To transmit additional bytes, return to Step 4.
Transmitting Data Using Interrupt-Driven Method
The LIN-UART transmitter interrupt indicates the availability of the Transmit Data Regis-
ter to accept new data for transmission. Observe the following steps to configure the LIN-
UART for interrupt-driven data transmission:
1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate
baud rate.
2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
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4. Write to the interrupt control registers to enable the LIN-UART transmitter interrupt
and set the appropriate priority.
5. If MULTIPROCESSOR Mode is required, write to the LIN-UART Control 1 Register
to enable MULTIPROCESSOR (9-Bit) Mode functions. Set the MULTIPROCESSOR
Mode Select (MPEN) to enable MULTIPROCESSOR Mode.
6. Write to the LIN-UART Control 0 Register to:
a. Set the transmit enable bit (TEN) to enable the LIN-UART for data transmission
b. Enable parity, if MULTIPROCESSOR Mode is not enabled and select either even
or odd parity.
c. Set or clear the CTSE bit to enable or disable control from the remote receiver
through the CTS pin.
7. Execute an EI instruction to enable interrupts.
The LIN-UART is now configured for interrupt-driven data transmission. As the LIN-
UART Transmit Data Register is empty, an interrupt is generated immediately. When the
LIN-UART transmit interrupt is detected and there is transmit data ready to send, the asso-
ciated interrupt service rouISR performs the following:
1. If operating in MULTIPROCESSOR Mode, write the LIN-UART Control 1 Register
to select the outgoing address bit:
a. Set the multiprocessor bit transmitter (MPBT) if sending an address byte; clear it
if sending a data byte.
2. Write the data byte to the LIN-UART Transmit Data Register. The transmitter
automatically transfers the data to the Transmit Shift Register and transmits the data.
3. Execute the IRET instruction to return from the interrupt service routine and waits for
the Transmit Data Register to again become empty.
If a transmit interrupt occurs and there is no transmit data ready to send, the interrupt ser-
vice routine executes the IRET instruction. When the application does have data to trans-
mit, software sets the appropriate interrupt request bit in the interrupt controller to initiate
a new transmit interrupt. Another alternative would be for software to write the data to the
Transmit Data Register instead of invoking the ISR.
Receiving Data Using Polled Method
Observe the following steps to configure the LIN-UART for polled data reception:
1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate
baud rate.
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2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Write to the LIN-UART Control 1 Register to enable MULTIPROCESSOR Mode
functions.
4. Write to the LIN-UART Control 0 Register to:
a. Set the receive enable bit (REN) to enable the LIN-UART for data reception.
b. Enable parity, if MULTIPROCESSOR Mode is not enabled and select either even
or odd parity.
5. Check the RDA bit in the LIN-UART Status 0 Register to determine if the Receive
Data Register contains a valid data byte (indicated by a 1). If RDA is set to 1 to
indicate available data, continue to Step 6. If the Receive Data Register is empty
(indicated by 0), continue to monitor the RDA bit awaiting reception of the valid data.
6. Read data from the LIN-UART Receive Data Register. If operating in
MULTIPROCESSOR (9-Bit) Mode, further actions are required depending on the
MULTIPROCESSOR Mode bits MPMD[1:0].
7. Return to Step 5 to receive additional data.
Receiving Data using the Interrupt-Driven Method
The LIN-UART receiver interrupt indicates the availability of new data (as well as error
conditions). Observe the following steps to configure the LIN-UART receiver for inter-
rupt-driven operation:
1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate
baud rate.
2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the interrupt control registers to enable the LIN-UART receiver interrupt and
set the appropriate priority.
5. Clear the LIN-UART receiver interrupt in the applicable Interrupt Request Register.
6. Write to the LIN-UART Control 1 Register to enable MULTIPROCESSOR (9-Bit)
Mode functions:
a. Set the MULTIPROCESSOR Mode select (MPEN) to enable MULTIPROCES-
SOR Mode.
b. Set the MULTIPROCESSOR Mode bits, MPMD[1:0], to select the appropriate
address matching scheme.
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c. Configure the LIN-UART to interrupt on received data and errors or errors only
(interrupt on errors only is unlikely to be useful for Z16FMC Series devices with-
out a DMA block).
7. Write the device address to the address compare register (automatic multiprocessor
modes only).
8. Write to the LIN-UART Control 0 Register to:
a. Set the receive enable bit (REN) to enable the LIN-UART for data reception
b. Enable parity, if MULTIPROCESSOR Mode is not enabled and select either
even- or odd-parity.
9. Execute an EI instruction to enable interrupts.
The LIN-UART is now configured for interrupt-driven data reception. When the LIN-
UART receiver interrupt is detected, the associated ISR performs the following:
1. Check the LIN-UART Status 0 Register to determine whether the source of the inter-
rupt is error, break, or received data.
2. If the interrupt was due to data available, read the data from the LIN-UART Receive
Data Register. If operating in MULTIPROCESSOR (9-Bit) Mode, further actions are
required depending on the MULTIPROCESSOR Mode bits MPMD[1:0].
3. Execute the IRET instruction to return from the ISR and await more data.
Clear To Send Operation
The clear to send (CTS) pin, if enabled by the CTSE bit of the LIN-UART Control 0 Reg-
ister, performs flow control on the outgoing transmit data stream. The CTS input pin is
sampled one system clock before beginning any new character transmission. To delay
transmission of the next data character, an external receiver must deassert CTS at least one
system clock cycle before a new data transmission begins. For multiple character trans-
missions, this operation is typically performed during the stop bit transmission. If CTS
deasserts in the middle of a character transmission, the current character is sent com-
pletely.
External Driver Enable
The LIN-UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This
feature reduces the software overhead associated with using a GPIO pin to control the
transceiver when communicating on a multi-transceiver bus such as RS-485.
Driver Enable is a programmable polarity signal which envelopes the entire transmitted
data frame including parity and stop bits as illustrated in Figure 17. The DE signal asserts
when a byte is written to the LIN-UART Transmit Data Register. The DE signal asserts at
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least one bit period and no greater than two bit periods before the start bit is transmitted.
This allows a set-up time to enable the transceiver. The DE signal deasserts one system
clock period after the final stop bit is transmitted. This one system clock delay allows both
time for data to clear the transceiver before disabling it, as well as the ability to determine
if another character follows the current character. In the event of back to back characters
(new data must be written to the Transmit Data Register before the previous character is
completely transmitted) the DE signal is not deasserted between characters. The DEPOL
bit in the LIN-UART Control Register 1 sets the polarity of the DE signal.
1
DE
0
Data Field
Stop Bit
Idle State
of Line
lsb
msb
1
0
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7 Parity
1
Figure 17. LIN-UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
The DE to start bit set-up time is calculated as follows:
1
2
-------------------------------------
-------------------------------------
DE to Start Bit Setup Time (s)
Baud Rate (Hz)
Baud Rate (Hz)
LIN-UART Special Modes
The special modes of the LIN-UART:
MULTIPROCESSOR Mode
LIN Mode
•
•
The LIN-UART has a common control register (Control 0), which has a unique register
address and several mode-specific control registers (multiprocessor control, noise filter
control and LIN control) which share a common register address (Control 1). When the
Control 1 address is read or written, the Mode Select (MSEL[2:0]) field of the Mode
Select and Status Register determines which physical register is accessed. Similarly, there
are mode-specific status registers, one of which is returned when the Status 0 Register is
read, depending on the MSEL field.
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MULTIPROCESSOR (9-Bit) Mode
The LIN-UART features a MULTIPROCESSOR (9-Bit) Mode which uses an extra (9th)
bit for selective communication when a number of processors share a common UART bus.
In MULTIPROCESSOR Mode (also referred to as 9-Bit Mode), the multiprocessor bit
(MP) is transmitted immediately following the 8 bits of data and immediately preceding
the stop bit(s) as illustrated in Figure 18.
Data Field
Stop Bit(s)
Idle State
of Line
lsb
msb
Bit7
1
0
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
MP
1
2
Figure 18. LIN-UART Asynchronous MULTIPROCESSOR Mode Data Format
In MULTIPROCESSOR (9-Bit) Mode, the Parity bit location (9th bit) becomes the MUL-
TIPROCESSOR control bit. The LIN-UART Control 1 and Status 1 registers provide
MULTIPROCESSOR (9-Bit) Mode control and status information. If an automatic
address matching scheme is enabled, the LIN-UART Address Compare Register holds the
network address of the device.
MULTIPROCESSOR (9-Bit) Mode Receive Interrupts
When MULTIPROCESSOR Mode is enabled, the LIN-UART processes only frames
addressed to it. You can determine whether a frame of data is addressed to the LIN-UART
is made in hardware, software or a combination of the two, depending on the multiproces-
sor configuration bits. In general, the address compare feature reduces the load on the
CPU because it does not need to access the LIN-UART when it receives data directed to
other devices on the multi-node network. The following 3 MULTIPROCESSOR modes
are available in the hardware:
1. Interrupt on all address bytes.
2. Interrupt on matched address bytes and correctly framed data bytes.
3. Interrupt only on correctly framed data bytes.
These modes are selected with MPMD[1:0] in the LIN-UART Control 1 Register. For all
MULTIPROCESSOR modes, bit MPEN of the LIN-UART Control 1 Register must be set
to 1.
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The first scheme is enabled by writing 01bto MPMD[1:0]. In this mode, all incoming
address bytes cause an interrupt, while data bytes never cause an interrupt. The ISR checks
the address byte which triggered the interrupt. If it matches the LIN-UART address, the
software clears MPMD[0]. At this point, each new incoming byte interrupts the CPU. The
software determines the end of the frame and checks for it by reading the MPRX bit of the
LIN-UART Status 1 Register for each incoming byte. If MPRX=1, a new frame has
begun. If the address of this new frame is different from the LIN-UART’s address, then
MPMD[0] must be set to 1 by software, causing the LIN-UART interrupts to go inactive
until the next address byte. If the address of the new frame matches the LIN-UART
address, then the data in the new frame is processed.
The second scheme is enabled by setting MPMD[1:0] to 10band writing the LIN-UART’s
address into the LIN-UART Address Compare Register. This mode introduces more hard-
ware control, interrupting only on frames which match the address of LIN-UART. When
an incoming address byte does not match the address of LIN-UART, it is ignored. All suc-
cessive data bytes in this frame are also ignored. When a matching address byte occurs, an
interrupt is issued and further interrupts occur on each successive data byte. The first data
byte in the frame has NEWFRM = 1 in the LIN-UART Status 1 Register. When the next
address byte occurs, the hardware compares it to the address of LIN-UART. If there is a
match, the interrupt occurs and the NEWFRM bit is set for the first byte of the new frame.
If there is no match, the LIN-UART ignores all incoming bytes until the next address
match.
The third scheme is enabled by setting MPMD[1:0] to 11band by writing the address of
LIN-UART into the LIN-UART Address Compare Register. This mode is identical to the
second scheme, except that there are no interrupts on address bytes. The first data byte of
each frame remains accompanied by a NEWFRM assertion.
LIN PROTOCOL Mode
The LIN protocol, as supported by the LIN-UART module, is defined in revision 2.0 of
the LIN specification package. This LIN protocol specification covers all aspects of trans-
ferring information between LIN master and slave devices using message frames includ-
ing error detection and recovery, sleep mode, and wake-up from sleep mode. The LIN-
UART hardware in LIN Mode provides character transfers to support the LIN protocol
including break transmission and detection, WAKE-UP transmission and detection and
slave autobauding. Part of the error detection of the LIN protocol is for both master and
slave devices to monitor their receive data when transmitting. If the receive and transmit
data streams do not match, the LIN-UART asserts the PLE bit (a physical-layer error bit in
the Status 0 Register). The message frame time-out aspect of the protocol is left to soft-
ware, requiring the use of an additional general purpose timer. The LIN Mode of the LIN-
UART does not provide any hardware support for computing/verifying the checksum field
or to verify the contents of the identifier field. These fields are treated as data and are not
interpreted by the hardware.
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The LIN bus contains a single master and one or more slaves. The LIN master is responsi-
ble for transmitting the message frame header which consists of the Break, Synch, and
Identifier fields. Either the master or one of the slaves transmits the associated response
section of the message, which consists of data characters followed by a checksum charac-
ter.
In LIN Mode, the interrupts defined for normal UART operation still apply with the fol-
lowing changes:
•
Parity error (a PE bit in the Status 0 Register) is redefined as the Physical Layer Error
(PLE) bit. This PLE bit indicates that receive data does not match transmit data when
the LIN-UART is transmitting. This applies to both MASTER and SLAVE OPERAT-
ING modes.
•
The break detect interrupt (BRKD bit in the Status 0 Register) indicates when a break
is detected by the slave (break condition for at least 11 bit-times). Software uses this
interrupt to start a timer checking for message frame time-out. The duration of the
break is read in the RxBreakLength[3:0] field of the Mode Status Register.
•
•
The break detect interrupt (BRKD bit in Status 0 Register) indicates when a wake-up
message has been received if the LIN-UART is in a LINSLEEP state.
In LIN SLAVE Mode, if the BRG counter overflows while measuring the autobaud pe-
riod (start bit to beginning of bit 7 of autobaud character) an overrun error is indicated
(OE bit in the Status 0 Register). In this case, software sets the LinState field back to
10b, where the slave ignores the current message and waits for the next break signal.
The baud reload high and low registers are not updated by hardware if this autobaud
error occurs. The OE bit is also set if a data overrun error occurs.
LIN System Clock Requirements
The LIN master provides the timing reference for the LIN network and is required to have
a clock source with a tolerance of ±0.5%. A slave with autobaud capability is required to
have a baud clock matching the master oscillator within ±14%. The slave nodes autobaud
to lock onto the master timing reference with an accuracy of ±2%. If a slave does not con-
tain autobaud capability, it must include a baud clock which deviates from the masters by
no more than ±1.5%. These accuracy requirements must include effects such as voltage
and temperature drift during operation.
Before sending or receiving messages, the baud reload High/Low registers must be initial-
ized. Unlike standard UART modes, the baud reload High/Low registers must be loaded
with the baud interval rather than 1/16 of the baud interval.
To autobaud with the required accuracy, the LIN slave system clock must be at least 100
times the baud rate.
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LIN Mode Initialization and Operation
The LIN PROTOCOL Mode is selected by setting either the LIN master (LMST) or LIN
slave (LSLV) and, optionally for the LIN slave, the autobaud enable (ABEN) bits in the
LIN Control Register. To access the LIN Control Register, the Mode Select (MSEL) field
of the LIN-UART Mode Select/Status Register must be 010b. The LIN-UART Control 0
Register must be initialized with TEN = 1, REN = 1, all other bits = 0.
In addition to the LMST, LSLV and ABEN bits in the LIN Control Register, a Lin-
State[1:0] field exists that defines the current state of the LIN logic. This field is initially
set by the software. In the LIN SLAVE Mode, the LinState field is updated by hardware as
the slave moves through the Wait for Break, AutoBaud and Active states.
The noise filter is also required to be enabled and configured when interfacing to a LIN
bus.
LIN MASTER Mode Operation
LIN MASTER Mode is selected by setting the bits LMST = 1, LSLV = 0, ABEN = 0, Lin-
State[1:0] = 11b. If the LIN bus protocol indicates the bus is required go into the LIN
Sleep state, the LinState[1:0] bits must be set = 00bby the software.
The break is the first part of the message frame transmitted by the master, consisting of at
least 13 bit periods of logical zero on the LIN bus. During initialization of the LIN master,
the duration (in bit-times) of the break is written to the TxBreakLength field of the LIN
Control Register. The transmission of the break is performed by setting the SBRK bit in
the Control 0 Register. The LIN-UART starts the break after the SBRK bit is set and any
character transmission currently underway has completed. The SBRK bit is deasserted by
hardware after the break is completed.
The Synch character is transmitted by writing a 55hto the Transmit Data Register (TDRE
must be 1 before writing). The Synch character is not transmitted by the hardware until
after the break is complete.
The Identifier character is transmitted by writing the appropriate value to the Transmit
Data Register (TDRE must be 1 before writing).
If the master is sending the response portion of the message, these data and checksum
characters are written to the Transmit Data Register when the TDRE bit asserts.
If the Transmit Data Register is written after TDRE asserts, but before TXE asserts, the
hardware inserts one or two stop bits between each character as determined by the stop bit
in the Control 0 Register. Additional idle time occurs between characters if TXE asserts
before the next character is written.
LIN SLEEP Mode
While the LIN bus is in a Sleep state, the CPU is in either low-power STOP Mode, in
HALT Mode, or in a normal operational state. Any device on the LIN bus issues a wake-
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up message (transmit an 80hcharacter) if it needs the master to initiate a LIN message
frame. Following the wake-up message, the master wakes up and initiates a new message.
If the CPU is in STOP Mode, the LIN-UART is not active and the wake-up message must
be detected by a GPIO edge detect Stop-Mode Recovery. The duration of the Stop-Mode
Recovery sequence may preclude making an accurate measurement of the wake-up mes-
sage duration.
If the CPU is in HALT Mode or in an operational mode, the LIN-UART (if enabled) times
the duration of the wake-up and provides an interrupt following the end of the break
sequence if the duration is 4 bit-times. The total duration of the wake-up message in bit-
times is obtained by reading the RxBreakLength field in the Mode Status Register. After a
wake-up message is detected, the LIN-UART is placed (by software) into either Lin Mas-
ter or Lin Slave Wait for Break states as appropriate. If the break duration exceeds fifteen
bit-times, the RxBreakLength field contains the value Fh.
Lin Sleep state is selected by software setting LinState[1:0] = 00. The decision to move
from an active state to sleep state is based on the LIN messages as interpreted by the soft-
ware.
LIN Slave Operation
LIN SLAVE Mode is selected by setting the bits LMST = 0, LSLV = 1, ABEN = 1 or 0
and LinState[1:0] = 01b (Wait for Break state). The LIN slave detects the start of a new
message by the break which appears to the slave as a break of at least 11 bit-times in dura-
tion. The LIN-UART detects the break and generates an interrupt to the CPU. The dura-
tion of the break is observable in the RxBreakLength field of the Mode Status Register. A
break of less than 11 bit-times in duration does not generate a break interrupt when the
LIN-UART is in a Wait for Break state. If the break duration exceeds 15 bit-times, the
RxBreakLength field contains the value Fh.
Following the break, the LIN-UART hardware automatically transits to the autobaud state,
where it autobauds by timing the duration of the first 8 bit-times of the Synch character as
defined in the standard. At the end of the autobaud period, the duration measured by the
BRG counter (auto baud period divided by 8) is automatically transferred to the baud
reload high and low registers if the ABEN bit of the LIN Control Register is set. If the
BRG counter overflows before reaching the start of bit 7 in the autobaud sequence the
autobaud overrun error interrupt occurs, the OE bit in the Status 0 Register is set and the
baud reload registers are not updated. To autobaud within 2% of the master’s baud rate,
the slave system clock must be minimum 100 times the baud rate. To avoid an autobaud
overrun error, the system clock must not be greater than 219 times the baud rate (16 bit
counter following 3-bit prescaler when counting the 8 bit-times of the autobaud sequence).
Following the Synch character, the LIN-UART hardware transits to the active state, where
the Identifier character is received and the characters of the response section of the mes-
sage are sent or received. The slave remains in the active state until a break is received or
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the software forces a state change. When it is in active State (autobaud has completed), a
break of 10 or more bit-times is recognized and a transition to the autobaud state is caused.
LIN-UART Interrupts
The LIN-UART features separate interrupts for the transmitter and receiver. In addition,
when the LIN-UART primary functionality is disabled, the BRG also functions as a basic
timer with interrupt capability.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans-
mission. The TDRE interrupt occurs when the transmitter is initially enabled and after the
Transmit Shift Register has shifted the first bit of a character out. At this point, the Trans-
mit Data Register is written with the next character to send. This provides 7 bit periods of
latency to load the Transmit Data Register before the Transmit Shift Register completes
shifting the current character. Writing to the LIN-UART Transmit Data Register clears the
TDRE bit to 0.
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
•
A data byte is received and is available in the LIN-UART Receive Data Register. This
interrupt is disabled independent of the other receiver interrupt sources using the
RDAIRQ bit (this feature is useful in devices, which support DMA). The received data
interrupt occurs after the receive character is placed in the Receive Data Register. To
avoid an overrun error, the software responds to this received data available condition
before the next character is completely received.
Note: In MULTIPROCESSOR Mode (MPEN = 1), the receive data interrupts are dependent on
the multiprocessor configuration and the most recent address byte.
•
•
•
•
A break is received.
A receive data overrun or LIN slave autobaud overrun error is detected.
A data framing error is detected.
A parity error is detected (physical layer error in LIN Mode).
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LIN-UART Overrun Errors
When an overrun error condition occurs, the LIN-UART prevents overwriting of the valid
data currently in the Receive Data Register. The break detect and overrun status bits are
not displayed until the valid data is read.
When the valid data is read, the OE bit of the Status 0 Register is updated to indicate the
overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that
the Receive Data Register contains a data byte. However, because the overrun error
occurred, this byte may not contain valid data and must be ignored. The BRKD bit indi-
cates if the overrun is caused due to a break condition on the line. After reading the status
byte indicating an overrun error, the Receive Data Register must be read again to clear the
error bits in the LIN-UART Status 0 Register.
In LIN Mode, an overrun error is signaled for receive data overruns as described above
and in the LIN Slave, if the BRG counter overflows during the autobaud sequence (the
ATB bit will also be set in this case). There is no data associated with the autobaud over-
flow interrupt, however the Receive Data Register must be read to clear the OE bit. In this
case software must write 10bto the LinState field, forcing the LIN slave back to Wait for
break state.
LIN-UART Data and Error Handling Procedure
Figure 19 displays the recommended procedure for use in LIN-UART receiver interrupt
service routines.
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Receiver
Ready
Receiver
Interrupt
Read Status
No
Errors?
Yes
Read Data which
clears RDA bit and
resets error bits
Read Data
Discard Data
Figure 19. LIN-UART Receiver Interrupt Service Routine Flow
Baud Rate Generator Interrupts
If the BRGCTL bit of the Multiprocessor Control Register is set (see Table 81 on page
141) and the REN bit of the Control 0 Register is 0, the LIN-UART receiver interrupt
asserts when the LIN-UART baud rate generator reloads. This action allows the BRG to
function as an additional counter if the LIN-UART receiver functionality is not employed.
The transmitter is enabled in this mode.
LIN-UART DMA Interface
The DMA engine is configured to move UART transmit and/or receive data. This reduces
processor overhead, especially when moving blocks of data. The DMA interface on the
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LIN-UART consists of the TxDmaReq and RxDmaReq outputs and the TxDmaAck and
RxDmaAck inputs. Any of the DMA channels are configured to process the UART DMA
requests.
If transmit data is to be moved by the DMA, the transmit interrupt must be disabled in the
interrupt controller. If receive data is to be moved by the DMA, the RDAIRQ bit in the
LIN-UART Control 1 Register must be set. This disables receive data interrupts when still
enabling error interrupts. The receive interrupt must be enabled in the interrupt controller
to process error condition interrupts.
LIN-UART Baud Rate Generator
The LIN-UART baud rate generator creates a lower frequency baud rate clock for data
transmission. The input to the BRG is the system clock. The LIN-UART Baud Rate High
and Low Byte registers combine to create a 16-bit baud rate divisor value (BRG[15:0])
which sets the data transmission rate (baud rate) of the LIN-UART. The LIN-UART data
rate is calculated using the following equation for normal UART operation:
System Clock Frequency (Hz)
16 UART Baud Rate Divisor Value
------------------------------------------------------------------------------------------
UART Data Rate (bps) =
The LIN-UART data rate is calculated using the following equation for LIN Mode UART
operation:
System Clock Frequency (Hz)
UART Baud Rate Divisor Value
-----------------------------------------------------------------------------
UART Data Rate (bps) =
When the LIN-UART is disabled, the BRG functions as a basic 16-bit timer with interrupt
on time-out. Observe the following steps to configure BRG as a timer with interrupt on
time-out:
1. Disable the LIN-UART receiver by clearing the REN bit in the LIN-UART Control 0
Register to 0 (TEN bit is asserted, transmit activity may occur).
2. Load the appropriate 16-bit count value into the LIN-UART Baud Rate High and Low
Byte registers.
3. Enable the BRG timer function and associated interrupt by setting the BRGCTL bit in
the LIN-UART Control 1 Register to 1. Enable the UART receive interrupt in the
interrupt controller.
When configured as a general purpose timer, the BRG interrupt interval is calculated using
the following equation:
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UART BRG Interrupt Interval (s) = System Clock Period (s) BRG[15:0]
Noise Filter
A noise filter circuit is included to filter noise on a digital input signal, such as UART
receive data, before the data is sampled by the block. This noise filter circuit is a require-
ment for protocols operating in a noisy environment.
The noise filter includes following features:
•
•
Synchronizes the receive input data to the system clock
Noise filter enable (NFEN)input selects whether the noise filter is bypassed (NFEN =
0) or included (NFEN = 1) in the receive data path
•
Noise filter control (NFCTL[2:0])input selects the width of the up/down saturating
counter digital filter. The available widths range is from 4 to11 bits
•
•
The digital filter output has hysteresis
Provides an active low saturated state output (FiltSatB), used to indicate presence of
noise
Architecture
Figure 20 displays how the noise filter is integrated with the LIN-UART for use on a LIN
network.
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System
Clock
RxD
RxD
RxD
FiltSatB
Noise Filter
NFEN, NFCTL
LIN
Transceiver
LIN-UART
TxD
TxD
TxD
Figure 20. Noise Filter System Block Diagram
Operation
Figure 21 displays the operation of the noise filter with and without noise. The noise filter
in this example is a 2-bit up/down counter, which saturates at 00band 11b. A 2-bit coun-
ter is shown for convenience, the operation of wider counters is similar. The output of the
filter switches from 1 to 0 when the counter counts down from 01bto 00band switches
from 0 to 1 when the counter counts up from 10bto 11b. The noise filter delays the
received data by three system clock cycles.
The FiltSatB signal is checked when the filtered RxD is sampled in the center of the bit-
time. The presence of noise (FiltSatB = 1 at center of bit-time) does not mean the sampled
data is incorrect, just that the filter is not in its saturated state of all 1’s or all 0’s. If Filt-
SatB = 1 when RxD is sampled during a receive character, the NE bit in the ModeSta-
tus[4:0] field is set. An indication of the level of noise in the network is obtained by
observing this bit.
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Baud Period
Data Bit = 0
16x Sample
Clock
Input
RxD (ideal)
Data Bit = 1
Clean RxD
Example
Noise Filter
3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Up/Dn Cntr
Noise Filter
Output RxD
nominal filter delay
Input
RxD (noisy)
Data Bit=0
Data Bit=1
Noise RxD
Example
Noise Filter
3 3 2 1 0 0 0 0 0 0 1 2 1 0 0 0 0 0 1 0 1 2 3 3 3 3 2 3 3 3 3 3 3 3
Up/Dn Cntr
Noise Filter
Output RxD
FiltSatB
Output
UART
Sample
Point
Figure 21. Noise Filter Operation
LIN-UART Control Register Definitions
The LIN-UART control registers support the LIN-UART, the associated Infrared encoder/
decoder and the noise filter. For detailed information about the infrared operation, see the
Infrared Encoder/Decoder chapter on page 149.
LIN-UART Transmit Data Register
Data bytes written to the LIN-UART Transmit Data Register, shown in Table 71, are
shifted out on the TXD pin. The write-only LIN-UART Transmit Data Register shares a
Register File address with the read-only LIN-UART Receive Data Register.
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Table 71. LIN-UART Transmit Data Register (UxTXD)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
TXD
X
W
ADDR
FF_E200h, FF_E210h
Bit
Description
[7:0]
TXD
Transmit Data
LIN-UART transmitter data byte to be shifted out through the TXD pin.
LIN-UART Receive Data Register
Data bytes received through the RXD pin are stored in the LIN-UART Receive Data Reg-
ister (Table 72). The read-only LIN-UART Receive Data Register shares a register file
address with the write-only LIN-UART Transmit Data Register.
Table 72. LIN-UART Receive Data Register (UxRXD)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
RXD
X
R
ADDR
FF_E200h, FF_E210h
Bit
Description
[7:0]
RXD
Receive Data
LIN-UART receiver data byte from the RXD pin
LIN-UART Status 0 Register
The LIN-UART Status 0 Register identifies the current LIN-UART operating configura-
tion and status. Table 73 describes the Status 0 Register for standard UART Mode.
Table 74 describes the Status 0 Register for LIN Mode.
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Table 73. LIN-UART Status 0 Register, Standard UART Mode (UxSTAT0)
Bit
7
RDA
0
6
PE
0
5
OE
0
4
FE
0
3
BRKD
0
2
TDRE
1
1
TXE
1
0
CTS
X
Field
RESET
R/W
R
R
R
R
R
R
R
R
ADDR
FF_E201h, FF_E211h
Bit
Description
[7]
RDA
Receive Data Available
This bit indicates that the LIN-UART Receive Data Register has received data. Reading the
LIN-UART Receive Data Register clears this bit.
0 = The LIN-UART Receive Data Register is empty.
1 = There is a byte in the LIN-UART Receive Data Register.
[6]
PE
Parity Error
This bit indicates that a parity error has occurred. Reading the Receive Data Register clears
this bit.
0 = No parity error occurred.
1 = A parity error occurred.
[5]
OE
Overrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the Receive Data Register has not been read. Reading the Receive Data Regis-
ter clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
[4]
FE
Framing Error
This bit indicates that a framing error (no stop bit following data reception) is detected. Reading
the Receive Data Register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
[3]
BRKD
Break Detect
This bit indicates that a break has occurred. If the data bits, parity/multiprocessor bit and stop
bit(s) are all zeroes, then this bit is set to 1. Reading the Receive Data Register clears this bit.
0 = No break occurred.
1 = A break occurred.
[2]
TDRE
Transmitter Data Register Empty
This bit indicates that the Transmit Data Register is empty and ready for additional data. Writ-
ing to the Transmit Data Register resets this bit.
0 = Do not write to the Transmit Data Register.
1 = The Transmit Data Register is ready to receive an additional byte to be transmitted.
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Bit
Description (Continued)
[1]
TXE
Transmitter Empty
This bit indicates that the Transmit Shift Register is empty and character transmission is fin-
ished.
0 = Data is currently transmitting.
1 = Transmission is complete.
[0]
CTS
CTS Signal
When this bit is read it returns the CTS signal level. If LBEN = 1, the CTS input signal is
replaced by the internal receive data available signal to provide flow control in LOOPBACK
Mode. CTS only affects transmission if the CTSE bit = 1.
Table 74. LIN-UART Status 0 Register, LIN Mode (UxSTAT0)
Bit
7
RDA
0
6
PLE
0
5
OE
0
4
FE
0
3
BRKD
0
2
TDRE
1
1
TXE
1
0
ATB
0
Field
RESET
R/W
R
R
R
R
R
R
R
R
ADDR
FF_E201h, FF_E211h
Bit
Description
[7]
RDA
Receive Data Available
This bit indicates that the Receive Data Register has received data. Reading the Receive Data
Register clears this bit.
0 = The Receive Data Register is empty.
1 = There is a byte in the Receive Data Register.
[6]
PLE
Physical Layer Error
This bit indicates that transmit and receive data do not match when a LIN slave or master is
transmitting; it is caused by a fault in the physical layer or multiple devices driving the bus
simultaneously. Reading the Status 0 Register or the Receive Data Register clears this bit.
0 = Transmit and receive data match.
1 = Transmit and receive data do not match.
[5]
OE
Receive Data and Autobaud Overrun Error
This bit is set just as in normal UART operation if a receive data overrun error occurs. This bit
is also set during LIN slave autobaud if the BRG counter overflows before the end of the auto-
baud sequence, indicating that the receive activity was not an autobaud character or the mas-
ter baud rate is too slow. The ATB status bit will also be set in this case. This bit is cleared by
reading the Receive Data Register.
0 = No autobaud or data overrun error occurred.
1 = An autobaud or data overrun error occurred.
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Bit
Description (Continued)
[4]
FE
Framing Error
This bit indicates that a framing error (no stop bit following data reception) is detected. Reading
the Receive Data Register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
[3]
BRKD
Break Detect
This bit is set in LIN Mode if (a) in LinSleep state and a break of at least 4 bit-times occurred
(wake-up event) or (b) in Slave Wait for Break state and a break of at least 11 bit-times
occurred (break event), or (c) in Slave Active state and a break of at least 10 bit-times occurs.
Reading the Status 0 Register or the Receive Data Register clears this bit.
0 = No LIN break occurred.
1 = A LIN break occurred.
[2]
TDRE
Transmitter Data Register Empty
This bit indicates that the Transmit Data Register is empty and ready for additional data. Writ-
ing to the Transmit Data Register resets this bit.
0 = Do not write to the Transmit Data Register.
1 = The Transmit Data Register is ready to receive an additional byte to be transmitted.
[1]
TXE
Transmitter Empty
This bit indicates that the Transmit Shift Register is empty and character transmission is fin-
ished.
0 = Data is currently transmitting.
1 = Transmission is complete.
[0]
ATB
LIN Slave AutoBaud Complete
This bit is set in LIN SLAVE Mode when an autobaud character is received. If the ABIEN bit is
set in the LIN Control Register, then a receive interrupt is generated when this bit is set. Read-
ing the Status 0 Register clears this bit. This bit will be 0 in LIN MASTER Mode.
LIN-UART Mode Select and Status Register
The LIN-UART Mode Select and Status Register, shown in Table 75, contains mode select
and status bits. The status of these bits is dependent on mode selection; see Tables 76
through 79 for descriptions.
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Table 75. LIN-UART Mode Select and Status Register (UxMDSTAT)
Bit
7
6
MSEL
0
5
4
3
2
1
0
Field
RESET
R/W
Mode Status
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R
R
R
ADDR
FF_E204h, FF_E214h
Bit
Description
[7:5]
MSEL
Mode Select
This R/W field determines which control register is accessed when performing a Write or Read
to the UART Control 1 Register address. This field also determines which status is returned in
the mode status field when reading this register.
000 = MULTIPROCESSOR and NORMAL UART control/status; see Table 76.
001 = Noise filter control/status; see Table 77.
010 = LIN Protocol control/status; see Table 78.
011–110 = Reserved = {0, 0, 0, 0, 0}.
111 = LIN-UART hardware revision (allows hardware revision to be read in the mode status
field); see Table 79.
[4:0]
Mode Status
This read-only field returns status corresponding to the mode selected by MSEL as follows:
000 = MULTIPROCESSOR and NORMAL UART mode status = {NE, 0, 0, NEWFRM, MPRX};
see Table 76.
001 = Noise filter status = {NE, 0,0,0,0}; see Table 77.
010 = LIN Mode status = {NE, RxBreakLength[3:0]}; see Table 78.
011–110 = Reserved = {0, 0, 0, 0, 0}.
111 = LIN-UART hardware revision; see Table 79.
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Table 76. MULTIPROCESSOR Mode Status Field (MSEL = 000b)
Bit
Description
NE
Noise Event
This bit is asserted if digital noise is detected on the receive data line when the
data is sampled (center of bit-time). If this bit is set, it does not mean that the
receive data is corrupted (in extreme cases), just that one or more of the noise fil-
ter data samples near the center of the bit-time did not match the average data
value.
NEWFRM
MPRX
New Frame
Status bit denoting the start of a new frame. Reading the LIN-UART Receive
Data Register resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
Multiprocessor Receive
Returns the value of the final multiprocessor bit received. Reading from the LIN-
UART Receive Data Register resets this bit to 0.
Table 77. Digital Noise Filter Mode Status Field (MSEL = 001B)
Description
Bit
NE
Noise Event
This bit is asserted if digital noise is detected on the receive data line while the
data is sampled (center of bit-time). If this bit is set, it does not mean that the
receive data is corrupted (in extreme cases), just that one or more of the noise fil-
ter data samples near the center of the bit-time did not match the average data
value.
Table 78. LIN Mode Status Field (MSEL = 010b)
Description
Bit
NE
Noise Event
This bit is asserted if some noise level is detected on the receive data line
when the data is sampled (center of bit-time). If this bit is set, it does not
indicate that the receive data is corrupt (in extreme cases), just that one or
more of the 16x data samples near the center of the bit-time did not match
the average data value.
RxBreakLength
LIN Mode Received Break Length
This field is read following a break (LIN WAKE-UP or BREAK) so software
determines the measured duration of the break. If the break exceeds 15 bit-
times, the value saturates at 1111B.
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Table 79. Hardware Revision Mode Status Field (MSEL = 111B)
Bit
Description
111
This field indicates the hardware revision of the LIN-UART block.
00_xxx LIN UART hardware revision.
01_xxx = reserved.
10_xxx = reserved.
11_xxx = reserved.
LIN-UART Control 0 Register
The LIN-UART Control 0 Register, shown in Table 80, configures the basic properties of
the LIN-UART’s transmit and receive operations.
Table 80. LIN-UART Control 0 Register (UxCTL0)
Bit
7
6
5
CTSE
0
4
3
PSEL
0
2
SBRK
0
1
STOP
0
0
LBEN
0
Field
RESET
R/W
TEN
0
REN
0
PEN
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E202h, FF_E212h
Bit
Description
[7]
TEN
Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is Low and the CTSE bit is 1, the transmitter is enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
[6]
REN
Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
[5]
CTSE
CTS Enable
0 = The CTS signal has no effect on the transmitter.
1 = The LIN-UART recognizes the CTS signal as an enable control for the transmitter.
[4]
PEN
Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit.
0 = Parity is disabled. This bit is overridden by the MPEN bit.
1 = The transmitter sends data with an additional parity bit and the receiver receives an addi-
tional parity bit.
[3]
PSEL
Parity Select
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
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Bit
Description (Continued)
Send Break
[2]
SBRK
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit. In
standard UART Mode, the duration of the break is determined by how long software leaves this
bit asserted. Also the duration of any required stop bits following the break must be timed by
software before writing a new byte to be transmitted to the Transmit Data Register. In LIN
Mode, the master sends a break character by asserting SBRK. The duration of the break is
timed by hardware and the SBRK bit is deasserted by hardware when the break is completed.
The duration of the break is determined by the TxBreakLength field of the LIN Control Register.
One or two stop bits are automatically provided by the hardware in LIN Mode as defined by the
stop bit.
0 = No break is sent.
1 = The output of the transmitter is 0.
[1]
STOP
Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
[0]
LBEN
Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver within the IrDA module.
LIN-UART Control 1 Registers
Multiple registers (see Tables 81 through 83) are accessible by a single bus address. Regis-
ter selection is determined by the Mode Select (MSEL) field. These registers provide addi-
tional control over the LIN-UART operation.
Multiprocessor Control Register
When MSEL = 000b, this LIN-UART Control 1 Register provides control for UART
MULTIPROCESSOR Mode, IRDA Mode and Baud Rate Timer Mode, as well as other
features which apply to multiple modes; see Table 81.
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Table 81. Multiprocessor Control Register (UxCTL1 with MSEL = 000b)
Bit
7
MPMD[1]
0
6
MPEN
0
5
MPMD[0]
0
4
MPBT
0
3
DEPOL
0
2
1
0
IREN
0
Field
RESET
R/W
BRGCTL RDAIRQ
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E203h, FF_E213h with MSEL = 000b
Bit
Description
MULTIPROCESSOR Mode
[7,5]
MPMD[1:0] If MULTIPROCESSOR (9-Bit) Mode is enabled,
00 = The LIN-UART generates an interrupt request on all received bytes (data and
address).
01 = The LIN-UART generates an interrupt request only on received address bytes.
10 = The LIN-UART generates an interrupt request when a received address byte matches
the value stored in the Address Compare Register and on all successive data bytes
until an address mismatch occurs.
11 = The LIN-UART generates an interrupt request on all received data bytes for which the
most recent address byte matched the value in the Address Compare Register.
[6]
MPEN
MULTIPROCESSOR (9-bit) Enable
This bit is used to enable MULTIPROCESSOR (9-Bit) Mode.
0 = Disable MULTIPROCESSOR (9-Bit) Mode.
1 = Enable MULTIPROCESSOR (9-Bit) Mode.
[4]
MPBT
Multiprocessor Bit Transmit
This bit is applicable only when MULTIPROCESSOR (9-Bit) Mode is enabled.
0 = Send 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send 1 in the multiprocessor bit location of the data stream (9th bit).
[3]
DEPOL
Driver Enable Polarity
0 = DE signal is active High.
1 = DE signal is active Low.
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Bit
Description (Continued)
[2]
BRGCTL
Baud Rate Generator Control
This bit causes different LIN-UART behavior depending on whether the LIN-UART receiver
is enabled (REN = 1 in the LIN-UART Control 0 Register).
When the LIN-UART receiver is not enabled, this bit determines whether the baud rate gen-
erator issues interrupts.
0 = BRG is disabled. Reads from the Baud Rate High and Low Byte registers return the
BRG reload value.
1 = BRG is enabled and counting. The BRG generates a receive interrupt when it counts
down to 0. Reads from the Baud Rate High and Low Byte registers return the current
BRG count value.
When the LIN-UART receiver is enabled, this bit allows reads from the baud rate registers to
return the BRG count value instead of the reload value.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG reload value.
1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count
value. Unlike the timers, there is no mechanism to latch the High byte when the Low
byte is read.
[1]
RDAIRQ
Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the interrupt control-
ler.
1 = Received data does not generate an interrupt request to the interrupt controller. Only
receiver errors generate an interrupt request.
[0]
IREN
Infrared Encoder/Decoder Enable
0 = Infrared encoder/decoder is disabled. LIN-UART operates normally.
1 = Infrared encoder/decoder is enabled. The LIN-UART transmits and receives data
through the Infrared encoder/decoder.
Noise Filter Control Register
When MSEL = 001b, this LIN-UART Control 1 Register provides control for the digital
noise filter; see Table 82.
Table 82. Noise Filter Control Register (UxCTL1 with MSEL = 001b)
Bit
7
NFEN
0
6
5
NFCTL
0
4
3
2
1
0
Field
RESET
R/W
Reserved
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
ADDR
FF_E203h, FF_E213h with MSEL = 001b
Bit
Description
[7]
NFEN
Noise Filter Enable
0 = Noise filter is disabled.
1 = Noise filter is enabled. Receive data is preprocessed by the noise filter.
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143
Bit
Description (Continued)
Noise Filter Control
[6:3]
NFCTL
This field controls the delay and noise rejection characteristics of the noise filter. The wider the
counter the more delay that is introduced by the filter and the wider the noise event that is fil-
tered.
000 = 4-bit up/down counter.
001 = 5-bit up/down counter.
010 = 6-bit up/down counter.
011 = 7-bit up/down counter.
100 = 8-bit up/down counter.
101 = 9-bit up/down counter.
110 = 10-bit up/down counter.
111 = 11-bit up/down counter.
[2:0]
Reserved
These bits are reserved and must be programmed to 000.
LIN Control Register (LIN-UART Control 1 Register with MSEL = 010b)
When MSEL = 010b, this LIN-UART Control 1 Register provides control for the LIN
Mode of operation; see Table 83.
Table 83. LIN Control Register (UxCTL1 with MSEL = 010b)
Bit
7
LMST
0
6
LSLV
0
5
ABEN
0
4
ABIEN
0
3
2
1
0
Field
RESET
R/W
LinState[1:0]
TxBreakLength
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E203h, FF_E213h with MSEL = 010b
Bit
Description
[7]
LMST
LIN MASTER Mode
0 = LIN MASTER Mode not selected.
1 = LIN MASTER Mode selected (if MPEN, PEN, LSLV = 0).
[6]
LSLV
LIN SLAVE Mode
0 = LIN SLAVE Mode not selected.
1 = LIN SLAVE Mode selected (if MPEN, PEN, LMST = 0).
[5]
ABEN
Autobaud Enable
0 = Autobaud not enabled.
1 = Autobaud enabled if in LIN SLAVE Mode.
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Bit
Description (Continued)
[4]
ABIEN
Autobaud Interrupt Enable
0 = Interrupt following autobaud does not occur.
1 = Interrupt following autobaud enabled if in LIN SLAVE Mode. When the autobaud char-
acter is received, a receive interrupt is generated and the ATB bit is set in the Status 0
Register.
[3:2]
LinState[1:0]
LIN State Machine
The LinState is controlled by both hardware and software. Software force a state change
at any time if necessary. In normal operation, software moves the state in and out of
Sleep state. For a LIN Slave, software changes the state from Sleep to Wait for Break
after which hardware cycles through the Wait for Break, Autobaud and Active states.
Software changes the state from one of the active states to Sleep state if the LIN bus
goes into Sleep Mode. For a LIN Master, software changes state from Sleep to Active
where it remains until software sets it back to the Sleep state. After configuration software
does not alter the LinState field during operation.
00 = Sleep State (either LMST or LSLV is set).
01 = Wait for Break state (only valid for LSLV = 1).
10 = Autobaud state (only valid for LSLV = 1).
11 = Active state (either LMST or LSLV is set).
[1:0]
Used in LIN Mode by the master to control the duration of the transmitted break.
TxBreakLength 00 = 13 bit-times.
01 = 14 bit-times.
10 = 15 bit-times.
11 = 16 bit-times.
LIN-UART Address Compare Register
The LIN-UART Address Compare Register stores the multinode network address of the
LIN-UART. When the MPMD[1] bit of the LIN-UART Control Register 0 is set, all
incoming address bytes are compared to the value stored in this address compare register.
Receive interrupts and RDA assertions occur only in the event of a match.
Table 84. LIN-UART Address Compare Register (UxADDR)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
COMP_ADDR
00h
R/W
ADDR
FF_E205h, FF_E215h
Bit
Description
[7:0]
Compare Address
COMP_ADDR This 8-bit value is compared to the incoming address bytes.
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LIN-UART Baud Rate High and Low Byte Registers
The LIN-UART Baud Rate High and Low Byte registers, shown in Tables 85 and 86,
combine to create a 16-bit baud rate divisor value, BRG[15:0], which sets the data trans-
mission rate (baud rate) of the LIN-UART.
Table 85. LIN-UART Baud Rate High Byte Register (UxBRH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
BRH
1
R/W
ADDR
FF_E206h, FF_E216h
Table 86. LIN-UART Baud Rate Low Byte Register (UxBRL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
BRL
1
R/W
ADDR
FF_E207h, FF_E217h
The LIN-UART data rate is calculated using the following equation for standard UART
modes. For LIN protocol, the baud rate registers must be programmed with the baud
period rather than 1/16 baud period.
The UART must be disabled when updating the baud rate registers because these high and
low registers must be written independently.
Note:
The LIN-UART data rate is calculated using the following equation for standard UART
operation:
System Clock Frequency (Hz)
16 UART Baud Rate Divisor Value
------------------------------------------------------------------------------------------
UART Baud Rate (bits/s) =
The LIN-UART data rate is calculated using the following equation for LIN Mode UART
operation:
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System Clock Frequency (Hz)
-----------------------------------------------------------------------------
UART Data Rate (bits/s) =
UART Baud Rate Divisor Value
For a given LIN-UART data rate, the integer baud rate divisor value is calculated using the
following equation for standard UART operation:
System Clock Frequency (Hz)
16 UART Data Rate (bits/s)
------------------------------------------------------------------------
UART Baud Rate Divisor Value (BRG) = Round
For a given LIN-UART data rate, the integer baud rate divisor value is calculated using the
following equation for LIN Mode UART operation:
System Clock Frequency (Hz)
------------------------------------------------------------------------
UART Baud Rate Divisor Value (BRG) = Round
UART Data Rate (bits/s)
The baud rate error relative to the appropriate baud rate is calculated using the following
equation:
Actual Data Rate – Desired Data Rate
------------------------------------------------------------------------------------------
UART Baud Rate Error (%) = 100
Desired Data Rate
For reliable communication, the LIN-UART baud rate error must never exceed 5 percent.
Table 87 provides information about baud rate errors for popular baud rates and com-
monly used crystal oscillator frequencies for normal UART Mode of operation.
When the LIN-UART is disabled, the baud rate generator functions as a basic 16-bit timer
with interrupt on time-out. To configure the baud rate generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the LIN-UART receiver by clearing the REN bit in the LIN-UART Control 0
Register to 0 (TEN bit is asserted, transmit activity may occur).
2. Load the appropriate 16-bit count value into the LIN-UART Baud Rate High and Low
Byte registers.
3. Enable the baud rate generator timer function and associated interrupt by setting the
BRGCTL bit in the LIN-UART Control 1 Register to 1. Enable the UART receive
interrupt in the interrupt controller.
When configured as a general purpose timer, the BRG interrupt interval is calculated using
the following equation:
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UART BRG Interrupt Interval (s) = System Clock Period (s) BRG[15:0]
Table 87. LIN-UART Baud Rates
20.0MHz System Clock
10.0MHz System Clock
BRG
BRG
Desired
Divisor
Actual
Desired
Divisor
Actual
Rate (kHz) (Decimal) Rate (kHz) Error (%)
Rate (kHz) (Decimal) Rate (kHz) Error (%)
1250.0
625.0
250.0
115.2
57.6
1
2
1250.0
625.0
250.0
113.64
56.82
37.88
19.23
9.62
0.00
0.00
1250.0
625.0
250.0
115.2
57.6
N/A
1
N/A
625.0
208.33
125.0
56.8
N/A
0.00
5
0.00
3
–16.67
8.51
11
–1.19
–1.36
–1.36
0.16
5
22
11
–1.36
1.73
38.4
33
38.4
16
39.1
19.2
65
19.2
33
18.9
0.16
9.60
130
260
521
1042
2083
4167
0.16
9.60
65
9.62
0.16
4.80
4.81
0.16
4.80
130
260
521
1042
2083
4.81
0.16
2.40
2.399
1.199
0.60
–0.03
–0.03
0.02
2.40
2.40
–0.03
–0.03
–0.03
0.2
1.20
1.20
1.20
0.60
0.60
0.60
0.30
0.299
–0.01
0.30
0.30
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Table 87. LIN-UART Baud Rates (Continued)
5.5296MHz System Clock
BRG
3.579545MHz System Clock
BRG
Desired
Divisor
Actual
Desired
Divisor
Actual
Rate (kHz) (Decimal) Rate (kHz) Error (%)
Rate (kHz) (Decimal) Rate (kHz) Error (%)
1250.0
625.0
250.0
115.2
57.6
N/A
N/A
1
N/A
N/A
N/A
N/A
1250.0
625.0
250.0
115.2
57.6
N/A
N/A
1
N/A
N/A
N/A
N/A
345.6
115.2
57.6
38.4
19.2
9.60
4.80
2.40
1.20
0.60
0.30
38.24
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
223.72
111.9
55.9
37.3
18.6
9.73
4.76
2.41
1.20
0.60
0.30
–10.51
–2.90
–2.90
–2.90
–2.90
1.32
3
2
6
4
38.4
9
38.4
6
19.2
18
19.2
12
23
47
93
186
373
746
9.60
36
9.60
4.80
72
4.80
–0.83
0.23
2.40
144
288
576
1152
2.40
1.20
1.20
0.23
0.60
0.60
–0.04
–0.04
0.30
0.30
1.8432MHz System Clock
BRG
Desired
Divisor
Actual
Rate (kHz) (Decimal) Rate (kHz) Error (%)
1250.0
625.0
250.0
115.2
57.6
N/A
N/A
N/A
1
N/A
N/A
N/A
N/A
N/A
N/A
115.2
57.6
38.4
19.2
9.60
4.80
2.40
1.20
0.60
0.30
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
2
38.4
3
19.2
6
9.60
12
24
48
96
192
384
4.80
2.40
1.20
0.60
0.30
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Z16FMC Series Motor Control MCUs
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149
Infrared Encoder/Decoder
Z16FMC Series products contain two fully-functional, high-performance UART-to-infra-
red encoders/decoders (endecs). Each infrared endec is integrated with an on-chip UART
to allow easy communication between the Z16FMC device and IrDA physical layer speci-
fication version 1.3-compliant infrared transceivers. Infrared communication provides
secure, reliable, low-cost, point-to-point communication between PCs, PDAs, cell phones,
printers and other infrared-enabled devices.
Architecture
Figure 22 displays the architecture of the infrared endec.
System
Clock
Zilog
ZHX1810
RxD
RXD
TXD
RXD
Infrared
TxD
Encoder/Decoder
(Endec)
TXD
Infrared
Transceiver
UART
Baud Rate
Clock
Interrupt
I/O
Data
Signal Address
Figure 22. Infrared Data Communication System Block Diagram
Operation
When the infrared endec is enabled, the transmit data from the associated on-chip UART
is encoded as digital signals in accordance with the IrDA standard and output to the infra-
red transceiver via the TXD pin. Similarly, data received from the infrared transceiver is
passed to the infrared endec via the RXD pin, decoded by the infrared endec, and then
passed to the UART. Communication is half-duplex, which means that simultaneous data
transmission and reception is not allowed.
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150
The baud rate is set by the UART’s baud rate generator and supports IrDA standard baud
rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet
IrDA specifications. The UART must be enabled to use the infrared endec. The infrared
endec data rate is calculated using the below equation:
System Clock Frequency (Hz)
Infrared Data Rate (bps) = ---------------------------------------------------------------------------------------
16xUART Baud Rate Divisor Value
Transmitting IrDA Data
The data to be transmitted using the infrared transceiver is first sent to the UART. The
UART’s transmit signal (TXD) and baud rate clock are used by the IrDA to generate the
modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared
data bit is 16-clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains
Low for the full 16-clock period. If the data to be transmitted is 0, a 3-clock high pulse is
output following a 7-clock low period. After the 3-clock high pulse, a 6-clock low pulse is
output to complete the full 16-clock data period. Figure 23 displays IrDA data transmis-
sion. When the infrared endec is enabled, the UART’s TXD signal is internal to the
Z16FMC Series products while the IR_TXD signal is output through the TXD pin.
16-clock
period
Baud Rate
Clock
UART’s
TXD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
3-clock
pulse
IR_TXD
7-clock
delay
Figure 23. Infrared Data Transmission
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Z16FMC Series Motor Control MCUs
Product Specification
151
Receiving IrDA Data
Data received from the infrared transceiver via the IR_RXD signal through the RXD pin is
decoded by the infrared endec and passed to the UART. The UART’s baud rate clock is
used by the infrared endec to generate the demodulated signal (RXD) that drives the
UART. Each UART/Infrared data bit is 16-clocks wide. Figure 24 displays data reception.
When the infrared endec is enabled, the UART’s RXD signal is internal to the Z16FMC
Series products when the IR_RXD signal is received through the RXD pin.
16-clock
period
Baud Rate
Clock
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_RXD
min. 1.6µs
pulse
UART’s
RXD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
8-clock
delay
16-clock
period
16-clock
period
16-clock
period
16-clock
period
Figure 24. Infrared Data Reception
The system clock frequency must be at least 1.0MHz to ensure proper reception
of the 1.6µs minimum width pulses allowed by the IrDA standard.
Caution:
Endec Receiver Synchronization
The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the Endec counter is reset. When the count reaches a value of 8, the
UART RXD value is updated to reflect the value of the decoded data.
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When the count reaches 12 baud clock periods, the sampling window for the next incom-
ing pulse opens. The window remains open until the count again reaches 8 (i.e., 24 baud
clock periods since the previous pulse was detected). This gives the Endec a sampling
window of minus 4 baudrate clocks to plus 8 baudrate clocks around the expected time of
an incoming pulse. If an incoming pulse is detected inside this window, this process is
repeated. If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state
and waits for the next falling edge. As each falling edge is detected, the Endec clock coun-
ter is reset, resynchronizing the Endec to the incoming signal. This allows the Endec to
tolerate jitter and baud rate errors in the incoming data stream. Resynchronizing the Endec
does not alter the operation of the UART, which ultimately receives the data. The UART is
only synchronized to the incoming data stream when a start bit is received.
Infrared Encoder/Decoder Control Register Definitions
All infrared endec configuration and status information is set by the UART con-
trol registers as defined in the beginning of the LIN-UART Control Register Def-
initions section on page 132.
Caution:
To prevent spurious signals during IrDA data transmission, set the IREN bit in the UARTx
Control 1 Register to 1 to enable the Infrared Encoder/Decoder before enabling the GPIO
port alternate function for the corresponding pin.
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Enhanced Serial Peripheral Interface
The Enhanced Serial Peripheral Interface (ESPI) supports SPI (Serial Peripheral Interface)
and Inter-IC Sound (I2S) modes of operation.
The features of the ESPI include:
•
•
•
•
Full-duplex, synchronous, character-oriented communication
Four-wire interface (SS, SCK, MOSI, MISO)
Transmit and receive buffer registers to enable high throughput
Transfer rates up to a maximum of one-fourth the system clock frequency when in
SLAVE Mode
•
•
•
Error detection
Dedicated programmable baud rate generator (BRG)
Data transfer control through polling, interrupt, or DMA
Architecture
The ESPI is a full-duplex, synchronous, character-oriented channel that supporting a four-
wire interface (serial clock, transmit and receive data and Slave select). The ESPI block
consists of a shift register, transmit and receive data buffer registers, a baud rate (clock)
generator, control/status registers and a control state machine. Transmit and receive trans-
fers are in sync as there is a single shift register for both transmit and receive data. Fig-
ure 25 displays a block diagram of the ESPI.
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Peripheral Bus
Interrupt
DMA Requests
TX RX
ESPI BRH
Register
ESPI Control
Register
ESPI Status
Register
ESPI State
Register
ESPI BRL
Register
ESPI Mode
Register
ESPI State
Machine
Baud
Rate
Generator
Interrupt/
count = 1
DMA Logic
Transmit Data Register
SCK
Logic
0 Shift Register 7
data_out
Receive Data Register
SCK SCK
in
out
SS out SS in
MISO
out
MOSI
out
Pin Direction
Control
MISO MOSI
in
in
GPIO Logic and Port Pins
SS
MISO
MOSI
SCK
Figure 25. ESPI Block Diagram
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ESPI Signals
The four ESPI signals are:
•
•
•
•
Master-In/Slave-Out (MISO)
Master-Out/Slave-In (MOSI)
Serial clock (SCK)
Slave select (SS)
The following paragraphs describe these signals in both MASTER and SLAVE modes.
The appropriate GPIO pins must be configured using the GPIO Alternate Function regis-
ters.
Master-In/Slave-Out
The MISO pin is configured as an input in a master device and as an output in a slave
device. Data is transferred to most significant bit first. The MISO pin of a slave device is
placed in a high-impedance state if the slave is not selected. When the ESPI is not enabled,
this signal is in a high-impedance state. The direction of this pin is controlled by the
MMEN bit of the ESPI Control Register.
Master-Out/Slave-In
The MOSI pin is configured as an output in a master device and as an input in a slave
device. Data is transferred to most significant bit first. When the ESPI is not enabled, this
signal is in a high-impedance state. The direction of this pin is controlled by the MMEN
bit of the ESPI Control Register.
Serial Clock
The SCK synchronizes data movement both in and out of the shift register via the MOSI
and MISO pins. In MASTER Mode (MMEN = 1), the ESPI’s baud rate generator creates
the serial clock and drives it out via its SCK pin to the slave devices. In SLAVE Mode, the
SCK pin is an input. Slave devices ignore the SCK signal unless their SS pin is asserted.
The master and slave are each capable of exchanging a character of data during a sequence
of NUMBITS clock cycles (see the NUMBITS field in the the ESPI Mode Register sec-
tion on page 173). In both master and slave ESPI devices, data is shifted on one edge of
the SCK and is sampled on the opposite edge where data is stable. SCK phase and polarity
is determined by the PHASE and CLKPOL bits (see the ESPI Control Register section on
page 171).
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Slave Select
The SS signal is a bidirectional framing signal with several modes of operation to support
SPI and other synchronous serial interface protocols. The SLAVE SELECT Mode is
selected by the SSMD field of the ESPI Mode Register. The direction of the SS signal is
controlled by the SSIO bit of the ESPI Mode Register. The SS signal is an input on slave
devices and is an output on the active master device. Slave devices ignore transactions on
the bus unless their slave select input is asserted. In SPI MASTER Mode, additional GPIO
pins are required to provide Slave Selects if there is more than one slave device.
ESPI Register Overview
The ESPI Control/Status registers are summarized in Table 88. These registers are
accessed by either Word (16-bit) or Byte operations.
Table 88. ESPI Registers
Word Address
XXXXX0
Even Address
Data
Odd Address
Transmit Data Command
Mode
XXXXX2
Control
XXXXX4
Status
State
XXXXX6
Baud Rate High
Baud Rate Low
Comparison with Basic SPI Block
The ESPI module includes many enhancements when compared to the simpler SPI mod-
ule in other Z8 Encore! parts. This section highlights the differences between the ESPI
module and the SPI module as follows:
•
•
Transmit and receive data buffer register added to support higher performance.
Multiple interrupt sources (transmit data, receive data, errors). SPI module only has
data transfer complete interrupt.
•
•
•
DMA controller interface (separate transmit and receive interfaces).
Register addresses redefined to facilitate 16-bit transfers on the Z16FMC Series MCU.
Transmit Data Command Register: a new register to facilitate the DMA interface and
improve performance with 16-bit transfers. SSV and TEOF are set on the same cycle
upon which the data register is written.
•
Control register:
–
IRQE changed to DIRQE to allow data interrupts to be disabled when using the
DMA but still allow error interrupts
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–
–
STR bit on the SPI module replaced with ESPIEN1; SPIEN replaced by
ESPIEN0; these enhancements allow unidirectional transfers, which minimize
software or DMA overhead
BIRQ replaced with BRGCTL
•
Mode register:
–
–
–
Added SSMD field which adds support for loop back and I2S modes
Moved SSV bit to the Transmit Data Command Register, as described above
Added slave select polarity (SSPO) to support active High and Low slave select
on SS pin
•
•
Status register:
–
–
IRQ split into TDRE and RDRF (separate transmit and receive interrupts)
Replace overrun error with separate transmit under-run and receive overrun
State register:
–
–
Replaced SCKEN bit with SCKI
Replaced TCKEN with SDI
Operation
During transfer, data is sent and received simultaneously by both master and slave
devices. Separate signals are required to transmit data, receive data and the serial clock.
When a transfer occurs, a multibit (typically 8-bit) character is shifted out one data pin and
a multi-bit character is simultaneously shifted in on a second data pin. An 8-bit shift regis-
ter in the master and an 8-bit shift register in the slave is connected as a circular buffer.
The ESPI Shift Register is buffered to support back-to-back character transfers in high
performance applications.
A transaction is initiated when the Transmit Data Register is written in the master device.
The value from the data register is transferred into the Shift Register and the transaction
begins. After the transmit data is loaded into the Shift Register, the Transmit Data Register
Empty (TDRE) status bit asserts, indicating that the Transmit Data Register is written with
the next value. At the end of each character transfer, the Shift Register value (receive data)
is loaded into the Receive Data Register. At that point the Receive Data Register Full
(RDRF) status bit asserts. When software or DMA reads the receive data from the Receive
Data Register, the RDRF signal deasserts.
The master sources the SCK and SS signal during the transfer.
Internal data movement (either by software or DMA) to/from the ESPI block is controlled
by the Transmit Data Register Empty (TDRE) and Receive Data Register Full (RDRF)
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signals. These signals are read only bits in the ESPI Status Register. When either the
TDRE or RDRF bits assert, an interrupt is sent to the interrupt controller if the data inter-
rupt request enable (DIRQE) bit is set. The TDRE and RDRF signals also generate trans-
mit and receive DMA requests.
In many cases the software application is only moving information in one direction. In
such a case, either the TDRE or RDRF interrupts/DMA requests is disabled to minimize
software/DMA overhead. Unidirectional data transfer is supported by setting the
ESPIEN1, 0 bits in the Control Register to 10 or 01. If the DMA engine is being used to
move the data, the transmit and receive data interrupts are disabled through the DIRQE bit
of the Control Register. In this case error interrupts still occurs and must be handled
directly by the software.
Throughput
In MASTER Mode, the maximum SCK rate supported is one-half the system clock fre-
quency. This rate is achieved by programming the value 0001hinto the baud rate high/
low register pair. Though each character is transferred at this rate, it is unlikely that soft-
ware interrupt routines or DMA keeps up with this rate. In SPI Mode, the transfer will
automatically pause between characters until the current receive character is read and the
next transmit data value is written.
In SLAVE Mode, the transfer rate is controlled by the master. As long as the TDRE and
RDRF interrupt or DMA requests are serviced before the next character transfer completes
the slave will keep up with the master. In SLAVE Mode, the baud rate is restricted to a
maximum of one-fourth of the system clock frequency to allow for synchronization of the
SCK input to the internal system clock.
ESPI Clock Phase and Polarity Control
The ESPI supports four combinations of SCK phase and polarity using two bits in the
ESPI Control Register. The clock polarity bit, CLKPOL, selects an active High or active
Low clock and has no effect on the transfer format. The clock phase bit, PHASE, selects
one of two fundamentally different transfer formats. The data is output a half-cycle before
the receive clock edge which provides a half cycle of setup and hold time. Table 89 lists
the ESPI clock phase and polarity operation parameters.
Table 89. ESPI Clock Phase and Clock Polarity Operation
SCK Transmit
Edge
SCK Idle
State
PHASE
CLKPOL
SCK Receive Edge
Rising
0
0
1
1
0
1
0
1
Falling
Rising
Rising
Falling
Low
High
Low
High
Falling
Falling
Rising
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Transfer Format with Phase Equals Zero
Figure 26 displays the timing diagram for an SPI type transfer in which PHASE = 0. For
SPI transfers the clock only toggles during the character transfer. The two SCK wave-
forms show polarity with CLKPOL = 0 and with CLKPOL = 1. The diagram is interpreted
as either a Master or Slave timing diagram as the SCK MISO and MOSI pins are directly
connected between the master and the slave.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
MISO
Input Sample Time
SS
Figure 26. ESPI Timing when PHASE = 0
Transfer Format with Phase Equals One
Figure 27 displays the timing diagram for an SPI type transfer in which PHASE = 1. For
SPI transfers the clock only toggles during the character transfer. Two waveforms are
depicted for SCK, one for CLKPOL = 0 and another for CLKPOL = 1.
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SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
MISO
Input Sample Time
SS
Figure 27. ESPI Timing when PHASE = 1
Modes of Operation
This section describes the different modes of data transfer supported by the ESPI block.
The mode is selected by the SLAVE SELECT Mode (SSMD) field of the Mode Register.
SPI Mode
This mode is selected by setting the SSMD field of the mode Register to 000. In this
mode, software or DMA controls the assertion of the SS signal directly via the SSV bit of
the SPI Transmit Data Command Register. Either DMA or software is used to control an
SPI Mode transaction. Prior to or simultaneously with writing the first transmit data byte,
software or DMA sets the SSV bit. Software sets the SSV bit either by performing a byte
write to the Transmit Data Command Register prior to writing the first transmit character
to the data register or by performing a word write to the data register address which loads
the first transmit character and simultaneously sets the SSV bit.
The DMA sets the SSV bit via the command field of the descriptor. The SSV bit is written
on the DMA command bus prior to or in sync with the first data byte. SS will remain
asserted while one or more characters are transferred. There are two mechanisms for deas-
serting SS at the end of the transaction. One method is used by DMA and also by software,
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is to set the TEOF bit of the Transmit Data Command Register when the final TDRE inter-
rupt or DMA request is being serviced (set TEOF before or simultaneously with writing
the final data byte). When the final bit of the final character is transmitted, the hardware
will automatically deassert the SSV and TEOF bits. The second method is for software to
directly clear the SSV bit after the transaction completes. If software clears the SSV bit
directly, it is not necessary for software to also set the TEOF bit on the final transmit byte.
After writing the final transmit byte, the end of the transaction is detected by waiting for
the final RDRF interrupt or monitoring the TFST bit in the ESPI Status Register.
The transmit underrun and receive overrun errors do not occur in an SPI Mode master. If
the RDRF and TDRE requests have not been serviced before the current byte transfer
completes, SCLK is paused until the data register is read and written. The transmit under-
run and receive overrun errors will occur in a slave if the slave’s software/DMA does not
keep up with the master data rate. If a transmit underrun occurs in SLAVE Mode, the Shift
Register in the slave is loaded with all 1s.
In the SPI Mode, the SCK is active only for the data transfer with one SCK period per bit
transferred. If the SPI bus has multiple slaves, the slave select lines to all or one of the
slaves must be controlled independently by software using GPIO pins.
Figure 28 displays multiple character transfer in SPI Mode. Note that while character ’n’
is being transferred using the Shift Register, software/DMA responds to the receive
request for character n-1 and the transmit request for character n+1.
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SCK (SSMD = 00,
PHASE = 0,
CLKPOL = 0,
SSPO = 0)
Bit0
Bit7
Bit6
Bit1
Bit0
Bit7
Bit 6
MOSI, MISO
Rx Data Register
Empty
Tx n+1
empty
Tx n+2
Tx/Rx n+1
Rx n–1
Rx n
Tx n
Tx Data Register
Shift Register
Tx/Rx n–1
Tx/Rx n
TDRE
RDRF
ESPI Interrupt
Figure 28. SPI Mode (SSMD = 000)
I<SuperscriptH3>2S Mode
Inter-Integrated Circuit Sound Mode (I2S) is selected by setting the SSMD field of the
Mode Register to 010. The PHASE and CLKPOL bits of the Control Register must be set
to 0. This mode is illustrated in Figure 29 with SS alternating between consecutive frames.
A frame consists of a fixed number of data bytes as defined in the DMA buffer descriptor
or by software. I2S Mode is typically used to transfer left or right channel audio data.
The SSV indicates whether the corresponding bytes are left or right channel data. The
SSV value must be updated when servicing the TDRE interrupt/request for the first byte in
a left or write channel frame. Servicing this request is accomplished by performing a word
write when writing the first byte of the audio word, which updates both the ESPI data and
transmit data command words or by doing a byte write to update SSV followed by a byte
write to the data register. The SS signal leads the data by one SCK period.
If a DMA channel is controlling data transfer, each sequence of left (or right) channel byte
is considered a frame with a buffer descriptor. The SSV bit is defined in the buffer descrip-
tor command field and is automatically written to the Transmit Data Command Register
just prior to or in synchronous with the first data byte of the frame being written. Note that
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the number of bits per frame is a value other than an integral number of 8 bits by setting
NUMBITS to a value other than 0.
Example
To send 20 bits/frame, set NUMBITS = 5 and read/write 4 bytes per frame. The transmit
data must be left-justified and the receive data must be right-justified.
The transaction is terminated when the master has no more data to transmit. After the final
bit is transferred, SCLK stops and SS and SSV returns to their default states. If TEOF is
not set on the final byte, a transmit underrun error occurs at this point.
SCK (SSMD = 010,
PHASE = 0,
CLKPOL = 0)
SS
(SSPO = 0)
SSV=0
Bit7
SSV=1
Bit7
Bit0
Bit 7
MOSI, MISO
Bit0
frame n
(may be multiple
bytes)
frame n + 1
2
Figure 29. I S Mode (SSMD = 010)
SPI Protocol Configuration
This section describes in detail how to configure the ESPI block for the SPI protocol. In
the SPI protocol the master sources the SCK and asserts slave select signals to one or more
slaves. The slave select signals are typically active Low.
SPI Master Operation
The ESPI block is configured for MASTER Mode operation by setting the MMEN bit = 1
in the ESPICTL Register. The SSMD field of the ESPI Mode Register is set to 000 for SPI
PROTOCOL Mode. The PHASE, CLKPOL and WOR bits in the ESPICTL Register and
the NUMBITS field in the ESPI Mode Register must be consistent with the Slave SPI
devices. Typically for an SPI master SSIO = 1 and SSPO = 0. The appropriate GPIO pins
are configured for the ESPI alternate function on the MOSI, MISO and SCK pins. The
GPIO for the ESPI SS pin is configured in alternate function mode as well though soft-
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ware uses any GPIO pin(s) to drive one or more slave select lines. If the ESPI SS signal is
not used to drive a slave select the SSIO bit must still be set to 1 in a single master system.
Figure 30 and Figure 31 displays the ESPI block configured as an SPI master.
ESPI Master
To Slave’s SS Pin
From Slave
SS
8-bit Shift Register
Bit 0 Bit 7
MISO
MOSI
SCK
To Slave
To Slave
Baud Rate
Generator
Figure 30. ESPI Configured as an SPI Master in a Single Master, Single Slave System
ESPI Master
To Slave #2’s SS Pin
To Slave #1’s SS Pin
GPIO
GPIO
8-bit Shift Register
Bit 0 Bit 7
From Slaves
To Slaves
MISO
MOSI
Baud Rate
Generator
SCK
To Slaves
Figure 31. ESPI Configured as an SPI Master in a Single Master, Multiple Slave System
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Multi-Master SPI Operation
In a multi-master SPI system, all SCK pins are tied together, all MOSI pins are tied
together and all MISO pins are tied together. All SPI pins must be configured in open-
drain mode to prevent bus contention. At any time, only one SPI device is configured as
the master and all other devices on the bus are configured as slaves. The master asserts the
SS pin on the selected slave. Next, the active master drives the clock and transmit data on
the SCK and MOSI pins to the SCK and MOSI pins on the slave (including those slaves
which are not enabled). The enabled slave drives data out its MISO pin to the MISO mas-
ter pin.
When the ESPI is configured as a master in a multi-master SPI system, the SS pin must be
configured as an input. The SS input signal on a device configured as a master must
remain High. If the SS signal on the active master goes Low (indicating another master is
accessing this device as a slave), a collision error flag is set in the ESPI Status Register.
The slave select outputs on a master in a multi-master system must come from GPIO pins.
SPI Slave Operation
The ESPI block is configured for SLAVE Mode operation by setting the MMEN bit = 0 in
the ESPICTL Register and setting the SSIO bit = 0 in the ESPIMODE Register. The
SSMD field of the ESPI Mode Register is set to 00 for SPI PROTOCOL Mode. The
PHASE, Clkpoland WOR bits in the ESPICTL Register and the NUMBITS field in the
ESPIMODE Register must be set to be consistent with the other SPI devices. Typically for
an SPI slave SSPO = 0.
If the slave has data to send to the master, the data must be written to the data register
before the transaction starts (first edge of SCK when SS is asserted). If the data register is
not written prior to the slave transaction, the MISO pin outputs all 1s.
Due to the delay resulting from synchronization of the SS and SCK input signals to the
internal system clock, the maximum SCK baud rate which is supported in SLAVE Mode is
the system clock frequency divided by 8. This rate is controlled by the SPI master.
Figure 32 illustrates the ESPI configuration in SPI SLAVE Mode.
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SPI Slave
From Master
SS
8-bit Shift Register
Bit 7 Bit 0
MISO
MOSI
To Master
From Master
SCK
From Master
Figure 32. ESPI Configured as an SPI Slave
Error Detection
Error events detected by the ESPI block are described in this section. Error events gener-
ate an ESPI interrupt and set a bit in the ESPI Status Register. The error bits of the ESPI
Status Register are read/write 1 to clear.
Transmit Underrun
A transmit underrun error occurs for a master with SSMD = 10 or 11 when a character
transfer completes and TDRE = 1. In these modes when a transmit underrun occurs the
transfer is aborted (SCK will halt and SSV will be deasserted). For a master in SPI Mode
(SSMD = 00), a transmit underrun is not signaled because SCK will pause and wait for the
data register to be written.
In SLAVE Mode, a transmit underrun error occurs if TDRE = 1 at the start of a transfer.
When a transmit underrun occurs in SLAVE Mode, ESPI transmits a character of all 1s.
A transmit underrun sets the TUND bit in the ESPI Status Register to 1. Writing a 1 to
TUND clears this error flag.
Mode Fault (Multi-Master Collision)
A mode fault indicates when more than one master is trying to communicate at the same
time (a multi-master collision) in SPI Mode. The mode fault is detected when the enabled
master’s SS input pin is asserted. For this to happen the control and mode registers must
be configured with MMEN = 1, SSIO = 0 (SS is an input) and SS input = 0. A mode fault
sets the COL bit in the ESPI Status Register to 1. Writing a 1 to COL clears this error flag.
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Receive Overrun
A receive overrun error occurs when a transfer completes and the RDRF bit is still set
from the previous transfer. A receive overrun sets the ROVR bit in the ESPI Status Regis-
ter to 1. Writing a 1 to ROVR clears this error flag. The Receive Data Register is not over-
written and will contain the data from the transfer which initially set the RDRF bit.
Subsequent received data is lost until the RDRF bit is cleared.
Slave Mode Abort
In SLAVE Mode of operation if the SS pin deasserts before all bits in a character have
been transferred, the transaction is aborted. When this condition occurs the ABT bit is set
in the ESPI Status Register. A slave abort error resets the slave control logic to the idle
state.
A slave abort error is also asserted in SLAVE Mode, if BRGCTL = 1 and a BRG time-out
occurs. When BRGCTL = 1 is in SLAVE Mode, it functions as a WDT monitoring the
SCK signal. The BRG counter is reloaded every time a transition on SCK occurs while SS
is asserted. The baud rate reload registers must be programmed with a value longer than
the expected time between SS assertion and the first SCK edge, between SCK transitions
while SS is asserted and between the previous SCK edge and SS deassertion. A time-out
indicates the master is stalled or disabled. Writing a 1 to ABT clears this error flag.
ESPI Interrupts
ESPI has a single interrupt output which is asserted when any of the TDRE, TUND, COL,
ABT, ROVR, or RDRF bits are set in the ESPI Status Register. The interrupt is a pulse
(duration of one system clock) generated when any one of the source bits initially set. The
TDRE and RDRF interrupts are enabled/disabled through the Data Interrupt Request
Enable (DIRQE) bit of the ESPI Control Register.
A transmit interrupt is asserted by the TDRE status bit when the ESPI block is enabled and
the DIRQE bit is set. The TDRE bit in the Status Register is cleared automatically when
the Transmit Data Register is written or the ESPI block is disabled. When the Transmit
Data Register value is loaded into the Shift Register to start a new transfer, the TDRE bit
will be set again causing a new transmit interrupt. If information is being received but not
transmitted the transmit interrupts are eliminated by selecting RECEIVE ONLY Mode
(ESPIEN1,0 = 01). A master operates in Receive Only mode; however, a write to the ESPI
(Transmit) Data Register is still required to initiate the transfer of a character.
A receive interrupt is generated by the RDRF status bit when the ESPI block is enabled;
the DIRQE bit is set and a character transfer completes. At the end of the character trans-
fer, the contents of the Shift Register is transferred into the Receive Data Register, causing
the RDRF bit to assert. The RDRF bit is cleared when the Receive Data Register is read. If
information is being transmitted but not received by the software application, the receive
interrupt is eliminated by selecting Transmit Only mode (ESPIEN1,0 = 10) in either MAS-
TER or SLAVE modes.
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Product Specification
168
ESPI error interrupts occur if any of the TUND, COL, ABT and ROVR bits in the ESPI
Status Register are set. These bits are cleared by writing a 1 to the corresponding bit.
If the ESPI is disabled (ESPIEN1,0 = 00), an ESPI interrupt is generated by a BRG time-
out. This timer function must be enabled by setting the BRGCTL bit in the ESPICTL Reg-
ister. This timer interrupt does not set any of the bits of the ESPI Status Register.
DMA Interface
The assertion of the TDRE and RDRF signals generate transmit and receive DMA
requests (SPITxReq, SPIRxReq), allowing data movement to be handled by a DMA con-
troller rather than directly by software. The DMA acknowledges these requests through
the SPITxAck and SPIRxAck signals). Inputs allow the SSV and TEOF bits of the Trans-
mit Data Command Register to be controlled by the DMA. The SPITxReqEOF and
SPIRxReqEOF outputs to the DMA provides an indication that SS has deasserted (trans-
action complete).
If the software application is moving data in only one direction, the ESPIEN1,0 bits are set
to 10 or 01, allowing a single DMA channel to control the ESPI data transfer. For a master,
the valid options are transmit only or transmit-receive. For a slave, all options are valid.
When a slave is operating in Receive Only mode, it will transmit characters of all ones.
DMA Descriptors
For ESPI Transmit DMA descriptors, the 4-bit CMDSTAT field of the descriptor exists in
the format shown in Table 90. The SSV bit in the Master’s transmit buffer descriptor
CMDSTAT field controls the ESPI SS output. The SSV bit in the descriptor is transferred
to the SSV bit in the ESPI Data Command Register with the first byte of the buffer. If the
EOF bit is set in the DMA descriptor control word, the End Of Frame signal from the
DMA (EOFSync) will assert coincident with writing the final byte in the buffer to the
ESPI Data Register, setting the TEOF bit of the ESPI Data Command Register. After this
final byte has been transferred, the Master’s SS output will deassert and the SSV and
TEOF bits in the Data Command Register will be cleared. The CMDSTAT field in ESPI
Receive DMA Descriptors has no function.
Table 90. ESPI Tx DMA Descriptor Command Field
Reserved
Reserved
Reserved
SSV
For ESPI DMA descriptors, the 4-bit frame status field of the descriptor is depicted in the
formats shown in Tables 91 and 92.
Table 91. ESPI Tx DMA Descriptor Status field
0
0
COL
TUND
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Table 92. ESPI Rx DMA Descriptor Status field
RSS ABT ROVR
0
TUND, COL, ABT, ROVR. See the Status Register for a description of these bits.
RSS. Value of SS associated with final byte written (useful in I2S Mode to distinguish left/
right channel data).
ESPI Baud Rate Generator
In ESPI MASTER Mode, the BRG creates a lower frequency serial clock (SCK) for data
transmission synchronization between the Master and the external Slave. The input to the
BRG is the system clock. The ESPI Baud Rate High and Low Byte registers combine to
form a 16-bit reload value, BRG[15:0], for the ESPI BRG. The ESPI baud rate is calcu-
lated using the following equation:
System Clock Frequency (Hz)
------------------------------------------------------------------------
SPI Baud Rate (bps) =
2 BRG[15:0]
Minimum baud rate is obtained by setting BRG[15:0] to 0000hfor a clock divisor value
of (2 x 65536 = 131072).
When the ESPI is disabled, the BRG functions as a basic 16-bit timer with interrupt on
time-out. Observe the following steps to configure the BRG as a timer with interrupt on
time-out:
1. Disable the ESPI by clearing the ESPIEN1,0 bits in the ESPI Control Register.
2. Load the appropriate 16-bit count value into the ESPI Baud Rate High and Low Byte
registers.
3. Enable the BRG timer function and associated interrupt by setting the BRGCTL bit in
the ESPI Control Register to 1.
When configured as a general purpose timer, the SPI BRG interrupt interval is calculated
using the following equation:
SPI BRG Interrupt Interval (s) = System Clock Period (s) BRG[15:0]
ESPI Control Register Definitions
The remainder of this chapter describes the functions of the following ESPI control regis-
ters.
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Z16FMC Series Motor Control MCUs
Product Specification
170
•
•
•
•
•
•
•
ESPI Data Register
ESPI Transmit Data Command Register
ESPI Control Register
ESPI Mode Register
ESPI Status Register
ESPI State Register
ESPI Baud Rate High and Low Byte registers
ESPI Data Register
The ESPI Data Register, shown in Table 93, addresses both the outgoing Transmit Data
Register and the incoming Receive Data Register. Reads from the ESPI Data Register
return the contents of the Receive Data Register. The Receive Data Register is updated
with the contents of the Shift Register at the end of each transfer. Writes to the ESPI Data
Register load the Transmit Data Register unless TDRE = 0. Data is shifted out starting
with bit 7. The final bit received resides in bit position 0.
With the ESPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the ESPI configured as a Slave, writing a data byte to this register
loads the Shift Register in preparation for the next data transfer with the external Master.
In either the MASTER or SLAVE modes, if TDRE = 0, writes to this register are ignored.
When the character length is less than 8 bits (as set by the NUMBITS field in the ESPI
Mode Register), the transmit character must be left-justified in the ESPI Data Register. A
received character of less than 8 bits is right-justified (final bit received is in bit position
0). For example, if the ESPI is configured for 4-bit characters, the transmit characters must
be written to ESPIDATA[7:4] and the received characters are read from ESPIDATA[3:0].
Table 93. ESPI Data Register (ESPIDATA)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DATA
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E260h
Bit
Description
[7:0]
DATA
Data
Transmit and/or receive data. Writes to the ESPIDATA Register load the Shift Register. Reads
from the ESPIDATA Register return the value of the Receive Data Register.
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Product Specification
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ESPI Transmit Data Command Register
The ESPI Transmit Data Command Register, shown in Table 94, provides control of the
SS pin when it is configured as an output (MASTER Mode). The TEOF and SSV bits are
controlled by the DMA interface as well as by a bus write to this register.
Table 94. ESPI Transmit Data Command Register (ESPITDCR)
Bit
7
6
5
4
3
2
1
TEOF
0
0
Field
RESET
R/W
SSV
0
0
0
0
0
0
0
R
R
R
R
R
R
R/W
R/W
ADDR
FF_E261h
Bit
Description
Reserved
[7:2]
These bits are reserved and must be programmed to 000000.
[1]
TEOF
Transmit End Of Frame
This bit is used in MASTER Mode to indicate that the data in the Transmit Data Register is the
final byte of the transfer or frame. When the final byte has been sent SS (and SSV) change
state and TEOF automatically clears.
0 = The data in the Transmit Data Register is not the final character in the message.
1 = The data in the Transmit Data Register is the final character in the message.
[0]
SSV
Slave Select Value
When SSIO = 1, writes to this register controls the value output on the SS pin. See SSMD field
of the ESPI Mode Register for more details.
ESPI Control Register
The ESPI Control Register, shown in Table 95, configures the ESPI for transmit and
receive operations.
Table 95. ESPI Control Register (ESPICTL)
Bit
7
DIRQE
0
6
5
4
PHASE
0
3
CLKPOL
0
2
WOR
0
1
MMEN
0
0
ESPIEN0
0
Field
RESET
R/W
ESPIEN1 BRGCTL
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E262h
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Z16FMC Series Motor Control MCUs
Product Specification
172
Bit
Description
[7]
DIRQE
Data Interrupt Request Enable
This bit is used to disable or enable data (TDRE and RDRF) interrupts. Disabling the data
interrupts is needed when controlling data transfer by DMA or polling. Error interrupts are
not disabled. To block all ESPI interrupt sources, clear the ESPI interrupt enable bit in the
Interrupt Controller.
0 = TDRE and RDRF assertions do not cause an interrupt. Use this setting if controlling data
transfer through DMA or by software polling of TDRE and RDRF. The TUND, COL, ABT
and ROVR bits cause an interrupt.
1 = TDRE and RDRF assertions will cause an interrupt. TUND, COL, ABT and ROVR will
also cause interrupts. Use this setting if controlling data transfer through interrupt han-
dlers.
[6,0]
ESPIEN1,
ESPIEN0
ESPI Enable and Direction Control
00 = ESPI block is disabled. BRG is used as a general purpose timer by setting BRGCTL =
1.
01 = RECEIVE ONLY Mode. Use this setting if the software application is receiving data but
not sending. TDRE will assert, however the transmit interrupt and DMA requests will
not assert. In SLAVE Mode, the transmitted data will be all 1s. In MASTER Mode soft-
ware must still write to the Transmit Data Register to initiate the transfer.
10 = TRANSMIT ONLY Mode. Use this setting in MASTER or SLAVE Mode when the soft-
ware application is sending data but not receiving. RDRF will assert, but receive inter-
rupt and DMA requests not occur.
11 = TRANSMIT/RECEIVE Mode. Use this setting if the software application is both sending
and receiving information. Both TDRE and RDRF will be active.
[5]
BRGCTL
Baud Rate Generator Control
The function of this bit depends upon ESPIEN1,0. When ESPIEN1,0 = 00, this bit allows
enabling the BRG to provide periodic interrupts.
If the ESPI is disabled (ESPIEN1, ESPIEN0 = 00):
0 = The BRG timer function is disabled. Reading the Baud Rate High and Low registers
returns the BRG reload value.
1 = The BRG timer function and time-out interrupt are enabled. Reading the Baud Rate High
and Low registers returns the BRG Counter value.
If the ESPI is enabled:
0 = Reading the Baud Rate High and Low registers returns the BRG reload value. If MMEN
= 1, the BRG is enabled to generate SCK. If MMEN = 0, the BRG is disabled.
1 = Reading the Baud Rate High and Low registers returns the BRG Counter value. If
MMEN = 1, the BRG is enabled to generate SCK. If MMEN = 0, the BRG is enabled to
provide a Slave SCK time-out. See Slave Abort error description.
CAUTION: If reading the counter one byte at a time while the BRG is counting keep in mind
that the values will not be in sync. Zilog recommends reading the counter using word (2-
byte) reads.
[4]
PHASE
Phase Select
Sets the phase relationship of the data to the clock. For more information about operation of
the PHASE bit, see the ESPI Clock Phase and Polarity Control section on page 158.
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Bit
Description (Continued)
[3]
CLKPOL
Clock Polarity
0 = SCK idles Low (0).
1 = SCK idles High (1).
[2]
WOR
Wire-OR (Open-Drain) Mode Enabled
0 = ESPI signal pins not configured for open-drain.
1 = All four ESPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain
[1]
MMEN
ESPI MASTER Mode Enable
This bit controls the data I/O pin selection and SCK direction.
0 = Data-out on MISO, data-in on MOSI (used in SPI SLAVE Mode), SCK is an input.
1 = Data-out on MOSI, data-in on MISO (used in SPI MASTER Mode), SCK is an output.
ESPI Mode Register
The ESPI Mode Register, shown in Table 96, configures the character bit width and mode
of the ESPI I/O pins.
Table 96. ESPI Mode Register (ESPIMODE)
Bit
7
6
5
4
3
NUMBITS[2:0]
000
2
1
SSIO
0
0
SSPO
0
Field
RESET
R/W
SSMD
000
R/W
R/W
R/W
R/W
ADDR
FF_E263h
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Z16FMC Series Motor Control MCUs
Product Specification
174
Bit
Description
[7:5]
SSMD
SLAVE SELECT Mode
This field selects the behavior of SS as a framing signal. For a detailed description of
these modes; see the Slave Select section on page 156.
000 = SPI Mode
When SSIO = 1, the SS pin is driven directly from the SSV bit in the Transmit Data Com-
mand Register. The Master software or DMA must set SSV (or a GPIO output if the SS
pin is not connected to the appropriate Slave) to the asserted state prior to or on the
same clock cycle with which the Transmit Data Register is written with the initial byte.
At the end of a frame (after the final RDRF event), SSV is deasserted by software. Alter-
natively, SSV is automatically deasserted by hardware if the TEOF bit in the Transmit
Data Command Register is set when the final transmit byte is loaded. In SPI Mode, SCK
is active only for data transfer (one clock cycle per bit transferred).
001 = LOOPBACK Mode
When ESPI is configured as Master (MMEN = 1) the outputs are deasserted and data is
looped from shift register out to shift register in. When ESPI is configured as a Slave
(MMEN = 0) and SS in asserts, MISO (Slave output) is tied to MOSI (Slave input) to pro-
vide an a remote loop back (echo) function.
2
010 = I S Mode
In this mode, the value from SSV will be output by the Master on the SS pin one SCK
period before the data and will remain in that state until the start of the next frame. Typi-
cally this mode is used to send back-to-back frames with SS alternating on each frame. A
frame boundary is indicated in the Master when SSV changes. A frame boundary is
detected in the Slave by SS changing state. The SS framing signal will lead the frame by
one SCK period. In this mode, SCK will run continuously, starting with the initial SS asser-
tion. Frames will run back-to-back as long as software/DMA continue to provide data. The
2
I S protocol (Inter IC Sound) is used to carry left and right channel audio data with the SS
signal indicating which channel is being sent. In SLAVE Mode, the change in state of SS
(Low to High or High to Low) will trigger the start of a transaction on the next SCK cycle.
[4:2]
Number of Data Bit Per Character to Transfer
NUMBITS[2:0] This field contains the number of bits to shift for each character transfer. For information
about valid bit positions when the character length is less than 8 bits, see the ESPI Data
Register section on page 170.
000 = 8 bits.
001 = 1 bit.
010 = 2 bits.
011 = 3 bits.
100 = 4 bits.
101 = 5 bits.
110 = 6 bits.
111 = 7 bits.
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Bit
Description (Continued)
[1]
SSIO
Slave Select I/O
This bit controls the direction of the SS pin. In SINGLE MASTER Mode, SSIO is set to 1
unless a separate GPIO pin is being used to provide the SS output function. In the SPI
Slave or Multi-Master configuration SSIO is set to 0.
0 = SS pin configured as an input (SPI SLAVE and MULTI-MASTER modes).
1 = SS pin configured as an output (SPI SINGLE MASTER Mode).
[0]
SSPO
Slave Select Polarity
This bit controls the polarity of the SS pin.
0 = SS is active Low. (SSV = 1 corresponds to SS = 0).
1 = SS is active High. (SSV = 1 corresponds to SS = 1).
ESPI Status Register
The ESPI Status Register, shown in Table 97, indicates the current state of the ESPI. All
bits revert to their Reset state, if the ESPI is disabled.
Table 97. ESPI Status Register (ESPISTAT)
Bit
7
TDRE
0
6
5
4
ABT
0
3
ROVR
0
2
RDRF
0
1
TFST
0
0
SLAS
1
Field
RESET
R/W
TUND
0
COL
0
R
R/W*
R/W*
R/W*
R/W*
R
R
R
ADDR
FF_E264h
Note: *R/W = Read access. Write a 1 to clear the bit to 0.
Bit
Description
[7]
TDRE
Transmit Data Register Empty
0 = Transmit Data Register is full or ESPI is disabled.
1 = Transmit Data Register is empty. A write to the ESPI (Transmit) Data Register clears this
bit.
[6]
TUND
Transmit Underrun
0 = A Transmit Underrun error has not occurred.
1 = A Transmit Underrun error has occurred.
[5]
COL
Collision
0 = A Multi-Master collision (mode fault) has not occurred.
1 = A Multi-Master collision (mode fault) has been detected.
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Bit
Description (Continued)
[4]
ABT
Slave Mode Transaction Abort
This bit is set if the ESPI is configured in SLAVE Mode, a transaction is occurring and SS deas-
serts before all bits of a character have been transferred as defined by the NUMBITS field of
the ESPIMODE Register. This bit is also be set in SLAVE Mode by an SCK monitor time-out
(MMEN = 0, BRGCTL = 1).
0 = A SLAVE Mode transaction abort has not occurred.
1 = A SLAVE Mode transaction abort has been detected.
[3]
ROVR
Receive Overrun
0 = A Receive Overrun error has not occurred.
1 = A Receive Overrun error has occurred.
[2]
RDRF
Receive Data Register Full
0 = Receive Data Register is empty.
1 = Receive Data Register is full. A read from the ESPI (Receive) Data Register clears this bit.
[1]
TFST
Transfer Status
0 = No data transfer is currently in progress.
1 = Data transfer is currently in progress.
[0]
SLAS
Slave Select
Reading this bit returns the current value of the SS exclusive-OR’d with the SSPO bit.
0 = SS pin is Low, if SSPO = 0, SS pin is High if SSPO = 1 (SS is asserted).
1 = SS pin is High, if SSPO = 0, SS pin is Low if SSPO = 1 (SS is deasserted).
ESPI State Register
The ESPI State Register, shown in Table 98, provides observability of the ESPI clock, data
and internal state.
Table 98. ESPI State Register (ESPISTATE)
Bit
7
SCKI
0
6
SDI
0
5
4
3
2
1
0
Field
RESET
R/W
ESPISTATE
0
R
R
R
ADDR
FF_E265h
Bit
Description
[7]
SCKI
Serial Clock Input
This bit reflects the state of the serial clock pin.
0 = The SCK input pin is Low
1 = The SCK input pin is High
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Bit
Description (Continued)
[6]
SDI
Serial Data Input
This bit reflects the state of the serial data input (MOSI or MISO depending on the MMEN
bit).
0 = The serial data input pin is Low.
1 = The serial data input pin is High.
[5:0]
ESPI State Machine
ESPISTATE Indicates the current state of the internal ESPI State Machine. This information is intended
for manufacturing test. The state values may change in future hardware revisions and are
not intended to be used by a software driver. Table 99 defines the valid states.
Table 99. ESPISTATE Values and Description
ESPISTATE Value Description
00_0000
00_0001
00_0010
00_0011
01_0000
11_0001
11_0010
10_1110
10_1111
10_1100
10_1101
10_1010
10_1011
10_1000
10_1001
10_0110
10_0111
10_0100
10_0101
10_0010
10_0011
10_0000
10_0001
Idle
Slave Wait For SCK
2
I S SLAVE Mode start delay
2
I S SLAVE Mode start delay
SPI MASTER Mode start delay
2
I S MASTER Mode start delay
2
I S MASTER Mode start delay
Bit 7 Receive
Bit 7 Transmit
Bit 6 Receive
Bit 6 Transmit
Bit 5 Receive
Bit 5 Transmit
Bit 4 Receive
Bit 4 Transmit
Bit 3 Receive
Bit 3 Transmit
Bit 2 Receive
Bit 2 Transmit
Bit 1 Receive
Bit 1 Transmit
Bit 0 Receive
Bit 0 Transmit
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ESPI Baud Rate High and Low Byte Registers
The ESPI Baud Rate High and Low Byte registers, shown in Tables 100 and 101, combine
to form a 16-bit reload value, BRG[15:0], for the ESPI Baud Rate Generator. The ESPI
baud rate is calculated using the following equation:
System Clock Frequency (Hz)
------------------------------------------------------------------------
SPI Baud Rate (bps) =
2 BRG[15:0]
Minimum baud rate is obtained by setting BRG[15:0] to 0000hfor a clock divisor value
of (2 x 65536 = 131072).
When the ESPI function is disabled, the BRG functions as a basic 16-bit timer with inter-
rupt on time-out.
Follow the procedure below to configure the BRG as a general purpose timer with inter-
rupt on time-out:
1. Disable the ESPI by setting ESPIEN[1:0] = 00 in the SPI Control Register.
2. Load the appropriate 16-bit count value into the ESPI Baud Rate High and Low Byte
registers.
3. Enable the BRG timer function and associated interrupt by setting the BRGCTL bit in
the ESPI Control Register to 1.
When configured as a general purpose timer, the SPI BRG interrupt interval is calculated
using the following equation:
SPI BRG Interrupt Interval (s) = System Clock Period (s) BRG[15:0]
Table 100. ESPI Baud Rate High Byte Register (ESPIBRH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
BRH
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E266h
Bit
Description
[7:0]
BRH
ESPI Baud Rate High Byte
Most significant byte, BRG[15:8], of the ESPI Baud Rate Generator’s reload value.
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Product Specification
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Table 101. ESPI Baud Rate Low Byte Register (ESPIBRL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
BRL
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/w
ADDR
FF_E267h
Bit
Description
[7:0]
BRL
ESPI Baud Rate Low Byte
Least significant byte, BRG[7:0], of the ESPI Baud Rate Generator’s reload value.
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Product Specification
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2
I C Master/Slave Controller
The I2C Master/Slave Controller makes the ZNEO CPU bus compatible with the I2C pro-
tocol. The I2C bus consists of the serial data signal (SDA) and a serial clock (SCL) signal
bidirectional lines. Features of the I2C Controller include:
•
•
•
•
•
•
•
Operates in MASTER/SLAVE or SLAVE ONLY modes
Supports arbitration in a Multi-Master environment (MASTER/SLAVE Mode)
Supports data rates up to 400 kbps
7-bit or 10-bit slave address recognition (interrupt only on address match)
Optional general call address recognition
Optional digital filter on receive SDA and SCL lines
Optional Interactive Receive Mode allows software interpretation of each received
address and/or data byte before acknowledging
•
•
Unrestricted number of data bytes per transfer
Baud Rate Generator (BRG) is used as a general purpose timer with interrupt if the I2C
controller is disabled
Architecture
Figure 33 displays the architecture of the I2C Controller.
2
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Z16FMC Series Motor Control MCUs
Product Specification
181
SDA
SCL
Shift
SHIFT
Load
I2CDATA
Baud Rate Generator
I2CBRH
I2CBRL
Tx/Rx State Machine
I2CSTATE
I2CISTAT
I2CCTL
I2CMODE
I2CSLVAD
2
I C Interrupt
Tx and Rx DMA Requests
Register Bus
2
Figure 33. I C Controller Block Diagram
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Product Specification
182
I2C Master/Slave Controller Registers
Table 102 summarizes the I2C Master/Slave Controller software-accessible registers.
2
Table 102. I C Master/Slave Controller Registers
Name
Abbreviation Description
2
I C Data
I2CDATA
I2CISTAT
I2CCTL
Transmit/Receive Data Register.
2
I C Interrupt Status
Interrupt Status Register.
2
I C Control
Control Register basic control functions.
High byte of baud rate generator initialization value.
Low byte of baud rate generator initialization value.
State Register.
2
I C Baud Rate High I2CBRH
2
I C Baud Rate Low
I2CBRL
2
I C State
I2CSTATE
I2CMODE
2
I C Mode
Selects MASTER or SLAVE modes, 7-bit or 10-bit addressing.
Configures address recognition, Defines Slave Address bits [9:8].
2
I C Slave Address
I2CSLVAD
Defines Slave Address bits [7:0].
Comparison with MASTER ONLY Mode I2C Controller
Porting code written for the Master-Only I2C Controller found on other Z8 Encore! parts
to the I2C Master/Slave Controller is straightforward. The I2CDATA, I2CCTL, I2CBRH
and I2CBRL register definitions are not changed. The difference between the Master-Only
I2C Controller and the I2C Master/Slave Controller designs is explained below.
•
•
•
The Status Register (I2CSTATE) from the Master-only I2C Controller is split into the
Interrupt Status (I2CISTAT) Register and the State (I2CSTATE) Register because there
are more interrupt sources. The ACK, 10B, TAS (now called AS) and DSS (now called
DS) bits formerly in the Status Register are moved to the State Register.
The I2CSTATE Register is called as Diagnostic State (I2CDST) Register in the MAS-
TER ONLY Mode version. The I2CDST Register provides diagnostic information. The
I2CSTATE Register contains status and state information that are useful to software in
operational mode.
The I2CMODE Register is called as Diagnostic Control (I2CDIAG) Register in the
MASTER ONLY Mode version. The I2CMODE Register provides control for SLAVE
modes of operation as well as the most significant two bits of the 10-bit slave address.
•
•
The I2CSLVAD Register is added for programming the slave address.
The ACKV bit in the I2CSTATE Register enables the Master to verify the Acknowl-
edge from the Slave before sending the next byte.
•
Support for multi-master environments. If arbitration is lost when operating as a Mas-
ter, the ARBLST bit in the I2CISTAT Register is set and the mode automatically
switches to SLAVE Mode.
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Operation
The I2C Master/Slave Controller operates in either SLAVE ONLY Mode or MASTER/
SLAVE Mode with Master arbitration. In MASTER/SLAVE Mode, it is used as the only
Master on the bus or as one of several Masters on the bus with arbitration. In a multi-Mas-
ter environment, the controller switches from MASTER to SLAVE Mode on losing arbi-
tration.
Though slave operation is fully supported in MASTER/SLAVE Mode, if a device is
intended to operate only as a slave, the SLAVE ONLY Mode is selected. In SLAVE ONLY
Mode, the device does not initiate a transaction even if software inadvertently sets the start
bit.
SDA and SCL Signals
The I2C sends all addresses, data and acknowledge signals over the SDA line, the most-
significant bit first. SCL is the clock for the I2C bus. When the SDA and SCL pin alternate
functions are selected for their respective GPIO ports, the pins are automatically config-
ured for open-drain operation.
The Master is responsible for driving the SCL clock signal. During the Low period of the
clock, a Slave holds the SCL signal Low to suspend the transaction if it is not ready to pro-
ceed. The Master releases the clock at the end of the Low period and notices that the clock
remains Low instead of returning to a High level. When the Slave releases the clock, the
I2C Master continues the transaction. All data is transferred in bytes and there is no limit
to the amount of data transferred in one operation. When transmitting address, data or
acknowledge, the SDA signal changes in the middle of the Low period of SCL. When
receiving address, data, or acknowledge, the SDA signal is sampled in the middle of the
High period of SCL.
A low-pass digital filter is applied to the SDA and SCL receive signals by setting the filter
enable (FILTEN) bit in the I2C Control Register. When the filter is enabled, any glitch,
which is less than a system clock period in width is rejected. This filter must be enabled
when running in I2C Fast Mode (400kbps) and is also used at lower data rates.
I2C Interrupts
The I2C Controller contains multiple interrupt sources that are combined into one interrupt
request signal to the interrupt controller. If the I2C Controller is enabled, the source of the
interrupt is determined by bits, which are set in the I2CISTAT Register. If the I2C Control-
ler is disabled, the BRG Controller is used to generate general-purpose timer interrupts.
Each interrupt source other than the baud rate generator interrupt has an associated bit in
the I2CISTAT Register, which clears automatically when software reads the register or
performs some other task such as reading or writing the data register.
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Transmit Interrupts
Transmit interrupts (TDRE bit = 1 in I2CISTAT) occur under the following conditions:
•
•
The Transmit Data Register is empty and the TXI bit = 1 in the I2C Control Register
The I2C Controller is enabled, with any one of the following:
–
–
The first bit of a 10-bit address is shifted out
The first bit of the final byte of an address is shifted out and the RD bit is deas-
serted
–
The first bit of a data byte is shifted out
Writing to the I2C Data Register always clears the TRDE bit to 0.
Receive Interrupts
Receive interrupts (RDRF bit = 1 in I2CISTAT) occur when a byte of data has been
received by the I2C Controller. The RDRF bit is cleared by reading from the I2C Data
Register. If the RDRF interrupt is not serviced prior to the completion of the next receive
byte, the I2C Controller holds SCL Low during the final data bit of the next byte until
RDRF is cleared to prevent receive overruns. A receive interrupt does not occur when a
Slave receives an address byte or for data bytes following a slave address that did not
match. An exception is if the Interactive Receive Mode (IRM) bit is set in the I2CMODE
Register in which case receive interrupts occur for all receive address and data bytes in
SLAVE Mode.
Slave Address Match Interrupts
Slave address match interrupts (SAM bit = 1 in I2CISTAT) occur when the I2C Controller
is in SLAVE Mode and an address is received which matches the unique slave address.
The General Call Address (0000_0000) and STARTBYTE (0000_0001) are recognized
if the GCE bit = 1 in the I2CMODE Register. Software verifies the RD bit in the
I2CISTAT Register to determine if the transaction is a read or write transaction. The Gen-
eral Call Address and STARTBYTE addresses are also distinguished by the RD bit. The
general call address (GCA) bit of the I2CISTAT Register indicates whether the address
match occurred on the unique slave address or the General Call/STARTBYTE address.
The SAM bit clears automatically when the I2CISTAT Register is read.
If configured using the MODE[1:0] field of the I2C Mode Register for 7-bit slave address-
ing, the most significant 7 bits of the first byte of the transaction are compared against the
SLA[6:0] bits of the Slave Address Register. If configured for 10-bit slave addressing, the
first byte of the transaction is compared against {11110,SLA[9:8], R/W} and the second
byte is compared against SLA[7:0].
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Arbitration Lost Interrupts
Arbitration Lost interrupts (ARBLST bit = 1 in I2CISTAT) occur when the I2C Controller
is in MASTER Mode and loses arbitration (outputs a 1 on SDA and receives a 0 on SDA).
The I2C Controller switches to SLAVE Mode when this occurs. This bit clears automati-
cally when the I2CISTAT Register is read.
Stop/Restart Interrupts
A Stop/Restart event interrupt (SPRS bit = 1 in I2CISTAT) occurs when the I2C Controller
is in SLAVE Mode and a Stop or Restart condition is received, indicating the end of the
transaction. The RSTR bit in the I2C State Register (see page 209) indicates whether the
bit was set due to a Stop or Restart condition. When a Restart occurs, a new transaction by
the same Master is expected to follow. This bit is cleared automatically when the
I2CISTAT Register is read. The Stop/Restart interrupt only occurs on a selected (address
match) slave.
Not Acknowledge Interrupts
Not Acknowledge interrupts (NCKI bit = 1 in I2CISTAT) occur in MASTER Mode when
a Not Acknowledge is received or sent by the I2C Controller and the start or stop bit is not
set in the I2C State Register (see page 209). In MASTER Mode, the Not Acknowledge
interrupt clears by setting the start or stop bit. When this interrupt occurs in MASTER
Mode, the I2C Controller waits until it is cleared before performing any action. In SLAVE
Mode, the Not Acknowledge interrupt occurs when a Not Acknowledge is received in
response to the data sent. The NCKI bit clears in SLAVE Mode when software reads the
I2CISTAT Register.
General Purpose Timer Interrupt from Baud Rate Generator
If the I2C Controller is disabled (IEN bit in the I2CCTL Register = 0) and the BIRQ bit in
the I2CCTL Register = 1, an interrupt is generated when the BRG counts down to 1. The
BRG reloads and continues counting, providing a periodic interrupt. None of the bits in
the I2CISTAT Register are set, allowing the BRG in the I2C Controller to be used as a gen-
eral purpose timer when the I2C Controller is disabled.
Start and Stop Conditions
The Master generates the start and stop conditions to start or end a transaction. To start a
transaction, the I2C Controller generates a start condition by pulling the SDA signal Low
while SCL is High. To complete a transaction, the I2C Controller generates a stop condi-
tion by creating a Low-to-High transition of the SDA signal while the SCL signal is High.
The start and stop events occur when the start and stop bits in the I2C Control Register are
written by software to begin or end a transaction. Any byte transfer currently under way
finishes, including the acknowledge phase before the start or stop condition occurs.
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Software Control of I2C Transactions
The I2C Controller is configured using the I2C Control and I2C Mode registers. The
MODE[1:0] field of the I2C Mode Register allows for the configuration of the I2C Con-
troller for MASTER/SLAVE or SLAVE ONLY Mode, and configures the slave for 7-bit
or 10-bit addressing recognition. The Baud Rate High and Low Byte registers must be
programmed for the I2C baud rate in SLAVE Mode as well as in MASTER Mode. In
SLAVE Mode, the baud rate value programmed must match the master's baud rate within
+/- 25% for proper operation.
MASTER/SLAVE Mode is used for:
•
•
•
Master only operation in a single master, one or more slave I2C system
Master/Slave in a multi-master, multi-slave I2C system
Slave only operation in an I2C system
In SLAVE ONLY Mode, the start bit of the I2C Control Register is ignored (software can-
not initiate a master transaction by accident). This restricts the operation to SLAVE ONLY
Mode and prevents accidental operation in MASTER Mode.
Software controls I2C transactions by enabling the I2C Controller interrupt in the interrupt
controller or by polling the I2C Status Register.
To use interrupts, the I2C interrupt must be enabled in the Interrupt Controller and fol-
lowed by executing an EI instruction. The TXI bit in the I2C Control Register must be set
to enable transmit interrupts. An I2C interrupt service routine then verifies the I2C Status
Register to determine the cause of the interrupt.
To control transactions by polling, the interrupt bits (TDRE, RDRF, SAM, ARBLST,
SPRS and NCKI) in the I2C Status Register must be polled. The TDRE bit asserts regard-
less of the state of the TXI bit.
Master Transactions
The following sections describe the Master read and write transactions to both 7- and
10-bit Slaves.
Master Arbitration
If a Master loses arbitration during the address byte, it releases the SDA line, switches to
SLAVE Mode and monitors the address to determine if it is selected as a Slave. If a Master
loses arbitration during a transmit data byte, it releases the SDA line and waits for the next
stop or start condition.
The Master detects a loss of arbitration when a 1 is transmitted but a 0 is received from the
bus in the same bit-time. This loss occurs if more than one Master is simultaneously
accessing the bus. Loss of arbitration occurs during the address phase (two or more Mas-
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ters accessing different Slaves) or during the data phase when the Masters are attempting
to write different data to the same Slave.
When a Master loses arbitration, software is informed by means of the Arbitration Lost
interrupt. Software repeats the same transaction again at a later time.
A special case occurs when a slave transaction starts just before software attempts to start
a new master transaction by setting the start bit. In this case the state machine enters the
slave states before the start bit is set and the I2C Controller does not arbitrate. If a slave
address match occurs and the I2C Controller receives or transmits data, the start bit is
cleared and an Arbitration Lost interrupt is asserted. Software minimizes the chance of
this occurring by checking the BUSY bit in the I2CSTATE Register before initiating a
master transaction. If a slave address match does not occur, the Arbitration Lost interrupt
does not occur and the start bit is not cleared. The I2C Controller initiates the master trans-
action after the I2C bus is no longer busy.
Master Address Only Transactions
It is sometimes appropriate to perform an address-only transaction to determine if a partic-
ular Slave device is able to respond. This transaction is performed by monitoring the
ACKV bit in the I2CSTATE Register after the address has been written to the I2CDATA
Register and the start bit has been set. After ACKV is set, the ACK bit in the I2CSTATE
Register determines if the Slave is able to communicate. The stop bit must be set in the
I2CCTL Register to terminate the transaction without transferring data. For a 10-bit slave
address, if the first address byte is acknowledged, the second address byte must also be
sent to determine if the appropriate slave is responding.
Another approach is to set both the stop and start bits (for sending a 7-bit address). After
both bits are cleared (7-bit address has been sent and transaction is complete), the ACK bit
is read to determine if the slave is acknowledged. For a 10-bit slave, set the stop bit after
the second TDRE interrupt (second address byte is being sent).
Master Transaction Diagrams
In the following transaction diagrams, shaded regions indicate data transferred from the
Master to the Slave and unshaded regions indicate data transferred from the Slave to the
Master. The transaction field labels are defined as:
S
Start
W
A
A
P
Write
Acknowledge
Not Acknowledge
Stop
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Master Write Transaction with a 7-Bit Address
Figure 34 displays the data transfer format from a Master to a 7-bit addressed Slave.
Slave
Address
S
W=0
A
Data
A
Data
A
Data
A/A
P/S
Figure 34. Data Transfer Format: Master Write Transaction with a 7-Bit Address
Follow the procedure below to perform a Master transmit operation to a 7-bit addressed
Slave.
1. Software initializes the MODE field in the I2C Mode Register for MASTER/SLAVE
Mode with either 7-bit or 10-bit slave address. The MODE field selects the address
width for this node when addressed as a Slave, not for the remote Slave. Software
asserts the IEN bit in the I2C Control Register.
2. Software asserts the TXI bit of the I2C Control Register to enable Transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data Register is empty.
4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0)
to the I2C Data Register.
5. Software sets the start bit of the I2C Control Register.
6. The I2C Controller sends the start condition to the I2C Slave.
7. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data
Register.
8. When one bit of address is shifted out by the SDA signal, the Transmit interrupt
asserts.
9. Software responds by writing the transmit data into the I2C Data Register.
10. The I2C Controller shifts the rest of the address and write bit out the SDA signal.
11. The I2C Slave sends an acknowledge (by pulling the SDA signal Low) during the next
High period of SCL. The I2C Controller sets the ACK bit in the I2C State Register.
If the slave does not acknowledge the address byte, the I2C Controller sets the NCKI
bit in the I2C Interrupt Status Register, sets the ACKV bit and clears the ACK bit in
the I2C State Register. Software responds to the Not Acknowledge interrupt by setting
the stop bit and clearing the TXI bit. The I2C Controller flushes the Transmit Data
Register, sends the stop condition on the bus and clears the STOP and NCKI bits. The
transaction is complete (ignore the following steps).
12. The I2C Controller loads the contents of the I2C Shift Register with the contents of the
I2C Data Register.
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13. The I2C Controller shifts the data out of through the SDA signal. When the first bit is
sent, the Transmit interrupt asserts.
14. If more bytes remain to be sent, return to step 9.
15. When there is no more data to be sent, software responds by setting the stop bit of the
I2C Control Register (or start bit to initiate a new transaction).
16. If no additional transaction is queued by the Master, software clears the TXI bit of the
I2C Control Register.
17. The I2C Controller completes transmission of the data on the SDA signal.
18. The I2C Controller sends the stop condition to the I2C bus.
If the Slave terminates the transaction early by responding with a Not Acknowledge dur-
ing the transfer, the I2C Controller asserts the NCKI interrupt and halts. Software must ter-
minate the transaction by setting either the stop bit (end transaction) or the start bit (end
this transaction, start a new one). In this case, it is not necessary for software to set the
FLUSH bit of the I2CCTL Register to flush the data that was previously written but not
transmitted. The I2C Controller hardware automatically flushes transmit data in this Not
Acknowledge case.
Note:
Master Write Transaction with a 10-Bit Address
Figure 35 displays the data transfer format from a Master to a 10-bit addressed Slave.
Slave Address
1st Byte
Slave Address
2nd Byte
S
W=0
A
A
Data
A
Data
A/A
F/S
Figure 35. Data Transfer Format: Master Write Transaction with 10-Bit Address
The first seven bits transmitted in the first byte are 11110XX. The two XXbits are the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
read/write control bit (= 0). The transmit operation is carried out in the same manner as 7-
bit addressing.
Follow the procedure below to perform a Master transmit operation to a 10-bit addressed
Slave.
1. Software initializes the MODE field in the I2C Mode Register for MASTER/SLAVE
Mode with 7- or 10-bit addressing (I2C bus protocol allows mixing slave address
types). The MODE field selects the address width for this node when addressed as a
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Slave, not for the remote Slave. Software asserts the IEN bit in the I2C Control Regis-
ter.
2. Software asserts the TXI bit of the I2C Control Register to enable Transmit interrupts.
3. The I2C interrupt asserts because the I2C Data Register is empty.
4. Software responds to the TDRE interrupt by writing the first slave address byte
(11110xx0). The least-significant bit must be 0 for the write operation.
5. Software asserts the start bit of the I2C Control Register.
6. The I2C Controller sends the start condition to the I2C Slave.
7. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data
Register.
8. When one bit of address is shifted out by the SDA signal, the Transmit interrupt
asserts.
9. Software responds by writing the second byte of address into the contents of the I2C
Data Register.
10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA
signal.
11. The I2C Slave sends an acknowledge by pulling the SDA signal Low during the next
High period of SCL. The I2C Controller sets the ACK bit in the I2C Status Register.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKI bit in the I2C Status Register, sets the ACKV bit and clears the ACK bit in the
I2C State Register. Software responds to the Not Acknowledge interrupt by setting the
stop bit and clearing the TXI bit. The I2C Controller flushes the second address byte
from the data register, sends the stop condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore the following steps).
12. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data
Register (2nd address byte).
13. The I2C Controller shifts the second address byte out the SDA signal. When the first
bit is sent, the Transmit interrupt asserts.
14. Software responds by writing the data to be written out to the I2C Control Register.
15. The I2C Controller shifts out the rest of the second byte of slave address (or ensuing
data bytes if looping) by the SDA signal.
16. The I2C Slave sends an acknowledge by pulling the SDA signal Low during the next
High period of SCL. The I2C Controller sets the ACK bit in the I2C Status Register.
If the slave does not acknowledge, see the second paragraph of step 11 above.
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17. The I2C Controller shifts the data out by the SDA signal. After the first bit is sent, the
Transmit interrupt asserts.
18. If more bytes remain to be sent, return to step 14.
19. Software responds by asserting the stop bit of the I2C Control Register.
20. The I2C Controller completes transmission of the data on the SDA signal.
21. The I2C Controller sends the stop condition to the I2C bus.
If the Slave responds with a Not Acknowledge during the transfer, the I2C Controller
asserts the NCKI bit, sets the ACKV bit and clears the ACK bit in the I2C State Register
and halts. Software terminates the transaction by setting either the stop bit (end transac-
tion) or the start bit (end this transaction, start a new one). The Transmit Data Register is
flushed automatically.
Note:
Master Read Transaction with a 7-Bit Address
Figure 36 displays the data transfer format for a read operation to a 7-bit addressed Slave.
S
Slave Address
R=1
A
Data
A
Data
A
P/S
Figure 36. Data Transfer Format: Master Read Transaction with 7-Bit Address
Follow the procedure below to perform a Master read operation to a 7-bit addressed Slave.
1. Software initializes the MODE field in the I2C Mode Register for MASTER/SLAVE
Mode with 7- or 10-bit addressing (I2C bus protocol allows mixing slave address
types). The MODE field selects the address width for this node when addressed as a
Slave, not for the remote Slave. Software asserts the IEN bit in the I2C Control Regis-
ter.
2. Software writes the I2C Data Register with a 7-bit slave address plus the read bit (= 1).
3. Software asserts the start bit of the I2C Control Register.
4. If the operation is a single byte transfer, software asserts the NAK bit of the I2C
Control Register so that after the first byte of data has been read by the I2C Controller,
a Not Acknowledge instruction is sent to the I2C Slave.
5. The I2C Controller sends the start condition.
6. The I2C Controller sends the address and read bit out the SDA signal.
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7. The I2C Slave acknowledges the address by pulling the SDA signal Low during the
next High period of SCL.
If the slave does not acknowledge the address byte, the I2C Controller sets the NCKI
bit in the I2C Status Register, sets the ACKV bit and clears the ACK bit in the I2C
State Register. Software responds to the Not Acknowledge interrupt by setting the
stop bit and clearing the TXI bit. The I2C Controller flushes the Transmit Data Regis-
ter, sends the stop condition on the bus and clears the STOP and NCKI bits. The trans-
action is complete (ignore the following steps).
8. The I2C Controller shifts in the first byte of data from the I2C Slave on the SDA
signal.
9. The I2C Controller asserts the Receive interrupt.
10. Software responds by reading the I2C Data Register. If the next data byte is to be the
final byte, software must set the NAK bit of the I2C Control Register.
11. The I2C Controller sends a Not Acknowledge to the I2C Slave if it is the final byte;
otherwise it sends an Acknowledge.
12. If there are more bytes to transfer, the I2C Controller returns to step 7.
13. A NAK interrupt (NCKI bit in I2CISTAT) is generated by the I2C Controller.
14. Software responds by setting the stop bit of the I2C Control Register.
15. A stop condition is sent to the I2C Slave.
Master Read Transaction with a 10-Bit Address
Figure 37 displays the read transaction format for a 10-bit addressed Slave.
Slave Address
1st Byte
Slave Address
2nd Byte
Slave Address
1st Byte
S
W=0 A
A S
R=1
A
Data
A
Data A P
Figure 37. Data Transfer Format: Master Read Transaction with 10-Bit Address
The first seven bits transmitted in the first byte are 11110XX. The two XXbits are the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
Follow the procedure below to perform a data transfer for a read operation to a 10-bit
addressed Slave.
1. Software initializes the MODE field in the I2C Mode Register for MASTER/SLAVE
Mode with 7-bit or 10-bit addressing (I2C bus protocol allows mixing slave address
types). The MODE field selects the address width for this node when addressed as a
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Slave, not for the remote Slave. Software asserts the IEN bit in the I2C Control Regis-
ter.
2. Software writes 11110b followed by the two most significant address bits and a 0
(write) to the I2C Data Register.
3. Software asserts the start bit of the I2C Control Register.
4. The I2C Controller sends the start condition.
5. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data
Register.
6. When the first bit is shifted out, a Transmit interrupt asserts.
7. Software responds by writing the least significant eight bits of address to the I2C Data
Register.
8. The I2C Controller completes shifting of the first address byte.
9. The I2C Slave sends an acknowledge by pulling the SDA signal Low during the next
High period of SCL.
If the slave does not acknowledge the address byte, the I2C Controller sets the NCKI
bit in the I2C Status Register, sets the ACKV bit and clears the ACK bit in the I2C
State Register. Software responds to the Not Acknowledge interrupt by setting the
stop bit and clearing the TXI bit. The I2C Controller flushes the Transmit Data Regis-
ter, sends the stop condition on the bus and clears the stop and NCKI bits. The transac-
tion is complete (ignore the following steps).
10. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data
Register (lower byte of 10 bit address).
11. The I2C Controller shifts out the next eight bits of address. After the first bit shifts, the
I2C Controller generates a Transmit interrupt.
12. Software responds by setting the start bit of the I2C Control Register to generate a
repeated Start.
13. Software responds by writing 11110bfollowed by the 2-bit slave address, and a 1
(read) to the I2C Data Register.
14. If you want to read only one byte, software responds by setting the NAK bit of the
I2C Control Register.
15. After the I2C Controller shifts out the address bits mentioned in step 9 (second address
transfer), the I2C Slave sends an acknowledge by pulling the SDA signal Low during
the next High period of SCL.
If the slave does not acknowledge the address byte, the I2C Controller sets the NCKI
bit in the I2C Status Register, sets the ACKV bit and clears the ACK bit in the I2C
State Register. Software responds to the Not Acknowledge interrupt by setting the
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stop bit and clearing the TXI bit. The I2C Controller flushes the Transmit Data Regis-
ter, sends the stop condition on the bus and clears the STOP and NCKI bits. The trans-
action is complete (ignore the following steps).
16. The I2C Controller sends the repeated start condition.
17. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data
Register (third address transfer).
18. The I2C Controller sends 11110bfollowed by the two most significant bits of the
Slave read address and a 1 (read).
19. The I2C Slave sends an acknowledge by pulling the SDA signal Low during the next
High period of SCL.
20. The I2C Controller shifts in a byte of data from the Slave.
21. The I2C Controller asserts the Receive interrupt.
22. Software responds by reading the I2C Data Register. If the next data byte is to be the
final byte, software must set the NAK bit of the I2C Control Register.
23. The I2C Controller sends an Acknowledge or Not Acknowledge to the I2C Slave
based on the NAK bit.
24. If there are more bytes to transfer, the I2C Controller returns to step 18.
25. The I2C Controller generates a NAK interrupt (NCKI bit in I2CISTAT).
26. Software responds by setting the stop bit of the I2C Control Register.
27. A stop condition is sent to the I2C Slave.
Slave Transactions
The following sections describe Read and Write transactions to the I2C Controller config-
ured for 7-bit and 10-bit SLAVE modes.
Slave Address Recognition
The following slave address recognition options are supported:
Slave 7-Bit Address Recognition Mode. If IRM = 0 during the address phase and the
controller is configured for Master/Slave or Slave 7-bit address mode, the hardware
detects a match to the 7-bit slave address defined in the I2CSLVAD Register and generates
the Slave Address Match interrupt (SAM bit = 1 in I2CISTAT Register). The I2C Control-
ler automatically responds during the acknowledge phase with the value in the NAK bit of
the I2CCTL Register.
Slave 10-Bit Address Recognition Mode. If IRM = 0 during the address phase and the
controller is configured for Master/Slave or Slave 10-bit address mode, the hardware
detects a match to the 10-bit slave address defined in the I2CMODE and I2CSLVAD reg-
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isters and generates the Slave Address Match interrupt (SAM bit = 1 in I2CISTAT Regis-
ter). The I2C Controller automatically responds during the acknowledge phase with the
value in the NAK bit of the I2CCTL Register.
General Call and STARTBYTE Address Recognition. If GCE = 1 and IRM = 0 during
the address phase and the controller is configured for Master/Slave or Slave in either 7- or
10-bit address mode, the hardware detects a match to the General Call Address or start
byte and generates the Slave Address Match interrupt. A General Call Address is a 7-bit
address of all 0’s with the R/W bit = 0. A start byte is a 7-bit address of all 0’s with the R/
W bit = 1. The SAM and GCA bits are set in the I2CISTAT Register. The RD bit in the
I2CISTAT Register distinguishes a General Call Address from a start byte (= 0 for General
Call Address). For a General Call Address, the I2C Controller automatically responds dur-
ing the address acknowledge phase with the value in the NAK bit of the I2CCTL Register.
If software processes the data bytes associated with the GCA bit, the IRM bit is optionally
set following the SAM interrupt to allow software to examine each received data byte
before deciding to set or clear the NAK bit. A start byte will not be acknowledged
(requirement the I2C specification).
Software address recognition. To disable the hardware address recognition, the IRM bit
must be set = 1 prior to the reception of the address byte(s). When IRM = 1 each received
byte generates a receive interrupt (RDRF = 1 in the I2CISTAT Register). Software must
examine each byte and determine whether to set or clear the NAK bit. The Slave holds
SCL Low during the acknowledge phase until software responds by writing to the
I2CCTL Register. The value written to the NAK bit is used by the controller to drive the
I2C Bus, then releasing the SCL. The SAM and GCA bits are not set when IRM = 1 during
the address phase, but the RD bit is updated based on the first address byte.
Slave Transaction Diagrams
In the following transaction diagrams, shaded regions indicate data transferred from the
Master to the Slave and unshaded regions indicate data transferred from the Slave to the
Master. The transaction field labels are defined as follows:
S
Start
W
A
A
P
Write
Acknowledge
Not Acknowledge
Stop
Slave Receive Transaction with 7-Bit Address
The data transfer format for writing data from Master to Slave in 7-bit address mode is
shown in Figure 38. The following procedure describes the I2C Master/Slave Controller
operating as a Slave in 7-bit addressing mode, receiving data from the bus Master.
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S
Slave Address
W=0
A
Data
A
Data
A
Data
A/A
P/S
Figure 38. Data Transfer Format: Slave Receive Transaction with 7-Bit Address
1. Software configures the controller for operation as a Slave in 7-bit addressing mode as
follows.
a. Initialize the MODE field in the I2C Mode Register for either SLAVE ONLY
Mode or MASTER/SLAVE Mode with 7-bit addressing.
b. Optionally set the GCE bit.
c. Initialize the SLA[6:0] bits in the I2C Slave Address Register.
d. Set IEN = 1 in the I2C Control Register. Set NAK = 0 in the I2C Control Register.
e. Program the Baud Rate High and Low Byte registers for the I2C baud rate.
2. The bus Master initiates a transfer, sending the address byte. The SLAVE Mode I2C
Controller recognizes its own address and detects the R/W bit = 0 (write from Master
to Slave). The I2C Controller acknowledges, indicating it is available to accept the
transaction.The SAM bit in the I2CISTAT Register is set = 1, causing an interrupt. The
RD bit in the I2CISTAT Register is set = 0, indicating a write to the Slave. The I2C
Controller holds the SCL signal Low, waiting for software to load the first data byte.
3. Software responds to the interrupt by reading the I2CISTAT Register (which clears the
SAM bit). After verifying that the SAM bit = 1, software checks the RD bit. When RD
= 0, no immediate action is required until the first byte of data is received. If software
is only able to accept a single byte it sets the NAK bit in the I2CCTL Register at this
time.
4. The Master detects the acknowledge and sends the byte of data.
5. The I2C controller receives the data byte and responds with Acknowledge or Not
Acknowledge depending on the state of the NAK bit in the I2CCTL Register. The I2C
controller generates the receive data interrupt by setting the RDRF bit in the
I2CISTAT Register.
6. Software responds by reading the I2CISTAT Register, finding the RDRF bit=1 and
reading the I2CDATA Register clearing the RDRF bit. If software accepts only one
more data byte, it sets the NAK bit in the I2CCTL Register.
7. The Master and Slave loop on steps 4–6 until the Master detects a Not Acknowledge
instruction or runs out of data to send.
8. The Master sends the STOP or RESTART signal on the bus. Either of these signals
cause the I2C Controller to assert the Stop interrupt (stop bit = 1 in the I2CISTAT
Register). When the Slave receive data from the Master, software takes no action in
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response to the Stop interrupt other than reading the I2CISTAT Register, clearing the
stop bit in the I2CISTAT Register.
Slave Receive Transaction with 10-Bit Address
The data transfer format for writing data from Master to Slave with 10-bit addressing is
shown in Figure 39. The following procedure describes the I2C Master/Slave Controller
operating as a Slave in 10-bit addressing mode, receiving data from the bus Master.
Slave Address
1st Byte
Slave Address
2nd Byte
S
W=0
A
A
Data
A
Data
A/A
P/S
Figure 39. Data Transfer Format: Slave Receive Transaction with 10-Bit Address
1. Software configures the controller for operation as a Slave in 10-bit addressing mode
as follows.
–
Initialize the MODE field in the I2CMODE Register for either SLAVE ONLY
Mode or MASTER/SLAVE Mode with 10-bit addressing
–
–
Optionally set the GCE bit
Initialize the SLA[7:0] bits in the I2CSLVAD Register and the SLA[9:8] bits in
the I2CMODE Register
–
–
Set IEN = 1 in the I2CCTL Register. Set NAK = 0 in the I2C Control Register
Program the Baud Rate High and Low Byte registers for the I2C baud rate
2. The Master initiates a transfer by sending the first address byte. The I2C Controller
recognizes the start of a 10-bit address with a match to SLA[9:8] and detects the R/W
bit = 0 (write from Master to Slave). The I2C Controller acknowledges, indicating that
it is available to accept the transaction.
3. The Master sends the second address byte. The SLAVE Mode I2C Controller detects
an address match between the second address byte and SLA[7:0]. The SAM bit in the
I2CISTAT Register is set = 1, causing an interrupt. The RD bit is set = 0, indicating a
write to the Slave. The I2C Controller Acknowledges, indicating it is available to
accept the data.
4. Software responds to the interrupt by reading the I2CISTAT Register, which clears the
SAM bit. When RD = 0, no immediate action is taken by software until the first byte
of data is received. If software is only able to accept a single byte it sets the NAK bit
in the I2CCTL Register.
5. The Master detects the Acknowledge and sends the first byte of data.
6. The I2C controller receives the first byte and responds with Acknowledge or Not
Acknowledge, depending on the state of the NAK bit in the I2CCTL Register. The I2C
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controller generates the receive data interrupt by setting the RDRF bit in the
I2CISTAT Register.
7. Software responds by reading the I2CISTAT Register, finding the RDRF bit = 1, then
reading the I2CDATA Register, which clears the RDRF bit. If software accepts only
one more data byte, it sets the NAK bit in the I2CCTL Register.
8. The Master and Slave loops on steps 5–7 until the Master detects a Not Acknowledge
instruction or runs out of data to send.
9. The Master sends the STOP or RESTART signal on the bus. Either of these signals
cause the I2C Controller to assert the Stop interrupt (stop bit = 1 in the I2CISTAT
Register). When the Slave receive data from the Master, software takes no action in
response to the Stop interrupt other than reading the I2CISTAT Register, clearing the
stop bit.
Slave Transmit Transaction with 7-Bit Address
The data transfer format for a Master reading data from a Slave in 7-bit address mode is
shown in Figure 40. The following procedure describes the I2C Master/Slave Controller
operating as a Slave in 7-bit addressing mode, transmitting data to the bus Master.
Slave
Address
S
R=1
A
Data
A
Data
A
P/S
Figure 40. Data Transfer Format: Slave Transmit Transaction with 7-Bit Address
1. Software configures the controller for operation as a Slave in 7-bit addressing mode as
follows.
a. Initialize the MODE field in the I2C Mode Register for either SLAVE ONLY
Mode or MASTER/SLAVE Mode with 7-bit addressing.
b. Optionally set the GCE bit.
c. Initialize the SLA[6:0] bits in the I2C Slave Address Register.
d. Set IEN = 1 in the I2C Control Register. Set NAK = 0 in the I2C Control Register.
e. Program the Baud Rate High and Low Byte registers for the I2C baud rate.
2. The Master initiates a transfer, sending the address byte. The SLAVE Mode I2C
Controller finds an address match and detects the R/W bit = 1 (read by Master from
Slave). The I2C Controller acknowledges, indicating that it is ready to accept the
transaction.The SAM bit in the I2CISTAT Register is set = 1, causing an interrupt. The
RD bit is set = 1, indicating a read from the Slave.
3. Software responds to the interrupt by reading the I2CISTAT Register, clearing the
SAM bit. When RD = 1, software responds by loading the first data byte into the
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I2CDATA Register. Software sets the TXI bit in the I2CCTL Register to enable
transmit interrupts. When the Master initiates the data transfer, the I2C Controller
holds SCL Low until software has written the first data byte to the I2CDATA Register.
4. SCL is released and the first data byte is shifted out.
5. When the first bit of the first data byte is transferred, the I2C controller sets the TDRE
bit, which asserts the transmit data interrupt.
6. Software responds to the transmit data interrupt (TDRE = 1) by loading the next data
byte into the I2CDATA Register, which clears TDRE.
7. When the Master receives the data byte, the Master transmits an Acknowledge
instruction (or Not Acknowledge instruction for the final data byte).
8. The bus cycles through steps 5–7 until the final byte has been transferred. If software
has not yet loaded the next data byte when the Master brings SCL Low to transfer the
most significant data bit, the Slave I2C Controller holds SCL Low until the data
register is written.
When the Slave receives a Not Acknowledge instruction, the I2C Controller sets the
NCKI bit in the I2CISTAT Register and generates the Not Acknowledge interrupt.
9. Software responds to the Not Acknowledge interrupt by clearing the TXI bit in the
I2CCTL Register and by asserting the FLUSH bit of the I2CCTL Register to empty
the data register.
10. When the Master completes the final acknowledge cycle, it asserts the STOP or
RESTART condition on the bus.
11. The Slave I2C Controller asserts the STOP/RESTART interrupt (set SPRS bit in
I2CISTAT Register).
12. Software responds to the STOP/RESTART interrupt by reading the I2CISTAT
Register which clears the SPRS bit.
Slave Transmit (Master Read) Transaction with 10-Bit Address
Figure 41 displays the data transfer format for a Master reading data from a Slave with 10-
bit addressing.
Slave Address
1st Byte
Slave Address
2nd Byte
Slave Address
1st Byte
S
W=0 A
A S
R=1
A
Data
A
Data A P
Figure 41. Data Transfer Format: Slave Transmit Transaction with 10-Bit Address
The following procedure describes the I2C Master/Slave Controller operating as a Slave in
10-bit addressing mode, transmitting data to the bus Master:
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1. Software configures the controller for operation as a Slave in 10-bit addressing mode.
a. Initialize the MODE field in the I2C Mode Register for either SLAVE ONLY
Mode or MASTER/SLAVE Mode with 10-bit addressing.
b. Optionally set the GCE bit.
c. Initialize the SLA[7:0] bits in the I2CSLVAD Register and SLA[9:8] in the
I2CMODE Register.
d. Set IEN = 1, NAK = 0 in the I2C Control Register.
e. Program the Baud Rate High and Low Byte registers for the I2C baud rate.
2. The Master initiates a transfer, sending the first address byte. The SLAVE Mode I2C
Controller recognizes the start of a 10-bit address with a match to SLA[9:8] and
detects the R/W bit = 0 (write from Master to Slave). The I2C Controller
acknowledges, indicating that it is available to accept the transaction.
3. The Master sends the second address byte. The SLAVE Mode I2C Controller
compares the second address byte with the value in SLA[7:0]. If there is a match, the
SAM bit in the I2CISTAT Register is set = 1, causing a Slave Address Match
interrupt. The RD bit is set = 0, indicating a write to the Slave. If a match occurs, the
I2C Controller acknowledges on the I2C bus, indicating that it is available to accept
the data.
4. Software responds to the Slave Address Match interrupt by reading the I2CISTAT
Register which clears the SAM bit. When the RD bit = 0, no further action is required.
5. The Master notifies the Acknowledge and sends a Restart instruction, followed by the
2
first address byte with the R/W = 1. The SLAVE Mode I C Controller recognizes the
Restart followed by the first address byte with a match to SLA[9:8] and detects the R/
2
W = 1 (Master reads from Slave). The Slave I C Controller sets the SAM bit in the
I2CISTAT Register, which causes the Slave Address Match interrupt. The RD bit is set
2
= 1. The SLAVE Mode I C Controller acknowledges on the bus.
6. Software responds to the interrupt by reading the I2CISTAT Register, clearing the
SAM bit. Software loads the initial data byte into the I2CDATA Register and sets the
TXI bit in the I2CCTL Register.
7. The Master starts the data transfer by asserting SCL Low. After the I2C Controller has
data available to transmit the SCL is released and the Master proceeds to shift the first
data byte.
8. When the first bit of the first data byte is transferred, the I2C controller sets the TDRE
bit, which asserts the transmit data interrupt.
9. Software responds to the transmit data interrupt by loading the next data byte into the
I2CDATA Register.
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10. The I2C Master shifts in the remainder of the data byte. The Master transmits the
Acknowledge (or Not Acknowledge for the final data byte).
11. The bus cycles through steps 7–10 until the final byte has been transferred. If software
has not yet loaded the next data byte when the Master brings SCL Low to transfer the
most significant data bit, the Slave I2C Controller holds SCL Low until the data
register is written.
When the Slave receives a Not Acknowledge, the I2C Controller sets the NCKI bit in
the I2CISTAT Register and generates the NAK interrupt.
12. Software responds to the NAK interrupt by clearing the TXI bit in the I2CCTL
Register and by asserting the FLUSH bit of the I2CCTL Register.
13. When the Master has completed the acknowledge cycle of the final transfer it asserts
the STOP or RESTART condition on the bus.
14. The Slave I2C Controller asserts the STOP/RESTART interrupt (set SPRS bit in
I2CISTAT Register).
15. Software responds to the Stop interrupt by reading the I2CISTAT Register, clearing
the SPRS bit.
DMA Control of I2C Transactions
The DMA engine is configured to support transmit and receive DMA requests from the
I2C Controller. The I2C data interrupt requests must be disabled by setting the DMAIF bit
in the I2C Mode Register and clearing the TXI bit in the I2C Control Register. This allows
error condition interrupts to be handled by software while data movement is handled by
the DMA engine.
The DMA interface on the I2C Controller is intended to support data transfer but not
MASTER Mode address byte transfer. The start, stop and NAK bits must be controlled by
software.
A summary of the I2C transfer of data using the DMA follows.
Master Write Transaction with Data DMA
•
•
•
Configure the selected DMA channel for I2C transmit. The IEOB bit must be set in the
DMACTL Register for the final buffer to be transferred.
The I2C interrupt must be enabled in the interrupt controller to alert software of any I2C
error conditions. A Not Acknowledge interrupt occurs on the final byte transferred.
The I2C Master/Slave must be configured as defined in the sections above describing
MASTER Mode transactions. The TXI bit in the I2CCTL Register must be cleared.
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•
Initiate the I2C transaction as described in the Master Address Only Transactions sec-
tion on page 187, using the ACKV and ACK bits in the I2CSTATE Register to deter-
mine if the slave acknowledges.
•
•
•
Set the DMAIF bit in the I2CMODE Register.
The DMA transfers the data, which is to be transmitted to the slave.
When the DMA interrupt occurs, poll the I2CSTAT Register until the TDRE bit = 1.
This ensures that the I2C Master/Slave hardware has commenced transmitting the final
byte written by the DMA.
•
•
Set the stop bit in the I2CCTL Register. The stop bit is polled by software to determine
when the transaction is actually completed.
Clear the DMAIF bit in the I2CMODE Register.
The following procedure describes the I2C Master/Slave Controller operating as a Slave in
10-bit addressing mode, transmitting data to the bus Master.
Note: If the slave sends a Not Acknowledge prior to the final byte, a Not Acknowledge interrupt
occurs. Software must respond to this interrupt by clearing the DMAIF bit and setting the
stop bit to end the transaction.
Master Read Transaction with Data DMA
In master read transactions, the Master is responsible for the Acknowledge for each data
byte transferred. The Master software must set the NAK bit after the next to the final data
byte has been received or while the final byte is being received. The DMA supports this by
setting the DMA watermark to 0x01, which results in a DMA interrupt when the next to
the final byte has been received. A DMA interrupt also occurs when the final byte is
received. Otherwise, the sequence is similar to that described above for the Master write
transaction.
•
Configure the selected DMA channel for I2C receive. The IEOB bit must be set in the
DMACTL Register for the final buffer to be transferred. Typically one buffer is defined
with a transfer length of N where N bytes are expected to be read from the slave. The
watermark is set to 1 by writing a 0x01 to DMAxLAR[23:16].
•
•
•
The I2C interrupt must be enabled in the interrupt controller to alert software of any I2C
error conditions. A Not Acknowledge interrupt occurs on the final byte transferred.
The I2C Master/Slave must be configured as defined in the sections above describing
MASTER Mode transactions. The TXI bit in the I2CCTL Register must be cleared.
Initiate the I2C transaction as described in the Master Address Only Transactions sec-
tion on page 187, using the ACKV and ACK bits in the I2CSTATE Register to deter-
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mine if the slave acknowledges. Do not set the stop bit unless ACKV = 1 and ACK =
0 (slave did not acknowledge).
•
•
•
Set the DMAIF bit in the I2CMODE Register.
The DMA transfers the data to memory as it is received from the slave.
When the first DMA interrupt occurs indicating the (N–1)st byte has been received, the
NAK bit must be set in the I2CCTL Register.
•
•
When the second DMA interrupt occurs, it indicates that the Nth byte has been re-
ceived. Set the stop bit in the I2CCTL Register. The stop bit is polled by software to
determine when the transaction is actually completed.
Clear the DMAIF bit in the I2CMODE Register.
Slave Write Transaction with Data DMA
In a transaction where the I2C Master/Slave operates as a slave receiving data written by a
master, the software must set the NAK bit after the N–1st byte has been received or during
the reception of the final byte. As in the Master Read transaction described above, the
watermark DMA interrupt is used to notify software when the N–1st byte has been
received.
•
Configure the selected DMA channel for I2C receive. The IEOB bit must be set in the
DMACTL Register for the final buffer to be transferred. Typically one buffer will be
defined with a transfer length of N where N bytes are expected to be received from the
master. The watermark is set to 1 by writing a 0x01to DMAxLAR[23:16].
•
•
The I2C interrupt must be enabled in the interrupt controller to alert software of any I2C
error conditions.
The I2C Master/Slave must be configured as defined in the sections above describing
SLAVE Mode transactions. The TXI bit in the I2CCTL Register must be cleared.
•
•
•
When the SAM interrupt occurs, set the DMAIF bit in the I2CMODE Register.
The DMA transfers the data to memory as it is received from the master.
When the first DMA interrupt occurs indicating that the (N–1)st byte is received, the
NAK bit must be set in the I2CCTL Register.
•
•
When the second DMA interrupt occurs, it indicates that the Nth byte is received. A
Stop I2C interrupt occurs (SPRS bit set in the I2CSTAT Register) when the master is-
sues the STOP (or RESTART) condition.
Clear the DMAIF bit in the I2CMODE Register.
Slave Read Transaction with Data DMA
In this transaction the I2C Master/Slave operates as a slave, sending data to the master.
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•
Configure the selected DMA channel for I2C transmit. The IEOB bit must be set in the
DMACTL Register for the final buffer to be transferred. Typically a single buffer with
a transfer length of N is defined.
•
•
The I2C interrupt must be enabled in the interrupt controller to alert software of any I2C
error conditions. A Not Acknowledge interrupt occurs on the final byte transferred.
The I2C Master/Slave must be configured as defined in the sections above describing
SLAVE Mode transactions. The TXI bit in the I2CCTL Register must be cleared.
•
•
•
When the SAM interrupt occurs, set the DMAIF bit in the I2CMODE Register.
The DMA transfers the data to be transmitted to the master.
When the DMA interrupt occurs, the final byte is being transferred to the master. The
master must send a Not Acknowledge for this final byte, setting the NCKI bit in the
I2CSTAT Register and generating the I2C interrupt. A Stop or Restart interrupt (SPRS
bit set in I2CSTAT Register) follows.
•
Clear the DMAIF bit in the I2CMODE Register.
Note: If the master sends a Not Acknowledge prior to the final byte, software responds to the
Not Acknowledge interrupt by clearing the DMAIF bit.
2
I C Control Register Definitions
The following section describes the I2C Control registers.
I2C Data Register
The I2C Data Register, shown in Table 103, holds the data that is to be loaded into the
Shift Register to transmit onto the I2C bus. This register also holds data that is loaded from
the Shift Register after it is received from the I2C bus. The I2C Shift Register is not acces-
sible in the Register File address space, but is used only to buffer incoming and outgoing
data.
Writes by software to the I2CDATA Register are blocked if a slave write transaction is
underway (I2C Controller in SLAVE Mode, data being received).
2
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2
Table 103. I C Data Register (I2CDATA)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DATA
0
R/W
ADDR
FF_E240h
I2C Interrupt Status Register
The read-only I2C Interrupt Status Register, shown in Table 104, indicates the cause of
any current I2C interrupt and provides status of the I2C Controller. When an interrupt
occurs, one or more of the TDRE, RDRF, SAM, ARBLST, SPRS or NCKI bits is set. The
GCA and RD bits do not generate an interrupt but rather provide status associated with the
SAM bit interrupt.
2
Table 104. I C Interrupt Status Register (I2CISTAT)
Bit
7
TDRE
1
6
RDRF
0
5
SAM
0
4
GCA
0
3
RD
0
2
1
SPRS
0
0
NCKI
0
Field
RESET
R/W
ARBLST
0
R
R
R
R
R
R
R
R
ADDR
FF_E241h
Bit
Description
[7]
TDRE
Transmit Data Register Empty
2
2
When the I C Controller is enabled, this bit is 1 if the I C Data Register is empty. When set, the
2
2
I C Controller generates an interrupt, except when the I C Controller is shifting in data during
the reception of a byte or when shifting an address and the RD bit is set. This bit clears by writ-
ing to the I2CDATA Register.
[6]
RDRF
Receive Data Register Full
This bit is set = 1 when the I C Controller is enabled and the I C Controller has received a byte
of data. When asserted, this bit causes the I C Controller to generate an interrupt. This bit
2
2
2
clears by reading the I2CDATA Register.
[5]
SAM
Slave Address Match
2
This bit is set = 1 if the I C Controller is enabled in SLAVE Mode and an address is received
which matches the unique slave address or General Call Address (if enabled by the GCE bit in
2
the I C Mode Register). In 10-bit addressing mode, this bit is not set until a match is achieved
on both address bytes. When this bit is set, the RD and GCA bits are also valid. This bit clears
by reading the I2CISTAT Register.
2
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Bit
Description (Continued)
[4]
GCA
General Call Address
This bit is set in SLAVE Mode when the General Call Address or start byte is recognized (in
either 7- or 10-bit SLAVE Mode). The GCE bit in the I C Mode Register must be set to enable
2
recognition of the General Call Address and start byte. This bit clears when IEN = 0 and is
updated following the first address byte of each SLAVE Mode transaction. A General Call
Address is distinguished from a start byte by the value of the RD bit (RD = 0 for General Call
Address, 1 for start byte).
[3]
RD
Read
This bit indicates the direction of transfer of the data. It is set when the Master is reading data
from the Slave. This bit matches the least-significant bit of the address byte after the start con-
dition occurs (for both Master and Slave modes). This bit clears when IEN = 0 and is updated
following the first address byte of each transaction.
[2]
Arbitration Lost
2
ARBLST This bit is set when the I C Controller is enabled in MASTER Mode and loses arbitration (out-
puts a 1 on SDA and receives a 0 on SDA). The ARBLST bit clears when the I2CISTAT Regis-
ter is read.
[1]
SPRS
Stop/Restart Condition Interrupt
This bit is set when the I C Controller is enabled in SLAVE Mode and detects a STOP or
2
RESTART condition during a transaction directed to this slave. This bit clears when the
I2CISTAT Register is read. Read the RSTR bit of the I2CSTATE Register to determine whether
the interrupt was caused by a STOP or RESTART condition.
[0]
NCKI
NAK Interrupt
In MASTER Mode, this bit is set when a Not Acknowledge condition is received or sent and
neither the start nor the stop bit is active. In MASTER Mode, this bit is cleared only by setting
the start or stop bits. In SLAVE Mode, this bit is set when a Not Acknowledge condition is
received (Master reading data from Slave), indicating the Master is finished reading. A STOP
or RESTART condition follows. In SLAVE Mode this bit clears when the I2CISTAT Register is
read.
I2C Control Register
The I2C Control Register, shown in Table 105, enables and configures the I2C operation.
2
Table 105. I C Control Register (I2CCTL)
Bit
7
IEN
0
6
START
0
5
4
BIRQ
0
3
TXI
0
2
NAK
0
1
FLUSH
0
0
FILTEN
0
Field
RESET
R/W
STOP
0
R/W
R/W1
R/W1
R/W
R/W
R/W1
R/W
R/W
ADDR
FF_E242h
Note: R/W1 = bit is set (write 1) but not cleared.
2
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Product Specification
207
Bit
Description
2
[7]
I C Enable
2
IEN
This bit enables the I C Controller.
[6]
START
Send Start Condition
2
When set, this bit causes the I C Controller (when configured as the Master) to send the start
condition. After assertion, this bit is cleared by the I C Controller after it sends the start condi-
2
tion or by deasserting the IEN bit. If this bit is 1, it cannot be cleared by writing to the bit. After
this bit is set, the start condition is sent if there is data in the I2CDATA or I2CSHIFT Register. If
2
there is no data in one of these registers, the I C Controller waits until data is loaded. If this bit
2
is set while the I C Controller is shifting out data, it generates a RESTART condition after the
byte shifts and the acknowledge phase completes. If the stop bit is also set, it also waits until
the stop condition is sent before the start condition.
If start is set while a SLAVE Mode transaction is underway to this device, the start bit is cleared
and ARBLST bit in the Interrupt Status Register will be set.
[5]
STOP
Send Stop Condition
2
When set, this bit causes the I C Controller (when configured as the Master) to send the stop
condition after the byte in the I C Shift Register has completed transmission or after a byte has
been received in a receive operation. When set, this bit is reset by the I C Controller after a
2
2
stop condition has been sent or by deasserting the IEN bit. If this bit is 1, it cannot be cleared to
0 by writing to the register. If a stop is set while a SLAVE Mode transaction is underway, the
stop bit will be cleared by hardware.
[4]
BIRQ
Baud Rate Generator Interrupt Request
2
2
This bit is ignored when the I C Controller is enabled. If this bit is set = 1 when the I C Control-
ler is disabled (IEN = 0) the baud rate generator is used as an additional timer causing an inter-
rupt to occur every time the baud rate generator counts down to one. The baud rate generator
runs continuously in this mode, generating periodic interrupts.
[3]
TXI
Enable TDRE Interrupts
This bit enables interrupts when the I C Data Register is empty.
2
[2]
NAK
Send NAK
Setting this bit sends a Not Acknowledge condition after the next byte of data has been
received. It is automatically deasserted after the Not Acknowledge is sent or the IEN bit is
cleared. If this bit is 1, it cannot be cleared to 0 by writing to the register.
[1]
FLUSH
Flush Data
2
Setting this bit clears the I C Data Register and sets the TDRE bit to 1. This bit allows flushing
2
of the I C Data Register when an NAK condition is received after the next data byte has been
2
written to the I C Data Register. Reading this bit always returns 0.
2
[0]
I C Signal Filter Enable
FILTEN Setting this bit enables low-pass digital filters on the SDA and SCL input signals. This function
2
provides the spike suppression filter required in I C Fast Mode. These filters reject any input
pulse with periods less than a full system clock cycle. The filters introduce a 3-system clock
cycle latency on the inputs.
2
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Product Specification
208
I2C Baud Rate High and Low Byte Registers
The I2C Baud Rate High and Low Byte registers, shown in Tables 106 and 107, combine
to form a 16-bit reload value, BRG[15:0], for the I2C Baud Rate Generator. The Baud Rate
High and Low Byte registers must be programmed for the I2C baud rate in SLAVE Mode
as well as in MASTER Mode. In SLAVE Mode, the baud rate value programmed must
match the master's baud rate within +/- 25% for proper operation.
The I2C baud rate is calculated using the below equation.
Note: If BRG = 0000h, use 10000hin the equation.
System Clock Frequency (Hz)
------------------------------------------------------------------------
I2C Baud Rate (bps) =
4 BRG[15:0]
.
:
2
Table 106. I C Baud Rate High Byte Register (I2CBRH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
BRH
FFh
R/W
ADDR
FF_E243h
Bit
Description
2
[7:0]
I C Baud Rate High Byte
2
BRH
Most significant byte, BRG[15:8], of the I C Baud Rate Generator’s reload value.
Note: If the DIAG bit in the I<SuperscriptTableFootnote>2C Mode Register is set to 1, a read of the I2CBRH Register
returns the current value of the I<SuperscriptTableFootnote>2C Baud Rate Counter[15:8].
2
Table 107. I C Baud Rate Low Byte Register (I2CBRL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
BRL
FFh
R/W
ADDR
FF_E244h
2
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Product Specification
209
Bit
Description
2
[7:0]
I C Baud Rate Low Byte
2
BRL
Least significant byte, BRG[7:0], of the I C Baud Rate Generator’s reload value.
Note: If the DIAG bit in the I<SuperscriptTableFootnote>2C Mode Register is set to 1, a read of the I2CBRL Register
returns the current value of the I<SuperscriptTableFootnote>2C Baud Rate Counter[7:0].
I2C State Register
The read only I2C State Register provides information about the state of the I2C bus and
the I2C Bus Controller.
When the DIAG bit of the I2C Mode Register is cleared, this register provides information
about the internal state of the I2C Controller and I2C Bus as shown in Table 108.
Conversely, when the DIAG bit of the I2C Mode Register is set, this register returns the
value of the I2C Controller state machine as shown in Table 109.
2
Table 108. I C State Register (I2CSTATE), Description when DIAG = 0
Bit
7
ACKV
0
6
ACK
0
5
AS
0
4
DS
0
3
10B
0
2
RSTR
0
1
0
BUSY
X
Field
RESET
R/W
SCLOUT
X
R
R
R
R
R
R
R
R
ADDR
FF_E245h
Bit
Description
[7]
ACKV
ACK Valid
This bit is set if sending data (Master or Slave) and the ACK bit in this register is valid for the
byte just transmitted. This bit is monitored if it is appropriate for software to verify the ACK
value before writing the next byte to be sent. To operate in this mode, the data register must
not be written when TDRE asserts; instead, software waits for ACKV to assert. This bit clears
when transmission of the next byte begins or the transaction is ended by a STOP or RESTART
condition.
[6]
ACK
Acknowledge
This bit indicates the status of the Acknowledge for the final byte transmitted or received. This
bit is set for an Acknowledge and cleared for a Not Acknowledge condition.
[5]
AS
Address State
2
This bit is active High while the address is being transferred on the I C bus.
[4]
DS
Data State
2
This bit is active High while the data is being transferred on the I C bus.
2
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Bit
Description (Continued)
10B
[3]
10B
This bit indicates whether a 10- or 7-bit address is being transmitted when operating as a Mas-
ter. After the start bit is set, if the five most-significant bits of the address are 11110b, this bit is
set. When set, it is reset after the address has been sent.
[2]
RSTR
Restart
This bit is updated each time a STOP or RESTART interrupt occurs (SPRS bit set in I2CISTAT
Register).
0 = Stop condition.
1 = Restart condition.
[1]
Serial Clock Output
SCLOUT Current value of Serial Clock being output onto the bus. The actual values of the SCL and SDA
2
signals on the I C bus is observed via the GPIO Input Register.
2
[0]
I C Bus Busy
2
BUSY
0 = No activity on the I C Bus.
2
1 = A transaction is underway on the I C bus.
2
Table 109. I C State Register (I2CSTATE), Description when DIAG = 1
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
I2CSTATE_H
I2CSTATE_L
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
ADDR
FF_E245h
Bit
Description
2
[7:4]
I C State High
2
I2CSTATE_H This field defines the current state of the I C Controller. It is the most significant nibble of
the internal state machine. Table 110 defines the states for this field.
2
[3:0]
I C State Low
2
I2CSTATE_L Least significant nibble of the I C state machine.
This field defines the substates for the states defined by I2CSTATE_H. Table 111 defines
the values for this field.
Table 110. I2CSTATE_H
State Description
State Encoding State Name
2
2
0000
0001
Idle
I C bus is idle or I C Controller is disabled.
2
Slave Start
I C Controller has received a start condition.
2
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Table 110. I2CSTATE_H (Continued)
State Encoding State Name
State Description
0010
0011
Slave Bystander
Slave Wait
Address did not match; ignore remainder of transaction.
Waiting for STOP or RESTART condition after sending a Not
Acknowledge instruction.
0100
0101
0110
0111
Master Stop2
Master completing stop condition (SCL = 1, SDA = 1).
MASTER Mode sending start condition (SCL = 1, SDA = 0).
Master initiating stop condition (SCL = 1, SDA = 0).
Master Start/Restart
Master Stop1
Master Wait
Master received a Not Acknowledge instruction, waiting for
software to assert stop or start control bits.
1000
1001
1010
Slave Transmit Data
Slave Receive Data
Nine substates, one for each data bit and one for the acknowl-
edge.
Nine substates, one for each data bit and one for the acknowl-
edge.
Slave Receive Addr1 Slave Receiving first address byte (7 and 10 bit addressing)
Nine substates, one for each address bit and one for the
acknowledge.
1011
Slave Receive Addr2 Slave Receiving second address byte (10 bit addressing)
Nine substates, one for each address bit and one for the
acknowledge.
1100
1101
1110
Master Transmit Data Nine substates, one for each data bit and one for the acknowl-
edge.
Master Receive Data Nine substates, one for each data bit and one for the acknowl-
edge.
Master Transmit Addr1 Master sending first address byte (7- and 10-bit addressing)
Nine substates, one for each address bit and one for the
acknowledge.
1111
Master Transmit Addr2 Master sending second address byte (10-bit addressing)
Nine substates, one for each address bit and one for the
acknowledge.
2
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Table 111. I2CSTATE_L
State
Sub-State
I2CSTATE_H I2CSTATE_L Sub-State Name
State Description
0000–0100
0110–0111
0101
0000
0000
–
–
There are no substates for these I2CSTATE_H val-
ues.
There are no substates for these I2CSTATE_H val-
ues.
0000
0001
Master Start
Initiating a new transaction.
Master Restart
Master is ending one transaction and starting a
new one without letting the bus go nonactive.
1000–1111
0111
0110
0101
0100
0011
0010
0001
0000
1000
send/receive bit 7
send/receive bit 6
send/receive bit 5
send/receive bit 4
send/receive bit 3
send/receive bit 2
send/receive bit 1
send/receive bit 0
Sending/Receiving most significant bit.
Sending/Receiving least significant bit
Sending/Receiving Acknowledge
send/receive
Acknowledge
I2C Mode Register
The I2C Mode Register, shown in Table 112, provides control over the Master vs. Slave
operating mode, plus the slave address and diagnostic modes.
2
Table 112. I C Mode Register (I2CMODE)
Bit
7
DMAIF
0
6
5
4
3
2
1
0
DIAG
0
Field
RESET
R/W
MODE[1:0]
IRM
0
GCE
0
SLA[9:8]
0
0
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E246h
2
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Product Specification
213
Bit
Description
[7]
DMAIF
DMA Interface Mode
0 = Used when software polling or interrupts are used to move data.
1 = Used when the DMA is used to move data. The TDRE and RDRF bits in the Status Regis-
2
ter are not affected but the I C interrupt is not asserted when TDRE or RDRF are set. The
2
I C interrupt reflects only the error conditions. The assertion of TDRE causes a transmit
DMA request. The assertion of RDRF causes a receive DMA request.
2
[6:5]
Selects the I C Controller Operational Mode
MODE
00 = Master/Slave capable (supports multi-Master arbitration) with 7-bit slave address.
01 = Master/Slave capable (supports multi-Master arbitration) with 10-bit slave address.
10 = Slave Only capable with 7-bit address.
11 = Slave Only capable with 10-bit address.
[4]
IRM
Interactive Receive Mode
Valid in SLAVE Mode when software needs to interpret each received byte before acknowledg-
ing. This bit is useful for processing the data bytes following a General Call Address or if soft-
ware wants to disable hardware address recognition.
0 = Acknowledge occurs automatically and is determined by the value of the NAK bit of the
I2CCTL Register.
1 = A receive interrupt is generated for each byte received (address or data). The SCL is held
Low during the acknowledge cycle until software writes to the I2CCTL Register. The value
written to the NAK bit of the I2CCTL Register is output on SDA. This value allows software
to Acknowledge or Not Acknowledge after interpreting the associated address/data byte.
[3]
GCE
General Call Address Enable
Enables reception of messages beginning with the General Call Address or start byte.
0 = Do not accept a message with the General Call Address or start byte.
1 = Do accept a message with the General Call Address or start byte. When an address match
2
occurs, the GCA and RD bits in the I C Status Register indicates whether the address
matched the General Call Address/start byte or not. Following the General Call Address
byte, software sets the IRM bit that allows software to examine the following data byte(s)
before acknowledging.
[2:1]
Slave Address Bit 9 and 8
SLA[9:8] Initialize with the appropriate slave address value when using 10-bit Slave addressing. These
bits are ignored when using 7-bit Slave addressing.
[0]
DIAG
Diagnostic Mode
Selects read back value of the Baud Rate Reload and State registers.
0 = Reading the Baud Rate registers returns the Baud Rate Register values. Reading the State
2
Register returns I C Controller state information.
1 = Reading the Baud Rate registers returns the current value of the baud rate counter. Read-
ing the State Register returns additional state information.
I2C Slave Address Register
The I2C Slave Address Register, shown in Table 113, provides control over the lower
order address bits used in 7-bit and 10-bit slave address recognition.
2
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2
Table 113. I C Slave Address Register (I2CSLVAD)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
SLA[7:0]
00h
R/W
ADDR
FF_E247h
Bit
Description
[7:0]
Slave Address Bit 7–0
SLA[7:0] Initialize with the appropriate slave address value. When using 7-bit Slave addressing, bits in
the range SLA[9:7] are ignored.
2
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Analog Functions
Z16FMC Series devices include a 12-channel Analog-to-Digital Converter (ADC), an
operational amplifier and a comparator.
The features of the analog functions include:
•
ADC with 12 analog input sources multiplexed with General-Purpose Input/Output
(GPIO) ports
•
•
Operational amplifier with output internally connect to the ADC
Comparator with separate inputs or shared with the operational amplifier
Figure 42 shows a block diagram displaying these analog functions.
Figure 42. Analog Functions Block Diagram
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Product Specification
216
ADC Overview
Z16FMC Series devices include a 12-channel ADC. The ADC converts an analog input
signal to a 10-bit binary number. The features of the successive approximation ADC
include:
•
•
•
•
•
•
•
•
12 analog input sources multiplexed with GPIO ports
Fast conversion time (2.5µs)
Programmable timing controls
Interrupt on conversion complete
Internal voltage reference generator
Internal reference voltage available externally
Ability to supply external reference voltage
Ability to do simultaneous or independent conversions
Architecture
The architecture as illustrated in Figure 42 consists of an 12-input multiplexer, sample-
and-hold amplifier and 10-bit successive approximation ADC. The ADC digitizes the sig-
nal on selected channel and stores the digitized data in the ADC data registers. In environ-
ment with high electrical noise, an external RC filter must be added at the input pins to
reduce high frequency noise.
Operation
The ADC converts the analog input, ANAx, to a 10-bit digital representation. The equa-
tion for calculating the digital value is represented by:
ADC Output = 1024*(ANAx/VREF)
Assuming zero gain and offset errors, any voltage outside the ADC input limits of AVSS
and VREF returns all 0s or 1s, respectively.
A new conversion is initiated by either software write to the ADC Control Register’s start
bit or by PWM trigger. For detailed information about the PWM trigger, see s. Initiating a
new conversion stops any conversion currently in progress and begins a new conversion.
To avoid disrupting a conversion already in progress, the start bit is read to indicate ADC
operation status (busy or available).
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ADC Timing
Each ADC measurement consists of three phases:
1. Input sampling (programmable, minimum of 1.0µs).
2. Sample-and-hold amplifier settling (programmable, minimum of 0.5µs).
3. Conversion is 12 ADCLK cycles.
Figure 43 displays the timing of an ADC conversion.
conversion period
Start bit
set by user
cleared by BUSY
1.0µs min
sample period
Programable
settling period
SAMPLE/HOLD
Internal signal
BUSY
Internal signal
12 clock
convert period
Figure 43. ADC Timing Diagram
Figure 44 displays the timing of the conversion period showing the 10-bit progression of
the output.
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Z16FMC Series Motor Control MCUs
Product Specification
218
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
ADC Clock
BUSY
12 clocks
convert period
Figure 44. ADC Convert Timing
ADC Interrupts
The ADC generates an interrupt request when a conversion has been completed. An inter-
rupt request pending when the ADC is disabled is not automatically cleared.
ADC0 Timer0 Capture
The Timer0 count is captured for every ADC0 conversion. The information is used to
determine the zero crossing of back EMF in motor control applications. The capture of the
Timer0 count occurs when the programmed sample time is complete for every conversion
and stored in the ADC Timer Capture Register (ADCTCAP).
ADC Convert on Read
The ADC is set up to automatically convert the next channel input after reading the results
of the current conversion. The conversions continue up to the channel listed in the
ADC0MAX Register, then start over at the initial channel. The initial channel to convert is
written to the Control Register, ADC0CTL, prior to starting the convert on Read process.
After conversions have started, they continue to loop from the initial channel to Max chan-
nel until the convert on Read bit, CVTRD0, is cleared or the data is not read from the data
registers.
Reference Buffer, RBUF
The reference buffer, RBUF, supplies the reference voltage for the ADC. When enabled,
the internal voltage reference generator supplies the ADC and the voltage is available on
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Product Specification
219
the VREF pin. When RBUF is disabled, the reference voltage must be supplied externally
through the VREF pin. RBUF is controlled by the REFENbit in the ADC0 Control Register.
Internal Voltage Reference Generator
The internal voltage reference generator provides the voltage to RBUF. The internal refer-
ence voltage is 2V.
ADC Control Register Definitions
This section defines the control registers for the Analog-to-Digital Converter block.
ADC0 Control Register 0
The ADC0 Control Register initiates the A/D conversion and provides ADC0 status infor-
mation.
Table 114. ADC0 Control Register 0 (ADC0CTL)
Bit
7
6
5
REFEN
0
4
ADC0EN
0
3
2
1
0
Field
RESET
R/W
START0 CVTRD0
ANAIN0[3:0]
0
0
0
0
0
0
R/W1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E500h
Bit
Description
[7]
ADC0 Start/Busy
START0 0 = Writing to 0 has no effect. Reading a 0 indicates the ADC0 is available to begin a conver-
sion.
1 = Writing to 1 starts a conversion on ADC0. Reading a 1 indicates a conversion is currently in
progress.
[6]
Convert On Read
CVTRD0 0 = The ADC0 operates normally.
1 = If this bit is set to 1, whenever the ADC0D Register is read it increments the ANAIN field by
one and start a new conversion. The ANAIN field increments until it reaches the value set
in the ADC0MAX Register. After doing the conversion on the channel specified by the
ADC0MAX Register, the next read resets the ANAIN field to zero. This function is used with
the DMA to perform continuous conversions.
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Product Specification
220
Bit
Description (Continued)
Reference Enable
[5]
REFEN 0 = Internal reference voltage is disabled allowing an external reference voltage to be used by
the ADC0.
1 = Internal reference voltage for the ADC0 is enabled. The internal reference voltage is mea-
sured on the VREF pin.
[4]
ADC0 Enable
ADC0EN 0 = ADC0 is disabled for low power operation.
1 = ADC0 is enabled for normal use.
[3:0]
Analog Input Select
ANAIN0 0000 = ANA0 input is selected for analog-to-digital conversion.
0001 = ANA1 input is selected for analog-to-digital conversion.
0010 = ANA2 input is selected for analog-to-digital conversion.
0011 = ANA3 input is selected for analog-to-digital conversion.
0100 = ANA4 input is selected for analog-to-digital conversion.
0101 = ANA5 input is selected for analog-to-digital conversion.
0110 = ANA6 input is selected for analog-to-digital conversion.
0111 = ANA7 input is selected for analog-to-digital conversion.
1000 = ANA8 input is selected for analog-to-digital conversion.
1001 = ANA9 input is selected for analog-to-digital conversion.
1010 = ANA10 input is selected for analog-to-digital conversion.
1011 = ANA11 input is selected for analog-to-digital conversion.
1100–1111 = Reserved.
ADC0 Data High Byte Register
The ADC0 Data High Byte Register contains the upper eight bits of the ADC0 output.
Access to the ADC0 Data High Byte Register is read-only.
Table 115. ADC0 Data High Byte Register (ADC0D_H)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
ADC0D_H
X
R
ADDR
FF_E502h
Bit
Description (Continued)
ADC0 High Byte
[7:0]
ADC0D_H 00h–FFh = The final conversion output is held in the data registers until the next ADC con-
version is completed.
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221
ADC0 Data Low Bit Register
The ADC0 Data Low Bit Register contains the lower bits of the ADC0 output. Access to
the ADC0 Data Low Bit Register is read-only.
Table 116. ADC0 Data Low Bit Register (ADC0D_L)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
ADC0D_L
Reserved
X
R
X
R
ADDR
FF_E503h
Bit
Description
ADC0 Low Bit
[7:6]
ADC0D_L
00–11b = These bits are the 2 least significant bits of the 10-bit ADC0 output. These bits are
undefined after a Reset.
[5:0]
Reserved
Reserved
These bits are reserved and must be programmed to 000000.
Sample Settling Time Register
The Sample Settling Time Register is used to program the length of time from the SAM-
PLE/HOLD signal to the start signal, when the conversion begins. The number of clock
cycles required for settling varies from system to system depending on the system clock
period used. You must program this register to contain the number of clocks required to
meet a 0.5µs minimum settling time.
Table 117. Sample and Settling Time (ADCSST)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
Reserved
SST
1
0
0
0
1
1
1
1
R
R/W
ADDR
FF_E504h
Bit
Description
Reserved
[7:5]
These bits are reserved and must be programmed to 000.
[4:0]
SST
Sample Settling Time
00h–1Fh = Sample settling time in number of system clock periods to meet 0.5µs minimum.
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Sample Time Register
The Sample Time Register is used to program the length of active time for the sample after
a conversion has begun by setting the start bit in the ADC Control Register or initiated by
the PWM. The number of system clock cycles required for sample time varies from sys-
tem to system depending on the clock period used. You must program this register to con-
tain the number of system clocks required to meet a 1µs minimum sample time.
Table 118. Sample Time (ADCST)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
Reserved
ST
0
1
1
1
1
1
1
R
R/W
ADDR
FF_E505h
Bit
Description
Reserved
[7:6]
These bits are reserved and must be programmed to 00.
[5:0]
SHT
Sample Hold Time
00h–3Fh = Sample Hold time in number of system clock periods to meet 1µs minimum.
ADC Clock Prescale Register
The ADC Clock Prescale Register is used to provide a divided system clock to the ADC.
When this register is programmed with 0h, the system clock is used for the ADC Clock.
Table 119. ADC Clock Prescale Register (ADCCP)
Bit
7
6
5
4
3
DIV16
0
2
DIV8
0
1
DIV4
0
0
DIV2
0
Field
RESET
R/W
Reserved
0
R
R/W
ADDR
FF_E506h
Bit
Description
Reserved
[7:4]
These bits are reserved and must be programmed to 0000.
[3]
DIV16
DIV16
0 = Clock is not divided.
1 = System Clock is divided by 16 for ADC Clock.
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Bit
Description (Continued)
[2]
DIV8
DIV8
0 = Clock is not divided.
1 = System Clock is divided by 8 for ADC Clock.
[1]
DIV4
DIV4
0 = Clock is not divided.
1 = System Clock is divided by 4 for ADC Clock.
[0]
DIV2
DIV2
0 = Clock is not divided.
1 = System Clock is divided by 2 for ADC Clock.
ADC0 Max Register
The ADC0 Max Register determines the highest channel that the Convert on Read incre-
ments too.
Table 120. ADC0 Max Register (ADC0MAX)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
Reserved
0
LASTCHAN0
0h
R/W
ADDR
FF_E507h
Bit
Description
Reserved
[7:4]
These bits are reserved and must be programmed to 0000.
[3:0]
LAST CHANNEL0
LASTCHAN0 0 = These bits determine the final channel number to increment to when the Convert On
Read is set.
ADC Timer0 Capture Register
The ADC Timer0 Capture Register contains the sixteen bits of the ADC Timer0 count and
can read a 16-bit word or read 8 bits at a time. Access to the ADC Timer0 Capture Regis-
ter is read-only.
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Table 121. ADC Timer0 Capture Register, High Byte (ADCTCAP_H)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
ADCTCAPH
X
R
ADDR
FF_E512h
Bit
Description
ADC Timer0 Count High Byte
[7:0]
ADCTCAPH
00h–FFh = The Timer0 count is held in the data registers until the next ADC conversion is
started.
Table 122. ADC Timer0 Capture Register, Low Byte (ADCTCAP_L)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
ADCTCAPL
X
R
ADDR
FF_E513h
Bit
Description
ADC Timer0 Count Low Byte
[7:0]
ADCTCAPL
00h–FFh = The Timer0 count is held in the data registers until the next ADC conversion is
started.
Comparator and Operational Amplifier Overview
Z16FMC Series devices feature a general-purpose comparator and an operational ampli-
fier. The comparator is a moderate speed (200 ns propagation delay) device which is
designed for a maximum input offset of 5 mV. The comparator is used to compare two
analog input signals. General-purpose input pins (CINP and CINN) provides the compara-
tor inputs. The output is available as an interrupt source.
The operational amplifier is a two-input, one-output operational amplifier with a typical
open loop gain of 10,000 (80dB). The general-purpose input pin (OPINP) provides the
noninverting amplifier input, while general-purpose input pin (OPINN) provides the
inverting amplifier input. The output is available at the output pin (OPOUT).
The key operating characteristics of the operational amplifier are:
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•
•
•
•
•
•
Frequency compensated for unity gain stability
Input common-mode-range from GND (0.0 V) to VDD–1V
Input offset voltage less than 15mV
Output voltage swing from GND + 0.1 V to VDD–0.1V
Input bias current less than 1µA
Operating the operational amplifier open loop (no feedback) effectively provides
another on-chip comparator
Comparator Operation
The comparator output reflects the relationship between the noninverting input and the
inverting (reference) input. If the voltage on the noninverting input is higher than the volt-
age on the inverting input, the comparator output is at a high state. If the voltage on the
noninverting input is lower than the voltage on the inverting input, the comparator output
is at a low state.
To operate, the comparator must be enabled by setting the CMPEN bit in the Comparator
and Op-Amp Register to 1. In addition, the CINP and CINN comparator input alternate
functions must be enabled on their respective GPIO pins. For more information, see s.
The comparator does not automatically power-down. To reduce operating current when
not in use, the comparator is disabled by clearing the CMPEN bit to 0.
Operational Amplifier Operation
To operate, the operational amplifier must be enabled by setting the OPEN bit in the Com-
parator and Op-Amp Register to 1. In addition, the OPINP, OPINN and OPOUT alternate
functions must be enabled on their respective general-purpose I/O pins. For more informa-
tion, see s.
The logical value of the operational amplifier output (OPOUT) is read from the Port 3
Data Input Register if both the operational amplifier and input pin Schmitt trigger are
enabled. For more information, see s. The operational amplifier generates an interrupt via
the GPIO Port B3 input interrupt, if enabled.
The output of the operational amplifier is also connected to an analog input (ANA3) of the
ADC multiplexer.
The operational amplifier does not automatically power-down. To reduce operating cur-
rent when not in use, the operational amplifier is disabled by clearing the OPEN bit in the
Comparator and Op-Amp Register to 0.
When the operational amplifier is disabled, the output is high impedance.
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Interrupts
The comparator generates an interrupt on any change in the logic output value (from 0 to 1
and from 1 to 0). For information about enabling and prioritization of the comparator
interrupt, see the Interrupt Controller chapter on page 54.
Comparator Control Register Definitions
The following sections describe the comparator control registers.
Comparator and Operational Amplifier Control Register
The Comparator and Operational Amplifier Control Register (CMPOPC) enables the
comparator and operational amplifier and provides access to the comparator output.
Table 123. Comparator and Op Amp Control Register (CMPOPC)
Bit
7
OPEN
0
6
5
4
3
2
CMPIV
0
1
0
Field
RESET
R/W
Reserved
CPISEL CMPIRQ
CMPOUT CMPEN
00
R
0
0
X
R
0
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E510h
Bit
Description
[7]
OPEN
Operational Amplifier Disable
0 = Operational amplifier is disabled.
1 = Operational amplifier is enabled.
[6:5]
Reserved
These bits are reserved and must be programmed to 00.
[4]
Comparator Input Select
CPISEL
0 = PortB6 provides the comparator; input.
1 = PortC0 provides the comparator; input.
[3]
CMPIRQ
Comparator Interrupt Edge Select
0 = Interrupt Request on Comparator Rising Edge.
1 = Interrupt Request on Comparator Falling Edge.
[2]
CMPIV
PWM Fault Comparator Polarity
0 = PWM Fault is active when cp+ > cp-
1 = PWM Fault is active when cp- > cp+
[1]
CMPOUT
Comparator Output Value
0 = Comparator output is logical 0.
1 = Comparator output is logical 1.
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Bit
Description (Continued)
[0]
CMPEN
Comparator Enable
0 = Comparator is disabled.
1 = Comparator is enabled.
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DMA Controller
The four DMA channels are used to transfer data from memory to memory, memory to
peripherals, peripherals to memory, or peripherals to peripherals.
DMA Features
The features of DMA controller include:
•
•
Four independent DMA channels
Memory <=> memory, memory <=> peripheral, peripheral <=> memory, peripheral
<=> peripheral transfers
•
•
•
•
Direct or linked list modes of operation
Byte, word, or quad operation
DMA and CPU bandwidth sharing control
Up to 64K transfers (64KB, 64 KWord or 64 KQuad)
A block diagram of the DMA Controller is shown in Figure 45.
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Request0
Request EOF0
Acknowledge0
Interrupt0
Channel 0
Channel 1
Channel 2
Channel
MUX
Request1
Request EOF1
Acknowledge1
Interrupt1
Request2
Request EOF2
DMA
Bus
Controller
Acknowledge2
Interrupt2
Request3
Request EOF3
Channel 3
Acknowledge3
Interrupt3
(Internal Only)
CMDVLD
EOFSYNC
RDSTAT
CMDBUS
STATBUS
Memory Bus
Figure 45. DMA Block Diagram
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DMA Description
The DMA is used to off load the processor from doing repetitive tasks. DMA transfers
data from one memory address to another memory address. Because all peripherals are
mapped in memory, the DMA transfers data to or from peripherals.
The DMA transfers data from the source address to the destination address. This requires a
read and/or write cycle that is generated by the DMA controller. Each DMA transfer
requires a minimum of two system clock cycles to execute.
The DMA operates in DIRECT or LINKED LIST Mode. DIRECT Mode and LINKED
LIST Mode are almost identical. In DIRECT Mode, the software loads the DMA channel
registers directly. In LINKED LIST Mode, the DMA loads its registers from memory.
DMA Register Description
Each DMA channel consists of 16-bit control register, a 16-bit transfer length register, a
24-bit destination address register, a 24-bit source address register and a 24-bit list address
register, shown in Figure 46.
DMA Control (DMACTL)
Transfer Length (TXLN)
Destination Address (DAR)
Source Address (SAR)
List Address (LAR)
Figure 46. DMA Channel Registers
Buffers
A buffer is an allocation of contiguous memory bytes. Buffers are allocated by software to
be used by the DMA. The DMA transfers data to or from buffers. A typical application
would be to send data to serial channels such as I2C, UART and SPI. The data to be sent is
placed in a buffer by software.
Frames
A frame is a single buffer or a collection of buffers. Frame boundaries spans multiple buf-
fers.
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Source Address Register
The Source Address Register (SAR) points to the data to be transferred. Each time a trans-
fer occurs the SAR is selected to stay fixed or increment/decrement by the size of the
transfer (example 1, 2, 4). If we were sending data to a serial channel, the SAR points to
the data to be transferred and the SAR would be set to increment or decrement depending
on the order of data in the buffer (ascending or desending).
Destination Address Register
The Destination Address Register (DAR) points to the location to store the data trans-
ferred from the address pointed to by the SAR. Each time a transfer occurs the DAR is
selected to stay fixed or increment/decrement by the size of the transfer (for example, 1, 2
and 4). When sending data to a serial channel, the DAR points to the data register of the
serial channel and is set to a fixed address. Each transfer is then sent to the serial channel
data register because the DAR would not change.
Transfer Length
The Transfer Length Register (TXLN) is used to specify how many transfers need to occur
to transfer this buffer. If we were sending bytes to a serial channel, the value of the number
of bytes in the buffer pointed to by the SAR would be placed in this register. Each time a
transfer takes place this register is decremented by one. When the transfer length decre-
ments to zero, the buffer is complete and the DMA either stops or loads new control infor-
mation and addresses.
List Address Register
The List Address Register (LAR) is only used for LINKED LIST Mode. The LAR points
to a list of descriptors (described below). This descriptor list contains set-up information
for each buffer that the DMA will transfer. Linked-list DMAs reduce the amount of over-
head on the CPU to service the DMA.
Descriptor
A Descriptor is a 16-byte field in the memory space. It must be aligned on 16-byte bound-
aries (i.e., the lower 4 bits of the address is 0). Table 124 provides the descriptor format.
Table 124. Linked List Descriptor
Address
Even
LAR
CONTROL
TXLN
LAR + 02h
LAR + 04h
LAR + 08h
LAR + 0Ch
DAR High
SAR High
LAR High
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DMA Control Bit Definitions
The following paragraphs explain the control bits of each DMA channel.
DMAxEN
This bit if set by the CPU enables the DMA channel for direct operation. Direct operation
uses the addresses and transfer length, which has been directly written to the DMA Chan-
nel by software.
If this bit is set by a descriptor read, then LINKED LIST Mode is enabled. Linked list
operation starts when an address is written to the DMAxLAR. This write causes the DMA
to read in the descriptor control value and addresses and place them in the DMA Channel.
LOOP
If the DMA is in LINKED LIST Mode and this bit is set to 1, it prevents the DMA from
updating the descriptor when the buffer is closed. This bit is set to allow lists to loop on
themselves without software intervention.
TXSIZE
The TXSIZE bits sets the width of the transfer.
00 = 8-bit bytes are transferred on each DMA transfer. The destination and source
addresses increment or decrement by one for each transfers if the DSTCTL and/or SRC-
CTL is selected for increment or decrement. The transfer length is decremented by one,
allowing 64KB to be transferred.
01 = A 16-bit word is transferred on each DMA transfer. The destination and source
addresses increment or decrement by two if the DSTCTL and/or SRCCTL is selected
for increment or decrement. In word mode the transfer length is still decremented by
one. This allows 64 Kwords to be transferred.
10 = A 32-bit quad is transferred on each DMA transfer. The destination and source
addresses increment or decrement by four if the DSTCTL and/or SRCCTL is
selected for increment or decrement. In quad mode, the transfer length is still decre-
mented by one. This allows 64 Kquads to be transferred.
DSTCTL and SRCCTL Fields
The DSTCTL and SRCCTL fields control the increment or decrement of the source and
destination addresses. The address is set to increment, decrement or not change on each
DMA transfer.
00 = Fixed
01 = Increment
10 = Decrement
11 = Reserved
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Interrupt on End Of Buffer (IEOB)
The Interrupt on end of buffer bit forces the DMA channel to generate an interrupt when
the buffer is closed. If the DMA is operating in DIRECT Mode, the TXLN decrements to
the watermark value (see the DMA Watermark section on page 233) and this bit is set,
then a interrupt is also generated.
Transfer List (TXFR)
If the DMA is operating in LINKED LIST Mode and this bit is set, the DMA uses the next
LAR address in the descriptor for the next descriptor address instead of incrementing the
current DMAxLAR address by 16. This allows looping, true linked lists with buffers fol-
lowing the descriptor or just transfers to other loops.
End Of Frame (EOF)
If this bit is set, the EOF signal is sent to the peripheral on the final transfer in the buffer
(i.e., TXLN == 1). This action signals the peripheral to close the current frame; it is only
used for on-chip peripherals. This bit is also set if a peripheral requests an End Of Frame
before the buffer transfer is completed.
Halt After This Buffer (HALT)
If this bit is set, then the DMA stops after this buffer is closed. The DMAxLAR points to
the next descriptor but the descriptor will not be fetched.
Command Status (CMDSTAT)
These four bits are exported to the requesting device on the CMDBUS on the first transfer
of a new buffer. These bits are set by a software write or from the DMA reading the
descriptor. At the end of a buffer these four bits will contain status from the peripheral if
the EOF bit is set. See Zilog’s peripheral devices specifications for definitions of com-
mands and status.
DMA Watermark
When operating in DIRECT Mode, the DMAxLAR[23:16] byte is used as a watermark
interrupt. If these bits are set to any value other than 0, they are compared to the low byte
of the decremented transfer length during a transfer. If the IEOB bit is set and the upper
byte of DMAxTXLN[15:8] is zero and DMAxTXLN[7:0] == DMAxLAR[23:16], then an
interrupt is generated. This function allows the DMA channel to generate an interrupt
prior to the buffer becoming empty.
DMA Peripheral Interface signals
The DMA uses two input signals, four output signals and two 4-bit buses to communicate
with the peripherals. The input signals are Request (REQ) and Request EOF. The output
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signals are Acknowledge (ACK), Command Valid (CMDVLD), End Of Frame (EOF-
SYNC) and Read Status (RDSTAT). The two 4-bit busses are Command Bus (CMDBUS)
and Stat Bus (STATBUS).
A DMA transfer is initiated with the Request (REQ). When the DMA is servicing a
Request from a peripheral it will assert its acknowledge signal (ACK) to let the peripheral
know that a transfer is in progress. When the first byte of the transfer is written the CMD-
VLD is asserted and the command bits are placed on the CMDBUS. The peripheral needs
to latch the command from the bus when it sees this combination of signals.
If the EOF bit is set on the current buffer, and when the TXLN decrements to zero, the
EOFSYNC signal is asserted on the final data transfer to the peripheral to signal that it is
the final byte in the frame.
After receiving the EOFSYNC signal the peripheral need to assert the Request EOF signal
to the DMA to let the DMA know that the descriptor is closed. This could be immediately
or at some later time if the data transferred still needs to be processed. For peripherals,
which do not support a Request EOF, the EOFSYNC is tied to Request EOF to terminate
the transfer.
After the Request EOF is asserted the DMA closes the descriptor. The DMA asserts the
ACK and RDSTAT signal, if the descriptor EOF bit is set. The peripheral, if it has status,
places it on the STATBUS. This status is then placed in the descriptor and DMA status bits
when it is closed.
If a peripheral needs to close a descriptor because of an error or the end of a packet is
reached, then it asserts it is Request EOF. If the transfer length is not zero, then the DMA
will set the EOF bit, close the descriptor and generate an interrupt.
Buffer Closure
A DMA buffer closure is requested in two ways. The first is when the transfer length
reaches zero. The second is when the DMA receives a request End Of Frame from the
peripheral. When either of these cases occur, the DMA begins closure of the buffer.
Loop Mode Closure
If the LOOP bit is set, then the current buffer descriptor is not modified. The DMAxLAR
increments or a new LAR value is fetched from the descriptor.
EOF Closure
The DMAxEN bit is reset to 0. If the EOF bit is set, the CMDSTAT field is set with the
status data from the peripheral. If the channel is in LINKED LIST Mode, then the DMAx-
CTL word is written back to the CONTROL word of the descriptor. The DMAxLAR
increments or is loaded with new LAR data from the descriptor if the TXFR bit is set.
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Normal Closure
The DMAxEN bit is reset to 0. If the channel is in LINKED LIST Mode, then the DMAx-
CTL word is written back to the CONTROL word of the descriptor. The DMAxLAR
increments or is loaded with new LAR data from the descriptor if the TXFR bit is set.
DMA Modes
Each DMA channel operates in two modes, direct and linked list. Both modes use the
DMA channel registers. The only difference is in how they are loaded. In DIRECT Mode,
the DMA channel registers are directly loaded by software. When the transfer is complete,
the DMA stops. In LINKED LIST Mode the DMA will load its own registers from a
descriptor list which is pointed to by the DMAxLAR Register. It next loads the next
descriptor in the list and continue executing.
The descriptor Control/Status field and address bytes have the same format as the control
and address registers in the DMA.
DIRECT Mode
DIRECT Mode only uses the registers in the DMA for operation. The software writes
these register directly to set up and enable the DMA. DIRECT Mode is entered by directly
setting the DMAxEN bit in the DMAxCTL0 Register. Figure 47 displays the DMA regis-
ters and how they point to the buffers allocated in memory.
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Memory Map
Destination
Buffer
DMA Channel Registers
DMA Control (DMACTL0,1)
Transfer Length (TXLN)
Destination Address (DAR)
Source Address (SAR)
List Address (LAR)
Source
Buffer
Figure 47. Direct DMA Diagram
Direct DMA Setup and Operation
Observe the following steps to set up the DMA in DIRECT Mode:
1. Write the DMAxREQSEL to select the request source.
2. Write the DMAxDAR Register with the destination address.
3. Write the DMAxSAR Register with the source address.
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4. Write the DMAxTXLN with the transfer length.
5. Write DMAxLARU with watermark if required; otherwise write to zero.
6. Write DMAxCTL, and note that the control register and the address are directly
written with word and quad operations.
–
–
–
–
–
–
–
–
–
–
DMAxEN; set to 1
LOOP; reset to 0, not used in this mode
TXSIZE; set to the transfer size, byte, word or quad
DSTCTL; set to fixed, increment, or decrement
SRCCTL; set to fixed, increment, or decrement
IEOB; set to 1 to generate an interrupt at the end of buffer or watermark
TXFR; reset to 0, not used in this mode
EOF; set this bit to one if it is an EOF buffer
HALT; reset to 0, not used in this mode
CMDSTAT; set these bits with the command for the peripheral
7. The DMA is now set up and begins operating when it receives a request.
After the DMA is set up and a request is received the DMA does the following:
1. Generate a request to the CPU.
2. It transfers data for each request until the transfer length reaches zero or the DMA
receives a Request EOF signal.
3. When the DMA receives the Request EOF signal, or when the transfer length reaches
zero, it resets the DMAxEN bit. Next, based upon the EOF and IEOB bits, and if EOF
is set, then the DMA reads the status from the peripheral and places it in the
CMDSTAT field of the DMAxCTL Register. If the IEOB bit is set, or if the buffer
ended with a Request EOF, the DMA channel generates a request to the CPU. If EOF
is not set and IEOB is set, then the DMA channel generates a request to the CPU.
LINKED LIST Mode
LINKED LIST Mode requires the software to allocate buffers and set up a list of descrip-
tors for each buffer. After this allocation is performed, the software writes to DMAxLAR
with the address of the first descriptor. After the DMAxLAR is written, the DMA reads the
first descriptor into the DMA control and address registers with the exception of the LAR
data. It executes the transfers as specified by the descriptor data in the DMA. When the
transfers are complete, the DMA reads in the next descriptor in the list and continue exe-
cuting transfers. Figure 48 displays two descriptors and two sets of destination and source
buffers. It also displays how the descriptors are loaded into the DMA and then executed.
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Memory
Destination Pointers
Destination Buffer 0
Destination Buffer 1
Source Pointers
Source Buffer 0
Source Buffer 1
rst
1
Descriptor
Control/Status
TXLN
DAR
SAR
nd
2
Descriptor
LAR
Control/Status
TXLN
DAR
SAR
LAR
TXFR Bit Set
Figure 48. Linked List Diagram
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Linked List Setup and Operation
The software initially needs to create the descriptor lists and allocate the buffers for each
list. In addition, software needs to do the following:
1. Write the DMAxREQSEL to select the appropriate request source.
2. Set the CONTROL field in the descriptor (not the DMA) for the appropriate
operation:
–
–
–
–
–
–
–
–
–
–
DMAxEN; set to 1
LOOP; set to 1 to not have the descriptor modified
TXSIZE; set the appropriate size for byte, word or quad
DSTCTL; set this for increment, decrement, or fixed
SRCCTL; set this for increment, decrement, or fixed
IEOB; set to 1 if an interrupt must be generated when this descriptor is closed
TXFR; set this bit if the LAR is used to point to the next descriptor
EOF; if it is an End Of Frame buffer, then set this bit
HALT; if the DMA must stop at the end of this buffer, then set this bit to one
CMDSTAT; set this field with a command for the selected peripheral
3. Write the destination address to the destination field.
4. Write the source address to the source field.
5. Write the transfer length for this buffer.
6. If this descriptor has its TXFR bit set, then the LAR address to point to the next
descriptor.
7. If there are additional descriptors in the list, then set them up using the same procedure
listed above.
After the descriptor has been set up, the software must write the DMAxLAR in the appro-
priate DMA with the address of the descriptor. The DMA performs the following:
1. Generate a request to the CPU.
2. Place the DMAxLAR address on the bus and fetch the CONTROL word from the
descriptor. This word is then placed in the DMAxCTL Register of the DMA channel.
3. Fetch the Destination address from the descriptor and place it in the DMAxDAR
Register in the DMA channel.
4. Fetch the Source address from the descriptor and place it in the DMAxSAR Register
in the DMA channel.
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5. Fetch the TXLN length from the descriptor and place it in the DMAxTXLN Register
in the DMA channel.
6. After the reads have been completed, the DMA starts looking for requests and transfer
data until the transfer length reaches zero or the DMA receives a Request EOF signal.
7. When the DMA receives the Request EOF signal, it performs the following operations
based upon the LOOP and EOF bit:
–
00 = The DMA writes the descriptor Control/Status word with the DMAxEN bit
reset to 0.
–
01 = The DMA requests status from the peripheral. It then writes the descriptor
Control/Status word with the DMAxEN bit reset to 0 and the status returned from
the peripheral. The DMA then writes the TXLN length to the descriptor.
–
1X: The DMA does not modify the descriptor.
8. If the HALT bit is set the DMA closes the current buffer but does not fetch the next
descriptor.
9. After a new DMAxLAR address has been updated, the DMA goes back to step 2
above and fetches the control/status byte.
DMA Priority
The DMA priority is based upon the final channel serviced. After a channel is serviced it
becomes the lowest-priority channel. Table 125 lists the DMA priority.
Table 125. DMA Priority
Last Channel Serviced DMA Priority
DMA0
DMA1
DMA2
DMA3
DMA1 (Highest)
DMA2
DMA3
DMA0 (Lowest)
DMA2 (Highest)
DMA3
DMA0
DMA1 (Lowest)
DMA3 (Highest)
DMA0
DMA1
DMA2 (Lowest)
DMA 0 (Highest)
DMA 1
DMA 2
DMA 3 (Lowest)
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Each DMA has equal priority under this scheme.
DMA Bandwidth Selection
In the CPUCTL Register, the DMABW mode bits set the maximum bus bandwidth the
DMA is allowed; there are four modes. (For more detail, refer to the ZNEO CPU Core
User Manual (UM0188), available free for download from the Zilog website.)
Table 126 lists the DMA bandwidth selection.
Table 126. DMA Bandwidth Selection
Bit
00
01
10
11
Description
DMA uses 100% of the bandwidth
DMA is allowed one transfer for each CPU operation
DMA is allowed one transfer for every two CPU operations
DMA is allowed one transfer for every three CPU operations
DMA Interrupts
Each DMA has its own interrupt vector. For additional information about the interrupts,
see the Interrupt Controller chapter on page 54.
Interrupts occur on the following conditions:
•
•
Whenever a buffer is completed which has its IEOB set
When the upper eight bits of the transfer length equal zero and the lower eight bits of
the transfer length is equal to the DMAxLAR[23:16] and the DMA is in DIRECT Mode
•
If a buffer has been terminated by a Request EOF
DMA Request Select Register
The DMA Request Select Register, shown in Table 127, controls the states of the DMA
channel, whether LINKED LIST Mode or DIRECT Mode.
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Table 127. DMA Request Select Register (DMAxREQSEL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
CHANSTATE
REQSEL
0
0
0
0
0
0
0
0
R
R
R
R
R/W
R/W
R/W
R/W
ADDR
FFE400h, FFE401h, FFE402h, FFE403h
Note: x indicates values in the range 0–3.
Bit
Description
[7:4]
Channel State
CHANSTATE 0000 = DMA Off
0001 = DIRECT Mode, Waiting for End Of Frame signal
0010 = LINKED LIST Mode, Waiting for End Of Frame signal
0011 = Reserved
0100 = DIRECT Mode, First byte transfer, send command
0101 = LINKED LIST Mode, First byte transfer, send command
0110 = DIRECT Mode, Transfer of buffer in progress
0111 = LINKED LIST Mode, Transfer of buffer in progress
1000 = DIRECT Mode, Close Descriptor
1001 = LINKED LIST Mode, New List
1010 = LINKED LIST Mode, Close Descriptor
1011–1111 = Reserved
[3:0]
DMA 0 Request Select
DMA0, DMA1, 0000 = Continuous (i.e., Memory to Memory)
DMA2, DMA3 0001 = Timer 0
REQSEL
0010 = Timer 1
0011 = Timer 2
0100 = UART 0 RXD
0101 = UART 0 TXD
0110 = UART 1 RXD
0111 = UART 1 TXD
2
1000 = I C RX
2
1001 = I C TX
1010 = SPI RX
1011 = SPI TX
1100 = ADC0
1101 = Reserved
1110 = Reserved
1111 = Reserved
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Bit
Description (Continued)
DMA 1 Request Select
[3:0]
DMA0, DMA1, 0000 = Continuous (i.e., Memory to Memory)
DMA2, DMA3 0001 = Timer 0
REQSEL
0010 = Timer 1
(cont’d.)
0011 = Timer 2
0100 = UART 0 RXD
0101 = UART 0 TXD
0110 = UART 1 RXD
0111 = UART 1 TXD
2
1000 = I C RX
2
1001 = I C TX
1010 = SPI RX
1011 = SPI TX
1100 = ADC0
1101 = Reserved
1110 = Reserved
1111 = Reserved
DMA 2 Request Select
0000 = Continuous (i.e., Memory to Memory)
0001 = Timer 0
0010 = Timer 1
0011 = Timer 2
0100 = UART 0 RXD
0101 = UART 0 TXD
0110 = UART 1 RXD
0111 = UART 1 TXD
2
1000 = I C RX
2
1001 = I C TX
1010 = SPI RX
1011 = SPI TX
1100 = ADC0
1101 = Reserved
1110 = Reserved
1111 = Reserved
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Bit
Description (Continued)
DMA 3 Request Select
[3:0]
DMA0, DMA1, 0000 = Continuous (i.e., Memory to Memory)
DMA2, DMA3 0001 = Timer 0
REQSEL
0010 = Timer 1
(cont’d.)
0011 = Timer 2
0100 = UART 0 RXD
0101 = UART 0 TXD
0110 = UART 1 RXD
0111 = UART 1 TXD
2
1000 = I C RX
2
1001 = I C TX
1010 = SPI RX
1011 = SPI TX
1100 = ADC0
1101 = Reserved
1110 = Reserved
1111 = Reserved
DMA Control Registers
This section describes the DMA control registers.
DMA Control Register
The DMA Control Register, shown in Table 128, enables and controls DMA transfers.
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Table 128. DMA Control Register A (DMAxCTL))
Bit
15
DMAxEN
0
14
LOOP
0
13
12
11
10
9
8
Field
RESET
R/W
TXSIZE
DSTCTL
SRCCTL
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFE410h, FFE420h, FFE430h, FFE440h
Field
IEOB
0
TXFR
0
EOF
0
HALT
0
CMDSTAT
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFE411h, FFE421h, FFE431h, FFE441h
Note: x indicates values in the range 0–3.
Bit
Description
[15]
DMAxEN
DMA X Enable
If this bit is written directly, then normal mode is executed. If this bit is read in from a descrip-
tor, then LINKED LIST Mode is executed.
0 = DMA is disabled.
1 = DMA is enabled.
[14]
LOOP
LOOP Mode
0 = Descriptor is modified when the buffer is closed.
1 = Descriptor is not modified when buffer is closed.
[13:12]
TXSIZE
Transfer Size
00 = Byte
01 = Word
10 = Quad
11 = Reserved
[11:10]
DSTCTL
Destination Control Register
00 = Destination address does not change
01 = Destination address increments
10 = Destination address decrements
11 = Reserved
[9:8]
SRCCTL
Source Control Register
00 = Source address does not change
01 = Source address increments
10 = Source address decrements
11 = Reserved
[7]
IEOB
Interrupt On End Of Buffer
0 = Do not generate an interrupt when the DMA completes this buffer
1 = Generate interrupt at the end of this buffer
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Bit
Description (Continued)
[6]
TXFR
Transfer to New List Address
This bit is used only in LINKED LIST Mode.
0 = Increment DMAxLAR by 16 at the end of this buffer.
1 = Load the DMAxLAR with the new List Address value from the descriptor.
[5]
EOF
End Of Frame
0 = Not an End Of Frame buffer.
1 = This buffer is the end of the current frame.
[4]
HALT
Halt After This Buffer
This bit is used only in LINKED LIST Mode.
0 = Next descriptor is loaded.
1 = The DMA will halt at the end of this buffer.
[3:0]
Command Status Field
CMDSTAT On the first transfer of a buffer this field is placed on the CMDBUS and the CMDVALID is
asserted. If the EOF bit is set, the DMA requests a status from the peripheral and places it in
this field. In LINKED LIST Mode, this field is written back to the descriptor. The DMA does
not use this field it simply passes it on. The definitions of these bits are specified in each
peripheral.
DMA X Transfer Length Register
These two registers form a 16-bit transfer length. This register is decremented each time a
DMA transfer occurs.
Table 129. DMA X Transfer Length High Register (DMAxTXLNH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DMAxTXLNH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFE412h, FFE422h, FFE432h, FFE442h
Note: x indicates values in the range 0–3.
Table 130. DMA X Transfer Length Low Register (DMAxTXLNL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DMAxTXLNL
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFE413h, FFE423h, FFE433h, FFE443h
Note: x indicates values in the range 0–3.
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DMA Destination Address
These three register form the destination address. This address points to where the data
from the transfer will be stored.
Table 131. DMA Destination Address Register Upper (DMAxDARU)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DMAxDARU
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFE415h, FFE425h,FFE435h,FFE445
Note: x indicates values in the range 0–3.
Table 132. DMA Destination Address Register High (DMAxDARH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DMAxDARH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFE416h, FFE426h, FFE436h, FFE446h
Note: x indicates values in the range 0–3.
Table 133. DMA Destination Address Register Low (DMAxDARL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DMAxDARL
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFE417h, FFE427h, FFE437h, FFE447h
Note: x indicates values in the range 0–3.
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DMA Source Address Registers
The source address registers form a 24-bit source address. This address is used to point to
the source data for the transfer.
Table 134. DMA X Source Address Register Upper (DMAxSARU)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DMAxSARU
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFE419h, FFE429h, FFE439h, FFE449h
Note: x indicates values in the range 0–3.
Table 135. DMA X Source Address Register High (DMAxSARH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DMAxSARH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFE41Ah, FFE42Ah, FFE43Ah, FFE44Ah
Note: x indicates values in the range 0–3.
Table 136. DMA X Source Address Register Low (DMAxSARL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DMAxSARL
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFE41Bh, FFE42Bh, FFE43Bh, FFE44Bh
Note: x indicates values in the range 0–3.
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DMA List Address Register
This registers is written when the list mode for the DMA is used. This register contains the
address of the current list the DMA is operating on. Writing the DMAxLARL Register
enables the DMA for list operation.
Table 137. DMA X List Address Register Upper (DMAxLARU)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DMAxLARU
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFE41Dh, FFE42Dh, FFE43Dh, FFE44Dh
Note: x indicates values in the range 0–3.
In DIRECT Mode, this register is used to set a watermark interrupt. This interrupt occurs
when the DMATXLN[15:8] equals 0 and DMAxTXLN[7:0] equals DMAxLARU. Note
when using the watermark the DMAxLARL must not be written.
Table 138. DMA X List Address Register High (DMAxLARH)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DMAxLARH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFE41Eh, FFE42Eh, FFE43Eh, FFE44Eh
Note: x indicates values in the range 0–3.
Table 139. DMA X List Address Register Low (DMAxLARL)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
DMAxLARL
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFE41Fh, FFE42Fh, FFE43Fh, FFE44Fh
Note: x indicates values in the range 0–3.
Writing the DMAxLARL Register causes the DMA to enter LINKED LIST Mode.
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Flash Memory
The products in the Z16FMC Series MCUs feature up to 128KB of nonvolatile Flash
memory with read/write/erase capability. Flash memory is programmed and erased in-
circuit by either user code or through the OCD.
The Flash memory array is arranged in 2KB pages. The 2KB page is the minimum Flash
block size that is erased. Flash memory is also divided into eight sectors, which is pro-
tected from programming and erase operations on a per sector basis.
Table 140 describes the Flash memory configuration for each device in the Z16FMC
Series. Table 141 lists the sector address ranges. Figure 49 displays the Flash memory
arrangement.
Table 140. Flash Memory Configurations
Part
Internal
Number of Program Memory
Number of Pages per
Number
Flash Size
Pages
Addresses
000000h–01FFFFh
0000h–FFFFh
Sector Size Sectors
Sector
Z16FMC28
Z16FMC64
Z16FMC32
128KB
64KB
32KB
64
16KB
8KB
4KB
8
8
8
8
4
2
32
16
0000h–7FFFh
Table 141. Flash Memory Sector Addresses
Flash Sector Address Ranges
Sector
Number
Z16FMC28
000000h–003FFFh
Z16FMC64
Z16FMC32
0
1
2
3
4
5
6
7
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00E000h–00FFFFh
000000h–000FFFh
001000h–001FFFh
002000h–002FFFh
003000h–003FFFh
004000h–004FFFh
005000h–005FFFh
006000h–006FFFh
007000h–007FFFh
004000h–007FFFh
008000h–00BFFFh
00C000h–00FFFFh
010000h–013FFFh
014000h–017FFFh
018000h–01BFFFh
01C000h–01FFFFh
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251
128KB Flash
Program Memory
Addresses
01FFFFh
01F800h
01F7FFh
01F000h
01EFFFh
01E800h
64 Pages
2KB per Page
0017FFh
001000h
000FFFh
000800h
0007FFh
000000h
Figure 49. Flash Memory Arrangement
Information Area
Table 142 describes the Z16FMC MCU’s Information Area. This 128-byte Information
Area is accessed by setting bit 7 of the Flash Control Register to 1. When access is
enabled, the Information Area is mapped into program memory and overlays the 128 bytes
at addresses 000000hto 00007Fh. When the Information Area access is enabled, instruc-
tions access data from the Information Area. The CPU instruction fetches always come
from Main Memory regardless of the Information Area access bit. Access to the Informa-
tion Area is read-only.
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Table 142. Information Area Map
Program Memory Address (Hex)
000000h–00003Fh
Function
Reserved.
000040h–000053h
Part Number: a 20-character ASCII alphanumeric code that is left-
justified and padded with zeroes.
000054h–00007Fh
Reserved.
Operation
The Flash Controller provides the proper signals and timing for the word programming,
Page Erase and Mass erase functions within Flash memory. The Flash Controller contains
a protection mechanism, using the Flash Command Register (FCMD), to prevent acciden-
tal programming or erasure. The following subsections provide details about the various
operations (Lock, Unlock, Sector Protect, Byte Programming, Page Erase and Mass
Erase).
Timing Using the Flash Frequency Register
Before performing a program or erase operation on the Flash memory, you must first con-
figure the Flash Frequency Register. The Flash Frequency Register allows programming
and erasure of the Flash with system clock frequencies ranging from 32kHz through
20MHz (the valid range is limited to the device operating frequencies).
The 16-bit Flash Frequency Register must be written with the system clock frequency in
kHz before a program or erase operation is initiated. This value is calculated using the fol-
lowing equation:
System Clock Frequency (Hz)
-----------------------------------------------------------------
FFREQ[15:0] =
1000
Flash programming and erasure is not supported for system clock frequencies below
32kHz, above 20MHz, or outside of the device operating frequency range. The Flash
Frequency Register must be loaded with the correct value to ensure proper Flash pro-
gramming and erase operations.
Caution:
Flash Read Protection
The user code within Flash memory is protected from external access. Programming the
Flash Read Protect option bit prevents reading of user code by the OCD or by using the
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Flash Controller Bypass Mode. For more information, see the Option Bit chapter on page
260 and the On-Chip Debugger chapter on page 266.
Flash Write/Erase Protection
Z16FMC Series MCUs provide several levels of protection against accidental program and
erasure of Flash memory contents. This protection is provided by the Flash Controller unlock
mechanism, the Flash Sector Protect Register and the Flash Write Protect option bit.
Flash Controller Unlock Mechanism
At Reset, the Flash Controller locks to prevent accidental program or erasure of Flash
memory. To program or erase Flash memory, the Flash controller must be unlocked. After
unlocking the Flash Controller, the Flash is programmed or erased. Any value written by
user code to the Flash Command Register or Flash Page Select Register out of sequence
locks the Flash Controller.
Observe the following steps to unlock the Flash Controller from user code:
1. Write the page to be programmed or erased to the Flash Page Select Register.
2. Write the first unlock command 73hto the Flash Command Register.
3. Write the second unlock command 8Chto the Flash Command Register.
Flash Sector Protection
The Flash Sector Protect Register is configured to prevent sectors from being programmed
or erased. After a sector is protected, it cannot be unprotected by user code. The Flash Sec-
tor Protect Register is cleared after reset and any previously written protection values will
be lost. User code must write this register in their initialization routine if they want to
enable sector protection.
When user code writes the Flash Sector Protect Register, bits are set to 1 only. Thus, sec-
tors are protected, but not unprotected, using register write operations.
Flash Write Protection Option Bit
The Flash Write Protect option bit is enabled to block all program and erase operations
from user code. For detailed information, see the Option Bit chapter on page 260.
Programming
When the Flash Controller is unlocked, word writes to Program memory from user code
programs a word into the Flash if the address is located in the unlocked page. An erased
Flash word contains all ones (FFFFh). The programming operation is used to change bits
from one to zero. To change a Flash bit (or multiple bits) from zero to one requires a Page
Erase or Mass Erase operation.
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The Flash must be programmed one word (16 bits) at a time. If a byte (8-bit) write to Flash
memory occurs, the Flash controller waits until the other byte within the word is written
before beginning the programming operation.
While the Flash Controller programs Flash memory, Flash reads are held in wait. If the
CPU is fetching instruction from Flash, the CPU idles until the programming operation is
complete. Interrupts that occur when a programming operation is in progress are serviced
after the programming operation is complete. To exit Programming mode and lock the
Flash Controller, write 00hto the Flash Command Register.
User code cannot program Flash Memory on a page that lies in a protected sector. When
user code writes memory locations, only addresses located in the unlocked page are pro-
grammed. Memory writes outside of the unlocked page are ignored.
Each memory location must not be programmed more than twice before an erase occurs.
Caution:
Observe the following steps to program the Flash from user code:
1. Write the page of memory to be programmed to the Flash Page Select Register.
2. Write the first unlock command 73hto the Flash Command Register.
3. Write the second unlock command 8Ch to the Flash Command Register.
4. Write a word to Program memory.
5. Repeat step 4 to program additional memory locations on the same page.
6. Write 00hto the Flash Command Register to lock the Flash Controller.
Page Erase
Flash memory is erased one page (2KB) at a time. Page-erasing Flash memory sets all
words in a page to the value FFFFh. The Flash Page Select Register identifies the page to
be erased. While the Flash Controller executes the Page Erase operation, Flash reads are
held in wait. Interrupts that occur when the Page Erase operation is in progress will be ser-
viced after the Page Erase operation is complete. When the Page Erase operation is com-
plete, the Flash Controller returns to its locked state. Only pages located in unprotected
sectors are erased.
The steps to perform a Page Erase operation are:
1. Write the page to be erased to the Flash Page Select Register.
2. Write the first unlock command 73hto the Flash Command Register.
3. Write the second unlock command 8Chto the Flash Command Register.
4. Write the Page Erase command 95hto the Flash Command Register.
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Mass Erase
The Flash memory cannot be Mass Erased by user code.
Flash Controller Bypass
The Flash Controller is bypassed and the control signals for the Flash memory brought out
to the GPIO pins. Bypassing the Flash Controller allows faster Programming algorithms
by controlling the Flash programming signals directly.
Flash Controller Bypass is recommended for large volume gang programming applica-
tions, which do not require in-circuit programming of the Flash memory.
Flash Controller Behavior Using the On-Chip Debugger
The following changes in behavior of the Flash Controller occur when the Flash
Controller is accessed using the On-Chip Debugger:
•
•
•
•
The Flash Controller does not have to be unlocked for program and erase operations
The Flash Write Protect option bit is ignored
The Flash Sector Protect Register is ignored for programming and erase operations
Programming operations are not limited to the page selected in the Flash Page Select
Register
•
•
•
Bit in the Flash Sector Protect Register is written to one or zero
The Flash Page Select Register is written when the Flash Controller is unlocked
The Mass Erase command is enabled
Flash Control Register Definitions
This section defines the features of the following Flash Control registers.
Flash Command Register: see page 256
Flash Status Register: see page 256
Flash Control Register: see page 257
Flash Sector Protect Register: see page 257
Flash Page Select Register: see page 258
Flash Frequency Register: see page 259
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Flash Command Register
The Flash Command Register, shown in Table 143, unlocks the Flash Controller for pro-
gramming and erase operations. The write-only Flash Command Register shares its
address with the read-only Flash Status Register.
Table 143. Flash Command Register (FCMD)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
FCMD
XXH
W
ADDR
FF_E060h
Bit
Description
[7:0]
FCMD
Flash Command
73h = First unlock command.
8Ch = Second unlock command.
95h = Page erase command.
63h = Mass erase command.
Note: *All other commands, or any command out of sequence locks the Flash Controller.
Flash Status Register
The Flash Status Register, shown in Table 144, indicates the current state of the Flash
Controller. This register is read at any time. The read-only Flash Status Register shares its
address with the write-only Flash Command Register.
Table 144. Flash Status Register (FSTAT)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
UNLOCK Reserved
FSTAT
00h
R
0
0
R
R
ADDR
FF_E060h
Bit
Description
[7]
Unlocked
UNLOCK This status bit is set when the flash controller is unlocked.
0 = Flash Controller locked.
1 = Flash Controller unlocked.
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Z16FMC Series Motor Control MCUs
Product Specification
257
Bit
Description (Continued)
[6]
Reserved
This bit is reserved and is 0.
[5:0]
FSTAT
Flash Controller status
00_0000 = Flash Controller idle.
00_1xxx = Program operation in progress.
01_0xxx = Page erase operation in progress.
10_0xxx = Mass erase operation in progress.
Flash Control Register
The Flash Control Register selects how the Flash memory is accessed.
Table 145. Flash Control Register (FCTL)
Bit
7
INFO
0
6
5
4
3
Reserved
00h
2
1
0
Field
RESET
R/W
R/W
R
ADDR
FF_E061h
Bit
Description
[7]
INFO
Information Area Access
This bit selects access to the information area.
0 = Information Area is not selected.
1 = Information Area is selected. The Information area is mapped into the Program memory
address space at addresses 000000hthrough 00007Fh.
[6:0]
Reserved
These bits are reserved and must be written to zero.
Flash Sector Protect Register
The Flash Sector Protect Register, shown in Table 146, protects Flash memory sectors
from being programmed or erased from user code. User code can only write bits in this
register to 1 (bits cannot be cleared to 0 by user code).
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Z16FMC Series Motor Control MCUs
Product Specification
258
Table 146. Flash Sector Protect Register (FSECT)
Bit
7
SECT7
0
6
SECT6
0
5
SECT5
0
4
SECT4
0
3
SECT3
0
2
SECT2
0
1
SECT1
0
0
SECT0
0
Field
RESET
R/W
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
ADDR
FF_E062h
R/W1 = Register is accessible for Read operations. Register is written to 1 only (via user code).
Bit
Description
[7:0]
SECTn
Sector Protect
0 = Sector n is programmed or erased from user code.
1 = Sector n is protected and cannot be programmed or erased from user code.
Note: *User code write bits from 0 to 1 only.
Flash Page Select Register
The Flash Page Select (FPAGE) Register, shown in Table 147, selects one of the 64 avail-
able Flash memory pages to be erased or programmed. Each Flash Page contains 2048
words of Flash memory. During a Page Erase operation, all Flash memory locations within
the page will be erased to FFFFh.
Table 147. Flash Page Select Register (FPAGE)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
RESET
R/W
Reserved
PAGE
Reserved
00h
R
00h
0h
R
R/W
ADDR
FF_E064-FF_E065h
Bit
Description
[15:9]
Reserved
These bits are reserved and are 0.
[8:3]
PAGE
Page Select
This 6-bit field selects the Flash memory page for Programming and Page Erase operations.
Program Memory Address[16:11] = FPAGE[8:3] = PAGE[5:0].
[2:0]
Reserved
These bits are reserved and are 0.
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Z16FMC Series Motor Control MCUs
Product Specification
259
Flash Frequency Register
The Flash Frequency Register, shown in Table 148, sets the time for Flash program and
erase operations. The 16-bit Flash Frequency Register must be written with the system
clock frequency in kiloHertz. The Flash Frequency value is calculated using the following
equation:
System Clock Frequency (Hz)
-----------------------------------------------------------------
FFREQ[15:0] =
1000
Flash programming and erasure is not supported for system clock frequencies below
32kHz, above 20MHz, or outside of the valid operating frequency range for the device.
The Flash Frequency Register must be loaded with the correct value to ensure proper pro-
gram and erase times.
Caution:
Table 148. Flash Frequency Register (FFREQ)
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
FFREQ
0000h
R/W
RESET
R/W
Addr
FF_E066–FF_E067h
Bit
Description
[15:0]
Flash Frequency
FFREQ This value is used to time Flash program and erase operations.
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Z16FMC Series Motor Control MCUs
Product Specification
260
Option Bit
Option bits allow user configuration of certain aspects of the Z16FMC operation. The fea-
ture configuration data is stored in the Program memory and read during Reset. The fea-
tures available for control using the option bits are:
•
•
•
•
WDT time-out response selection – interrupt or Reset
WDT enabled at Reset
The ability to prevent unwanted read access to user code in Program memory
The ability to prevent accidental programming and erasure of the user code in Program
memory
•
•
•
Voltage Brown-Out (VBO) configuration – always enabled or disabled during STOP
Mode to reduce STOP Mode power consumption
Oscillator mode selection for high, medium and low power crystal oscillators, or exter-
nal RC oscillator
PWM pin set up for motor control application
Option Bit Configuration By Reset
Each time the option bits are programmed or erased, the device must be Reset for the
change to take place. During any reset operation (System Reset, Short Reset, or Stop-
Mode Recovery), the option bits are automatically read from the Program memory and
written to Option Configuration registers. The Option Configuration registers control
operation of the device. Option Bit control registers are loaded before the device exits
Reset and the CPU begins code execution. The Option Configuration registers are not part
of the Register file and are not accessible for read or write access.
Option Bit Address Space
The first four bytes of Program Memory at addresses 0000hthrough 0003h, shown in
Table 150, are reserved for the user option bits. These bytes are used to configure user spe-
cific options. You can change the option bits to meet the application needs.
Program Memory Address 0000h
Option bits in this space are altered to change the chip configuration at reset.
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Option Bit
Z16FMC Series Motor Control MCUs
Product Specification
261
Table 149. Option Bit At Program Memory Address 0000h
Bit
7
6
5
4
3
2
1
0
RP
U
Field
RESET
R/W
OSC_SEL[1:0]
WDT_RES WDT_AO VBO_AO DBGUART
FWP
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
Program Memory 0000h
Note: U = Unchanged by Reset; R/W = Read/Write.
Bit
Description
[7:6]
Oscillator Mode Selection
OSC_SEL 00 = On-chip oscillator configured for use with external RC networks (<4MHz).
01 = Minimum power for use with very low frequency crystals (32kHz to 1.0MHz).
10 = Medium power for use with medium frequency crystals or ceramic resonators (0.5MHz
to 10.0MHz).
11 = Maximum power for use with high frequency crystals (8.0MHz to 20.0MHz). This set-
ting is the default for unprogrammed (erased) Flash.
[5]
WDT Reset
WDT_RES 0 = WDT time-out generates an interrupt request. Interrupts must be globally enabled for the
CPU to acknowledge the interrupt request.
1 = WDT time-out causes a Short Reset. This setting is the default for unprogrammed
(erased) Flash.
[4]
WDT_AO
WDT Always On
0 = WDT is automatically enabled after reset. The WDT oscillator is disabled by clearing the
WDTEN bit in the OSCCTL Register.
1 = WDT is enabled upon execution of the WDT instruction. The WDT oscillator is disabled
by clearing the WDTEN bit in the OSCCTL Register.
[3]
VBO_AO
Voltage Brown-Out Protection Always On
0 = Voltage Brown-Out protection is disabled in STOP Mode to reduce total power con-
sumption.
1 = Voltage Brown-Out protection is always enabled, including during STOP Mode. This set-
ting is the default for unprogrammed (erased) Flash.
[2]
Debug UART Enable
DBGUART 0 = The Debug UART option is enabled.
1 = The Debug UART option is disabled.
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Option Bit Address Space
Z16FMC Series Motor Control MCUs
Product Specification
262
Bit
Description
[1]
FWP
Flash Write Protect
0 = Programming, Page Erase and Mass Erase through user code is disabled. Flash opera-
tions are allowed through the On-Chip Debugger.
1 = Programming, Page Erase and Mass Erase are enabled for all of Flash Program Mem-
ory.
[0[
RP
Read Protect
0 = User program code is inaccessible. Limited control features are available through the
OCD.
1 = User program code is accessible. All OCD commands are enabled. This setting is the
default for unprogrammed (erased) Flash.
Program Memory Address 0001h
Option bits in this space are altered to change the chip configuration at reset.
Table 150. Options Bit at Program Memory Address 0001h
Bit
7
6
5
Reserved
U
4
3
2
MCEN
U
1
PWMHI
U
0
PWMLO
U
Field
RESET
R/W
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
Program Memory 0001h
Note: U = Unchanged by Reset; R/W = Read/Write.
Bit
Description
[7:3]
Reserved
These option bits are reserved for future use and must always be programmed to 11111. This
setting is the default for unprogrammed (erased) Flash.
[2]
MCEN
Motor Control Enable
0 = Motor control pins are enabled on reset.
1 = Normal Pin operation.
[1]
High Side Off Initial Value
PWMHI 0 = The high side off value is equal to zero.
1 = The high side off value is equal to one.
[0]
Low Side Off Initial Value
PWMLO 0 = The low side off value is equal to zero.
1 = The low side off value is equal to one.
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Z16FMC Series Motor Control MCUs
Product Specification
263
Program Memory Address 0002h
Option Bit in this space are altered to change the chip configuration at reset.
Table 151. Options Bit at Program Memory Address 0002h
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
Reserved
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
Program Memory 0002h
Note: U = Unchanged by Reset; R/W = Read/Write.
Bit
Description
[7:0]
Reserved
These option bits are reserved for future use and must always programmed to 11111111. This
setting is the default for unprogrammed (erased) Flash.
Program Memory Address 0003h
Option bits in this space are altered to change the chip configuration at reset.
Table 152. Options Bit at Program Memory Address 0003h
Bit
7
Reserved
U
6
LPOPT
U
5
4
3
2
1
0
Field
RESET
R/W
Reserved
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
Program Memory 0003h
Note: U = Unchanged by Reset; R/W = Read/Write.
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 1.This setting is the default for unprogrammed
(erased) Flash.
[6]
LPOPT
Low Power Option
0 = The part will come up in low power mode. The Clock is divide by 8 and the flash will only be
accessed the second half of the final cycle of the divide. This reduces Flash power
consumption.
1 = The part will come up normally.
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Option Bit Address Space
Z16FMC Series Motor Control MCUs
Product Specification
264
Bit
Description (Continued)
[5:0]
Reserved
These option bits are reserved for future use and must always be programmed to 111111. This
setting is the default for unprogrammed (erased) Flash.
Information Area
Data in the information area of memory cannot be altered directly. If you wish to alter the
factory settings, it must be performed by writing to the Register Address identified. The
part defaults to the factory settings after reset and the registers must be rewritten to have
the user settings in effect. Read the information area address to determine the factory set-
tings.
IPO Trim Registers (Information Area Address 0021h and 0022h)
Tables 153 and 154 define the IPO Trim settings. They are altered after reset by accessing
the IPOTRIM1 and IPOTRIM2 registers.
Note: The IPO Trim table values have yet to be determined.
Table 153. IPO Trim 1 (IPOTRIM1)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
IPO TEMP TRIM
IPO TRIM
L
L
L
L
L
L
L
L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFFF_FF25h
Note: L = Loaded at Reset. R/W = Read/Write. This register is loaded from Information area on Reset.
Table 154. IPO Trim 2 (IPOTRIM2)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
IPO TRIM
L
L
L
L
L
L
L
L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFFF_FF26
Note: L = Loaded at Reset. R/W = Read/Write. This register is loaded from Information area on Reset.
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Z16FMC Series Motor Control MCUs
Product Specification
265
ADC Reference Voltage Trim (Information Area Address 0023h)
Table 155 defines the ADC Reference Voltage Trim settings. They are altered after reset
by accessing the ADCTRIM Register.
Table 155. ADC Reference Voltage Trim (ADCTRIM)
Bit
7
6
Reserved
L
5
4
3
2
1
0
Field
RESET
R/W
ADC REFERENCE TRIM
L
L
L
L
L
L
L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FFFF_FF27
Note: L = Loaded at Reset. R/W = Read/Write. This register is loaded from Information area on Reset.
Bit
Description
[7:5]
Reserved
These bits are reserved and must be programmed to 1.
[4:0]
ADCREF
ADC Reference Trim
These bits are used to trim the ADC reference voltage generator. If the part is not going to
be trimmed, the value of this register must be F0h.
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266
On-Chip Debugger
Z16FMC Series products offer an integrated On-Chip Debugger (OCD) that includes the
following features:
•
•
•
•
•
•
•
Reads/writes of memory and CPU registers
Execution of CPU instructions
In-circuit programming and erasure of Flash memory
Unlimited number of software breakpoints
Four hardware breakpoints
Instruction execution trace
Single-pin serial communication interface
Architecture
The OCD consists of two main blocks: the transmitter/receiver unit and the debug control
logic. Figure 50 displays the architecture of the OCD.
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On-Chip Debugger
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Product Specification
267
BAUD RATE
DETECTOR &
GENERATOR
TRANSMIT
& RECEIVE
CONTROLLER
RX DATA
TX DATA
SHIFTER
DBG
PIN
DEBUG
CONTROLLER
CPU
Figure 50. On-Chip Debugger Block Diagram
Operation
For effective operation of the device, all power pins (VDD and AVDD) must be
supplied with power and all ground pins (VSS and AVSS) must be properly
grounded. The DBG pin must be connected to VDD through an external pull-up
resistor to ensure proper operation.
Caution:
On-Chip Debug Enable
The DBG pin is mainly used for debugging. The OCD is always enabled by default fol-
lowing reset. Disable the OCD after startup and use the DBG pin as a UART or a GPIO
pin if the DBGUART option bit has been cleared.
To use the DBG pin as a UART or GPIO pin, the OCD must be disabled. The OCD is dis-
abled by clearing the OCDEN bit in the Debug Control Register (DBGCTL) on page 288.
The OCD cannot be disabled, if the OCDLOCK bit in the DBGCTL Register is set.
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Product Specification
268
Serial Interface
The DBG pin is used for serial communication. This one-pin interface is a bidirectional
half-duplex open-drain interface that transmits and receives data. Transmit and receive
operations cannot occur simultaneously. The serial data is sent and received using the
asynchronous protocol defined in RS–232. The serial pin is connected to the serial port of
the PC using minimal external hardware. Two different methods for connecting the serial
pin to an RS-232 interface are depicted in Figures 51 and 52 .
The serial pin is open-drain and must be connected to VDD through an external pull-up
resistor to ensure proper operation.
V
DD
RS-232
Transceiver
10 k
Ω
Diode
RS232 TX
RS232 RX
DBG pin
Figure 51. Interfacing the Serial Pin with an RS-232 Interface, #1 of 2
V
DD
RS-232
Tranceiver
Open-Drain
Buffer
10 kΩ
RS232 TX
RS232 RX
DBG pin
Figure 52. Interfacing the Serial Pin with an RS-232 Interface, #2 of 2
Serial Data Format
The data format of the serial interface uses the asynchronous protocol defined in RS-232.
Each character is transmitted as 1 start bit, 8-9 data bits (least-significant bit first) and one
stop bit, shown in Figure 53.
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Product Specification
269
ST
D0 D1 D2 D3 D4 D5 D6
D7 SP
ST = Start Bit
SP = Stop Bit
D0–D7 = Data Bit
Figure 53. OCD Serial Data Format
Each bit-time is of same length. The bit period is set by the baud rate generator.
When the transmitter sends a character, it first sends a Low start bit. The transmitter then
waits one bit-time. After the start bit is sent, the transmitter sends the next data bit. The
transmitter sends each data bit in turn, waiting one full bit-time before sending the next
data bit. After the final data bit is sent, the transmitter sends a high stop bit for one bit-
time.
The receiver looks for the falling edge of the start bit. After the receiver sees the start bit is
Low, it waits one half bit-time and samples the middle of the start bit. If the middle of the
start bit is High, the receiver considers this as a false start bit. The receiver ignores a false
start bit and searches for another falling edge. If the middle of the start bit is Low, the
receiver considers the start bit valid. The receiver will wait a full bit-time from the middle
of the start bit to sample the next data bit. The next data bit is sampled in the middle of the
bit period. The receiver repeats this operation for each data bit, waiting one full bit-time to
between sampling each data bit.
After the receiver has sampled the final data bit, it waits one full bit-time and sample the
middle of the stop bit. If the stop bit is Low, the receiver detects a framing error.
If the stop bit is High, the data was correctly framed between a start and stop bit. After the
receiver samples the middle of the stop bit, it begins searching for another start bit. The
receiver does not wait for the full stop bit to be received before searching for the next start
bit, in effect correcting for any bit skew due to error between the transmit and receive baud
rate clocks.
Baud Rate Generator
The baud rate generator (BRG) is used to generate a bit clock for transmit and receive
operations. The BRG Reload Register is automatically configured by the auto-baud
detector, or it is written by software.
The value in the BRG Reload Register is calculated as:
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Z16FMC Series Motor Control MCUs
Product Specification
270
SYSTEM CLOCK
BAUD RATE
BAUD RELOAD VALUE =
x 8
This reload value is the number of system clocks used to transmit and receive eight data
bits.
The BRG has a 16-bit reload counter and is clocked by the system clock. When the OCD
is enabled, this register is limited to 12 bits. The minimum baud rate is calculated using the
following equation:
SYSTEM CLOCK
BAUD RELOAD VALUE =
x 8
BAUD RATE
The minimum baud rate when the OCD is enabled is the system clock frequency divided
by 512. The minimum baud rate is the system clock frequency divided by 8192 when the
OCD is disabled.
For asynchronous operation, the maximum baud rate is roughly the system clock fre-
quency divided by eight (eight clocks per bit). With slow baud rates and clean signals, you
will be able to achieve asynchronous baud rates up to 4 clocks per bit. If data is synchro-
nized with the system clock, the maximum baud rate is the system clock frequency (one
bit per clock). The maximum baud rates are limited by the rise and fall times due to the
cable impedance. Table 156 lists minimum and maximum baud rates for sample crystal
frequencies.
Table 156. OCD Baud Rate Limits
System Clock
Frequency
Minimum Baud Rate
(OCDEN=0)
Minimum Baud Rate
(OCDEN=1)
Maximum Baud Rate
2.5 M baud*
20.0MHz
1.0MHz
2442 baud
123 baud
4.0 baud
39,062 baud
1953 baud
64 baud
125 k baud
32.768kHz
4096 baud
Note: * The maximum baud rate is limited by the rise and fall times due to the cable impedance.
Auto-Baud Detector
To operate using various clock frequencies over a range of baud rates, the serial interface
has an auto-baud detector. The auto-baud detector is used to automatically set up the baud
rate generator.
The auto-baud detector is set up to measure one of two different auto-baud characters, 80h
(default) or 0Dh. The default auto-baud character 80his compatible with previous Z8
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271
Encore! debug interfaces. When the OCD is disabled and the DBG pin is being used as a
UART, you can switch to an auto-baud character of 0Dh. The 0Dhcharacter is the ASCII
carriage return character and is sent using a terminal interface.
When using the auto-baud character 80h, the auto-baud detector measures the period from
the falling edge at the beginning of the start bit to the rising edge at the beginning of data
bit 7. For the auto-baud character 0Dh, the auto-baud detector measures the period from
the rising edge at the end of the start bit to the rising edge at the beginning of the stop bit.
This measured value is automatically written to the BRG Reload Register after the auto-
baud character is received. After it is configured, the BRG will generate a bit clock based
on this measured character time.
Line Control
When operating at high speeds, it is appropriate to speed up the rise and fall times of the
single wire bus. Three control bits are used to control the bus rise and fall times, the high
drive strength enable bit, the drive high enable bit and the output enable control bit.
The high drive strength enable bit puts the pin into high drive mode. For information about
high drive strength, see the Electrical Characteristics chapter on page 304.
If the output enable control bit is set, the line is driven High and Low during transmission.
If the drive high control bit is set, it drives the line high for short periods when transmit-
ting a logic one. This rapidly charges the inherent capacitance of the single wire bus.
If both the output enable and drive high control bits are set, the line is driven high for one
clock cycle when transmitting a one. If the output enable bit is clear and the drive high bit
is set, the line is driven high until the input is detected High or the center of the bit-time
occurs, whichever is first.
Logic 0
Logic 1
System Clock
Bus Voltage
Drive High
Output
Driver
High Impedance
{
Drive Low
Figure 54. Output Driver when Drive High and Open Drain Enabled
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Product Specification
272
9-Bit Mode
The serial interface is configured to transmit and receive a ninth data bit. This ninth bit is
used to transmit or receive a software generated parity bit. It is used as an address/data bit
in a multi-node system such as RS-485. See Figure 55.
ST
D0 D1 D2 D3 D4 D5 D6 D7 NB SP
ST = Start Bit
SP = Stop Bit
NB = Ninth Bit
D0-D7 = Data Bit
Figure 55. 9-Bit Mode
Start Bit Flow Control
If flow control is needed, start bit flow control is used. start bit flow control requires the
receiving device send the start bit. The transmitter waits for the start bit, then transmit its
data following the start bit. See Figure 56.
Receiving
ST
Device
Transmitting
Device
D0 D1 D2 D3 D4 D5 D6 D7 SP
Single Wire
Bus
ST
D0 D1 D2 D3 D4 D5 D6 D7 SP
ST = Start Bit
SP = Stop Bit
D0-D7 = Data Bit
Figure 56. Start Bit Flow Control
If the standard serial port of a PC is used, transmit flow control is enabled on the Z16FMC
Series device. The PC sends the start bit when receiving data by transmitting the character
FFh. Because character FFhis also received from a nonresponsive device, space parity
(parity bit always zero) must be enabled and used as an acknowledge bit.
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273
Initialization
The OCD ignores any data received until it receives the read revision command 00h. After
the read revision command is received, the remaining debug commands are issued. The
packet CRC is not sent for the first read revision command issued during initialization.
Initialization During Reset
The OCD is initialized during reset by asserting the reset pin, sending the auto-baud char-
acter and then issuing the read revision command. When the OCD is initialized during
reset, the DBGHALT bit in the OCDCTL Register is automatically set. See Figure 57.
Reset Pin
Internal
System Reset
Debug Reset
Debug Pin
80h
00h IDH IDL
Reset time-out
Reset Pin Remains Asserted
Figure 57. Initialization During Reset
Debug Lock
The interface has a locking mechanism to prevent user code from disabling the OCD and
using the DBG pin as a UART or GPIO pin. The DBGLOCK bit in the DBGCTL Register
prevents you from disabling the OCD and modifying any register that would inhibit com-
munication with the OCD. The default state of the DBGLOCK bit is set accordingly to the
DBGUART option bit.
To use the DBG pin as a UART or GPIO pin, you must program the DBGUART option bit
to zero so the OCDLOCK control bit is cleared after reset. After the control register is
unlocked, software then clears the OCDEN control bit to use the DBG pin as a UART or
GPIO pin.
If the DBGUART option bit is cleared and the OCDLOCK control bit is not set, the OCD
is still locked before the code can disable the OCD. This locking occurs upon initializing
the Debugger during reset and writing the OCDLOCK control bit to 1.
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Error Reset
The serial interface has an Auto-Reset mechanism that resets the serial interface when a
Transmit Collision or Receive Framing Error is detected. When a Transmit Collision or
Receive Framing Error is detected when OCDEN is set, the OCD aborts any command
currently in progress, transmits a Serial Break condition for 4096 system clocks and sets
the ABSRCH bit in the DBGCTL Register. This break is sent to ensure the host also
detects the error.
A clock change invalidates the baud reload value. Communication cannot continue until a
new autobaud reload value is set. As a result, the device automatically sends a serial break
to reset the communication link whenever a clock change occurs.
DEBUG HALT Mode
During debugging, it is appropriate to stop the CPU from executing instructions by plac-
ing the device into DEBUG HALT Mode. The operating characteristics of Z16FMC Series
devices when in DEBUG HALT Mode are:
•
•
•
The CPU fetch unit stops, idling the CPU
All enabled on-chip peripherals operate unless in STOP Mode
Constantly refreshes the WDT, if enabled
Entering DEBUG HALT Mode
The device enters DEBUG HALT Mode by any of the following operations:
•
•
•
Write the DBGHALT bit in the DBGCTL Register to 1 using the OCD interface
CPU execution of BRK instruction (when enabled)
Hardware breakpoint match
Exiting DEBUG HALT Mode
The device exits DEBUG HALT Mode by any of the following operations:
•
•
•
•
Clearing the DBGHALT bit in the DBGCTL Register to 0
Power-on reset
Voltage Brown-Out reset
Asserting the RESET pin Low to initiate a Reset
Reading and Writing Memory
Most debugging functions are accomplished by reading and writing control registers. The
OCD hardware is capable of reading and writing memory when the CPU is running.
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When a read or write request from the OCD hardware occurs, the OCD steals the bus for
the number of cycles needed to complete the read or write operation. This bus stealing
occurs on a per byte basis, not a per command basis. Because the debugger operates seri-
ally, it takes several clock cycles to transmit or receive a character.
If the debugger receives a command to read or write a block of memory, it will not steal
the bus for the entire read or write command. The debugger will only steal the bus for a
short period of time for each data byte. A debug write cycle will occur after a byte has
been received during a write operation. A debug read cycle will occur when the transmit-
ter is empty during a read operation.
Data read from or written to the OCD occurs one byte at a time. Therefore, memory read
and write operations occur one byte at a time. Operations that occur on multi-byte words
does not occur concurrently.
Reading Memory CRC
Because Z16FMC MCUs contain such a large memory space and the debug interface is
serial, reading massive amounts of data during debugging can be time-consuming. The
OCD hardware is capable of calculating a cyclic redundancy check (CRC) on memory to
allow memory-caching mechanisms to be used by the host debugging software. This CRC
verifies that the contents of a memory cache have not changed.
When the read CRC command is issued, the OCD hardware steals the CPU bus during the
entire Read operation. The length of time it takes to generate the CRC is equal to the
amount of time it takes to read the memory used in the CRC calculation.
The OCD hardware is also capable of returning separate CRCs for each 4K block of mem-
ory. These CRCs are used by software to determine the portions of memory which have
been modified when the cache for a large block of memory is invalidated.
Breakpoints
Software Breakpoints
Breakpoints are generated when the CPU executes the BRK instruction and breakpoints
are enabled. If breakpoints are not enabled, the BRK instruction will vector to the system
exception vector and set the illegal instruction status bit.
If a Breakpoint is generated, the OCD is configured to automatically enter DEBUG HALT
Mode or to just loop on the instruction. If the OCD is configured to loop on the instruc-
tion, the CPU is still able to service DMA and interrupt requests in the background. Soft-
ware polls the DBGBRK bit of the DBGCTL Register to determine if the OCD has
reached a Breakpoint.
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Hardware Breakpoint
There are four hardware breakpoints on the Z16FMC device. When enabled, a breakpoint
is generated when the program counter matches the value in the breakpoint register, or
when a memory access occurs at the address in the breakpoint register. A data watchpoint
watches a range of addresses by selecting how many lower address bits are ignored.
Instruction Trace
Trace Overview
The Z16FMC Series device has the ability to trace the instruction flow. If enabled, it uses
existing Memory to store the Program Counter data each time a change in execution flow
occurs. This requires you to allocate memory space to hold the trace information.
Trace Events
A trace event occurs anytime a CALL, RET, Interrupt, IRET, TRAP, JP, DJNZ, or Excep-
tion occurs. Trace takes four cycles each time a trace event occurs (five cycles for IRQ,
TRAP and Exceptions).
Trace Buffer
The Trace Buffer is controlled by two registers: Trace Control (TRACECTL) and Trace
Address (TRACEADDR) Register. The TRACECTL Register is used to enable the trace
and select the size of the Trace Buffer. TRACEADDR selects the starting address for the
trace. The trace address is modulo-n based upon the size of the TRACESEL field in the
TRACECTL Register. The modulo-n is zero aligned, which means that the trace buffer
always wraps to zero for the selected size. For example, if the TRACEADDR is set to
FFFFB050hand the TRACECTL is set to 81h, the buffer is located from FFFFB000hto
FFFFB0FFhwith the first trace event to be written to FFFFB050h. When the address
reaches FFFFB0FFhit will roll over to FFFFB000h.
Trace buffer sizes are 128, 256, 512, 1024, 2048, 4096, 8192 and 16384 bytes. Each trace
event requires eight bytes giving a minimum of 16 events to a maximum of 2048 events.
Only the Program Counter values are stored. Other information has to be inferred from the
source code by the trace debugger.
Trace Operation
On each trace event the current program counter is placed in memory pointed to by the
TRACEADDR. TRACEADDR increments by 4 and the next state of the program counter
is written to the TRACEADDR. TRACEADDR increments by 4 again. TRACEADDR
always points to the next data to be written. The lower two bits of the TRACEADDR are
always zero.
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Extracting Trace Information
The trace information is extracted by reading the data from the selected trace memory
area. The data is then interpreted by the Trace Debugger software.
On-Chip Debugger Commands
The hardware OCD supports several commands for controlling the device. In the
following list of commands, data sent from the host to the OCD is identified by:
‘DBG <-- Data’
Data sent from the OCD back to the host is identified by ‘DBG --> Data’. Multiple bytes
transmitted are represented with double arrows ‘<<‘or’>>’.
Read Revision. The Read Revision command returns the revision identifier.
DBG <-- 0000_0000
DBG --> RevID[15:8]
DBG --> RevID[7:0]
DBG --> CRC[0:7]
Read Status Register. The Read Status Register command returns the contents of the
OCDSTAT Register.
DBG <-- 0000_0001
DBG --> status[7:0]
DBG --> CRC[0:7]
Read Control Register. The Read Control Register command returns the contents of the
OCDCTL Register.
DBG <-- 0000_0010
DBG --> OCDCTL[7:0]
DBG --> CRC[0:7]
Write Control Register. The Write Control Register command writes data to the
OCDCTL Register.
DBG <-- 0000_0011
DBG <-- OCDCTL[7:0]
DBG --> CRC[0:7]
Read Registers. The Read registers command returns the contents of CPU registers R15
through R0.
DBG <-- 0000_0100
DBG ->> regdata[31:24]
DBG ->> regdata[23:16]
DBG ->> regdata[15:8]
DBG ->> regdata[7:0]
DBG --> CRC[0:7]
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Write Registers. The Write registers command writes data to CPU registers R15 through
R0.
DBG <-- 0000_0101
DBG <<- regdata[31:24]
DBG <<- regdata[23:16]
DBG <<- regdata[15:8]
DBG <<- regdata[7:0]
DBG --> CRC[0:7]
Read PC. The Read Program Counter command returns the contents of the program coun-
ter.
DBG <-- 0000_0110
DBG --> 00h
DBG --> PC[23:16]
DBG --> PC[15:8]
DBG --> PC[7:0]
DBG --> CRC[0:7]
Write PC. The Write Program Counter command writes data to the program counter.
DBG <-- 0000_0111
DBG <-- 00h
DBG <-- PC[23:16]
DBG <-- PC[15:8]
DBG <-- PC[7:0]
DBG --> CRC[0:7]
Read Flags. The Read Flags command returns the contents of the CPU flags.
DBG <-- 0000_1000
DBG --> 00h
DBG --> flags[7:0]
DBG --> CRC[0:7]
Write Instruction. The Write Instruction command writes one word of opcode to the
CPU.
DBG <-- 0000_1001
DBG <-- opcode[15:8]
DBG <-- opcode[7:0]
DBG --> CRC[0:7]
Read Register. The Read Register command returns the contents of a single CPU Regis-
ter.
DBG <-- {0100,regno[3:0]}
DBG --> regdata[31:24]
DBG --> regdata[23:16]
DBG --> regdata[15:8]
DBG --> regdata[7:0]
DBG --> CRC[0:7]
Write Register. The Write Register command writes data to a single CPU Register.
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DBG <-- {0101,regno[3:0]}
DBG <-- regdata[31:24]
DBG <-- regdata[23:16]
DBG <-- regdata[15:8]
DBG <-- regdata[7:0]
DBG --> CRC[0:7]
Read Memory. The Read memory command reads data from memory. The memory
address is sign extended.
DBG <-- {1000,Size[3:0]}
DBG <-- addr[15:8]
DBG <-- addr[7:0]
DBG ->> 1 to 16 bytes of data
DBG --> CRC[0:7]
Write Memory. The Write memory command writes data to memory. The memory
address is sign extended.
DBG <-- {1001,size[3:0}
DBG <-- addr[15:8]
DBG <-- addr[7:0]
DBG <<- 1 to 16 bytes of data
DBG --> CRC[0:7]
Read Memory. The Read memory command reads data from memory.
DBG <-- {1010,size[3:0}
DBG <-- size[11:4]
DBG <-- 00h
DBG <-- addr[23:16]
DBG <-- addr[15:8]
DBG <-- addr[7:0]
DBG ->> 1 to 4096 bytes of data
DBG --> CRC[0:7]
Write Memory. The Write memory command writes data to memory.
DBG <-- {1011,size[3:0}
DBG <-- size[11:4]
DBG <-- 00h
DBG <-- addr[23:16]
DBG <-- addr[15:8]
DBG <-- addr[7:0]
DBG <<- 1 to 4096 bytes of data
DBG --> CRC[0:7]
Read Memory CRC. The Read memory CRC command computes and return the CRC of
a block of memory.
DBG <-- {1110,BlockCount[3:0]}
DBG <-- BlockCount[11:4]
DBG <-- 00h
DBG <-- addr[23:16]
DBG <-- {addr[15:12],xxxx}
DBG --> MemoryCRC[0:7]
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DBG --> MemoryCRC[8:15]
DBG --> CRC[0:7]
The MemoryCRC is computed on memory in increments of 4K blocks. The BlockCount
field determines how many blocks of memory to compute the MemoryCRC on.
Read Each Memory CRC. The Read memory CRC command computes and return the
CRC of a block each 4K memory block.
DBG <-- {1111,BlockCount[3:0]}
DBG <-- BlockCount[11:4]
DBG <-- 00h
DBG <-- addr[23:16]
DBG <-- {addr[15:12],xxxx}
DBG ->> MemoryCRC[0:7]
DBG ->> MemoryCRC[8:15]
DBG --> CRC[0:7]
The MemoryCRC is computed on memory in increments of 4K blocks. The CRC is
returned for each 4K block and is reset at the start of each block. The BlockCount field
determines how many blocks of memory to compute the MemoryCRC on.
The On-Chip Debugger commands are summarized in Table 157.
Table 157. On-Chip Debugger Commands
Disabled by Read Protect
Debug Command
Command Byte
0000–0000
0000–0001
0000–0010
0000–0011
Option Bit
Read Revision
–
–
–
Read OCD Status Register
Read OCD Control Register
Write OCD Control Register
Cannot single step (bit0 has not
effect)
Read registers (CPU registers R15-R0)
Write registers (CPU registers R15-R0)
Read Program Counter
0000–0100
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0000–0101
0000–0110
Write Program Counter
0000–0111
Read Flags
0000–1000
Write Instruction
0000–1001
Read Register (single CPU register)
Write Register (single CPU register)
0100-(regno[3:0])
0100-(regno[3:0])
0100-(regno[3:0])
Read Memory (short -address is sign
extended)
Read only unprotected memory
locations
Note: Unlisted command byte values are reserved.
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Table 157. On-Chip Debugger Commands (Continued)
Disabled by Read Protect
Option Bit
Debug Command
Command Byte
Write Memory (short -address is sign
extended)
0100-(regno[3:0])
Write only unprotected memory
locations
Read Memory (long)
1010-size[3:0]
1011-size[3:0]
Read only unprotected memory
locations
Write Memory (long)
Write only unprotected memory
locations
Read Memory CRC
1110-BlockCount[3:0]
1111-BlockCount[3:0]
–
–
Read Each Memory CRC
Note: Unlisted command byte values are reserved.
Cyclic Redundancy Check
To ensure transmitted and received data is free of errors, the OCD transmits an 8-bit cyclic
redundancy check (CRC) at the end of each command. The CRC is enabled after the OCD
is initialized, it is not sent with the first read revision command. This CRC is disabled by
clearing the CRCEN bit of the DBGCTL Register.
The CRC is reset at the beginning of each command and is computed on the data received
from and sent to the host. The CRC is calculated using the ATM-8 HEC polynomial
8
2
1
0
x +x +x +x . The CRC is preset to all ones. Data is shifted through the polynomial LSB
first. The resulting CRC is reversed and inverted. The check value is CFh.
Memory Cyclic Redundancy Check
The read memory CRC command computes the CRC on memory in 4K blocks, up to 4K
blocks at a time (16M of data). The Memory CRC is computed using the 16-bit CCITT
16 12
5
0
polynomial x +x +x +x . The CRC is preset to all ones. Data is shifted through the
polynomial LSB first. The resulting CRC is reversed and inverted. The check value is
F0B8h.
UART Mode
When the OCD is disabled, the DBG pin is used as a single pin half-duplex UART. When
the serial interface is in UART mode, data received on the single wire bus is written to the
Receive Data Register. Data written to the Transmit Data Register is transmitted on the
single wire bus. In UART mode, the auto-baud hardware is used to configure the BRG, or
the baud rate registers are written to set a specific baud rate.
The UARTEN control bit must be set to 1 to use the serial interface as a UART. Clearing
the UARTEN control bit to zero will prevent data received on the DBG pin from being
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written to the Receive Data Register. Clearing the UARTEN control bit to zero also pre-
vents data written to the Transmit Data Register from being transmitted on the single pin
interface.
If the UART is disabled, data is still written to the Receive Data Register and read from
the Transmit Data Register. These actions still generates UART interrupts. The UARTEN
control bit only prevents data from being transmitted to or received from the DBG pin.
Serial Errors
The serial interface detects the following error conditions:
•
•
•
•
Receive framing error (received stop bit is Low)
Transmit collision (OCD releases the bus high to send a logic 1 and detects it is Low)
Receive overrun (received data before previously received data read)
Receive break detect (10 or more bits Low)
Transmission of data is prevented if the transmit collision, receive framing error, receive
break detect, receive overrun, or Receive Data Register Full status bits are set.
Interrupts
The Debug UART generates interrupts during the following conditions:
•
•
•
•
Receive Data Register is Full (includes Rx Framing Error and Rx Overrun Error)
Transmit Data Register is empty
Auto-Baud Detector loads the BRG (auto-baud character received)
Receive Break detected
DBG pin used as a GPIO pin
The DBG pin is used as a GPIO pin. The serial interface cannot be used for debugging
when the DBG pin is configured as a GPIO pin. To set up the DBG pin as a GPIO pin,
software must clear the DBGUART option bit and OCDEN control bit.
Software uses the pin as an input by clearing the output enable control bit. The PIN status
bit in the Line Control Register (DBGLCR) on page 285 reflects the state of the DBG pin.
The DBG pin is configured as an output pin by setting the output enable control bit. The
logic state of the IDLE bit in the Line Control Register (DBGLCR) on page 285 is driven
onto the DBG pin.
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Control Register Definitions
This section describes the following OCD control registers:
Receive Data Register (DBGRXD) – see page 283
Transmit Data Register (DBGTXD) – see page 284
Baud Rate Reload Register (DBGBR) – see page 284
Line Control Register (DBGLCR) – see page 285
Status Register (DBGSTAT) – see page 286
Debug Control Register (DBGCTL) – see page 288
OCD Control Register (OCDCTL) – see page 289
OCD Status Register (OCDSTAT) – see page 290
Hardware Breakpoint Register (HWBPn) – see page 291
Trace Control Register (TRACECTL) – see page 292
Trace Address (TRACEADDR) – see page 293
Receive Data Register
The Receive Data Register (DBGRXD) holds data received by the serial UART.
Table 158. Receive Data Register (DBGRXD)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
RXDATA
XX
R/W
ADDR
FF_E080
Bit
Description
[7:0]
Receive Data
RXDATA In UART Mode, data received on the serial interface is transferred from the shift register into
this register. This register is written to simulate data received if the DBG pin is being used by
the OCD.
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Transmit Data Register
The Transmit Data Register (DBGTXD) holds data to be transmitted by the serial UART.
Table 159. Transmit Data Register (DBGTXD)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
TXDATA
XX
R/W
ADDR
FF_E081
Bit
Description
[7:0]
Transmit Data
TXDATA In UART Mode, data written to this register is transmitted on the serial interface. This register is
read to simulate data transmitted if the DBG pin is being used by the OCD.
Baud Rate Reload Register
The Baud Rate Reload Register (DBGBR) is used to configure the baud rate of the serial
communication stream. This register is automatically set by the Auto-Baud Detector. This
register cannot be written by the CPU when OCDLOCK is set.
Table 160. Baud Rate Reload Register (DBGBR)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
RESET
R/W
RELOAD
0000h
R/W
ADDR
FF_E082-FF_E083
Bit
Description
[15:0]
This value is the baud rate reload value used to generate a bit clock. It is calculated as:
RELOAD
SYSTEM CLOCK
RELOAD =
x 8
BAUD RATE
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Line Control Register
The Line Control Register (DBGLCR) controls the state of the UART. This register cannot
be written by the CPU when OCDLOCK is set.
Table 161. Line Control Register (DBGLCR)
Bit
7
OE
0
6
5
4
TXFC
0
3
NBEN
0
2
NB
0
1
0
PIN
X
Field
RESET
R/W
TDH
0
HDS
0
OUT
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
ADDR
FF_E084
Bit
Description
7
OE
Output Enable
This bit controls the output driver. If the UART is enabled, this bit controls the output driver dur-
ing transmission only.
0 = Pin is open-drain during UART transmit. Pin behaves as an input if UART is disabled.
1 = Pin is driven during transmission if UART is enabled. Pin is an output if UART is disabled.
6
TDH
Transmit Drive High
This control bit causes the interface to drive the line high when a logic 1 is being transmitted. If
OE is zero, the line stops being driven when the input is high or at the center of the bit, which-
ever is first. If OE is one, the line is driven high for one clock cycle. This bit is ignored if Debug
Mode is zero and the UART is disabled.
0 = Transmit Drive High disabled.
1 = Transmit Drive High enabled.
5
HDS
High Drive Strength
This control bit enabled high drive strength for the output driver.
0 = Low Drive Strength
1 = High Drive Strength
4
TXFC
Transmitter Start Bit Flow Control
This control bit enables start bit flow control on the transmitter. The transmitter waits until a
remote device sends a start bit before transmitting its data.
0 = Transmitter start bit flow control disabled.
1 = Transmitter start bit flow control enabled.
3
NBEN
9-Bit Mode Enable
This control bit enables transmission and reception of a ninth data bit.
0 = Nine bit mode disabled.
1 = Nine bit mode enabled.
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Bit
Description (Continued)
2
NB
Ninth Bit
This bit is the value of the ninth data bit. When written, this reflects the ninth data bit that will be
transmitted if nine bit mode is enabled. When read, this bit reflects the value of the ninth bit of
the final nine-bit character received.
0 = Ninth bit is zero.
1 = Ninth bit is one.
1
OUT
Output State
This control bit sets the state of the output transceiver. If the UART is enabled, this bit must be
set to 1 to idle high. Clearing this bit to zero when the UART is enabled will transmit a break
condition. If the UART is disabled, this logic value will be driven onto the pin if OE is set. This
bit is ignored in Debug Mode.
0 = Transmit Break if UART enabled. Drive Low if UART disabled and output enabled.
1 = Idle High if UART enabled. Drive high if UART disabled and output enabled.
0
PIN
Debug Pin
This bit reflects the state of the DBG pin.
0 = DBG pin is Low.
1 = DBG pin is High.
Status Register
The Status Register (DBGSTAT), shown in Table 162, contains information about the
state of the UART.
Table 162. Status Register (DBGSTAT)
Bit
7
6
5
4
3
2
1
0
Field
RESET
R/W
RDRF
0
RXOV
0
RXFE
0
RXBRK
0
TDRE
1
TXCOL
0
RXBUSY TXBUSY
0
0
R/W1C
R/W1C
R/W1C
R/W1C
R/W1S
R/W1C
R
R
ADDR
FF_E085
Bit
Description
7
RDRF
Receive Data Register Full
This bit reflects the status of the Receive Data Register. When data is written to the Receive
Data Register, or data is transferred from the shift register to the Receive Data Register, this bit
is set to 1. When the Receive Data Register is read, this bit is cleared to zero. This bit is also
cleared to zero by writing a one to this bit.
0 = Receive Data Register is empty.
1 = Receive Data Register is full.
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Bit
Description (Continued)
6
RXOV
Receive Overrun
This bit is set when a Receive Overrun occurs. A Receive Overrun occurs when there is data in
the Receive Data Register and another byte is written to this register.
0 = Receive Overrun has not occurred
1 = Receive Overrun has occurred.
5
RXFE
Receive Framing Error
This bit is set when a Receive Framing error has been detected. This bit is cleared by writing a
one to this bit.
0 = No Framing Error detected.
1 = Receive Framing Error detected.
4
Receive Break Detect
RXBRK This bit is set when a Break condition has been detected. This occurs when 10 or more bits
received are Low. This bit is cleared by writing a one to this bit.
0 = No Break detected.
1 = Break detected.
3
TDRE
Transmit Data Register Empty
This bit reflects the status of the Transmit Data Register. When the Transmit Data Register is
written, this bit is cleared to zero. When data from the Transmit Data Register is read or trans-
ferred to the Transmit Shift Register, this bit is set to 1. This bit is written to one to abort the
transmission of data being held in the Transmit Data Register.
0 = Transmit Data Register is full.
1 = Transmit Data Register is empty.
2
Transmit Collision
TXCOL This bit is set when a Transmit Collision occurs. This bit is cleared by writing a one to this bit.
0 = No collision has been detected.
1 = Transmit Collision has been detected.
1
Receiver Busy
RXBUSY This bit is set when the receiver is receiving the data. Multi-master systems uses this bit to
ensure the line is idle before sending the data.
0 = Receiver is idle.
1 = Receiver is receiving data.
0
Transmitter Busy
TXBUSY This bit is set when the transmitter is sending the data. This bit is used to determine when to
turn off a transceiver for RS-485 applications.
0 = Transmitter is idle.
1 = Transmitter is sending the data.
Debug Control Register
The Debug Debug Control Register (DBGCTL) sets the mode of the serial interface.
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Table 163. Debug Control Register (DBGCTL)
Bit
7
6
5
4
3
2
1
0
Field
OCD-
LOCK
OCDEN
Reserved
CRCEN UARTEN ABCHAR ABSRCH
RESET
R/W
1
1
00
R
1
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E086
Bit
Description
7
On-Chip Debug Lock
OCDLOCK This bit locks the Debug Control Register so it cannot be written by the CPU. This bit is auto-
matically set if the DBGUART option bit is in its default erased state (one).
0 = Debug Control Register unlocked.
1 = Debug Control Register locked.
6
On-Chip Debug Enable
OCDEN
This bit is set when the OCD is enabled. When this bit is set, received data is interpreted as
debug command. To use the DBG pin as a UART or GPIO pin, this bit must be cleared to
zero by software. This bit cannot be written by the CPU if OCDLOCK is set.
0 = OCD is disabled.
1 = OCD is enabled.
[5:4]
Reserved
These bits are reserved.
3
CRC Enable
CRCEN
If this bit is set, a CRC is appended to the end of each debug command. Clearing this bit will
disable transmission of the CRC.
0 = CRC disabled.
1 = CRC enabled.
2
UART Enable
UARTEN
This bit is used to enable or disable the UART. This bit is ignored when OCDEN is set.
0 = UART disabled.
1 = UART enabled.
1
Auto-Baud Character
ABCHAR
This bit selects the character used during auto-baud detection. This bit cannot be written by
the CPU if OCDEN is set.
0 = Auto-baud character to be measured is 80h.
1 = Auto-baud character to be measured is 0Dh.
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Product Specification
289
Bit
Description (Continued)
0
Auto-Baud Search Mode
ABSRCH
This bit enables auto-baud search mode. When this bit is set, the next character received is
measured to set the Baud Rate Reload Register. This bit clears itself to zero after the reload
register has been written. This bit is automatically set when OCDEN is set if a serial commu-
nication error occurs. This bit cannot be written by the CPU if the OCDEN bit is set.
0 = Auto-baud search disabled.
1 = Auto-baud search enabled.
OCD Control Register
The OCD Control Register (OCDCTL) controls the state of the CPU. This register puts
the CPU in DEBUG HALT Mode, enable breakpoints, or single step an instruction.
Table 164. OCD Control Register (OCDCTL)
Bit
7
6
5
4
3
2
1
0
Field
DBGHALT BRKHALT BRKEN
DBG-
STOP
Reserved
STEP
RESET
R/W
0
0
0
0
000
R
0
R/W
R/W
R/W
R/W
R/W
Bit
Description
7
Debug Halt
DBGHALT Setting this bit to one causes the device to enter DEBUG HALT Mode. When in DEBUG
HALT Mode, the CPU stops fetching instructions. Clearing this bit causes the CPU to start
running again. This bit is automatically set to 1 when a breakpoint occurs if the BRKHALT bit
is set.
0 = The device is running.
1 = The device is in DEBUG HALT Mode.
6
Breakpoint Halt
BRKHALT This bit determines what action the OCD takes when a Breakpoint occurs. If this bit is set to
1, then the DBGHALT bit is automatically set to 1 when a breakpoint occurs. If BRKHALT is
zero, then the CPU will loop on the breakpoint.
0 = CPU loops on current instruction when breakpoint occurs.
1 = A Breakpoint sets DBGHALT to one.
5
Enable Breakpoints
BRKEN
This bit controls the behavior of the BRK instruction and the hardware breakpoint. By
default, these generate an illegal instruction system trap. If this bit is set to 1, these events
generate a Breakpoint instead of a system trap. The resulting action depends upon the
BRKHALT bit.
0 = BRK instruction and hardware breakpoint generates system trap.
1 = BRK instruction and hardware breakpoint generates a breakpoint.
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Control Register Definitions
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Product Specification
290
Bit
Description (Continued)
4
Debug Stop Mode
DBGSTOP This bit controls the system clock behavior in STOP Mode. When set to 1, the system clock
will continue to operate in STOP Mode.
0 = Stop mode debug disabled; system clock stops in STOP Mode.
1 = Stop mode debug enabled; system clock runs in STOP Mode.
3:1
Reserved
This bit is reserved and must be written to zero.
0
STEP
Single Step An Instruction
This bit is used to single step an instruction when in DEBUG HALT Mode. This bit is auto-
matically cleared after an instruction is executed.
0 = Idle
1 = Single Step an Instruction.
OCD Status Register
The OCD Status Register (OCDSTAT) reports status information about the current state of
the system.
Table 165. OCD Status Register (OCDSTAT)
Bit
7
6
5
HALT
0
4
STOP
0
3
RPEN
0
2
1
TDRF
0
0
RDRE
1
Field
RESET
R/W
DBGHALT DBGBRK
Reserved
0
0
0
R
R
R
R
R
R
R
R
Bit
Description
7
Debug Halt Mode
DBGHALT This status bit indicates if the CPU is stopped and in DEBUG HALT Mode.
0 = Device is running.
1 = CPU is in DEBUG HALT Mode.
6
Debug Break
DBGBRK
This bit indicates if the CPU has reached a BRK instruction. This bit is set when a BRK
instruction is executed. It is cleared when the DBGHALT control bit is written to zero.
5
HALT
HALT Mode
0 = The device is not in HALT Mode.
1 = The device is in HALT Mode.
4
STOP
STOP Mode
0 = The device is not in Stop mode.
1 = The device is in Stop mode.
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Control Register Definitions
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Product Specification
291
Bit
Description (Continued)
3
RPEN
Read Protect Enabled
0 = Memory Read Protect is disabled.
1 = Memory Read Protect is enabled.
2
Reserved
These bits are reserved and always read back zero.
1
TDRF
Transmit Data Register Full
This bit is set when the Transmit Data Register is full.
0 = Transmit Data Register is empty
1 = Transmit Data Register is full
0
RDRE
Receive Data Register Empty
This bit indicates when the Receive Data Register is empty.
0 = Receive Data Register is full.
1 = Receive Data Register is empty.
Hardware Breakpoint Registers
The Hardware Breakpoint Register (HWBPn) is used to set hardware breakpoints.
Table 166. Hardware Breakpoint Register (HWBPn)
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Field
RESET
R/W
PC ST RD WR
MASK
ADDR[23:16]
00h
0
0
0
0
0000
R/W
R/W R/W R/W R/W
R/W
ADDR
FF_E090-FF_E091,FF_E094-FF_E095,FF_E098-FF_E099,FF_E09C-FF_E09D
14 13 12 11 10
Bit
15
9
8
7
6
5
4
3
2
1
0
Field
RESET
R/W
ADDR[15:0]
0000h
R/W
ADDR
FF_E092-FF_E093,FF_E096-FF_E097,FF_E09A-FF_E09B,FF_E09E-FF_E09F
Bit
Description
31
PC
Break on Program Counter Match
This bit will enable the hardware breakpoint.
0 = Break on program counter match disabled.
1 = Break on program counter match enabled.
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Control Register Definitions
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Product Specification
292
Bit
Description (Continued)
30
ST
Status
This bit is set when a hardware breakpoint occurs.
0 = No breakpoint occurred because this bit was last written to zero.
1 = Breakpoint has occurred or this bit written to one.
29
RD
Break On Data Read
This bit will enable the hardware watchpoint for data reads.
0 = Hardware watchpoint on read disabled.
1 = Hardware Watchpoint on read enabled.
28
WR
Break On Data Write
This bit will enable the hardware watchpoint for data writes.
0 = Hardware watchpoint on data write disabled.
1 = Hardware watchpoint on data write enabled.
[27:24] Watchpoint Address Mask
MASK
The MASK field specifies the number of bits in ADDR to ignore when comparing against
addresses for read and write watchpoints. The mask is set to ignore 0 to 15 of the lower
address bits to allow the watchpoint to monitor a memory block up to 32K in size.
[23:0]
ADDR
Breakpoint Address
The address to match when generating a breakpoint.
Trace Control Register
The Trace Control Register (TRACECTL) is used to enable the Trace operation. It also
selects the size of the trace buffer.
Table 167. Trace Control Register (TRACECTL)
Bit
7
TRACEEN
0
6
5
4
3
2
1
TRACESEL
000
0
Field
RESET
R/W
Reserved
0
0
0
0
R/W
R
R
R
R
R/W
ADDR
FF_E013
Bit
Description
7
Trace Enable
TRACEEN 0 = Trace is disabled.
1 = Traces is enabled
[6:3]
Reserved
These bits are reserved.
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Control Register Definitions
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Product Specification
293
Bit
Description (Continued)
[2:0]
Trace Size Select
TRACESEL 000–128 Bytes (16 Events)
001–256 Bytes (32 Events)
010–512 Bytes (64 Events)
011–1024 Bytes (128 Events)
100–2048 Bytes (256 Events)
101–4096 Bytes (512 Events)
110–8192 Bytes (1024 Events)
111–16384 Bytes (2048 Events)
Trace Address Register
The Trace Address (TRACEADDR) Register points to the next Data trace location.
Table 168. Trace Address (TRACEADDR)
Bit
31
15
30
14
29
13
28
27
26
25
24
23
22
21
20
19
18
17
16
Field
RESET
R/W
Reserved
TRACEADDR[23:16]
00h
R
XXH
R/W
ADDR
FF_E014
Bit
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
RESET
R/W
TRACEADDR[15:2]
XXXXH
00
00
R
R/W
ADDR
FF_E016
Bit
Description
[31:24]
Reserved
These bits are reserved.
[23:2]
Trace Address
TRACEADDR These bits form a 24 bit address used by the trace logic to store the next PC value to
memory.
[1:0]
Reserved
These bits are reserved.
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Product Specification
294
On-Chip Oscillator
The products in the Z16FMC Series feature an on-chip oscillator for use with external
crystals with frequencies from 32kHz to 20MHz. In addition, the oscillator supports exter-
nal RC networks with oscillation frequencies up to 4MHz or ceramic resonators with
oscillation frequencies up to 20MHz. This oscillator generates the primary system clock
for the internal CPU and the majority of the on-chip peripherals. Alternatively, the XIN
input pin also accept a CMOS-level clock input signal (32kHz to 20MHz). If an external
clock generator is used, the XOUT pin must be left unconnected.
When configured for use with crystal oscillators or external clock drivers, the frequency of
the signal on the XIN input pin determines the frequency of the system clock (i.e., no inter-
nal clock divider). In RC operation, the system clock is driven by a clock divider (divide
by 2) to ensure 50% duty cycle.
Operating Modes
Z16FMC Series products support four different oscillator modes:
•
•
•
On-chip oscillator configured for use with external RC networks (<4MHz)
Minimum power for use with very low frequency crystals (32kHz to 1.0MHz)
Medium power for use with medium frequency crystals or ceramic resonators (0.5MHz
to 10.0MHz)
•
Maximum power for use with high frequency crystals or ceramic resonators (8.0MHz
to 20.0MHz)
The oscillator mode is selected via user-programmable option bits. For more information,
see the Option Bit chapter on page 260.
Crystal Oscillator Operation
Figure 58 displays a recommended configuration for connection with an external
fundamental mode, parallel-resonant crystal operating at 20MHz. Recommended 20MHz
crystal specifications are provided in Table 169. Resistor R1 is optional and limits total
power dissipation by the crystal. The printed circuit board layout must add no more than 4
pF of stray capacitance to either the XIN or XOUT pins. If oscillation does not occur, it
reduce the values of capacitors C1 and C2 to decrease loading.
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On-Chip Oscillator
Z16FMC Series Motor Control MCUs
Product Specification
295
On-Chip Oscillator
X
X
OUT
IN
R1 = 220
Crystal
C1 = 22 pF
C2 = 22 pF
Figure 58. Recommended 20MHz Crystal Oscillator Configuration
Table 169. Recommended Crystal Oscillator Specifications (20 MHz Operation)
Parameter
Frequency
Resonance
Mode
Value
Units
Comments
20
MHz
Parallel
Fundamental
Series Resistance (R )
25
20
7
W
pF
Maximum
Maximum
Maximum
Maximum
S
Load Capacitance (C )
L
Shunt Capacitance (C )
pF
0
Drive Level
1
mW
Oscillator Operation with an External RC Network
Figure 59 displays a recommended configuration for connection with an external
resistor-capacitor (RC) network.
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Z16FMC Series Motor Control MCUs
Product Specification
296
V
DD
R
C
X
IN
Figure 59. Connecting the On-Chip Oscillator to an External RC Network
An external resistance value of 15kΩ is recommended for oscillator operation with an
external RC network. The minimum resistance value to ensure operation is 10kΩ The
typical oscillator frequency is estimated from the values of the resistor (R in kΩ) and
capacitor (C in pF) elements using the following equation:
6
110
--------------------------------
Oscillator Frequency (kHz) =
1.5 R C
Figure 60 displays the typical (3.3 V and 25°C) oscillator frequency as a function of the
capacitor (C in pF) employed in the RC network assuming a 15kΩ external resistor. For
very small values of C, the parasitic capacitance of the oscillator XIN pin and the printed
circuit board must be included in the estimation of the oscillator frequency.
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Z16FMC Series Motor Control MCUs
Product Specification
297
1000
900
800
700
600
500
400
300
200
100
0
0
100
200
300
400
500
600
700
800
900
1000
C (pF)
Figure 60. Typical RC Oscillator Frequency as a Function of External Capacitance
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Z16FMC Series Motor Control MCUs
Product Specification
298
Internal Precision Oscillator
The Internal Precision Oscillator (IPO) is designed for use without external components.
Nominal untrimmed accuracy is approximately ±30%. You can manually trim the
oscillator to achieve a ±4% frequency accuracy over the operating temperature and supply
voltage range of the device.
The IPO features include:
•
•
•
•
•
On-chip RC oscillator which does not require external components
Nominal ±30% accuracy without trim or manually trim the oscillator to achieve a ± 4%
Typical output frequency of 5.5296MHz
Trimming possible through Flash option bits with user override
Eliminates crystals or ceramic resonators in applications where high timing accuracy is
not required
Operation
The internal oscillator is an RC relaxation oscillator and has its sensitivity to power supply
variation minimized. By using ratio tracking thresholds, the effect of power supply voltage
is cancelled out. The dominant source of oscillator error is the absolute variance of chip
level fabricated components, such as capacitors. An 8-bit trimming register, incorporated
into the design, allows compensation of absolute variation of oscillator frequency. After it
is calibrated, the oscillator frequency is relatively stable and does not require subsequent
calibration.
By default, the oscillator is configured through the Flash Option bits. However, the user
code overrides these trim values as described in the Option Bit Configuration By Reset
chapter on page 260.
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Internal Precision Oscillator
Z16FMC Series Motor Control MCUs
Product Specification
299
Oscillator Control
Z16FMC Series devices use three possible user-selectable clocking schemes:
•
•
•
Trimmable internal precision oscillator
On-chip oscillator using off-chip crystal/resonator or external clock driver
On-chip low precision Watchdog Timer oscillator
In addition, Z16FMC devices contain clock failure detection and recovery circuitry, allow-
ing continued operation despite a failure of the primary oscillator.
The on-chip system clock frequency is reduced through a clock divider allowing reduced
dynamic power dissipation. Flash memory is powered down during portions of the clock
period when running slower than 10MHz.
Operation
This section explains the logic used to select the system clock, divide down the system
clock and handle oscillator failures. A description of the specific operation of each oscilla-
tor is outlined elsewhere in this document. See the Watchdog Timer chapter on page 109,
the Internal Precision Oscillator chapter on page 298, and the On-Chip Oscillator chapter
on page 294.
System Clock Selection
The oscillator control block selects from the available clocks. Table 170 details each clock
source and its usage.
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300
Table 170. Oscillator Configuration and Selection
Clock Source
Characteristics
Required Setup
Internal Precision
Oscillator
• 5.5MHz
• High precision possible when
trimmed
• The reset default.
• No external components required
External Crystal/
Resonator/
External Clock Drive
• 0 to 20MHz
• Very high accuracy (dependent on
• Configure Option Bit for correct
external oscillator mode
crystal/resonator or external source) • Unlock and write Oscillator Control
• Requires external components
Register (OSCCTL) to enable exter-
nal oscillator
• Wait for required stabilization time
• Unlock and write Oscillator Control
Register (OSCCTL) to select exter-
nal oscillator
Internal Watchdog
Timer Oscillator
• 10kHz nominal
• Low accuracy
• No external components required
• Low power consumption
• Unlock and write Oscillator Control
Register (OSCCTL) to enable and
select Internal WDT oscillator
Unintentional access to the Oscillator Control Register (OSCCTL) stops the chip by
switching to a nonfunctioning oscillator. Accidental alteration of the OSCCTL Register is
prevented by a locking/unlocking scheme. To write the register, unlock it by making two
writes to the OSCCTL Register with the values E7hfollowed by 18h. A third write to the
OSCCTL Register then changes the value of the register and returns the register to a
locked state. Any other sequence of Oscillator Control Register writes exhibits no effect.
The values written to unlock the register must be ordered correctly, but need not be con-
secutive. It is possible to access other registers within the locking/unlocking operation.
Clock Selection Following System Reset
The internal precision oscillator is selected following a System Reset. Startup code after
the System Reset changes the system clock source by unlocking and configuring the OSC-
CTL Register. If the LPOPT bit in the Program Memory Address 0003h section on page
263 is zero, Flash Low Power mode is enabled during reset. When Flash Low Power mode
is enabled during reset, the FLPEN bit in the Oscillator Control Register (OSCCTL) will
be set and the DIV field of the OSCDIV Register will be set to 08h.
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Operation
Z16FMC Series Motor Control MCUs
Product Specification
301
Clock Failure Detection and Recovery
This section discusses the potential failure aspects of the Z16FMC Series MCU’s primary
and watchdog timer oscillators, plus clock switchovers and system exceptions that occur
upon failure events.
Primary Oscillator Failure
The Z16FMC device generates a System Exception when a failure of the primary
oscillator occurs if the POFEN bit is set in the OSCCTL Register. To maintain system
function in this situation, the clock failure recovery circuitry automatically forces the
Watchdog Timer oscillator to drive the system clock. Although this oscillator runs at a
much lower frequency than the original system clock, the CPU continues to operate,
allowing execution of a clock failure vector and software routines that either remedy the
oscillator failure or issue a failure alert. This automatic switch-over is not available if the
WDT is the primary oscillator.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1kHz ±50%. For operating frequencies below 2kHz, do not enable the clock
failure circuitry (POFEN must be deserted in the OSCCTL Register).
Watchdog Timer Failure
In the event of a Watchdog Timer oscillator failure, a System Exception is used if the
WDFEN bit of the OSCCTL Register is set. This event does not trigger an attendant clock
switch-over, but alerts the CPU of the failure. After a WDT failure, it is no longer possible
to detect a primary oscillator failure.
The Watchdog Timer oscillator failure detection circuit counts system clocks while
looking for a WDT clock. The logic counts 8000 system clock cycles before determining
that a failure occurred. The system clock rate determines the speed at which the WDT
failure is detected. A very slow system clock results in very slow detection times.
If the WDT is the primary oscillator or if the Watchdog Timer oscillator is disabled,
deassert the WDFEN bit of the OSCCTL Register.
Oscillator Control Register Definitions
This section presents tabled bit descriptions for the oscillator control and divide registers.
Oscillator Control Register
The Oscillator Control Register (OSCCTL) enables or disables the various oscillator
circuits, enables/disables the failure detection/recovery circuitry, actively powers down
the flash and selects the primary oscillator, which becomes the system clock.
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302
The Oscillator Control Register must be unlocked before writing. Writing the two-step
sequence E7hfollowed by 18hto the Oscillator Control Register address unlocks it. The
register locks after completion of a register write to the OSCCTL.
Table 171. Oscillator Control Register (OSCCTL)
1
Bit
7
INTEN
1
6
XTLEN
0
5
WDTEN
1
4
POFEN
0
3
WDFEN
0
2
FLPEN
0*
0
Field
RESET
R/W
SCKSEL
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
FF_E0A0h
Note: *The reset value is 1 if the option bit LPOPT is 0.
Bit
Description
[7]
INTEN
Internal Precision Oscillator Enable
0 = Internal precision oscillator is disabled.
1 = Internal precision oscillator is enabled.
[6]
XTLEN
Crystal Oscillator Enable
0 = Crystal oscillator is disabled.
1 = Crystal oscillator is enabled.
[5]
WDT Oscillator Enable
WDTEN 0 = WDT oscillator is disabled.
1 = WDT oscillator is enabled.
[4]
Primary Oscillator Failure Detection Enable
POFEN 0 = Failure detection and recovery of primary oscillator is disabled. This bit is cleared automat-
ically if a primary oscillator failure is detected.
1 = Failure detection and recovery of primary oscillator is enabled.
[3]
WDT Oscillator Failure Detection Enable
WDFEN 0 = Failure detection of WDT oscillator is disabled.This bit is cleared automatically if a WDT
oscillator failure is detected.
1 = Failure detection of WDT oscillator is enabled.
[2]
FLPEN
Flash Low Power Mode Enable
0 = Flash Low Power Mode is disabled.
1 = Flash Low Power Mode is enabled. The Flash will be powered down during idle periods of
the clock and powered up during Flash reads. This bit must only be set if the frequency of
the primary oscillator source is 8MHz or lower. The reset value of this bit is controlled by
the LPOPT option bit during reset.
[1:0]
System Clock Oscillator Select
SCKSEL 00 = Internal precision oscillator functions as system clock at 5.6MHz.
01 = Crystal oscillator or external clock driver functions as system clock.
10 = Reserved.
11 = Watchdog Timer oscillator functions as system clock.
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Oscillator Control Register Definitions
Z16FMC Series Motor Control MCUs
Product Specification
303
Oscillator Divide Register
The Oscillator Divide Register (OSCDIV) provides the value to divide the system clock
by. The Oscillator Divide Register must be unlocked before writing. Writing the two-step
sequence E7hfollowed by 18hto the Oscillator Control Register address unlocks it. The
register locks after completion of a register write to the OSCDIV.
Table 172. Oscillator Divide Register (OSCDIV)
1
Bit
7
6
5
4
3
2
0
Field
RESET
R/W
DIV
00h*
R/W
ADDR
FF_E0A1h
Note: *The reset value is 08h if the option bit LPOPT is 0.
Bit
Description
[7:0]
DIV
Oscillator Divide
00h to FFh = divider is disabled, all other entries are the divide value for scaling the system
clock.
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Oscillator Control Register Definitions
Z16FMC Series Motor Control MCUs
Product Specification
304
Electrical Characteristics
All data in this chapter is prequalification and precharacterization and is subject to change.
Absolute Maximum Ratings
Stress greater than those listed in Table 173 may cause permanent damage to the device.
These ratings are stress ratings only. Operation of the device at any condition outside those
indicated in the operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods affects device reliability. For
improved reliability, unused inputs must be tied to one of the supply voltages (VDD or
VSS).
Table 173. Absolute Maximum Ratings
Parameter
Minimum Maximum
Units
Notes
Ambient temperature under bias
Storage temperature
–40
–65
–0.3
+105
+150
+5.5
C
C
V
Voltage on any pin with respect to V
<Link
Table>3
04
SS
Voltage on V pin with respect to V
–0.3
+3.6
V
<Link
Table>3
04
DD
SS
Maximum current on input and/or inactive output pin
Maximum output current from active output pin
–5
+5
µA
–25
+25
mA
64-Pin LQFP Maximum Ratings at –40°C to 70°C
Total power dissipation
1.0
W
Maximum current into V or out of V
275
mA
DD
SS
64-Pin LQFP Maximum Ratings at
7
0°C to 105°C
Total power dissipation
540
150
W
Maximum current into V or out of V
mA
DD
SS
Notes:
1. This voltage applies to the 5V-tolerant Port A, C, D, E, F and G pins (except pins PC0 and PC1).
2. This voltage applies to V , AV , pins supporting analog input (Ports B and H), Pins PC0 and PC1, RESET,
DD
DD
DBG and XIN pins which are non 5V-tolerant pins.
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Electrical Characteristics
Z16FMC Series Motor Control MCUs
Product Specification
305
DC Characteristics
Table 174 lists the DC characteristics of the Z16FMC Series products. All voltages are ref-
erenced to VSS, the primary system ground. Any parameter value in the typical column is
from characterization at 3.3V and 0°C. These values are provided for design guidance
only and are not tested in production.
Table 174. DC Characteristics
T = –40°C to 105°C
A
Symbol Parameter
Min
Typ
Max
Units Conditions
V
V
Supply Voltage
2.7
–
3.6
V
DD
IL1
Low Level Input Voltage
–0.3
0.3*V
V
For all input pins except
RESET, DBG, X
DD
IN
V
V
Low Level Input Voltage
High Level Input Voltage
–0.3
–
–
0.2*V
5.5
V
V
For RESET, DBG and X
IN
IL2
DD
0.7*V
Port A, C, D, E, F and G
IH1
DD
1
pins except pins PC0
and PC1
V
V
V
High Level Input Voltage
High Level Input Voltage
0.7*V
0.8*V
–
–
–
–
V
V
+0.3
+0.3
V
V
V
Port B, H and pins PC0
and PC1
IH2
IH3
OL1
DD
DD
DD
RESET, DBG and X
pins
DD
IN
Low Level Output Voltage
Standard Drive
0.4
I
= 2 mA; V = 3.0V
OL DD
High Output Drive dis-
abled
V
V
High Level Output Voltage
Standard Drive
2.4
–
–
–
–
V
V
I
= –2 mA; V = 3.0V
OH DD
OH1
OL2
High Output Drive dis-
abled
Low Level Output Voltage
High Drive
0.6
I
= 20 mA; V = 3.3V
OL DD
High Output Drive
enabled
T = –40°C to +70°C
A
V
V
High Level Output Voltage
High Drive
2.4
–
–
–
–
V
V
IOH = –20 mA; V =3.3V
High Output Drive
enabled;
TA = –40°C to +70°C
OH2
OL3
DD
Low Level Output Voltage
High Drive
0.6
I
= 15 mA; V = 3.3V
OL DD
High Output Drive
enabled;
TA = +70°C to +105°C
Note: This condition excludes all pins that have on-chip pull-ups enabled, when driven Low.
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DC Characteristics
Z16FMC Series Motor Control MCUs
Product Specification
306
Table 174. DC Characteristics (Continued)
T = –40°C to 105°C
A
Symbol Parameter
Min
Typ
Max
Units Conditions
V
High Level Output Voltage
2.4
–
–
V
I
= 15 mA; V = 3.3V
OH DD
OH3
High Drive
High Output Drive
enabled;
TA = +70°C to +105°C
I
Input Leakage Current
–5
v
+5
mA
V
V
= 3.6V;
DD
IL
1
= V or V
IN
DD
SS
I
Tri-State Leakage Current
–5
–
–
+5
–
mA
pF
V
= 3.6V
DD
TL
2
C
GPIO Port Pad Capaci-
tance
8.0
PAD
2
C
C
X
X
Pad Capacitance
–
–
8.0
–
–
pF
pF
XIN
IN
2
Pad Capacitance
9.5
XOUT
OUT
I
I
Weak Pull-up Current
30
100
600
350
mA
mA
V
V
= 2.7 V to 3.6V
= 3.0V; 25°C
PU
DD
DD
Supply Current in STOP
Mode with VBO enabled
CCS1
CCS2
CCS3
I
I
Supply Current in STOP
Mode with VBO disabled
2
1
mA
mA
V
V
= 3.0V; 25°C
= 3.0V; 25°C
DD
DD
Supply Current in STOP
Mode with VBO disabled
and WDT disabled
I
Active I at 20MHz
–
–
18
4
35
6
mA Typ: V = 3.0V/30°C
DD
CCA
CCH
DD
Max: V = 3.6 V/105°C
DD
Peripherals enabled, no
loads
I
I
in HALT Mode at
mA Typ: V = 3.0V/30°C
DD
DD
20MHz
Max: V = 3.6 V/105°C
DD
Peripherals off, no loads
Note: This condition excludes all pins that have on-chip pull-ups enabled, when driven Low.
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DC Characteristics
Z16FMC Series Motor Control MCUs
Product Specification
307
Figure 61 displays the typical current consumption while operating at 3.3 V at 30ºC vs. the
system clock frequency.
Active Idd vs CLK Freq at 30 ºC
35
30
25
20
15
10
5
0
0
5
10
15
20
25
CLK Freq (MHz)
Vdd=2.6V
Vdd=3.0V
Vdd=3.3V
Vdd=3.7V
Figure 61. Typical I Versus System Clock Frequency
DD
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DC Characteristics
Z16FMC Series Motor Control MCUs
Product Specification
308
Figure 62 displays typical current consumption while operating at 3.3 V at 30ºC in HALT
Mode vs. the system clock frequency.
Halt Idd vs CLK Freq at 30 ºC
6
5
4
3
2
1
0
0
5
10
15
20
25
CLK Freq (MHz)
Vdd=2.6V
Vdd=3.0V
Vdd=3.3V
Vdd=3.7V
Figure 62. Typical HALT Mode I Versus System Clock Frequency
DD
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DC Characteristics
Z16FMC Series Motor Control MCUs
Product Specification
309
Figure 63 displays the STOP Mode current consumption vs. VDD at ambient temperature
with VBO and WDT disabled (ICCS2).
Stop Idd vs Vdd at Temperature
60
50
40
30
20
10
0
2.5
3
3.5
4
Vdd (V)
-40C
0C
30C
70C
105C
Figure 63. Stop Mode Current Versus V
DD
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Z16FMC Series Motor Control MCUs
Product Specification
310
On-Chip Peripheral AC and DC Electrical Characteristics
Table 175 lists the POR and VBO electrical characteristics and timing.
Table 175. POR and VBO Electrical Characteristics and Timing
T = –40°C to 105°C
A
1
Symbol Parameter
Min
Typ
Max
Units Conditions
V
Power-on reset voltage
threshold
2.20
2.45
2.70
V
V
= V
POR
DD
POR
V
Voltage Brown-Out reset
voltage threshold
2.15
2.40
50
2.65
V
V
= V
VBO
DD
VBO
V
–V
100
–
mV
V
POR
VBO
Starting V voltage to
–
–
V
SS
DD
ensure valid POR
T
Power-on reset analog
delay
50
–
—
ms
µs
V
> V
; T
Digital
ANA
DD
POR POR
Reset delay follows T
ANA
T
Power-on reset digital
delay
—
12
10
—
66 IPO cycles
POR
T
T
Voltage Brown-Out pulse
rejection period
—
—
ms
ms
V
Reset
< V
to generate a
VBO
VBO
DD
Time for V to transition
0.10
100
RAMP
DD
from V to V
to
SS
POR
ensure valid Reset
I
Supply current
500
µA
V
= 3.3V
DD
CC
Note:
1. Data in the typical column is from characterization at 3.3 V and 0°C. These values are provided for design guid-
ance only and are not tested in production.
Table 176 lists the Reset and Stop-Mode Recovery pin timing.
.
Table 176. Reset and Stop-Mode Recovery Pin Timing
T = –40°C to 105°C
A
Symbol Parameter
Min
Typ
Max
Units Conditions
T
RESET pin assertion to
initiate a System Reset
4
–
–
T
Not in STOP Mode. T
System Clock period.
=
CLK
RESET
CLK
T
Stop-Mode Recovery pin
Pulse Rejection Period
10
20
40
ns
RESET, DBG and GPIO
pins configured as SMR
sources.
SMR
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P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z16FMC Series Motor Control MCUs
Product Specification
311
Table 177 lists Flash memory electrical characteristics and timing.
Table 177. Flash Memory Electrical Characteristics and Timing
V
= 2.7 to 3.6 V
DD
T = –40°C to 105°C
A
Parameter
Min
Typ
—
Max
Units Notes
Flash Byte Read Time
Flash Byte Program Time
Flash Page Erase Time
Flash Mass Erase Time
50
20
—
40
—
—
2
ns
µs
—
10
—
ms
ms
200
—
—
Writes to Single Address
Before Next Erase
—
Flash Row Program Time
—
—
8
ms Cumulative program time for
single row cannot exceed limit
1
before next erase
Data Retention
Endurance
Note:
100
—
—
—
—
years 25°C
10,000
cycles Program/erase cycles
1. This parameter is only an issue when bypassing the Flash Controller.
Table 178 lists the Watchdog Timer (WDT) electrical characteristics and timing.
Table 178. Watchdog Timer Electrical Characteristics and Timing
T = –40°C to 105°C
A
Symbol Parameter
WDT Oscillator Frequency
Min
Typ
Max
20
Units Conditions
F
5
10
kHz
WDT
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P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z16FMC Series Motor Control MCUs
Product Specification
312
Table 179 lists the Analog-to-Digital Converter (ADC) electrical characteristics and tim-
ing.
Table 179. ADC Electrical Characteristics and Timing
T = –40°C to 105°C
A
Symbol Parameter
Min
Typ
Max
Units Conditions
bits External V
Resolution
10
13
–
–
= 2.0V
REF
Throughput Conversion
CLKs ADC clock cycles
ADCCLK Frequency
20
2
MHz
1
2
2
2
2
DNL
INL
Differential Nonlinearity
–0.99
–3
LSB Typical system config
1
Integral Nonlinearity
3
LSB Typical system config
1
Offset Error
–30
–4.5
1.9
30
4.5
2.1
2.1
mV Typical system config
1
Gain Error
LSB Typical system config
3
On-Chip Voltage Reference
2
2
V
V
Externally supplied Voltage
Reference
1.9
VREF
Analog Input Voltage Range
Analog Input Current
0
V
V
REF
500
nA
Reference Input Current
Analog Input Capacitance
Operating Supply Voltage
2.0
mA Worst case code
15
pF
V
AV
2.7
3.6
DD
Operating Current, AV
9
mA Active conversion @
20MHz
DD
Power Down Current
<1
µA
Notes:
1. These parameters are guaranteed by design and not tested on every part.
2. Typical system configuration is defined as, 20MHz clock with ADC clock divide by 4, 1µs sample hold time,
0.5µs sample settling time.
3. On-chip voltage reference cannot be used if AV
is below 3.0V.
DD
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P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z16FMC Series Motor Control MCUs
Product Specification
313
Table 180 provides electrical characteristics and timing information for the on-chip com-
parator.
Table 180. Comparator Electrical Characteristics
T = –40ºC to 105ºC
A
Symbol
Parameter
Min
Typ
Max
Units Conditions
V
Input offset
–
5
mV
V
V
= 3.3V;
DD
COFF
= V ÷ 2
IN
DD
T
Propagation delay
–
200
40
ns
V
V
mode = 1V
COMM
CPROP
= 100mV
DIFF
I
Input bias current
1
µA
V
B
CMVR
Common-mode voltage
range
–0.3
V
–1
DD
I
Supply current
µA
µs
V
= 3.6V
DD
CC
T
Wake-up time from off
state
5
CINP = 0.9V
CINN= 1.0V
wup
Table 181 provides electrical characteristics and timing information for the on-chip opera-
tional amplifier.
Table 181. Operational Amplifier Electrical Characteristics
T = –40ºC to 105ºC
A
Symbol
Parameter
Min
Typ
Max
15
Units Conditions
V
Input offset
5
mV
V
V
=3.3 V;
OS
DD
CM
= V ÷ 2
DD
TC
Input offset Average Drift
Input bias current
1
µV/C
µA
µA
V
VOS
I
I
TBD
TBD
B
Input offset current
OS
CMVR
Common-Mode Voltage
Range
–0.3
V
–1
DD
V
V
Output Low
Output High
0.1
V
V
I
I
= 100 µA
OL
SINK
V
–1
= 100 µA
SOURCE
OH
DD
CMRR
Common-Mode Rejection
Ratio
70
80
80
dB
0 < V
< 1.4V;
CM
T = 25ºC
A
PSRR
Power Supply Rejection
Ratio
dB
dB
V
= 2.7 V–3.6V;
DD
T = 25ºC
A
A
Voltage Gain
VOL
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P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z16FMC Series Motor Control MCUs
Product Specification
314
Table 181. Operational Amplifier Electrical Characteristics (Continued)
T = –40ºC to 105ºC
A
Symbol
Parameter
Min
Typ
Max
Units Conditions
SR+
Slew Rate while rising
12
V/µs
R
C
A
= 33K;
= 50pF;
= 1,
LOAD
LOAD
VCL
V
= 0.7V to 1.7V
IN
SR-
Slew Rate while falling
16
50
V/µs
R
C
A
= 33K;
= 50pF;
= 1,
= 1.7V to 0.7 V
LOAD
LOAD
VCL
V
IN
GBW
FM
Gain-Bandwidth Product
Phase Margin
5
MHz
degree
mA
I
Supply Current
1
V
= 3.6V;
DD
S
V
= V ÷ 2
OUT
DD
T
Wake-up time from off
state
20
µs
WUP
AC Characteristics
The section provides information about the AC characteristics and timing. All AC timing
information assumes a standard load of 50pF on all outputs. Table 182 lists the AC char-
acteristics and timing attributes of the Z16FMC Series device.
Table 182. AC Characteristics
T = –40°C to
A
105°C
Symbol
Parameter
Min
–
Max
20.0
20.0
Units Conditions
F
System Clock Frequency
MHz
MHz
Read-only from Flash memory
sysclk
0.032768
Program or erasure of Flash
memory
F
Crystal Oscillator Fre-
quency
1.0
20.0
MHz
System clock frequencies
below the crystal oscillator mini-
mum require an external clock
driver
XTAL
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AC Characteristics
Z16FMC Series Motor Control MCUs
Product Specification
315
Table 182. AC Characteristics (Continued)
T = –40°C to
A
105°C
Symbol
Parameter
Min
50
20
20
–
Max
–
Units Conditions
T
T
T
T
T
System Clock Period
System Clock High Time
System Clock Low Time
System Clock Rise Time
System Clock Fall Time
ns
ns
ns
ns
ns
T
T
T
T
T
= 1/F
SYSCLK
XIN
CLK
CLK
CLK
CLK
CLK
30
30
3
= 50ns
= 50ns
= 50ns
= 50ns
XINH
XINL
XINR
XINF
–
3
General Purpose I/O Port Input Data Sample Timing
Figure 64 displays timing of the GPIO port input sampling. The input value on a GPIO
port pin is sampled on the rising edge of the system clock. The port value is then available
to the CPU on the second rising clock edge following the change of the port value.
Table 183 lists the GPIO port input timing.
TCLK
System
Clock
Port Value
Changes to 0
Port Pin
Input Value
Port Input Data
0 Value May Be Read
Register Latch
From Port Input
Data Register
Figure 64. Port Input Sample Timing
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AC Characteristics
Z16FMC Series Motor Control MCUs
Product Specification
316
Table 183. GPIO Port Input Timing
Delay (ns)
Min Max
1µs
Parameter Abbreviation
T
GPIO Port Pin Pulse Width to ensure Stop-Mode Recovery (for GPIO
Port Pins enabled as SMR sources)
SMR
On-Chip Debugger Timing
Table 184 provide timing information for the DBG pin. The DBG pin timing specifica-
tions assume a 4µs maximum rise and fall time.
Table 184. On-Chip Debugger Timing
Delay (ns)
Parameter
Min
Max
DBG
System Clock/4
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AC Characteristics
Z16FMC Series Motor Control MCUs
Product Specification
317
SPI MASTER Mode Timing
Figure 65 and Table 185 provide timing information for SPI MASTER Mode pins. Timing
is shown with the SCK rising edge used to source MOSI output data and the SCK falling
edge used to sample MISO input data. Timing on the SS output pin(s) is controlled by
software.
SCK
T1
MOSI
Output)
Output Data
T2
T3
MISO
Input Data
(Input)
Figure 65. SPI MASTER Mode Timing
Table 185. SPI MASTER Mode Timing
Delay (ns)
Parameter
SPI Master
Abbreviation
Min
Max
T
T
T
SCK Rise to MOSI output Valid Delay
–5
20
0
+5
1
2
3
MISO input to SCK (receive edge) Setup Time
MISO input to SCK (receive edge) Hold Time
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AC Characteristics
Z16FMC Series Motor Control MCUs
Product Specification
318
SPI Slave Mode Timing
Figure 66 and Table 186 provide timing information for the SPI SLAVE Mode pins. Tim-
ing is shown with the SCK rising edge used to source MISO output data and the SCK fall-
ing edge used to sample MOSI input data.
SCK
T1
MISO
(Output)
Output Data
T2
T3
MOSI
Input Data
(Input)
T4
SS
(Input)
Figure 66. SPI Slave Mode Timing
Table 186. SPI Slave Mode Timing
Delay (ns)
Parameter Abbreviation
SPI Slave
Min
Max
T
SCK (transmit edge) to MISO output Valid
Delay
2 * X period
3 * X period + 20ns
1
IN
IN
T
MOSI input to SCK (receive edge) Setup
Time
0
2
T
T
MOSI input to SCK (receive edge) Hold Time
SS input assertion to SCK setup
3 * X period
3
4
IN
1 * X period
IN
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AC Characteristics
Z16FMC Series Motor Control MCUs
Product Specification
319
I2C Timing
Figure 67 and Table 187 provide timing information for I2C pins.
SCL
(Output)
T1
SDA
(Output)
Output Data
T3
T2
Input Data
SDA
(Input)
2
Figure 67. I C Timing
2
Table 187. I C Timing
Delay (ns)
Parameter
Abbreviation
Min
Max
2
I C
T
T
T
SCL Fall to SDA output delay
SCL period/4
1
2
3
SDA Input to SCL rising edge Setup Time 0
SDA Input to SCL falling edge Hold Time
0
UART Timing
Figure 68 and Table 188 provide timing information for UART pins for the case where the
Clear To Send input pin (CTS) is used for flow control. In this example, it is assumed that
the Driver Enable polarity has been configured to be Active Low and is represented here
by DE. The CTS to DE assertion delay (T1) assumes the UART Transmit Data Register
has been loaded with data prior to CTS assertion.
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AC Characteristics
Z16FMC Series Motor Control MCUs
Product Specification
320
CTS
(Input)
T1
DE
(Output)
T2
T3
TXD
(Output)
Stop
Start Bit 0 Bit 1
Bit 7 Parity
End of
Stop Bit(s)
Figure 68. UART Timing with CTS
Table 188. UART Timing with CTS
Delay (ns)
Parameter Abbreviation
Min
Max
T
T
CTS Fall to DE Assertion Delay
2 * X period
2 * X period + 1 Bit period
1
2
IN
IN
DE Assertion to TXD Falling Edge (Start)
Delay
1 Bit period
1 Bit period+1 * X period
IN
T
End of Stop Bit(s) to DE Deassertion
Delay
1 * X period
2 * X period
3
IN
IN
Figure 69 and Table 189 provide timing information for UART pins for cases in which the
Clear To Send input signal (CTS) is not used for flow control. In this example, it is
assumed that the Driver Enable polarity has been configured to be Active Low and is rep-
resented here by DE. DE asserts after the UART Transmit Data Register has been written.
DE remains asserted for multiple characters as long as the Transmit Data Register is writ-
ten with the next character before the current character has completed.
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AC Characteristics
Z16FMC Series Motor Control MCUs
Product Specification
321
DE
(Output)
T1
T2
TXD
(Output)
Stop
Start Bit 0 Bit 1
Bit 7 Parity
End of
Stop Bit(s)
Figure 69. UART Timing without CTS
Table 189. UART Timing without CTS
Delay (ns)
Parameter Abbreviation
Min
Max
T
DE Assertion to TXD Falling Edge (Start)
Delay
End of Stop Bit(s) to DE Deassertion Delay 1 * X period
1 Bit period
1Bit period+1 * X period
1
IN
T
2 * X period
2
IN
IN
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AC Characteristics
Z16FMC Series Motor Control MCUs
Product Specification
322
Packaging
Zilog’s Z16FMC Series is comprised of the Z16FMC28, Z16FMC32 and Z16FMC64
MCUs, which are based on the ZNEO CPU and are available in the 64-pin Low-Profile
Quad Flat Package (LQFP).
Current diagrams for this package are published in Zilog’s Packaging Product Specifica-
tion (PS0072), which is available free for download from the Zilog website.
Ordering Information
Table 190 identifies the basic features and package styles available for each device within
the Z16FMC Series products.
Table 190. Z16FMC Series Part Selection Guide
Part Number
Z16FMC28
Z16FMC64
Z16FMC32
128
64
4
4
2
46
46
46
1
1
1
3
3
3
12
12
12
2
2
2
1
1
1
1
1
1
32
You can order Z16FMC Series devices by providing the part numbers listed in Table 191.
Visit our Zilog Sales Location page to find an interactive map to guide you to your
regional Zilog sales office and to find additional information about Z16FMC Series prod-
ucts.
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Packaging
Z16FMC Series Motor Control MCUs
Product Specification
323
Table 191. Zilog Part Numbers
Part Number
Z16FMC Series MCU
Standard Temperature: 0°C to +70°C
Z16FMC28AG20SG
Z16FMC64AG20SG
Z16FMC32AG20SG
128
64
4
4
4
46
46
46
1
1
1
3
3
3
12
12
12
1
1
1
2
2
2
1
1
1
64-pin LQFP
64-pin LQFP
64-pin LQFP
32
Extended Temperature: –40°C to +105°C
Z16FMC28AG20EG
Z16FMC64AG20EG
Z16FMC32AG20EG
128
64
4
4
4
46
46
46
1
1
1
3
3
3
12
12
12
1
1
1
2
2
2
1
1
1
64-pin LQFP
64-pin LQFP
64-pin LQFP
32
Z16FMC Series MCU Development Tools
Z16FMC28200KITG
Z16FMC Series Motor Control Development Kit
Opto-Isolated USB Smart Cable Accessory Kit
ZUSBOPTSC01ZACG
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P R E L I M I N A R Y
Ordering Information
Z16FMC Series Motor Control MCUs
Product Specification
324
Part Number Suffix Designations
Zilog part numbers consist of a number of components, as indicated in the following
example.
Example. Part number Z16FMC28AG20SG is an 8-bit, 20MHz Flash Motor Controller
with 128KB of Flash memory in a 64-pin LQFP package, operating within a 0ºC to +70ºC
temperature range and built using lead-free solder.
Z16
F
MC 28 AG 20
S
G
Environmental Flow
G = Lead Free
Temperature Range
S = Standard, 0°C to +70°C
Speed
20 = 20MHz
Package
AG = 64-pin LQFP
Memory Size
28 = 128KB
Product Line
MC = Motor Control
Memory Type
F = Flash
Zilog 16-bit MCU
Precharacterization Product
The product represented by this document is newly introduced and Zilog has not com-
pleted full characterization of the product. The document states what Zilog knows about
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the document might be found, either by Zilog or its customers, in the course of further
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PS028706-0813
P R E L I M I N A R Y
Ordering Information
Z16FMC Series Motor Control MCUs
Product Specification
325
Index
non-inverting/inverting input 225
operation 225
control register definition, UART 132
control register, I2C 206
control registers
CPU 14
CPU
control registers 14
CPU and peripheral overview 2
current measurement
architecture 216
Numerics
10-bit ADC 3
A
absolute maximum ratings 304
AC characteristics 314
ADC
block diagram 215
electrical characteristics and timing 312
overview 216
operation 216
Customer Support 331
ADC Channel Register 1 (ADCCTL) 219
ADC Data High Byte Register (ADCDH) 220, 224
ADC Data Low Bit Register (ADCDL) 221, 222,
223, 224
analog block/PWM signal synchronization 218
analog block/PWM signal zynchronization 218
analog signals 9
D
data
width 12
data register, I2C 204
DC characteristics 305
debugger, on-chip 266
device, port availability 42
DMA
analog-to-digital converter
overview 216
architecture
voltage measurements 216
controller 4
B
baud rate generator, UART 129
block diagram 2
bus
width 12
bus width
E
electrical characteristics 304
ADC 312
flash memory and timing 311
GPIO input data sample timing 315
watchdog timer 311
non-volatile memory (internal) 15
RAM (internal) 15
electrical noise 216
external pin reset 37
C
characteristics, electrical 304
clock phase (SPI) 158
comparator
F
flash
controller 3
option bit address space 260
definition 224
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Index
Z16FMC Series Motor Control MCUs
Product Specification
326
option bit configuration - reset 260
program memory address 0000H 260
program memory address 0001H 262, 263
flash memory 250
H
H 47
HALT mode 40
arrangement 251
code protection 252
configurations 250
I
I/O memory 12
precautions 14
I2C 3
control register definitions 255
controller bypass 255
electrical characteristics and timing 311
flash status register 256
mass erase 255
10-bit address read transaction 192
10-bit address transaction 189
10-bit addressed slave data transfer format 189,
197
7-bit address transaction 186, 194
7-bit address, reading a transaction 191
7-bit addressed slave data transfer format 188,
196
operation 252
page erase 254
page select register 258
FPS register 258
FSTAT register 256
7-bit receive data transfer format 192, 198, 199
baud high and low byte registers 208, 209, 212,
213
C status register 205, 209
control register definitions 204
controller 180, 215
controller signals 8
interrupts 183
operation 183
G
general-purpose I/O 42
GPIO 3, 42
alternate functions 43
architecture 42
input data sample timing 315
interrupts 45
Port A IRQ Edge Register 53
Port A IRQ MUX Register 52
Port A IRQ MUX1 Register 52
Port A–H Alternate Function High and Low
registers 48
SDA and SCL signals 183
stop and start conditions 185
I2CBRH register 208, 210, 212, 214
I2CBRL register 208
I2CCTL register 206
port A-H alternate function sub-registers 48
Port A–H Data Direction registers 47
Port A–H Input Data registers 45
Port A–H Output Data registers 46
Port A–H Pull-Up Enable Registers 50
Port A–H Stop-Mode Recovery Source Enable
registers 51
port availability by device 42
Port C IRQ MUX Register 53
port input timing 316
I2CDATA register 205
I2CSTAT register 205, 209
infrared encoder/decoder (IrDA) 149
interrupt controller 4, 54
interrupt assertion types 58
interrupt vectors and priority 57
operation 57
System Exception Status Registers 58
interrupt request 0 register 60
interrupt request 1 register 62
interrupt request 2 register 63
interrupt vector listing 54
interrupts
PS028706-0813
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
327
SPI 167
UART 126
N
noise, electrical 216
non-volatile memory 12, 13
bus width 15
introduction 1
IrDA
architecture 130, 149
block diagram 131, 149
control register definitions 152
operation 131, 149
O
OCD
receiving data 151
architecture 266
transmitting data 150
IRQ0 enable high and low bit registers 64
IRQ1 enable high and low bit registers 66
IRQ2 enable high and low bit registers 67
baud rate limits 270
block diagram 267
commands 277
timing 316
on-chip debugger 4
on-chip debugger (OCD) 266
on-chip debugger signals 10
on-chip oscillator 294
operation 218
L
LIN-UART 113
low power modes 40
current measurement 216
voltage measurement timing diagram 217, 218
operational amplifier
operation 225
overview 224
Operational Description 88, 298, 299
option bits 13
M
master interrupt enable 57
master-in, slave-out and-in 155
memory
bus widths 12
I/O 12
oscillator signals 10
internal 12, 13, 14
map 12
non-volatile 12, 13
RAM 12, 14
random access 12, 14
memory access
quad 16
word 16
memory map 12
MISO 155
MOSI 155
motor control measurements
ADC Control register definitions 219
interrupts 218, 219
overview 216
P
peripheral AC and DC electrical characteristics 310
memory
internal 12
PHASE=0 timing (SPI) 159
PHASE=1 timing (SPI) 160
pin characteristics 11
port availability, device 42
port input timing (GPIO) 316
power supply signals 10
power-on and voltage brown-out electrical charac-
teristics and timing 310
precautions, I/O memory 14
multiprocessor mode, UART 121
PS028706-0813
P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
328
UARTx status 1 (UxSTAT1) 137
UARTx transmit data (UxTXD) 133
watchdog timer control (WDTCTL) 302, 303
watchdog timer reload high byte (WDTH) 112
watchdog timer reload low byte (WDTL) 112
register file address map 17
registers
Q
quad mode
memory access 16
R
RAM 12, 14
ADC channel 1 219
bus width 15
ADC data high byte 220, 224
ADC data low bit 221, 222, 223, 224
reset
random-access memory 12, 14
receive
7-bit data transfer format (I2C) 192, 198, 199
IrDA data 151
and STOP mode characteristics 33
and STOP mode recovery 33
controller 4
receiving UART data-interrupt-driven method 118
receiving UART data-polled method 117
register 173
baud low and high byte (I2C) 208, 209, 212, 213
baud rate high and low byte (SPI) 178
control (SPI) 171
control, I2C 206
data, SPI 170, 171
flash page select (FPS) 258
flash status (FSTAT) 256
GPIO port A-H alternate function sub-registers
48
GPIO port A-H data direction sub-registers 47
I2C baud rate high (I2CBRH) 208, 210, 212, 214
I2C control (I2CCTL) 206
S
SCK 155
SDA and SCL (IrDA) signals 183
serial clock 155
serial peripheral interface (SPI) 153
signal descriptions 8
SIO 4
slave data transfer formats (I2C) 189, 197
slave select 156
SPI
architecture 153
baud rate generator 169
baud rate high and low byte register 178
clock phase 158
configured as slave 166
control register 171
control register definitions 169
data register 170, 171
error detection 166
interrupts 167
mode fault error 166
mode register 173
multi-master operation 163
operation 155
overrun error 166, 167
signals 155
I2C data (I2CDATA) 205
I2C status 205, 209
I2C status (I2CSTAT) 205, 209
I2Cbaud rate low (I2CBRL) 208
mode, SPI 173
SPI baud rate high byte (SPIBRH) 178
SPI baud rate low byte (SPIBRL) 179
SPI control (SPICTL) 171
SPI data (SPIDATA) 170, 171
SPI status (SPISTAT) 175
status, SPI 175
UARTx baud rate high byte (UxBRH) 145
UARTx baud rate low byte (UxBRL) 145
UARTx Control 0 (UxCTL0) 139, 144
UARTx control 1 (UxCTL1) 141, 142, 143
UARTx receive data (UxRXD) 133
UARTx status 0 (UxSTAT0) 134, 135
single master, multiple slave system 164
single master,single slave system 164
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Index
Z16FMC Series Motor Control MCUs
Product Specification
329
status register 175
timing, PHASE = 0 159
timing, PHASE=1 160
SPI controller signals 8
SPI mode (SPIMODE) 173
SPIBRH register 178
SPIBRL register 179
SPICTL register 171
SPIDATA register 170, 171
SPIMODE register 173
SPISTAT register 175
SS, SPI signal 155
high and low byte registers 80, 83, 96, 98
timing diagram, voltage measurement 217
transmit
IrDA data 150
transmitting UART data-polled method 115
U
UART 3
architecture 113
asynchronous data format without/with parity
115
STOP mode 40
baud rate generator 129
STOP mode recovery
sources 38
using a GPIO port pin transition 38
using watchdog timer time-out 38
system 13
baud rates table 147
control register definitions 132
controller signals 9
Data Format for Standard UART Modes 115
interrupts 126
system and core resets 34
system vectors 13
multiprocessor mode 121
receiving data using interrupt-driven method 118
receiving data using the polled method 117
transmitting data using the polled method 115
x baud rate high and low registers 145
x control 0 and control 1 registers 139, 140
x status 0 and status 1 registers 133, 136
UxBRH register 145
T
tiing diagram, voltage measurement 218
timer signals 9
Timers 69
timers 4
UxBRL register 145
architecture 69, 88
UxCTL0 register 139, 144
UxCTL1 register 141, 142, 143
UxRXD register 133
UxSTAT0 register 134, 135
UxSTAT1 register 137
block diagram 70, 89
capture mode 76, 77
capture/compare mode 77
compare mode 78
continuous mode 73
counter mode 73
UxTXD register 133
gated mode 79
one-shot mode 71
operating mode 71
PWM mode 75
V
vectors 13
interrupts 13
reading the timer count values 80
reload high and low byte registers 82, 97
timer control register definitions 80, 96
triggered one-shot mode 72
timers 0-2
system exceptions 13
voltage brownout reset (VBR) 36
voltage measurement timing diagram 217, 218
control registers 84, 85
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P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
330
W
watch-dog timer
approximate time-out delays 298
control register 301, 303
operation 298
reset 37
watchdog timer
approximate time-out delay 110
electrical characteristics and timing 311
interrupt in normal operation 110
interrupt in STOP mode 110
refresh 110
reload unlock sequence 111
reload upper, high and low registers 112
reset in normal operation 111
reset in STOP mode 111
WDTCTL register 302, 303
WDTH register 112
WDTL register 112
word mode
memory access 16
Z
ZNEO
block diagram 2
introduction 1
ZNEO CPU features 2
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P R E L I M I N A R Y
Index
Z16FMC Series Motor Control MCUs
Product Specification
331
Customer Support
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http://support.zilog.com.
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PS028706-0813
P R E L I M I N A R Y
Customer Support
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